70 lines
2.3 KiB
Verilog
70 lines
2.3 KiB
Verilog
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// Copyright (c) 2017 Massachusetts Institute of Technology
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//
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// Permission is hereby granted, free of charge, to any person
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// obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without
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// restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies
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// of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be
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// included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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// This module outputs a 1-bit signal
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// The signal is initially 0 after programming the FPGA
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// XXX: everything should be inited to 0 after programming
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// When a reset arrives, the module starts counting
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// In N cycles after the reset, the signal becomes 1
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// This signal can be used as a guard for sync fifo operations
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module reset_guard(
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input CLK,
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input RST,
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output IS_READY
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);
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reg ready = 0;
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reg rst_done = 0;
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always@(posedge CLK) begin
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if(RST == `BSV_RESET_VALUE) begin
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ready <= 0;
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rst_done <= 1;
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// synopsys translate_off
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if(!rst_done) begin
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$display("[reset_guard] %t %m reset happen", $time);
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end
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// synopsys translate_on
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end
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else if(rst_done) begin
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ready <= 1;
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// synopsys translate_off
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if(!ready) begin
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$display("[reset_guard] %t %m guard ready", $time);
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end
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// synopsys translate_on
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end
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end
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assign IS_READY = ready;
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endmodule
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