4756 lines
934 KiB
Plaintext
4756 lines
934 KiB
Plaintext
make -C ../../Tests/elf_to_hex
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make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex'
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make[1]: 'elf_to_hex' is up to date.
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make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex'
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../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex
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c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file
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Section .text : addr 80000000 to addr 8000048c; size 0x 48c (= 1164) bytes
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Section .sbss : addr 80001490 to addr 80001498; size 0x 8 (= 8) bytes
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Section .bss : addr 80001498 to addr 80011498; size 0x 10000 (= 65536) bytes
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Section .riscv.attributes: Ignored
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Section .comment : Ignored
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Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols
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Writing symbols to: symbol_table.txt
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No 'exit' label found
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No 'tohost' symbol found
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Section .shstrtab : Ignored
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Section .strtab : Ignored
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Min addr: 80000000 (hex)
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Max addr: 80011497 (hex)
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Writing mem hex to file 'Mem.hex'
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Subtracting 0x80000000 base from addresses
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./exe_HW_sim +v1 +tohost
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Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 2213 to 33554430.
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1: top.soc_top.rl_reset_start_initial ...
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11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000
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SoC address map:
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Boot ROM: 0x1000 .. 0x2000
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Mem0 Controller: 0x80000000 .. 0xc0000000
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UART0: 0xc0000000 .. 0xc0000080
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11: top.soc_top.rl_reset_complete_initial
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================================================================
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Bluespec RISC-V standalone system simulation v1.2
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Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.
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================================================================
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INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0
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12: top.soc_top.method start (tohost 0, fromhost 0)
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100: top.soc_top.rl_step_0, n = 0, do_release
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100: top.soc_top do_release(restartRunning: True, to_host_addr: 0)
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100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0
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101: top.soc_top.rl_ctrl_req
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101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0
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101: top.soc_top do_release(restartRunning: True, to_host_addr: 0)
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000
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[RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000
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instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167
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instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000
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instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x00001018
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After delta: vaddr = 0x00001018
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3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False }
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3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 }
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[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: <V False False False False False False False False True True True True True True True True >, data: TaggedData { tag: , data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, loadTags: False }
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[RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000
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[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000000 > }; TaggedData { tag: False, data: <V 'h0000000080000000 'h0000000000000000 > }
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instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403
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[ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 }
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[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; <V 'h03 'h02 > ; <V 'h02 'h02 > ; <V <V False False True False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h1 ; <V 'h03 'h02 > ; <V 'h00 'h00 >
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instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000316 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000
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[RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000
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[RFile] wr_ 1: r 47 <= 0000000000020000400000001fffff44000000
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instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x020000db iType:Auipcc [doCommitNormalInst [0]] 1155
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instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1155
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[RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000
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instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156
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[RFile] wr_ 0: r 4a <= 0000000020000004000000001fffff44000000
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[RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000
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instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[RFile] wr_ 1: r 4b <= 0000000020000006000000001fffff44000000
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[ALU redirect - 1] 'h1ffff0000000000000000000080000326; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b }
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11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158
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instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1158
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[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; <V 'h07 'h07 > ; <V 'h06 'h05 > ; <V <V False False False False False False True False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False True True False False False False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False True False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False True False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h0 ; <V 'h06 'h06 > ; <V 'h01 'h01 >
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instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x316080e7 iType:Jr [doCommitNormalInst [0]] 1160
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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12640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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12650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ff8
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After delta: vaddr = 0x80000ff8
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12650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffcee }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 4c <= 00000000200003e8000000001fffff44000000
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12660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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12660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ff0
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After delta: vaddr = 0x80000ff0
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12660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000
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12670 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 }
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12670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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12670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000fec
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After delta: vaddr = 0x80000fec
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instret:12 PC:0x1ffff0000000000000000000080000326 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 1267
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calling cycle
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[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000
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12680 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 }
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12680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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instret:13 PC:0x1ffff0000000000000000000080000328 instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 1268
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calling cycle
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[RFile] wr_ 0: r 52 <= 00000000200000cd000000001fffff44000000
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12690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000018 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8328 }
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12690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 }
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instret:14 PC:0x1ffff000000000000000000008000032a instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 1269
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instret:15 PC:0x1ffff000000000000000000008000032c instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 1269
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calling cycle
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[RFile] wr_ 1: r 53 <= 00000000200000cf000000001fffff44000000
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[ALU redirect - 1] 'h1ffff0000000000000000000080000022; 'h0; InstTag { way: 'h1, ptr: 'h09, t: 'h13 }
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12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 }
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12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
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instret:16 PC:0x1ffff000000000000000000008000032e instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1270
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instret:17 PC:0x1ffff0000000000000000000080000330 instr:0xfea42623 iType:St [doCommitNormalInst [1]] 1270
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calling cycle
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[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h09, t: 'h13 } ; 'h0 ; 'h0 ; <V 'h0a 'h0a > ; <V 'h09 'h09 > ; <V <V False False False False False False False False False True False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False True False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h0 ; <V 'h0a 'h0a > ; <V 'h00 'h00 >
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calling cycle
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12720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
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instret:18 PC:0x1ffff0000000000000000000080000334 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1272
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instret:19 PC:0x1ffff0000000000000000000080000338 instr:0xcee080e7 iType:Jr [doCommitNormalInst [1]] 1272
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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13210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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13220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f98
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After delta: vaddr = 0x80000f98
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13220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 54 <= 00000000200003cc000000001fffff44000000
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13230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000033c o: 'h000000008000033c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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13230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f90
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After delta: vaddr = 0x80000f90
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13230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 57 <= 00000000200003e8000000001fffff44000000
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13240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 }
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13240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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13240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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13240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:20 PC:0x1ffff0000000000000000000080000022 instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1324
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000456 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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13250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 }
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13250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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13250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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instret:21 PC:0x1ffff0000000000000000000080000024 instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1325
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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13260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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13260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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instret:22 PC:0x1ffff0000000000000000000080000026 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1326
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instret:23 PC:0x1ffff0000000000000000000080000028 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1326
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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13270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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13270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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13270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:24 PC:0x1ffff000000000000000000008000002a instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1327
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 5d <= 000000002000040e800000001fffff44000000
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13280 : [doRespLdForward] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 59 <= 0000000000000000000000001fffff44000000
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13280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80001490
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After delta: vaddr = 0x80001490
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13280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 5e <= 0000000020000524000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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13290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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13290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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13300 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 }
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13300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8042 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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13300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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13300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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13300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 }
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instret:25 PC:0x1ffff000000000000000000008000002e instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1330
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calling cycle
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[RFile] wr_ 0: r 5a <= 0000000000000001c00000001fffff44000000
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[RFile] wr_ 1: r 62 <= 0000000000004000000000001fffff44000000
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13310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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13310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 }
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13310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
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13310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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calling cycle
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[RFile] wr_ 0: r 63 <= 0000000000004000400000001fffff44000000
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[RFile] wr_ 1: r 5b <= 0000000000000000000000001fffff44000000
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13320 : [doRespLdForward] 'h03; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000
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13320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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instret:26 PC:0x1ffff0000000000000000000080000032 instr:0x0000051d iType:Alu [doCommitNormalInst [0]] 1332
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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13330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001490, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
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13330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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instret:27 PC:0x1ffff0000000000000000000080000034 instr:0x00009961 iType:Alu [doCommitNormalInst [0]] 1333
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000422 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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13340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:28 PC:0x1ffff0000000000000000000080000036 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1334
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instret:29 PC:0x1ffff000000000000000000008000003a instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1334
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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13350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f60
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After delta: vaddr = 0x80000f60
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instret:30 PC:0x1ffff000000000000000000008000003e instr:0x45650513 iType:Alu [doCommitNormalInst [0]] 1335
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 66 <= 40000000000000000000ffff1fffff44000000
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13360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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13360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 68 <= 000000002000041b800000001fffff44000000
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13370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 }
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13370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f38
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After delta: vaddr = 0x80000f38
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13370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 69 <= 0000000020000524000000001fffff44000000
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13380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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13380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80001490
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After delta: vaddr = 0x80001490
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[RFile] wr_ 1: r 6c <= 000000002000041f000000001fffff44000000
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13390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 }
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13390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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13400 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h001 }
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13400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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13400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
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calling cycle
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13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
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13410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1
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14240 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
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calling cycle
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14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
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14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8328 }
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|
[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000018 > } }
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|
14250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h832a }
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14260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a }
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calling cycle
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14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } }, repInfo: , setAuxData: tagged Invalid }
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14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a }
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14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h832a }
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[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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14270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: <V False False False False False False False False False False False False True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8330 }
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14280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 }
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calling cycle
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14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } }, repInfo: , setAuxData: tagged Invalid }
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14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 }
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14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8330 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: <V False False False False False False False False False False False False True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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14290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000033c > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 }
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14300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
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14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
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14310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
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14330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f98, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
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14760 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001490, toState: E, child: , data: tagged Valid CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
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calling cycle
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14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
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14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8042 }
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14770 : [Ld resp] 'h02; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }
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14770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Valid 'h2
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calling cycle
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14780 : [doRespLdMem] 'h02; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 5f <= 0000000000000000000000001fffff44000000
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14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
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14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
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14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
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14780 : [Ld resp] 'h04; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }
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14780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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14790 : [doRespLdMem] 'h04; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Valid St }
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instret:31 PC:0x1ffff0000000000000000000080000042 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1480
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calling cycle
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[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h027 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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15150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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15160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 62 <= 0000000000004000000000001fffff44000000
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15170 : [doRespLdForward] 'h04; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 60 <= 0000000000000000000000001fffff44000000
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15170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000422 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 63 <= 0000000000004000400000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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15180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f60
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After delta: vaddr = 0x80000f60
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 66 <= 40000000000000000000ffff1fffff44000000
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15190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h003 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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instret:32 PC:0x1ffff0000000000000000000080000044 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1519
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000041c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000
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15200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h001 }
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15200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 68 <= 000000002000041b800000001fffff44000000
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15210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f38
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After delta: vaddr = 0x80000f38
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15210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:33 PC:0x1ffff0000000000000000000080000048 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1521
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instret:34 PC:0x1ffff000000000000000000008000004a instr:0x000065c1 iType:Alu [doCommitNormalInst [1]] 1521
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 6c <= 000000002000041f000000001fffff44000000
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[RFile] wr_ 1: r 69 <= 0000000020000524000000001fffff44000000
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15220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80001490
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After delta: vaddr = 0x80001490
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15220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:35 PC:0x1ffff000000000000000000008000004c instr:0x00002585 iType:Alu [doCommitNormalInst [0]] 1522
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instret:36 PC:0x1ffff000000000000000000008000004e instr:0x00b57463 iType:Br [doCommitNormalInst [1]] 1522
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 6d <= 0000000020000526000000001fffff44000000
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15230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 }
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15230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f60
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After delta: vaddr = 0x80000f60
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15230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:37 PC:0x1ffff0000000000000000000080000052 instr:0x0140006f iType:J [doCommitNormalInst [0]] 1523
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instret:38 PC:0x1ffff0000000000000000000080000066 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 1523
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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15240 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 }
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15240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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15240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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15240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000f58
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After delta: vaddr = 0x80000f58
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15240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
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instret:39 PC:0x1ffff000000000000000000008000006a instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1524
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|
instret:40 PC:0x1ffff000000000000000000008000006e instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1524
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 }
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15250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h808a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, data: TaggedData { tag: True, data: <V 'h0000000000000000 'hffff000000000000 > } }
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15250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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|
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
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15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
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|
15250 : [Ld resp] 'h05; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }
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15250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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15250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:41 PC:0x1ffff0000000000000000000080000072 instr:0x42250513 iType:Alu [doCommitNormalInst [0]] 1525
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instret:42 PC:0x1ffff0000000000000000000080000076 instr:0xf8a43c23 iType:St [doCommitNormalInst [1]] 1525
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 }
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15260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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15260 : [doRespLdMem] 'h05; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000
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15260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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15260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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15260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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15270 : [doRespLdForward] 'h06; TaggedData { tag: True, data: <V 'h0000000000000000 'hffff000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000000000000 'hffff000000000000 > } }
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[RFile] wr_ 3: r 70 <= 40000000000000000000ffff1fffff44000000
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15270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e }
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15270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
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15270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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15270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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15280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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15280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f58
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After delta: vaddr = 0x80000f58
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15280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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15280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a }
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instret:43 PC:0x1ffff000000000000000000008000007a instr:0x0000610c iType:Ld [doCommitNormalInst [0]] 1528
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instret:44 PC:0x1ffff000000000000000000008000007c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1528
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f58, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
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[RFile] wr_ 1: r 6e <= 0000000020000526000000001fffff44000000
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15290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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15290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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15290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a }
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15290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7
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15290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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instret:45 PC:0x1ffff0000000000000000000080000080 instr:0x41c50513 iType:Alu [doCommitNormalInst [0]] 1529
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calling cycle
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15300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 }
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15300 : [doRespLdForward] 'h09; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000
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15300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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instret:46 PC:0x1ffff0000000000000000000080000084 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1530
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calling cycle
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[RFile] wr_ 0: r 79 <= 0000000000000002800000001fffff44000000
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15310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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15310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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|
15310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa }
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instret:47 PC:0x1ffff0000000000000000000080000086 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 1531
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|
calling cycle
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[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000
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|
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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|
15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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|
15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa }
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15320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0
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|
calling cycle
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|
[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000
|
|
[ALU redirect - 0] 'h1ffff00000000000000000000800000e2; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }
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|
instret:48 PC:0x1ffff000000000000000000008000008a instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1533
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calling cycle
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|
[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h1 ; <V 'h0e 'h0e > ; <V 'h09 'h08 > ; <V <V False False False False False False False False False True True True True True False False False False False False False False False False False False False False False False False False > <V False False False False False False False False True True True True True True False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h0 ; <V 'h0e 'h0e > ; <V 'h00 'h00 >
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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15380 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f98, toState: M, child: , data: tagged Valid CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
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calling cycle
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15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
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15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000033c > } }
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15390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000080001000 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8026 }
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15400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 }
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calling cycle
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15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 }
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15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8026 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h0000000080001000 'h0000000000000000 > } }
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15410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a }
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15420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
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calling cycle
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15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
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15430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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15830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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15830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000
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15840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f20
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After delta: vaddr = 0x80000f20
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15840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000
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15850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 }
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15850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 }
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15860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f10
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After delta: vaddr = 0x80000f10
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15860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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15870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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15870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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calling cycle
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15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 }
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15880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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15880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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15880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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calling cycle
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15890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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15890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > } }
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15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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15890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
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calling cycle
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15900 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000000000000a 'h0000000000000000 > } }
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[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000
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calling cycle
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15910 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f10, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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16060 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f58, toState: E, child: , data: tagged Valid CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
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calling cycle
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16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
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16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808e }
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16070 : [Ld resp] 'h07; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }
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16070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Valid 'h0
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calling cycle
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16080 : [doRespLdMem] 'h07; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 71 <= 0000000000000000000000001fffff44000000
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16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a }
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16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
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16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a }
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16080 : [Ld resp] 'h08; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }
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16080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Valid 'h3
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Valid St }
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16090 : [doRespLdMem] 'h08; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000
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16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa }
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16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
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16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa }
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16090 : [Ld resp] 'h0a; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }
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16090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Valid 'h1
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16090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16100 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 78 <= 0000000000000000000000001fffff44000000
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16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
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16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
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16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
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[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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16100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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16100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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16100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8036 }
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16110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 }
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calling cycle
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16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 }
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16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8036 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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16120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000000000000000 'hffff000000000000 > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h806a }
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16130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a }
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calling cycle
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16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a }
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16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806a }
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[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000000000000000 'hffff000000000000 > } }
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16140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001490 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8076 }
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16150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 }
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calling cycle
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16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 }
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16160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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16440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f58
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After delta: vaddr = 0x80000f58
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 }
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16460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h808e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001498 > } }
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16460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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16460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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16470 : [doRespLdForward] 'h08; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001498 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080001498 'h0000000000000000 > } }
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[RFile] wr_ 3: r 71 <= 0000000020000526000000001fffff44000000
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16470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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16480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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16480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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16480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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16490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a }
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16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809a }
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16490 : [Ld resp] 'h09; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }
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16490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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16490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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16490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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16490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e }
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instret:49 PC:0x1ffff000000000000000000008000008e instr:0xfb843583 iType:Ld [doCommitNormalInst [0]] 1649
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 72 <= 40000000200005260000ffff1fffff44000000
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16500 : [doRespLdMem] 'h09; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000
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16500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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|
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e }
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16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e }
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16500 : [Ld resp] 'h0a; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }
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16500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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16500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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|
Decoded delta from register = 0
|
|
Before delta: vaddr = 0x80000f40
|
|
After delta: vaddr = 0x80000f40
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 79 <= 0000000000000002800000001fffff44000000
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16510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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16510 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000
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16510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:50 PC:0x1ffff0000000000000000000080000092 instr:0x20b5055b iType:Cap [doCommitNormalInst [0]] 1651
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000
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16520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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16520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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16520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:51 PC:0x1ffff0000000000000000000080000096 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1652
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000
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[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Valid St }
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16530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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16530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 76 <= 0000000000000000000000001ffff800000000
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[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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16540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 }
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16540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f20
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After delta: vaddr = 0x80000f20
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16540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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16550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False }
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|
L1 TLB inc
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16550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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16550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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16560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 }
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16560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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|
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f10
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After delta: vaddr = 0x80000f10
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16560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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16570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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16570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 }
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16580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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|
Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000ef0
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After delta: vaddr = 0x80000ef0
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16580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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16580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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16590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > } }
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16590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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|
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True }
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|
L1 TLB inc
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|
16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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|
16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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|
16590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4
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|
16590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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|
Decoded delta from register = 0
|
|
Before delta: vaddr = 0x80000f28
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|
After delta: vaddr = 0x80000f28
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|
16590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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|
calling cycle
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16600 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 }
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16600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16600 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000000000000a 'h0000000000000000 > } }
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|
[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000
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16600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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|
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False }
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|
L1 TLB inc
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|
16600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
|
Decoded delta from register = 0
|
|
Before delta: vaddr = 0x80000f20
|
|
After delta: vaddr = 0x80000f20
|
|
16600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
|
|
calling cycle
|
|
calling cycle
|
|
16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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|
16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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|
16620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
|
calling cycle
|
|
calling cycle
|
|
16640 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ef0, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
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|
calling cycle
|
|
calling cycle
|
|
calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16680 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f10, toState: E, child: , data: tagged Valid CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
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16680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
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16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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16690 : [Ld resp] 'h0b; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }
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16690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Valid 'h4
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16690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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16690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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16700 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > } }
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16700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 }
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16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
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16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8076 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001490 > } }
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16700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Valid 'h3
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16700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001498 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8086 }
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16710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h809a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff000000000000 > } }
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16710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
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16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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16710 : [Ld resp] 'h0c; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }
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16710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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16710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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16710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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16720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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16720 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 }
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16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8086 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001498 > } }
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16720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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16720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff000000000000 > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8096 }
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16730 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h809e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16730 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: <V 'h0000000080001498 'hffff000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff000000000000 > } }
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[RFile] wr_ 3: r 74 <= 40000000200005260000ffff1fffff44000000
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16730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 79 <= 0000000000000002800000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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16740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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16740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff000000000000 > } }
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16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e }
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16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809e }
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16740 : [Ld resp] 'h0c; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }
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16740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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16740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 7a <= 000000002000002c000000001fffff44000000
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16750 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000
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16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False True False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 }
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16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8096 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff000000000000 > } }
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16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff000000000000 > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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16750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:52 PC:0x1ffff000000000000000000008000009a instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1675
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 7b <= 000000002000002e000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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16760 : [doRespLdForward] 'h0d; TaggedData { tag: True, data: <V 'h0000000080001498 'hffff000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff000000000000 > } }
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[RFile] wr_ 3: r 78 <= 40000000200005260000ffff1fffff44000000
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16760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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16760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 7c <= 00000000200003bc000000001fffff44000000
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16770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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16770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:53 PC:0x1ffff000000000000000000008000009e instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 1677
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 7f <= 00000000200003cc000000001fffff44000000
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[RFile] wr_ 1: r 76 <= 40000000200005261498ffff1ffff805261498
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16780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 }
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16780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000000000000 b: 'h0000000080001498 t: 'h00000000080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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16780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f20
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After delta: vaddr = 0x80000f20
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16780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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16790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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16790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f10
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After delta: vaddr = 0x80000f10
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16790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:54 PC:0x1ffff00000000000000000000800000a2 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 1679
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 }
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16800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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16800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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16800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:55 PC:0x1ffff00000000000000000000800000a6 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 1680
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Valid St }
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16810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80a6 }
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16810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f10
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After delta: vaddr = 0x80000f10
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16810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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16810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h3 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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16820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff000000000000 > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 }
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16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a6 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > } }
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16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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16820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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16820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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16830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 }
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16830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ef0
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After delta: vaddr = 0x80000ef0
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16830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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16840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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16840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > } }
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16840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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16840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000
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16850 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 }
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16850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16850 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000000000000a 'h0000000000000000 > } }
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[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000
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16850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f20
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After delta: vaddr = 0x80000f20
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16850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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16860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 }
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16860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h00000000800000b8 > } }
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16860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
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16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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16860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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16870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 }
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16870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > } }
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16870 : [doRespLdForward] 'h11; TaggedData { tag: False, data: <V 'h0000000000000000 'h00000000800000b8 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h00000000800000b8 'h0000000000000000 > } }
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[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16880 : [doRespLdForward] 'h12; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > } }
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[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000
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16880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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16890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f38
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After delta: vaddr = 0x80000f38
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16890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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16900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 }
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16910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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16910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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16910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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16910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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16920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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16920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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16920 : [Ld resp] 'h13; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001490 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }
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16920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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16920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f80
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After delta: vaddr = 0x80000f80
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16920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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16920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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16930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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16930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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16930 : [doRespLdMem] 'h13; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001490 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080001490 'h0000000000000000 > } }
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[RFile] wr_ 3: r 4a <= 0000000020000524000000001fffff44000000
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16930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 }
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16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 }
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16930 : [Ld resp] 'h14; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }
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16930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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16930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f98
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After delta: vaddr = 0x80000f98
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16930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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16930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca }
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calling cycle
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calling cycle
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16950 : [doRespLdMem] 'h14; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca }
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16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ca }
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16950 : [Ld resp] 'h16; TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }
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16950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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16960 : [doRespLdMem] 'h16; TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > } }
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000032 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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17030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 79 <= 0000000000000002800000001fffff44000000
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17040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 7a <= 000000002000002c000000001fffff44000000
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17050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 7b <= 000000002000002e000000001fffff44000000
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17060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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17060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 7c <= 00000000200003bc000000001fffff44000000
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17070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000b8 o: 'h00000000800000b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f20
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After delta: vaddr = 0x80000f20
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17070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 7f <= 00000000200003cc000000001fffff44000000
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17080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 }
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17080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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17080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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17090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 }
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17090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000000a o: 'h000000000000000a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f10
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After delta: vaddr = 0x80000f10
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17090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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17100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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17100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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17100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 }
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17110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ef0
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After delta: vaddr = 0x80000ef0
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17110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17120 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ef0, toState: E, child: , data: tagged Valid CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
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17120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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17120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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17120 : [Ld resp] 'h0f; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }
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17120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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17120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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17120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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17130 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 }
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17130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17130 : [doRespLdMem] 'h0f; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 0a <= 4000000000000000000000001fffff44000000
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17130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
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17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17130 : [Ld resp] 'h0e; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }
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17130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Valid 'h2
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17130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f20
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After delta: vaddr = 0x80000f20
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17130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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17140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 }
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17140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h00000000800000b8 > } }
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17140 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > } }
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17140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
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17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17140 : [Ld resp] 'h10; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }
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17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000
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17150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 }
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17150 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17150 : [doRespLdMem] 'h10; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17150 : [Ld resp] 'h11; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }
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17150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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17150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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17160 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > } }
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17160 : [doRespLdMem] 'h11; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 43 <= 4000000000000000000000001fffff44000000
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17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa }
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17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80aa }
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17160 : [Ld resp] 'h0e; TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }
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17160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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17170 : [doRespLdMem] 'h0e; TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 78 <= 40000000200005261498ffff1ffff805261498
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17170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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17180 : [doRespLdForward] 'h12; TaggedData { tag: False, data: <V 'h0000000000000000 'h00000000800000b8 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h00000000800000b8 'h0000000000000000 > } }
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[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000
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17180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f10
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After delta: vaddr = 0x80000f10
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17180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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17190 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > } }
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17190 : [doRespLdForward] 'h10; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000000000000a 'h0000000000000000 > } }
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[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000
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17190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001498 o: 'h0000000000000000 b: 'h0000000080001498 t: 'h00000000080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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instret:56 PC:0x1ffff00000000000000000000800000aa instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1719
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instret:57 PC:0x1ffff00000000000000000000800000ae instr:0x000045a9 iType:Alu [doCommitNormalInst [1]] 1719
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 }
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17200 : [doRespLdForward] 'h13; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > } }
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[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000
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instret:58 PC:0x1ffff00000000000000000000800000b0 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 1720
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instret:59 PC:0x1ffff00000000000000000000800000b4 instr:0x032080e7 iType:Jr [doCommitNormalInst [1]] 1720
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ef0
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After delta: vaddr = 0x80000ef0
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17210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:60 PC:0x1ffff00000000000000000000800000e2 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1721
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instret:61 PC:0x1ffff00000000000000000000800000e4 instr:0x0000fc06 iType:St [doCommitNormalInst [1]] 1721
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 44 <= 4000014000000000000000001fffff44000000
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h00000000800000b8 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e4 }
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17220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050000000000 o: 'h0000050000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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17220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f38
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After delta: vaddr = 0x80000f38
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17220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 }
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instret:62 PC:0x1ffff00000000000000000000800000e6 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1722
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instret:63 PC:0x1ffff00000000000000000000800000e8 instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1722
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Valid St }
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17230 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 }
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17230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 }
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17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e4 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h00000000800000b8 > } }
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17230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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17230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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17230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:64 PC:0x1ffff00000000000000000000800000ea instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1723
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instret:65 PC:0x1ffff00000000000000000000800000ee instr:0xfcb42e23 iType:St [doCommitNormalInst [1]] 1723
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|
calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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17240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80e6 }
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17240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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17240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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17240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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calling cycle
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17250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 }
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calling cycle
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17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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17260 : [Ld resp] 'h14; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001490 > }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }
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17260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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calling cycle
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17270 : [doRespLdMem] 'h14; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001490 > }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080001490 'h0000000000000000 > } }
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17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 }
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17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e6 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > } }
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17270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ea }
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17280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea }
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calling cycle
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17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea }
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17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ea }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > } }
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17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: <V False False False False False False False False False False False False True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80ee }
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17300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee }
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calling cycle
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17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee }
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17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f0c, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee }
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[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V False False False False False False False False False False False False True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > } }
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17310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f10
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After delta: vaddr = 0x80000f10
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17330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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17340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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17340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f0c
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After delta: vaddr = 0x80000f0c
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 }
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17350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, shiftBEData: <V False False False False False False False False False False False False True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f0c, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f0c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, vaddr: v: True a: 'h0000000080000f0c o: 'h0000000080000f0c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f0c, check_high: 'h00000000080000f10, check_inclusive: True } }, specBits: 'h000 }
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17360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f0c, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, pcHash: 'h80f6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f2 }
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17360 : [Ld resp] 'h11; TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }
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17360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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17360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ef0
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After delta: vaddr = 0x80000ef0
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17360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17370 : [doRespLdMem] 'h11; TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 0a <= 40000000200005261498ffff1ffff805261498
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17370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 }
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17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080000f0c, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f6 }
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17370 : [Ld resp] 'h12; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }
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17370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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17370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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17370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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17380 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 }
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17380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17380 : [doRespLdMem] 'h12; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000a00000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000000000000a 'h0000000000000000 > } }
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[RFile] wr_ 3: r 40 <= 0000000000000002800000001fffff44000000
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17380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f20
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After delta: vaddr = 0x80000f20
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17380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True False False False False False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f0c, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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17390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 }
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17390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17390 : [Ld resp] 'h13; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }
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17390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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17390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 }
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instret:66 PC:0x1ffff00000000000000000000800000f2 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1739
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 02 <= 00000000200003cc000000001fffff44000000
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17400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 }
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17400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17400 : [doRespLdMem] 'h13; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 43 <= 4000000000000000000000001fffff44000000
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17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 }
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17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 }
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17400 : [Ld resp] 'h14; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h00000000800000b8 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }
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17400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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17400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ef0
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After delta: vaddr = 0x80000ef0
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17400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 }
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instret:67 PC:0x1ffff00000000000000000000800000f6 instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 1740
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 44 <= 40000140200005261498ffff1ffff805261498
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17410 : [doRespLdMem] 'h14; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h00000000800000b8 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h00000000800000b8 'h0000000000000000 > } }
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[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000
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17410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 }
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17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 }
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17410 : [Ld resp] 'h15; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h00000000800000b8 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }
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17410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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17420 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 }
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17420 : [doRespLdMem] 'h15; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h00000000800000b8 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > } }
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[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000
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17420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:68 PC:0x1ffff00000000000000000000800000fa instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 1742
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 49 <= 0000000000000000000000001fffff44000000
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[RFile] wr_ 1: r 4a <= 0000000000000000000000001fffff44000000
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17430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x00000000
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After delta: vaddr = 0x00000000
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17430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:69 PC:0x1ffff00000000000000000000800000fe instr:0xfca44023 iType:St [doCommitNormalInst [0]] 1743
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 4d <= 0000000000000000400000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Valid St }
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[ALU redirect - 0] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80fe }
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17440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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17440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe }
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calling cycle
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[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h0 ; 'h0 ; <V 'h09 'h09 > ; <V 'h02 'h02 > ; <V <V False False True True True True True True True False False False False False False False False False False False False False False False False False False False False False False False > <V False False True True True True True True True False False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False True True True True False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False True True True True True False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h1 ; <V 'h05 'h04 > ; <V 'h04 'h05 >
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe }
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17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000ef0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe }
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[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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17460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000050080001498 'hffff00000527949c > > } ; tagged Invalid
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ef0
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After delta: vaddr = 0x80000ef0
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17550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef0, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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17560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f28
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After delta: vaddr = 0x80000f28
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17560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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17570 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef0, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 }
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17570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ef0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f20
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After delta: vaddr = 0x80000f20
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17570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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calling cycle
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17580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 }
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17580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8106 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000050080001498 'hffff00000527949c > > } }, repInfo: , setAuxData: tagged Invalid }
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17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000ef0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8102 }
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17580 : [Ld resp] 'h15; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }
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17580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000050080001498 'hffff00000527949c > > } ; tagged Invalid
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17580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 }
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calling cycle
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[RFile] wr_ 1: r 02 <= 00000000200003cc000000001fffff44000000
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17590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 }
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17590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8108 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17590 : [doRespLdMem] 'h15; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 43 <= 40000140200005261498ffff1ffff805261498
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17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 }
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17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8106 }
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17590 : [Ld resp] 'h16; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h00000000800000b8 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }
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17590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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17590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000ef0, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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17600 : [doRespLdMem] 'h16; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h00000000800000b8 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h00000000800000b8 'h0000000000000000 > } }
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[RFile] wr_ 3: r 46 <= 000000002000002e000000001fffff44000000
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17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 }
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17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8108 }
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17600 : [Ld resp] 'h17; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h00000000800000b8 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }
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17600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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17610 : [doRespLdMem] 'h17; TaggedData { tag: False, data: <V 'h0000000080000fa0 'h00000000800000b8 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080000fa0 'h0000000000000000 > } }
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[RFile] wr_ 3: r 47 <= 00000000200003e8000000001fffff44000000
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instret:70 PC:0x1ffff0000000000000000000080000102 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 1761
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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instret:71 PC:0x1ffff0000000000000000000080000106 instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 1762
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calling cycle
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[ALU redirect - 1] 'h1ffff00000000000000000000800000b8; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 }
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instret:72 PC:0x1ffff0000000000000000000080000108 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 1763
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instret:73 PC:0x1ffff000000000000000000008000010a instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 1763
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calling cycle
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|
[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; <V 'h03 'h02 > ; <V 'h02 'h02 > ; <V <V False False True False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False True True True True False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False True True True True True False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h1 ; <V 'h03 'h02 > ; <V 'h00 'h00 >
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calling cycle
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instret:74 PC:0x1ffff000000000000000000008000010c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1765
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f38
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After delta: vaddr = 0x80000f38
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17720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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17730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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17740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 }
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17740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h80b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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17740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000f78
|
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After delta: vaddr = 0x80000f78
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17740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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17750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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17750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } }, repInfo: , setAuxData: tagged Invalid }
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17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 }
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17750 : [Ld resp] 'h00; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001490 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }
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17750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000a00000000 > <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000080000fa0 'h00000000800000b8 > <V 'h0000000000000000 'h0000000080001490 > > } ; tagged Invalid
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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17760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17760 : [doRespLdMem] 'h00; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080001490 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080001490 'h0000000000000000 > } }
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[RFile] wr_ 3: r 4a <= 0000000020000524000000001fffff44000000
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17760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 }
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17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 }
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17770 : [Ld resp] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }
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17770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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17770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80001490
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After delta: vaddr = 0x80001490
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17770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17780 : [doRespLdMem] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 4d <= 0000000000000000000000001fffff44000000
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17780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f40
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After delta: vaddr = 0x80000f40
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17780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:75 PC:0x1ffff00000000000000000000800000b8 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 1778
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instret:76 PC:0x1ffff00000000000000000000800000bc instr:0xfaa44023 iType:St [doCommitNormalInst [1]] 1778
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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17790 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80bc }
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17790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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17790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f80
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After delta: vaddr = 0x80000f80
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17790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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17800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 }
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17800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80ca } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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17800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 }
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17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c4 }
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17800 : [Ld resp] 'h02; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }
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17800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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17800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f98
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After delta: vaddr = 0x80000f98
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17800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc }
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instret:77 PC:0x1ffff00000000000000000000800000c0 instr:0xfd843603 iType:Ld [doCommitNormalInst [0]] 1780
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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17810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 }
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17810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17810 : [doRespLdMem] 'h02; TaggedData { tag: True, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000
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17810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000000080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc }
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17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc }
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[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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17810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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17810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f90
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After delta: vaddr = 0x80000f90
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17810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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17820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 }
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17820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17820 : [doRespLdForward] 'h03; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 51 <= 40000140200005261498ffff1ffff805261498
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17820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 }
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17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 }
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17820 : [Ld resp] 'h04; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }
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17820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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17820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da }
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calling cycle
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[RFile] wr_ 0: r 4f <= 00000000200003e8000000001fffff44000000
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17830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 }
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17830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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17830 : [doRespLdMem] 'h04; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 4c <= 0000000000000000000000001fffff44000000
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17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da }
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17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da }
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17830 : [Ld resp] 'h05; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000033c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }
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17830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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17830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f80
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After delta: vaddr = 0x80000f80
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17830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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17830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc }
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instret:78 PC:0x1ffff00000000000000000000800000c4 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1783
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calling cycle
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[RFile] wr_ 1: r 08 <= 0000000000000000000000001fffff44000000
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17840 : [doRespLdMem] 'h05; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000033c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000008000033c 'h0000000000000000 > } }
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[RFile] wr_ 3: r 55 <= 00000000200000cf000000001fffff44000000
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17840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc }
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17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc }
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17840 : [Ld resp] 'h06; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000033c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }
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17840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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17840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80001490
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After delta: vaddr = 0x80001490
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calling cycle
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17850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 }
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17850 : [doRespLdMem] 'h06; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000033c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080001000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 56 <= 0000000020000400000000001fffff44000000
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17850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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instret:79 PC:0x1ffff00000000000000000000800000c6 instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 1785
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calling cycle
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17860 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 }
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calling cycle
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[ALU redirect - 0] 'h1ffff000000000000000000008000033c; 'h1; InstTag { way: 'h0, ptr: 'h09, t: 'h12 }
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instret:80 PC:0x1ffff00000000000000000000800000c8 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1787
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001490, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80c8 }
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17880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 }
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[ROB incorrectSpec] 'h1 ; InstTag { way: 'h0, ptr: 'h09, t: 'h12 } ; 'h1 ; 'h1 ; <V 'h0a 'h09 > ; <V 'h06 'h05 > ; <V <V False False False False False False True True True True False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False True True True True False False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h1 ; <V 'h0a 'h09 > ; <V 'h00 'h00 >
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 }
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17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080001490, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c8 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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17890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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instret:81 PC:0x1ffff00000000000000000000800000ca instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 1790
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instret:82 PC:0x1ffff00000000000000000000800000ce instr:0xfea44023 iType:St [doCommitNormalInst [1]] 1790
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Valid St }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h80ce }
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17910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce }
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instret:83 PC:0x1ffff00000000000000000000800000d2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1791
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce }
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17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ce }
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[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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17920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f80
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After delta: vaddr = 0x80000f80
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18010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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18020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f98
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After delta: vaddr = 0x80000f98
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18020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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18030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 }
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18030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h80d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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18030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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18030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f90
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After delta: vaddr = 0x80000f90
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18030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 }
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calling cycle
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18040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 }
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18040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h80da } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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18040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 }
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18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80d6 }
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18040 : [Ld resp] 'h06; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }
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18040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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18040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da }
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calling cycle
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[RFile] wr_ 1: r 4f <= 00000000200003e8000000001fffff44000000
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18050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 }
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18050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h80dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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18050 : [doRespLdMem] 'h06; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 4c <= 40000140200005261498ffff1ffff805261498
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18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da }
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18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80da }
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18050 : [Ld resp] 'h07; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000033c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }
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18050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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18050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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18060 : [doRespLdMem] 'h07; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000033c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000008000033c 'h0000000000000000 > } }
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[RFile] wr_ 3: r 55 <= 00000000200000cf000000001fffff44000000
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18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc }
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18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80dc }
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18060 : [Ld resp] 'h08; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000033c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }
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18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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18070 : [doRespLdMem] 'h08; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000033c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080001000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 56 <= 0000000020000400000000001fffff44000000
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instret:84 PC:0x1ffff00000000000000000000800000d6 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1807
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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instret:85 PC:0x1ffff00000000000000000000800000da instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 1808
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calling cycle
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[ALU redirect - 1] 'h1ffff000000000000000000008000033c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 }
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instret:86 PC:0x1ffff00000000000000000000800000dc instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 1809
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instret:87 PC:0x1ffff00000000000000000000800000de instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 1809
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calling cycle
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[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; <V 'h03 'h02 > ; <V 'h02 'h02 > ; <V <V False False True False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h1 ; <V 'h03 'h02 > ; <V 'h00 'h00 >
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calling cycle
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instret:88 PC:0x1ffff00000000000000000000800000e0 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 1811
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000050 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000fd0
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After delta: vaddr = 0x80000fd0
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18180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000045 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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18190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000fc8
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After delta: vaddr = 0x80000fc8
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18190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 59 <= 0000000000000014000000001fffff44000000
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18200 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 }
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18200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000050 o: 'h0000000000000050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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18200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000fc8
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After delta: vaddr = 0x80000fc8
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h16, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000116 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18210 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 }
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18210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc8, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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instret:89 PC:0x1ffff000000000000000000008000033c instr:0xfca44823 iType:St [doCommitNormalInst [0]] 1821
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instret:90 PC:0x1ffff0000000000000000000080000340 instr:0x05000513 iType:Alu [doCommitNormalInst [1]] 1821
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calling cycle
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[RFile] wr_ 0: r 5d <= 0000000000000011400000001fffff44000000
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18220 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000fc8 o: 'h0000000080000fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc8, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h833c }
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18220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000fc8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h834c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000050 > } }
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18220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c }
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instret:91 PC:0x1ffff0000000000000000000080000344 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 1822
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instret:92 PC:0x1ffff0000000000000000000080000348 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1822
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calling cycle
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18230 : [doRespLdForward] 'h09; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000050 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000050 'h0000000000000000 > } }
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[RFile] wr_ 3: r 5b <= 0000000000000014000000001fffff44000000
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18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } }, repInfo: , setAuxData: tagged Invalid }
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18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c }
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18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h833c }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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18230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc8, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000050 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8344 }
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18240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 }
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calling cycle
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18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } }, repInfo: , setAuxData: tagged Invalid }
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18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 }
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18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fc8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8344 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000050 > } }
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18250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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instret:93 PC:0x1ffff000000000000000000008000034c instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 1825
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instret:94 PC:0x1ffff0000000000000000000080000350 instr:0x04500513 iType:Alu [doCommitNormalInst [1]] 1825
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calling cycle
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calling cycle
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instret:95 PC:0x1ffff0000000000000000000080000354 instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 1827
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instret:96 PC:0x1ffff0000000000000000000080000358 instr:0x1160006f iType:J [doCommitNormalInst [1]] 1827
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffcb8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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18750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000fd0
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After delta: vaddr = 0x80000fd0
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calling cycle
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18760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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calling cycle
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[RFile] wr_ 1: r 60 <= 000000002000011c800000001fffff44000000
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18770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 }
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18770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h846e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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18770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e }
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calling cycle
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[RFile] wr_ 1: r 62 <= 000000002000011e800000001fffff44000000
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[ALU redirect - 1] 'h1ffff000000000000000000008000012a; 'h0; InstTag { way: 'h1, ptr: 'h07, t: 'h0f }
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18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } }, repInfo: , setAuxData: tagged Invalid }
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18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e }
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18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846e }
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18780 : [Ld resp] 'h0a; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }
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18780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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calling cycle
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[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h07, t: 'h0f } ; 'h0 ; 'h1 ; <V 'h08 'h08 > ; <V 'h07 'h06 > ; <V <V False False False False False False False True False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False True True False False False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h0 ; <V 'h08 'h08 > ; <V 'h00 'h00 >
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calling cycle
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18800 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 5f <= 40000140200005261498ffff1ffff805261498
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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calling cycle
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instret:97 PC:0x1ffff000000000000000000008000046e instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 1882
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instret:98 PC:0x1ffff0000000000000000000080000472 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1882
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calling cycle
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instret:99 PC:0x1ffff0000000000000000000080000476 instr:0xcb8080e7 iType:Jr [doCommitNormalInst [0]] 1883
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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19310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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19320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f98
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After delta: vaddr = 0x80000f98
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19320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 64 <= 00000000200003dc000000001fffff44000000
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19330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000047a o: 'h000000008000047a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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19330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f90
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After delta: vaddr = 0x80000f90
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19330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 67 <= 00000000200003e8000000001fffff44000000
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19340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 }
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19340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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19340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f80
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After delta: vaddr = 0x80000f80
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19340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:100 PC:0x1ffff000000000000000000008000012a instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 1934
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calling cycle
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19350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 }
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19350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000050080001498 o: 'h0000000000000000 b: 'h0000050080001498 t: 'h00000050080001498 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: True, potentialCapLoad: True }
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L1 TLB inc
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19350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f80
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After delta: vaddr = 0x80000f80
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instret:101 PC:0x1ffff000000000000000000008000012c instr:0x0000f406 iType:St [doCommitNormalInst [0]] 1935
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calling cycle
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[RFile] wr_ 0: r 6a <= 0000000000000000000000001fffff44000000
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19360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000047a > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812c }
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19360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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19360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c }
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|
instret:102 PC:0x1ffff000000000000000000008000012e instr:0x0000f022 iType:St [doCommitNormalInst [0]] 1936
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instret:103 PC:0x1ffff0000000000000000000080000130 instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 1936
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calling cycle
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19370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 }
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19370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h8136 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000033c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c }
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19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812c }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000047a > } }
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19370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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instret:104 PC:0x1ffff0000000000000000000080000132 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 1937
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000080001000 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h812e }
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19380 : [doRespLdForward] 'h0b; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 68 <= 40000140200005261498ffff1ffff805261498
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19380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e }
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19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h812e }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h0000000080001000 'h0000000000000000 > } }
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19390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8132 }
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19400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 }
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instret:105 PC:0x1ffff0000000000000000000080000136 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1940
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instret:106 PC:0x1ffff000000000000000000008000013a instr:0xfea005db iType:Cap [doCommitNormalInst [1]] 1940
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calling cycle
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19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 }
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19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8132 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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19410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h09f }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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19880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:107 PC:0x1ffff000000000000000000008000013e instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 1988
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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19890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f80
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After delta: vaddr = 0x80000f80
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instret:108 PC:0x1ffff0000000000000000000080000142 instr:0x00c0006f iType:J [doCommitNormalInst [0]] 1989
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapInspect GetLen, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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19900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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19900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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19910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 }
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19910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h814e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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19910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f80
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After delta: vaddr = 0x80000f80
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19910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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19920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e }
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19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e }
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19920 : [Ld resp] 'h0c; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }
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19920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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19920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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19930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 }
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19930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, pcHash: 'h8158 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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19930 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 6c <= 40000140200005261498ffff1ffff805261498
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19930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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19930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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19930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000322 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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19940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 }
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19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8158 }
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19940 : [Ld resp] 'h0d; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }
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19940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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19940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f70
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After delta: vaddr = 0x80000f70
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19940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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19950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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19950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8164 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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19950 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000050080001498 'hffff00000527949c > } }
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[RFile] wr_ 3: r 6e <= 40000140200005261498ffff1ffff805261498
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19950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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19950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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19950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 }
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instret:109 PC:0x1ffff000000000000000000008000014e instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 1995
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000320 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 6d <= 0000014020000526000000001fffff44000000
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19960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 }
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19960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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19960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000050080001498 o: 'h0000050080001498 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 }
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19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 }
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19960 : [Ld resp] 'h0e; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }
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19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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19960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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19960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 }
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calling cycle
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[RFile] wr_ 1: r 74 <= 000000002000045b800000001fffff44000000
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19970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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19970 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 73 <= 0000000000000000000000001fffff44000000
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19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 }
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19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 }
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19970 : [Ld resp] 'h0f; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }
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19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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19970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f70
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After delta: vaddr = 0x80000f70
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19970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:110 PC:0x1ffff0000000000000000000080000152 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 1997
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calling cycle
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[RFile] wr_ 0: r 6b <= 0000000000000000000000001fffff44000000
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19980 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000
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19980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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19980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80001490
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After delta: vaddr = 0x80001490
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instret:111 PC:0x1ffff0000000000000000000080000154 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1998
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calling cycle
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[RFile] wr_ 0: r 77 <= 0000000020000524000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid }
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19990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000050080001498 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8154 }
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19990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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19990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 }
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calling cycle
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[RFile] wr_ 0: r 75 <= 000000002000045e000000001fffff44000000
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20000 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 }
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20000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8176 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 }
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20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V False False False False False False False False True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000050080001498 > } }
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20000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000050080001498 > > } ; tagged Invalid
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20000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 }
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instret:112 PC:0x1ffff0000000000000000000080000158 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2000
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instret:113 PC:0x1ffff000000000000000000008000015c instr:0xfe35055b iType:Cap [doCommitNormalInst [1]] 2000
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calling cycle
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[RFile] wr_ 1: r 71 <= 0000000000000000000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Valid St }
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20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 }
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20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 }
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20010 : [Ld resp] 'h10; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }
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20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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instret:114 PC:0x1ffff0000000000000000000080000160 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2001
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calling cycle
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[RFile] wr_ 1: r 53 <= 0000000020000526000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Valid St }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8160 }
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20020 : [doRespLdMem] 'h10; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000
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20020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 }
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calling cycle
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calling cycle
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20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000050080001498 > > } }, repInfo: , setAuxData: tagged Invalid }
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20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 }
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20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8160 }
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[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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20040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000050080001498 > > } ; tagged Invalid
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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20480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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20490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f78
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After delta: vaddr = 0x80000f78
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20490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000322 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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20500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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20500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f70
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After delta: vaddr = 0x80000f70
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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20510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 }
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20510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8164 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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20510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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20510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000320 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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20520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 }
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20520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000050080001498 > > } }, repInfo: , setAuxData: tagged Invalid }
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20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 }
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20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 }
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20520 : [Ld resp] 'h10; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000050080001498 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }
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20520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000050080001498 > > } ; tagged Invalid
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20520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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20520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0c2 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 74 <= 000000002000045b800000001fffff44000000
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20530 : [doRespLdMem] 'h10; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000050080001498 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000050080001498 'h0000000000000000 > } }
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[RFile] wr_ 3: r 73 <= 0000014020000526000000001fffff44000000
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20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000050080001498 > > } }, repInfo: , setAuxData: tagged Invalid }
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20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 }
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20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8168 }
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20530 : [Ld resp] 'h11; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000050080001498 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }
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20530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False True False >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000080001498 > <V 'h0000000000000000 'hffff000000000000 > <V 'h0000000000000000 'h0000050080001498 > > } ; tagged Invalid
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20530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80001490
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After delta: vaddr = 0x80001490
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 77 <= 0000000020000524000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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20540 : [doRespLdMem] 'h11; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000050080001498 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 72 <= 0000000000000000000000001fffff44000000
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20540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001490, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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calling cycle
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[RFile] wr_ 0: r 75 <= 000000002000045e000000001fffff44000000
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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20550 : [doFinishMem] DTlbResp { resp: <'h0000000080001490,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001490 o: 'h0000000080001490 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001490, check_high: 'h00000000080001498, check_inclusive: True } }, specBits: 'h000 }
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20550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080001490, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8176 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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20550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 }
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instret:115 PC:0x1ffff0000000000000000000080000164 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2055
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calling cycle
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[RFile] wr_ 0: r 53 <= 0000000020000526000000001fffff44000000
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20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 }
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20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080001490, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8176 }
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20560 : [Ld resp] 'h12; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }
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20560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False True >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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instret:116 PC:0x1ffff0000000000000000000080000168 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 2056
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 71 <= 0000014020000526000000001fffff44000000
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20570 : [doRespLdMem] 'h12; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000
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20570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080001490, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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20580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f98
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After delta: vaddr = 0x80000f98
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20580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:117 PC:0x1ffff000000000000000000008000016c instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2058
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instret:118 PC:0x1ffff000000000000000000008000016e instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2058
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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20590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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20590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000f90
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After delta: vaddr = 0x80000f90
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instret:119 PC:0x1ffff0000000000000000000080000172 instr:0x32258593 iType:Alu [doCommitNormalInst [0]] 2059
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instret:120 PC:0x1ffff0000000000000000000080000176 instr:0x00006190 iType:Ld [doCommitNormalInst [1]] 2059
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calling cycle
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[RFile] wr_ 1: r 7a <= 0000000020000526000000001fffff44000000
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20600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h001 }
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20600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h81a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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20600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h001 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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20600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 }
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instret:121 PC:0x1ffff0000000000000000000080000178 instr:0x00001597 iType:Auipc [doCommitNormalInst [0]] 2060
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instret:122 PC:0x1ffff000000000000000000008000017c instr:0x32058593 iType:Alu [doCommitNormalInst [1]] 2060
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calling cycle
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[RFile] wr_ 0: r 05 <= 00000000200003e8000000001fffff44000000
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20610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 }
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|
20610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h81a6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 }
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20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 }
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20610 : [Ld resp] 'h13; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000047a > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }
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20610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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20610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 }
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instret:123 PC:0x1ffff0000000000000000000080000180 instr:0x000095b2 iType:Alu [doCommitNormalInst [0]] 2061
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calling cycle
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20620 : [doRespLdMem] 'h13; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000047a > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000008000047a 'h0000000000000000 > } }
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[RFile] wr_ 3: r 7e <= 000000002000011e800000001fffff44000000
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20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
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20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 }
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20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a6 }
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20620 : [Ld resp] 'h14; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000047a > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }
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20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V True False False True >, data: <V <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000080001000 'h000000008000047a > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
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instret:124 PC:0x1ffff0000000000000000000080000182 instr:0x00b50463 iType:Br [doCommitNormalInst [0]] 2062
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instret:125 PC:0x1ffff0000000000000000000080000186 instr:0x01e0006f iType:J [doCommitNormalInst [1]] 2062
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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20630 : [doRespLdMem] 'h14; TaggedData { tag: False, data: <V 'h0000000080001000 'h000000008000047a > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080001000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 57 <= 0000000020000400000000001fffff44000000
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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instret:126 PC:0x1ffff00000000000000000000800001a4 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 2064
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calling cycle
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instret:127 PC:0x1ffff00000000000000000000800001a6 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 2065
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instret:128 PC:0x1ffff00000000000000000000800001a8 instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 2065
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calling cycle
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instret:129 PC:0x1ffff00000000000000000000800001aa instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2066
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged Move , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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21130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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21140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000fd0
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After delta: vaddr = 0x80000fd0
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21140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 78 <= 0000000000000000000000001fffff44000000
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21150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, shiftBEData: <V True True True True True True True True True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: False, potentialCapLoad: True }
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L1 TLB inc
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21150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ff8
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After delta: vaddr = 0x80000ff8
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21150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 0a <= 0000000000000000000000001fffff44000000
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21160 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True >, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 }
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21160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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21160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ff0
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After delta: vaddr = 0x80000ff0
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instret:130 PC:0x1ffff000000000000000000008000047a instr:0xfea0055b iType:Cap [doCommitNormalInst [0]] 2116
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calling cycle
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21170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 }
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21170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h8484 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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21170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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21170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 }
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instret:131 PC:0x1ffff000000000000000000008000047e instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2117
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instret:132 PC:0x1ffff0000000000000000000080000482 instr:0x00004501 iType:Alu [doCommitNormalInst [1]] 2117
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calling cycle
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[RFile] wr_ 0: r 7b <= 0000000020000400000000001fffff44000000
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21180 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h847e }
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21180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8486 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
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21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } }, repInfo: , setAuxData: tagged Invalid }
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21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 }
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21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8484 }
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21180 : [Ld resp] 'h15; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000018 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }
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21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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21180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 }
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calling cycle
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21190 : [doRespLdMem] 'h15; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000018 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000080000018 'h0000000000000000 > } }
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[RFile] wr_ 3: r 01 <= 0000000020000006000000001fffff44000000
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21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } }, repInfo: , setAuxData: tagged Invalid }
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21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 }
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21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8486 }
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21190 : [Ld resp] 'h16; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000018 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }
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21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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21190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e }
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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21200 : [doRespLdMem] 'h16; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000018 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 44 <= 0000000000000000000000001fffff44000000
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21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000050080001498 'hffff00000527949c > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } }, repInfo: , setAuxData: tagged Invalid }
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21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e }
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21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
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21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h847e }
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[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True True True True True True True True True >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000050 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000080000018 > > } ; tagged Invalid
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calling cycle
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[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
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instret:133 PC:0x1ffff0000000000000000000080000484 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2121
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calling cycle
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[ALU redirect - 1] 'h1ffff0000000000000000000080000018; 'h0; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }
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instret:134 PC:0x1ffff0000000000000000000080000486 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2122
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|
instret:135 PC:0x1ffff0000000000000000000080000488 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2122
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calling cycle
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[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0a, t: 'h15 } ; 'h0 ; 'h1 ; <V 'h0b 'h0b > ; <V 'h0b 'h0a > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False True False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h0 ; <V 'h0b 'h0b > ; <V 'h00 'h00 >
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calling cycle
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instret:136 PC:0x1ffff000000000000000000008000048a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2124
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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21320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 45 <= 0000000000000000000000001fffff44000000
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[RFile] wr_ 1: r 7c <= 0000000000000000000000001fffff44000000
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21330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x00000000
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After delta: vaddr = 0x00000000
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21330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 40 <= 0000000000000000400000001fffff44000000
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21340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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21340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ff8
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After delta: vaddr = 0x80000ff8
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21340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:137 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 2134
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instret:138 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 2134
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 1: r 0c <= 00000000200003e4000000001fffff44000000
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21350 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 }
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21350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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21350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000ff0
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After delta: vaddr = 0x80000ff0
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21350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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instret:139 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 2135
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 42 <= 0000000020000400000000001fffff44000000
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21360 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 }
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21360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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21360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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|
Before delta: vaddr = 0x80000fd8
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After delta: vaddr = 0x80000fd8
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21360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000456 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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21370 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 }
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[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: <V True True True True True True True True False False False False False False False False >, data: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000 > }, loadTags: False }
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21370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: True, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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21370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80000fd8
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After delta: vaddr = 0x80000fd8
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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21380 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 }
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21380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
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DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd8, write: False, capStore: False, potentialCapLoad: False }
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L1 TLB inc
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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calling cycle
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21390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000080000fd8 o: 'h0000000080000fd8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd8, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 }
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21390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fd8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, pcHash: 'h802e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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21390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00010000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
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calling cycle
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[RFile] wr_ 0: r 47 <= 000000002000040e800000001fffff44000000
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21400 : [doRespLdForward] 'h17; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
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[RFile] wr_ 3: r 4b <= 0000000000000000000000001fffff44000000
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21400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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Decoded delta from register = 0
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Before delta: vaddr = 0x80001490
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After delta: vaddr = 0x80001490
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21400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h027 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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2141: mmioPlatform.rl_tohost: 0x1 (= 1)
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PASS
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