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3a79b022ea0ccf14f4aabaf620bf466b8923e093
Toooba/src_Core/RISCY_OOO/procs/lib
History
Jonathan Woodruff 3a79b022ea Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage!
2020-03-18 11:35:59 +00:00
..
Amo.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Bht.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
BrPred.bsv
Changes to support 'C' extension (compressed instructions). Details follow.
2019-04-09 13:50:16 -04:00
Btb.bsv
Reduce needless fetch stalls in presence of compressed instructions
2020-01-01 22:22:17 +00:00
Bypass.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
CacheUtils.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ConcatReg.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Decode.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
DirPredictor.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
DTlb.bsv
Added verbosity guards around $displays to dial down log verbosity
2019-04-01 20:35:52 -04:00
Ehr.bsv
Pipe through memory results. This design passes 100 memory test sequences of TestRIG. Yay!
2019-12-13 10:53:02 +00:00
EpochManager.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Exec.bsv
Changes to support 'C' extension (compressed instructions). Details follow.
2019-04-09 13:50:16 -04:00
Fifo.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
FP_Utils.bsv
FP ISA tests bug fixes:
2019-12-06 14:27:33 +05:30
Fpu.bsv
Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.
2020-03-08 21:29:30 -04:00
FullAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GlobalBrHistReg.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GlobalSpecUpdate.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GSelectPred.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GSharePred.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
HasSpecBits.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ITlb.bsv
Added verbosity guards around $displays to dial down log verbosity
2019-04-01 20:35:52 -04:00
L1CoCache.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
L1LLConnect.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
L2SetAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
L2Tlb.bsv
Bugfix. Now passing rv64si-p-dirty ISA test.
2019-04-11 14:30:53 -04:00
LatencyTimer.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
LLCache.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
LLCDmaConnect.bsv
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
LLCRqMshrSecureModel.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
MemLoader.bsv
Changes to support 'C' extension (compressed instructions). Details follow.
2019-04-09 13:50:16 -04:00
MemLoaderIF.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
MemoryTypes.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
MMIOAddrs.bsv
In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately.
2020-02-28 14:07:45 -05:00
MMIOCore.bsv
Bug fixes; now passing rv64mi-p-access ISA test
2019-04-10 12:42:23 -04:00
MMIOInst.bsv
Revert unwanted MMIOInst diff in e7fbf32b38
2019-11-03 03:47:25 +00:00
MsgFifo.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
MulDiv.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Performance.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
PhysRFile.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ProcTypes.bsv
Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage!
2020-03-18 11:35:59 +00:00
Ras.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
RenameDebugIF.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
RenamingTable.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ReorderBuffer.bsv
Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage!
2020-03-18 11:35:59 +00:00
ReservationStationEhr.bsv
Added verbosity guards around $displays to dial down log verbosity
2019-04-01 20:35:52 -04:00
SafeCounter.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Scoreboard.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SetAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SpecFifo.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SpecPoisonFifo.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SpecTagManager.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SplitLSQ.bsv
Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage!
2020-03-18 11:35:59 +00:00
StoreBuffer.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
TlbConnect.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
TlbTypes.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
TourPred.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
TourPredSecure.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
TranslationCache.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Types.bsv
Changes to support vectored RVFI_DII bridge directly, which enables us to successfully run memory tests with traps.
2019-12-09 16:34:27 +00:00
VerificationPacket.bsv
Initial load of files
2019-03-26 14:49:40 -04:00