rsnikhil 40b55d2c32 Fixed a Tandem-Verification issue (report MIP change due to interrupts). ...

CSR MIP can change due to external/timer interrupts.  These non-instruction-related
changes were not being reported to the Tandem Verifier.

2020-03-03 18:34:00 -05:00

..

Core.bsv

Fixed Tandem Verif trace gen for CSRRx on WARL regs: report post-WARL-xformed write-data

2020-02-11 15:46:24 -05:00

CPU_Decode_C.bsv

Changes to support 'C' extension (compressed instructions). Details follow.

2019-04-09 13:50:16 -04:00

CsrFile.bsv

Fixed a Tandem-Verification issue (report MIP change due to interrupts).

2020-03-03 18:34:00 -05:00

LLC_AXI4_Adapter.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

MMIO_AXI4_Adapter.bsv

In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately.

2020-02-28 14:07:45 -05:00

MMIOPlatform.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Proc_IFC.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Proc.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00