4131dcd073
specified and causes kernel panics. Hopefully the details of what should happen in these cases is correct, but we shall see...
638 lines
24 KiB
Plaintext
638 lines
24 KiB
Plaintext
// Copyright (c) 2019-2020 Bluespec, Inc. All Rights Reserved
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//
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Alexandre Joannou
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package PLIC;
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// ================================================================
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// This package implements a PLIC (Platform-Level Interrupt Controller)
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// conforming to the RISC-V PLIC standard.
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// It is parameterized for:
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// - # of sources
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// - # of targets
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// - # of priorities
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//
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// ================================================================
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// Bluespec lib imports
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import ConfigReg :: *;
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import Vector :: *;
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import FIFOF :: *;
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import ClientServer :: *;
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import Assert :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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import Semi_FIFOF :: *;
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import SourceSink :: *;
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import AXI4 :: *;
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// ================================================================
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// Project imports
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import Fabric_Defs :: *; // for Wd_SId_2x3, Wd_Addr, Wd_Data...
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// ================================================================
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// Change bitwidth without requiring < or > constraints.
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function Bit #(m) changeWidth (Bit #(n) x);
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Bit #(TAdd #(m, n)) y = zeroExtend (x);
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Bit #(m) z = y [valueOf (m)-1 : 0];
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return z;
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endfunction
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// ================================================================
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// Maximum supported sources, targets, ...
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typedef 10 T_wd_source_id; // Max 1024 sources (source 0 is reserved for 'no interrupt')
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typedef 5 T_wd_target_id; // Max 32 targets
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// ================================================================
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// Interfaces
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// ----------------
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// Individual source interface
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interface PLIC_Source_IFC;
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(* always_ready, always_enabled *)
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method Action m_interrupt_req (Bool set_not_clear);
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endinterface
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// ----------------
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// Individual target interface
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interface PLIC_Target_IFC;
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(* always_ready *)
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method Bool m_eip; // external interrupt pending
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endinterface
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// ----------------
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// PLIC interface
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interface PLIC_IFC #(numeric type t_n_external_sources,
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numeric type t_n_targets,
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numeric type t_max_priority);
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// Debugging
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method Action set_verbosity (Bit #(4) verbosity);
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method Action show_PLIC_state;
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// Reset
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interface Server #(Bit #(0), Bit #(0)) server_reset;
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// set_addr_map should be called after this module's reset
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method Action set_addr_map (Bit #(64) addr_base, Bit #(64) addr_lim);
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// Memory-mapped access
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interface AXI4_Slave #( Wd_SId_2x3, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
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axi4_slave;
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// sources
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interface Vector #(t_n_external_sources, PLIC_Source_IFC) v_sources;
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// targets EIPs (External Interrupt Pending)
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interface Vector #(t_n_targets, PLIC_Target_IFC) v_targets;
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endinterface
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// ================================================================
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// PLIC module implementation
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module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
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provisos (Add #(1, t_n_external_sources, t_n_sources), // source 0 is reserved for 'no source'
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Add #(_any_0, TLog #(t_n_sources), T_wd_source_id),
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Add #(_any_1, TLog #(t_n_targets), T_wd_target_id),
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Log #(TAdd #(t_max_priority, 1), t_wd_priority));
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// 0 = quiet; 1 = show PLIC transactions; 2 = also show AXI4 transactions
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0);
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// Source_Ids and Priorities are read and written over the memory interface
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// and should fit within the data bus width, currently 64 bits.
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staticAssert ((valueOf (TLog #(t_n_sources)) <= 64), "PLIC: t_n_sources parameter too large");
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staticAssert ((valueOf (TLog #(TAdd #(t_max_priority, 1))) <= 64), "PLIC: t_max_priority parameter too large");
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Integer n_sources = valueOf (t_n_sources);
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Integer n_targets = valueOf (t_n_targets);
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// ----------------
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// Soft reset requests and responses
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FIFOF #(Bit #(0)) f_reset_reqs <- mkFIFOF;
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FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF;
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// ----------------
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// Memory-mapped access
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// Base and limit addrs for this memory-mapped block.
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Reg #(Bit #(64)) rg_addr_base <- mkRegU;
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Reg #(Bit #(64)) rg_addr_lim <- mkRegU;
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// Connector to AXI4 fabric
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let slavePortShim <- mkAXI4ShimFF;
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// ----------------
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// Per-interrupt source state
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// Interrupt pending from source
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Vector #(t_n_sources, Reg #(Bool)) vrg_source_ip <- replicateM (mkConfigReg (False));
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// Interrupt claimed and being serviced by a hart
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Vector #(t_n_sources, Reg #(Bool)) vrg_source_busy <- replicateM (mkReg (False));
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// Priority for this source
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Vector #(t_n_sources, Reg #(Bit #(t_wd_priority))) vrg_source_prio <- replicateM (mkReg (0));
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// ----------------
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// Per-target hart context state
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// Threshold: interrupts at or below threshold should be masked out for target
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Vector #(t_n_targets, Reg #(Bit #(t_wd_priority))) vrg_target_threshold <- replicateM (mkReg ('1));
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// Target has claimed interrupt for source and is servicing it
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Vector #(t_n_targets, Reg #(Bit #(TLog #(t_n_sources)))) vrg_servicing_source <- replicateM (mkReg (0));
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// ----------------
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// Per-target, per-source state
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// Interrupt enables from source to target
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Vector #(t_n_targets,
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Vector #(t_n_sources, Reg #(Bool))) vvrg_ie <- replicateM (replicateM (mkReg (False)));
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// ================================================================
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// Compute outputs for each target (combinational)
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function Tuple2 #(Bit #(t_wd_priority), Bit #(TLog #(t_n_sources)))
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fn_target_max_prio_and_max_id (Bit #(T_wd_target_id) target_id);
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Bit #(t_wd_priority) max_prio = 0;
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Bit #(TLog #(t_n_sources)) max_id = 0;
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// Note: source_ids begin at 1, not 0.
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for (Integer source_id = 1; source_id < n_sources; source_id = source_id + 1)
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if ( vrg_source_ip [source_id]
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&& (vrg_source_prio [source_id] > max_prio)
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&& (vvrg_ie [target_id][source_id])) begin
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max_id = fromInteger (source_id);
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max_prio = vrg_source_prio [source_id];
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end
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// Assert: if any interrupt is pending (max_id > 0), then prio > 0
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return tuple2 (max_prio, max_id);
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endfunction
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function Action fa_show_PLIC_state;
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action
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$display ("----------------");
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$write ("Src IPs :");
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for (Integer source_id = 0; source_id < n_sources; source_id = source_id + 1)
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$write (" %0d", pack (vrg_source_ip [source_id]));
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$display ("");
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$write ("Src Prios:");
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for (Integer source_id = 0; source_id < n_sources; source_id = source_id + 1)
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$write (" %0d", vrg_source_prio [source_id]);
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$display ("");
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$write ("Src busy :");
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for (Integer source_id = 0; source_id < n_sources; source_id = source_id + 1)
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$write (" %0d", pack (vrg_source_busy [source_id]));
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$display ("");
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for (Integer target_id = 0; target_id < n_targets; target_id = target_id + 1) begin
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$write ("T %0d IEs :", target_id);
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for (Integer source_id = 0; source_id < n_sources; source_id = source_id + 1)
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$write (" %0d", vvrg_ie [target_id][source_id]);
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match { .max_prio, .max_id } = fn_target_max_prio_and_max_id (fromInteger (target_id));
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$display (" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d",
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max_prio, vrg_target_threshold [target_id], max_id, vrg_servicing_source [target_id]);
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end
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endaction
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endfunction
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// ================================================================
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// Soft reset
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rule rl_reset;
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if (cfg_verbosity > 0)
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$display ("%0d: PLIC.rl_reset", cur_cycle);
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let x <- pop (f_reset_reqs);
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for (Integer source_id = 0; source_id < n_sources; source_id = source_id + 1) begin
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vrg_source_ip [source_id] <= False;
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vrg_source_busy [source_id] <= False;
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vrg_source_prio [source_id] <= 0;
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end
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for (Integer target_id = 0; target_id < n_targets; target_id = target_id + 1) begin
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// Mask all interrupts with highest threshold
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vrg_target_threshold [target_id] <= '1;
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vrg_servicing_source [target_id] <= 0;
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end
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for (Integer target_id = 0; target_id < n_targets; target_id = target_id + 1)
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for (Integer source_id = 0; source_id < n_sources; source_id = source_id + 1)
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vvrg_ie [target_id][source_id] <= False;
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slavePortShim.clear;
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f_reset_rsps.enq (?);
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endrule
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// ================================================================
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// Bus interface for reading/writing control/status regs
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// Relative-address map is same as 'SiFive U54-MC Core Complex Manual v1p0'.
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// Accesses are 4-bytes wide, even though bus may be 64b wide.
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// ----------------------------------------------------------------
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// Handle memory-mapped read requests
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rule rl_process_rd_req (! f_reset_reqs.notEmpty);
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let rda <- get(slavePortShim.master.ar);
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if (cfg_verbosity > 1) begin
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$display ("%0d: PLIC.rl_process_rd_req:", cur_cycle);
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$display (" ", fshow (rda));
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end
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let addr_offset = rda.araddr - rg_addr_base;
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Bit #(64) rdata = 0;
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AXI4_Resp rresp = OKAY;
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if (rda.araddr < rg_addr_base) begin
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// Technically this should not happen: the fabric should
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// never have delivered such an addr to this IP.
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$display ("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", cur_cycle);
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$display (" ", fshow (rda));
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rresp = DECERR;
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end
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// Source Priority
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else if (addr_offset < 'h1000) begin
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Bit #(T_wd_source_id) source_id = truncate (addr_offset [11:2]);
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if ((0 < source_id) && (source_id <= fromInteger (n_sources - 1))) begin
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rdata = changeWidth (vrg_source_prio [source_id]);
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if (cfg_verbosity > 0)
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$display ("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h",
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cur_cycle, source_id, rdata);
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end
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else
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rresp = SLVERR;
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end
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// Source IPs (interrupt pending).
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// Return 32 consecutive IP bits starting with addr.
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else if (('h1000 <= addr_offset) && (addr_offset < 'h2000)) begin
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Bit #(T_wd_source_id) source_id_base = truncate ({ addr_offset [11:0], 5'h0 });
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function Bool fn_ip_source_id (Integer source_id_offset);
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let source_id = source_id_base + fromInteger (source_id_offset);
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Bool ip_source_id = ( (source_id <= fromInteger (n_sources - 1))
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? vrg_source_ip [source_id]
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: False);
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return ip_source_id;
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endfunction
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if (source_id_base <= fromInteger (n_sources - 1)) begin
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Bit #(32) v_ip = pack (genWith (fn_ip_source_id));
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rdata = changeWidth (v_ip);
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if (cfg_verbosity > 0)
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$display ("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h",
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cur_cycle, source_id_base, rdata);
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end
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else
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rresp = SLVERR;
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end
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// Source IEs (interrupt enables) for a target
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// Return 32 consecutive IE bits starting with addr.
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// Target 0 addrs: 2000-207F, Target 1 addrs: 2080-20FF, ...
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else if (('h2000 <= addr_offset) && (addr_offset < 'h3000)) begin
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Bit #(T_wd_target_id) target_id = truncate (addr_offset [11:7]);
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Bit #(T_wd_source_id) source_id_base = truncate ({ addr_offset [6:0], 5'h0 });
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function Bool fn_ie_source_id (Integer source_id_offset);
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let source_id = fromInteger (source_id_offset) + source_id_base;
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return ( (source_id <= fromInteger (n_sources - 1))
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? vvrg_ie [target_id][source_id]
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: False);
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endfunction
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if ( (source_id_base <= fromInteger (n_sources - 1))
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&& (target_id <= fromInteger (n_targets - 1))) begin
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Bit #(32) v_ie = pack (genWith (fn_ie_source_id));
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rdata = changeWidth (v_ie);
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if (cfg_verbosity > 0)
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$display ("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h",
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cur_cycle, source_id_base, rdata);
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end
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else
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rresp = SLVERR;
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end
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// Target threshold
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else if ((addr_offset [31:0] & 32'hFFFF_0FFF) == 32'h0020_0000) begin
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Bit #(T_wd_target_id) target_id = truncate (addr_offset [20:12]);
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if (target_id <= fromInteger (n_targets - 1)) begin
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rdata = changeWidth (vrg_target_threshold [target_id]);
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if (cfg_verbosity > 0)
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$display ("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h",
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cur_cycle, target_id, rdata);
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end
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else
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rresp = SLVERR;
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end
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// Interrupt service claim by target
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else if ((addr_offset [31:0] & 32'hFFFF_0FFF) == 32'h0020_0004) begin
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Bit #(T_wd_target_id) target_id = truncate (addr_offset [20:12]);
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match { .max_prio, .max_id } = fn_target_max_prio_and_max_id (target_id);
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Bool eip = (max_prio > vrg_target_threshold [target_id]);
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if (target_id <= fromInteger (n_targets - 1)) begin
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if (max_id != 0) vrg_source_busy [max_id] <= True; // Set vrg_source_busy even if there was an error.
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if (vrg_servicing_source [target_id] != 0) begin
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$display ("%0d: ERROR: PLIC: target %0d claiming without prior completion",
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cur_cycle, target_id);
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$display (" Still servicing interrupt from source %0d", vrg_servicing_source [target_id]);
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$display (" Trying to claim service for source %0d", max_id);
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$display (" Ignoring.");
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end
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else begin
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if (max_id != 0) begin
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vrg_source_ip [max_id] <= False;
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vrg_servicing_source [target_id] <= truncate (max_id);
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rdata = changeWidth (max_id);
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if (cfg_verbosity > 0)
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$display ("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h",
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cur_cycle, target_id, rdata);
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end
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end
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end
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else
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rresp = SLVERR;
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end
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else
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rresp = SLVERR;
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if (rresp != OKAY) begin
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$display ("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", cur_cycle);
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$display (" ", fshow (rda));
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end
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if ((valueOf (Wd_Data) == 64) && ((addr_offset & 'h7) == 'h4))
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rdata = { rdata [31:0], 32'h0 };
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// Send read-response to bus
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Fabric_Data x = truncate (rdata);
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let rdr = AXI4_RFlit {rid: rda.arid,
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rdata: x,
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rresp: rresp,
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rlast: True,
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ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User
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slavePortShim.master.r.put(rdr);
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if (cfg_verbosity > 1) begin
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$display ("%0d: PLIC.rl_process_rd_req", cur_cycle);
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$display (" ", fshow (rda));
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$display (" ", fshow (rdr));
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end
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endrule: rl_process_rd_req
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// ----------------------------------------------------------------
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// Handle memory-mapped write requests
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(* descending_urgency = "rl_process_rd_req, rl_process_wr_req" *) // Ad hoc order
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rule rl_process_wr_req (! f_reset_reqs.notEmpty);
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let wra <- get(slavePortShim.master.aw);
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let wrd <- get(slavePortShim.master.w);
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if (cfg_verbosity > 1) begin
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$display ("%0d: PLIC.rl_process_wr_req", cur_cycle);
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$display (" ", fshow (wra));
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$display (" ", fshow (wrd));
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end
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let addr_offset = wra.awaddr - rg_addr_base;
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let wdata32 = (((valueOf (Wd_Data) == 64) && ((addr_offset & 'h7) == 'h4))
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? wrd.wdata [63:32]
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: wrd.wdata [31:0]);
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let bresp = OKAY;
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if (wra.awaddr < rg_addr_base) begin
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// Technically this should not happen: the fabric should
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// never have delivered such an addr to this IP.
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$display ("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", cur_cycle);
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$display (" ", fshow (wra));
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$display (" ", fshow (wrd));
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bresp = DECERR;
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end
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// Source priority
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else if (addr_offset < 'h1000) begin
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Bit #(T_wd_source_id) source_id = truncate (addr_offset [11:2]);
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if ((0 < source_id) && (source_id <= fromInteger (n_sources - 1))) begin
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vrg_source_prio [source_id] <= changeWidth (wdata32);
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if (cfg_verbosity > 0)
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$display ("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h",
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cur_cycle, source_id, wdata32);
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end
|
|
else begin
|
|
// Note: write to source_id 0 is error; should it just be ignored?
|
|
bresp = SLVERR;
|
|
end
|
|
end
|
|
|
|
// Source IPs (interrupt pending).
|
|
// Read-only, so ignore write; just check that addr ok.
|
|
else if (('h1000 <= addr_offset) && (addr_offset < 'h2000)) begin
|
|
Bit #(T_wd_source_id) source_id_base = truncate ({ addr_offset [11:0], 5'h0 });
|
|
|
|
if (source_id_base <= fromInteger (n_sources - 1)) begin
|
|
if (cfg_verbosity > 0)
|
|
$display ("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d",
|
|
cur_cycle, source_id_base);
|
|
end
|
|
else
|
|
bresp = SLVERR;
|
|
end
|
|
|
|
// Source IEs (interrupt enables) for a target
|
|
// Write 32 consecutive IE bits starting with addr.
|
|
// Target 0 addrs: 2000-207F, Target 1 addrs: 2080-20FF, ...
|
|
else if (('h2000 <= addr_offset) && (addr_offset < 'h3000)) begin
|
|
Bit #(T_wd_target_id) target_id = truncate (addr_offset [11:7]);
|
|
Bit #(T_wd_source_id) source_id_base = truncate ({ addr_offset [6:0], 5'h0 });
|
|
|
|
if ( (source_id_base <= fromInteger (n_sources - 1))
|
|
&& (target_id <= fromInteger (n_targets - 1))) begin
|
|
for (Bit #(T_wd_source_id) k = 0; k < 32; k = k + 1) begin
|
|
Bit #(T_wd_source_id) source_id = source_id_base + k;
|
|
if (source_id <= fromInteger (n_sources - 1))
|
|
vvrg_ie [target_id][source_id] <= unpack (wdata32 [k]);
|
|
end
|
|
|
|
if (cfg_verbosity > 0)
|
|
$display ("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h",
|
|
cur_cycle, target_id, source_id_base, wdata32);
|
|
end
|
|
else
|
|
bresp = SLVERR;
|
|
end
|
|
|
|
// Target threshold
|
|
else if ((addr_offset [31:0] & 32'hFFFF_0FFF) == 32'h0020_0000) begin
|
|
Bit #(T_wd_target_id) target_id = truncate (addr_offset [20:12]);
|
|
if (target_id <= fromInteger (n_targets - 1)) begin
|
|
vrg_target_threshold [target_id] <= changeWidth (wdata32);
|
|
|
|
if (cfg_verbosity > 0)
|
|
$display ("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h",
|
|
cur_cycle, target_id, wdata32);
|
|
end
|
|
else
|
|
bresp = SLVERR;
|
|
end
|
|
|
|
// Interrupt service completion by target
|
|
// Actual memory-write-data is irrelevant.
|
|
else if ((addr_offset [31:0] & 32'hFFFF_0FFF) == 32'h0020_0004) begin
|
|
Bit #(T_wd_target_id) target_id = truncate (addr_offset [20:12]);
|
|
Bit #(T_wd_source_id) source_id = zeroExtend (vrg_servicing_source [target_id]);
|
|
|
|
if (target_id <= fromInteger (n_targets - 1)) begin
|
|
if (vrg_source_busy [source_id]) begin
|
|
vrg_source_busy [source_id] <= False;
|
|
vrg_servicing_source [target_id] <= 0;
|
|
if (cfg_verbosity > 0)
|
|
$display ("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h",
|
|
cur_cycle, target_id, source_id);
|
|
end
|
|
else begin
|
|
$display ("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced",
|
|
cur_cycle);
|
|
$display (" Completion message from target %0d to source %0d", target_id, source_id);
|
|
$display (" Ignoring");
|
|
end
|
|
end
|
|
else
|
|
bresp = SLVERR;
|
|
end
|
|
|
|
else
|
|
bresp = SLVERR;
|
|
|
|
if (bresp != OKAY) begin
|
|
$display ("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", cur_cycle);
|
|
$display (" ", fshow (wra));
|
|
$display (" ", fshow (wrd));
|
|
end
|
|
|
|
// Send write-response to bus
|
|
let wrr = AXI4_BFlit {bid: wra.awid,
|
|
bresp: bresp,
|
|
buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User
|
|
slavePortShim.master.b.put(wrr);
|
|
|
|
if (cfg_verbosity > 1) begin
|
|
$display ("%0d: PLIC.AXI4.rl_process_wr_req", cur_cycle);
|
|
$display (" ", fshow (wra));
|
|
$display (" ", fshow (wrd));
|
|
$display (" ", fshow (wrr));
|
|
end
|
|
endrule: rl_process_wr_req
|
|
|
|
// ================================================================
|
|
// Creator of each source interface
|
|
|
|
function PLIC_Source_IFC fn_mk_PLIC_Source_IFC (Integer source_id);
|
|
return interface PLIC_Source_IFC;
|
|
method Action m_interrupt_req (Bool set_not_clear);
|
|
action
|
|
if (! vrg_source_busy [source_id + 1]) begin
|
|
vrg_source_ip [source_id + 1] <= set_not_clear;
|
|
|
|
if ((cfg_verbosity > 0) && (vrg_source_ip [source_id + 1] != set_not_clear))
|
|
$display ("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
|
|
cur_cycle, source_id + 1, pack (set_not_clear));
|
|
end
|
|
endaction
|
|
endmethod
|
|
endinterface;
|
|
endfunction
|
|
|
|
// ================================================================
|
|
// Creator of each target interface
|
|
|
|
function PLIC_Target_IFC fn_mk_PLIC_Target_IFC (Integer target_id);
|
|
return interface PLIC_Target_IFC;
|
|
method Bool m_eip; // external interrupt pending
|
|
match { .max_prio, .max_id } = fn_target_max_prio_and_max_id (fromInteger (target_id));
|
|
Bool eip = (max_prio > vrg_target_threshold [target_id]);
|
|
return eip;
|
|
endmethod
|
|
endinterface;
|
|
endfunction
|
|
|
|
// ================================================================
|
|
// INTERFACE
|
|
|
|
// Debugging
|
|
method Action set_verbosity (Bit #(4) verbosity);
|
|
cfg_verbosity <= verbosity;
|
|
endmethod
|
|
|
|
method Action show_PLIC_state;
|
|
fa_show_PLIC_state;
|
|
endmethod
|
|
|
|
// Reset
|
|
interface server_reset = toGPServer (f_reset_reqs, f_reset_rsps);
|
|
|
|
// set_addr_map should be called after this module's reset
|
|
method Action set_addr_map (Bit #(64) addr_base, Bit #(64) addr_lim);
|
|
if (addr_base [1:0] != 0)
|
|
$display ("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
|
|
cur_cycle, addr_base);
|
|
|
|
if (addr_lim [1:0] != 0)
|
|
$display ("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
|
|
cur_cycle, addr_lim);
|
|
|
|
rg_addr_base <= addr_base;
|
|
rg_addr_lim <= addr_lim;
|
|
|
|
if (cfg_verbosity > 0)
|
|
$display ("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", cur_cycle, addr_base, addr_lim);
|
|
endmethod
|
|
|
|
// Memory-mapped access
|
|
interface axi4_slave = slavePortShim.slave;
|
|
|
|
// sources
|
|
interface v_sources = genWith (fn_mk_PLIC_Source_IFC);
|
|
|
|
// targets
|
|
interface v_targets = genWith (fn_mk_PLIC_Target_IFC);
|
|
endmodule
|
|
|
|
// ================================================================
|
|
|
|
endpackage
|