4960a59da0
After a test, GDB can write DCSR to restore to Machine privilege, write to PC (DPC) to restore boot value, write MSTATUS to restore to initial value, then can load and run next test.
107 lines
3.2 KiB
Plaintext
107 lines
3.2 KiB
Plaintext
// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved
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package Proc_IFC;
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// ================================================================
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// BSV library imports
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import Vector :: *;
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import GetPut :: *;
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import ClientServer :: *;
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// ================================================================
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// Project imports
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import ISA_Decls :: *;
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import AXI4_Types :: *;
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import Fabric_Defs :: *;
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`ifdef INCLUDE_GDB_CONTROL
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import DM_CPU_Req_Rsp :: *;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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import ProcTypes :: *;
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import Trace_Data2 :: *;
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`endif
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// ================================================================
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// CPU interface
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// Note: this Proc_IFC is similar, but not identical to CPU_IFC for Piccolo and Flute
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// Specifically, it removes interfaces for software and timer,
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// because the RISCY-OOO mkProc contains those elements.
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interface Proc_IFC;
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// Init
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interface Server #(Token, Token) init_server;
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// ----------------
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// Start the cores running
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method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr);
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// ----------------
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// SoC fabric connections
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// Fabric master interface for memory (from LLC)
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interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master0;
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// Fabric master interface for IO (from MMIOPlatform)
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interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master1;
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// ----------------
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// External interrupts
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(* always_ready, always_enabled *)
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method Action m_external_interrupt_req (Bool set_not_clear);
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(* always_ready, always_enabled *)
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method Action s_external_interrupt_req (Bool set_not_clear);
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// ----------------
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// Non-maskable interrupt
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(* always_ready, always_enabled *)
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method Action non_maskable_interrupt_req (Bool set_not_clear);
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// ----------------
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// Set core's verbosity
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method Action set_verbosity (Bit #(4) verbosity);
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// ----------------
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// Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory)
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interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) debug_module_mem_server;
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// ----------------
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// Optional interface to Debug Module
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`ifdef INCLUDE_GDB_CONTROL
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interface Server #(Bool, Bool) hart0_run_halt_server;
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interface Server #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN)) hart0_gpr_mem_server;
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`ifdef ISA_F
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interface Server #(DM_CPU_Req #(5, FLEN), DM_CPU_Rsp #(FLEN)) hart0_fpr_mem_server;
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`endif
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interface Server #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN)) hart0_csr_mem_server;
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// Non-standard
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interface Put #(Bit #(4)) hart0_put_other_req;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// Note: this is a SupSize vector of streams of Trace_Data2 structs,
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// each of which has a serialnum field. Each of the SupSize
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// streams has serialnums in increasing order. Each serialnum
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// appears exactly once in exactly one of the streams. Thus, the
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// channels can easily be merged into a single program-order stream.
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interface Vector #(SupSize, Get #(Trace_Data2)) v_to_TV;
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`endif
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endinterface
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// ================================================================
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endpackage
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