4960a59da0
After a test, GDB can write DCSR to restore to Machine privilege, write to PC (DPC) to restore boot value, write MSTATUS to restore to initial value, then can load and run next test.
503 lines
16 KiB
Plaintext
503 lines
16 KiB
Plaintext
// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved.
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package CoreW;
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// ================================================================
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// This package is called 'CoreW' for 'Core Wrapper'
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// and corresponds to 'Core' in Piccolo and Flute.
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//
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// Here in Toooba, we use the name 'CoreW' to avoid a name-clash with
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// an inner module called 'Core' in MIT's RISCY-OOO.
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//
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// The specific correspondence with Piccolo/Flute structure is:
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// Piccolo/Flute Toooba
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// mkCore mkCoreW
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// mkProc
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// mkCPU mkCore
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// This package defines:
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// Core_IFC
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// mkCore #(Core_IFC)
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// mkFabric_2x3 -- specialized AXI4 fabric used inside this core
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//
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// mkCoreW instantiates:
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// - mkProc (the RISC-V CPU, a version of MIT's RISCY-OOO)
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// - mkFabric_2x3
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// - mkPLIC_16_2_7
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// - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF)
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// - mkDebug_Module (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL)
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// and connects them all up.
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// ================================================================
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// BSV library imports
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import Vector :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Connectable :: *;
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import Clocks :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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// ================================================================
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// Project imports
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// ----------------
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// From RISCY-ooo
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import ProcTypes :: *;
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// ----------------
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// From Toooba
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// Main fabric
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import AXI4_Types :: *;
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import AXI4_Fabric :: *;
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import Fabric_Defs :: *; // for Wd_Id, Wd_Addr, Wd_Data, Wd_User
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import SoC_Map :: *;
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`ifdef INCLUDE_GDB_CONTROL
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import Debug_Module :: *;
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`endif
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import CoreW_IFC :: *;
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import PLIC :: *;
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import PLIC_16_2_7 :: *;
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import Proc_IFC :: *;
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import Proc :: *;
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`ifdef INCLUDE_TANDEM_VERIF
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import TV_Info :: *;
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import Trace_Data2 :: *;
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import TV_Encode :: *;
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import Trace_Data2_to_Trace_Data :: *;
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`endif
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// TV_Taps needed when both GDB_CONTROL and TANDEM_VERIF are present
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`ifdef INCLUDE_GDB_CONTROL
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`ifdef INCLUDE_TANDEM_VERIF
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import TV_Taps :: *;
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`endif
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`endif
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import DM_CPU_Req_Rsp ::*;
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// ================================================================
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// The Core module
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(* synthesize *)
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module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources));
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// ================================================================
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// STATE
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// System address map
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SoC_Map_IFC soc_map <- mkSoC_Map;
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// RISCY-OOO processor
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Proc_IFC proc <- mkProc;
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// A 2x3 fabric for connecting {CPU, Debug_Module} to {Fabric, PLIC}
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Fabric_2x3_IFC fabric_2x3 <- mkFabric_2x3;
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// PLIC (Platform-Level Interrupt Controller)
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PLIC_IFC_16_2_7 plic <- mkPLIC_16_2_7;
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// Reset requests from SoC and responses to SoC
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FIFOF #(Bit #(0)) f_reset_reqs <- mkFIFOF;
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FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF;
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`ifdef INCLUDE_GDB_CONTROL
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// Debug Module
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Debug_Module_IFC debug_module <- mkDebug_Module;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// The following are a superscalar-wide set of transformers from RISCY-OOO output Trace_Data2
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// to Trace_Data which is input to the TV encoder
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Vector #(SupSize, Trace_Data2_to_Trace_Data_IFC) v_td2_to_td <- replicateM (mkTrace_Data2_to_Trace_Data);
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// The TV encoder transforms Trace_Data structures from the CPU and DM
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// into encoded byte vectors for transmission to the Tandem Verifier
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TV_Encode_IFC tv_encode <- mkTV_Encode;
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`endif
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// HTIF locations (for debugging only)
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Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0);
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Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0);
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// ================================================================
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// RESET
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// There are two sources of reset requests to the CPU: externally
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// from the SoC and, optionally, the DM. The SoC requires a
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// response, the DM does not. When both requestors are present
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// (i.e., DM is present), we merge the reset requests into the CPU,
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// and we remember which one was the requestor in
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// f_reset_requestor, so that we know whether or not to respond to
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// the SoC.
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// TODO (multicore): currently the incoming 'init' token is from
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// Debug Module's hart0_get_reset_req, but when we call
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// proc.init_server here, we are resetting all the cores, i.e., all
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// the harts. Needs to be cleaned up.
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Bit #(1) reset_requestor_dm = 0;
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Bit #(1) reset_requestor_soc = 1;
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`ifdef INCLUDE_GDB_CONTROL
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FIFOF #(Bit #(1)) f_reset_requestor <- mkFIFOF;
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`endif
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// Reset-hart0 request from SoC
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rule rl_cpu_hart0_reset_from_soc_start;
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let req <- pop (f_reset_reqs);
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proc.init_server.request.put (?); // CPU
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plic.server_reset.request.put (?); // PLIC
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fabric_2x3.reset; // Local 2x3 Fabric
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`ifdef INCLUDE_TANDEM_VERIF
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tv_encode.reset;
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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// Remember the requestor, so we can respond to it
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f_reset_requestor.enq (reset_requestor_soc);
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`endif
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$display ("%0d: Core.rl_cpu_hart0_reset_from_soc_start (requestor %0d)", cur_cycle, reset_requestor_soc);
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endrule
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`ifdef INCLUDE_GDB_CONTROL
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// Reset-hart0 from Debug Module
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rule rl_cpu_hart0_reset_from_dm_start;
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let req <- debug_module.hart0_get_reset_req.get;
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proc.init_server.request.put (?); // CPU
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plic.server_reset.request.put (?); // PLIC
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fabric_2x3.reset; // Local 2x3 fabric
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`ifdef INCLUDE_TANDEM_VERIF
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tv_encode.reset;
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`endif
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// Remember the requestor, so we can respond to it
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f_reset_requestor.enq (reset_requestor_dm);
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$display ("%0d: Core.rl_cpu_hart0_reset_from_dm_start (requestor %0d)", cur_cycle, reset_requestor_dm);
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endrule
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`endif
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FIFOF #(Bit #(0)) f_proc_start <- mkFIFOF;
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rule rl_cpu_hart0_reset_complete;
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let rsp1 <- proc.init_server.response.get; // CPU
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let rsp3 <- plic.server_reset.response.get; // PLIC
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plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_base),
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zeroExtend (soc_map.m_plic_addr_lim));
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Bit #(1) requestor = reset_requestor_soc;
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`ifdef INCLUDE_GDB_CONTROL
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requestor <- pop (f_reset_requestor);
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`endif
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if (requestor == reset_requestor_soc)
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f_reset_rsps.enq (?);
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// Start running the cores
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f_proc_start.enq (?);
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$display ("%0d: Core.rl_cpu_hart0_reset_complete; starting proc", cur_cycle);
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endrule
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rule rl_cpu_hart0_reset_proc_start;
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let x <- pop (f_proc_start);
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proc.start (soc_map_struct.pc_reset_value,
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rg_tohost_addr,
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rg_fromhost_addr);
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$display ("%0d: Core.rl_cpu_hart0_reset_proc_start; started running proc", cur_cycle);
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endrule
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`ifdef INCLUDE_GDB_CONTROL
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// ================================================================
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// Direct DM-to-CPU connections for run-control and other misc requests
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mkConnection (debug_module.hart0_client_run_halt, proc.hart0_run_halt_server);
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mkConnection (debug_module.hart0_get_other_req, proc.hart0_put_other_req);
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// ================================================================
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// Direct CPU-to-TV connections for TV trace data
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for (Integer j = 0; j < valueOf (SupSize); j = j + 1) begin
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// CPU Trace_Data2 output streams to Trace_Data2_to_Trace_Data converters
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mkConnection (proc.v_to_TV [j], v_td2_to_td [j].in);
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// Trace_Data2_to_Trace_Data converters to TV encoder
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mkConnection (v_td2_to_td [j].out, tv_encode.v_cpu_in [j]);
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end
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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`ifdef INCLUDE_TANDEM_VERIF
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// ================================================================
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// BEGIN SECTION: DM and TV both present
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// We instantiate 'taps' into connections where DM writes CPU GPRs,
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// FPRs, CSRs, and main memory. The tap outputs go the TV encoder,
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// to keep the tandem verifier in sync with DM updates to the CPU.
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// Create a tap for DM's memory-writes to the bus, and merge-in the trace data.
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DM_Mem_Tap_IFC dm_mem_tap <- mkDM_Mem_Tap;
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mkConnection (debug_module.master, dm_mem_tap.slave);
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let dm_master_local = dm_mem_tap.master;
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rule rl_merge_dm_mem_trace_data;
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let tmp <- dm_mem_tap.trace_data_out.get;
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tv_encode.dm_in.put (tmp);
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endrule
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// Create a tap for DM's GPR writes to the CPU, and merge-in the trace data.
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DM_GPR_Tap_IFC dm_gpr_tap_ifc <- mkDM_GPR_Tap;
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mkConnection (debug_module.hart0_gpr_mem_client, dm_gpr_tap_ifc.server);
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mkConnection (dm_gpr_tap_ifc.client, proc.hart0_gpr_mem_server);
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rule rl_merge_dm_gpr_trace_data;
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let tmp <- dm_gpr_tap_ifc.trace_data_out.get;
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tv_encode.dm_in.put (tmp);
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endrule
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`ifdef ISA_F_OR_D
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// Create a tap for DM's FPR writes to the CPU, and merge-in the trace data.
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DM_FPR_Tap_IFC dm_fpr_tap_ifc <- mkDM_FPR_Tap;
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mkConnection (debug_module.hart0_fpr_mem_client, dm_fpr_tap_ifc.server);
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mkConnection (dm_fpr_tap_ifc.client, proc.hart0_fpr_mem_server);
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rule rl_merge_dm_fpr_trace_data;
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let tmp <- dm_fpr_tap_ifc.trace_data_out.get;
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tv_encode.dm_in.put (tmp);
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endrule
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`endif
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// for ifdef ISA_F_OR_D
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// Create a tap for DM's CSR writes, and merge-in the trace data.
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DM_CSR_Tap_IFC dm_csr_tap <- mkDM_CSR_Tap;
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mkConnection(debug_module.hart0_csr_mem_client, dm_csr_tap.server);
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mkConnection(dm_csr_tap.client, proc.hart0_csr_mem_server);
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rule rl_merge_dm_csr_trace_data;
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let tmp <- dm_csr_tap.trace_data_out.get;
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tv_encode.dm_in.put(tmp);
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endrule
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`ifdef ISA_F_OR_D
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(* descending_urgency = "rl_merge_dm_fpr_trace_data, rl_merge_dm_gpr_trace_data" *)
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`endif
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(* descending_urgency = "rl_merge_dm_gpr_trace_data, rl_merge_dm_csr_trace_data" *)
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(* descending_urgency = "rl_merge_dm_csr_trace_data, rl_merge_dm_mem_trace_data" *)
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rule rl_bogus_for_sched_attributes;
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endrule
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// END SECTION: DM and TV
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// ================================================================
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`else // of ifdef INCLUDE_TANDEM_VERIF
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// ================================================================
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// BEGIN SECTION: DM, no TV
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// Connect DM's GPR interface directly to CPU
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mkConnection (debug_module.hart0_gpr_mem_client, proc.hart0_gpr_mem_server);
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`ifdef ISA_F_OR_D
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// Connect DM's FPR interface directly to CPU
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mkConnection (debug_module.hart0_fpr_mem_client, proc.hart0_fpr_mem_server);
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`endif
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// Connect DM's CSR interface directly to CPU
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mkConnection (debug_module.hart0_csr_mem_client, proc.hart0_csr_mem_server);
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// DM's bus master is directly the bus master
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let dm_master_local = debug_module.master;
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// END SECTION: DM, no TV
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// ================================================================
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`endif // for ifdef INCLUDE_TANDEM_VERIF
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// ================================================================
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`else // for ifdef INCLUDE_GDB_CONTROL
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// ================================================================
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// BEGIN SECTION: no DM
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// No DM, so 'DM bus master' is AXI4 dummy
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AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User)
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dm_master_local = dummy_AXI4_Master_ifc;
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`endif // for ifdef INCLUDE_GDB_CONTROL
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// ================================================================
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// Connect the local 2x3 fabric
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// Masters on the local 2x3 fabric
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mkConnection (proc.master1, fabric_2x3.v_from_masters [cpu_dmem_master_num]);
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mkConnection (dm_master_local, fabric_2x3.v_from_masters [debug_module_sba_master_num]);
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// Slaves on the local 2x3 fabric
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// Two of the slaves are connected here.
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// The third slave (default slave) is taken out directly to the Core interface
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mkConnection (fabric_2x3.v_to_slaves [plic_slave_num], plic.axi4_slave);
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mkConnection (fabric_2x3.v_to_slaves [llc_slave_num], proc.debug_module_mem_server);
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// ================================================================
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// Connect external interrupt lines from PLIC to CPU
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rule rl_relay_external_interrupts; // from PLIC
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Bool meip = plic.v_targets [0].m_eip;
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proc.m_external_interrupt_req (meip);
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Bool seip = plic.v_targets [1].m_eip;
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proc.s_external_interrupt_req (seip);
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// $display ("%0d: Core.rl_relay_external_interrupts: relaying: %d", cur_cycle, pack (x));
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endrule
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// TODO: fixup. Need to combine NMIs from multiple sources (cache, fabric, devices, ...)
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rule rl_relay_non_maskable_interrupt;
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proc.non_maskable_interrupt_req (False);
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// $display ("%0d: Core.rl_relay_non_maskable_interrupts: relaying: %d", cur_cycle, pack (x));
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endrule
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// ================================================================
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// INTERFACE
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// ----------------------------------------------------------------
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// Debugging: set core's verbosity, htif addrs
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method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);
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// Warning: ignoring logdelay
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proc.set_verbosity (verbosity);
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endmethod
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method Action set_htif_addrs (Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
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rg_tohost_addr <= tohost_addr;
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rg_fromhost_addr <= fromhost_addr;
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endmethod
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// ----------------------------------------------------------------
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// Soft reset
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interface Server cpu_reset_server = toGPServer (f_reset_reqs, f_reset_rsps);
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// ----------------------------------------------------------------
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// AXI4 Fabric interfaces
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// IMem to Fabric master interface
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interface AXI4_Master_IFC cpu_imem_master = proc.master0;
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// DMem to Fabric master interface
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interface AXI4_Master_IFC cpu_dmem_master = fabric_2x3.v_to_slaves [default_slave_num];
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// ----------------------------------------------------------------
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// External interrupt sources
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interface core_external_interrupt_sources = plic.v_sources;
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`ifdef INCLUDE_GDB_CONTROL
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// ----------------------------------------------------------------
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// Optional DM interfaces
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// ----------------
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// DMI (Debug Module Interface) facing remote debugger
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interface DMI dm_dmi = debug_module.dmi;
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// ----------------
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// Facing Platform
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// Non-Debug-Module Reset (reset all except DM)
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interface Get dm_ndm_reset_req_get = debug_module.get_ndm_reset_req;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// ----------------------------------------------------------------
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// Optional TV interface
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interface Get tv_verifier_info_get;
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method ActionValue #(Info_CPU_to_Verifier) get();
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match { .n, .v } <- tv_encode.out.get;
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return (Info_CPU_to_Verifier { num_bytes: n, vec_bytes: v });
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endmethod
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endinterface
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`endif
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endmodule: mkCoreW
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// ================================================================
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// 2x3 Fabric for this Core
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// Masters: CPU DMem, Debug Module System Bus Access, External access
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// ----------------
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// Fabric port numbers for masters
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typedef 2 Num_Masters_2x3;
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typedef Bit #(TLog #(Num_Masters_2x3)) Master_Num_2x3;
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Master_Num_2x3 cpu_dmem_master_num = 0;
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Master_Num_2x3 debug_module_sba_master_num = 1;
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// ----------------
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// Fabric port numbers for slaves
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typedef 3 Num_Slaves_2x3;
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typedef Bit #(TLog #(Num_Slaves_2x3)) Slave_Num_2x3;
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Slave_Num_2x3 default_slave_num = 0; // for I/O, uncached memory, etc.
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Slave_Num_2x3 plic_slave_num = 1; // PLIC mem-mapped registers
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Slave_Num_2x3 llc_slave_num = 2; // Normal cached memory (connects to coherent Last-Level Cache)
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// ----------------
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// Specialization of parameterized AXI4 fabric for 2x3 Core fabric
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typedef AXI4_Fabric_IFC #(Num_Masters_2x3,
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Num_Slaves_2x3,
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Wd_Id,
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Wd_Addr,
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Wd_Data,
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Wd_User) Fabric_2x3_IFC;
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// ----------------
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(* synthesize *)
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module mkFabric_2x3 (Fabric_2x3_IFC);
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// System address map
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SoC_Map_IFC soc_map <- mkSoC_Map;
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// ----------------
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// Slave address decoder
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// Any addr is legal, and there is only one slave to service it.
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function Tuple2 #(Bool, Slave_Num_2x3) fn_addr_to_slave_num_2x3 (Fabric_Addr addr);
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if ( (soc_map.m_mem0_controller_addr_base <= addr)
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&& (addr < soc_map.m_mem0_controller_addr_lim))
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return tuple2 (True, llc_slave_num);
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else if ( (soc_map.m_plic_addr_base <= addr)
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&& (addr < soc_map.m_plic_addr_lim))
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return tuple2 (True, plic_slave_num);
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else
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return tuple2 (True, default_slave_num);
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endfunction
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AXI4_Fabric_IFC #(Num_Masters_2x3, Num_Slaves_2x3, Wd_Id, Wd_Addr, Wd_Data, Wd_User)
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fabric <- mkAXI4_Fabric (fn_addr_to_slave_num_2x3);
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return fabric;
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endmodule: mkFabric_2x3
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// ================================================================
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endpackage
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