687 lines
21 KiB
Verilog
687 lines
21 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Wed Jun 24 20:21:04 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1 reg
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// first O 230
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// RDY_first O 1 reg
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 230
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_deq I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// Combinational paths from inputs to outputs:
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// (specUpdate_incorrectSpeculation_kill_all,
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// specUpdate_incorrectSpeculation_kill_tag,
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// EN_deq,
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// EN_specUpdate_incorrectSpeculation) -> RDY_enq
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkAluDispToRegFifo(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first,
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RDY_first,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [229 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first
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output [229 : 0] first;
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output RDY_first;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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wire [229 : 0] first;
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wire RDY_deq,
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RDY_enq,
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RDY_first,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation;
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// inlined wires
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wire [11 : 0] m_m_specBits_0_lat_1$wget;
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wire m_m_valid_0_lat_0$whas;
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// register m_m_row_0
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reg [217 : 0] m_m_row_0;
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wire [217 : 0] m_m_row_0$D_IN;
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wire m_m_row_0$EN;
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// register m_m_specBits_0_rl
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reg [11 : 0] m_m_specBits_0_rl;
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wire [11 : 0] m_m_specBits_0_rl$D_IN;
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wire m_m_specBits_0_rl$EN;
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// register m_m_valid_0_rl
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reg m_m_valid_0_rl;
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wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_m_specBits_0_canon,
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CAN_FIRE_RL_m_m_valid_0_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_RL_m_m_specBits_0_canon,
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WILL_FIRE_RL_m_m_valid_0_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation;
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// inputs to muxes for submodule ports
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wire MUX_m_m_valid_0_lat_0$wset_1__SEL_1;
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// remaining internal signals
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reg [29 : 0] CASE_enq_x_BITS_224_TO_222_0_enq_x_BITS_224_TO_ETC__q4,
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CASE_m_m_row_0_BITS_212_TO_210_0_m_m_row_0_BIT_ETC__q11;
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reg [11 : 0] CASE_enq_x_BITS_136_TO_125_1_enq_x_BITS_136_TO_ETC__q6,
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CASE_m_m_row_0_BITS_124_TO_113_1_m_m_row_0_BIT_ETC__q13;
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reg [10 : 0] CASE_enq_x_BITS_194_TO_193_0_enq_x_BITS_194_TO_ETC__q5,
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CASE_m_m_row_0_BITS_182_TO_181_0_m_m_row_0_BIT_ETC__q12;
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reg [4 : 0] CASE_enq_x_BITS_123_TO_119_0_enq_x_BITS_123_TO_ETC__q7,
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CASE_m_m_row_0_BITS_111_TO_107_0_m_m_row_0_BIT_ETC__q14;
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reg [3 : 0] CASE_IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq__ETC__q2,
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CASE_IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_4_ETC__q9,
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IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69,
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352;
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reg [2 : 0] CASE_IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq__ETC__q1,
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CASE_IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_7_ETC__q8,
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CASE_enq_x_BITS_198_TO_196_0_enq_x_BITS_198_TO_ETC__q3,
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CASE_m_m_row_0_BITS_186_TO_184_0_m_m_row_0_BIT_ETC__q10,
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IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq_x_BIT_ETC___d98,
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IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_78_OR__ETC___d381;
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wire [11 : 0] sb__h11973, upd__h1154;
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wire [8 : 0] IF_enq_x_BITS_192_TO_189_8_EQ_0_9_OR_NOT_enq_x_ETC___d143,
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IF_enq_x_BITS_192_TO_189_8_EQ_1_0_OR_NOT_enq_x_ETC___d142,
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IF_enq_x_BITS_192_TO_189_8_EQ_2_2_OR_NOT_enq_x_ETC___d141,
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_0_32_OR__ETC___d425,
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_1_33_OR__ETC___d424,
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_2_35_OR__ETC___d423;
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wire IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6;
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// action method enq
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assign RDY_enq = m_m_valid_0_lat_0$whas ? !1'd0 : !m_m_valid_0_rl ;
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assign CAN_FIRE_enq = m_m_valid_0_lat_0$whas ? !1'd0 : !m_m_valid_0_rl ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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assign RDY_deq = m_m_valid_0_rl ;
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assign CAN_FIRE_deq = m_m_valid_0_rl ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first
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assign first =
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{ m_m_row_0[217:213],
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CASE_m_m_row_0_BITS_212_TO_210_0_m_m_row_0_BIT_ETC__q11,
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CASE_m_m_row_0_BITS_182_TO_181_0_m_m_row_0_BIT_ETC__q12,
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m_m_row_0[171:125],
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CASE_m_m_row_0_BITS_124_TO_113_1_m_m_row_0_BIT_ETC__q13,
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m_m_row_0[112],
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CASE_m_m_row_0_BITS_111_TO_107_0_m_m_row_0_BIT_ETC__q14,
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m_m_row_0[106:0],
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m_m_specBits_0_rl } ;
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assign RDY_first = m_m_valid_0_rl ;
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// action method specUpdate_incorrectSpeculation
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assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_incorrectSpeculation =
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EN_specUpdate_incorrectSpeculation ;
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// action method specUpdate_correctSpeculation
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assign RDY_specUpdate_correctSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_correctSpeculation =
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EN_specUpdate_correctSpeculation ;
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// rule RL_m_m_valid_0_canon
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assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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// rule RL_m_m_specBits_0_canon
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assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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// inputs to muxes for submodule ports
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assign MUX_m_m_valid_0_lat_0$wset_1__SEL_1 =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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m_m_specBits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
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// inlined wires
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assign m_m_valid_0_lat_0$whas =
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MUX_m_m_valid_0_lat_0$wset_1__SEL_1 || EN_deq ;
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assign m_m_specBits_0_lat_1$wget =
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sb__h11973 & specUpdate_correctSpeculation_mask ;
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// register m_m_row_0
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assign m_m_row_0$D_IN =
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{ enq_x[229:225],
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CASE_enq_x_BITS_224_TO_222_0_enq_x_BITS_224_TO_ETC__q4,
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CASE_enq_x_BITS_194_TO_193_0_enq_x_BITS_194_TO_ETC__q5,
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enq_x[183:137],
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CASE_enq_x_BITS_136_TO_125_1_enq_x_BITS_136_TO_ETC__q6,
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enq_x[124],
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CASE_enq_x_BITS_123_TO_119_0_enq_x_BITS_123_TO_ETC__q7,
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enq_x[118:12] } ;
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assign m_m_row_0$EN = EN_enq ;
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// register m_m_specBits_0_rl
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assign m_m_specBits_0_rl$D_IN =
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EN_specUpdate_correctSpeculation ? upd__h1154 : sb__h11973 ;
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assign m_m_specBits_0_rl$EN = 1'd1 ;
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// register m_m_valid_0_rl
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assign m_m_valid_0_rl$D_IN =
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EN_enq ||
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IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 ;
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assign m_m_valid_0_rl$EN = 1'd1 ;
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// remaining internal signals
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assign IF_enq_x_BITS_192_TO_189_8_EQ_0_9_OR_NOT_enq_x_ETC___d143 =
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(enq_x[192:189] == 4'd0 ||
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enq_x[192:189] != 4'd1 && enq_x[192:189] != 4'd2 &&
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enq_x[192:189] != 4'd3 &&
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enq_x[192:189] != 4'd4 &&
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enq_x[192:189] != 4'd5 &&
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IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69 ==
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4'd0) ?
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{ 4'd0, enq_x[188:184] } :
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IF_enq_x_BITS_192_TO_189_8_EQ_1_0_OR_NOT_enq_x_ETC___d142 ;
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assign IF_enq_x_BITS_192_TO_189_8_EQ_1_0_OR_NOT_enq_x_ETC___d142 =
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(enq_x[192:189] == 4'd1 ||
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enq_x[192:189] != 4'd2 && enq_x[192:189] != 4'd3 &&
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enq_x[192:189] != 4'd4 &&
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enq_x[192:189] != 4'd5 &&
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IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69 ==
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4'd1) ?
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{ 4'd1, enq_x[188:184] } :
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IF_enq_x_BITS_192_TO_189_8_EQ_2_2_OR_NOT_enq_x_ETC___d141 ;
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assign IF_enq_x_BITS_192_TO_189_8_EQ_2_2_OR_NOT_enq_x_ETC___d141 =
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(enq_x[192:189] == 4'd2 ||
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enq_x[192:189] != 4'd3 && enq_x[192:189] != 4'd4 &&
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enq_x[192:189] != 4'd5 &&
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IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69 ==
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4'd2) ?
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{ 4'd2,
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(enq_x[188:186] == 3'd0 ||
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enq_x[188:186] != 3'd1 &&
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IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq_x_BIT_ETC___d98 ==
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3'd0) ?
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{ 3'd0, enq_x[185:184] } :
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((enq_x[188:186] == 3'd1 ||
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IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq_x_BIT_ETC___d98 ==
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3'd1) ?
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{ 3'd1, enq_x[185:184] } :
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{ CASE_IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq__ETC__q1,
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2'h2 }) } :
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((enq_x[192:189] == 4'd3 ||
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enq_x[192:189] != 4'd4 && enq_x[192:189] != 4'd5 &&
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IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69 ==
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4'd3) ?
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{ 4'd3, enq_x[188:184] } :
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((enq_x[192:189] == 4'd4 ||
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enq_x[192:189] != 4'd5 &&
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IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69 ==
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4'd4) ?
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9'd138 :
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((enq_x[192:189] == 4'd5 ||
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IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69 ==
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4'd5) ?
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{ 4'd5, enq_x[188:184] } :
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{ CASE_IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq__ETC__q2,
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5'h0A }))) ;
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assign IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_0_32_OR__ETC___d425 =
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(m_m_row_0[180:177] == 4'd0 ||
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m_m_row_0[180:177] != 4'd1 && m_m_row_0[180:177] != 4'd2 &&
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m_m_row_0[180:177] != 4'd3 &&
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m_m_row_0[180:177] != 4'd4 &&
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m_m_row_0[180:177] != 4'd5 &&
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352 ==
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4'd0) ?
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{ 4'd0, m_m_row_0[176:172] } :
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_1_33_OR__ETC___d424 ;
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assign IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_1_33_OR__ETC___d424 =
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(m_m_row_0[180:177] == 4'd1 ||
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m_m_row_0[180:177] != 4'd2 && m_m_row_0[180:177] != 4'd3 &&
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m_m_row_0[180:177] != 4'd4 &&
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m_m_row_0[180:177] != 4'd5 &&
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352 ==
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4'd1) ?
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{ 4'd1, m_m_row_0[176:172] } :
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_2_35_OR__ETC___d423 ;
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assign IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_2_35_OR__ETC___d423 =
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(m_m_row_0[180:177] == 4'd2 ||
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m_m_row_0[180:177] != 4'd3 && m_m_row_0[180:177] != 4'd4 &&
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m_m_row_0[180:177] != 4'd5 &&
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352 ==
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4'd2) ?
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{ 4'd2,
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(m_m_row_0[176:174] == 3'd0 ||
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m_m_row_0[176:174] != 3'd1 &&
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IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_78_OR__ETC___d381 ==
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3'd0) ?
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{ 3'd0, m_m_row_0[173:172] } :
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((m_m_row_0[176:174] == 3'd1 ||
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IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_78_OR__ETC___d381 ==
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3'd1) ?
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{ 3'd1, m_m_row_0[173:172] } :
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{ CASE_IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_7_ETC__q8,
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2'h2 }) } :
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((m_m_row_0[180:177] == 4'd3 ||
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m_m_row_0[180:177] != 4'd4 && m_m_row_0[180:177] != 4'd5 &&
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352 ==
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4'd3) ?
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{ 4'd3, m_m_row_0[176:172] } :
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((m_m_row_0[180:177] == 4'd4 ||
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m_m_row_0[180:177] != 4'd5 &&
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352 ==
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4'd4) ?
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9'd138 :
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((m_m_row_0[180:177] == 4'd5 ||
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IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352 ==
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4'd5) ?
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{ 4'd5, m_m_row_0[176:172] } :
|
|
{ CASE_IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_4_ETC__q9,
|
|
5'h0A }))) ;
|
|
assign IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 =
|
|
m_m_valid_0_lat_0$whas ? 1'd0 : m_m_valid_0_rl ;
|
|
assign sb__h11973 = EN_enq ? enq_x[11:0] : m_m_specBits_0_rl ;
|
|
assign upd__h1154 = m_m_specBits_0_lat_1$wget ;
|
|
always@(enq_x)
|
|
begin
|
|
case (enq_x[192:189])
|
|
4'd6, 4'd7, 4'd8, 4'd9, 4'd10:
|
|
IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69 =
|
|
enq_x[192:189];
|
|
default: IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69 =
|
|
4'd11;
|
|
endcase
|
|
end
|
|
always@(enq_x)
|
|
begin
|
|
case (enq_x[188:186])
|
|
3'd2, 3'd3:
|
|
IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq_x_BIT_ETC___d98 =
|
|
enq_x[188:186];
|
|
default: IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq_x_BIT_ETC___d98 =
|
|
3'd4;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[180:177])
|
|
4'd6, 4'd7, 4'd8, 4'd9, 4'd10:
|
|
IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352 =
|
|
m_m_row_0[180:177];
|
|
default: IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352 =
|
|
4'd11;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[176:174])
|
|
3'd2, 3'd3:
|
|
IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_78_OR__ETC___d381 =
|
|
m_m_row_0[176:174];
|
|
default: IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_78_OR__ETC___d381 =
|
|
3'd4;
|
|
endcase
|
|
end
|
|
always@(IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq_x_BIT_ETC___d98)
|
|
begin
|
|
case (IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq_x_BIT_ETC___d98)
|
|
3'd2, 3'd3:
|
|
CASE_IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq__ETC__q1 =
|
|
IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq_x_BIT_ETC___d98;
|
|
default: CASE_IF_enq_x_BITS_188_TO_186_1_EQ_2_5_OR_enq__ETC__q1 = 3'd4;
|
|
endcase
|
|
end
|
|
always@(IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69)
|
|
begin
|
|
case (IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69)
|
|
4'd6, 4'd7, 4'd8, 4'd9, 4'd10:
|
|
CASE_IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq__ETC__q2 =
|
|
IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq_x_BIT_ETC___d69;
|
|
default: CASE_IF_enq_x_BITS_192_TO_189_8_EQ_6_0_OR_enq__ETC__q2 = 4'd11;
|
|
endcase
|
|
end
|
|
always@(enq_x)
|
|
begin
|
|
case (enq_x[198:196])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_enq_x_BITS_198_TO_196_0_enq_x_BITS_198_TO_ETC__q3 =
|
|
enq_x[198:196];
|
|
default: CASE_enq_x_BITS_198_TO_196_0_enq_x_BITS_198_TO_ETC__q3 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(enq_x or CASE_enq_x_BITS_198_TO_196_0_enq_x_BITS_198_TO_ETC__q3)
|
|
begin
|
|
case (enq_x[224:222])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_enq_x_BITS_224_TO_222_0_enq_x_BITS_224_TO_ETC__q4 =
|
|
enq_x[224:195];
|
|
3'd4:
|
|
CASE_enq_x_BITS_224_TO_222_0_enq_x_BITS_224_TO_ETC__q4 =
|
|
{ enq_x[224:222],
|
|
18'h2AAAA,
|
|
enq_x[203:199],
|
|
CASE_enq_x_BITS_198_TO_196_0_enq_x_BITS_198_TO_ETC__q3,
|
|
enq_x[195] };
|
|
default: CASE_enq_x_BITS_224_TO_222_0_enq_x_BITS_224_TO_ETC__q4 =
|
|
30'd715827882;
|
|
endcase
|
|
end
|
|
always@(enq_x or IF_enq_x_BITS_192_TO_189_8_EQ_0_9_OR_NOT_enq_x_ETC___d143)
|
|
begin
|
|
case (enq_x[194:193])
|
|
2'd0:
|
|
CASE_enq_x_BITS_194_TO_193_0_enq_x_BITS_194_TO_ETC__q5 =
|
|
enq_x[194:184];
|
|
2'd1:
|
|
CASE_enq_x_BITS_194_TO_193_0_enq_x_BITS_194_TO_ETC__q5 =
|
|
{ enq_x[194:193],
|
|
IF_enq_x_BITS_192_TO_189_8_EQ_0_9_OR_NOT_enq_x_ETC___d143 };
|
|
default: CASE_enq_x_BITS_194_TO_193_0_enq_x_BITS_194_TO_ETC__q5 =
|
|
11'd1194;
|
|
endcase
|
|
end
|
|
always@(enq_x)
|
|
begin
|
|
case (enq_x[136:125])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd1952,
|
|
12'd1953,
|
|
12'd1954,
|
|
12'd1955,
|
|
12'd1968,
|
|
12'd1969,
|
|
12'd1970,
|
|
12'd1971,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2496,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3008,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_enq_x_BITS_136_TO_125_1_enq_x_BITS_136_TO_ETC__q6 =
|
|
enq_x[136:125];
|
|
default: CASE_enq_x_BITS_136_TO_125_1_enq_x_BITS_136_TO_ETC__q6 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(enq_x)
|
|
begin
|
|
case (enq_x[123:119])
|
|
5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31:
|
|
CASE_enq_x_BITS_123_TO_119_0_enq_x_BITS_123_TO_ETC__q7 =
|
|
enq_x[123:119];
|
|
default: CASE_enq_x_BITS_123_TO_119_0_enq_x_BITS_123_TO_ETC__q7 = 5'd10;
|
|
endcase
|
|
end
|
|
always@(IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_78_OR__ETC___d381)
|
|
begin
|
|
case (IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_78_OR__ETC___d381)
|
|
3'd2, 3'd3:
|
|
CASE_IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_7_ETC__q8 =
|
|
IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_78_OR__ETC___d381;
|
|
default: CASE_IF_m_m_row_0_98_BITS_176_TO_174_74_EQ_2_7_ETC__q8 = 3'd4;
|
|
endcase
|
|
end
|
|
always@(IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352)
|
|
begin
|
|
case (IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352)
|
|
4'd6, 4'd7, 4'd8, 4'd9, 4'd10:
|
|
CASE_IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_4_ETC__q9 =
|
|
IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_43_OR__ETC___d352;
|
|
default: CASE_IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_6_4_ETC__q9 = 4'd11;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[186:184])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_m_m_row_0_BITS_186_TO_184_0_m_m_row_0_BIT_ETC__q10 =
|
|
m_m_row_0[186:184];
|
|
default: CASE_m_m_row_0_BITS_186_TO_184_0_m_m_row_0_BIT_ETC__q10 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0 or
|
|
CASE_m_m_row_0_BITS_186_TO_184_0_m_m_row_0_BIT_ETC__q10)
|
|
begin
|
|
case (m_m_row_0[212:210])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_m_m_row_0_BITS_212_TO_210_0_m_m_row_0_BIT_ETC__q11 =
|
|
m_m_row_0[212:183];
|
|
3'd4:
|
|
CASE_m_m_row_0_BITS_212_TO_210_0_m_m_row_0_BIT_ETC__q11 =
|
|
{ m_m_row_0[212:210],
|
|
18'h2AAAA,
|
|
m_m_row_0[191:187],
|
|
CASE_m_m_row_0_BITS_186_TO_184_0_m_m_row_0_BIT_ETC__q10,
|
|
m_m_row_0[183] };
|
|
default: CASE_m_m_row_0_BITS_212_TO_210_0_m_m_row_0_BIT_ETC__q11 =
|
|
30'd715827882;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0 or
|
|
IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_0_32_OR__ETC___d425)
|
|
begin
|
|
case (m_m_row_0[182:181])
|
|
2'd0:
|
|
CASE_m_m_row_0_BITS_182_TO_181_0_m_m_row_0_BIT_ETC__q12 =
|
|
m_m_row_0[182:172];
|
|
2'd1:
|
|
CASE_m_m_row_0_BITS_182_TO_181_0_m_m_row_0_BIT_ETC__q12 =
|
|
{ m_m_row_0[182:181],
|
|
IF_m_m_row_0_98_BITS_180_TO_177_31_EQ_0_32_OR__ETC___d425 };
|
|
default: CASE_m_m_row_0_BITS_182_TO_181_0_m_m_row_0_BIT_ETC__q12 =
|
|
11'd1194;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[124:113])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd1952,
|
|
12'd1953,
|
|
12'd1954,
|
|
12'd1955,
|
|
12'd1968,
|
|
12'd1969,
|
|
12'd1970,
|
|
12'd1971,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2496,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3008,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_m_m_row_0_BITS_124_TO_113_1_m_m_row_0_BIT_ETC__q13 =
|
|
m_m_row_0[124:113];
|
|
default: CASE_m_m_row_0_BITS_124_TO_113_1_m_m_row_0_BIT_ETC__q13 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[111:107])
|
|
5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31:
|
|
CASE_m_m_row_0_BITS_111_TO_107_0_m_m_row_0_BIT_ETC__q14 =
|
|
m_m_row_0[111:107];
|
|
default: CASE_m_m_row_0_BITS_111_TO_107_0_m_m_row_0_BIT_ETC__q14 =
|
|
5'd10;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_specBits_0_rl$EN)
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN;
|
|
if (m_m_valid_0_rl$EN)
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN;
|
|
end
|
|
if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_row_0 = 218'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_specBits_0_rl = 12'hAAA;
|
|
m_m_valid_0_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_enq && IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkAluDispToRegFifo
|
|
|