565 lines
25 KiB
Verilog
565 lines
25 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Wed Jun 24 20:10:21 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// specialRWALU O 163
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// specialRWALU_cap I 163
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// specialRWALU_oldCap I 163
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// specialRWALU_scrType I 5
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//
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// Combinational paths from inputs to outputs:
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// (specialRWALU_cap,
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// specialRWALU_oldCap,
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// specialRWALU_scrType) -> specialRWALU
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_specialRWALU(specialRWALU_cap,
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specialRWALU_oldCap,
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specialRWALU_scrType,
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specialRWALU);
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// value method specialRWALU
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input [162 : 0] specialRWALU_cap;
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input [162 : 0] specialRWALU_oldCap;
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input [4 : 0] specialRWALU_scrType;
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output [162 : 0] specialRWALU;
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// signals for module outputs
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wire [162 : 0] specialRWALU;
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// remaining internal signals
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reg [65 : 0] IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d166;
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reg [63 : 0] IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35;
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reg [13 : 0] CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1;
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reg [4 : 0] CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3;
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reg [2 : 0] CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q5,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8;
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reg CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q2,
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CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4,
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CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q6;
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wire [71 : 0] IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_IF_ETC___d205;
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wire [65 : 0] IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d167,
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in__h1125,
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in__h392,
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res_capFat_address__h1768,
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x__h1143,
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x__h410,
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y__h1142,
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y__h409;
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wire [63 : 0] SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95,
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addBase__h1838,
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addBase__h2022,
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bot__h1841,
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bot__h2025,
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offsetAddr__h129,
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offsetAddr__h1382,
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offsetAddr__h693,
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offsetAddr__h987,
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oldOffset__h23,
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x__h1043,
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x__h1045,
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x__h1262,
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x__h1509,
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x__h283,
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x__h285,
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x__h564,
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x__h867,
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y__h764;
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wire [49 : 0] highOffsetBits__h1386,
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highOffsetBits__h697,
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mask__h1931,
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mask__h2115,
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signBits__h1383,
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signBits__h694,
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x__h1413,
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x__h724;
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wire [15 : 0] newAddrBits__h1640,
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newAddrBits__h1674,
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newAddrBits__h1708,
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newAddrBits__h1742,
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offset__h1031,
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offset__h271,
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x__h1895,
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x__h2079;
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wire [13 : 0] IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d190,
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d196,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d176,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d182,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d199,
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res_capFat_addrBits__h1769,
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toBoundsM1__h1396,
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toBoundsM1__h707,
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toBounds__h1395,
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toBounds__h706;
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wire [9 : 0] IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d280,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d282,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d281;
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wire [5 : 0] IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d279;
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wire [4 : 0] IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d263,
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d275;
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wire [3 : 0] IF_specialRWALU_oldCap_BITS_37_TO_35_09_ULT_sp_ETC___d223,
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IF_specialRWALU_oldCap_BITS_37_TO_35_09_ULT_sp_ETC___d237;
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wire [2 : 0] repBound__h2650, repBound__h2672;
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wire IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d56,
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IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d75,
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IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d116,
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IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d134,
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d253,
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d265,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d213,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d227,
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d63,
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d78,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d142,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d141,
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NOT_specialRWALU_cap_BITS_43_TO_38_8_ULT_50_18___d119,
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NOT_specialRWALU_oldCap_BITS_43_TO_38_3_ULT_50_8___d59,
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SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d123,
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SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d137,
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specialRWALU_cap_BITS_23_TO_21_41_ULT_specialR_ETC___d249,
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specialRWALU_cap_BITS_37_TO_35_45_ULT_specialR_ETC___d246,
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specialRWALU_oldCap_BITS_23_TO_21_07_ULT_speci_ETC___d211,
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specialRWALU_oldCap_BITS_37_TO_35_09_ULT_speci_ETC___d210;
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// value method specialRWALU
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assign specialRWALU =
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{ IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d142,
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res_capFat_address__h1768,
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res_capFat_addrBits__h1769,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_IF_ETC___d205,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d282 } ;
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// remaining internal signals
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assign IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d56 =
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63] ?
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x__h564[13:0] >= toBounds__h706 :
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x__h564[13:0] <= toBoundsM1__h707 ;
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assign IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d75 =
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63] ?
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x__h867[13:0] >= toBounds__h706 :
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x__h867[13:0] <= toBoundsM1__h707 ;
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assign IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d279 =
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{ CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q2,
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CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3 } ;
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assign IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d280 =
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{ CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q5,
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CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q6,
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IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d279 } ;
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assign IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d116 =
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SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63] ?
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x__h1262[13:0] >= toBounds__h1395 :
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x__h1262[13:0] <= toBoundsM1__h1396 ;
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assign IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d134 =
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SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63] ?
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x__h1509[13:0] >= toBounds__h1395 :
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x__h1509[13:0] <= toBoundsM1__h1396 ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d190 =
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(specialRWALU_cap[43:38] == 6'd52) ?
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{ 1'b0, newAddrBits__h1708[12:0] } :
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newAddrBits__h1708[13:0] ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d196 =
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(specialRWALU_cap[43:38] == 6'd52) ?
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{ 1'b0, newAddrBits__h1742[12:0] } :
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newAddrBits__h1742[13:0] ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d253 =
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d190[13:11] <
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repBound__h2672 ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d263 =
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{ IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d253,
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(specialRWALU_cap_BITS_37_TO_35_45_ULT_specialR_ETC___d246 ==
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d253) ?
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2'd0 :
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((specialRWALU_cap_BITS_37_TO_35_45_ULT_specialR_ETC___d246 &&
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!IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d253) ?
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2'd1 :
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2'd3),
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(specialRWALU_cap_BITS_23_TO_21_41_ULT_specialR_ETC___d249 ==
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d253) ?
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2'd0 :
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((specialRWALU_cap_BITS_23_TO_21_41_ULT_specialR_ETC___d249 &&
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!IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d253) ?
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2'd1 :
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2'd3) } ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d265 =
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d196[13:11] <
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repBound__h2672 ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d275 =
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{ IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d265,
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(specialRWALU_cap_BITS_37_TO_35_45_ULT_specialR_ETC___d246 ==
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d265) ?
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2'd0 :
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((specialRWALU_cap_BITS_37_TO_35_45_ULT_specialR_ETC___d246 &&
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!IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d265) ?
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2'd1 :
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2'd3),
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(specialRWALU_cap_BITS_23_TO_21_41_ULT_specialR_ETC___d249 ==
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d265) ?
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2'd0 :
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((specialRWALU_cap_BITS_23_TO_21_41_ULT_specialR_ETC___d249 &&
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!IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d265) ?
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2'd1 :
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2'd3) } ;
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assign IF_specialRWALU_oldCap_BITS_37_TO_35_09_ULT_sp_ETC___d223 =
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{ (specialRWALU_oldCap_BITS_37_TO_35_09_ULT_speci_ETC___d210 ==
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d213) ?
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2'd0 :
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((specialRWALU_oldCap_BITS_37_TO_35_09_ULT_speci_ETC___d210 &&
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!IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d213) ?
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2'd1 :
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2'd3),
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(specialRWALU_oldCap_BITS_23_TO_21_07_ULT_speci_ETC___d211 ==
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d213) ?
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2'd0 :
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((specialRWALU_oldCap_BITS_23_TO_21_07_ULT_speci_ETC___d211 &&
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!IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d213) ?
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2'd1 :
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2'd3) } ;
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assign IF_specialRWALU_oldCap_BITS_37_TO_35_09_ULT_sp_ETC___d237 =
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{ (specialRWALU_oldCap_BITS_37_TO_35_09_ULT_speci_ETC___d210 ==
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d227) ?
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2'd0 :
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((specialRWALU_oldCap_BITS_37_TO_35_09_ULT_speci_ETC___d210 &&
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!IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d227) ?
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2'd1 :
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2'd3),
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(specialRWALU_oldCap_BITS_23_TO_21_07_ULT_speci_ETC___d211 ==
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d227) ?
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2'd0 :
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((specialRWALU_oldCap_BITS_23_TO_21_07_ULT_speci_ETC___d211 &&
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!IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d227) ?
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2'd1 :
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2'd3) } ;
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assign IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d176 =
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(specialRWALU_oldCap[43:38] == 6'd52) ?
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{ 1'b0, newAddrBits__h1640[12:0] } :
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newAddrBits__h1640[13:0] ;
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assign IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d182 =
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(specialRWALU_oldCap[43:38] == 6'd52) ?
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{ 1'b0, newAddrBits__h1674[12:0] } :
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newAddrBits__h1674[13:0] ;
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assign IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d213 =
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d176[13:11] <
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repBound__h2650 ;
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assign IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d227 =
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d182[13:11] <
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repBound__h2650 ;
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assign IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d63 =
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(highOffsetBits__h697 == 50'd0 &&
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IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d56 ||
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NOT_specialRWALU_oldCap_BITS_43_TO_38_3_ULT_50_8___d59) &&
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specialRWALU_oldCap[62:45] == 18'd262143 ;
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assign IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d78 =
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(highOffsetBits__h697 == 50'd0 &&
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IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d75 ||
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NOT_specialRWALU_oldCap_BITS_43_TO_38_3_ULT_50_8___d59) &&
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specialRWALU_oldCap[62:45] == 18'd262143 ;
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assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_IF_ETC___d205 =
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(specialRWALU_scrType[4:2] == 3'd0 ||
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
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3'd0 ||
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specialRWALU_scrType[4:2] == 3'd1 ||
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
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3'd1) ?
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specialRWALU_oldCap[81:10] :
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specialRWALU_cap[81:10] ;
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assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d142 =
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(specialRWALU_scrType[4:2] == 3'd0 ||
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specialRWALU_scrType[4:2] != 3'd1 &&
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
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3'd0) ?
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d63 &&
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specialRWALU_oldCap[162] :
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d141 ;
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assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d282 =
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(specialRWALU_scrType[4:2] == 3'd0 ||
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specialRWALU_scrType[4:2] != 3'd1 &&
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
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3'd0) ?
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{ repBound__h2650,
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specialRWALU_oldCap_BITS_37_TO_35_09_ULT_speci_ETC___d210,
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specialRWALU_oldCap_BITS_23_TO_21_07_ULT_speci_ETC___d211,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d213,
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IF_specialRWALU_oldCap_BITS_37_TO_35_09_ULT_sp_ETC___d223 } :
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d281 ;
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assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d141 =
|
|
(specialRWALU_scrType[4:2] == 3'd1 ||
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd1) ?
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d78 &&
|
|
specialRWALU_oldCap[162] :
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4 ;
|
|
assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d167 =
|
|
(specialRWALU_scrType[4:2] == 3'd1 ||
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd1) ?
|
|
{ 2'd0, bot__h1841 } + { 2'd0, offsetAddr__h693 } :
|
|
IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d166 ;
|
|
assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d199 =
|
|
(specialRWALU_scrType[4:2] == 3'd1 ||
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd1) ?
|
|
IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d182 :
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1 ;
|
|
assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d281 =
|
|
(specialRWALU_scrType[4:2] == 3'd1 ||
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd1) ?
|
|
{ repBound__h2650,
|
|
specialRWALU_oldCap_BITS_37_TO_35_09_ULT_speci_ETC___d210,
|
|
specialRWALU_oldCap_BITS_23_TO_21_07_ULT_speci_ETC___d211,
|
|
IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d227,
|
|
IF_specialRWALU_oldCap_BITS_37_TO_35_09_ULT_sp_ETC___d237 } :
|
|
IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d280 ;
|
|
assign NOT_specialRWALU_cap_BITS_43_TO_38_8_ULT_50_18___d119 =
|
|
specialRWALU_cap[43:38] >= 6'd50 ;
|
|
assign NOT_specialRWALU_oldCap_BITS_43_TO_38_3_ULT_50_8___d59 =
|
|
specialRWALU_oldCap[43:38] >= 6'd50 ;
|
|
assign SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d123 =
|
|
(highOffsetBits__h1386 == 50'd0 &&
|
|
IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d116 ||
|
|
NOT_specialRWALU_cap_BITS_43_TO_38_8_ULT_50_18___d119) &&
|
|
specialRWALU_cap[62:45] == 18'd262143 ;
|
|
assign SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d137 =
|
|
(highOffsetBits__h1386 == 50'd0 &&
|
|
IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d134 ||
|
|
NOT_specialRWALU_cap_BITS_43_TO_38_8_ULT_50_18___d119) &&
|
|
specialRWALU_cap[62:45] == 18'd262143 ;
|
|
assign SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95 =
|
|
x__h1043 | in__h1125[63:0] ;
|
|
assign addBase__h1838 =
|
|
{ {48{x__h1895[15]}}, x__h1895 } << specialRWALU_oldCap[43:38] ;
|
|
assign addBase__h2022 =
|
|
{ {48{x__h2079[15]}}, x__h2079 } << specialRWALU_cap[43:38] ;
|
|
assign bot__h1841 =
|
|
{ specialRWALU_oldCap[159:110] & mask__h1931, 14'd0 } +
|
|
addBase__h1838 ;
|
|
assign bot__h2025 =
|
|
{ specialRWALU_cap[159:110] & mask__h2115, 14'd0 } +
|
|
addBase__h2022 ;
|
|
assign highOffsetBits__h1386 = x__h1413 & mask__h2115 ;
|
|
assign highOffsetBits__h697 = x__h724 & mask__h1931 ;
|
|
assign in__h1125 = specialRWALU_cap[161:96] & y__h1142 ;
|
|
assign in__h392 = specialRWALU_oldCap[161:96] & y__h409 ;
|
|
assign mask__h1931 = 50'h3FFFFFFFFFFFF << specialRWALU_oldCap[43:38] ;
|
|
assign mask__h2115 = 50'h3FFFFFFFFFFFF << specialRWALU_cap[43:38] ;
|
|
assign newAddrBits__h1640 =
|
|
{ 2'd0, specialRWALU_oldCap[23:10] } + { 2'd0, x__h564[13:0] } ;
|
|
assign newAddrBits__h1674 =
|
|
{ 2'd0, specialRWALU_oldCap[23:10] } + { 2'd0, x__h867[13:0] } ;
|
|
assign newAddrBits__h1708 =
|
|
{ 2'd0, specialRWALU_cap[23:10] } + { 2'd0, x__h1262[13:0] } ;
|
|
assign newAddrBits__h1742 =
|
|
{ 2'd0, specialRWALU_cap[23:10] } + { 2'd0, x__h1509[13:0] } ;
|
|
assign offsetAddr__h129 =
|
|
{ IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63:2],
|
|
1'd0,
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[0] } ;
|
|
assign offsetAddr__h1382 =
|
|
{ SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63:1],
|
|
1'd0 } ;
|
|
assign offsetAddr__h693 =
|
|
{ IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63:1],
|
|
1'd0 } ;
|
|
assign offsetAddr__h987 =
|
|
{ SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63:2],
|
|
1'd0,
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[0] } ;
|
|
assign offset__h1031 = { 2'd0, specialRWALU_cap[95:82] } - x__h2079 ;
|
|
assign offset__h271 = { 2'd0, specialRWALU_oldCap[95:82] } - x__h1895 ;
|
|
assign oldOffset__h23 = x__h283 | in__h392[63:0] ;
|
|
assign repBound__h2650 = specialRWALU_oldCap[23:21] - 3'b001 ;
|
|
assign repBound__h2672 = specialRWALU_cap[23:21] - 3'b001 ;
|
|
assign res_capFat_addrBits__h1769 =
|
|
(specialRWALU_scrType[4:2] == 3'd0 ||
|
|
specialRWALU_scrType[4:2] != 3'd1 &&
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd0) ?
|
|
IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_6_ETC___d176 :
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d199 ;
|
|
assign res_capFat_address__h1768 =
|
|
(specialRWALU_scrType[4:2] == 3'd0 ||
|
|
specialRWALU_scrType[4:2] != 3'd1 &&
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd0) ?
|
|
{ 2'd0, bot__h1841 } + { 2'd0, offsetAddr__h129 } :
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d167 ;
|
|
assign signBits__h1383 =
|
|
{50{SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63]}} ;
|
|
assign signBits__h694 =
|
|
{50{IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63]}} ;
|
|
assign specialRWALU_cap_BITS_23_TO_21_41_ULT_specialR_ETC___d249 =
|
|
specialRWALU_cap[23:21] < repBound__h2672 ;
|
|
assign specialRWALU_cap_BITS_37_TO_35_45_ULT_specialR_ETC___d246 =
|
|
specialRWALU_cap[37:35] < repBound__h2672 ;
|
|
assign specialRWALU_oldCap_BITS_23_TO_21_07_ULT_speci_ETC___d211 =
|
|
specialRWALU_oldCap[23:21] < repBound__h2650 ;
|
|
assign specialRWALU_oldCap_BITS_37_TO_35_09_ULT_speci_ETC___d210 =
|
|
specialRWALU_oldCap[37:35] < repBound__h2650 ;
|
|
assign toBoundsM1__h1396 = { 3'b110, ~specialRWALU_cap[20:10] } ;
|
|
assign toBoundsM1__h707 = { 3'b110, ~specialRWALU_oldCap[20:10] } ;
|
|
assign toBounds__h1395 = 14'd14336 - { 3'b0, specialRWALU_cap[20:10] } ;
|
|
assign toBounds__h706 = 14'd14336 - { 3'b0, specialRWALU_oldCap[20:10] } ;
|
|
assign x__h1043 = x__h1045 << specialRWALU_cap[43:38] ;
|
|
assign x__h1045 = { {48{offset__h1031[15]}}, offset__h1031 } ;
|
|
assign x__h1143 = 66'h3FFFFFFFFFFFFFFFF << specialRWALU_cap[43:38] ;
|
|
assign x__h1262 = offsetAddr__h987 >> specialRWALU_cap[43:38] ;
|
|
assign x__h1413 =
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63:14] ^
|
|
signBits__h1383 ;
|
|
assign x__h1509 = offsetAddr__h1382 >> specialRWALU_cap[43:38] ;
|
|
assign x__h1895 = { specialRWALU_oldCap[1:0], specialRWALU_oldCap[23:10] } ;
|
|
assign x__h2079 = { specialRWALU_cap[1:0], specialRWALU_cap[23:10] } ;
|
|
assign x__h283 = x__h285 << specialRWALU_oldCap[43:38] ;
|
|
assign x__h285 = { {48{offset__h271[15]}}, offset__h271 } ;
|
|
assign x__h410 = 66'h3FFFFFFFFFFFFFFFF << specialRWALU_oldCap[43:38] ;
|
|
assign x__h564 = offsetAddr__h129 >> specialRWALU_oldCap[43:38] ;
|
|
assign x__h724 =
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63:14] ^
|
|
signBits__h694 ;
|
|
assign x__h867 = offsetAddr__h693 >> specialRWALU_oldCap[43:38] ;
|
|
assign y__h1142 = ~x__h1143 ;
|
|
assign y__h409 = ~x__h410 ;
|
|
assign y__h764 = ~specialRWALU_cap[159:96] ;
|
|
always@(specialRWALU_scrType)
|
|
begin
|
|
case (specialRWALU_scrType[4:2])
|
|
3'd2, 3'd3:
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 =
|
|
specialRWALU_scrType[4:2];
|
|
default: IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 = 3'd4;
|
|
endcase
|
|
end
|
|
always@(specialRWALU_scrType or
|
|
oldOffset__h23 or y__h764 or specialRWALU_cap)
|
|
begin
|
|
case (specialRWALU_scrType[1:0])
|
|
2'd0:
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35 =
|
|
specialRWALU_cap[159:96];
|
|
2'd1:
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35 =
|
|
oldOffset__h23 | specialRWALU_cap[159:96];
|
|
default: IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35 =
|
|
oldOffset__h23 & y__h764;
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
bot__h2025 or offsetAddr__h987 or offsetAddr__h1382)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2:
|
|
IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d166 =
|
|
{ 2'd0, bot__h2025 } + { 2'd0, offsetAddr__h987 };
|
|
3'd3:
|
|
IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d166 =
|
|
{ 2'd0, bot__h2025 } + { 2'd0, offsetAddr__h1382 };
|
|
default: IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d166 =
|
|
specialRWALU_cap[161:96];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d190 or
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d196)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1 =
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d190;
|
|
3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1 =
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d196;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1 =
|
|
specialRWALU_cap[95:82];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
specialRWALU_cap_BITS_23_TO_21_41_ULT_specialR_ETC___d249)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2, 3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q2 =
|
|
specialRWALU_cap_BITS_23_TO_21_41_ULT_specialR_ETC___d249;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q2 =
|
|
specialRWALU_cap[5];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d263 or
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d275)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3 =
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d263;
|
|
3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3 =
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_83_T_ETC___d275;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3 =
|
|
specialRWALU_cap[4:0];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d123 or
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d137)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4 =
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d123 &&
|
|
specialRWALU_cap[162];
|
|
3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4 =
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d137 &&
|
|
specialRWALU_cap[162];
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4 =
|
|
specialRWALU_cap[162];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or repBound__h2672)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2, 3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q5 =
|
|
repBound__h2672;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q5 =
|
|
specialRWALU_cap[9:7];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
specialRWALU_cap_BITS_37_TO_35_45_ULT_specialR_ETC___d246)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2, 3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q6 =
|
|
specialRWALU_cap_BITS_37_TO_35_45_ULT_specialR_ETC___d246;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q6 =
|
|
specialRWALU_cap[6];
|
|
endcase
|
|
end
|
|
endmodule // module_specialRWALU
|
|
|