202 lines
6.1 KiB
Plaintext
202 lines
6.1 KiB
Plaintext
// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved
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package Boot_ROM;
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// ================================================================
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// This package implements a slave IP that is a RISC-V boot ROM of
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// 1024 32b locations.
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// - Ignores all writes, always responsing OKAY
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// - Assumes all reads are 4-byte aligned requests for 4-bytes
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// ================================================================
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export Boot_ROM_IFC (..), mkBoot_ROM;
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// ================================================================
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// BSV library imports
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import ConfigReg :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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import Semi_FIFOF :: *;
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// ================================================================
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// Project imports
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import AXI4_Types :: *;
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import Fabric_Defs :: *;
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// ================================================================
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// Include the auto-generated BSV-include file with the ROM function
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`ifdef RV32
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`include "fn_read_ROM_RV32.bsvi"
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`endif
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`ifdef RV64
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`include "fn_read_ROM_RV64.bsvi"
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`endif
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// ================================================================
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// Interface
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interface Boot_ROM_IFC;
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// set_addr_map should be called after this module's reset
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method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
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// Main Fabric Reqs/Rsps
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interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave;
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endinterface
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// ================================================================
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(* synthesize *)
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module mkBoot_ROM (Boot_ROM_IFC);
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// Verbosity: 0: quiet; 1: reads/writes
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Integer verbosity = 0;
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Reg #(Bool) rg_module_ready <- mkReg (False);
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Reg #(Fabric_Addr) rg_addr_base <- mkRegU;
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Reg #(Fabric_Addr) rg_addr_lim <- mkRegU;
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// ----------------
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// Connector to fabric
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AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor;
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// ----------------
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function Bool fn_addr_is_aligned (Fabric_Addr addr);
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if (valueOf (Wd_Data) == 32)
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return (addr [1:0] == 2'b_00);
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else if (valueOf (Wd_Data) == 64)
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return (addr [2:0] == 3'b_000);
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else
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return False;
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endfunction
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function Bool fn_addr_is_in_range (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
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return ((base <= addr) && (addr < lim));
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endfunction
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function Bool fn_addr_is_ok (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
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return ( fn_addr_is_aligned (addr)
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&& fn_addr_is_in_range (base, addr, lim));
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endfunction
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// ================================================================
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// BEHAVIOR
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// ----------------------------------------------------------------
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// Handle fabric read requests
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rule rl_process_rd_req (rg_module_ready);
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let rda <- pop_o (slave_xactor.o_rd_addr);
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let byte_addr = rda.araddr - rg_addr_base;
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AXI4_Resp rresp = axi4_resp_okay;
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Bit #(64) data64 = 0;
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if (! fn_addr_is_ok (rg_addr_base, rda.araddr, rg_addr_lim)) begin
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rresp = axi4_resp_slverr;
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$display ("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", cur_cycle);
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$display (" ", fshow (rda));
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end
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else if (rda.araddr [2:0] == 3'b0) begin
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Bit #(32) d0 = fn_read_ROM_0 (byte_addr);
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Bit #(32) d1 = fn_read_ROM_4 (byte_addr + 4);
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data64 = { d1, d0 };
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end
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else begin // ((valueOf (Wd_Data) == 32) && (rda.addr [1:0] == 2'b_00))
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Bit #(32) d1 = fn_read_ROM_4 (byte_addr);
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data64 = { 0, d1 };
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end
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Bit #(Wd_Data) rdata = truncate (data64);
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let rdr = AXI4_Rd_Data {rid: rda.arid,
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rdata: rdata,
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rresp: rresp,
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rlast: True,
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ruser: rda.aruser};
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slave_xactor.i_rd_data.enq (rdr);
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if (verbosity > 0) begin
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$display ("%0d: Boot_ROM.rl_process_rd_req: ", cur_cycle);
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$display (" ", fshow (rda));
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$display (" => ", fshow (rdr));
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end
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endrule
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// ----------------------------------------------------------------
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// Handle fabric write requests: ignore all of them (this is a ROM)
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rule rl_process_wr_req (rg_module_ready);
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let wra <- pop_o (slave_xactor.o_wr_addr);
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let wrd <- pop_o (slave_xactor.o_wr_data);
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AXI4_Resp bresp = axi4_resp_okay;
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if (! fn_addr_is_ok (rg_addr_base, wra.awaddr, rg_addr_lim)) begin
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bresp = axi4_resp_slverr;
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$display ("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", cur_cycle);
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$display (" ", fshow (wra));
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end
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let wrr = AXI4_Wr_Resp {bid: wra.awid,
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bresp: bresp,
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buser: wra.awuser};
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slave_xactor.i_wr_resp.enq (wrr);
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if (verbosity > 0) begin
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$display ("%0d: Boot_ROM.rl_process_wr_req; ignoring all writes", cur_cycle);
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$display (" ", fshow (wra));
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$display (" ", fshow (wrd));
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$display (" => ", fshow (wrr));
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end
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endrule
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// ================================================================
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// INTERFACE
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// set_addr_map should be called after this module's reset
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method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
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if (valueOf (Wd_Data) == 32) begin
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if (addr_base [1:0] != 0)
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$display ("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
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cur_cycle, addr_base);
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if (addr_lim [1:0] != 0)
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$display ("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
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cur_cycle, addr_lim);
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end
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else if (valueOf (Wd_Data) == 64) begin
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if (addr_base [2:0] != 0)
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$display ("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
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cur_cycle, addr_base);
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if (addr_lim [2:0] != 0)
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$display ("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
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cur_cycle, addr_lim);
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end
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rg_addr_base <= addr_base;
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rg_addr_lim <= addr_lim;
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rg_module_ready <= True;
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if (verbosity > 0) begin
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$display ("%0d: Boot_ROM.set_addr_map: base 0x%0h lim 0x%0h", cur_cycle, addr_base, addr_lim);
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end
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endmethod
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// Main Fabric Reqs/Rsps
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interface slave = slave_xactor.axi_side;
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endmodule
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// ================================================================
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endpackage
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