125 lines
4.1 KiB
Plaintext
125 lines
4.1 KiB
Plaintext
// Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Alexandre Joannou
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package Fabric_Defs;
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// ================================================================
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// Defines key parameters of the AXI4/AXI4-Lite system interconnect
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// fabric to which the core connects, such as address bus width, data
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// bus width, etc.
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// ***** WARNING! WARNING! WARNING! *****
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// During system integration, these parameters should be checked to be
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// identical to the system interconnect settings. Strong
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// type-checking (EXACT match on bus widths) will do this; but some
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// languages/tools may silently ignore mismatched widths.
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// ================================================================
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// BSV lib imports
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import AXI4 :: *;
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import ISA_Decls_CHERI :: *;
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// ================================================================
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// Core local Fabric parameters
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typedef 2 Num_Masters_2x3;
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typedef 3 Num_Slaves_2x3;
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typedef Bit#(TLog #(Num_Masters_2x3)) Master_Num_2x3;
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typedef Bit#(TLog #(Num_Slaves_2x3)) Slave_Num_2x3;
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// ----------------
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// Width of fabric 'Id' buses
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typedef 4 Wd_MId_2x3;
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typedef TAdd#(Wd_MId_2x3, TLog#(Num_Masters_2x3)) Wd_SId_2x3;
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typedef Wd_SId_2x3 Wd_MId;
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// ----------------
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// Width of fabric 'addr' buses
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`ifdef FABRIC64
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typedef 64 Wd_Addr;
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`else
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typedef 32 Wd_Addr;
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`endif
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typedef Bit #(Wd_Addr) Fabric_Addr;
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typedef TDiv #(Wd_Addr, 8) Bytes_per_Fabric_Addr;
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Integer bytes_per_fabric_addr = valueOf (Bytes_per_Fabric_Addr);
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// ----------------
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// Widths of the main bus data are 128 bits. Peripherals each have a shim
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// converting this down to 64 bits (and stripping tags).
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// (caches <==> Bus <==> (tag controller) <==> main memory
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// |
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// Periph
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typedef 64 Wd_Data;
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// ----------------
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// Width of fabric 'user' datapaths. Carry capability tags on data lines.
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typedef 0 Wd_AW_User;
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typedef 0 Wd_B_User;
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typedef 0 Wd_AR_User;
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typedef TMax#(TDiv#(Wd_Data, CLEN),1) Wd_W_User;
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typedef TMax#(TDiv#(Wd_Data, CLEN),1) Wd_R_User;
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typedef TDiv #(Wd_Data, 8) Bytes_per_Fabric_Data;
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Integer bytes_per_fabric_data = valueOf (Bytes_per_Fabric_Data);
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typedef Bit #(Wd_Data) Fabric_Data;
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typedef Bit #(TDiv #(Wd_Data, 8)) Fabric_Strb;
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// ----------------
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typedef 64 Wd_Data_Periph;
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typedef 0 Wd_AW_User_Periph;
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typedef 0 Wd_W_User_Periph;
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typedef 0 Wd_B_User_Periph;
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typedef 0 Wd_AR_User_Periph;
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typedef 0 Wd_R_User_Periph;
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typedef Bit #(Wd_Data_Periph) Fabric_Data_Periph;
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typedef Bit #(TDiv #(Wd_Data_Periph, 8)) Fabric_Strb_Periph;
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typedef TDiv #(Wd_Data_Periph, 8) Bytes_per_Fabric_Data_Periph;
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// ----------------
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// Number of zero LSBs in a fabric address aligned to the fabric data width
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typedef TLog #(Bytes_per_Fabric_Data) ZLSBs_Aligned_Fabric_Addr;
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Integer zlsbs_aligned_fabric_addr = valueOf (ZLSBs_Aligned_Fabric_Addr);
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// ================================================================
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// AXI4 defaults for this project
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Bit#(Wd_MId_2x3) fabric_2x3_default_mid = 0;
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Bit#(Wd_MId) fabric_default_mid = 0;
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AXI4_Burst fabric_default_burst = INCR;
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AXI4_Lock fabric_default_lock = NORMAL;
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AXI4_Cache fabric_default_arcache = arcache_dev_nonbuf;
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AXI4_Cache fabric_default_awcache = awcache_dev_nonbuf;
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AXI4_Prot fabric_default_prot = axi4Prot(DATA, SECURE, UNPRIV);
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AXI4_QoS fabric_default_qos = 0;
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AXI4_Region fabric_default_region = 0;
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Bit#(Wd_AW_User) fabric_default_awuser = 0;
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Bit#(Wd_W_User) fabric_default_wuser = 0;
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Bit#(Wd_B_User) fabric_default_buser = 0;
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Bit#(Wd_AR_User) fabric_default_aruser = 0;
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Bit#(Wd_R_User) fabric_default_ruser = 0;
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// ================================================================
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endpackage
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