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Toooba/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v
Jessica Clarke 72f49a1109 Regenerate verilog
2020-07-16 19:35:51 +01:00

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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Thu Jul 16 18:27:56 BST 2020
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// av_read O 32
// RDY_av_read O 1
// RDY_write O 1
// master_awid O 4
// master_awaddr O 64
// master_awlen O 8
// master_awsize O 3
// master_awburst O 2
// master_awlock O 1
// master_awcache O 4
// master_awprot O 3
// master_awqos O 4
// master_awregion O 4
// master_awvalid O 1
// master_wdata O 64
// master_wstrb O 8
// master_wlast O 1
// master_wuser O 1
// master_wvalid O 1
// master_bready O 1
// master_arid O 4
// master_araddr O 64
// master_arlen O 8
// master_arsize O 3
// master_arburst O 2
// master_arlock O 1
// master_arcache O 4
// master_arprot O 3
// master_arqos O 4
// master_arregion O 4
// master_arvalid O 1
// master_rready O 1
// CLK I 1 clock
// RST_N I 1 reset
// av_read_dm_addr I 7
// write_dm_addr I 7
// write_dm_word I 32
// master_awready I 1
// master_wready I 1
// master_bvalid I 1
// master_bid I 4
// master_bresp I 2
// master_arready I 1
// master_rvalid I 1
// master_rid I 4
// master_rdata I 64
// master_rresp I 2
// master_rlast I 1
// master_ruser I 1
// EN_reset I 1
// EN_write I 1
// EN_av_read I 1
//
// Combinational paths from inputs to outputs:
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awid
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awaddr
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awlen
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awsize
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awburst
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awlock
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awcache
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awprot
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awqos
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awregion
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awuser
// (write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_awvalid
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_wdata
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_wstrb
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_wlast
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_wuser
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_write) -> master_wvalid
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arid
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_araddr
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arlen
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arsize
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arburst
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arlock
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arcache
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arprot
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arqos
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arregion
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_aruser
// (write_dm_addr,
// write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// av_read_dm_addr,
// EN_write,
// EN_av_read) -> master_arvalid
// av_read_dm_addr -> av_read
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDM_System_Bus(CLK,
RST_N,
EN_reset,
RDY_reset,
av_read_dm_addr,
EN_av_read,
av_read,
RDY_av_read,
write_dm_addr,
write_dm_word,
EN_write,
RDY_write,
master_awid,
master_awaddr,
master_awlen,
master_awsize,
master_awburst,
master_awlock,
master_awcache,
master_awprot,
master_awqos,
master_awregion,
master_awvalid,
master_awready,
master_wdata,
master_wstrb,
master_wlast,
master_wuser,
master_wvalid,
master_wready,
master_bvalid,
master_bid,
master_bresp,
master_bready,
master_arid,
master_araddr,
master_arlen,
master_arsize,
master_arburst,
master_arlock,
master_arcache,
master_arprot,
master_arqos,
master_arregion,
master_arvalid,
master_arready,
master_rvalid,
master_rid,
master_rdata,
master_rresp,
master_rlast,
master_ruser,
master_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// actionvalue method av_read
input [6 : 0] av_read_dm_addr;
input EN_av_read;
output [31 : 0] av_read;
output RDY_av_read;
// action method write
input [6 : 0] write_dm_addr;
input [31 : 0] write_dm_word;
input EN_write;
output RDY_write;
// value method master_aw_awid
output [3 : 0] master_awid;
// value method master_aw_awaddr
output [63 : 0] master_awaddr;
// value method master_aw_awlen
output [7 : 0] master_awlen;
// value method master_aw_awsize
output [2 : 0] master_awsize;
// value method master_aw_awburst
output [1 : 0] master_awburst;
// value method master_aw_awlock
output master_awlock;
// value method master_aw_awcache
output [3 : 0] master_awcache;
// value method master_aw_awprot
output [2 : 0] master_awprot;
// value method master_aw_awqos
output [3 : 0] master_awqos;
// value method master_aw_awregion
output [3 : 0] master_awregion;
// value method master_aw_awuser
// value method master_aw_awvalid
output master_awvalid;
// action method master_aw_awready
input master_awready;
// value method master_w_wdata
output [63 : 0] master_wdata;
// value method master_w_wstrb
output [7 : 0] master_wstrb;
// value method master_w_wlast
output master_wlast;
// value method master_w_wuser
output master_wuser;
// value method master_w_wvalid
output master_wvalid;
// action method master_w_wready
input master_wready;
// action method master_b_bflit
input master_bvalid;
input [3 : 0] master_bid;
input [1 : 0] master_bresp;
// value method master_b_bready
output master_bready;
// value method master_ar_arid
output [3 : 0] master_arid;
// value method master_ar_araddr
output [63 : 0] master_araddr;
// value method master_ar_arlen
output [7 : 0] master_arlen;
// value method master_ar_arsize
output [2 : 0] master_arsize;
// value method master_ar_arburst
output [1 : 0] master_arburst;
// value method master_ar_arlock
output master_arlock;
// value method master_ar_arcache
output [3 : 0] master_arcache;
// value method master_ar_arprot
output [2 : 0] master_arprot;
// value method master_ar_arqos
output [3 : 0] master_arqos;
// value method master_ar_arregion
output [3 : 0] master_arregion;
// value method master_ar_aruser
// value method master_ar_arvalid
output master_arvalid;
// action method master_ar_arready
input master_arready;
// action method master_r_rflit
input master_rvalid;
input [3 : 0] master_rid;
input [63 : 0] master_rdata;
input [1 : 0] master_rresp;
input master_rlast;
input master_ruser;
// value method master_r_rready
output master_rready;
// signals for module outputs
reg [31 : 0] av_read;
wire [63 : 0] master_araddr, master_awaddr, master_wdata;
wire [7 : 0] master_arlen, master_awlen, master_wstrb;
wire [3 : 0] master_arcache,
master_arid,
master_arqos,
master_arregion,
master_awcache,
master_awid,
master_awqos,
master_awregion;
wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize;
wire [1 : 0] master_arburst, master_awburst;
wire RDY_av_read,
RDY_reset,
RDY_write,
master_arlock,
master_arvalid,
master_awlock,
master_awvalid,
master_bready,
master_rready,
master_wlast,
master_wuser,
master_wvalid;
// inlined wires
wire [97 : 0] master_xactor_shim_arff_rv$port0__write_1,
master_xactor_shim_arff_rv$port1__read,
master_xactor_shim_arff_rv$port1__write_1,
master_xactor_shim_arff_rv$port2__read,
master_xactor_shim_arff_rv$port3__read,
master_xactor_shim_awff_rv$port0__write_1,
master_xactor_shim_awff_rv$port1__read,
master_xactor_shim_awff_rv$port2__read,
master_xactor_shim_awff_rv$port3__read;
wire [74 : 0] master_xactor_shim_wff_rv$port0__write_1,
master_xactor_shim_wff_rv$port1__read,
master_xactor_shim_wff_rv$port1__write_1,
master_xactor_shim_wff_rv$port2__read,
master_xactor_shim_wff_rv$port3__read;
wire [72 : 0] master_xactor_shim_rff_rv$port0__write_1,
master_xactor_shim_rff_rv$port1__read,
master_xactor_shim_rff_rv$port1__write_1,
master_xactor_shim_rff_rv$port2__read,
master_xactor_shim_rff_rv$port3__read;
wire [71 : 0] master_xactor_master_rSynth_snk_putWire$wget;
wire [6 : 0] master_xactor_shim_bff_rv$port0__write_1,
master_xactor_shim_bff_rv$port1__read,
master_xactor_shim_bff_rv$port1__write_1,
master_xactor_shim_bff_rv$port2__read,
master_xactor_shim_bff_rv$port3__read;
wire [5 : 0] master_xactor_master_bSynth_snk_putWire$wget;
wire master_xactor_master_arSynth_src_dropWire$whas,
master_xactor_master_awSynth_src_dropWire$whas,
master_xactor_master_bSynth_snk_putWire$whas,
master_xactor_master_rSynth_snk_putWire$whas,
master_xactor_master_wSynth_src_dropWire$whas,
master_xactor_shim_arff_rv$EN_port0__write;
// register master_xactor_clearing
reg master_xactor_clearing;
wire master_xactor_clearing$D_IN, master_xactor_clearing$EN;
// register master_xactor_shim_arff_rv
reg [97 : 0] master_xactor_shim_arff_rv;
wire [97 : 0] master_xactor_shim_arff_rv$D_IN;
wire master_xactor_shim_arff_rv$EN;
// register master_xactor_shim_awff_rv
reg [97 : 0] master_xactor_shim_awff_rv;
wire [97 : 0] master_xactor_shim_awff_rv$D_IN;
wire master_xactor_shim_awff_rv$EN;
// register master_xactor_shim_bff_rv
reg [6 : 0] master_xactor_shim_bff_rv;
wire [6 : 0] master_xactor_shim_bff_rv$D_IN;
wire master_xactor_shim_bff_rv$EN;
// register master_xactor_shim_rff_rv
reg [72 : 0] master_xactor_shim_rff_rv;
wire [72 : 0] master_xactor_shim_rff_rv$D_IN;
wire master_xactor_shim_rff_rv$EN;
// register master_xactor_shim_wff_rv
reg [74 : 0] master_xactor_shim_wff_rv;
wire [74 : 0] master_xactor_shim_wff_rv$D_IN;
wire master_xactor_shim_wff_rv$EN;
// register rg_sb_state
reg [1 : 0] rg_sb_state;
wire [1 : 0] rg_sb_state$D_IN;
wire rg_sb_state$EN;
// register rg_sbaddress0
reg [31 : 0] rg_sbaddress0;
reg [31 : 0] rg_sbaddress0$D_IN;
wire rg_sbaddress0$EN;
// register rg_sbaddress1
reg [31 : 0] rg_sbaddress1;
reg [31 : 0] rg_sbaddress1$D_IN;
wire rg_sbaddress1$EN;
// register rg_sbaddress_reading
reg [63 : 0] rg_sbaddress_reading;
wire [63 : 0] rg_sbaddress_reading$D_IN;
wire rg_sbaddress_reading$EN;
// register rg_sbcs_sbaccess
reg [2 : 0] rg_sbcs_sbaccess;
wire [2 : 0] rg_sbcs_sbaccess$D_IN;
wire rg_sbcs_sbaccess$EN;
// register rg_sbcs_sbautoincrement
reg rg_sbcs_sbautoincrement;
wire rg_sbcs_sbautoincrement$D_IN, rg_sbcs_sbautoincrement$EN;
// register rg_sbcs_sbbusyerror
reg rg_sbcs_sbbusyerror;
reg rg_sbcs_sbbusyerror$D_IN;
wire rg_sbcs_sbbusyerror$EN;
// register rg_sbcs_sberror
reg [2 : 0] rg_sbcs_sberror;
reg [2 : 0] rg_sbcs_sberror$D_IN;
wire rg_sbcs_sberror$EN;
// register rg_sbcs_sbreadonaddr
reg rg_sbcs_sbreadonaddr;
wire rg_sbcs_sbreadonaddr$D_IN, rg_sbcs_sbreadonaddr$EN;
// register rg_sbcs_sbreadondata
reg rg_sbcs_sbreadondata;
wire rg_sbcs_sbreadondata$D_IN, rg_sbcs_sbreadondata$EN;
// register rg_sbdata0
reg [31 : 0] rg_sbdata0;
reg [31 : 0] rg_sbdata0$D_IN;
wire rg_sbdata0$EN;
// rule scheduling signals
wire CAN_FIRE_RL_master_xactor_do_clear,
CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop,
CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek,
CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop,
CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop,
CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek,
CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop,
CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut,
CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut,
CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut,
CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut,
CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop,
CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek,
CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop,
CAN_FIRE_RL_rl_sb_read_finish,
CAN_FIRE_RL_rl_sb_write_response,
CAN_FIRE_av_read,
CAN_FIRE_master_ar_arready,
CAN_FIRE_master_aw_awready,
CAN_FIRE_master_b_bflit,
CAN_FIRE_master_r_rflit,
CAN_FIRE_master_w_wready,
CAN_FIRE_reset,
CAN_FIRE_write,
WILL_FIRE_RL_master_xactor_do_clear,
WILL_FIRE_RL_master_xactor_master_arSynth_src_doDrop,
WILL_FIRE_RL_master_xactor_master_arSynth_src_setPeek,
WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop,
WILL_FIRE_RL_master_xactor_master_awSynth_src_doDrop,
WILL_FIRE_RL_master_xactor_master_awSynth_src_setPeek,
WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop,
WILL_FIRE_RL_master_xactor_master_bSynth_snk_doPut,
WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut,
WILL_FIRE_RL_master_xactor_master_rSynth_snk_doPut,
WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut,
WILL_FIRE_RL_master_xactor_master_wSynth_src_doDrop,
WILL_FIRE_RL_master_xactor_master_wSynth_src_setPeek,
WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop,
WILL_FIRE_RL_rl_sb_read_finish,
WILL_FIRE_RL_rl_sb_write_response,
WILL_FIRE_av_read,
WILL_FIRE_master_ar_arready,
WILL_FIRE_master_aw_awready,
WILL_FIRE_master_b_bflit,
WILL_FIRE_master_r_rflit,
WILL_FIRE_master_w_wready,
WILL_FIRE_reset,
WILL_FIRE_write;
// inputs to muxes for submodule ports
reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2,
MUX_rg_sbaddress1$write_1__VAL_2;
reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4;
wire [97 : 0] MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1,
MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2;
wire MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1,
MUX_rg_sbaddress0$write_1__SEL_2,
MUX_rg_sbaddress0$write_1__SEL_3,
MUX_rg_sbaddress1$write_1__SEL_2,
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2,
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3,
MUX_rg_sbcs_sberror$write_1__SEL_1,
MUX_rg_sbcs_sberror$write_1__SEL_3,
MUX_rg_sbcs_sberror$write_1__SEL_4,
MUX_rg_sbdata0$write_1__SEL_3;
// remaining internal signals
reg [63 : 0] CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4,
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104,
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117,
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155,
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130,
wrd_wdata__h7347;
reg [7 : 0] wrd_wstrb__h7348;
reg [2 : 0] _theResult___snd_snd_val__h7238, axi4_size_val__h5493;
wire [96 : 0] master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3,
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1;
wire [73 : 0] master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2;
wire [63 : 0] _theResult___fst__h7223,
addr64__h6510,
result__h3886,
result__h3916,
result__h3943,
result__h3970,
result__h3997,
result__h4024,
result__h4051,
result__h4078,
result__h4123,
result__h4150,
result__h4177,
result__h4204,
result__h4245,
result__h4272,
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156,
rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354,
sbaddress__h3177,
word64__h7168;
wire [31 : 0] IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365,
IF_write_dm_addr_EQ_0x39_13_THEN_rg_sbaddress1_ETC___d356,
v__h4885,
v__h5019;
wire [7 : 0] strobe64__h7221, strobe64__h7225, strobe64__h7229;
wire [5 : 0] shift_bits__h7171;
wire rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147,
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162,
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d371,
rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d346,
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311,
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d320,
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d326,
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d328,
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d333,
write_dm_addr_EQ_0x3C_16_AND_rg_sb_state_7_EQ__ETC___d381;
// action method reset
assign RDY_reset = !master_xactor_clearing ;
assign CAN_FIRE_reset = !master_xactor_clearing ;
assign WILL_FIRE_reset = EN_reset ;
// actionvalue method av_read
always@(av_read_dm_addr or
v__h4885 or rg_sbaddress0 or rg_sbaddress1 or v__h5019)
begin
case (av_read_dm_addr)
7'h38: av_read = v__h4885;
7'h39: av_read = rg_sbaddress0;
7'h3A: av_read = rg_sbaddress1;
7'h3C: av_read = v__h5019;
default: av_read = 32'd0;
endcase
end
assign RDY_av_read =
rg_sb_state == 2'd0 &&
(rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 ||
!rg_sbcs_sbreadondata ||
!master_xactor_clearing && !master_xactor_shim_arff_rv[97]) ;
assign CAN_FIRE_av_read = RDY_av_read ;
assign WILL_FIRE_av_read = EN_av_read ;
// action method write
assign RDY_write = CAN_FIRE_write && !WILL_FIRE_RL_rl_sb_read_finish ;
assign CAN_FIRE_write =
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0 ||
!rg_sbcs_sbreadonaddr ||
!master_xactor_clearing && !master_xactor_shim_arff_rv[97]) &&
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0 ||
!master_xactor_clearing && !master_xactor_shim_awff_rv[97] &&
!master_xactor_shim_wff_rv[74]) ;
assign WILL_FIRE_write = EN_write ;
// value method master_aw_awid
assign master_awid =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[96:93] ;
// value method master_aw_awaddr
assign master_awaddr =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[92:29] ;
// value method master_aw_awlen
assign master_awlen =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[28:21] ;
// value method master_aw_awsize
assign master_awsize =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[20:18] ;
// value method master_aw_awburst
assign master_awburst =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[17:16] ;
// value method master_aw_awlock
assign master_awlock =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[15] ;
// value method master_aw_awcache
assign master_awcache =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[14:11] ;
// value method master_aw_awprot
assign master_awprot =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[10:8] ;
// value method master_aw_awqos
assign master_awqos =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[7:4] ;
// value method master_aw_awregion
assign master_awregion =
master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[3:0] ;
// value method master_aw_awvalid
assign master_awvalid =
CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek ;
// action method master_aw_awready
assign CAN_FIRE_master_aw_awready = 1'd1 ;
assign WILL_FIRE_master_aw_awready = 1'd1 ;
// value method master_w_wdata
assign master_wdata =
master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2[73:10] ;
// value method master_w_wstrb
assign master_wstrb =
master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2[9:2] ;
// value method master_w_wlast
assign master_wlast =
master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2[1] ;
// value method master_w_wuser
assign master_wuser =
master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2[0] ;
// value method master_w_wvalid
assign master_wvalid = CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek ;
// action method master_w_wready
assign CAN_FIRE_master_w_wready = 1'd1 ;
assign WILL_FIRE_master_w_wready = 1'd1 ;
// action method master_b_bflit
assign CAN_FIRE_master_b_bflit = 1'd1 ;
assign WILL_FIRE_master_b_bflit = 1'd1 ;
// value method master_b_bready
assign master_bready = !master_xactor_shim_bff_rv[6] ;
// value method master_ar_arid
assign master_arid =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[96:93] ;
// value method master_ar_araddr
assign master_araddr =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[92:29] ;
// value method master_ar_arlen
assign master_arlen =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[28:21] ;
// value method master_ar_arsize
assign master_arsize =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[20:18] ;
// value method master_ar_arburst
assign master_arburst =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[17:16] ;
// value method master_ar_arlock
assign master_arlock =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[15] ;
// value method master_ar_arcache
assign master_arcache =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[14:11] ;
// value method master_ar_arprot
assign master_arprot =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[10:8] ;
// value method master_ar_arqos
assign master_arqos =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[7:4] ;
// value method master_ar_arregion
assign master_arregion =
master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[3:0] ;
// value method master_ar_arvalid
assign master_arvalid =
CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek ;
// action method master_ar_arready
assign CAN_FIRE_master_ar_arready = 1'd1 ;
assign WILL_FIRE_master_ar_arready = 1'd1 ;
// action method master_r_rflit
assign CAN_FIRE_master_r_rflit = 1'd1 ;
assign WILL_FIRE_master_r_rflit = 1'd1 ;
// value method master_r_rready
assign master_rready = !master_xactor_shim_rff_rv[72] ;
// rule RL_master_xactor_master_bSynth_snk_warnDoPut
assign CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut =
master_xactor_master_bSynth_snk_putWire$whas &&
master_xactor_shim_bff_rv[6] ;
assign WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut =
CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut ;
// rule RL_master_xactor_master_bSynth_snk_doPut
assign CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut =
!master_xactor_shim_bff_rv[6] &&
master_xactor_master_bSynth_snk_putWire$whas ;
assign WILL_FIRE_RL_master_xactor_master_bSynth_snk_doPut =
CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut ;
// rule RL_master_xactor_master_rSynth_snk_warnDoPut
assign CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut =
master_xactor_master_rSynth_snk_putWire$whas &&
master_xactor_shim_rff_rv[72] ;
assign WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut =
CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut ;
// rule RL_master_xactor_master_rSynth_snk_doPut
assign CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut =
!master_xactor_shim_rff_rv[72] &&
master_xactor_master_rSynth_snk_putWire$whas ;
assign WILL_FIRE_RL_master_xactor_master_rSynth_snk_doPut =
CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut ;
// rule RL_rl_sb_read_finish
assign CAN_FIRE_RL_rl_sb_read_finish =
!master_xactor_clearing &&
master_xactor_shim_rff_rv$port1__read[72] &&
rg_sb_state == 2'd1 &&
rg_sbcs_sberror == 3'd0 ;
assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ;
// rule RL_rl_sb_write_response
assign CAN_FIRE_RL_rl_sb_write_response =
!master_xactor_clearing &&
master_xactor_shim_bff_rv$port1__read[6] ;
assign WILL_FIRE_RL_rl_sb_write_response =
CAN_FIRE_RL_rl_sb_write_response ;
// rule RL_master_xactor_master_awSynth_src_setPeek
assign CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek =
master_xactor_shim_awff_rv$port1__read[97] ;
assign WILL_FIRE_RL_master_xactor_master_awSynth_src_setPeek =
CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek ;
// rule RL_master_xactor_master_awSynth_src_warnDoDrop
assign CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop =
master_xactor_master_awSynth_src_dropWire$whas &&
!master_xactor_shim_awff_rv$port1__read[97] ;
assign WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop =
CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop ;
// rule RL_master_xactor_master_awSynth_src_doDrop
assign CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop =
master_xactor_shim_awff_rv$port1__read[97] &&
master_xactor_master_awSynth_src_dropWire$whas ;
assign WILL_FIRE_RL_master_xactor_master_awSynth_src_doDrop =
CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop ;
// rule RL_master_xactor_master_wSynth_src_setPeek
assign CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek =
master_xactor_shim_wff_rv$port1__read[74] ;
assign WILL_FIRE_RL_master_xactor_master_wSynth_src_setPeek =
CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek ;
// rule RL_master_xactor_master_wSynth_src_warnDoDrop
assign CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop =
master_xactor_master_wSynth_src_dropWire$whas &&
!master_xactor_shim_wff_rv$port1__read[74] ;
assign WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop =
CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop ;
// rule RL_master_xactor_master_wSynth_src_doDrop
assign CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop =
master_xactor_shim_wff_rv$port1__read[74] &&
master_xactor_master_wSynth_src_dropWire$whas ;
assign WILL_FIRE_RL_master_xactor_master_wSynth_src_doDrop =
CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop ;
// rule RL_master_xactor_master_arSynth_src_setPeek
assign CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek =
master_xactor_shim_arff_rv$port1__read[97] ;
assign WILL_FIRE_RL_master_xactor_master_arSynth_src_setPeek =
CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek ;
// rule RL_master_xactor_master_arSynth_src_warnDoDrop
assign CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop =
master_xactor_master_arSynth_src_dropWire$whas &&
!master_xactor_shim_arff_rv$port1__read[97] ;
assign WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop =
CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop ;
// rule RL_master_xactor_master_arSynth_src_doDrop
assign CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop =
master_xactor_shim_arff_rv$port1__read[97] &&
master_xactor_master_arSynth_src_dropWire$whas ;
assign WILL_FIRE_RL_master_xactor_master_arSynth_src_doDrop =
CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop ;
// rule RL_master_xactor_do_clear
assign CAN_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ;
assign WILL_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ;
// inputs to muxes for submodule ports
assign MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162 ;
assign MUX_rg_sbaddress0$write_1__SEL_2 =
EN_write && write_dm_addr != 7'h38 &&
(rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
write_dm_addr == 7'h39 ||
write_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147) ;
assign MUX_rg_sbaddress0$write_1__SEL_3 =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147 ;
assign MUX_rg_sbaddress1$write_1__SEL_2 =
EN_write && write_dm_addr != 7'h38 &&
((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d346 ||
write_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147) ;
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 =
EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d320 ;
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 =
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_1 =
WILL_FIRE_RL_rl_sb_write_response &&
master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_3 =
WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_4 =
EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d328 ;
assign MUX_rg_sbdata0$write_1__SEL_3 =
EN_write &&
write_dm_addr_EQ_0x3C_16_AND_rg_sb_state_7_EQ__ETC___d381 ;
assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 =
{ 5'd16,
sbaddress__h3177,
8'd0,
axi4_size_val__h5493,
18'd65536 } ;
assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 =
{ 5'd16, addr64__h6510, 8'd0, axi4_size_val__h5493, 18'd65536 } ;
always@(write_dm_addr or
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 or
IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365)
begin
case (write_dm_addr)
7'h39, 7'h3A:
MUX_rg_sbaddress0$write_1__VAL_2 =
IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365;
default: MUX_rg_sbaddress0$write_1__VAL_2 =
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156[31:0];
endcase
end
always@(write_dm_addr or
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 or
IF_write_dm_addr_EQ_0x39_13_THEN_rg_sbaddress1_ETC___d356)
begin
case (write_dm_addr)
7'h39, 7'h3A:
MUX_rg_sbaddress1$write_1__VAL_2 =
IF_write_dm_addr_EQ_0x39_13_THEN_rg_sbaddress1_ETC___d356;
default: MUX_rg_sbaddress1$write_1__VAL_2 =
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156[63:32];
endcase
end
always@(write_dm_word)
begin
case (write_dm_word[19:17])
3'd3, 3'd4: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd3;
default: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd0;
endcase
end
// inlined wires
assign master_xactor_master_bSynth_snk_putWire$wget =
{ master_bid, master_bresp } ;
assign master_xactor_master_bSynth_snk_putWire$whas =
master_bvalid && !master_xactor_shim_bff_rv[6] ;
assign master_xactor_master_rSynth_snk_putWire$wget =
{ master_rid,
master_rdata,
master_rresp,
master_rlast,
master_ruser } ;
assign master_xactor_master_rSynth_snk_putWire$whas =
master_rvalid && !master_xactor_shim_rff_rv[72] ;
assign master_xactor_master_awSynth_src_dropWire$whas =
master_xactor_shim_awff_rv$port1__read[97] && master_awready ;
assign master_xactor_master_wSynth_src_dropWire$whas =
master_xactor_shim_wff_rv$port1__read[74] && master_wready ;
assign master_xactor_master_arSynth_src_dropWire$whas =
master_xactor_shim_arff_rv$port1__read[97] && master_arready ;
assign master_xactor_shim_awff_rv$port0__write_1 =
{ 5'd16,
sbaddress__h3177,
8'd0,
_theResult___snd_snd_val__h7238,
18'd65536 } ;
assign master_xactor_shim_awff_rv$port1__read =
MUX_rg_sbdata0$write_1__SEL_3 ?
master_xactor_shim_awff_rv$port0__write_1 :
master_xactor_shim_awff_rv ;
assign master_xactor_shim_awff_rv$port2__read =
CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop ?
master_xactor_shim_arff_rv$port1__write_1 :
master_xactor_shim_awff_rv$port1__read ;
assign master_xactor_shim_awff_rv$port3__read =
master_xactor_clearing ?
master_xactor_shim_arff_rv$port1__write_1 :
master_xactor_shim_awff_rv$port2__read ;
assign master_xactor_shim_wff_rv$port0__write_1 =
{ 1'd1, wrd_wdata__h7347, wrd_wstrb__h7348, 2'd2 } ;
assign master_xactor_shim_wff_rv$port1__read =
MUX_rg_sbdata0$write_1__SEL_3 ?
master_xactor_shim_wff_rv$port0__write_1 :
master_xactor_shim_wff_rv ;
assign master_xactor_shim_wff_rv$port1__write_1 =
{ 1'd0,
74'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
assign master_xactor_shim_wff_rv$port2__read =
CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop ?
master_xactor_shim_wff_rv$port1__write_1 :
master_xactor_shim_wff_rv$port1__read ;
assign master_xactor_shim_wff_rv$port3__read =
master_xactor_clearing ?
master_xactor_shim_wff_rv$port1__write_1 :
master_xactor_shim_wff_rv$port2__read ;
assign master_xactor_shim_bff_rv$port0__write_1 =
{ 1'd1, master_xactor_master_bSynth_snk_putWire$wget } ;
assign master_xactor_shim_bff_rv$port1__read =
CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut ?
master_xactor_shim_bff_rv$port0__write_1 :
master_xactor_shim_bff_rv ;
assign master_xactor_shim_bff_rv$port1__write_1 =
{ 1'd0, 6'bxxxxxx /* unspecified value */ } ;
assign master_xactor_shim_bff_rv$port2__read =
CAN_FIRE_RL_rl_sb_write_response ?
master_xactor_shim_bff_rv$port1__write_1 :
master_xactor_shim_bff_rv$port1__read ;
assign master_xactor_shim_bff_rv$port3__read =
master_xactor_clearing ?
master_xactor_shim_bff_rv$port1__write_1 :
master_xactor_shim_bff_rv$port2__read ;
assign master_xactor_shim_arff_rv$EN_port0__write =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d371 ;
assign master_xactor_shim_arff_rv$port0__write_1 =
MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ?
MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 :
MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 ;
assign master_xactor_shim_arff_rv$port1__read =
master_xactor_shim_arff_rv$EN_port0__write ?
master_xactor_shim_arff_rv$port0__write_1 :
master_xactor_shim_arff_rv ;
assign master_xactor_shim_arff_rv$port1__write_1 =
{ 1'd0,
97'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
assign master_xactor_shim_arff_rv$port2__read =
CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop ?
master_xactor_shim_arff_rv$port1__write_1 :
master_xactor_shim_arff_rv$port1__read ;
assign master_xactor_shim_arff_rv$port3__read =
master_xactor_clearing ?
master_xactor_shim_arff_rv$port1__write_1 :
master_xactor_shim_arff_rv$port2__read ;
assign master_xactor_shim_rff_rv$port0__write_1 =
{ 1'd1, master_xactor_master_rSynth_snk_putWire$wget } ;
assign master_xactor_shim_rff_rv$port1__read =
CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut ?
master_xactor_shim_rff_rv$port0__write_1 :
master_xactor_shim_rff_rv ;
assign master_xactor_shim_rff_rv$port1__write_1 =
{ 1'd0,
72'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
assign master_xactor_shim_rff_rv$port2__read =
CAN_FIRE_RL_rl_sb_read_finish ?
master_xactor_shim_rff_rv$port1__write_1 :
master_xactor_shim_rff_rv$port1__read ;
assign master_xactor_shim_rff_rv$port3__read =
master_xactor_clearing ?
master_xactor_shim_rff_rv$port1__write_1 :
master_xactor_shim_rff_rv$port2__read ;
// register master_xactor_clearing
assign master_xactor_clearing$D_IN = !master_xactor_clearing ;
assign master_xactor_clearing$EN = master_xactor_clearing || EN_reset ;
// register master_xactor_shim_arff_rv
assign master_xactor_shim_arff_rv$D_IN =
master_xactor_shim_arff_rv$port3__read ;
assign master_xactor_shim_arff_rv$EN = 1'b1 ;
// register master_xactor_shim_awff_rv
assign master_xactor_shim_awff_rv$D_IN =
master_xactor_shim_awff_rv$port3__read ;
assign master_xactor_shim_awff_rv$EN = 1'b1 ;
// register master_xactor_shim_bff_rv
assign master_xactor_shim_bff_rv$D_IN =
master_xactor_shim_bff_rv$port3__read ;
assign master_xactor_shim_bff_rv$EN = 1'b1 ;
// register master_xactor_shim_rff_rv
assign master_xactor_shim_rff_rv$D_IN =
master_xactor_shim_rff_rv$port3__read ;
assign master_xactor_shim_rff_rv$EN = 1'b1 ;
// register master_xactor_shim_wff_rv
assign master_xactor_shim_wff_rv$D_IN =
master_xactor_shim_wff_rv$port3__read ;
assign master_xactor_shim_wff_rv$EN = 1'b1 ;
// register rg_sb_state
assign rg_sb_state$D_IN =
(EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ;
assign rg_sb_state$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d371 ||
WILL_FIRE_RL_rl_sb_read_finish ||
EN_reset ;
// register rg_sbaddress0
always@(EN_reset or
MUX_rg_sbaddress0$write_1__SEL_2 or
MUX_rg_sbaddress0$write_1__VAL_2 or
MUX_rg_sbaddress0$write_1__SEL_3 or
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156)
case (1'b1)
EN_reset: rg_sbaddress0$D_IN = 32'd0;
MUX_rg_sbaddress0$write_1__SEL_2:
rg_sbaddress0$D_IN = MUX_rg_sbaddress0$write_1__VAL_2;
MUX_rg_sbaddress0$write_1__SEL_3:
rg_sbaddress0$D_IN =
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156[31:0];
default: rg_sbaddress0$D_IN =
32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
endcase
assign rg_sbaddress0$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147 ||
MUX_rg_sbaddress0$write_1__SEL_2 ||
EN_reset ;
// register rg_sbaddress1
always@(EN_reset or
MUX_rg_sbaddress1$write_1__SEL_2 or
MUX_rg_sbaddress1$write_1__VAL_2 or
MUX_rg_sbaddress0$write_1__SEL_3 or
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156)
case (1'b1)
EN_reset: rg_sbaddress1$D_IN = 32'd0;
MUX_rg_sbaddress1$write_1__SEL_2:
rg_sbaddress1$D_IN = MUX_rg_sbaddress1$write_1__VAL_2;
MUX_rg_sbaddress0$write_1__SEL_3:
rg_sbaddress1$D_IN =
rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156[63:32];
default: rg_sbaddress1$D_IN =
32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
endcase
assign rg_sbaddress1$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147 ||
MUX_rg_sbaddress1$write_1__SEL_2 ||
EN_reset ;
// register rg_sbaddress_reading
assign rg_sbaddress_reading$D_IN =
MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ?
sbaddress__h3177 :
addr64__h6510 ;
assign rg_sbaddress_reading$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d371 ;
// register rg_sbcs_sbaccess
assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ;
assign rg_sbcs_sbaccess$EN =
EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 ||
EN_reset ;
// register rg_sbcs_sbautoincrement
assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ;
assign rg_sbcs_sbautoincrement$EN =
EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 ||
EN_reset ;
// register rg_sbcs_sbbusyerror
always@(EN_reset or
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 or
write_dm_addr or MUX_rg_sbcs_sbbusyerror$write_1__SEL_3)
case (1'b1)
EN_reset: rg_sbcs_sbbusyerror$D_IN = 1'd0;
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2:
rg_sbcs_sbbusyerror$D_IN = write_dm_addr != 7'h38;
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3: rg_sbcs_sbbusyerror$D_IN = 1'd1;
default: rg_sbcs_sbbusyerror$D_IN = 1'bx /* unspecified value */ ;
endcase
assign rg_sbcs_sbbusyerror$EN =
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ||
EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d320 ||
EN_reset ;
// register rg_sbcs_sberror
always@(MUX_rg_sbcs_sberror$write_1__SEL_1 or
EN_reset or
MUX_rg_sbcs_sberror$write_1__SEL_3 or
MUX_rg_sbcs_sberror$write_1__SEL_4 or
MUX_rg_sbcs_sberror$write_1__VAL_4)
case (1'b1)
MUX_rg_sbcs_sberror$write_1__SEL_1: rg_sbcs_sberror$D_IN = 3'd3;
EN_reset: rg_sbcs_sberror$D_IN = 3'd0;
MUX_rg_sbcs_sberror$write_1__SEL_3: rg_sbcs_sberror$D_IN = 3'd3;
MUX_rg_sbcs_sberror$write_1__SEL_4:
rg_sbcs_sberror$D_IN = MUX_rg_sbcs_sberror$write_1__VAL_4;
default: rg_sbcs_sberror$D_IN = 3'bxxx /* unspecified value */ ;
endcase
assign rg_sbcs_sberror$EN =
WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 ||
WILL_FIRE_RL_rl_sb_write_response &&
master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 ||
EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d328 ||
EN_reset ;
// register rg_sbcs_sbreadonaddr
assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ;
assign rg_sbcs_sbreadonaddr$EN =
EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 ||
EN_reset ;
// register rg_sbcs_sbreadondata
assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ;
assign rg_sbcs_sbreadondata$EN =
EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 ||
EN_reset ;
// register rg_sbdata0
always@(EN_reset or
WILL_FIRE_RL_rl_sb_read_finish or
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130 or
MUX_rg_sbdata0$write_1__SEL_3 or write_dm_word)
case (1'b1)
EN_reset: rg_sbdata0$D_IN = 32'd0;
WILL_FIRE_RL_rl_sb_read_finish:
rg_sbdata0$D_IN =
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130[31:0];
MUX_rg_sbdata0$write_1__SEL_3: rg_sbdata0$D_IN = write_dm_word;
default: rg_sbdata0$D_IN =
32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
endcase
assign rg_sbdata0$EN =
EN_write &&
write_dm_addr_EQ_0x3C_16_AND_rg_sb_state_7_EQ__ETC___d381 ||
WILL_FIRE_RL_rl_sb_read_finish ||
EN_reset ;
// remaining internal signals
assign IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365 =
rg_sbcs_sbreadonaddr ?
(rg_sbcs_sbautoincrement ?
rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354[31:0] :
write_dm_word) :
write_dm_word ;
assign IF_write_dm_addr_EQ_0x39_13_THEN_rg_sbaddress1_ETC___d356 =
(write_dm_addr == 7'h39) ?
rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354[63:32] :
write_dm_word ;
assign _theResult___fst__h7223 = word64__h7168 << shift_bits__h7171 ;
assign addr64__h6510 = { rg_sbaddress1, write_dm_word } ;
assign master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3 =
master_xactor_shim_arff_rv$port1__read[96:0] ;
assign master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1 =
master_xactor_shim_awff_rv$port1__read[96:0] ;
assign master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2 =
master_xactor_shim_wff_rv$port1__read[73:0] ;
assign result__h3886 =
{ 56'd0, master_xactor_shim_rff_rv$port1__read[11:4] } ;
assign result__h3916 =
{ 56'd0, master_xactor_shim_rff_rv$port1__read[19:12] } ;
assign result__h3943 =
{ 56'd0, master_xactor_shim_rff_rv$port1__read[27:20] } ;
assign result__h3970 =
{ 56'd0, master_xactor_shim_rff_rv$port1__read[35:28] } ;
assign result__h3997 =
{ 56'd0, master_xactor_shim_rff_rv$port1__read[43:36] } ;
assign result__h4024 =
{ 56'd0, master_xactor_shim_rff_rv$port1__read[51:44] } ;
assign result__h4051 =
{ 56'd0, master_xactor_shim_rff_rv$port1__read[59:52] } ;
assign result__h4078 =
{ 56'd0, master_xactor_shim_rff_rv$port1__read[67:60] } ;
assign result__h4123 =
{ 48'd0, master_xactor_shim_rff_rv$port1__read[19:4] } ;
assign result__h4150 =
{ 48'd0, master_xactor_shim_rff_rv$port1__read[35:20] } ;
assign result__h4177 =
{ 48'd0, master_xactor_shim_rff_rv$port1__read[51:36] } ;
assign result__h4204 =
{ 48'd0, master_xactor_shim_rff_rv$port1__read[67:52] } ;
assign result__h4245 =
{ 32'd0, master_xactor_shim_rff_rv$port1__read[35:4] } ;
assign result__h4272 =
{ 32'd0, master_xactor_shim_rff_rv$port1__read[67:36] } ;
assign rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbautoincrement ;
assign rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbreadondata ;
assign rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d371 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbreadonaddr ;
assign rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 =
sbaddress__h3177 +
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 ;
assign rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354 =
addr64__h6510 +
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 ;
assign rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d346 =
rg_sbcs_sberror == 3'd0 &&
(rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement ||
write_dm_addr != 7'h39) ;
assign sbaddress__h3177 = { rg_sbaddress1, rg_sbaddress0 } ;
assign shift_bits__h7171 = { rg_sbaddress0[2:0], 3'b0 } ;
assign strobe64__h7221 = 8'b00000001 << rg_sbaddress0[2:0] ;
assign strobe64__h7225 = 8'b00000011 << rg_sbaddress0[2:0] ;
assign strobe64__h7229 = 8'b00001111 << rg_sbaddress0[2:0] ;
assign v__h4885 =
{ 9'd64,
rg_sbcs_sbbusyerror,
rg_sb_state != 2'd0,
rg_sbcs_sbreadonaddr,
rg_sbcs_sbaccess,
rg_sbcs_sbautoincrement,
rg_sbcs_sbreadondata,
rg_sbcs_sberror,
12'd2055 } ;
assign v__h5019 =
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0) ?
32'd0 :
rg_sbdata0 ;
assign word64__h7168 = { 32'd0, write_dm_word } ;
assign write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] != 3'd4 &&
write_dm_word[19:17] != 3'd3 ;
assign write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d320 =
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 ||
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A ||
write_dm_addr == 7'h3C) &&
rg_sb_state != 2'd0 ;
assign write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d326 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
rg_sbcs_sbbusyerror &&
!write_dm_word[22] ;
assign write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d328 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) ;
assign write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d333 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
(write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ;
assign write_dm_addr_EQ_0x3C_16_AND_rg_sb_state_7_EQ__ETC___d381 =
write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 ;
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2: axi4_size_val__h5493 = rg_sbcs_sbaccess;
default: axi4_size_val__h5493 = 3'b011;
endcase
end
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2, 3'd3:
_theResult___snd_snd_val__h7238 = rg_sbcs_sbaccess;
default: _theResult___snd_snd_val__h7238 = 3'b111;
endcase
end
always@(rg_sbcs_sbaccess or
strobe64__h7221 or strobe64__h7225 or strobe64__h7229)
begin
case (rg_sbcs_sbaccess)
3'd0: wrd_wstrb__h7348 = strobe64__h7221;
3'd1: wrd_wstrb__h7348 = strobe64__h7225;
3'd2: wrd_wstrb__h7348 = strobe64__h7229;
3'd3: wrd_wstrb__h7348 = 8'b11111111;
default: wrd_wstrb__h7348 = 8'd0;
endcase
end
always@(rg_sbcs_sbaccess or word64__h7168 or _theResult___fst__h7223)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2: wrd_wdata__h7347 = _theResult___fst__h7223;
default: wrd_wdata__h7347 = word64__h7168;
endcase
end
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0: IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 = 64'd1;
3'd1: IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 = 64'd2;
3'd2: IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 = 64'd4;
3'd3: IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 = 64'd8;
default: IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 =
64'd16;
endcase
end
always@(rg_sbaddress_reading or
result__h3886 or
result__h3916 or
result__h3943 or
result__h3970 or
result__h3997 or result__h4024 or result__h4051 or result__h4078)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 =
result__h3886;
3'h1:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 =
result__h3916;
3'h2:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 =
result__h3943;
3'h3:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 =
result__h3970;
3'h4:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 =
result__h3997;
3'h5:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 =
result__h4024;
3'h6:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 =
result__h4051;
3'h7:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 =
result__h4078;
endcase
end
always@(rg_sbaddress_reading or
result__h4123 or result__h4150 or result__h4177 or result__h4204)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 =
result__h4123;
3'h2:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 =
result__h4150;
3'h4:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 =
result__h4177;
3'h6:
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 =
result__h4204;
default: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 =
64'd0;
endcase
end
always@(rg_sbaddress_reading or result__h4245 or result__h4272)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 =
result__h4245;
3'h4:
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 =
result__h4272;
default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = 64'd0;
endcase
end
always@(rg_sbcs_sbaccess or
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 or
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 or
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 or
rg_sbaddress_reading or master_xactor_shim_rff_rv$port1__read)
begin
case (rg_sbcs_sbaccess)
3'd0:
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130 =
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104;
3'd1:
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130 =
IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117;
3'd2:
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130 =
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4;
3'd3:
IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130 =
(rg_sbaddress_reading[2:0] == 3'h0) ?
master_xactor_shim_rff_rv$port1__read[67:4] :
64'd0;
default: IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130 =
64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0;
master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY
{ 1'd0,
97'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY
{ 1'd0,
97'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY
{ 1'd0, 6'bxxxxxx /* unspecified value */ };
master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY
{ 1'd0,
72'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY
{ 1'd0,
74'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (master_xactor_clearing$EN)
master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY
master_xactor_clearing$D_IN;
if (master_xactor_shim_arff_rv$EN)
master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY
master_xactor_shim_arff_rv$D_IN;
if (master_xactor_shim_awff_rv$EN)
master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY
master_xactor_shim_awff_rv$D_IN;
if (master_xactor_shim_bff_rv$EN)
master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY
master_xactor_shim_bff_rv$D_IN;
if (master_xactor_shim_rff_rv$EN)
master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY
master_xactor_shim_rff_rv$D_IN;
if (master_xactor_shim_wff_rv$EN)
master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY
master_xactor_shim_wff_rv$D_IN;
if (rg_sbaddress0$EN)
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN;
if (rg_sbaddress1$EN)
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN;
end
if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN;
if (rg_sbaddress_reading$EN)
rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN;
if (rg_sbcs_sbaccess$EN)
rg_sbcs_sbaccess <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbaccess$D_IN;
if (rg_sbcs_sbautoincrement$EN)
rg_sbcs_sbautoincrement <= `BSV_ASSIGNMENT_DELAY
rg_sbcs_sbautoincrement$D_IN;
if (rg_sbcs_sbbusyerror$EN)
rg_sbcs_sbbusyerror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbbusyerror$D_IN;
if (rg_sbcs_sberror$EN)
rg_sbcs_sberror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sberror$D_IN;
if (rg_sbcs_sbreadonaddr$EN)
rg_sbcs_sbreadonaddr <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadonaddr$D_IN;
if (rg_sbcs_sbreadondata$EN)
rg_sbcs_sbreadondata <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadondata$D_IN;
if (rg_sbdata0$EN) rg_sbdata0 <= `BSV_ASSIGNMENT_DELAY rg_sbdata0$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
master_xactor_clearing = 1'h0;
master_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA;
master_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA;
master_xactor_shim_bff_rv = 7'h2A;
master_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA;
master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA;
rg_sb_state = 2'h2;
rg_sbaddress0 = 32'hAAAAAAAA;
rg_sbaddress1 = 32'hAAAAAAAA;
rg_sbaddress_reading = 64'hAAAAAAAAAAAAAAAA;
rg_sbcs_sbaccess = 3'h2;
rg_sbcs_sbautoincrement = 1'h0;
rg_sbcs_sbbusyerror = 1'h0;
rg_sbcs_sberror = 3'h2;
rg_sbcs_sbreadonaddr = 1'h0;
rg_sbcs_sbreadondata = 1'h0;
rg_sbdata0 = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbdata.read: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbdata.read: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0)
$display("DM_System_Bus.sbdata.read: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C)
$write("DM_System_Bus.read: [");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h11) $write("dm_addr_dmstatus");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h12) $write("dm_addr_hartinfo");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h13) $write("dm_addr_haltsum");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h14)
$write("dm_addr_hawindowsel");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h15) $write("dm_addr_hawindow");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h19)
$write("dm_addr_devtreeaddr0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h30) $write("dm_addr_authdata");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h40)
$write("dm_addr_haltregion0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h5F)
$write("dm_addr_haltregion31");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h60) $write("dm_addr_verbosity");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h16)
$write("dm_addr_abstractcs");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h17) $write("dm_addr_command");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h04) $write("dm_addr_data0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h05) $write("dm_addr_data1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h06) $write("dm_addr_data2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h07) $write("dm_addr_data3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h08) $write("dm_addr_data4");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h09) $write("dm_addr_data5");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0A) $write("dm_addr_data6");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0B) $write("dm_addr_data7");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0C) $write("dm_addr_data8");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0D) $write("dm_addr_data9");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0F) $write("dm_addr_data11");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h18)
$write("dm_addr_abstractauto");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h20) $write("dm_addr_progbuf0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3B)
$write("dm_addr_sbaddress2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C &&
av_read_dm_addr != 7'h10 &&
av_read_dm_addr != 7'h11 &&
av_read_dm_addr != 7'h12 &&
av_read_dm_addr != 7'h13 &&
av_read_dm_addr != 7'h14 &&
av_read_dm_addr != 7'h15 &&
av_read_dm_addr != 7'h19 &&
av_read_dm_addr != 7'h30 &&
av_read_dm_addr != 7'h40 &&
av_read_dm_addr != 7'h5F &&
av_read_dm_addr != 7'h60 &&
av_read_dm_addr != 7'h16 &&
av_read_dm_addr != 7'h17 &&
av_read_dm_addr != 7'h04 &&
av_read_dm_addr != 7'h05 &&
av_read_dm_addr != 7'h06 &&
av_read_dm_addr != 7'h07 &&
av_read_dm_addr != 7'h08 &&
av_read_dm_addr != 7'h09 &&
av_read_dm_addr != 7'h0A &&
av_read_dm_addr != 7'h0B &&
av_read_dm_addr != 7'h0C &&
av_read_dm_addr != 7'h0D &&
av_read_dm_addr != 7'h0F &&
av_read_dm_addr != 7'h18 &&
av_read_dm_addr != 7'h20 &&
av_read_dm_addr != 7'h3B &&
av_read_dm_addr != 7'h3D &&
av_read_dm_addr != 7'h3E &&
av_read_dm_addr != 7'h3F)
$write("<Unknown dm_abstract_command dm_addr 0x%0h>",
av_read_dm_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C)
$write("] not supported", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut)
$display("WARNING: %m - putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut)
$display("WARNING: %m - putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display(" ERROR: existing sberror (0x%0h) is not being cleared.",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display(" Must be cleared to re-enable system bus access.");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d326)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d326)
$display(" ERROR: existing sbbusyerror (%0d) is not being cleared.",
rg_sbcs_sbbusyerror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d326)
$display(" Must be cleared to re-enable system bus access.");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d333)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d333)
$write(" ERROR: sbaccess ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] == 3'd3)
$write("DM_SBACCESS_64_BIT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] == 3'd4)
$write("DM_SBACCESS_128_BIT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d333)
$write(" not supported", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbaddress.write: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbaddress.write: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state != 2'd0)
$display("DM_System_Bus.sbaddress.write: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbdata.write: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbdata.write: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state != 2'd0)
$display("DM_System_Bus.sbdata.write: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C)
$write("DM_System_Bus.write: [");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h11) $write("dm_addr_dmstatus");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h12) $write("dm_addr_hartinfo");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h13) $write("dm_addr_haltsum");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h14) $write("dm_addr_hawindowsel");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h15) $write("dm_addr_hawindow");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h19) $write("dm_addr_devtreeaddr0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h30) $write("dm_addr_authdata");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h40) $write("dm_addr_haltregion0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h5F) $write("dm_addr_haltregion31");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h60) $write("dm_addr_verbosity");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h16) $write("dm_addr_abstractcs");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h17) $write("dm_addr_command");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h04) $write("dm_addr_data0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h05) $write("dm_addr_data1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h06) $write("dm_addr_data2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h07) $write("dm_addr_data3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h08) $write("dm_addr_data4");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h09) $write("dm_addr_data5");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0A) $write("dm_addr_data6");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0B) $write("dm_addr_data7");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0C) $write("dm_addr_data8");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0D) $write("dm_addr_data9");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0F) $write("dm_addr_data11");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h18) $write("dm_addr_abstractauto");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h20) $write("dm_addr_progbuf0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3B) $write("dm_addr_sbaddress2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C &&
write_dm_addr != 7'h10 &&
write_dm_addr != 7'h11 &&
write_dm_addr != 7'h12 &&
write_dm_addr != 7'h13 &&
write_dm_addr != 7'h14 &&
write_dm_addr != 7'h15 &&
write_dm_addr != 7'h19 &&
write_dm_addr != 7'h30 &&
write_dm_addr != 7'h40 &&
write_dm_addr != 7'h5F &&
write_dm_addr != 7'h60 &&
write_dm_addr != 7'h16 &&
write_dm_addr != 7'h17 &&
write_dm_addr != 7'h04 &&
write_dm_addr != 7'h05 &&
write_dm_addr != 7'h06 &&
write_dm_addr != 7'h07 &&
write_dm_addr != 7'h08 &&
write_dm_addr != 7'h09 &&
write_dm_addr != 7'h0A &&
write_dm_addr != 7'h0B &&
write_dm_addr != 7'h0C &&
write_dm_addr != 7'h0D &&
write_dm_addr != 7'h0F &&
write_dm_addr != 7'h18 &&
write_dm_addr != 7'h20 &&
write_dm_addr != 7'h3B &&
write_dm_addr != 7'h3D &&
write_dm_addr != 7'h3E &&
write_dm_addr != 7'h3F)
$write("<Unknown dm_abstract_command dm_addr 0x%0h>", write_dm_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C)
$write("] <= 0x%08h; addr not supported", write_dm_word, "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(" rdr = ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("AXI4_RFlit { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("'h%h", master_xactor_shim_rff_rv$port1__read[71:68]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("'h%h", master_xactor_shim_rff_rv$port1__read[67:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1)
$write("EXOKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2)
$write("SLVERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd1 &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd2)
$write("DECERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 &&
master_xactor_shim_rff_rv$port1__read[1])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 &&
!master_xactor_shim_rff_rv$port1__read[1])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("'h%h", master_xactor_shim_rff_rv$port1__read[0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop)
$display("WARNING: %m - dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop)
$display("WARNING: %m - dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop)
$display("WARNING: %m - dropping from Source that can't be dropped from");
end
// synopsys translate_on
endmodule // mkDM_System_Bus
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