8989 lines
359 KiB
Verilog
8989 lines
359 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:34:44 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// flush_done O 1
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// RDY_flush_done O 1 const
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// RDY_flush O 1
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// RDY_updateVMInfo O 1 const
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// noPendingReq O 1
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// RDY_noPendingReq O 1 const
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// RDY_procReq O 1
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// procResp O 561
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// RDY_procResp O 1
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// RDY_deqProcResp O 1
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// toParent_rqToP_notEmpty O 1
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// RDY_toParent_rqToP_notEmpty O 1 const
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// RDY_toParent_rqToP_deq O 1
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// toParent_rqToP_first O 29
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// RDY_toParent_rqToP_first O 1
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// toParent_ldTransRsFromP_notFull O 1
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// RDY_toParent_ldTransRsFromP_notFull O 1 const
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// RDY_toParent_ldTransRsFromP_enq O 1
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// RDY_toParent_flush_request_get O 1
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// RDY_toParent_flush_response_put O 1
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// RDY_perf_setStatus O 1 const
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// RDY_perf_req O 1
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// perf_resp O 67
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// RDY_perf_resp O 1
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// perf_respValid O 1
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// RDY_perf_respValid O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// updateVMInfo_vm I 49 reg
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// procReq_req I 491
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// toParent_ldTransRsFromP_enq_x I 83
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// perf_setStatus_doStats I 1 unused
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// perf_req_r I 3
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// EN_flush I 1
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// EN_updateVMInfo I 1
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// EN_procReq I 1
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// EN_deqProcResp I 1
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// EN_toParent_rqToP_deq I 1
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// EN_toParent_ldTransRsFromP_enq I 1
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// EN_toParent_flush_request_get I 1
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// EN_toParent_flush_response_put I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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// EN_perf_setStatus I 1 unused
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// EN_perf_req I 1
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// EN_perf_resp I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDTlbSynth(CLK,
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RST_N,
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flush_done,
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RDY_flush_done,
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EN_flush,
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RDY_flush,
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updateVMInfo_vm,
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EN_updateVMInfo,
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RDY_updateVMInfo,
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noPendingReq,
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RDY_noPendingReq,
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procReq_req,
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EN_procReq,
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RDY_procReq,
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procResp,
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RDY_procResp,
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EN_deqProcResp,
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RDY_deqProcResp,
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toParent_rqToP_notEmpty,
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RDY_toParent_rqToP_notEmpty,
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EN_toParent_rqToP_deq,
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RDY_toParent_rqToP_deq,
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toParent_rqToP_first,
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RDY_toParent_rqToP_first,
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toParent_ldTransRsFromP_notFull,
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RDY_toParent_ldTransRsFromP_notFull,
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toParent_ldTransRsFromP_enq_x,
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EN_toParent_ldTransRsFromP_enq,
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RDY_toParent_ldTransRsFromP_enq,
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EN_toParent_flush_request_get,
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RDY_toParent_flush_request_get,
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EN_toParent_flush_response_put,
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RDY_toParent_flush_response_put,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation,
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perf_setStatus_doStats,
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EN_perf_setStatus,
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RDY_perf_setStatus,
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perf_req_r,
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EN_perf_req,
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RDY_perf_req,
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EN_perf_resp,
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perf_resp,
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RDY_perf_resp,
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perf_respValid,
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RDY_perf_respValid);
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input CLK;
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input RST_N;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// action method updateVMInfo
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input [48 : 0] updateVMInfo_vm;
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input EN_updateVMInfo;
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output RDY_updateVMInfo;
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// value method noPendingReq
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output noPendingReq;
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output RDY_noPendingReq;
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// action method procReq
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input [490 : 0] procReq_req;
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input EN_procReq;
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output RDY_procReq;
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// value method procResp
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output [560 : 0] procResp;
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output RDY_procResp;
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// action method deqProcResp
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input EN_deqProcResp;
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output RDY_deqProcResp;
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// value method toParent_rqToP_notEmpty
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output toParent_rqToP_notEmpty;
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output RDY_toParent_rqToP_notEmpty;
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// action method toParent_rqToP_deq
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input EN_toParent_rqToP_deq;
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output RDY_toParent_rqToP_deq;
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// value method toParent_rqToP_first
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output [28 : 0] toParent_rqToP_first;
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output RDY_toParent_rqToP_first;
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// value method toParent_ldTransRsFromP_notFull
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output toParent_ldTransRsFromP_notFull;
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output RDY_toParent_ldTransRsFromP_notFull;
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// action method toParent_ldTransRsFromP_enq
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input [82 : 0] toParent_ldTransRsFromP_enq_x;
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input EN_toParent_ldTransRsFromP_enq;
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output RDY_toParent_ldTransRsFromP_enq;
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// action method toParent_flush_request_get
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input EN_toParent_flush_request_get;
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output RDY_toParent_flush_request_get;
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// action method toParent_flush_response_put
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input EN_toParent_flush_response_put;
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output RDY_toParent_flush_response_put;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// action method perf_setStatus
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input perf_setStatus_doStats;
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input EN_perf_setStatus;
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output RDY_perf_setStatus;
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// action method perf_req
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input [2 : 0] perf_req_r;
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input EN_perf_req;
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output RDY_perf_req;
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// actionvalue method perf_resp
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input EN_perf_resp;
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output [66 : 0] perf_resp;
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output RDY_perf_resp;
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// value method perf_respValid
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output perf_respValid;
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output RDY_perf_respValid;
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// signals for module outputs
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wire [560 : 0] procResp;
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wire [66 : 0] perf_resp;
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wire [28 : 0] toParent_rqToP_first;
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wire RDY_deqProcResp,
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RDY_flush,
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RDY_flush_done,
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RDY_noPendingReq,
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RDY_perf_req,
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RDY_perf_resp,
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RDY_perf_respValid,
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RDY_perf_setStatus,
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RDY_procReq,
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RDY_procResp,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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RDY_toParent_flush_request_get,
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RDY_toParent_flush_response_put,
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RDY_toParent_ldTransRsFromP_enq,
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RDY_toParent_ldTransRsFromP_notFull,
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RDY_toParent_rqToP_deq,
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RDY_toParent_rqToP_first,
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RDY_toParent_rqToP_notEmpty,
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RDY_updateVMInfo,
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flush_done,
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noPendingReq,
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perf_respValid,
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toParent_ldTransRsFromP_notFull,
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toParent_rqToP_notEmpty;
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// inlined wires
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reg [2 : 0] m_freeQ_enqReq_lat_0$wget;
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wire [83 : 0] m_ldTransRsFromPQ_enqReq_lat_0$wget,
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m_ldTransRsFromPQ_enqReq_lat_2$wget;
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wire [29 : 0] m_rqToPQ_enqReq_lat_0$wget, m_rqToPQ_enqReq_lat_2$wget;
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wire [5 : 0] m_tlb_m_updRepIdx_lat_0$wget, m_tlb_m_updRepIdx_lat_1$wget;
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wire [3 : 0] m_perfReqQ_enqReq_lat_0$wget, m_perfReqQ_enqReq_lat_2$wget;
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wire [2 : 0] m_freeQ_enqReq_lat_2$wget;
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wire m_freeQ_enqReq_lat_0$whas,
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m_ldTransRsFromPQ_deqReq_lat_0$whas,
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m_pendValid_0_lat_0$whas,
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m_pendValid_1_lat_0$whas,
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m_pendValid_2_lat_0$whas,
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m_pendValid_3_lat_0$whas,
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m_rqToPQ_enqReq_lat_0$whas,
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m_tlb_m_lruBit_lat_0$whas,
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m_tlb_m_updRepIdx_lat_0$whas,
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m_tlb_m_updRepIdx_lat_1$whas;
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// register m_flushRqToPQ_clearReq_rl
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reg m_flushRqToPQ_clearReq_rl;
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wire m_flushRqToPQ_clearReq_rl$D_IN, m_flushRqToPQ_clearReq_rl$EN;
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// register m_flushRqToPQ_deqReq_rl
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reg m_flushRqToPQ_deqReq_rl;
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wire m_flushRqToPQ_deqReq_rl$D_IN, m_flushRqToPQ_deqReq_rl$EN;
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// register m_flushRqToPQ_empty
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reg m_flushRqToPQ_empty;
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wire m_flushRqToPQ_empty$D_IN, m_flushRqToPQ_empty$EN;
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// register m_flushRqToPQ_enqReq_rl
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reg m_flushRqToPQ_enqReq_rl;
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wire m_flushRqToPQ_enqReq_rl$D_IN, m_flushRqToPQ_enqReq_rl$EN;
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// register m_flushRqToPQ_full
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reg m_flushRqToPQ_full;
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wire m_flushRqToPQ_full$D_IN, m_flushRqToPQ_full$EN;
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// register m_flushRsFromPQ_clearReq_rl
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reg m_flushRsFromPQ_clearReq_rl;
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wire m_flushRsFromPQ_clearReq_rl$D_IN, m_flushRsFromPQ_clearReq_rl$EN;
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// register m_flushRsFromPQ_deqReq_rl
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reg m_flushRsFromPQ_deqReq_rl;
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wire m_flushRsFromPQ_deqReq_rl$D_IN, m_flushRsFromPQ_deqReq_rl$EN;
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// register m_flushRsFromPQ_empty
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reg m_flushRsFromPQ_empty;
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wire m_flushRsFromPQ_empty$D_IN, m_flushRsFromPQ_empty$EN;
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// register m_flushRsFromPQ_enqReq_rl
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reg m_flushRsFromPQ_enqReq_rl;
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wire m_flushRsFromPQ_enqReq_rl$D_IN, m_flushRsFromPQ_enqReq_rl$EN;
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// register m_flushRsFromPQ_full
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reg m_flushRsFromPQ_full;
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wire m_flushRsFromPQ_full$D_IN, m_flushRsFromPQ_full$EN;
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// register m_freeQInitIdx
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reg [1 : 0] m_freeQInitIdx;
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wire [1 : 0] m_freeQInitIdx$D_IN;
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wire m_freeQInitIdx$EN;
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// register m_freeQInited
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reg m_freeQInited;
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wire m_freeQInited$D_IN, m_freeQInited$EN;
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// register m_freeQ_clearReq_rl
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reg m_freeQ_clearReq_rl;
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wire m_freeQ_clearReq_rl$D_IN, m_freeQ_clearReq_rl$EN;
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// register m_freeQ_data_0
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reg [1 : 0] m_freeQ_data_0;
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wire [1 : 0] m_freeQ_data_0$D_IN;
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wire m_freeQ_data_0$EN;
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// register m_freeQ_data_1
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reg [1 : 0] m_freeQ_data_1;
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wire [1 : 0] m_freeQ_data_1$D_IN;
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wire m_freeQ_data_1$EN;
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// register m_freeQ_data_2
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reg [1 : 0] m_freeQ_data_2;
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wire [1 : 0] m_freeQ_data_2$D_IN;
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wire m_freeQ_data_2$EN;
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// register m_freeQ_data_3
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reg [1 : 0] m_freeQ_data_3;
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wire [1 : 0] m_freeQ_data_3$D_IN;
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wire m_freeQ_data_3$EN;
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// register m_freeQ_deqP
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reg [1 : 0] m_freeQ_deqP;
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wire [1 : 0] m_freeQ_deqP$D_IN;
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wire m_freeQ_deqP$EN;
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// register m_freeQ_deqReq_rl
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reg m_freeQ_deqReq_rl;
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wire m_freeQ_deqReq_rl$D_IN, m_freeQ_deqReq_rl$EN;
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// register m_freeQ_empty
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reg m_freeQ_empty;
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wire m_freeQ_empty$D_IN, m_freeQ_empty$EN;
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// register m_freeQ_enqP
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reg [1 : 0] m_freeQ_enqP;
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wire [1 : 0] m_freeQ_enqP$D_IN;
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wire m_freeQ_enqP$EN;
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// register m_freeQ_enqReq_rl
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reg [2 : 0] m_freeQ_enqReq_rl;
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wire [2 : 0] m_freeQ_enqReq_rl$D_IN;
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wire m_freeQ_enqReq_rl$EN;
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// register m_freeQ_full
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reg m_freeQ_full;
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wire m_freeQ_full$D_IN, m_freeQ_full$EN;
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// register m_ldTransRsFromPQ_clearReq_rl
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reg m_ldTransRsFromPQ_clearReq_rl;
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wire m_ldTransRsFromPQ_clearReq_rl$D_IN, m_ldTransRsFromPQ_clearReq_rl$EN;
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// register m_ldTransRsFromPQ_data_0
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reg [82 : 0] m_ldTransRsFromPQ_data_0;
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wire [82 : 0] m_ldTransRsFromPQ_data_0$D_IN;
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wire m_ldTransRsFromPQ_data_0$EN;
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// register m_ldTransRsFromPQ_data_1
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reg [82 : 0] m_ldTransRsFromPQ_data_1;
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wire [82 : 0] m_ldTransRsFromPQ_data_1$D_IN;
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wire m_ldTransRsFromPQ_data_1$EN;
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// register m_ldTransRsFromPQ_deqP
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reg m_ldTransRsFromPQ_deqP;
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wire m_ldTransRsFromPQ_deqP$D_IN, m_ldTransRsFromPQ_deqP$EN;
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// register m_ldTransRsFromPQ_deqReq_rl
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reg m_ldTransRsFromPQ_deqReq_rl;
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wire m_ldTransRsFromPQ_deqReq_rl$D_IN, m_ldTransRsFromPQ_deqReq_rl$EN;
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// register m_ldTransRsFromPQ_empty
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reg m_ldTransRsFromPQ_empty;
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wire m_ldTransRsFromPQ_empty$D_IN, m_ldTransRsFromPQ_empty$EN;
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// register m_ldTransRsFromPQ_enqP
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reg m_ldTransRsFromPQ_enqP;
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wire m_ldTransRsFromPQ_enqP$D_IN, m_ldTransRsFromPQ_enqP$EN;
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// register m_ldTransRsFromPQ_enqReq_rl
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reg [83 : 0] m_ldTransRsFromPQ_enqReq_rl;
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wire [83 : 0] m_ldTransRsFromPQ_enqReq_rl$D_IN;
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wire m_ldTransRsFromPQ_enqReq_rl$EN;
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// register m_ldTransRsFromPQ_full
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reg m_ldTransRsFromPQ_full;
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wire m_ldTransRsFromPQ_full$D_IN, m_ldTransRsFromPQ_full$EN;
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// register m_needFlush
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reg m_needFlush;
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wire m_needFlush$D_IN, m_needFlush$EN;
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// register m_pendInst_0
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reg [478 : 0] m_pendInst_0;
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wire [478 : 0] m_pendInst_0$D_IN;
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wire m_pendInst_0$EN;
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// register m_pendInst_1
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reg [478 : 0] m_pendInst_1;
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wire [478 : 0] m_pendInst_1$D_IN;
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wire m_pendInst_1$EN;
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// register m_pendInst_2
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reg [478 : 0] m_pendInst_2;
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wire [478 : 0] m_pendInst_2$D_IN;
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wire m_pendInst_2$EN;
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// register m_pendInst_3
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reg [478 : 0] m_pendInst_3;
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wire [478 : 0] m_pendInst_3$D_IN;
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wire m_pendInst_3$EN;
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// register m_pendPoisoned_0
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reg m_pendPoisoned_0;
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wire m_pendPoisoned_0$D_IN, m_pendPoisoned_0$EN;
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// register m_pendPoisoned_1
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reg m_pendPoisoned_1;
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wire m_pendPoisoned_1$D_IN, m_pendPoisoned_1$EN;
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// register m_pendPoisoned_2
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reg m_pendPoisoned_2;
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wire m_pendPoisoned_2$D_IN, m_pendPoisoned_2$EN;
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|
|
// register m_pendPoisoned_3
|
|
reg m_pendPoisoned_3;
|
|
wire m_pendPoisoned_3$D_IN, m_pendPoisoned_3$EN;
|
|
|
|
// register m_pendResp_0
|
|
reg [69 : 0] m_pendResp_0;
|
|
wire [69 : 0] m_pendResp_0$D_IN;
|
|
wire m_pendResp_0$EN;
|
|
|
|
// register m_pendResp_1
|
|
reg [69 : 0] m_pendResp_1;
|
|
wire [69 : 0] m_pendResp_1$D_IN;
|
|
wire m_pendResp_1$EN;
|
|
|
|
// register m_pendResp_2
|
|
reg [69 : 0] m_pendResp_2;
|
|
wire [69 : 0] m_pendResp_2$D_IN;
|
|
wire m_pendResp_2$EN;
|
|
|
|
// register m_pendResp_3
|
|
reg [69 : 0] m_pendResp_3;
|
|
wire [69 : 0] m_pendResp_3$D_IN;
|
|
wire m_pendResp_3$EN;
|
|
|
|
// register m_pendSpecBits_0_rl
|
|
reg [11 : 0] m_pendSpecBits_0_rl;
|
|
wire [11 : 0] m_pendSpecBits_0_rl$D_IN;
|
|
wire m_pendSpecBits_0_rl$EN;
|
|
|
|
// register m_pendSpecBits_1_rl
|
|
reg [11 : 0] m_pendSpecBits_1_rl;
|
|
wire [11 : 0] m_pendSpecBits_1_rl$D_IN;
|
|
wire m_pendSpecBits_1_rl$EN;
|
|
|
|
// register m_pendSpecBits_2_rl
|
|
reg [11 : 0] m_pendSpecBits_2_rl;
|
|
wire [11 : 0] m_pendSpecBits_2_rl$D_IN;
|
|
wire m_pendSpecBits_2_rl$EN;
|
|
|
|
// register m_pendSpecBits_3_rl
|
|
reg [11 : 0] m_pendSpecBits_3_rl;
|
|
wire [11 : 0] m_pendSpecBits_3_rl$D_IN;
|
|
wire m_pendSpecBits_3_rl$EN;
|
|
|
|
// register m_pendValid_0_rl
|
|
reg m_pendValid_0_rl;
|
|
wire m_pendValid_0_rl$D_IN, m_pendValid_0_rl$EN;
|
|
|
|
// register m_pendValid_1_rl
|
|
reg m_pendValid_1_rl;
|
|
wire m_pendValid_1_rl$D_IN, m_pendValid_1_rl$EN;
|
|
|
|
// register m_pendValid_2_rl
|
|
reg m_pendValid_2_rl;
|
|
wire m_pendValid_2_rl$D_IN, m_pendValid_2_rl$EN;
|
|
|
|
// register m_pendValid_3_rl
|
|
reg m_pendValid_3_rl;
|
|
wire m_pendValid_3_rl$D_IN, m_pendValid_3_rl$EN;
|
|
|
|
// register m_pendWait_0
|
|
reg [3 : 0] m_pendWait_0;
|
|
wire [3 : 0] m_pendWait_0$D_IN;
|
|
wire m_pendWait_0$EN;
|
|
|
|
// register m_pendWait_1
|
|
reg [3 : 0] m_pendWait_1;
|
|
wire [3 : 0] m_pendWait_1$D_IN;
|
|
wire m_pendWait_1$EN;
|
|
|
|
// register m_pendWait_2
|
|
reg [3 : 0] m_pendWait_2;
|
|
wire [3 : 0] m_pendWait_2$D_IN;
|
|
wire m_pendWait_2$EN;
|
|
|
|
// register m_pendWait_3
|
|
reg [3 : 0] m_pendWait_3;
|
|
wire [3 : 0] m_pendWait_3$D_IN;
|
|
wire m_pendWait_3$EN;
|
|
|
|
// register m_perfReqQ_clearReq_rl
|
|
reg m_perfReqQ_clearReq_rl;
|
|
wire m_perfReqQ_clearReq_rl$D_IN, m_perfReqQ_clearReq_rl$EN;
|
|
|
|
// register m_perfReqQ_data_0
|
|
reg [2 : 0] m_perfReqQ_data_0;
|
|
wire [2 : 0] m_perfReqQ_data_0$D_IN;
|
|
wire m_perfReqQ_data_0$EN;
|
|
|
|
// register m_perfReqQ_deqReq_rl
|
|
reg m_perfReqQ_deqReq_rl;
|
|
wire m_perfReqQ_deqReq_rl$D_IN, m_perfReqQ_deqReq_rl$EN;
|
|
|
|
// register m_perfReqQ_empty
|
|
reg m_perfReqQ_empty;
|
|
wire m_perfReqQ_empty$D_IN, m_perfReqQ_empty$EN;
|
|
|
|
// register m_perfReqQ_enqReq_rl
|
|
reg [3 : 0] m_perfReqQ_enqReq_rl;
|
|
wire [3 : 0] m_perfReqQ_enqReq_rl$D_IN;
|
|
wire m_perfReqQ_enqReq_rl$EN;
|
|
|
|
// register m_perfReqQ_full
|
|
reg m_perfReqQ_full;
|
|
wire m_perfReqQ_full$D_IN, m_perfReqQ_full$EN;
|
|
|
|
// register m_respForOtherReq
|
|
reg [2 : 0] m_respForOtherReq;
|
|
wire [2 : 0] m_respForOtherReq$D_IN;
|
|
wire m_respForOtherReq$EN;
|
|
|
|
// register m_rqToPQ_clearReq_rl
|
|
reg m_rqToPQ_clearReq_rl;
|
|
wire m_rqToPQ_clearReq_rl$D_IN, m_rqToPQ_clearReq_rl$EN;
|
|
|
|
// register m_rqToPQ_data_0
|
|
reg [28 : 0] m_rqToPQ_data_0;
|
|
wire [28 : 0] m_rqToPQ_data_0$D_IN;
|
|
wire m_rqToPQ_data_0$EN;
|
|
|
|
// register m_rqToPQ_data_1
|
|
reg [28 : 0] m_rqToPQ_data_1;
|
|
wire [28 : 0] m_rqToPQ_data_1$D_IN;
|
|
wire m_rqToPQ_data_1$EN;
|
|
|
|
// register m_rqToPQ_data_2
|
|
reg [28 : 0] m_rqToPQ_data_2;
|
|
wire [28 : 0] m_rqToPQ_data_2$D_IN;
|
|
wire m_rqToPQ_data_2$EN;
|
|
|
|
// register m_rqToPQ_data_3
|
|
reg [28 : 0] m_rqToPQ_data_3;
|
|
wire [28 : 0] m_rqToPQ_data_3$D_IN;
|
|
wire m_rqToPQ_data_3$EN;
|
|
|
|
// register m_rqToPQ_deqP
|
|
reg [1 : 0] m_rqToPQ_deqP;
|
|
wire [1 : 0] m_rqToPQ_deqP$D_IN;
|
|
wire m_rqToPQ_deqP$EN;
|
|
|
|
// register m_rqToPQ_deqReq_rl
|
|
reg m_rqToPQ_deqReq_rl;
|
|
wire m_rqToPQ_deqReq_rl$D_IN, m_rqToPQ_deqReq_rl$EN;
|
|
|
|
// register m_rqToPQ_empty
|
|
reg m_rqToPQ_empty;
|
|
wire m_rqToPQ_empty$D_IN, m_rqToPQ_empty$EN;
|
|
|
|
// register m_rqToPQ_enqP
|
|
reg [1 : 0] m_rqToPQ_enqP;
|
|
wire [1 : 0] m_rqToPQ_enqP$D_IN;
|
|
wire m_rqToPQ_enqP$EN;
|
|
|
|
// register m_rqToPQ_enqReq_rl
|
|
reg [29 : 0] m_rqToPQ_enqReq_rl;
|
|
wire [29 : 0] m_rqToPQ_enqReq_rl$D_IN;
|
|
wire m_rqToPQ_enqReq_rl$EN;
|
|
|
|
// register m_rqToPQ_full
|
|
reg m_rqToPQ_full;
|
|
wire m_rqToPQ_full$D_IN, m_rqToPQ_full$EN;
|
|
|
|
// register m_tlb_m_entryVec_0
|
|
reg [79 : 0] m_tlb_m_entryVec_0;
|
|
wire [79 : 0] m_tlb_m_entryVec_0$D_IN;
|
|
wire m_tlb_m_entryVec_0$EN;
|
|
|
|
// register m_tlb_m_entryVec_1
|
|
reg [79 : 0] m_tlb_m_entryVec_1;
|
|
wire [79 : 0] m_tlb_m_entryVec_1$D_IN;
|
|
wire m_tlb_m_entryVec_1$EN;
|
|
|
|
// register m_tlb_m_entryVec_10
|
|
reg [79 : 0] m_tlb_m_entryVec_10;
|
|
wire [79 : 0] m_tlb_m_entryVec_10$D_IN;
|
|
wire m_tlb_m_entryVec_10$EN;
|
|
|
|
// register m_tlb_m_entryVec_11
|
|
reg [79 : 0] m_tlb_m_entryVec_11;
|
|
wire [79 : 0] m_tlb_m_entryVec_11$D_IN;
|
|
wire m_tlb_m_entryVec_11$EN;
|
|
|
|
// register m_tlb_m_entryVec_12
|
|
reg [79 : 0] m_tlb_m_entryVec_12;
|
|
wire [79 : 0] m_tlb_m_entryVec_12$D_IN;
|
|
wire m_tlb_m_entryVec_12$EN;
|
|
|
|
// register m_tlb_m_entryVec_13
|
|
reg [79 : 0] m_tlb_m_entryVec_13;
|
|
wire [79 : 0] m_tlb_m_entryVec_13$D_IN;
|
|
wire m_tlb_m_entryVec_13$EN;
|
|
|
|
// register m_tlb_m_entryVec_14
|
|
reg [79 : 0] m_tlb_m_entryVec_14;
|
|
wire [79 : 0] m_tlb_m_entryVec_14$D_IN;
|
|
wire m_tlb_m_entryVec_14$EN;
|
|
|
|
// register m_tlb_m_entryVec_15
|
|
reg [79 : 0] m_tlb_m_entryVec_15;
|
|
wire [79 : 0] m_tlb_m_entryVec_15$D_IN;
|
|
wire m_tlb_m_entryVec_15$EN;
|
|
|
|
// register m_tlb_m_entryVec_16
|
|
reg [79 : 0] m_tlb_m_entryVec_16;
|
|
wire [79 : 0] m_tlb_m_entryVec_16$D_IN;
|
|
wire m_tlb_m_entryVec_16$EN;
|
|
|
|
// register m_tlb_m_entryVec_17
|
|
reg [79 : 0] m_tlb_m_entryVec_17;
|
|
wire [79 : 0] m_tlb_m_entryVec_17$D_IN;
|
|
wire m_tlb_m_entryVec_17$EN;
|
|
|
|
// register m_tlb_m_entryVec_18
|
|
reg [79 : 0] m_tlb_m_entryVec_18;
|
|
wire [79 : 0] m_tlb_m_entryVec_18$D_IN;
|
|
wire m_tlb_m_entryVec_18$EN;
|
|
|
|
// register m_tlb_m_entryVec_19
|
|
reg [79 : 0] m_tlb_m_entryVec_19;
|
|
wire [79 : 0] m_tlb_m_entryVec_19$D_IN;
|
|
wire m_tlb_m_entryVec_19$EN;
|
|
|
|
// register m_tlb_m_entryVec_2
|
|
reg [79 : 0] m_tlb_m_entryVec_2;
|
|
wire [79 : 0] m_tlb_m_entryVec_2$D_IN;
|
|
wire m_tlb_m_entryVec_2$EN;
|
|
|
|
// register m_tlb_m_entryVec_20
|
|
reg [79 : 0] m_tlb_m_entryVec_20;
|
|
wire [79 : 0] m_tlb_m_entryVec_20$D_IN;
|
|
wire m_tlb_m_entryVec_20$EN;
|
|
|
|
// register m_tlb_m_entryVec_21
|
|
reg [79 : 0] m_tlb_m_entryVec_21;
|
|
wire [79 : 0] m_tlb_m_entryVec_21$D_IN;
|
|
wire m_tlb_m_entryVec_21$EN;
|
|
|
|
// register m_tlb_m_entryVec_22
|
|
reg [79 : 0] m_tlb_m_entryVec_22;
|
|
wire [79 : 0] m_tlb_m_entryVec_22$D_IN;
|
|
wire m_tlb_m_entryVec_22$EN;
|
|
|
|
// register m_tlb_m_entryVec_23
|
|
reg [79 : 0] m_tlb_m_entryVec_23;
|
|
wire [79 : 0] m_tlb_m_entryVec_23$D_IN;
|
|
wire m_tlb_m_entryVec_23$EN;
|
|
|
|
// register m_tlb_m_entryVec_24
|
|
reg [79 : 0] m_tlb_m_entryVec_24;
|
|
wire [79 : 0] m_tlb_m_entryVec_24$D_IN;
|
|
wire m_tlb_m_entryVec_24$EN;
|
|
|
|
// register m_tlb_m_entryVec_25
|
|
reg [79 : 0] m_tlb_m_entryVec_25;
|
|
wire [79 : 0] m_tlb_m_entryVec_25$D_IN;
|
|
wire m_tlb_m_entryVec_25$EN;
|
|
|
|
// register m_tlb_m_entryVec_26
|
|
reg [79 : 0] m_tlb_m_entryVec_26;
|
|
wire [79 : 0] m_tlb_m_entryVec_26$D_IN;
|
|
wire m_tlb_m_entryVec_26$EN;
|
|
|
|
// register m_tlb_m_entryVec_27
|
|
reg [79 : 0] m_tlb_m_entryVec_27;
|
|
wire [79 : 0] m_tlb_m_entryVec_27$D_IN;
|
|
wire m_tlb_m_entryVec_27$EN;
|
|
|
|
// register m_tlb_m_entryVec_28
|
|
reg [79 : 0] m_tlb_m_entryVec_28;
|
|
wire [79 : 0] m_tlb_m_entryVec_28$D_IN;
|
|
wire m_tlb_m_entryVec_28$EN;
|
|
|
|
// register m_tlb_m_entryVec_29
|
|
reg [79 : 0] m_tlb_m_entryVec_29;
|
|
wire [79 : 0] m_tlb_m_entryVec_29$D_IN;
|
|
wire m_tlb_m_entryVec_29$EN;
|
|
|
|
// register m_tlb_m_entryVec_3
|
|
reg [79 : 0] m_tlb_m_entryVec_3;
|
|
wire [79 : 0] m_tlb_m_entryVec_3$D_IN;
|
|
wire m_tlb_m_entryVec_3$EN;
|
|
|
|
// register m_tlb_m_entryVec_30
|
|
reg [79 : 0] m_tlb_m_entryVec_30;
|
|
wire [79 : 0] m_tlb_m_entryVec_30$D_IN;
|
|
wire m_tlb_m_entryVec_30$EN;
|
|
|
|
// register m_tlb_m_entryVec_31
|
|
reg [79 : 0] m_tlb_m_entryVec_31;
|
|
wire [79 : 0] m_tlb_m_entryVec_31$D_IN;
|
|
wire m_tlb_m_entryVec_31$EN;
|
|
|
|
// register m_tlb_m_entryVec_4
|
|
reg [79 : 0] m_tlb_m_entryVec_4;
|
|
wire [79 : 0] m_tlb_m_entryVec_4$D_IN;
|
|
wire m_tlb_m_entryVec_4$EN;
|
|
|
|
// register m_tlb_m_entryVec_5
|
|
reg [79 : 0] m_tlb_m_entryVec_5;
|
|
wire [79 : 0] m_tlb_m_entryVec_5$D_IN;
|
|
wire m_tlb_m_entryVec_5$EN;
|
|
|
|
// register m_tlb_m_entryVec_6
|
|
reg [79 : 0] m_tlb_m_entryVec_6;
|
|
wire [79 : 0] m_tlb_m_entryVec_6$D_IN;
|
|
wire m_tlb_m_entryVec_6$EN;
|
|
|
|
// register m_tlb_m_entryVec_7
|
|
reg [79 : 0] m_tlb_m_entryVec_7;
|
|
wire [79 : 0] m_tlb_m_entryVec_7$D_IN;
|
|
wire m_tlb_m_entryVec_7$EN;
|
|
|
|
// register m_tlb_m_entryVec_8
|
|
reg [79 : 0] m_tlb_m_entryVec_8;
|
|
wire [79 : 0] m_tlb_m_entryVec_8$D_IN;
|
|
wire m_tlb_m_entryVec_8$EN;
|
|
|
|
// register m_tlb_m_entryVec_9
|
|
reg [79 : 0] m_tlb_m_entryVec_9;
|
|
wire [79 : 0] m_tlb_m_entryVec_9$D_IN;
|
|
wire m_tlb_m_entryVec_9$EN;
|
|
|
|
// register m_tlb_m_lruBit_rl
|
|
reg [31 : 0] m_tlb_m_lruBit_rl;
|
|
wire [31 : 0] m_tlb_m_lruBit_rl$D_IN;
|
|
wire m_tlb_m_lruBit_rl$EN;
|
|
|
|
// register m_tlb_m_randIdx
|
|
reg [4 : 0] m_tlb_m_randIdx;
|
|
wire [4 : 0] m_tlb_m_randIdx$D_IN;
|
|
wire m_tlb_m_randIdx$EN;
|
|
|
|
// register m_tlb_m_updRepIdx_rl
|
|
reg [5 : 0] m_tlb_m_updRepIdx_rl;
|
|
wire [5 : 0] m_tlb_m_updRepIdx_rl$D_IN;
|
|
wire m_tlb_m_updRepIdx_rl$EN;
|
|
|
|
// register m_tlb_m_validVec_0
|
|
reg m_tlb_m_validVec_0;
|
|
wire m_tlb_m_validVec_0$D_IN, m_tlb_m_validVec_0$EN;
|
|
|
|
// register m_tlb_m_validVec_1
|
|
reg m_tlb_m_validVec_1;
|
|
wire m_tlb_m_validVec_1$D_IN, m_tlb_m_validVec_1$EN;
|
|
|
|
// register m_tlb_m_validVec_10
|
|
reg m_tlb_m_validVec_10;
|
|
wire m_tlb_m_validVec_10$D_IN, m_tlb_m_validVec_10$EN;
|
|
|
|
// register m_tlb_m_validVec_11
|
|
reg m_tlb_m_validVec_11;
|
|
wire m_tlb_m_validVec_11$D_IN, m_tlb_m_validVec_11$EN;
|
|
|
|
// register m_tlb_m_validVec_12
|
|
reg m_tlb_m_validVec_12;
|
|
wire m_tlb_m_validVec_12$D_IN, m_tlb_m_validVec_12$EN;
|
|
|
|
// register m_tlb_m_validVec_13
|
|
reg m_tlb_m_validVec_13;
|
|
wire m_tlb_m_validVec_13$D_IN, m_tlb_m_validVec_13$EN;
|
|
|
|
// register m_tlb_m_validVec_14
|
|
reg m_tlb_m_validVec_14;
|
|
wire m_tlb_m_validVec_14$D_IN, m_tlb_m_validVec_14$EN;
|
|
|
|
// register m_tlb_m_validVec_15
|
|
reg m_tlb_m_validVec_15;
|
|
wire m_tlb_m_validVec_15$D_IN, m_tlb_m_validVec_15$EN;
|
|
|
|
// register m_tlb_m_validVec_16
|
|
reg m_tlb_m_validVec_16;
|
|
wire m_tlb_m_validVec_16$D_IN, m_tlb_m_validVec_16$EN;
|
|
|
|
// register m_tlb_m_validVec_17
|
|
reg m_tlb_m_validVec_17;
|
|
wire m_tlb_m_validVec_17$D_IN, m_tlb_m_validVec_17$EN;
|
|
|
|
// register m_tlb_m_validVec_18
|
|
reg m_tlb_m_validVec_18;
|
|
wire m_tlb_m_validVec_18$D_IN, m_tlb_m_validVec_18$EN;
|
|
|
|
// register m_tlb_m_validVec_19
|
|
reg m_tlb_m_validVec_19;
|
|
wire m_tlb_m_validVec_19$D_IN, m_tlb_m_validVec_19$EN;
|
|
|
|
// register m_tlb_m_validVec_2
|
|
reg m_tlb_m_validVec_2;
|
|
wire m_tlb_m_validVec_2$D_IN, m_tlb_m_validVec_2$EN;
|
|
|
|
// register m_tlb_m_validVec_20
|
|
reg m_tlb_m_validVec_20;
|
|
wire m_tlb_m_validVec_20$D_IN, m_tlb_m_validVec_20$EN;
|
|
|
|
// register m_tlb_m_validVec_21
|
|
reg m_tlb_m_validVec_21;
|
|
wire m_tlb_m_validVec_21$D_IN, m_tlb_m_validVec_21$EN;
|
|
|
|
// register m_tlb_m_validVec_22
|
|
reg m_tlb_m_validVec_22;
|
|
wire m_tlb_m_validVec_22$D_IN, m_tlb_m_validVec_22$EN;
|
|
|
|
// register m_tlb_m_validVec_23
|
|
reg m_tlb_m_validVec_23;
|
|
wire m_tlb_m_validVec_23$D_IN, m_tlb_m_validVec_23$EN;
|
|
|
|
// register m_tlb_m_validVec_24
|
|
reg m_tlb_m_validVec_24;
|
|
wire m_tlb_m_validVec_24$D_IN, m_tlb_m_validVec_24$EN;
|
|
|
|
// register m_tlb_m_validVec_25
|
|
reg m_tlb_m_validVec_25;
|
|
wire m_tlb_m_validVec_25$D_IN, m_tlb_m_validVec_25$EN;
|
|
|
|
// register m_tlb_m_validVec_26
|
|
reg m_tlb_m_validVec_26;
|
|
wire m_tlb_m_validVec_26$D_IN, m_tlb_m_validVec_26$EN;
|
|
|
|
// register m_tlb_m_validVec_27
|
|
reg m_tlb_m_validVec_27;
|
|
wire m_tlb_m_validVec_27$D_IN, m_tlb_m_validVec_27$EN;
|
|
|
|
// register m_tlb_m_validVec_28
|
|
reg m_tlb_m_validVec_28;
|
|
wire m_tlb_m_validVec_28$D_IN, m_tlb_m_validVec_28$EN;
|
|
|
|
// register m_tlb_m_validVec_29
|
|
reg m_tlb_m_validVec_29;
|
|
wire m_tlb_m_validVec_29$D_IN, m_tlb_m_validVec_29$EN;
|
|
|
|
// register m_tlb_m_validVec_3
|
|
reg m_tlb_m_validVec_3;
|
|
wire m_tlb_m_validVec_3$D_IN, m_tlb_m_validVec_3$EN;
|
|
|
|
// register m_tlb_m_validVec_30
|
|
reg m_tlb_m_validVec_30;
|
|
wire m_tlb_m_validVec_30$D_IN, m_tlb_m_validVec_30$EN;
|
|
|
|
// register m_tlb_m_validVec_31
|
|
reg m_tlb_m_validVec_31;
|
|
wire m_tlb_m_validVec_31$D_IN, m_tlb_m_validVec_31$EN;
|
|
|
|
// register m_tlb_m_validVec_4
|
|
reg m_tlb_m_validVec_4;
|
|
wire m_tlb_m_validVec_4$D_IN, m_tlb_m_validVec_4$EN;
|
|
|
|
// register m_tlb_m_validVec_5
|
|
reg m_tlb_m_validVec_5;
|
|
wire m_tlb_m_validVec_5$D_IN, m_tlb_m_validVec_5$EN;
|
|
|
|
// register m_tlb_m_validVec_6
|
|
reg m_tlb_m_validVec_6;
|
|
wire m_tlb_m_validVec_6$D_IN, m_tlb_m_validVec_6$EN;
|
|
|
|
// register m_tlb_m_validVec_7
|
|
reg m_tlb_m_validVec_7;
|
|
wire m_tlb_m_validVec_7$D_IN, m_tlb_m_validVec_7$EN;
|
|
|
|
// register m_tlb_m_validVec_8
|
|
reg m_tlb_m_validVec_8;
|
|
wire m_tlb_m_validVec_8$D_IN, m_tlb_m_validVec_8$EN;
|
|
|
|
// register m_tlb_m_validVec_9
|
|
reg m_tlb_m_validVec_9;
|
|
wire m_tlb_m_validVec_9$D_IN, m_tlb_m_validVec_9$EN;
|
|
|
|
// register m_vm_info
|
|
reg [48 : 0] m_vm_info;
|
|
wire [48 : 0] m_vm_info$D_IN;
|
|
wire m_vm_info$EN;
|
|
|
|
// register m_waitFlushP
|
|
reg m_waitFlushP;
|
|
wire m_waitFlushP$D_IN, m_waitFlushP$EN;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_doFinishFlush,
|
|
CAN_FIRE_RL_m_doInitFreeQ,
|
|
CAN_FIRE_RL_m_doPRs,
|
|
CAN_FIRE_RL_m_doPoisonedProcResp,
|
|
CAN_FIRE_RL_m_doStartFlush,
|
|
CAN_FIRE_RL_m_flushRqToPQ_canonicalize,
|
|
CAN_FIRE_RL_m_flushRqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_flushRqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_flushRqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_flushRsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_m_flushRsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_flushRsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_flushRsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_freeQ_canonicalize,
|
|
CAN_FIRE_RL_m_freeQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_freeQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_freeQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_ldTransRsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_pendSpecBits_0_canon,
|
|
CAN_FIRE_RL_m_pendSpecBits_1_canon,
|
|
CAN_FIRE_RL_m_pendSpecBits_2_canon,
|
|
CAN_FIRE_RL_m_pendSpecBits_3_canon,
|
|
CAN_FIRE_RL_m_pendValid_0_canon,
|
|
CAN_FIRE_RL_m_pendValid_1_canon,
|
|
CAN_FIRE_RL_m_pendValid_2_canon,
|
|
CAN_FIRE_RL_m_pendValid_3_canon,
|
|
CAN_FIRE_RL_m_perfReqQ_canonicalize,
|
|
CAN_FIRE_RL_m_perfReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_perfReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_perfReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_rqToPQ_canonicalize,
|
|
CAN_FIRE_RL_m_rqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_rqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_rqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_tlb_m_doUpdateRep,
|
|
CAN_FIRE_RL_m_tlb_m_incRandIdx,
|
|
CAN_FIRE_RL_m_tlb_m_lruBit_canon,
|
|
CAN_FIRE_RL_m_tlb_m_updRepIdx_canon,
|
|
CAN_FIRE_deqProcResp,
|
|
CAN_FIRE_flush,
|
|
CAN_FIRE_perf_req,
|
|
CAN_FIRE_perf_resp,
|
|
CAN_FIRE_perf_setStatus,
|
|
CAN_FIRE_procReq,
|
|
CAN_FIRE_specUpdate_correctSpeculation,
|
|
CAN_FIRE_specUpdate_incorrectSpeculation,
|
|
CAN_FIRE_toParent_flush_request_get,
|
|
CAN_FIRE_toParent_flush_response_put,
|
|
CAN_FIRE_toParent_ldTransRsFromP_enq,
|
|
CAN_FIRE_toParent_rqToP_deq,
|
|
CAN_FIRE_updateVMInfo,
|
|
WILL_FIRE_RL_m_doFinishFlush,
|
|
WILL_FIRE_RL_m_doInitFreeQ,
|
|
WILL_FIRE_RL_m_doPRs,
|
|
WILL_FIRE_RL_m_doPoisonedProcResp,
|
|
WILL_FIRE_RL_m_doStartFlush,
|
|
WILL_FIRE_RL_m_flushRqToPQ_canonicalize,
|
|
WILL_FIRE_RL_m_flushRqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_flushRqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_flushRqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_flushRsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_m_flushRsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_flushRsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_flushRsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_freeQ_canonicalize,
|
|
WILL_FIRE_RL_m_freeQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_freeQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_freeQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_ldTransRsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_pendSpecBits_0_canon,
|
|
WILL_FIRE_RL_m_pendSpecBits_1_canon,
|
|
WILL_FIRE_RL_m_pendSpecBits_2_canon,
|
|
WILL_FIRE_RL_m_pendSpecBits_3_canon,
|
|
WILL_FIRE_RL_m_pendValid_0_canon,
|
|
WILL_FIRE_RL_m_pendValid_1_canon,
|
|
WILL_FIRE_RL_m_pendValid_2_canon,
|
|
WILL_FIRE_RL_m_pendValid_3_canon,
|
|
WILL_FIRE_RL_m_perfReqQ_canonicalize,
|
|
WILL_FIRE_RL_m_perfReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_perfReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_perfReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_rqToPQ_canonicalize,
|
|
WILL_FIRE_RL_m_rqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_rqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_rqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_tlb_m_doUpdateRep,
|
|
WILL_FIRE_RL_m_tlb_m_incRandIdx,
|
|
WILL_FIRE_RL_m_tlb_m_lruBit_canon,
|
|
WILL_FIRE_RL_m_tlb_m_updRepIdx_canon,
|
|
WILL_FIRE_deqProcResp,
|
|
WILL_FIRE_flush,
|
|
WILL_FIRE_perf_req,
|
|
WILL_FIRE_perf_resp,
|
|
WILL_FIRE_perf_setStatus,
|
|
WILL_FIRE_procReq,
|
|
WILL_FIRE_specUpdate_correctSpeculation,
|
|
WILL_FIRE_specUpdate_incorrectSpeculation,
|
|
WILL_FIRE_toParent_flush_request_get,
|
|
WILL_FIRE_toParent_flush_response_put,
|
|
WILL_FIRE_toParent_ldTransRsFromP_enq,
|
|
WILL_FIRE_toParent_rqToP_deq,
|
|
WILL_FIRE_updateVMInfo;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [69 : 0] MUX_m_pendResp_0$write_1__VAL_1,
|
|
MUX_m_pendResp_0$write_1__VAL_2,
|
|
MUX_m_pendResp_1$write_1__VAL_1,
|
|
MUX_m_pendResp_1$write_1__VAL_2,
|
|
MUX_m_pendResp_2$write_1__VAL_1,
|
|
MUX_m_pendResp_2$write_1__VAL_2,
|
|
MUX_m_pendResp_3$write_1__VAL_1,
|
|
MUX_m_pendResp_3$write_1__VAL_2;
|
|
wire [31 : 0] MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1;
|
|
wire [5 : 0] MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1,
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2;
|
|
wire [3 : 0] MUX_m_pendWait_0$write_1__VAL_1,
|
|
MUX_m_pendWait_0$write_1__VAL_2,
|
|
MUX_m_pendWait_1$write_1__VAL_1,
|
|
MUX_m_pendWait_2$write_1__VAL_1,
|
|
MUX_m_pendWait_3$write_1__VAL_1;
|
|
wire [2 : 0] MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2,
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3;
|
|
wire MUX_m_pendPoisoned_0$write_1__SEL_1,
|
|
MUX_m_pendPoisoned_0$write_1__SEL_2,
|
|
MUX_m_pendPoisoned_1$write_1__SEL_1,
|
|
MUX_m_pendPoisoned_1$write_1__SEL_2,
|
|
MUX_m_pendPoisoned_2$write_1__SEL_1,
|
|
MUX_m_pendPoisoned_2$write_1__SEL_2,
|
|
MUX_m_pendPoisoned_3$write_1__SEL_1,
|
|
MUX_m_pendPoisoned_3$write_1__SEL_2,
|
|
MUX_m_pendResp_0$write_1__SEL_1,
|
|
MUX_m_pendResp_1$write_1__SEL_1,
|
|
MUX_m_pendResp_2$write_1__SEL_1,
|
|
MUX_m_pendResp_3$write_1__SEL_1,
|
|
MUX_m_pendWait_0$write_1__SEL_1,
|
|
MUX_m_pendWait_1$write_1__SEL_1,
|
|
MUX_m_pendWait_2$write_1__SEL_1,
|
|
MUX_m_pendWait_3$write_1__SEL_1,
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_0$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_1$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_10$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_11$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_12$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_13$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_14$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_15$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_16$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_17$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_18$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_19$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_2$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_20$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_21$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_22$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_23$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_24$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_25$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_26$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_27$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_28$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_29$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_3$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_30$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_31$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_4$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_5$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_6$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_7$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_8$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_9$write_1__SEL_1,
|
|
MUX_m_waitFlushP$write_1__SEL_1;
|
|
|
|
// remaining internal signals
|
|
reg [65 : 0] SEL_ARR_m_pendInst_0_85_BITS_440_TO_375_739_m__ETC___d2969,
|
|
x__h70397;
|
|
reg [64 : 0] x__h98589, x__h98616;
|
|
reg [63 : 0] x__h92718, x__h98552, x__h98607;
|
|
reg [55 : 0] x__h70310, x__h90434;
|
|
reg [43 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653,
|
|
ppn__h90430;
|
|
reg [26 : 0] CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q2,
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11,
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12,
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13,
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14,
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15,
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16,
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17,
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18,
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19,
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20,
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1,
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21,
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22,
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23,
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24,
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25,
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26,
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27,
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28,
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29,
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30,
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q3,
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31,
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32,
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4,
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5,
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6,
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7,
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8,
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9,
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703,
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_28_TO_2_249_m_ETC___d3257;
|
|
reg [17 : 0] SEL_ARR_m_pendInst_0_85_BITS_341_TO_324_072_m__ETC___d3077;
|
|
reg [13 : 0] SEL_ARR_m_pendInst_0_85_BITS_374_TO_361_970_m__ETC___d2975,
|
|
x__h98052,
|
|
x__h98061;
|
|
reg [11 : 0] SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3233;
|
|
reg [5 : 0] SEL_ARR_m_pendInst_0_85_BITS_135_TO_130_200_m__ETC___d3205,
|
|
SEL_ARR_m_pendInst_0_85_BITS_276_TO_271_163_m__ETC___d3168,
|
|
SEL_ARR_m_pendInst_0_85_BITS_322_TO_317_084_m__ETC___d3089,
|
|
SEL_ARR_m_pendInst_0_85_BITS_469_TO_464_827_m__ETC___d2832;
|
|
reg [4 : 0] CASE_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_8_ETC__q35,
|
|
CASE_procReq_req_BITS_490_TO_488_1_15_3_15_4_1_ETC__q36,
|
|
SEL_ARR_m_pendInst_0_85_BITS_270_TO_266_169_m__ETC___d3174,
|
|
SEL_ARR_m_pendInst_0_85_BITS_462_TO_458_845_m__ETC___d2850,
|
|
SEL_ARR_m_pendInst_0_85_BITS_474_TO_470_821_m__ETC___d2826,
|
|
SEL_ARR_m_pendResp_0_777_BITS_4_TO_0_806_m_pen_ETC___d2811;
|
|
reg [3 : 0] SEL_ARR_m_pendInst_0_85_BITS_360_TO_357_976_m__ETC___d2981,
|
|
SEL_ARR_m_pendInst_0_85_BITS_461_TO_458_851_m__ETC___d2856;
|
|
reg [2 : 0] SEL_ARR_m_pendInst_0_85_BITS_288_TO_286_107_m__ETC___d3112,
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d2814,
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594;
|
|
reg [1 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577,
|
|
SEL_ARR_m_pendInst_0_85_BITS_280_TO_279_137_m__ETC___d3142,
|
|
SEL_ARR_m_pendInst_0_85_BITS_282_TO_281_131_m__ETC___d3136,
|
|
SEL_ARR_m_pendInst_0_85_BITS_343_TO_342_066_m__ETC___d3071,
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_1_TO_0_258_m__ETC___d3263,
|
|
idx__h73608,
|
|
level__h38292,
|
|
level__h85474;
|
|
reg CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q33,
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q34,
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d605,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d612,
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_265_177_178_NO_ETC___d3186,
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_277_152_153_NO_ETC___d3161,
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_835_NO_ETC___d2843,
|
|
SEL_ARR_NOT_m_pendResp_0_777_BIT_5_795_796_NOT_ETC___d2804,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_18_m_ETC___d680,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_65_m_ETC___d668,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_34_m_ETC___d637,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714,
|
|
SEL_ARR_m_pendInst_0_85_BIT_0_218_m_pendInst_1_ETC___d3223,
|
|
SEL_ARR_m_pendInst_0_85_BIT_278_146_m_pendInst_ETC___d3151,
|
|
SEL_ARR_m_pendInst_0_85_BIT_283_125_m_pendInst_ETC___d3130,
|
|
SEL_ARR_m_pendInst_0_85_BIT_284_119_m_pendInst_ETC___d3124,
|
|
SEL_ARR_m_pendInst_0_85_BIT_285_113_m_pendInst_ETC___d3118,
|
|
SEL_ARR_m_pendInst_0_85_BIT_323_078_m_pendInst_ETC___d3083,
|
|
SEL_ARR_m_pendInst_0_85_BIT_344_060_m_pendInst_ETC___d3065,
|
|
SEL_ARR_m_pendInst_0_85_BIT_345_048_m_pendInst_ETC___d3053,
|
|
SEL_ARR_m_pendInst_0_85_BIT_346_042_m_pendInst_ETC___d3047,
|
|
SEL_ARR_m_pendInst_0_85_BIT_347_036_m_pendInst_ETC___d3041,
|
|
SEL_ARR_m_pendInst_0_85_BIT_348_030_m_pendInst_ETC___d3035,
|
|
SEL_ARR_m_pendInst_0_85_BIT_349_024_m_pendInst_ETC___d3029,
|
|
SEL_ARR_m_pendInst_0_85_BIT_350_018_m_pendInst_ETC___d3023,
|
|
SEL_ARR_m_pendInst_0_85_BIT_351_012_m_pendInst_ETC___d3017,
|
|
SEL_ARR_m_pendInst_0_85_BIT_352_006_m_pendInst_ETC___d3011,
|
|
SEL_ARR_m_pendInst_0_85_BIT_353_000_m_pendInst_ETC___d3005,
|
|
SEL_ARR_m_pendInst_0_85_BIT_354_994_m_pendInst_ETC___d2999,
|
|
SEL_ARR_m_pendInst_0_85_BIT_355_988_m_pendInst_ETC___d2993,
|
|
SEL_ARR_m_pendInst_0_85_BIT_356_982_m_pendInst_ETC___d2987,
|
|
SEL_ARR_m_pendInst_0_85_BIT_441_963_m_pendInst_ETC___d2968,
|
|
SEL_ARR_m_pendInst_0_85_BIT_442_956_m_pendInst_ETC___d2961,
|
|
SEL_ARR_m_pendInst_0_85_BIT_443_950_m_pendInst_ETC___d2955,
|
|
SEL_ARR_m_pendInst_0_85_BIT_444_943_m_pendInst_ETC___d2948,
|
|
SEL_ARR_m_pendInst_0_85_BIT_445_937_m_pendInst_ETC___d2942,
|
|
SEL_ARR_m_pendInst_0_85_BIT_446_930_m_pendInst_ETC___d2935,
|
|
SEL_ARR_m_pendInst_0_85_BIT_447_924_m_pendInst_ETC___d2929,
|
|
SEL_ARR_m_pendInst_0_85_BIT_448_917_m_pendInst_ETC___d2922,
|
|
SEL_ARR_m_pendInst_0_85_BIT_449_911_m_pendInst_ETC___d2916,
|
|
SEL_ARR_m_pendInst_0_85_BIT_450_904_m_pendInst_ETC___d2909,
|
|
SEL_ARR_m_pendInst_0_85_BIT_451_898_m_pendInst_ETC___d2903,
|
|
SEL_ARR_m_pendInst_0_85_BIT_452_891_m_pendInst_ETC___d2896,
|
|
SEL_ARR_m_pendInst_0_85_BIT_453_885_m_pendInst_ETC___d2890,
|
|
SEL_ARR_m_pendInst_0_85_BIT_454_878_m_pendInst_ETC___d2883,
|
|
SEL_ARR_m_pendInst_0_85_BIT_455_872_m_pendInst_ETC___d2877,
|
|
SEL_ARR_m_pendInst_0_85_BIT_456_865_m_pendInst_ETC___d2870,
|
|
SEL_ARR_m_pendInst_0_85_BIT_457_859_m_pendInst_ETC___d2864,
|
|
SEL_ARR_m_pendInst_0_85_BIT_475_815_m_pendInst_ETC___d2820,
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579,
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650,
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641,
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522,
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558;
|
|
wire [463 : 0] NOT_SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_83_ETC___d3230;
|
|
wire [69 : 0] DONTCARE_CONCAT_1_CONCAT_IF_SEL_ARR_m_pendInst_ETC___d1766,
|
|
DONTCARE_CONCAT_1_CONCAT_IF_procReq_req_BITS_4_ETC___d2716;
|
|
wire [63 : 0] x__h70301, x__h90425;
|
|
wire [31 : 0] INV_n__read0928__q37,
|
|
n__read__h50928,
|
|
upd__h50955,
|
|
val__h5329,
|
|
x__h5387;
|
|
wire [11 : 0] n__read__h100423,
|
|
n__read__h100554,
|
|
n__read__h100685,
|
|
n__read__h100816,
|
|
upd__h10027,
|
|
upd__h8992,
|
|
upd__h9337,
|
|
upd__h9682;
|
|
wire [8 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_10_00__ETC___d1733;
|
|
wire [5 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_9_07_m_ETC___d1732;
|
|
wire [4 : 0] IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2322,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2324,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2326,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2328,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2330,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2332,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2334,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2336,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2338,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2340,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2342,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2344,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2346,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2348,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2350,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27,
|
|
IF_m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec__ETC___d1425,
|
|
IF_m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec__ETC___d1426,
|
|
IF_m_tlb_m_validVec_12_96_AND_m_tlb_m_validVec_ETC___d1415,
|
|
IF_m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_ETC___d1410,
|
|
IF_m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_ETC___d1411,
|
|
IF_m_tlb_m_validVec_20_024_AND_m_tlb_m_validVe_ETC___d1407,
|
|
IF_m_tlb_m_validVec_24_088_AND_m_tlb_m_validVe_ETC___d1403,
|
|
IF_m_tlb_m_validVec_24_088_AND_m_tlb_m_validVe_ETC___d1404,
|
|
IF_m_tlb_m_validVec_28_152_AND_m_tlb_m_validVe_ETC___d1400,
|
|
IF_m_tlb_m_validVec_4_68_AND_m_tlb_m_validVec__ETC___d1422,
|
|
IF_m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec__ETC___d1418,
|
|
IF_m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec__ETC___d1419,
|
|
addIdx__h55557,
|
|
addIdx__h60407,
|
|
idx__h85435,
|
|
v__h45375,
|
|
v__h50192,
|
|
v__h51720;
|
|
wire [3 : 0] _2_CONCAT_IF_NOT_m_pendWait_0_269_BITS_3_TO_2_2_ETC___d2749,
|
|
_dfoo26,
|
|
_dfoo28,
|
|
_dfoo30,
|
|
_dfoo32;
|
|
wire [1 : 0] IF_NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_2_ETC___d2747,
|
|
IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1799,
|
|
_theResult_____2__h13508,
|
|
_theResult_____2__h17468,
|
|
idx__h37917,
|
|
idx__h73220,
|
|
idx__h93065,
|
|
next_deqP___1__h13697,
|
|
next_deqP___1__h17657,
|
|
v__h13028,
|
|
v__h13179,
|
|
v__h16896,
|
|
v__h17047,
|
|
x_id__h21371;
|
|
wire IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2647,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2655,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2697,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2704,
|
|
IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_ETC___d2644,
|
|
IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_ETC___d2652,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172,
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357,
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260,
|
|
IF_NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_ETC___d1613,
|
|
IF_NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_ETC___d690,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1829,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1830,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1831,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3238,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3239,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3240,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2216,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2217,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2218,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2219,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2220,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2221,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2222,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2223,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2224,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2225,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2226,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2227,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2228,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2229,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2230,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2231,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2232,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2233,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2234,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2235,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2236,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2237,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2238,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2239,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2240,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2241,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2242,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2243,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2244,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2245,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_ldTra_ETC___d1264,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1663,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1665,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1667,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1669,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1671,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1673,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1675,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1677,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1679,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1681,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1683,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1685,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1687,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1689,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1691,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1693,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1695,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1697,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1699,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1701,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1703,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1705,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1707,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1709,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1711,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1713,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1715,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1717,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1719,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1721,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1723,
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1725,
|
|
IF_NOT_m_tlb_m_validVec_10_64_65_OR_NOT_m_tlb__ETC___d1244,
|
|
IF_NOT_m_tlb_m_validVec_11_80_81_OR_NOT_m_tlb__ETC___d1242,
|
|
IF_NOT_m_tlb_m_validVec_12_96_97_OR_NOT_m_tlb__ETC___d1240,
|
|
IF_NOT_m_tlb_m_validVec_13_12_13_OR_NOT_m_tlb__ETC___d1238,
|
|
IF_NOT_m_tlb_m_validVec_14_28_29_OR_NOT_m_tlb__ETC___d1236,
|
|
IF_NOT_m_tlb_m_validVec_15_44_45_OR_NOT_m_tlb__ETC___d1234,
|
|
IF_NOT_m_tlb_m_validVec_16_60_61_OR_NOT_m_tlb__ETC___d1232,
|
|
IF_NOT_m_tlb_m_validVec_17_76_77_OR_NOT_m_tlb__ETC___d1230,
|
|
IF_NOT_m_tlb_m_validVec_18_92_93_OR_NOT_m_tlb__ETC___d1228,
|
|
IF_NOT_m_tlb_m_validVec_19_008_009_OR_NOT_m_tl_ETC___d1226,
|
|
IF_NOT_m_tlb_m_validVec_1_20_21_OR_NOT_m_tlb_m_ETC___d1262,
|
|
IF_NOT_m_tlb_m_validVec_20_024_025_OR_NOT_m_tl_ETC___d1224,
|
|
IF_NOT_m_tlb_m_validVec_21_040_041_OR_NOT_m_tl_ETC___d1222,
|
|
IF_NOT_m_tlb_m_validVec_22_056_057_OR_NOT_m_tl_ETC___d1220,
|
|
IF_NOT_m_tlb_m_validVec_23_072_073_OR_NOT_m_tl_ETC___d1218,
|
|
IF_NOT_m_tlb_m_validVec_24_088_089_OR_NOT_m_tl_ETC___d1216,
|
|
IF_NOT_m_tlb_m_validVec_25_104_105_OR_NOT_m_tl_ETC___d1214,
|
|
IF_NOT_m_tlb_m_validVec_26_120_121_OR_NOT_m_tl_ETC___d1212,
|
|
IF_NOT_m_tlb_m_validVec_27_136_137_OR_NOT_m_tl_ETC___d1210,
|
|
IF_NOT_m_tlb_m_validVec_28_152_153_OR_NOT_m_tl_ETC___d1208,
|
|
IF_NOT_m_tlb_m_validVec_29_168_169_OR_NOT_m_tl_ETC___d1206,
|
|
IF_NOT_m_tlb_m_validVec_2_36_37_OR_NOT_m_tlb_m_ETC___d1260,
|
|
IF_NOT_m_tlb_m_validVec_30_184_185_OR_NOT_m_tl_ETC___d1204,
|
|
IF_NOT_m_tlb_m_validVec_3_52_53_OR_NOT_m_tlb_m_ETC___d1258,
|
|
IF_NOT_m_tlb_m_validVec_4_68_69_OR_NOT_m_tlb_m_ETC___d1256,
|
|
IF_NOT_m_tlb_m_validVec_5_84_85_OR_NOT_m_tlb_m_ETC___d1254,
|
|
IF_NOT_m_tlb_m_validVec_6_00_01_OR_NOT_m_tlb_m_ETC___d1252,
|
|
IF_NOT_m_tlb_m_validVec_7_16_17_OR_NOT_m_tlb_m_ETC___d1250,
|
|
IF_NOT_m_tlb_m_validVec_8_32_33_OR_NOT_m_tlb_m_ETC___d1248,
|
|
IF_NOT_m_tlb_m_validVec_9_48_49_OR_NOT_m_tlb_m_ETC___d1246,
|
|
IF_NOT_procReq_req_BITS_490_TO_488_247_EQ_1_24_ETC___d2657,
|
|
IF_NOT_procReq_req_BITS_490_TO_488_247_EQ_1_24_ETC___d2706,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1604,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1611,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d677,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d688,
|
|
IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134,
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108,
|
|
IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333,
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284,
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291,
|
|
IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1320,
|
|
IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1337,
|
|
IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493,
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1738,
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1758,
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1759,
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1761,
|
|
IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222,
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196,
|
|
IF_m_tlb_m_entryVec_10_67_BITS_1_TO_0_71_EQ_0__ETC___d1974,
|
|
IF_m_tlb_m_entryVec_11_83_BITS_1_TO_0_87_EQ_0__ETC___d1984,
|
|
IF_m_tlb_m_entryVec_12_99_BITS_1_TO_0_03_EQ_0__ETC___d1994,
|
|
IF_m_tlb_m_entryVec_13_15_BITS_1_TO_0_19_EQ_0__ETC___d2004,
|
|
IF_m_tlb_m_entryVec_14_31_BITS_1_TO_0_35_EQ_0__ETC___d2014,
|
|
IF_m_tlb_m_entryVec_15_47_BITS_1_TO_0_51_EQ_0__ETC___d2024,
|
|
IF_m_tlb_m_entryVec_16_63_BITS_1_TO_0_67_EQ_0__ETC___d2034,
|
|
IF_m_tlb_m_entryVec_17_79_BITS_1_TO_0_83_EQ_0__ETC___d2044,
|
|
IF_m_tlb_m_entryVec_18_95_BITS_1_TO_0_99_EQ_0__ETC___d2054,
|
|
IF_m_tlb_m_entryVec_19_011_BITS_1_TO_0_015_EQ__ETC___d2064,
|
|
IF_m_tlb_m_entryVec_1_23_BITS_1_TO_0_27_EQ_0_8_ETC___d1884,
|
|
IF_m_tlb_m_entryVec_20_027_BITS_1_TO_0_031_EQ__ETC___d2074,
|
|
IF_m_tlb_m_entryVec_21_043_BITS_1_TO_0_047_EQ__ETC___d2084,
|
|
IF_m_tlb_m_entryVec_22_059_BITS_1_TO_0_063_EQ__ETC___d2094,
|
|
IF_m_tlb_m_entryVec_23_075_BITS_1_TO_0_079_EQ__ETC___d2104,
|
|
IF_m_tlb_m_entryVec_24_091_BITS_1_TO_0_095_EQ__ETC___d2114,
|
|
IF_m_tlb_m_entryVec_25_107_BITS_1_TO_0_111_EQ__ETC___d2124,
|
|
IF_m_tlb_m_entryVec_26_123_BITS_1_TO_0_127_EQ__ETC___d2134,
|
|
IF_m_tlb_m_entryVec_27_139_BITS_1_TO_0_143_EQ__ETC___d2144,
|
|
IF_m_tlb_m_entryVec_28_155_BITS_1_TO_0_159_EQ__ETC___d2154,
|
|
IF_m_tlb_m_entryVec_29_171_BITS_1_TO_0_175_EQ__ETC___d2164,
|
|
IF_m_tlb_m_entryVec_2_39_BITS_1_TO_0_43_EQ_0_8_ETC___d1894,
|
|
IF_m_tlb_m_entryVec_30_187_BITS_1_TO_0_191_EQ__ETC___d2174,
|
|
IF_m_tlb_m_entryVec_31_616_BITS_1_TO_0_620_EQ__ETC___d2184,
|
|
IF_m_tlb_m_entryVec_3_55_BITS_1_TO_0_59_EQ_0_8_ETC___d1904,
|
|
IF_m_tlb_m_entryVec_4_71_BITS_1_TO_0_75_EQ_0_9_ETC___d1914,
|
|
IF_m_tlb_m_entryVec_5_87_BITS_1_TO_0_91_EQ_0_9_ETC___d1924,
|
|
IF_m_tlb_m_entryVec_6_03_BITS_1_TO_0_07_EQ_0_9_ETC___d1934,
|
|
IF_m_tlb_m_entryVec_7_19_BITS_1_TO_0_23_EQ_0_9_ETC___d1944,
|
|
IF_m_tlb_m_entryVec_8_35_BITS_1_TO_0_39_EQ_0_9_ETC___d1954,
|
|
IF_m_tlb_m_entryVec_9_51_BITS_1_TO_0_55_EQ_0_9_ETC___d1964,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17,
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT__ETC___d2694,
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT__ETC___d2701,
|
|
NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BI_ETC___d1605,
|
|
NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_42_ETC___d2648,
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d673,
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d685,
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1615,
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660,
|
|
NOT_m_ldTransRsFromPQ_empty_68_96_AND_NOT_m_pe_ETC___d1318,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1818,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1822,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2788,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2790,
|
|
NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271__ETC___d1782,
|
|
NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271__ETC___d1796,
|
|
NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_272__ETC___d2745,
|
|
NOT_m_tlb_m_entryVec_0_98_BITS_79_TO_53_99_EQ__ETC___d717,
|
|
NOT_m_tlb_m_entryVec_10_67_BITS_79_TO_53_68_EQ_ETC___d878,
|
|
NOT_m_tlb_m_entryVec_11_83_BITS_79_TO_53_84_EQ_ETC___d894,
|
|
NOT_m_tlb_m_entryVec_12_99_BITS_79_TO_53_00_EQ_ETC___d910,
|
|
NOT_m_tlb_m_entryVec_13_15_BITS_79_TO_53_16_EQ_ETC___d926,
|
|
NOT_m_tlb_m_entryVec_14_31_BITS_79_TO_53_32_EQ_ETC___d942,
|
|
NOT_m_tlb_m_entryVec_15_47_BITS_79_TO_53_48_EQ_ETC___d958,
|
|
NOT_m_tlb_m_entryVec_16_63_BITS_79_TO_53_64_EQ_ETC___d974,
|
|
NOT_m_tlb_m_entryVec_17_79_BITS_79_TO_53_80_EQ_ETC___d990,
|
|
NOT_m_tlb_m_entryVec_18_95_BITS_79_TO_53_96_EQ_ETC___d1006,
|
|
NOT_m_tlb_m_entryVec_19_011_BITS_79_TO_53_012__ETC___d1022,
|
|
NOT_m_tlb_m_entryVec_1_23_BITS_79_TO_53_24_EQ__ETC___d734,
|
|
NOT_m_tlb_m_entryVec_20_027_BITS_79_TO_53_028__ETC___d1038,
|
|
NOT_m_tlb_m_entryVec_21_043_BITS_79_TO_53_044__ETC___d1054,
|
|
NOT_m_tlb_m_entryVec_22_059_BITS_79_TO_53_060__ETC___d1070,
|
|
NOT_m_tlb_m_entryVec_23_075_BITS_79_TO_53_076__ETC___d1086,
|
|
NOT_m_tlb_m_entryVec_24_091_BITS_79_TO_53_092__ETC___d1102,
|
|
NOT_m_tlb_m_entryVec_25_107_BITS_79_TO_53_108__ETC___d1118,
|
|
NOT_m_tlb_m_entryVec_26_123_BITS_79_TO_53_124__ETC___d1134,
|
|
NOT_m_tlb_m_entryVec_27_139_BITS_79_TO_53_140__ETC___d1150,
|
|
NOT_m_tlb_m_entryVec_28_155_BITS_79_TO_53_156__ETC___d1166,
|
|
NOT_m_tlb_m_entryVec_29_171_BITS_79_TO_53_172__ETC___d1182,
|
|
NOT_m_tlb_m_entryVec_2_39_BITS_79_TO_53_40_EQ__ETC___d750,
|
|
NOT_m_tlb_m_entryVec_30_187_BITS_79_TO_53_188__ETC___d1198,
|
|
NOT_m_tlb_m_entryVec_3_55_BITS_79_TO_53_56_EQ__ETC___d766,
|
|
NOT_m_tlb_m_entryVec_4_71_BITS_79_TO_53_72_EQ__ETC___d782,
|
|
NOT_m_tlb_m_entryVec_5_87_BITS_79_TO_53_88_EQ__ETC___d798,
|
|
NOT_m_tlb_m_entryVec_6_03_BITS_79_TO_53_04_EQ__ETC___d814,
|
|
NOT_m_tlb_m_entryVec_7_19_BITS_79_TO_53_20_EQ__ETC___d830,
|
|
NOT_m_tlb_m_entryVec_8_35_BITS_79_TO_53_36_EQ__ETC___d846,
|
|
NOT_m_tlb_m_entryVec_9_51_BITS_79_TO_53_52_EQ__ETC___d862,
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d693,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1877,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1897,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1917,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1937,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1957,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1977,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1997,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2017,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2037,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2057,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2077,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2097,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2117,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2137,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2157,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2177,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756,
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_va_ETC___d1347,
|
|
NOT_m_tlb_m_validVec_11_80_81_OR_NOT_m_tlb_m_e_ETC___d1648,
|
|
NOT_m_tlb_m_validVec_13_12_13_OR_NOT_m_tlb_m_e_ETC___d1646,
|
|
NOT_m_tlb_m_validVec_15_44_45_OR_NOT_m_tlb_m_e_ETC___d1644,
|
|
NOT_m_tlb_m_validVec_16_60_61_OR_NOT_m_tlb_m_v_ETC___d1362,
|
|
NOT_m_tlb_m_validVec_17_76_77_OR_NOT_m_tlb_m_e_ETC___d1642,
|
|
NOT_m_tlb_m_validVec_19_008_009_OR_NOT_m_tlb_m_ETC___d1640,
|
|
NOT_m_tlb_m_validVec_1_20_21_OR_NOT_m_tlb_m_en_ETC___d1658,
|
|
NOT_m_tlb_m_validVec_21_040_041_OR_NOT_m_tlb_m_ETC___d1638,
|
|
NOT_m_tlb_m_validVec_23_072_073_OR_NOT_m_tlb_m_ETC___d1636,
|
|
NOT_m_tlb_m_validVec_24_088_089_OR_NOT_m_tlb_m_ETC___d1369,
|
|
NOT_m_tlb_m_validVec_25_104_105_OR_NOT_m_tlb_m_ETC___d1634,
|
|
NOT_m_tlb_m_validVec_27_136_137_OR_NOT_m_tlb_m_ETC___d1632,
|
|
NOT_m_tlb_m_validVec_29_168_169_OR_NOT_m_tlb_m_ETC___d1630,
|
|
NOT_m_tlb_m_validVec_3_52_53_OR_NOT_m_tlb_m_en_ETC___d1656,
|
|
NOT_m_tlb_m_validVec_5_84_85_OR_NOT_m_tlb_m_en_ETC___d1654,
|
|
NOT_m_tlb_m_validVec_7_16_17_OR_NOT_m_tlb_m_en_ETC___d1652,
|
|
NOT_m_tlb_m_validVec_8_32_33_OR_NOT_m_tlb_m_va_ETC___d1354,
|
|
NOT_m_tlb_m_validVec_9_48_49_OR_NOT_m_tlb_m_en_ETC___d1650,
|
|
NOT_procReq_req_BITS_490_TO_488_247_EQ_1_248_2_ETC___d2659,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d678,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2698,
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2663,
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2664,
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2665,
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2666,
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2711,
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2712,
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2713,
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2714,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d1600,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d1608,
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d692,
|
|
_dfoo1,
|
|
_dfoo11,
|
|
_dfoo13,
|
|
_dfoo15,
|
|
_dfoo25,
|
|
_dfoo27,
|
|
_dfoo29,
|
|
_dfoo3,
|
|
_dfoo31,
|
|
_dfoo49,
|
|
_dfoo5,
|
|
_dfoo51,
|
|
_dfoo53,
|
|
_dfoo55,
|
|
_dfoo57,
|
|
_dfoo59,
|
|
_dfoo61,
|
|
_dfoo63,
|
|
_dfoo7,
|
|
_dfoo9,
|
|
_theResult_____2__h22136,
|
|
m_pendWait_0_269_BITS_1_TO_0_289_EQ_SEL_ARR_m__ETC___d1290,
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1288,
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1297,
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1323,
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_272_AND__ETC___d2730,
|
|
m_pendWait_1_275_BITS_1_TO_0_281_EQ_SEL_ARR_m__ETC___d1282,
|
|
m_pendWait_1_275_BITS_3_TO_2_276_EQ_0_277_OR_m_ETC___d1286,
|
|
m_pendWait_2_299_BITS_1_TO_0_305_EQ_SEL_ARR_m__ETC___d1306,
|
|
m_pendWait_3_325_BITS_1_TO_0_331_EQ_SEL_ARR_m__ETC___d1332,
|
|
m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec_1_2_ETC___d1378,
|
|
m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_17_ETC___d1393,
|
|
m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec_9_4_ETC___d1385,
|
|
next_deqP___1__h22325,
|
|
procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2721,
|
|
procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2724,
|
|
procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2728,
|
|
procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2732,
|
|
procReq_req_BITS_490_TO_488_247_EQ_1_248_OR_pr_ETC___d2708,
|
|
v__h21066,
|
|
v__h21217;
|
|
|
|
// value method flush_done
|
|
assign flush_done = !m_needFlush ;
|
|
assign RDY_flush_done = 1'd1 ;
|
|
|
|
// action method flush
|
|
assign RDY_flush = !m_needFlush ;
|
|
assign CAN_FIRE_flush = !m_needFlush ;
|
|
assign WILL_FIRE_flush = EN_flush ;
|
|
|
|
// action method updateVMInfo
|
|
assign RDY_updateVMInfo = 1'd1 ;
|
|
assign CAN_FIRE_updateVMInfo = 1'd1 ;
|
|
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
|
|
|
|
// value method noPendingReq
|
|
assign noPendingReq =
|
|
!m_pendValid_0_rl && !m_pendValid_1_rl && !m_pendValid_2_rl &&
|
|
!m_pendValid_3_rl ;
|
|
assign RDY_noPendingReq = 1'd1 ;
|
|
|
|
// action method procReq
|
|
assign RDY_procReq =
|
|
!m_freeQ_empty && !m_needFlush && m_ldTransRsFromPQ_empty &&
|
|
!m_rqToPQ_full &&
|
|
m_freeQInited &&
|
|
(!m_vm_info[46] ||
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d693) ;
|
|
assign CAN_FIRE_procReq = RDY_procReq ;
|
|
assign WILL_FIRE_procReq = EN_procReq ;
|
|
|
|
// value method procResp
|
|
assign procResp =
|
|
{ x__h92718,
|
|
!SEL_ARR_NOT_m_pendResp_0_777_BIT_5_795_796_NOT_ETC___d2804,
|
|
SEL_ARR_m_pendResp_0_777_BITS_4_TO_0_806_m_pen_ETC___d2811,
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d2814,
|
|
SEL_ARR_m_pendInst_0_85_BIT_475_815_m_pendInst_ETC___d2820,
|
|
SEL_ARR_m_pendInst_0_85_BITS_474_TO_470_821_m__ETC___d2826,
|
|
SEL_ARR_m_pendInst_0_85_BITS_469_TO_464_827_m__ETC___d2832,
|
|
NOT_SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_83_ETC___d3230,
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3233 } ;
|
|
assign RDY_procResp =
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3240 &&
|
|
m_freeQInited ;
|
|
|
|
// action method deqProcResp
|
|
assign RDY_deqProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3240 &&
|
|
m_freeQInited ;
|
|
assign CAN_FIRE_deqProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3240 &&
|
|
m_freeQInited ;
|
|
assign WILL_FIRE_deqProcResp = EN_deqProcResp ;
|
|
|
|
// value method toParent_rqToP_notEmpty
|
|
assign toParent_rqToP_notEmpty = !m_rqToPQ_empty ;
|
|
assign RDY_toParent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method toParent_rqToP_deq
|
|
assign RDY_toParent_rqToP_deq = !m_rqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_rqToP_deq = !m_rqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_rqToP_deq = EN_toParent_rqToP_deq ;
|
|
|
|
// value method toParent_rqToP_first
|
|
assign toParent_rqToP_first =
|
|
{ SEL_ARR_m_rqToPQ_data_0_248_BITS_28_TO_2_249_m_ETC___d3257,
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_1_TO_0_258_m__ETC___d3263 } ;
|
|
assign RDY_toParent_rqToP_first = !m_rqToPQ_empty ;
|
|
|
|
// value method toParent_ldTransRsFromP_notFull
|
|
assign toParent_ldTransRsFromP_notFull = !m_ldTransRsFromPQ_full ;
|
|
assign RDY_toParent_ldTransRsFromP_notFull = 1'd1 ;
|
|
|
|
// action method toParent_ldTransRsFromP_enq
|
|
assign RDY_toParent_ldTransRsFromP_enq = !m_ldTransRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_ldTransRsFromP_enq = !m_ldTransRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_ldTransRsFromP_enq =
|
|
EN_toParent_ldTransRsFromP_enq ;
|
|
|
|
// action method toParent_flush_request_get
|
|
assign RDY_toParent_flush_request_get = !m_flushRqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_flush_request_get = !m_flushRqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_flush_request_get =
|
|
EN_toParent_flush_request_get ;
|
|
|
|
// action method toParent_flush_response_put
|
|
assign RDY_toParent_flush_response_put = !m_flushRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_flush_response_put = !m_flushRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_flush_response_put =
|
|
EN_toParent_flush_response_put ;
|
|
|
|
// action method specUpdate_incorrectSpeculation
|
|
assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_specUpdate_incorrectSpeculation =
|
|
EN_specUpdate_incorrectSpeculation ;
|
|
|
|
// action method specUpdate_correctSpeculation
|
|
assign RDY_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_specUpdate_correctSpeculation =
|
|
EN_specUpdate_correctSpeculation ;
|
|
|
|
// action method perf_setStatus
|
|
assign RDY_perf_setStatus = 1'd1 ;
|
|
assign CAN_FIRE_perf_setStatus = 1'd1 ;
|
|
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
|
|
|
|
// action method perf_req
|
|
assign RDY_perf_req = !m_perfReqQ_full ;
|
|
assign CAN_FIRE_perf_req = !m_perfReqQ_full ;
|
|
assign WILL_FIRE_perf_req = EN_perf_req ;
|
|
|
|
// actionvalue method perf_resp
|
|
assign perf_resp = { m_perfReqQ_data_0, 64'd0 } ;
|
|
assign RDY_perf_resp = !m_perfReqQ_empty ;
|
|
assign CAN_FIRE_perf_resp = !m_perfReqQ_empty ;
|
|
assign WILL_FIRE_perf_resp = EN_perf_resp ;
|
|
|
|
// value method perf_respValid
|
|
assign perf_respValid = !m_perfReqQ_empty ;
|
|
assign RDY_perf_respValid = 1'd1 ;
|
|
|
|
// rule RL_m_doStartFlush
|
|
assign CAN_FIRE_RL_m_doStartFlush =
|
|
!m_flushRqToPQ_full && m_needFlush && !m_waitFlushP &&
|
|
!m_pendValid_0_rl &&
|
|
!m_pendValid_1_rl &&
|
|
!m_pendValid_2_rl &&
|
|
!m_pendValid_3_rl ;
|
|
assign WILL_FIRE_RL_m_doStartFlush = CAN_FIRE_RL_m_doStartFlush ;
|
|
|
|
// rule RL_m_doFinishFlush
|
|
assign CAN_FIRE_RL_m_doFinishFlush =
|
|
!m_flushRsFromPQ_empty && m_needFlush && m_waitFlushP ;
|
|
assign WILL_FIRE_RL_m_doFinishFlush = CAN_FIRE_RL_m_doFinishFlush ;
|
|
|
|
// rule RL_m_doInitFreeQ
|
|
assign CAN_FIRE_RL_m_doInitFreeQ = !m_freeQ_full && !m_freeQInited ;
|
|
assign WILL_FIRE_RL_m_doInitFreeQ = CAN_FIRE_RL_m_doInitFreeQ ;
|
|
|
|
// rule RL_m_doPoisonedProcResp
|
|
assign CAN_FIRE_RL_m_doPoisonedProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1831 &&
|
|
m_freeQInited ;
|
|
assign WILL_FIRE_RL_m_doPoisonedProcResp =
|
|
CAN_FIRE_RL_m_doPoisonedProcResp &&
|
|
!EN_specUpdate_incorrectSpeculation &&
|
|
!EN_deqProcResp ;
|
|
|
|
// rule RL_m_tlb_m_doUpdateRep
|
|
assign CAN_FIRE_RL_m_tlb_m_doUpdateRep =
|
|
!CAN_FIRE_RL_m_doStartFlush && m_tlb_m_updRepIdx_rl[5] ;
|
|
assign WILL_FIRE_RL_m_tlb_m_doUpdateRep =
|
|
CAN_FIRE_RL_m_tlb_m_doUpdateRep && !WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// rule RL_m_doPRs
|
|
assign CAN_FIRE_RL_m_doPRs =
|
|
(SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 ||
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ||
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d692 ||
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d693 &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_ldTra_ETC___d1264) &&
|
|
IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1320 &&
|
|
IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1337 &&
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign WILL_FIRE_RL_m_doPRs =
|
|
CAN_FIRE_RL_m_doPRs && !WILL_FIRE_RL_m_doStartFlush &&
|
|
!EN_specUpdate_incorrectSpeculation ;
|
|
|
|
// rule RL_m_tlb_m_incRandIdx
|
|
assign CAN_FIRE_RL_m_tlb_m_incRandIdx = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_incRandIdx = 1'd1 ;
|
|
|
|
// rule RL_m_tlb_m_lruBit_canon
|
|
assign CAN_FIRE_RL_m_tlb_m_lruBit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_lruBit_canon = 1'd1 ;
|
|
|
|
// rule RL_m_tlb_m_updRepIdx_canon
|
|
assign CAN_FIRE_RL_m_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_0_canon
|
|
assign CAN_FIRE_RL_m_pendValid_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_1_canon
|
|
assign CAN_FIRE_RL_m_pendValid_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_2_canon
|
|
assign CAN_FIRE_RL_m_pendValid_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_3_canon
|
|
assign CAN_FIRE_RL_m_pendValid_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_0_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_1_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_2_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_3_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_canonicalize
|
|
assign CAN_FIRE_RL_m_freeQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_m_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_pendPoisoned_0$write_1__SEL_1 =
|
|
EN_procReq && idx__h73608 == 2'd0 ;
|
|
assign MUX_m_pendPoisoned_0$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_1$write_1__SEL_1 =
|
|
EN_procReq && idx__h73608 == 2'd1 ;
|
|
assign MUX_m_pendPoisoned_1$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_1_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_2$write_1__SEL_1 =
|
|
EN_procReq && idx__h73608 == 2'd2 ;
|
|
assign MUX_m_pendPoisoned_2$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_2_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_3$write_1__SEL_1 =
|
|
EN_procReq && idx__h73608 == 2'd3 ;
|
|
assign MUX_m_pendPoisoned_3$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_3_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendResp_0$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo15 ;
|
|
assign MUX_m_pendResp_1$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo13 ;
|
|
assign MUX_m_pendResp_2$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo11 ;
|
|
assign MUX_m_pendResp_3$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo9 ;
|
|
assign MUX_m_pendWait_0$write_1__SEL_1 = EN_procReq && _dfoo63 ;
|
|
assign MUX_m_pendWait_1$write_1__SEL_1 = EN_procReq && _dfoo61 ;
|
|
assign MUX_m_pendWait_2$write_1__SEL_1 = EN_procReq && _dfoo59 ;
|
|
assign MUX_m_pendWait_3$write_1__SEL_1 = EN_procReq && _dfoo57 ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign MUX_m_tlb_m_validVec_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1663 ;
|
|
assign MUX_m_tlb_m_validVec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1665 ;
|
|
assign MUX_m_tlb_m_validVec_10$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1683 ;
|
|
assign MUX_m_tlb_m_validVec_11$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1685 ;
|
|
assign MUX_m_tlb_m_validVec_12$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1687 ;
|
|
assign MUX_m_tlb_m_validVec_13$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1689 ;
|
|
assign MUX_m_tlb_m_validVec_14$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1691 ;
|
|
assign MUX_m_tlb_m_validVec_15$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1693 ;
|
|
assign MUX_m_tlb_m_validVec_16$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1695 ;
|
|
assign MUX_m_tlb_m_validVec_17$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1697 ;
|
|
assign MUX_m_tlb_m_validVec_18$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1699 ;
|
|
assign MUX_m_tlb_m_validVec_19$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1701 ;
|
|
assign MUX_m_tlb_m_validVec_2$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1667 ;
|
|
assign MUX_m_tlb_m_validVec_20$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1703 ;
|
|
assign MUX_m_tlb_m_validVec_21$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1705 ;
|
|
assign MUX_m_tlb_m_validVec_22$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1707 ;
|
|
assign MUX_m_tlb_m_validVec_23$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1709 ;
|
|
assign MUX_m_tlb_m_validVec_24$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1711 ;
|
|
assign MUX_m_tlb_m_validVec_25$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1713 ;
|
|
assign MUX_m_tlb_m_validVec_26$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1715 ;
|
|
assign MUX_m_tlb_m_validVec_27$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1717 ;
|
|
assign MUX_m_tlb_m_validVec_28$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1719 ;
|
|
assign MUX_m_tlb_m_validVec_29$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1721 ;
|
|
assign MUX_m_tlb_m_validVec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1669 ;
|
|
assign MUX_m_tlb_m_validVec_30$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1723 ;
|
|
assign MUX_m_tlb_m_validVec_31$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1725 ;
|
|
assign MUX_m_tlb_m_validVec_4$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1671 ;
|
|
assign MUX_m_tlb_m_validVec_5$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1673 ;
|
|
assign MUX_m_tlb_m_validVec_6$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1675 ;
|
|
assign MUX_m_tlb_m_validVec_7$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1677 ;
|
|
assign MUX_m_tlb_m_validVec_8$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1679 ;
|
|
assign MUX_m_tlb_m_validVec_9$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1681 ;
|
|
assign MUX_m_waitFlushP$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doFinishFlush || EN_flush ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, m_freeQInitIdx } ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, idx__h73220 } ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, idx__h93065 } ;
|
|
assign MUX_m_pendResp_0$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1738 ?
|
|
{ x__h70301, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_SEL_ARR_m_pendInst_ETC___d1766 ;
|
|
assign MUX_m_pendResp_0$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2663 ?
|
|
{ x__h90425, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
(SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2711 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_procReq_req_BITS_4_ETC___d2716 :
|
|
{ procReq_req[450:387],
|
|
1'd0,
|
|
5'bxxxxx /* unspecified value */ }) ;
|
|
assign MUX_m_pendResp_1$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1758 ?
|
|
{ x__h70301, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_SEL_ARR_m_pendInst_ETC___d1766 ;
|
|
assign MUX_m_pendResp_1$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2664 ?
|
|
{ x__h90425, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
(SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2712 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_procReq_req_BITS_4_ETC___d2716 :
|
|
{ procReq_req[450:387],
|
|
1'd0,
|
|
5'bxxxxx /* unspecified value */ }) ;
|
|
assign MUX_m_pendResp_2$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1759 ?
|
|
{ x__h70301, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_SEL_ARR_m_pendInst_ETC___d1766 ;
|
|
assign MUX_m_pendResp_2$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2665 ?
|
|
{ x__h90425, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
(SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2713 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_procReq_req_BITS_4_ETC___d2716 :
|
|
{ procReq_req[450:387],
|
|
1'd0,
|
|
5'bxxxxx /* unspecified value */ }) ;
|
|
assign MUX_m_pendResp_3$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1761 ?
|
|
{ x__h70301, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_SEL_ARR_m_pendInst_ETC___d1766 ;
|
|
assign MUX_m_pendResp_3$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2666 ?
|
|
{ x__h90425, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
(SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2714 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_procReq_req_BITS_4_ETC___d2716 :
|
|
{ procReq_req[450:387],
|
|
1'd0,
|
|
5'bxxxxx /* unspecified value */ }) ;
|
|
assign MUX_m_pendWait_0$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2663 ?
|
|
{ 2'd0, 2'bxx /* unspecified value */ } :
|
|
(SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2711 ?
|
|
{ 2'd0, 2'bxx /* unspecified value */ } :
|
|
_dfoo32) ;
|
|
assign MUX_m_pendWait_0$write_1__VAL_2 =
|
|
{ 2'd0, 2'bxx /* unspecified value */ } ;
|
|
assign MUX_m_pendWait_1$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2664 ?
|
|
{ 2'd0, 2'bxx /* unspecified value */ } :
|
|
(SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2712 ?
|
|
{ 2'd0, 2'bxx /* unspecified value */ } :
|
|
_dfoo30) ;
|
|
assign MUX_m_pendWait_2$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2665 ?
|
|
{ 2'd0, 2'bxx /* unspecified value */ } :
|
|
(SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2713 ?
|
|
{ 2'd0, 2'bxx /* unspecified value */ } :
|
|
_dfoo28) ;
|
|
assign MUX_m_pendWait_3$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2666 ?
|
|
{ 2'd0, 2'bxx /* unspecified value */ } :
|
|
(SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2714 ?
|
|
{ 2'd0, 2'bxx /* unspecified value */ } :
|
|
_dfoo26) ;
|
|
assign MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1 =
|
|
(val__h5329 == 32'hFFFFFFFF) ? x__h5387 : val__h5329 ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, v__h45375 } ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, idx__h85435 } ;
|
|
|
|
// inlined wires
|
|
assign m_tlb_m_lruBit_lat_0$whas =
|
|
WILL_FIRE_RL_m_tlb_m_doUpdateRep || WILL_FIRE_RL_m_doStartFlush ;
|
|
assign m_tlb_m_updRepIdx_lat_0$wget =
|
|
{ 1'd0, 5'bxxxxx /* unspecified value */ } ;
|
|
assign m_tlb_m_updRepIdx_lat_0$whas =
|
|
WILL_FIRE_RL_m_doStartFlush || WILL_FIRE_RL_m_tlb_m_doUpdateRep ;
|
|
assign m_tlb_m_updRepIdx_lat_1$wget =
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 ?
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 :
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 ;
|
|
assign m_tlb_m_updRepIdx_lat_1$whas =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ||
|
|
EN_procReq && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
NOT_procReq_req_BITS_490_TO_488_247_EQ_1_248_2_ETC___d2659 ;
|
|
assign m_pendValid_0_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h73220 == 2'd0 ||
|
|
EN_deqProcResp && idx__h93065 == 2'd0 ;
|
|
assign m_pendValid_1_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h73220 == 2'd1 ||
|
|
EN_deqProcResp && idx__h93065 == 2'd1 ;
|
|
assign m_pendValid_2_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h73220 == 2'd2 ||
|
|
EN_deqProcResp && idx__h93065 == 2'd2 ;
|
|
assign m_pendValid_3_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h73220 == 2'd3 ||
|
|
EN_deqProcResp && idx__h93065 == 2'd3 ;
|
|
always@(WILL_FIRE_RL_m_doInitFreeQ or
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1 or
|
|
WILL_FIRE_RL_m_doPoisonedProcResp or
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2 or
|
|
EN_deqProcResp or MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_m_doInitFreeQ:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1;
|
|
WILL_FIRE_RL_m_doPoisonedProcResp:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2;
|
|
EN_deqProcResp:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3;
|
|
default: m_freeQ_enqReq_lat_0$wget = 3'bxxx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign m_freeQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_m_doInitFreeQ ||
|
|
WILL_FIRE_RL_m_doPoisonedProcResp ||
|
|
EN_deqProcResp ;
|
|
assign m_freeQ_enqReq_lat_2$wget =
|
|
{ 1'd0, 2'bxx /* unspecified value */ } ;
|
|
assign m_rqToPQ_enqReq_lat_0$wget =
|
|
{ 1'd1, procReq_req[425:399], idx__h73608 } ;
|
|
assign m_rqToPQ_enqReq_lat_0$whas =
|
|
EN_procReq && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756 ;
|
|
assign m_rqToPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
29'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign m_ldTransRsFromPQ_enqReq_lat_0$wget =
|
|
{ 1'd1, toParent_ldTransRsFromP_enq_x } ;
|
|
assign m_ldTransRsFromPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
83'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign m_ldTransRsFromPQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1323 &&
|
|
(m_pendWait_3[3:2] == 2'd0 || m_pendWait_3[3:2] == 2'd1 ||
|
|
!m_pendWait_3_325_BITS_1_TO_0_331_EQ_SEL_ARR_m__ETC___d1332 ||
|
|
idx__h37917 == 2'd3) ;
|
|
assign m_perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
assign m_perfReqQ_enqReq_lat_2$wget =
|
|
{ 1'd0, 3'bxxx /* unspecified value */ } ;
|
|
|
|
// register m_flushRqToPQ_clearReq_rl
|
|
assign m_flushRqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_deqReq_rl
|
|
assign m_flushRqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_empty
|
|
assign m_flushRqToPQ_empty$D_IN =
|
|
m_flushRqToPQ_clearReq_rl ||
|
|
!CAN_FIRE_RL_m_doStartFlush && !m_flushRqToPQ_enqReq_rl &&
|
|
(EN_toParent_flush_request_get || m_flushRqToPQ_deqReq_rl ||
|
|
m_flushRqToPQ_empty) ;
|
|
assign m_flushRqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_enqReq_rl
|
|
assign m_flushRqToPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_full
|
|
assign m_flushRqToPQ_full$D_IN =
|
|
!m_flushRqToPQ_clearReq_rl &&
|
|
(CAN_FIRE_RL_m_doStartFlush || m_flushRqToPQ_enqReq_rl ||
|
|
!EN_toParent_flush_request_get && !m_flushRqToPQ_deqReq_rl &&
|
|
m_flushRqToPQ_full) ;
|
|
assign m_flushRqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_clearReq_rl
|
|
assign m_flushRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_deqReq_rl
|
|
assign m_flushRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_empty
|
|
assign m_flushRsFromPQ_empty$D_IN =
|
|
m_flushRsFromPQ_clearReq_rl ||
|
|
!EN_toParent_flush_response_put && !m_flushRsFromPQ_enqReq_rl &&
|
|
(CAN_FIRE_RL_m_doFinishFlush || m_flushRsFromPQ_deqReq_rl ||
|
|
m_flushRsFromPQ_empty) ;
|
|
assign m_flushRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_enqReq_rl
|
|
assign m_flushRsFromPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_full
|
|
assign m_flushRsFromPQ_full$D_IN =
|
|
!m_flushRsFromPQ_clearReq_rl &&
|
|
(EN_toParent_flush_response_put || m_flushRsFromPQ_enqReq_rl ||
|
|
!CAN_FIRE_RL_m_doFinishFlush && !m_flushRsFromPQ_deqReq_rl &&
|
|
m_flushRsFromPQ_full) ;
|
|
assign m_flushRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_freeQInitIdx
|
|
assign m_freeQInitIdx$D_IN = m_freeQInitIdx + 2'd1 ;
|
|
assign m_freeQInitIdx$EN = CAN_FIRE_RL_m_doInitFreeQ ;
|
|
|
|
// register m_freeQInited
|
|
assign m_freeQInited$D_IN = 1'd1 ;
|
|
assign m_freeQInited$EN =
|
|
WILL_FIRE_RL_m_doInitFreeQ && m_freeQInitIdx == 2'd3 ;
|
|
|
|
// register m_freeQ_clearReq_rl
|
|
assign m_freeQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_freeQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_data_0
|
|
assign m_freeQ_data_0$D_IN =
|
|
m_freeQ_enqReq_lat_0$whas ?
|
|
m_freeQ_enqReq_lat_0$wget[1:0] :
|
|
m_freeQ_enqReq_rl[1:0] ;
|
|
assign m_freeQ_data_0$EN =
|
|
m_freeQ_enqP == 2'd0 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_1
|
|
assign m_freeQ_data_1$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_1$EN =
|
|
m_freeQ_enqP == 2'd1 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_2
|
|
assign m_freeQ_data_2$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_2$EN =
|
|
m_freeQ_enqP == 2'd2 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_3
|
|
assign m_freeQ_data_3$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_3$EN =
|
|
m_freeQ_enqP == 2'd3 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_deqP
|
|
assign m_freeQ_deqP$D_IN =
|
|
m_freeQ_clearReq_rl ? 2'd0 : _theResult_____2__h13508 ;
|
|
assign m_freeQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_deqReq_rl
|
|
assign m_freeQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_freeQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_empty
|
|
assign m_freeQ_empty$D_IN =
|
|
m_freeQ_clearReq_rl ||
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172 ;
|
|
assign m_freeQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_enqP
|
|
assign m_freeQ_enqP$D_IN = m_freeQ_clearReq_rl ? 2'd0 : v__h13028 ;
|
|
assign m_freeQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_enqReq_rl
|
|
assign m_freeQ_enqReq_rl$D_IN = m_freeQ_enqReq_lat_2$wget ;
|
|
assign m_freeQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_full
|
|
assign m_freeQ_full$D_IN =
|
|
!m_freeQ_clearReq_rl &&
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167 ;
|
|
assign m_freeQ_full$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_clearReq_rl
|
|
assign m_ldTransRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_ldTransRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_data_0
|
|
assign m_ldTransRsFromPQ_data_0$D_IN =
|
|
{ IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 ||
|
|
(EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[82] :
|
|
m_ldTransRsFromPQ_enqReq_rl[82]),
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[81:2] :
|
|
m_ldTransRsFromPQ_enqReq_rl[81:2],
|
|
x_id__h21371 } ;
|
|
assign m_ldTransRsFromPQ_data_0$EN =
|
|
m_ldTransRsFromPQ_enqP == 1'd0 &&
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ;
|
|
|
|
// register m_ldTransRsFromPQ_data_1
|
|
assign m_ldTransRsFromPQ_data_1$D_IN = m_ldTransRsFromPQ_data_0$D_IN ;
|
|
assign m_ldTransRsFromPQ_data_1$EN =
|
|
m_ldTransRsFromPQ_enqP == 1'd1 &&
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ;
|
|
|
|
// register m_ldTransRsFromPQ_deqP
|
|
assign m_ldTransRsFromPQ_deqP$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl && _theResult_____2__h22136 ;
|
|
assign m_ldTransRsFromPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_deqReq_rl
|
|
assign m_ldTransRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_ldTransRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_empty
|
|
assign m_ldTransRsFromPQ_empty$D_IN =
|
|
m_ldTransRsFromPQ_clearReq_rl ||
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 &&
|
|
(IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 ||
|
|
m_ldTransRsFromPQ_empty) ;
|
|
assign m_ldTransRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_enqP
|
|
assign m_ldTransRsFromPQ_enqP$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl && v__h21066 ;
|
|
assign m_ldTransRsFromPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_enqReq_rl
|
|
assign m_ldTransRsFromPQ_enqReq_rl$D_IN =
|
|
m_ldTransRsFromPQ_enqReq_lat_2$wget ;
|
|
assign m_ldTransRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_full
|
|
assign m_ldTransRsFromPQ_full$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366 ;
|
|
assign m_ldTransRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_needFlush
|
|
assign m_needFlush$D_IN = !WILL_FIRE_RL_m_doFinishFlush ;
|
|
assign m_needFlush$EN = MUX_m_waitFlushP$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_0
|
|
assign m_pendInst_0$D_IN = procReq_req[490:12] ;
|
|
assign m_pendInst_0$EN = MUX_m_pendPoisoned_0$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_1
|
|
assign m_pendInst_1$D_IN = procReq_req[490:12] ;
|
|
assign m_pendInst_1$EN = MUX_m_pendPoisoned_1$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_2
|
|
assign m_pendInst_2$D_IN = procReq_req[490:12] ;
|
|
assign m_pendInst_2$EN = MUX_m_pendPoisoned_2$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_3
|
|
assign m_pendInst_3$D_IN = procReq_req[490:12] ;
|
|
assign m_pendInst_3$EN = MUX_m_pendPoisoned_3$write_1__SEL_1 ;
|
|
|
|
// register m_pendPoisoned_0
|
|
assign m_pendPoisoned_0$D_IN = !MUX_m_pendPoisoned_0$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_0$EN =
|
|
EN_procReq && idx__h73608 == 2'd0 ||
|
|
MUX_m_pendPoisoned_0$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_1
|
|
assign m_pendPoisoned_1$D_IN = !MUX_m_pendPoisoned_1$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_1$EN =
|
|
EN_procReq && idx__h73608 == 2'd1 ||
|
|
MUX_m_pendPoisoned_1$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_2
|
|
assign m_pendPoisoned_2$D_IN = !MUX_m_pendPoisoned_2$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_2$EN =
|
|
EN_procReq && idx__h73608 == 2'd2 ||
|
|
MUX_m_pendPoisoned_2$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_3
|
|
assign m_pendPoisoned_3$D_IN = !MUX_m_pendPoisoned_3$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_3$EN =
|
|
EN_procReq && idx__h73608 == 2'd3 ||
|
|
MUX_m_pendPoisoned_3$write_1__SEL_2 ;
|
|
|
|
// register m_pendResp_0
|
|
assign m_pendResp_0$D_IN =
|
|
MUX_m_pendResp_0$write_1__SEL_1 ?
|
|
MUX_m_pendResp_0$write_1__VAL_1 :
|
|
MUX_m_pendResp_0$write_1__VAL_2 ;
|
|
assign m_pendResp_0$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo15 || EN_procReq && _dfoo55 ;
|
|
|
|
// register m_pendResp_1
|
|
assign m_pendResp_1$D_IN =
|
|
MUX_m_pendResp_1$write_1__SEL_1 ?
|
|
MUX_m_pendResp_1$write_1__VAL_1 :
|
|
MUX_m_pendResp_1$write_1__VAL_2 ;
|
|
assign m_pendResp_1$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo13 || EN_procReq && _dfoo53 ;
|
|
|
|
// register m_pendResp_2
|
|
assign m_pendResp_2$D_IN =
|
|
MUX_m_pendResp_2$write_1__SEL_1 ?
|
|
MUX_m_pendResp_2$write_1__VAL_1 :
|
|
MUX_m_pendResp_2$write_1__VAL_2 ;
|
|
assign m_pendResp_2$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo11 || EN_procReq && _dfoo51 ;
|
|
|
|
// register m_pendResp_3
|
|
assign m_pendResp_3$D_IN =
|
|
MUX_m_pendResp_3$write_1__SEL_1 ?
|
|
MUX_m_pendResp_3$write_1__VAL_1 :
|
|
MUX_m_pendResp_3$write_1__VAL_2 ;
|
|
assign m_pendResp_3$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo9 || EN_procReq && _dfoo49 ;
|
|
|
|
// register m_pendSpecBits_0_rl
|
|
assign m_pendSpecBits_0_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h8992 :
|
|
n__read__h100423 ;
|
|
assign m_pendSpecBits_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_1_rl
|
|
assign m_pendSpecBits_1_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h9337 :
|
|
n__read__h100554 ;
|
|
assign m_pendSpecBits_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_2_rl
|
|
assign m_pendSpecBits_2_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h9682 :
|
|
n__read__h100685 ;
|
|
assign m_pendSpecBits_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_3_rl
|
|
assign m_pendSpecBits_3_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h10027 :
|
|
n__read__h100816 ;
|
|
assign m_pendSpecBits_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_0_rl
|
|
assign m_pendValid_0_rl$D_IN =
|
|
MUX_m_pendPoisoned_0$write_1__SEL_1 ||
|
|
(m_pendValid_0_lat_0$whas ? 1'd0 : m_pendValid_0_rl) ;
|
|
assign m_pendValid_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_1_rl
|
|
assign m_pendValid_1_rl$D_IN =
|
|
MUX_m_pendPoisoned_1$write_1__SEL_1 ||
|
|
(m_pendValid_1_lat_0$whas ? 1'd0 : m_pendValid_1_rl) ;
|
|
assign m_pendValid_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_2_rl
|
|
assign m_pendValid_2_rl$D_IN =
|
|
MUX_m_pendPoisoned_2$write_1__SEL_1 ||
|
|
(m_pendValid_2_lat_0$whas ? 1'd0 : m_pendValid_2_rl) ;
|
|
assign m_pendValid_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_3_rl
|
|
assign m_pendValid_3_rl$D_IN =
|
|
MUX_m_pendPoisoned_3$write_1__SEL_1 ||
|
|
(m_pendValid_3_lat_0$whas ? 1'd0 : m_pendValid_3_rl) ;
|
|
assign m_pendValid_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendWait_0
|
|
assign m_pendWait_0$D_IN =
|
|
MUX_m_pendWait_0$write_1__SEL_1 ?
|
|
MUX_m_pendWait_0$write_1__VAL_1 :
|
|
MUX_m_pendWait_0$write_1__VAL_2 ;
|
|
assign m_pendWait_0$EN =
|
|
EN_procReq && _dfoo63 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd0 ;
|
|
|
|
// register m_pendWait_1
|
|
assign m_pendWait_1$D_IN =
|
|
MUX_m_pendWait_1$write_1__SEL_1 ?
|
|
MUX_m_pendWait_1$write_1__VAL_1 :
|
|
MUX_m_pendWait_0$write_1__VAL_2 ;
|
|
assign m_pendWait_1$EN =
|
|
EN_procReq && _dfoo61 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd1 ;
|
|
|
|
// register m_pendWait_2
|
|
assign m_pendWait_2$D_IN =
|
|
MUX_m_pendWait_2$write_1__SEL_1 ?
|
|
MUX_m_pendWait_2$write_1__VAL_1 :
|
|
MUX_m_pendWait_0$write_1__VAL_2 ;
|
|
assign m_pendWait_2$EN =
|
|
EN_procReq && _dfoo59 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd2 ;
|
|
|
|
// register m_pendWait_3
|
|
assign m_pendWait_3$D_IN =
|
|
MUX_m_pendWait_3$write_1__SEL_1 ?
|
|
MUX_m_pendWait_3$write_1__VAL_1 :
|
|
MUX_m_pendWait_0$write_1__VAL_2 ;
|
|
assign m_pendWait_3$EN =
|
|
EN_procReq && _dfoo57 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd3 ;
|
|
|
|
// register m_perfReqQ_clearReq_rl
|
|
assign m_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_data_0
|
|
assign m_perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
m_perfReqQ_enqReq_lat_0$wget[2:0] :
|
|
m_perfReqQ_enqReq_rl[2:0] ;
|
|
assign m_perfReqQ_data_0$EN =
|
|
!m_perfReqQ_clearReq_rl &&
|
|
IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 ;
|
|
|
|
// register m_perfReqQ_deqReq_rl
|
|
assign m_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_empty
|
|
assign m_perfReqQ_empty$D_IN =
|
|
m_perfReqQ_clearReq_rl ||
|
|
(EN_perf_req ?
|
|
!m_perfReqQ_enqReq_lat_0$wget[3] :
|
|
!m_perfReqQ_enqReq_rl[3]) &&
|
|
(EN_perf_resp || m_perfReqQ_deqReq_rl || m_perfReqQ_empty) ;
|
|
assign m_perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_enqReq_rl
|
|
assign m_perfReqQ_enqReq_rl$D_IN = m_perfReqQ_enqReq_lat_2$wget ;
|
|
assign m_perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_full
|
|
assign m_perfReqQ_full$D_IN =
|
|
!m_perfReqQ_clearReq_rl &&
|
|
(IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 ||
|
|
!EN_perf_resp && !m_perfReqQ_deqReq_rl && m_perfReqQ_full) ;
|
|
assign m_perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register m_respForOtherReq
|
|
assign m_respForOtherReq$D_IN =
|
|
{ NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271__ETC___d1796,
|
|
IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1799 } ;
|
|
assign m_respForOtherReq$EN = WILL_FIRE_RL_m_doPRs ;
|
|
|
|
// register m_rqToPQ_clearReq_rl
|
|
assign m_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_rqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_data_0
|
|
assign m_rqToPQ_data_0$D_IN =
|
|
m_rqToPQ_enqReq_lat_0$whas ?
|
|
m_rqToPQ_enqReq_lat_0$wget[28:0] :
|
|
m_rqToPQ_enqReq_rl[28:0] ;
|
|
assign m_rqToPQ_data_0$EN =
|
|
m_rqToPQ_enqP == 2'd0 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_1
|
|
assign m_rqToPQ_data_1$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_1$EN =
|
|
m_rqToPQ_enqP == 2'd1 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_2
|
|
assign m_rqToPQ_data_2$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_2$EN =
|
|
m_rqToPQ_enqP == 2'd2 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_3
|
|
assign m_rqToPQ_data_3$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_3$EN =
|
|
m_rqToPQ_enqP == 2'd3 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_deqP
|
|
assign m_rqToPQ_deqP$D_IN =
|
|
m_rqToPQ_clearReq_rl ? 2'd0 : _theResult_____2__h17468 ;
|
|
assign m_rqToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_deqReq_rl
|
|
assign m_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_rqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_empty
|
|
assign m_rqToPQ_empty$D_IN =
|
|
m_rqToPQ_clearReq_rl ||
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260 ;
|
|
assign m_rqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_enqP
|
|
assign m_rqToPQ_enqP$D_IN = m_rqToPQ_clearReq_rl ? 2'd0 : v__h16896 ;
|
|
assign m_rqToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_enqReq_rl
|
|
assign m_rqToPQ_enqReq_rl$D_IN = m_rqToPQ_enqReq_lat_2$wget ;
|
|
assign m_rqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_full
|
|
assign m_rqToPQ_full$D_IN =
|
|
!m_rqToPQ_clearReq_rl &&
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255 ;
|
|
assign m_rqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_entryVec_0
|
|
assign m_tlb_m_entryVec_0$D_IN =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_10_00__ETC___d1733 } ;
|
|
assign m_tlb_m_entryVec_0$EN = MUX_m_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_1
|
|
assign m_tlb_m_entryVec_1$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_1$EN = MUX_m_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_10
|
|
assign m_tlb_m_entryVec_10$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_10$EN = MUX_m_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_11
|
|
assign m_tlb_m_entryVec_11$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_11$EN = MUX_m_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_12
|
|
assign m_tlb_m_entryVec_12$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_12$EN = MUX_m_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_13
|
|
assign m_tlb_m_entryVec_13$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_13$EN = MUX_m_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_14
|
|
assign m_tlb_m_entryVec_14$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_14$EN = MUX_m_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_15
|
|
assign m_tlb_m_entryVec_15$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_15$EN = MUX_m_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_16
|
|
assign m_tlb_m_entryVec_16$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_16$EN = MUX_m_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_17
|
|
assign m_tlb_m_entryVec_17$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_17$EN = MUX_m_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_18
|
|
assign m_tlb_m_entryVec_18$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_18$EN = MUX_m_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_19
|
|
assign m_tlb_m_entryVec_19$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_19$EN = MUX_m_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_2
|
|
assign m_tlb_m_entryVec_2$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_2$EN = MUX_m_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_20
|
|
assign m_tlb_m_entryVec_20$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_20$EN = MUX_m_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_21
|
|
assign m_tlb_m_entryVec_21$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_21$EN = MUX_m_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_22
|
|
assign m_tlb_m_entryVec_22$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_22$EN = MUX_m_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_23
|
|
assign m_tlb_m_entryVec_23$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_23$EN = MUX_m_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_24
|
|
assign m_tlb_m_entryVec_24$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_24$EN = MUX_m_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_25
|
|
assign m_tlb_m_entryVec_25$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_25$EN = MUX_m_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_26
|
|
assign m_tlb_m_entryVec_26$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_26$EN = MUX_m_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_27
|
|
assign m_tlb_m_entryVec_27$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_27$EN = MUX_m_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_28
|
|
assign m_tlb_m_entryVec_28$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_28$EN = MUX_m_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_29
|
|
assign m_tlb_m_entryVec_29$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_29$EN = MUX_m_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_3
|
|
assign m_tlb_m_entryVec_3$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_3$EN = MUX_m_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_30
|
|
assign m_tlb_m_entryVec_30$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_30$EN = MUX_m_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_31
|
|
assign m_tlb_m_entryVec_31$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_31$EN = MUX_m_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_4
|
|
assign m_tlb_m_entryVec_4$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_4$EN = MUX_m_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_5
|
|
assign m_tlb_m_entryVec_5$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_5$EN = MUX_m_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_6
|
|
assign m_tlb_m_entryVec_6$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_6$EN = MUX_m_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_7
|
|
assign m_tlb_m_entryVec_7$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_7$EN = MUX_m_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_8
|
|
assign m_tlb_m_entryVec_8$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_8$EN = MUX_m_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_9
|
|
assign m_tlb_m_entryVec_9$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_9$EN = MUX_m_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_lruBit_rl
|
|
assign m_tlb_m_lruBit_rl$D_IN = n__read__h50928 ;
|
|
assign m_tlb_m_lruBit_rl$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_randIdx
|
|
assign m_tlb_m_randIdx$D_IN = m_tlb_m_randIdx + 5'd1 ;
|
|
assign m_tlb_m_randIdx$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_updRepIdx_rl
|
|
assign m_tlb_m_updRepIdx_rl$D_IN =
|
|
{ IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27 } ;
|
|
assign m_tlb_m_updRepIdx_rl$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_validVec_0
|
|
assign m_tlb_m_validVec_0$D_IN = MUX_m_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_0$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1663 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_1
|
|
assign m_tlb_m_validVec_1$D_IN = MUX_m_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_1$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1665 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_10
|
|
assign m_tlb_m_validVec_10$D_IN = MUX_m_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_10$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1683 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_11
|
|
assign m_tlb_m_validVec_11$D_IN = MUX_m_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_11$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1685 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_12
|
|
assign m_tlb_m_validVec_12$D_IN = MUX_m_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_12$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1687 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_13
|
|
assign m_tlb_m_validVec_13$D_IN = MUX_m_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_13$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1689 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_14
|
|
assign m_tlb_m_validVec_14$D_IN = MUX_m_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_14$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1691 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_15
|
|
assign m_tlb_m_validVec_15$D_IN = MUX_m_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_15$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1693 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_16
|
|
assign m_tlb_m_validVec_16$D_IN = MUX_m_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_16$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1695 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_17
|
|
assign m_tlb_m_validVec_17$D_IN = MUX_m_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_17$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1697 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_18
|
|
assign m_tlb_m_validVec_18$D_IN = MUX_m_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_18$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1699 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_19
|
|
assign m_tlb_m_validVec_19$D_IN = MUX_m_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_19$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1701 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_2
|
|
assign m_tlb_m_validVec_2$D_IN = MUX_m_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_2$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1667 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_20
|
|
assign m_tlb_m_validVec_20$D_IN = MUX_m_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_20$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1703 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_21
|
|
assign m_tlb_m_validVec_21$D_IN = MUX_m_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_21$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1705 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_22
|
|
assign m_tlb_m_validVec_22$D_IN = MUX_m_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_22$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1707 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_23
|
|
assign m_tlb_m_validVec_23$D_IN = MUX_m_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_23$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1709 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_24
|
|
assign m_tlb_m_validVec_24$D_IN = MUX_m_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_24$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1711 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_25
|
|
assign m_tlb_m_validVec_25$D_IN = MUX_m_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_25$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1713 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_26
|
|
assign m_tlb_m_validVec_26$D_IN = MUX_m_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_26$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1715 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_27
|
|
assign m_tlb_m_validVec_27$D_IN = MUX_m_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_27$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1717 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_28
|
|
assign m_tlb_m_validVec_28$D_IN = MUX_m_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_28$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1719 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_29
|
|
assign m_tlb_m_validVec_29$D_IN = MUX_m_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_29$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1721 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_3
|
|
assign m_tlb_m_validVec_3$D_IN = MUX_m_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_3$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1669 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_30
|
|
assign m_tlb_m_validVec_30$D_IN = MUX_m_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_30$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1723 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_31
|
|
assign m_tlb_m_validVec_31$D_IN = MUX_m_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_31$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1725 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_4
|
|
assign m_tlb_m_validVec_4$D_IN = MUX_m_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_4$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1671 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_5
|
|
assign m_tlb_m_validVec_5$D_IN = MUX_m_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_5$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1673 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_6
|
|
assign m_tlb_m_validVec_6$D_IN = MUX_m_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_6$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1675 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_7
|
|
assign m_tlb_m_validVec_7$D_IN = MUX_m_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_7$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1677 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_8
|
|
assign m_tlb_m_validVec_8$D_IN = MUX_m_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_8$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1679 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_9
|
|
assign m_tlb_m_validVec_9$D_IN = MUX_m_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_9$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1681 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_vm_info
|
|
assign m_vm_info$D_IN = updateVMInfo_vm ;
|
|
assign m_vm_info$EN = EN_updateVMInfo ;
|
|
|
|
// register m_waitFlushP
|
|
assign m_waitFlushP$D_IN = !MUX_m_waitFlushP$write_1__SEL_1 ;
|
|
assign m_waitFlushP$EN =
|
|
WILL_FIRE_RL_m_doFinishFlush || EN_flush ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// remaining internal signals
|
|
assign DONTCARE_CONCAT_1_CONCAT_IF_SEL_ARR_m_pendInst_ETC___d1766 =
|
|
{ 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd1,
|
|
CASE_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_8_ETC__q35 } ;
|
|
assign DONTCARE_CONCAT_1_CONCAT_IF_procReq_req_BITS_4_ETC___d2716 =
|
|
{ 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd1,
|
|
CASE_procReq_req_BITS_490_TO_488_1_15_3_15_4_1_ETC__q36 } ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2647 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_ETC___d2644 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_ETC___d2644 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2655 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_ETC___d2652 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_ETC___d2652 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2697 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT__ETC___d2694 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT__ETC___d2694 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2704 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT__ETC___d2701 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT__ETC___d2701 ;
|
|
assign IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_ETC___d2644 =
|
|
(level__h85474 == 2'd0 ||
|
|
((level__h85474 == 2'd1) ?
|
|
ppn__h90430[8:0] == 9'd0 :
|
|
level__h85474 == 2'd2 && ppn__h90430[17:0] == 18'd0)) &&
|
|
(!SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 ||
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487) ;
|
|
assign IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_ETC___d2652 =
|
|
(level__h85474 == 2'd0 ||
|
|
((level__h85474 == 2'd1) ?
|
|
ppn__h90430[8:0] == 9'd0 :
|
|
level__h85474 == 2'd2 && ppn__h90430[17:0] == 18'd0)) &&
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 =
|
|
_theResult_____2__h13508 == v__h13028 ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167 =
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 &&
|
|
(IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ||
|
|
!EN_procReq && !m_freeQ_deqReq_rl && m_freeQ_full) ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172 =
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 &&
|
|
(m_freeQ_enqReq_lat_0$whas ?
|
|
!m_freeQ_enqReq_lat_0$wget[2] :
|
|
!m_freeQ_enqReq_rl[2]) &&
|
|
(IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 ||
|
|
m_freeQ_empty) ;
|
|
assign IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 =
|
|
_theResult_____2__h22136 == v__h21066 ;
|
|
assign IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366 =
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 &&
|
|
(IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ||
|
|
!m_ldTransRsFromPQ_deqReq_lat_0$whas &&
|
|
!m_ldTransRsFromPQ_deqReq_rl &&
|
|
m_ldTransRsFromPQ_full) ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 =
|
|
_theResult_____2__h17468 == v__h16896 ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255 =
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 &&
|
|
(IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ||
|
|
!EN_toParent_rqToP_deq && !m_rqToPQ_deqReq_rl &&
|
|
m_rqToPQ_full) ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260 =
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 &&
|
|
(m_rqToPQ_enqReq_lat_0$whas ?
|
|
!m_rqToPQ_enqReq_lat_0$wget[29] :
|
|
!m_rqToPQ_enqReq_rl[29]) &&
|
|
(IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 ||
|
|
m_rqToPQ_empty) ;
|
|
assign IF_NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_ETC___d1613 =
|
|
(SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd4) ?
|
|
NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BI_ETC___d1605 :
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_18_m_ETC___d680 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_65_m_ETC___d668 &&
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1611 ;
|
|
assign IF_NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_ETC___d690 =
|
|
(SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd4) ?
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d678 :
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_18_m_ETC___d680 ||
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_65_m_ETC___d668 ||
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d688 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1829 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) ?
|
|
m_pendValid_1_rl && m_pendWait_1[3:2] == 2'd0 &&
|
|
m_pendPoisoned_1 :
|
|
m_pendValid_0_rl ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1830 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1818 ?
|
|
m_pendValid_2_rl && m_pendWait_2[3:2] == 2'd0 &&
|
|
m_pendPoisoned_2 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1829 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1831 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1822 ?
|
|
m_pendValid_3_rl && m_pendWait_3[3:2] == 2'd0 &&
|
|
m_pendPoisoned_3 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1830 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3238 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) ?
|
|
m_pendValid_1_rl && m_pendWait_1[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_1 :
|
|
m_pendValid_0_rl ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3239 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2788 ?
|
|
m_pendValid_2_rl && m_pendWait_2[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_2 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3238 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3240 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2790 ?
|
|
m_pendValid_3_rl && m_pendWait_3[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_3 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3239 ;
|
|
assign IF_NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_2_ETC___d2747 =
|
|
((m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2721) &&
|
|
(m_pendWait_1[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2724)) ?
|
|
2'd2 :
|
|
((m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2721) ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2216 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1877 ?
|
|
m_tlb_m_validVec_1 &&
|
|
IF_m_tlb_m_entryVec_1_23_BITS_1_TO_0_27_EQ_0_8_ETC___d1884 :
|
|
m_tlb_m_validVec_0 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2217 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1877 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_23_BITS_1_TO_0_27_EQ_0_8_ETC___d1884)) ?
|
|
m_tlb_m_validVec_2 &&
|
|
IF_m_tlb_m_entryVec_2_39_BITS_1_TO_0_43_EQ_0_8_ETC___d1894 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2216 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2218 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1897 ?
|
|
m_tlb_m_validVec_3 &&
|
|
IF_m_tlb_m_entryVec_3_55_BITS_1_TO_0_59_EQ_0_8_ETC___d1904 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2217 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2219 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1897 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_55_BITS_1_TO_0_59_EQ_0_8_ETC___d1904)) ?
|
|
m_tlb_m_validVec_4 &&
|
|
IF_m_tlb_m_entryVec_4_71_BITS_1_TO_0_75_EQ_0_9_ETC___d1914 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2218 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2220 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1917 ?
|
|
m_tlb_m_validVec_5 &&
|
|
IF_m_tlb_m_entryVec_5_87_BITS_1_TO_0_91_EQ_0_9_ETC___d1924 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2219 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2221 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1917 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_87_BITS_1_TO_0_91_EQ_0_9_ETC___d1924)) ?
|
|
m_tlb_m_validVec_6 &&
|
|
IF_m_tlb_m_entryVec_6_03_BITS_1_TO_0_07_EQ_0_9_ETC___d1934 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2220 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2222 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1937 ?
|
|
m_tlb_m_validVec_7 &&
|
|
IF_m_tlb_m_entryVec_7_19_BITS_1_TO_0_23_EQ_0_9_ETC___d1944 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2221 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2223 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1937 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_19_BITS_1_TO_0_23_EQ_0_9_ETC___d1944)) ?
|
|
m_tlb_m_validVec_8 &&
|
|
IF_m_tlb_m_entryVec_8_35_BITS_1_TO_0_39_EQ_0_9_ETC___d1954 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2222 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2224 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1957 ?
|
|
m_tlb_m_validVec_9 &&
|
|
IF_m_tlb_m_entryVec_9_51_BITS_1_TO_0_55_EQ_0_9_ETC___d1964 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2223 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2225 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1957 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_51_BITS_1_TO_0_55_EQ_0_9_ETC___d1964)) ?
|
|
m_tlb_m_validVec_10 &&
|
|
IF_m_tlb_m_entryVec_10_67_BITS_1_TO_0_71_EQ_0__ETC___d1974 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2224 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2226 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1977 ?
|
|
m_tlb_m_validVec_11 &&
|
|
IF_m_tlb_m_entryVec_11_83_BITS_1_TO_0_87_EQ_0__ETC___d1984 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2225 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2227 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1977 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_83_BITS_1_TO_0_87_EQ_0__ETC___d1984)) ?
|
|
m_tlb_m_validVec_12 &&
|
|
IF_m_tlb_m_entryVec_12_99_BITS_1_TO_0_03_EQ_0__ETC___d1994 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2226 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2228 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1997 ?
|
|
m_tlb_m_validVec_13 &&
|
|
IF_m_tlb_m_entryVec_13_15_BITS_1_TO_0_19_EQ_0__ETC___d2004 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2227 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2229 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1997 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_15_BITS_1_TO_0_19_EQ_0__ETC___d2004)) ?
|
|
m_tlb_m_validVec_14 &&
|
|
IF_m_tlb_m_entryVec_14_31_BITS_1_TO_0_35_EQ_0__ETC___d2014 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2228 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2230 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2017 ?
|
|
m_tlb_m_validVec_15 &&
|
|
IF_m_tlb_m_entryVec_15_47_BITS_1_TO_0_51_EQ_0__ETC___d2024 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2229 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2231 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2017 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_47_BITS_1_TO_0_51_EQ_0__ETC___d2024)) ?
|
|
m_tlb_m_validVec_16 &&
|
|
IF_m_tlb_m_entryVec_16_63_BITS_1_TO_0_67_EQ_0__ETC___d2034 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2230 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2232 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2037 ?
|
|
m_tlb_m_validVec_17 &&
|
|
IF_m_tlb_m_entryVec_17_79_BITS_1_TO_0_83_EQ_0__ETC___d2044 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2231 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2233 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2037 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_79_BITS_1_TO_0_83_EQ_0__ETC___d2044)) ?
|
|
m_tlb_m_validVec_18 &&
|
|
IF_m_tlb_m_entryVec_18_95_BITS_1_TO_0_99_EQ_0__ETC___d2054 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2232 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2234 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2057 ?
|
|
m_tlb_m_validVec_19 &&
|
|
IF_m_tlb_m_entryVec_19_011_BITS_1_TO_0_015_EQ__ETC___d2064 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2233 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2235 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2057 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_011_BITS_1_TO_0_015_EQ__ETC___d2064)) ?
|
|
m_tlb_m_validVec_20 &&
|
|
IF_m_tlb_m_entryVec_20_027_BITS_1_TO_0_031_EQ__ETC___d2074 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2234 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2236 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2077 ?
|
|
m_tlb_m_validVec_21 &&
|
|
IF_m_tlb_m_entryVec_21_043_BITS_1_TO_0_047_EQ__ETC___d2084 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2235 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2237 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2077 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_043_BITS_1_TO_0_047_EQ__ETC___d2084)) ?
|
|
m_tlb_m_validVec_22 &&
|
|
IF_m_tlb_m_entryVec_22_059_BITS_1_TO_0_063_EQ__ETC___d2094 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2236 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2238 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2097 ?
|
|
m_tlb_m_validVec_23 &&
|
|
IF_m_tlb_m_entryVec_23_075_BITS_1_TO_0_079_EQ__ETC___d2104 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2237 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2239 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2097 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_075_BITS_1_TO_0_079_EQ__ETC___d2104)) ?
|
|
m_tlb_m_validVec_24 &&
|
|
IF_m_tlb_m_entryVec_24_091_BITS_1_TO_0_095_EQ__ETC___d2114 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2238 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2240 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2117 ?
|
|
m_tlb_m_validVec_25 &&
|
|
IF_m_tlb_m_entryVec_25_107_BITS_1_TO_0_111_EQ__ETC___d2124 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2239 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2241 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2117 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_107_BITS_1_TO_0_111_EQ__ETC___d2124)) ?
|
|
m_tlb_m_validVec_26 &&
|
|
IF_m_tlb_m_entryVec_26_123_BITS_1_TO_0_127_EQ__ETC___d2134 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2240 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2242 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2137 ?
|
|
m_tlb_m_validVec_27 &&
|
|
IF_m_tlb_m_entryVec_27_139_BITS_1_TO_0_143_EQ__ETC___d2144 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2241 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2243 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2137 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_139_BITS_1_TO_0_143_EQ__ETC___d2144)) ?
|
|
m_tlb_m_validVec_28 &&
|
|
IF_m_tlb_m_entryVec_28_155_BITS_1_TO_0_159_EQ__ETC___d2154 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2242 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2244 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2157 ?
|
|
m_tlb_m_validVec_29 &&
|
|
IF_m_tlb_m_entryVec_29_171_BITS_1_TO_0_175_EQ__ETC___d2164 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2243 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2245 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2157 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_171_BITS_1_TO_0_175_EQ__ETC___d2164)) ?
|
|
m_tlb_m_validVec_30 &&
|
|
IF_m_tlb_m_entryVec_30_187_BITS_1_TO_0_191_EQ__ETC___d2174 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2244 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2177 ?
|
|
m_tlb_m_validVec_31 &&
|
|
IF_m_tlb_m_entryVec_31_616_BITS_1_TO_0_620_EQ__ETC___d2184 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2245 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2322 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1877 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_23_BITS_1_TO_0_27_EQ_0_8_ETC___d1884)) ?
|
|
5'd2 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1877 ?
|
|
5'd1 :
|
|
5'd0) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2324 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1897 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_55_BITS_1_TO_0_59_EQ_0_8_ETC___d1904)) ?
|
|
5'd4 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1897 ?
|
|
5'd3 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2322) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2326 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1917 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_87_BITS_1_TO_0_91_EQ_0_9_ETC___d1924)) ?
|
|
5'd6 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1917 ?
|
|
5'd5 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2324) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2328 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1937 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_19_BITS_1_TO_0_23_EQ_0_9_ETC___d1944)) ?
|
|
5'd8 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1937 ?
|
|
5'd7 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2326) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2330 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1957 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_51_BITS_1_TO_0_55_EQ_0_9_ETC___d1964)) ?
|
|
5'd10 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1957 ?
|
|
5'd9 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2328) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2332 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1977 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_83_BITS_1_TO_0_87_EQ_0__ETC___d1984)) ?
|
|
5'd12 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1977 ?
|
|
5'd11 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2330) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2334 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1997 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_15_BITS_1_TO_0_19_EQ_0__ETC___d2004)) ?
|
|
5'd14 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1997 ?
|
|
5'd13 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2332) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2336 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2017 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_47_BITS_1_TO_0_51_EQ_0__ETC___d2024)) ?
|
|
5'd16 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2017 ?
|
|
5'd15 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2334) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2338 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2037 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_79_BITS_1_TO_0_83_EQ_0__ETC___d2044)) ?
|
|
5'd18 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2037 ?
|
|
5'd17 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2336) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2340 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2057 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_011_BITS_1_TO_0_015_EQ__ETC___d2064)) ?
|
|
5'd20 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2057 ?
|
|
5'd19 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2338) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2342 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2077 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_043_BITS_1_TO_0_047_EQ__ETC___d2084)) ?
|
|
5'd22 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2077 ?
|
|
5'd21 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2340) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2344 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2097 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_075_BITS_1_TO_0_079_EQ__ETC___d2104)) ?
|
|
5'd24 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2097 ?
|
|
5'd23 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2342) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2346 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2117 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_107_BITS_1_TO_0_111_EQ__ETC___d2124)) ?
|
|
5'd26 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2117 ?
|
|
5'd25 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2344) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2348 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2137 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_139_BITS_1_TO_0_143_EQ__ETC___d2144)) ?
|
|
5'd28 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2137 ?
|
|
5'd27 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2346) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2350 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2157 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_171_BITS_1_TO_0_175_EQ__ETC___d2164)) ?
|
|
5'd30 :
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2157 ?
|
|
5'd29 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2348) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_ldTra_ETC___d1264 =
|
|
((!m_tlb_m_validVec_0 || !m_ldTransRsFromPQ_empty) &&
|
|
(!m_tlb_m_validVec_0 ||
|
|
NOT_m_tlb_m_entryVec_0_98_BITS_79_TO_53_99_EQ__ETC___d717)) ?
|
|
(!m_tlb_m_validVec_1 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_1_20_21_OR_NOT_m_tlb_m_ETC___d1262 :
|
|
!m_tlb_m_validVec_0 || !m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1663 =
|
|
v__h45375 == 5'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1665 =
|
|
v__h45375 == 5'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1667 =
|
|
v__h45375 == 5'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1669 =
|
|
v__h45375 == 5'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1671 =
|
|
v__h45375 == 5'd4 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1673 =
|
|
v__h45375 == 5'd5 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1675 =
|
|
v__h45375 == 5'd6 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1677 =
|
|
v__h45375 == 5'd7 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1679 =
|
|
v__h45375 == 5'd8 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1681 =
|
|
v__h45375 == 5'd9 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1683 =
|
|
v__h45375 == 5'd10 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1685 =
|
|
v__h45375 == 5'd11 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1687 =
|
|
v__h45375 == 5'd12 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1689 =
|
|
v__h45375 == 5'd13 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1691 =
|
|
v__h45375 == 5'd14 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1693 =
|
|
v__h45375 == 5'd15 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1695 =
|
|
v__h45375 == 5'd16 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1697 =
|
|
v__h45375 == 5'd17 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1699 =
|
|
v__h45375 == 5'd18 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1701 =
|
|
v__h45375 == 5'd19 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1703 =
|
|
v__h45375 == 5'd20 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1705 =
|
|
v__h45375 == 5'd21 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1707 =
|
|
v__h45375 == 5'd22 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1709 =
|
|
v__h45375 == 5'd23 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1711 =
|
|
v__h45375 == 5'd24 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1713 =
|
|
v__h45375 == 5'd25 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1715 =
|
|
v__h45375 == 5'd26 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1717 =
|
|
v__h45375 == 5'd27 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1719 =
|
|
v__h45375 == 5'd28 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1721 =
|
|
v__h45375 == 5'd29 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1723 =
|
|
v__h45375 == 5'd30 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_ETC___d1725 =
|
|
v__h45375 == 5'd31 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 ;
|
|
assign IF_NOT_m_tlb_m_validVec_10_64_65_OR_NOT_m_tlb__ETC___d1244 =
|
|
(!m_tlb_m_validVec_10 ||
|
|
NOT_m_tlb_m_entryVec_10_67_BITS_79_TO_53_68_EQ_ETC___d878) ?
|
|
(!m_tlb_m_validVec_11 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_11_80_81_OR_NOT_m_tlb__ETC___d1242 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_11_80_81_OR_NOT_m_tlb__ETC___d1242 =
|
|
(!m_tlb_m_validVec_11 ||
|
|
NOT_m_tlb_m_entryVec_11_83_BITS_79_TO_53_84_EQ_ETC___d894) ?
|
|
(!m_tlb_m_validVec_12 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_12_96_97_OR_NOT_m_tlb__ETC___d1240 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_12_96_97_OR_NOT_m_tlb__ETC___d1240 =
|
|
(!m_tlb_m_validVec_12 ||
|
|
NOT_m_tlb_m_entryVec_12_99_BITS_79_TO_53_00_EQ_ETC___d910) ?
|
|
(!m_tlb_m_validVec_13 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_13_12_13_OR_NOT_m_tlb__ETC___d1238 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_13_12_13_OR_NOT_m_tlb__ETC___d1238 =
|
|
(!m_tlb_m_validVec_13 ||
|
|
NOT_m_tlb_m_entryVec_13_15_BITS_79_TO_53_16_EQ_ETC___d926) ?
|
|
(!m_tlb_m_validVec_14 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_14_28_29_OR_NOT_m_tlb__ETC___d1236 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_14_28_29_OR_NOT_m_tlb__ETC___d1236 =
|
|
(!m_tlb_m_validVec_14 ||
|
|
NOT_m_tlb_m_entryVec_14_31_BITS_79_TO_53_32_EQ_ETC___d942) ?
|
|
(!m_tlb_m_validVec_15 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_15_44_45_OR_NOT_m_tlb__ETC___d1234 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_15_44_45_OR_NOT_m_tlb__ETC___d1234 =
|
|
(!m_tlb_m_validVec_15 ||
|
|
NOT_m_tlb_m_entryVec_15_47_BITS_79_TO_53_48_EQ_ETC___d958) ?
|
|
(!m_tlb_m_validVec_16 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_16_60_61_OR_NOT_m_tlb__ETC___d1232 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_16_60_61_OR_NOT_m_tlb__ETC___d1232 =
|
|
(!m_tlb_m_validVec_16 ||
|
|
NOT_m_tlb_m_entryVec_16_63_BITS_79_TO_53_64_EQ_ETC___d974) ?
|
|
(!m_tlb_m_validVec_17 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_17_76_77_OR_NOT_m_tlb__ETC___d1230 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_17_76_77_OR_NOT_m_tlb__ETC___d1230 =
|
|
(!m_tlb_m_validVec_17 ||
|
|
NOT_m_tlb_m_entryVec_17_79_BITS_79_TO_53_80_EQ_ETC___d990) ?
|
|
(!m_tlb_m_validVec_18 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_18_92_93_OR_NOT_m_tlb__ETC___d1228 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_18_92_93_OR_NOT_m_tlb__ETC___d1228 =
|
|
(!m_tlb_m_validVec_18 ||
|
|
NOT_m_tlb_m_entryVec_18_95_BITS_79_TO_53_96_EQ_ETC___d1006) ?
|
|
(!m_tlb_m_validVec_19 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_19_008_009_OR_NOT_m_tl_ETC___d1226 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_19_008_009_OR_NOT_m_tl_ETC___d1226 =
|
|
(!m_tlb_m_validVec_19 ||
|
|
NOT_m_tlb_m_entryVec_19_011_BITS_79_TO_53_012__ETC___d1022) ?
|
|
(!m_tlb_m_validVec_20 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_20_024_025_OR_NOT_m_tl_ETC___d1224 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_1_20_21_OR_NOT_m_tlb_m_ETC___d1262 =
|
|
(!m_tlb_m_validVec_1 ||
|
|
NOT_m_tlb_m_entryVec_1_23_BITS_79_TO_53_24_EQ__ETC___d734) ?
|
|
(!m_tlb_m_validVec_2 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_2_36_37_OR_NOT_m_tlb_m_ETC___d1260 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_20_024_025_OR_NOT_m_tl_ETC___d1224 =
|
|
(!m_tlb_m_validVec_20 ||
|
|
NOT_m_tlb_m_entryVec_20_027_BITS_79_TO_53_028__ETC___d1038) ?
|
|
(!m_tlb_m_validVec_21 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_21_040_041_OR_NOT_m_tl_ETC___d1222 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_21_040_041_OR_NOT_m_tl_ETC___d1222 =
|
|
(!m_tlb_m_validVec_21 ||
|
|
NOT_m_tlb_m_entryVec_21_043_BITS_79_TO_53_044__ETC___d1054) ?
|
|
(!m_tlb_m_validVec_22 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_22_056_057_OR_NOT_m_tl_ETC___d1220 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_22_056_057_OR_NOT_m_tl_ETC___d1220 =
|
|
(!m_tlb_m_validVec_22 ||
|
|
NOT_m_tlb_m_entryVec_22_059_BITS_79_TO_53_060__ETC___d1070) ?
|
|
(!m_tlb_m_validVec_23 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_23_072_073_OR_NOT_m_tl_ETC___d1218 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_23_072_073_OR_NOT_m_tl_ETC___d1218 =
|
|
(!m_tlb_m_validVec_23 ||
|
|
NOT_m_tlb_m_entryVec_23_075_BITS_79_TO_53_076__ETC___d1086) ?
|
|
(!m_tlb_m_validVec_24 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_24_088_089_OR_NOT_m_tl_ETC___d1216 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_24_088_089_OR_NOT_m_tl_ETC___d1216 =
|
|
(!m_tlb_m_validVec_24 ||
|
|
NOT_m_tlb_m_entryVec_24_091_BITS_79_TO_53_092__ETC___d1102) ?
|
|
(!m_tlb_m_validVec_25 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_25_104_105_OR_NOT_m_tl_ETC___d1214 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_25_104_105_OR_NOT_m_tl_ETC___d1214 =
|
|
(!m_tlb_m_validVec_25 ||
|
|
NOT_m_tlb_m_entryVec_25_107_BITS_79_TO_53_108__ETC___d1118) ?
|
|
(!m_tlb_m_validVec_26 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_26_120_121_OR_NOT_m_tl_ETC___d1212 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_26_120_121_OR_NOT_m_tl_ETC___d1212 =
|
|
(!m_tlb_m_validVec_26 ||
|
|
NOT_m_tlb_m_entryVec_26_123_BITS_79_TO_53_124__ETC___d1134) ?
|
|
(!m_tlb_m_validVec_27 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_27_136_137_OR_NOT_m_tl_ETC___d1210 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_27_136_137_OR_NOT_m_tl_ETC___d1210 =
|
|
(!m_tlb_m_validVec_27 ||
|
|
NOT_m_tlb_m_entryVec_27_139_BITS_79_TO_53_140__ETC___d1150) ?
|
|
(!m_tlb_m_validVec_28 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_28_152_153_OR_NOT_m_tl_ETC___d1208 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_28_152_153_OR_NOT_m_tl_ETC___d1208 =
|
|
(!m_tlb_m_validVec_28 ||
|
|
NOT_m_tlb_m_entryVec_28_155_BITS_79_TO_53_156__ETC___d1166) ?
|
|
(!m_tlb_m_validVec_29 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_29_168_169_OR_NOT_m_tl_ETC___d1206 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_29_168_169_OR_NOT_m_tl_ETC___d1206 =
|
|
(!m_tlb_m_validVec_29 ||
|
|
NOT_m_tlb_m_entryVec_29_171_BITS_79_TO_53_172__ETC___d1182) ?
|
|
(!m_tlb_m_validVec_30 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_30_184_185_OR_NOT_m_tl_ETC___d1204 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_2_36_37_OR_NOT_m_tlb_m_ETC___d1260 =
|
|
(!m_tlb_m_validVec_2 ||
|
|
NOT_m_tlb_m_entryVec_2_39_BITS_79_TO_53_40_EQ__ETC___d750) ?
|
|
(!m_tlb_m_validVec_3 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_3_52_53_OR_NOT_m_tlb_m_ETC___d1258 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_30_184_185_OR_NOT_m_tl_ETC___d1204 =
|
|
(!m_tlb_m_validVec_30 ||
|
|
NOT_m_tlb_m_entryVec_30_187_BITS_79_TO_53_188__ETC___d1198) ?
|
|
!m_tlb_m_validVec_31 || !m_ldTransRsFromPQ_empty :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_3_52_53_OR_NOT_m_tlb_m_ETC___d1258 =
|
|
(!m_tlb_m_validVec_3 ||
|
|
NOT_m_tlb_m_entryVec_3_55_BITS_79_TO_53_56_EQ__ETC___d766) ?
|
|
(!m_tlb_m_validVec_4 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_4_68_69_OR_NOT_m_tlb_m_ETC___d1256 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_4_68_69_OR_NOT_m_tlb_m_ETC___d1256 =
|
|
(!m_tlb_m_validVec_4 ||
|
|
NOT_m_tlb_m_entryVec_4_71_BITS_79_TO_53_72_EQ__ETC___d782) ?
|
|
(!m_tlb_m_validVec_5 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_5_84_85_OR_NOT_m_tlb_m_ETC___d1254 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_5_84_85_OR_NOT_m_tlb_m_ETC___d1254 =
|
|
(!m_tlb_m_validVec_5 ||
|
|
NOT_m_tlb_m_entryVec_5_87_BITS_79_TO_53_88_EQ__ETC___d798) ?
|
|
(!m_tlb_m_validVec_6 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_6_00_01_OR_NOT_m_tlb_m_ETC___d1252 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_6_00_01_OR_NOT_m_tlb_m_ETC___d1252 =
|
|
(!m_tlb_m_validVec_6 ||
|
|
NOT_m_tlb_m_entryVec_6_03_BITS_79_TO_53_04_EQ__ETC___d814) ?
|
|
(!m_tlb_m_validVec_7 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_7_16_17_OR_NOT_m_tlb_m_ETC___d1250 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_7_16_17_OR_NOT_m_tlb_m_ETC___d1250 =
|
|
(!m_tlb_m_validVec_7 ||
|
|
NOT_m_tlb_m_entryVec_7_19_BITS_79_TO_53_20_EQ__ETC___d830) ?
|
|
(!m_tlb_m_validVec_8 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_8_32_33_OR_NOT_m_tlb_m_ETC___d1248 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_8_32_33_OR_NOT_m_tlb_m_ETC___d1248 =
|
|
(!m_tlb_m_validVec_8 ||
|
|
NOT_m_tlb_m_entryVec_8_35_BITS_79_TO_53_36_EQ__ETC___d846) ?
|
|
(!m_tlb_m_validVec_9 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_9_48_49_OR_NOT_m_tlb_m_ETC___d1246 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_9_48_49_OR_NOT_m_tlb_m_ETC___d1246 =
|
|
(!m_tlb_m_validVec_9 ||
|
|
NOT_m_tlb_m_entryVec_9_51_BITS_79_TO_53_52_EQ__ETC___d862) ?
|
|
(!m_tlb_m_validVec_10 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_10_64_65_OR_NOT_m_tlb__ETC___d1244 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_procReq_req_BITS_490_TO_488_247_EQ_1_24_ETC___d2657 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4) ?
|
|
NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_42_ETC___d2648 :
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 &&
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 &&
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2655 ;
|
|
assign IF_NOT_procReq_req_BITS_490_TO_488_247_EQ_1_24_ETC___d2706 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4) ?
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2698 :
|
|
!SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 ||
|
|
!SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 ||
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2704 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1604 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_34_m_ETC___d637 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d1600 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d1600 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1611 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_34_m_ETC___d637 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d1608 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d1608 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d677 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_34_m_ETC___d637 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d673 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d673 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d688 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_34_m_ETC___d637 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d685 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d685 ;
|
|
assign IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 =
|
|
EN_procReq || m_freeQ_deqReq_rl ;
|
|
assign IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 =
|
|
m_freeQ_enqReq_lat_0$whas ?
|
|
m_freeQ_enqReq_lat_0$wget[2] :
|
|
m_freeQ_enqReq_rl[2] ;
|
|
assign IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 =
|
|
m_ldTransRsFromPQ_deqReq_lat_0$whas ||
|
|
m_ldTransRsFromPQ_deqReq_rl ;
|
|
assign IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[83] :
|
|
m_ldTransRsFromPQ_enqReq_rl[83] ;
|
|
assign IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
!m_ldTransRsFromPQ_enqReq_lat_0$wget[83] :
|
|
!m_ldTransRsFromPQ_enqReq_rl[83] ;
|
|
assign IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1320 =
|
|
(m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1288 &&
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1297) ?
|
|
m_pendWait_2[3:2] == 2'd0 || m_pendWait_2[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty :
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
NOT_m_ldTransRsFromPQ_empty_68_96_AND_NOT_m_pe_ETC___d1318 ;
|
|
assign IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1337 =
|
|
(m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1288 &&
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1323) ?
|
|
m_pendWait_3[3:2] == 2'd0 || m_pendWait_3[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty :
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
NOT_m_ldTransRsFromPQ_empty_68_96_AND_NOT_m_pe_ETC___d1318 ;
|
|
assign IF_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_O_ETC___d1799 =
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1323 ?
|
|
2'd3 :
|
|
(m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1297 ?
|
|
2'd2 :
|
|
((m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_pendWait_0_269_BITS_1_TO_0_289_EQ_SEL_ARR_m__ETC___d1290 ||
|
|
idx__h37917 == 2'd0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 =
|
|
EN_perf_req ?
|
|
m_perfReqQ_enqReq_lat_0$wget[3] :
|
|
m_perfReqQ_enqReq_rl[3] ;
|
|
assign IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1738 =
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1615 ;
|
|
assign IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1758 =
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1615 ;
|
|
assign IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1759 =
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1615 ;
|
|
assign IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1761 =
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1615 ;
|
|
assign IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 =
|
|
EN_toParent_rqToP_deq || m_rqToPQ_deqReq_rl ;
|
|
assign IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 =
|
|
m_rqToPQ_enqReq_lat_0$whas ?
|
|
m_rqToPQ_enqReq_lat_0$wget[29] :
|
|
m_rqToPQ_enqReq_rl[29] ;
|
|
assign IF_m_tlb_m_entryVec_10_67_BITS_1_TO_0_71_EQ_0__ETC___d1974 =
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 ==
|
|
m_tlb_m_entryVec_10[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_11_83_BITS_1_TO_0_87_EQ_0__ETC___d1984 =
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 ==
|
|
m_tlb_m_entryVec_11[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_12_99_BITS_1_TO_0_03_EQ_0__ETC___d1994 =
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 ==
|
|
m_tlb_m_entryVec_12[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_13_15_BITS_1_TO_0_19_EQ_0__ETC___d2004 =
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 ==
|
|
m_tlb_m_entryVec_13[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_14_31_BITS_1_TO_0_35_EQ_0__ETC___d2014 =
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 ==
|
|
m_tlb_m_entryVec_14[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_15_47_BITS_1_TO_0_51_EQ_0__ETC___d2024 =
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 ==
|
|
m_tlb_m_entryVec_15[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_16_63_BITS_1_TO_0_67_EQ_0__ETC___d2034 =
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 ==
|
|
m_tlb_m_entryVec_16[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_17_79_BITS_1_TO_0_83_EQ_0__ETC___d2044 =
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 ==
|
|
m_tlb_m_entryVec_17[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_18_95_BITS_1_TO_0_99_EQ_0__ETC___d2054 =
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 ==
|
|
m_tlb_m_entryVec_18[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_19_011_BITS_1_TO_0_015_EQ__ETC___d2064 =
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 ==
|
|
m_tlb_m_entryVec_19[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_1_23_BITS_1_TO_0_27_EQ_0_8_ETC___d1884 =
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 ==
|
|
m_tlb_m_entryVec_1[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_20_027_BITS_1_TO_0_031_EQ__ETC___d2074 =
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 ==
|
|
m_tlb_m_entryVec_20[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_21_043_BITS_1_TO_0_047_EQ__ETC___d2084 =
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 ==
|
|
m_tlb_m_entryVec_21[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_22_059_BITS_1_TO_0_063_EQ__ETC___d2094 =
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 ==
|
|
m_tlb_m_entryVec_22[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_23_075_BITS_1_TO_0_079_EQ__ETC___d2104 =
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 ==
|
|
m_tlb_m_entryVec_23[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_24_091_BITS_1_TO_0_095_EQ__ETC___d2114 =
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 ==
|
|
m_tlb_m_entryVec_24[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_25_107_BITS_1_TO_0_111_EQ__ETC___d2124 =
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 ==
|
|
m_tlb_m_entryVec_25[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_26_123_BITS_1_TO_0_127_EQ__ETC___d2134 =
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 ==
|
|
m_tlb_m_entryVec_26[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_27_139_BITS_1_TO_0_143_EQ__ETC___d2144 =
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 ==
|
|
m_tlb_m_entryVec_27[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_28_155_BITS_1_TO_0_159_EQ__ETC___d2154 =
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 ==
|
|
m_tlb_m_entryVec_28[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_29_171_BITS_1_TO_0_175_EQ__ETC___d2164 =
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 ==
|
|
m_tlb_m_entryVec_29[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_2_39_BITS_1_TO_0_43_EQ_0_8_ETC___d1894 =
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q3 ==
|
|
m_tlb_m_entryVec_2[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_30_187_BITS_1_TO_0_191_EQ__ETC___d2174 =
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 ==
|
|
m_tlb_m_entryVec_30[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_31_616_BITS_1_TO_0_620_EQ__ETC___d2184 =
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 ==
|
|
m_tlb_m_entryVec_31[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_3_55_BITS_1_TO_0_59_EQ_0_8_ETC___d1904 =
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 ==
|
|
m_tlb_m_entryVec_3[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_4_71_BITS_1_TO_0_75_EQ_0_9_ETC___d1914 =
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 ==
|
|
m_tlb_m_entryVec_4[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_5_87_BITS_1_TO_0_91_EQ_0_9_ETC___d1924 =
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 ==
|
|
m_tlb_m_entryVec_5[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_6_03_BITS_1_TO_0_07_EQ_0_9_ETC___d1934 =
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 ==
|
|
m_tlb_m_entryVec_6[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_7_19_BITS_1_TO_0_23_EQ_0_9_ETC___d1944 =
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 ==
|
|
m_tlb_m_entryVec_7[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_8_35_BITS_1_TO_0_39_EQ_0_9_ETC___d1954 =
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 ==
|
|
m_tlb_m_entryVec_8[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_9_51_BITS_1_TO_0_55_EQ_0_9_ETC___d1964 =
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 ==
|
|
m_tlb_m_entryVec_9[79:53] ;
|
|
assign IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17 =
|
|
m_tlb_m_updRepIdx_lat_1$whas ?
|
|
m_tlb_m_updRepIdx_lat_1$wget[5] :
|
|
(m_tlb_m_updRepIdx_lat_0$whas ?
|
|
m_tlb_m_updRepIdx_lat_0$wget[5] :
|
|
m_tlb_m_updRepIdx_rl[5]) ;
|
|
assign IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27 =
|
|
m_tlb_m_updRepIdx_lat_1$whas ?
|
|
m_tlb_m_updRepIdx_lat_1$wget[4:0] :
|
|
(m_tlb_m_updRepIdx_lat_0$whas ?
|
|
m_tlb_m_updRepIdx_lat_0$wget[4:0] :
|
|
m_tlb_m_updRepIdx_rl[4:0]) ;
|
|
assign IF_m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec__ETC___d1425 =
|
|
(m_tlb_m_validVec_0 && m_tlb_m_validVec_1) ?
|
|
(m_tlb_m_validVec_2 ? 5'd3 : 5'd2) :
|
|
(m_tlb_m_validVec_0 ? 5'd1 : 5'd0) ;
|
|
assign IF_m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec__ETC___d1426 =
|
|
(m_tlb_m_validVec_0 && m_tlb_m_validVec_1 &&
|
|
m_tlb_m_validVec_2 &&
|
|
m_tlb_m_validVec_3) ?
|
|
IF_m_tlb_m_validVec_4_68_AND_m_tlb_m_validVec__ETC___d1422 :
|
|
IF_m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec__ETC___d1425 ;
|
|
assign IF_m_tlb_m_validVec_12_96_AND_m_tlb_m_validVec_ETC___d1415 =
|
|
(m_tlb_m_validVec_12 && m_tlb_m_validVec_13) ?
|
|
(m_tlb_m_validVec_14 ? 5'd15 : 5'd14) :
|
|
(m_tlb_m_validVec_12 ? 5'd13 : 5'd12) ;
|
|
assign IF_m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_ETC___d1410 =
|
|
(m_tlb_m_validVec_16 && m_tlb_m_validVec_17) ?
|
|
(m_tlb_m_validVec_18 ? 5'd19 : 5'd18) :
|
|
(m_tlb_m_validVec_16 ? 5'd17 : 5'd16) ;
|
|
assign IF_m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_ETC___d1411 =
|
|
(m_tlb_m_validVec_16 && m_tlb_m_validVec_17 &&
|
|
m_tlb_m_validVec_18 &&
|
|
m_tlb_m_validVec_19) ?
|
|
IF_m_tlb_m_validVec_20_024_AND_m_tlb_m_validVe_ETC___d1407 :
|
|
IF_m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_ETC___d1410 ;
|
|
assign IF_m_tlb_m_validVec_20_024_AND_m_tlb_m_validVe_ETC___d1407 =
|
|
(m_tlb_m_validVec_20 && m_tlb_m_validVec_21) ?
|
|
(m_tlb_m_validVec_22 ? 5'd23 : 5'd22) :
|
|
(m_tlb_m_validVec_20 ? 5'd21 : 5'd20) ;
|
|
assign IF_m_tlb_m_validVec_24_088_AND_m_tlb_m_validVe_ETC___d1403 =
|
|
(m_tlb_m_validVec_24 && m_tlb_m_validVec_25) ?
|
|
(m_tlb_m_validVec_26 ? 5'd27 : 5'd26) :
|
|
(m_tlb_m_validVec_24 ? 5'd25 : 5'd24) ;
|
|
assign IF_m_tlb_m_validVec_24_088_AND_m_tlb_m_validVe_ETC___d1404 =
|
|
(m_tlb_m_validVec_24 && m_tlb_m_validVec_25 &&
|
|
m_tlb_m_validVec_26 &&
|
|
m_tlb_m_validVec_27) ?
|
|
IF_m_tlb_m_validVec_28_152_AND_m_tlb_m_validVe_ETC___d1400 :
|
|
IF_m_tlb_m_validVec_24_088_AND_m_tlb_m_validVe_ETC___d1403 ;
|
|
assign IF_m_tlb_m_validVec_28_152_AND_m_tlb_m_validVe_ETC___d1400 =
|
|
(m_tlb_m_validVec_28 && m_tlb_m_validVec_29) ?
|
|
(m_tlb_m_validVec_30 ? 5'd31 : 5'd30) :
|
|
(m_tlb_m_validVec_28 ? 5'd29 : 5'd28) ;
|
|
assign IF_m_tlb_m_validVec_4_68_AND_m_tlb_m_validVec__ETC___d1422 =
|
|
(m_tlb_m_validVec_4 && m_tlb_m_validVec_5) ?
|
|
(m_tlb_m_validVec_6 ? 5'd7 : 5'd6) :
|
|
(m_tlb_m_validVec_4 ? 5'd5 : 5'd4) ;
|
|
assign IF_m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec__ETC___d1418 =
|
|
(m_tlb_m_validVec_8 && m_tlb_m_validVec_9) ?
|
|
(m_tlb_m_validVec_10 ? 5'd11 : 5'd10) :
|
|
(m_tlb_m_validVec_8 ? 5'd9 : 5'd8) ;
|
|
assign IF_m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec__ETC___d1419 =
|
|
(m_tlb_m_validVec_8 && m_tlb_m_validVec_9 &&
|
|
m_tlb_m_validVec_10 &&
|
|
m_tlb_m_validVec_11) ?
|
|
IF_m_tlb_m_validVec_12_96_AND_m_tlb_m_validVec_ETC___d1415 :
|
|
IF_m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec__ETC___d1418 ;
|
|
assign INV_n__read0928__q37 = ~n__read__h50928 ;
|
|
assign NOT_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT__ETC___d2694 =
|
|
level__h85474 != 2'd0 &&
|
|
((level__h85474 == 2'd1) ?
|
|
ppn__h90430[8:0] != 9'd0 :
|
|
level__h85474 != 2'd2 || ppn__h90430[17:0] != 18'd0) ||
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 &&
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 ;
|
|
assign NOT_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT__ETC___d2701 =
|
|
level__h85474 != 2'd0 &&
|
|
((level__h85474 == 2'd1) ?
|
|
ppn__h90430[8:0] != 9'd0 :
|
|
level__h85474 != 2'd2 || ppn__h90430[17:0] != 18'd0) ||
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 ;
|
|
assign NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BI_ETC___d1605 =
|
|
(!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627 &&
|
|
m_vm_info[45]) &&
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1604 ;
|
|
assign NOT_SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_83_ETC___d3230 =
|
|
{ !SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_835_NO_ETC___d2843,
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_835_NO_ETC___d2843 ?
|
|
SEL_ARR_m_pendInst_0_85_BITS_462_TO_458_845_m__ETC___d2850 :
|
|
{ 1'bx /* unspecified value */ ,
|
|
SEL_ARR_m_pendInst_0_85_BITS_461_TO_458_851_m__ETC___d2856 },
|
|
SEL_ARR_m_pendInst_0_85_BIT_457_859_m_pendInst_ETC___d2864,
|
|
SEL_ARR_m_pendInst_0_85_BIT_456_865_m_pendInst_ETC___d2870,
|
|
SEL_ARR_m_pendInst_0_85_BIT_455_872_m_pendInst_ETC___d2877,
|
|
SEL_ARR_m_pendInst_0_85_BIT_454_878_m_pendInst_ETC___d2883,
|
|
SEL_ARR_m_pendInst_0_85_BIT_453_885_m_pendInst_ETC___d2890,
|
|
SEL_ARR_m_pendInst_0_85_BIT_452_891_m_pendInst_ETC___d2896,
|
|
SEL_ARR_m_pendInst_0_85_BIT_451_898_m_pendInst_ETC___d2903,
|
|
SEL_ARR_m_pendInst_0_85_BIT_450_904_m_pendInst_ETC___d2909,
|
|
SEL_ARR_m_pendInst_0_85_BIT_449_911_m_pendInst_ETC___d2916,
|
|
SEL_ARR_m_pendInst_0_85_BIT_448_917_m_pendInst_ETC___d2922,
|
|
SEL_ARR_m_pendInst_0_85_BIT_447_924_m_pendInst_ETC___d2929,
|
|
SEL_ARR_m_pendInst_0_85_BIT_446_930_m_pendInst_ETC___d2935,
|
|
SEL_ARR_m_pendInst_0_85_BIT_445_937_m_pendInst_ETC___d2942,
|
|
SEL_ARR_m_pendInst_0_85_BIT_444_943_m_pendInst_ETC___d2948,
|
|
SEL_ARR_m_pendInst_0_85_BIT_443_950_m_pendInst_ETC___d2955,
|
|
SEL_ARR_m_pendInst_0_85_BIT_442_956_m_pendInst_ETC___d2961,
|
|
SEL_ARR_m_pendInst_0_85_BIT_441_963_m_pendInst_ETC___d2968,
|
|
SEL_ARR_m_pendInst_0_85_BITS_440_TO_375_739_m__ETC___d2969,
|
|
SEL_ARR_m_pendInst_0_85_BITS_374_TO_361_970_m__ETC___d2975,
|
|
SEL_ARR_m_pendInst_0_85_BITS_360_TO_357_976_m__ETC___d2981,
|
|
SEL_ARR_m_pendInst_0_85_BIT_356_982_m_pendInst_ETC___d2987,
|
|
SEL_ARR_m_pendInst_0_85_BIT_355_988_m_pendInst_ETC___d2993,
|
|
SEL_ARR_m_pendInst_0_85_BIT_354_994_m_pendInst_ETC___d2999,
|
|
SEL_ARR_m_pendInst_0_85_BIT_353_000_m_pendInst_ETC___d3005,
|
|
SEL_ARR_m_pendInst_0_85_BIT_352_006_m_pendInst_ETC___d3011,
|
|
SEL_ARR_m_pendInst_0_85_BIT_351_012_m_pendInst_ETC___d3017,
|
|
SEL_ARR_m_pendInst_0_85_BIT_350_018_m_pendInst_ETC___d3023,
|
|
SEL_ARR_m_pendInst_0_85_BIT_349_024_m_pendInst_ETC___d3029,
|
|
SEL_ARR_m_pendInst_0_85_BIT_348_030_m_pendInst_ETC___d3035,
|
|
SEL_ARR_m_pendInst_0_85_BIT_347_036_m_pendInst_ETC___d3041,
|
|
SEL_ARR_m_pendInst_0_85_BIT_346_042_m_pendInst_ETC___d3047,
|
|
SEL_ARR_m_pendInst_0_85_BIT_345_048_m_pendInst_ETC___d3053,
|
|
SEL_ARR_m_pendInst_0_85_BIT_344_060_m_pendInst_ETC___d3065,
|
|
SEL_ARR_m_pendInst_0_85_BITS_343_TO_342_066_m__ETC___d3071,
|
|
SEL_ARR_m_pendInst_0_85_BITS_341_TO_324_072_m__ETC___d3077,
|
|
SEL_ARR_m_pendInst_0_85_BIT_323_078_m_pendInst_ETC___d3083,
|
|
SEL_ARR_m_pendInst_0_85_BITS_322_TO_317_084_m__ETC___d3089,
|
|
x__h98052,
|
|
x__h98061,
|
|
SEL_ARR_m_pendInst_0_85_BITS_288_TO_286_107_m__ETC___d3112,
|
|
SEL_ARR_m_pendInst_0_85_BIT_285_113_m_pendInst_ETC___d3118,
|
|
SEL_ARR_m_pendInst_0_85_BIT_284_119_m_pendInst_ETC___d3124,
|
|
SEL_ARR_m_pendInst_0_85_BIT_283_125_m_pendInst_ETC___d3130,
|
|
SEL_ARR_m_pendInst_0_85_BITS_282_TO_281_131_m__ETC___d3136,
|
|
SEL_ARR_m_pendInst_0_85_BITS_280_TO_279_137_m__ETC___d3142,
|
|
SEL_ARR_m_pendInst_0_85_BIT_278_146_m_pendInst_ETC___d3151,
|
|
!SEL_ARR_NOT_m_pendInst_0_85_BIT_277_152_153_NO_ETC___d3161,
|
|
SEL_ARR_m_pendInst_0_85_BITS_276_TO_271_163_m__ETC___d3168,
|
|
SEL_ARR_m_pendInst_0_85_BITS_270_TO_266_169_m__ETC___d3174,
|
|
!SEL_ARR_NOT_m_pendInst_0_85_BIT_265_177_178_NO_ETC___d3186,
|
|
x__h98552,
|
|
x__h98589,
|
|
SEL_ARR_m_pendInst_0_85_BITS_135_TO_130_200_m__ETC___d3205,
|
|
x__h98607,
|
|
x__h98616,
|
|
SEL_ARR_m_pendInst_0_85_BIT_0_218_m_pendInst_1_ETC___d3223 } ;
|
|
assign NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_42_ETC___d2648 =
|
|
(!SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 ||
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 &&
|
|
m_vm_info[45]) &&
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2647 ;
|
|
assign NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d673 =
|
|
level__h38292 != 2'd0 &&
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[8:0] !=
|
|
9'd0 :
|
|
level__h38292 != 2'd2 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_65_m_ETC___d668 &&
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623 ||
|
|
!m_vm_info[46] ;
|
|
assign NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d685 =
|
|
level__h38292 != 2'd0 &&
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[8:0] !=
|
|
9'd0 :
|
|
level__h38292 != 2'd2 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623 ||
|
|
!m_vm_info[46] ;
|
|
assign NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1615 =
|
|
(SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 !=
|
|
3'd4 ||
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d605) &&
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d612 &&
|
|
IF_NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_ETC___d1613 ;
|
|
assign NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1660 =
|
|
NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_ETC___d1615 &&
|
|
(!m_tlb_m_validVec_0 ||
|
|
NOT_m_tlb_m_entryVec_0_98_BITS_79_TO_53_99_EQ__ETC___d717) &&
|
|
NOT_m_tlb_m_validVec_1_20_21_OR_NOT_m_tlb_m_en_ETC___d1658 ;
|
|
assign NOT_m_ldTransRsFromPQ_empty_68_96_AND_NOT_m_pe_ETC___d1318 =
|
|
!m_ldTransRsFromPQ_empty && m_pendWait_0[3:2] != 2'd0 &&
|
|
m_pendWait_0[3:2] != 2'd1 &&
|
|
m_pendWait_0_269_BITS_1_TO_0_289_EQ_SEL_ARR_m__ETC___d1290 &&
|
|
idx__h37917 != 2'd0 ||
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
m_pendWait_1_275_BITS_3_TO_2_276_EQ_0_277_OR_m_ETC___d1286 ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1818 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) &&
|
|
(!m_pendValid_1_rl || m_pendWait_1[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_1) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1822 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1818 &&
|
|
(!m_pendValid_2_rl || m_pendWait_2[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_2) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2788 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) &&
|
|
(!m_pendValid_1_rl || m_pendWait_1[3:2] != 2'd0 ||
|
|
m_pendPoisoned_1) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2790 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2788 &&
|
|
(!m_pendValid_2_rl || m_pendWait_2[3:2] != 2'd0 ||
|
|
m_pendPoisoned_2) ;
|
|
assign NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271__ETC___d1782 =
|
|
m_pendWait_0[3:2] != 2'd0 && m_pendWait_0[3:2] != 2'd1 &&
|
|
m_pendWait_0_269_BITS_1_TO_0_289_EQ_SEL_ARR_m__ETC___d1290 &&
|
|
idx__h37917 != 2'd0 ||
|
|
m_pendWait_1[3:2] != 2'd0 && m_pendWait_1[3:2] != 2'd1 &&
|
|
m_pendWait_1_275_BITS_1_TO_0_281_EQ_SEL_ARR_m__ETC___d1282 &&
|
|
idx__h37917 != 2'd1 ;
|
|
assign NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271__ETC___d1796 =
|
|
NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271__ETC___d1782 ||
|
|
m_pendWait_2[3:2] != 2'd0 && m_pendWait_2[3:2] != 2'd1 &&
|
|
m_pendWait_2_299_BITS_1_TO_0_305_EQ_SEL_ARR_m__ETC___d1306 &&
|
|
idx__h37917 != 2'd2 ||
|
|
m_pendWait_3[3:2] != 2'd0 && m_pendWait_3[3:2] != 2'd1 &&
|
|
m_pendWait_3_325_BITS_1_TO_0_331_EQ_SEL_ARR_m__ETC___d1332 &&
|
|
idx__h37917 != 2'd3 ;
|
|
assign NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_272__ETC___d2745 =
|
|
(m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2721) &&
|
|
(m_pendWait_1[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2724) &&
|
|
(m_pendWait_2[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2728) ;
|
|
assign NOT_m_tlb_m_entryVec_0_98_BITS_79_TO_53_99_EQ__ETC___d717 =
|
|
m_tlb_m_entryVec_0[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_0[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_0[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_10_67_BITS_79_TO_53_68_EQ_ETC___d878 =
|
|
m_tlb_m_entryVec_10[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_10[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_10[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_11_83_BITS_79_TO_53_84_EQ_ETC___d894 =
|
|
m_tlb_m_entryVec_11[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_11[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_11[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_12_99_BITS_79_TO_53_00_EQ_ETC___d910 =
|
|
m_tlb_m_entryVec_12[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_12[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_12[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_13_15_BITS_79_TO_53_16_EQ_ETC___d926 =
|
|
m_tlb_m_entryVec_13[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_13[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_13[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_14_31_BITS_79_TO_53_32_EQ_ETC___d942 =
|
|
m_tlb_m_entryVec_14[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_14[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_14[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_15_47_BITS_79_TO_53_48_EQ_ETC___d958 =
|
|
m_tlb_m_entryVec_15[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_15[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_15[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_16_63_BITS_79_TO_53_64_EQ_ETC___d974 =
|
|
m_tlb_m_entryVec_16[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_16[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_16[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_17_79_BITS_79_TO_53_80_EQ_ETC___d990 =
|
|
m_tlb_m_entryVec_17[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_17[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_17[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_18_95_BITS_79_TO_53_96_EQ_ETC___d1006 =
|
|
m_tlb_m_entryVec_18[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_18[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_18[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_19_011_BITS_79_TO_53_012__ETC___d1022 =
|
|
m_tlb_m_entryVec_19[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_19[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_19[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_1_23_BITS_79_TO_53_24_EQ__ETC___d734 =
|
|
m_tlb_m_entryVec_1[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_1[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_1[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_20_027_BITS_79_TO_53_028__ETC___d1038 =
|
|
m_tlb_m_entryVec_20[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_20[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_20[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_21_043_BITS_79_TO_53_044__ETC___d1054 =
|
|
m_tlb_m_entryVec_21[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_21[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_21[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_22_059_BITS_79_TO_53_060__ETC___d1070 =
|
|
m_tlb_m_entryVec_22[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_22[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_22[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_23_075_BITS_79_TO_53_076__ETC___d1086 =
|
|
m_tlb_m_entryVec_23[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_23[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_23[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_24_091_BITS_79_TO_53_092__ETC___d1102 =
|
|
m_tlb_m_entryVec_24[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_24[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_24[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_25_107_BITS_79_TO_53_108__ETC___d1118 =
|
|
m_tlb_m_entryVec_25[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_25[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_25[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_26_123_BITS_79_TO_53_124__ETC___d1134 =
|
|
m_tlb_m_entryVec_26[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_26[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_26[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_27_139_BITS_79_TO_53_140__ETC___d1150 =
|
|
m_tlb_m_entryVec_27[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_27[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_27[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_28_155_BITS_79_TO_53_156__ETC___d1166 =
|
|
m_tlb_m_entryVec_28[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_28[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_28[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_29_171_BITS_79_TO_53_172__ETC___d1182 =
|
|
m_tlb_m_entryVec_29[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_29[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_29[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_2_39_BITS_79_TO_53_40_EQ__ETC___d750 =
|
|
m_tlb_m_entryVec_2[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_2[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_2[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_30_187_BITS_79_TO_53_188__ETC___d1198 =
|
|
m_tlb_m_entryVec_30[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_30[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_30[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_3_55_BITS_79_TO_53_56_EQ__ETC___d766 =
|
|
m_tlb_m_entryVec_3[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_3[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_3[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_4_71_BITS_79_TO_53_72_EQ__ETC___d782 =
|
|
m_tlb_m_entryVec_4[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_4[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_4[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_5_87_BITS_79_TO_53_88_EQ__ETC___d798 =
|
|
m_tlb_m_entryVec_5[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_5[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_5[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_6_03_BITS_79_TO_53_04_EQ__ETC___d814 =
|
|
m_tlb_m_entryVec_6[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_6[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_6[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_7_19_BITS_79_TO_53_20_EQ__ETC___d830 =
|
|
m_tlb_m_entryVec_7[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_7[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_7[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_8_35_BITS_79_TO_53_36_EQ__ETC___d846 =
|
|
m_tlb_m_entryVec_8[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_8[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_8[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_entryVec_9_51_BITS_79_TO_53_52_EQ__ETC___d862 =
|
|
m_tlb_m_entryVec_9[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_9[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_9[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 ;
|
|
assign NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d693 =
|
|
!CAN_FIRE_RL_m_doStartFlush &&
|
|
(m_tlb_m_updRepIdx_lat_0$whas ?
|
|
!m_tlb_m_updRepIdx_lat_0$wget[5] :
|
|
!m_tlb_m_updRepIdx_rl[5]) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1877 =
|
|
!m_tlb_m_validVec_0 ||
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q2 !=
|
|
m_tlb_m_entryVec_0[79:53] ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1897 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1877 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_23_BITS_1_TO_0_27_EQ_0_8_ETC___d1884) &&
|
|
(!m_tlb_m_validVec_2 ||
|
|
!IF_m_tlb_m_entryVec_2_39_BITS_1_TO_0_43_EQ_0_8_ETC___d1894) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1917 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1897 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_55_BITS_1_TO_0_59_EQ_0_8_ETC___d1904) &&
|
|
(!m_tlb_m_validVec_4 ||
|
|
!IF_m_tlb_m_entryVec_4_71_BITS_1_TO_0_75_EQ_0_9_ETC___d1914) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1937 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1917 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_87_BITS_1_TO_0_91_EQ_0_9_ETC___d1924) &&
|
|
(!m_tlb_m_validVec_6 ||
|
|
!IF_m_tlb_m_entryVec_6_03_BITS_1_TO_0_07_EQ_0_9_ETC___d1934) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1957 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1937 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_19_BITS_1_TO_0_23_EQ_0_9_ETC___d1944) &&
|
|
(!m_tlb_m_validVec_8 ||
|
|
!IF_m_tlb_m_entryVec_8_35_BITS_1_TO_0_39_EQ_0_9_ETC___d1954) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1977 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1957 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_51_BITS_1_TO_0_55_EQ_0_9_ETC___d1964) &&
|
|
(!m_tlb_m_validVec_10 ||
|
|
!IF_m_tlb_m_entryVec_10_67_BITS_1_TO_0_71_EQ_0__ETC___d1974) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1997 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1977 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_83_BITS_1_TO_0_87_EQ_0__ETC___d1984) &&
|
|
(!m_tlb_m_validVec_12 ||
|
|
!IF_m_tlb_m_entryVec_12_99_BITS_1_TO_0_03_EQ_0__ETC___d1994) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2017 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d1997 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_15_BITS_1_TO_0_19_EQ_0__ETC___d2004) &&
|
|
(!m_tlb_m_validVec_14 ||
|
|
!IF_m_tlb_m_entryVec_14_31_BITS_1_TO_0_35_EQ_0__ETC___d2014) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2037 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2017 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_47_BITS_1_TO_0_51_EQ_0__ETC___d2024) &&
|
|
(!m_tlb_m_validVec_16 ||
|
|
!IF_m_tlb_m_entryVec_16_63_BITS_1_TO_0_67_EQ_0__ETC___d2034) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2057 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2037 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_79_BITS_1_TO_0_83_EQ_0__ETC___d2044) &&
|
|
(!m_tlb_m_validVec_18 ||
|
|
!IF_m_tlb_m_entryVec_18_95_BITS_1_TO_0_99_EQ_0__ETC___d2054) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2077 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2057 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_011_BITS_1_TO_0_015_EQ__ETC___d2064) &&
|
|
(!m_tlb_m_validVec_20 ||
|
|
!IF_m_tlb_m_entryVec_20_027_BITS_1_TO_0_031_EQ__ETC___d2074) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2097 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2077 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_043_BITS_1_TO_0_047_EQ__ETC___d2084) &&
|
|
(!m_tlb_m_validVec_22 ||
|
|
!IF_m_tlb_m_entryVec_22_059_BITS_1_TO_0_063_EQ__ETC___d2094) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2117 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2097 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_075_BITS_1_TO_0_079_EQ__ETC___d2104) &&
|
|
(!m_tlb_m_validVec_24 ||
|
|
!IF_m_tlb_m_entryVec_24_091_BITS_1_TO_0_095_EQ__ETC___d2114) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2137 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2117 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_107_BITS_1_TO_0_111_EQ__ETC___d2124) &&
|
|
(!m_tlb_m_validVec_26 ||
|
|
!IF_m_tlb_m_entryVec_26_123_BITS_1_TO_0_127_EQ__ETC___d2134) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2157 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2137 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_139_BITS_1_TO_0_143_EQ__ETC___d2144) &&
|
|
(!m_tlb_m_validVec_28 ||
|
|
!IF_m_tlb_m_entryVec_28_155_BITS_1_TO_0_159_EQ__ETC___d2154) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2177 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2157 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_171_BITS_1_TO_0_175_EQ__ETC___d2164) &&
|
|
(!m_tlb_m_validVec_30 ||
|
|
!IF_m_tlb_m_entryVec_30_187_BITS_1_TO_0_191_EQ__ETC___d2174) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2177 &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
!IF_m_tlb_m_entryVec_31_616_BITS_1_TO_0_620_EQ__ETC___d2184) &&
|
|
(m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_272_AND__ETC___d2730 ||
|
|
m_pendWait_3[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2732) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2177 &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
!IF_m_tlb_m_entryVec_31_616_BITS_1_TO_0_620_EQ__ETC___d2184) &&
|
|
NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_272__ETC___d2745 &&
|
|
(m_pendWait_3[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2732) ;
|
|
assign NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_va_ETC___d1347 =
|
|
!m_tlb_m_validVec_0 || !m_tlb_m_validVec_1 ||
|
|
!m_tlb_m_validVec_2 ||
|
|
!m_tlb_m_validVec_3 ||
|
|
!m_tlb_m_validVec_4 ||
|
|
!m_tlb_m_validVec_5 ||
|
|
!m_tlb_m_validVec_6 ||
|
|
!m_tlb_m_validVec_7 ;
|
|
assign NOT_m_tlb_m_validVec_11_80_81_OR_NOT_m_tlb_m_e_ETC___d1648 =
|
|
(!m_tlb_m_validVec_11 ||
|
|
NOT_m_tlb_m_entryVec_11_83_BITS_79_TO_53_84_EQ_ETC___d894) &&
|
|
(!m_tlb_m_validVec_12 ||
|
|
NOT_m_tlb_m_entryVec_12_99_BITS_79_TO_53_00_EQ_ETC___d910) &&
|
|
NOT_m_tlb_m_validVec_13_12_13_OR_NOT_m_tlb_m_e_ETC___d1646 ;
|
|
assign NOT_m_tlb_m_validVec_13_12_13_OR_NOT_m_tlb_m_e_ETC___d1646 =
|
|
(!m_tlb_m_validVec_13 ||
|
|
NOT_m_tlb_m_entryVec_13_15_BITS_79_TO_53_16_EQ_ETC___d926) &&
|
|
(!m_tlb_m_validVec_14 ||
|
|
NOT_m_tlb_m_entryVec_14_31_BITS_79_TO_53_32_EQ_ETC___d942) &&
|
|
NOT_m_tlb_m_validVec_15_44_45_OR_NOT_m_tlb_m_e_ETC___d1644 ;
|
|
assign NOT_m_tlb_m_validVec_15_44_45_OR_NOT_m_tlb_m_e_ETC___d1644 =
|
|
(!m_tlb_m_validVec_15 ||
|
|
NOT_m_tlb_m_entryVec_15_47_BITS_79_TO_53_48_EQ_ETC___d958) &&
|
|
(!m_tlb_m_validVec_16 ||
|
|
NOT_m_tlb_m_entryVec_16_63_BITS_79_TO_53_64_EQ_ETC___d974) &&
|
|
NOT_m_tlb_m_validVec_17_76_77_OR_NOT_m_tlb_m_e_ETC___d1642 ;
|
|
assign NOT_m_tlb_m_validVec_16_60_61_OR_NOT_m_tlb_m_v_ETC___d1362 =
|
|
!m_tlb_m_validVec_16 || !m_tlb_m_validVec_17 ||
|
|
!m_tlb_m_validVec_18 ||
|
|
!m_tlb_m_validVec_19 ||
|
|
!m_tlb_m_validVec_20 ||
|
|
!m_tlb_m_validVec_21 ||
|
|
!m_tlb_m_validVec_22 ||
|
|
!m_tlb_m_validVec_23 ;
|
|
assign NOT_m_tlb_m_validVec_17_76_77_OR_NOT_m_tlb_m_e_ETC___d1642 =
|
|
(!m_tlb_m_validVec_17 ||
|
|
NOT_m_tlb_m_entryVec_17_79_BITS_79_TO_53_80_EQ_ETC___d990) &&
|
|
(!m_tlb_m_validVec_18 ||
|
|
NOT_m_tlb_m_entryVec_18_95_BITS_79_TO_53_96_EQ_ETC___d1006) &&
|
|
NOT_m_tlb_m_validVec_19_008_009_OR_NOT_m_tlb_m_ETC___d1640 ;
|
|
assign NOT_m_tlb_m_validVec_19_008_009_OR_NOT_m_tlb_m_ETC___d1640 =
|
|
(!m_tlb_m_validVec_19 ||
|
|
NOT_m_tlb_m_entryVec_19_011_BITS_79_TO_53_012__ETC___d1022) &&
|
|
(!m_tlb_m_validVec_20 ||
|
|
NOT_m_tlb_m_entryVec_20_027_BITS_79_TO_53_028__ETC___d1038) &&
|
|
NOT_m_tlb_m_validVec_21_040_041_OR_NOT_m_tlb_m_ETC___d1638 ;
|
|
assign NOT_m_tlb_m_validVec_1_20_21_OR_NOT_m_tlb_m_en_ETC___d1658 =
|
|
(!m_tlb_m_validVec_1 ||
|
|
NOT_m_tlb_m_entryVec_1_23_BITS_79_TO_53_24_EQ__ETC___d734) &&
|
|
(!m_tlb_m_validVec_2 ||
|
|
NOT_m_tlb_m_entryVec_2_39_BITS_79_TO_53_40_EQ__ETC___d750) &&
|
|
NOT_m_tlb_m_validVec_3_52_53_OR_NOT_m_tlb_m_en_ETC___d1656 ;
|
|
assign NOT_m_tlb_m_validVec_21_040_041_OR_NOT_m_tlb_m_ETC___d1638 =
|
|
(!m_tlb_m_validVec_21 ||
|
|
NOT_m_tlb_m_entryVec_21_043_BITS_79_TO_53_044__ETC___d1054) &&
|
|
(!m_tlb_m_validVec_22 ||
|
|
NOT_m_tlb_m_entryVec_22_059_BITS_79_TO_53_060__ETC___d1070) &&
|
|
NOT_m_tlb_m_validVec_23_072_073_OR_NOT_m_tlb_m_ETC___d1636 ;
|
|
assign NOT_m_tlb_m_validVec_23_072_073_OR_NOT_m_tlb_m_ETC___d1636 =
|
|
(!m_tlb_m_validVec_23 ||
|
|
NOT_m_tlb_m_entryVec_23_075_BITS_79_TO_53_076__ETC___d1086) &&
|
|
(!m_tlb_m_validVec_24 ||
|
|
NOT_m_tlb_m_entryVec_24_091_BITS_79_TO_53_092__ETC___d1102) &&
|
|
NOT_m_tlb_m_validVec_25_104_105_OR_NOT_m_tlb_m_ETC___d1634 ;
|
|
assign NOT_m_tlb_m_validVec_24_088_089_OR_NOT_m_tlb_m_ETC___d1369 =
|
|
!m_tlb_m_validVec_24 || !m_tlb_m_validVec_25 ||
|
|
!m_tlb_m_validVec_26 ||
|
|
!m_tlb_m_validVec_27 ||
|
|
!m_tlb_m_validVec_28 ||
|
|
!m_tlb_m_validVec_29 ||
|
|
!m_tlb_m_validVec_30 ||
|
|
!m_tlb_m_validVec_31 ;
|
|
assign NOT_m_tlb_m_validVec_25_104_105_OR_NOT_m_tlb_m_ETC___d1634 =
|
|
(!m_tlb_m_validVec_25 ||
|
|
NOT_m_tlb_m_entryVec_25_107_BITS_79_TO_53_108__ETC___d1118) &&
|
|
(!m_tlb_m_validVec_26 ||
|
|
NOT_m_tlb_m_entryVec_26_123_BITS_79_TO_53_124__ETC___d1134) &&
|
|
NOT_m_tlb_m_validVec_27_136_137_OR_NOT_m_tlb_m_ETC___d1632 ;
|
|
assign NOT_m_tlb_m_validVec_27_136_137_OR_NOT_m_tlb_m_ETC___d1632 =
|
|
(!m_tlb_m_validVec_27 ||
|
|
NOT_m_tlb_m_entryVec_27_139_BITS_79_TO_53_140__ETC___d1150) &&
|
|
(!m_tlb_m_validVec_28 ||
|
|
NOT_m_tlb_m_entryVec_28_155_BITS_79_TO_53_156__ETC___d1166) &&
|
|
NOT_m_tlb_m_validVec_29_168_169_OR_NOT_m_tlb_m_ETC___d1630 ;
|
|
assign NOT_m_tlb_m_validVec_29_168_169_OR_NOT_m_tlb_m_ETC___d1630 =
|
|
(!m_tlb_m_validVec_29 ||
|
|
NOT_m_tlb_m_entryVec_29_171_BITS_79_TO_53_172__ETC___d1182) &&
|
|
(!m_tlb_m_validVec_30 ||
|
|
NOT_m_tlb_m_entryVec_30_187_BITS_79_TO_53_188__ETC___d1198) &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
m_tlb_m_entryVec_31[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 ||
|
|
m_tlb_m_entryVec_31[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_31[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714) ;
|
|
assign NOT_m_tlb_m_validVec_3_52_53_OR_NOT_m_tlb_m_en_ETC___d1656 =
|
|
(!m_tlb_m_validVec_3 ||
|
|
NOT_m_tlb_m_entryVec_3_55_BITS_79_TO_53_56_EQ__ETC___d766) &&
|
|
(!m_tlb_m_validVec_4 ||
|
|
NOT_m_tlb_m_entryVec_4_71_BITS_79_TO_53_72_EQ__ETC___d782) &&
|
|
NOT_m_tlb_m_validVec_5_84_85_OR_NOT_m_tlb_m_en_ETC___d1654 ;
|
|
assign NOT_m_tlb_m_validVec_5_84_85_OR_NOT_m_tlb_m_en_ETC___d1654 =
|
|
(!m_tlb_m_validVec_5 ||
|
|
NOT_m_tlb_m_entryVec_5_87_BITS_79_TO_53_88_EQ__ETC___d798) &&
|
|
(!m_tlb_m_validVec_6 ||
|
|
NOT_m_tlb_m_entryVec_6_03_BITS_79_TO_53_04_EQ__ETC___d814) &&
|
|
NOT_m_tlb_m_validVec_7_16_17_OR_NOT_m_tlb_m_en_ETC___d1652 ;
|
|
assign NOT_m_tlb_m_validVec_7_16_17_OR_NOT_m_tlb_m_en_ETC___d1652 =
|
|
(!m_tlb_m_validVec_7 ||
|
|
NOT_m_tlb_m_entryVec_7_19_BITS_79_TO_53_20_EQ__ETC___d830) &&
|
|
(!m_tlb_m_validVec_8 ||
|
|
NOT_m_tlb_m_entryVec_8_35_BITS_79_TO_53_36_EQ__ETC___d846) &&
|
|
NOT_m_tlb_m_validVec_9_48_49_OR_NOT_m_tlb_m_en_ETC___d1650 ;
|
|
assign NOT_m_tlb_m_validVec_8_32_33_OR_NOT_m_tlb_m_va_ETC___d1354 =
|
|
!m_tlb_m_validVec_8 || !m_tlb_m_validVec_9 ||
|
|
!m_tlb_m_validVec_10 ||
|
|
!m_tlb_m_validVec_11 ||
|
|
!m_tlb_m_validVec_12 ||
|
|
!m_tlb_m_validVec_13 ||
|
|
!m_tlb_m_validVec_14 ||
|
|
!m_tlb_m_validVec_15 ;
|
|
assign NOT_m_tlb_m_validVec_9_48_49_OR_NOT_m_tlb_m_en_ETC___d1650 =
|
|
(!m_tlb_m_validVec_9 ||
|
|
NOT_m_tlb_m_entryVec_9_51_BITS_79_TO_53_52_EQ__ETC___d862) &&
|
|
(!m_tlb_m_validVec_10 ||
|
|
NOT_m_tlb_m_entryVec_10_67_BITS_79_TO_53_68_EQ_ETC___d878) &&
|
|
NOT_m_tlb_m_validVec_11_80_81_OR_NOT_m_tlb_m_e_ETC___d1648 ;
|
|
assign NOT_procReq_req_BITS_490_TO_488_247_EQ_1_248_2_ETC___d2659 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4 ||
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352) &&
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 &&
|
|
IF_NOT_procReq_req_BITS_490_TO_488_247_EQ_1_24_ETC___d2657 ;
|
|
assign SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d678 =
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623 &&
|
|
(!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627 ||
|
|
!m_vm_info[45]) ||
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d677 ;
|
|
assign SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2698 =
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 &&
|
|
(!SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 ||
|
|
!m_vm_info[45]) ||
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_I_ETC___d2697 ;
|
|
assign SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2663 =
|
|
idx__h73608 == 2'd0 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
NOT_procReq_req_BITS_490_TO_488_247_EQ_1_248_2_ETC___d2659 ;
|
|
assign SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2664 =
|
|
idx__h73608 == 2'd1 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
NOT_procReq_req_BITS_490_TO_488_247_EQ_1_248_2_ETC___d2659 ;
|
|
assign SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2665 =
|
|
idx__h73608 == 2'd2 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
NOT_procReq_req_BITS_490_TO_488_247_EQ_1_248_2_ETC___d2659 ;
|
|
assign SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2666 =
|
|
idx__h73608 == 2'd3 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
NOT_procReq_req_BITS_490_TO_488_247_EQ_1_248_2_ETC___d2659 ;
|
|
assign SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2711 =
|
|
idx__h73608 == 2'd0 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
procReq_req_BITS_490_TO_488_247_EQ_1_248_OR_pr_ETC___d2708 ;
|
|
assign SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2712 =
|
|
idx__h73608 == 2'd1 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
procReq_req_BITS_490_TO_488_247_EQ_1_248_OR_pr_ETC___d2708 ;
|
|
assign SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2713 =
|
|
idx__h73608 == 2'd2 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
procReq_req_BITS_490_TO_488_247_EQ_1_248_OR_pr_ETC___d2708 ;
|
|
assign SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2714 =
|
|
idx__h73608 == 2'd3 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2246 &&
|
|
procReq_req_BITS_490_TO_488_247_EQ_1_248_OR_pr_ETC___d2708 ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d1600 =
|
|
(level__h38292 == 2'd0 ||
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[8:0] ==
|
|
9'd0 :
|
|
level__h38292 == 2'd2 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[17:0] ==
|
|
18'd0)) &&
|
|
(!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_65_m_ETC___d668 ||
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623) &&
|
|
m_vm_info[46] ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d1608 =
|
|
(level__h38292 == 2'd0 ||
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[8:0] ==
|
|
9'd0 :
|
|
level__h38292 == 2'd2 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[17:0] ==
|
|
18'd0)) &&
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623 &&
|
|
m_vm_info[46] ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_10_00__ETC___d1733 =
|
|
{ CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q34,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_9_07_m_ETC___d1732,
|
|
level__h38292 } ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_9_07_m_ETC___d1732 =
|
|
{ CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q33,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_34_m_ETC___d637,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_65_m_ETC___d668,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_18_m_ETC___d680 } ;
|
|
assign SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d692 =
|
|
(SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 ==
|
|
3'd1 ||
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 ==
|
|
3'd3 ||
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 ==
|
|
3'd4) &&
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d605 ||
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d612 ||
|
|
IF_NOT_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_ETC___d690 ;
|
|
assign _2_CONCAT_IF_NOT_m_pendWait_0_269_BITS_3_TO_2_2_ETC___d2749 =
|
|
{ 2'd2,
|
|
NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_272__ETC___d2745 ?
|
|
2'd3 :
|
|
IF_NOT_m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_2_ETC___d2747 } ;
|
|
assign _dfoo1 =
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d692 ||
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ;
|
|
assign _dfoo11 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1759 ||
|
|
_dfoo3 ;
|
|
assign _dfoo13 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1758 ||
|
|
_dfoo5 ;
|
|
assign _dfoo15 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1738 ||
|
|
_dfoo7 ;
|
|
assign _dfoo25 =
|
|
idx__h73608 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735 ||
|
|
idx__h73608 == 2'd3 &&
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo26 =
|
|
(idx__h73608 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735) ?
|
|
_2_CONCAT_IF_NOT_m_pendWait_0_269_BITS_3_TO_2_2_ETC___d2749 :
|
|
((idx__h73608 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756) ?
|
|
{ 2'd1, 2'bxx /* unspecified value */ } :
|
|
{ 2'd0, 2'bxx /* unspecified value */ }) ;
|
|
assign _dfoo27 =
|
|
idx__h73608 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735 ||
|
|
idx__h73608 == 2'd2 &&
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo28 =
|
|
(idx__h73608 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735) ?
|
|
_2_CONCAT_IF_NOT_m_pendWait_0_269_BITS_3_TO_2_2_ETC___d2749 :
|
|
((idx__h73608 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756) ?
|
|
{ 2'd1, 2'bxx /* unspecified value */ } :
|
|
{ 2'd0, 2'bxx /* unspecified value */ }) ;
|
|
assign _dfoo29 =
|
|
idx__h73608 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735 ||
|
|
idx__h73608 == 2'd1 &&
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo3 =
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d692 ||
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ;
|
|
assign _dfoo30 =
|
|
(idx__h73608 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735) ?
|
|
_2_CONCAT_IF_NOT_m_pendWait_0_269_BITS_3_TO_2_2_ETC___d2749 :
|
|
((idx__h73608 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756) ?
|
|
{ 2'd1, 2'bxx /* unspecified value */ } :
|
|
{ 2'd0, 2'bxx /* unspecified value */ }) ;
|
|
assign _dfoo31 =
|
|
idx__h73608 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735 ||
|
|
idx__h73608 == 2'd0 &&
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo32 =
|
|
(idx__h73608 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2735) ?
|
|
_2_CONCAT_IF_NOT_m_pendWait_0_269_BITS_3_TO_2_2_ETC___d2749 :
|
|
((idx__h73608 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2756) ?
|
|
{ 2'd1, 2'bxx /* unspecified value */ } :
|
|
{ 2'd0, 2'bxx /* unspecified value */ }) ;
|
|
assign _dfoo49 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2666 ||
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2714 ||
|
|
idx__h73608 == 2'd3 && !m_vm_info[46] ;
|
|
assign _dfoo5 =
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d692 ||
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ;
|
|
assign _dfoo51 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2665 ||
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2713 ||
|
|
idx__h73608 == 2'd2 && !m_vm_info[46] ;
|
|
assign _dfoo53 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2664 ||
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2712 ||
|
|
idx__h73608 == 2'd1 && !m_vm_info[46] ;
|
|
assign _dfoo55 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2663 ||
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2711 ||
|
|
idx__h73608 == 2'd0 && !m_vm_info[46] ;
|
|
assign _dfoo57 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2666 ||
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2714 ||
|
|
_dfoo25 ;
|
|
assign _dfoo59 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2665 ||
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2713 ||
|
|
_dfoo27 ;
|
|
assign _dfoo61 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2664 ||
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2712 ||
|
|
_dfoo29 ;
|
|
assign _dfoo63 =
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2663 ||
|
|
SEL_ARR_m_freeQ_data_0_843_m_freeQ_data_1_844__ETC___d2711 ||
|
|
_dfoo31 ;
|
|
assign _dfoo7 =
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d692 ||
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ;
|
|
assign _dfoo9 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1761 ||
|
|
_dfoo1 ;
|
|
assign _theResult_____2__h13508 =
|
|
IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 ?
|
|
next_deqP___1__h13697 :
|
|
m_freeQ_deqP ;
|
|
assign _theResult_____2__h17468 =
|
|
IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 ?
|
|
next_deqP___1__h17657 :
|
|
m_rqToPQ_deqP ;
|
|
assign _theResult_____2__h22136 =
|
|
IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 ?
|
|
next_deqP___1__h22325 :
|
|
m_ldTransRsFromPQ_deqP ;
|
|
assign addIdx__h55557 =
|
|
(!INV_n__read0928__q37[0] && !INV_n__read0928__q37[1] &&
|
|
!INV_n__read0928__q37[2] &&
|
|
!INV_n__read0928__q37[3] &&
|
|
!INV_n__read0928__q37[4] &&
|
|
!INV_n__read0928__q37[5] &&
|
|
!INV_n__read0928__q37[6] &&
|
|
!INV_n__read0928__q37[7] &&
|
|
!INV_n__read0928__q37[8] &&
|
|
!INV_n__read0928__q37[9] &&
|
|
!INV_n__read0928__q37[10] &&
|
|
!INV_n__read0928__q37[11] &&
|
|
!INV_n__read0928__q37[12] &&
|
|
!INV_n__read0928__q37[13] &&
|
|
!INV_n__read0928__q37[14] &&
|
|
!INV_n__read0928__q37[15]) ?
|
|
((!INV_n__read0928__q37[16] && !INV_n__read0928__q37[17] &&
|
|
!INV_n__read0928__q37[18] &&
|
|
!INV_n__read0928__q37[19] &&
|
|
!INV_n__read0928__q37[20] &&
|
|
!INV_n__read0928__q37[21] &&
|
|
!INV_n__read0928__q37[22] &&
|
|
!INV_n__read0928__q37[23]) ?
|
|
((!INV_n__read0928__q37[24] && !INV_n__read0928__q37[25] &&
|
|
!INV_n__read0928__q37[26] &&
|
|
!INV_n__read0928__q37[27]) ?
|
|
((!INV_n__read0928__q37[28] &&
|
|
!INV_n__read0928__q37[29]) ?
|
|
(INV_n__read0928__q37[30] ? 5'd30 : 5'd31) :
|
|
(INV_n__read0928__q37[28] ? 5'd28 : 5'd29)) :
|
|
((!INV_n__read0928__q37[24] &&
|
|
!INV_n__read0928__q37[25]) ?
|
|
(INV_n__read0928__q37[26] ? 5'd26 : 5'd27) :
|
|
(INV_n__read0928__q37[24] ? 5'd24 : 5'd25))) :
|
|
((!INV_n__read0928__q37[16] && !INV_n__read0928__q37[17] &&
|
|
!INV_n__read0928__q37[18] &&
|
|
!INV_n__read0928__q37[19]) ?
|
|
((!INV_n__read0928__q37[20] &&
|
|
!INV_n__read0928__q37[21]) ?
|
|
(INV_n__read0928__q37[22] ? 5'd22 : 5'd23) :
|
|
(INV_n__read0928__q37[20] ? 5'd20 : 5'd21)) :
|
|
((!INV_n__read0928__q37[16] &&
|
|
!INV_n__read0928__q37[17]) ?
|
|
(INV_n__read0928__q37[18] ? 5'd18 : 5'd19) :
|
|
(INV_n__read0928__q37[16] ? 5'd16 : 5'd17)))) :
|
|
((!INV_n__read0928__q37[0] && !INV_n__read0928__q37[1] &&
|
|
!INV_n__read0928__q37[2] &&
|
|
!INV_n__read0928__q37[3] &&
|
|
!INV_n__read0928__q37[4] &&
|
|
!INV_n__read0928__q37[5] &&
|
|
!INV_n__read0928__q37[6] &&
|
|
!INV_n__read0928__q37[7]) ?
|
|
((!INV_n__read0928__q37[8] && !INV_n__read0928__q37[9] &&
|
|
!INV_n__read0928__q37[10] &&
|
|
!INV_n__read0928__q37[11]) ?
|
|
((!INV_n__read0928__q37[12] &&
|
|
!INV_n__read0928__q37[13]) ?
|
|
(INV_n__read0928__q37[14] ? 5'd14 : 5'd15) :
|
|
(INV_n__read0928__q37[12] ? 5'd12 : 5'd13)) :
|
|
((!INV_n__read0928__q37[8] && !INV_n__read0928__q37[9]) ?
|
|
(INV_n__read0928__q37[10] ? 5'd10 : 5'd11) :
|
|
(INV_n__read0928__q37[8] ? 5'd8 : 5'd9))) :
|
|
((!INV_n__read0928__q37[0] && !INV_n__read0928__q37[1] &&
|
|
!INV_n__read0928__q37[2] &&
|
|
!INV_n__read0928__q37[3]) ?
|
|
((!INV_n__read0928__q37[4] && !INV_n__read0928__q37[5]) ?
|
|
(INV_n__read0928__q37[6] ? 5'd6 : 5'd7) :
|
|
(INV_n__read0928__q37[4] ? 5'd4 : 5'd5)) :
|
|
((!INV_n__read0928__q37[0] && !INV_n__read0928__q37[1]) ?
|
|
(INV_n__read0928__q37[2] ? 5'd2 : 5'd3) :
|
|
(INV_n__read0928__q37[0] ? 5'd0 : 5'd1)))) ;
|
|
assign addIdx__h60407 =
|
|
(m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec_1_2_ETC___d1378 &&
|
|
m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec_9_4_ETC___d1385) ?
|
|
(m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_17_ETC___d1393 ?
|
|
IF_m_tlb_m_validVec_24_088_AND_m_tlb_m_validVe_ETC___d1404 :
|
|
IF_m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_ETC___d1411) :
|
|
(m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec_1_2_ETC___d1378 ?
|
|
IF_m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec__ETC___d1419 :
|
|
IF_m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec__ETC___d1426) ;
|
|
assign idx__h37917 =
|
|
m_respForOtherReq[2] ?
|
|
m_respForOtherReq[1:0] :
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign idx__h73220 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1822 ?
|
|
2'd3 :
|
|
(NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1818 ?
|
|
2'd2 :
|
|
((!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign idx__h85435 =
|
|
NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tlb_m_ETC___d2177 ?
|
|
5'd31 :
|
|
IF_NOT_m_tlb_m_validVec_0_94_95_OR_NOT_IF_m_tl_ETC___d2350 ;
|
|
assign idx__h93065 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2790 ?
|
|
2'd3 :
|
|
(NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2788 ?
|
|
2'd2 :
|
|
((!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign m_pendWait_0_269_BITS_1_TO_0_289_EQ_SEL_ARR_m__ETC___d1290 =
|
|
m_pendWait_0[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1288 =
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
m_pendWait_1_275_BITS_3_TO_2_276_EQ_0_277_OR_m_ETC___d1286 ;
|
|
assign m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1297 =
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_pendWait_0_269_BITS_1_TO_0_289_EQ_SEL_ARR_m__ETC___d1290 ||
|
|
idx__h37917 == 2'd0) &&
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_pendWait_1_275_BITS_1_TO_0_281_EQ_SEL_ARR_m__ETC___d1282 ||
|
|
idx__h37917 == 2'd1) ;
|
|
assign m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1323 =
|
|
m_pendWait_0_269_BITS_3_TO_2_270_EQ_0_271_OR_m_ETC___d1297 &&
|
|
(m_pendWait_2[3:2] == 2'd0 || m_pendWait_2[3:2] == 2'd1 ||
|
|
!m_pendWait_2_299_BITS_1_TO_0_305_EQ_SEL_ARR_m__ETC___d1306 ||
|
|
idx__h37917 == 2'd2) ;
|
|
assign m_pendWait_0_269_BITS_3_TO_2_270_EQ_1_272_AND__ETC___d2730 =
|
|
m_pendWait_0[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2721 ||
|
|
m_pendWait_1[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2724 ||
|
|
m_pendWait_2[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2728 ;
|
|
assign m_pendWait_1_275_BITS_1_TO_0_281_EQ_SEL_ARR_m__ETC___d1282 =
|
|
m_pendWait_1[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign m_pendWait_1_275_BITS_3_TO_2_276_EQ_0_277_OR_m_ETC___d1286 =
|
|
m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_pendWait_1_275_BITS_1_TO_0_281_EQ_SEL_ARR_m__ETC___d1282 ||
|
|
m_respForOtherReq[2] ||
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign m_pendWait_2_299_BITS_1_TO_0_305_EQ_SEL_ARR_m__ETC___d1306 =
|
|
m_pendWait_2[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign m_pendWait_3_325_BITS_1_TO_0_331_EQ_SEL_ARR_m__ETC___d1332 =
|
|
m_pendWait_3[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign m_tlb_m_validVec_0_94_AND_m_tlb_m_validVec_1_2_ETC___d1378 =
|
|
m_tlb_m_validVec_0 && m_tlb_m_validVec_1 && m_tlb_m_validVec_2 &&
|
|
m_tlb_m_validVec_3 &&
|
|
m_tlb_m_validVec_4 &&
|
|
m_tlb_m_validVec_5 &&
|
|
m_tlb_m_validVec_6 &&
|
|
m_tlb_m_validVec_7 ;
|
|
assign m_tlb_m_validVec_16_60_AND_m_tlb_m_validVec_17_ETC___d1393 =
|
|
m_tlb_m_validVec_16 && m_tlb_m_validVec_17 &&
|
|
m_tlb_m_validVec_18 &&
|
|
m_tlb_m_validVec_19 &&
|
|
m_tlb_m_validVec_20 &&
|
|
m_tlb_m_validVec_21 &&
|
|
m_tlb_m_validVec_22 &&
|
|
m_tlb_m_validVec_23 ;
|
|
assign m_tlb_m_validVec_8_32_AND_m_tlb_m_validVec_9_4_ETC___d1385 =
|
|
m_tlb_m_validVec_8 && m_tlb_m_validVec_9 &&
|
|
m_tlb_m_validVec_10 &&
|
|
m_tlb_m_validVec_11 &&
|
|
m_tlb_m_validVec_12 &&
|
|
m_tlb_m_validVec_13 &&
|
|
m_tlb_m_validVec_14 &&
|
|
m_tlb_m_validVec_15 ;
|
|
assign n__read__h100423 =
|
|
MUX_m_pendPoisoned_0$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_0_rl ;
|
|
assign n__read__h100554 =
|
|
MUX_m_pendPoisoned_1$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_1_rl ;
|
|
assign n__read__h100685 =
|
|
MUX_m_pendPoisoned_2$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_2_rl ;
|
|
assign n__read__h100816 =
|
|
MUX_m_pendPoisoned_3$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_3_rl ;
|
|
assign n__read__h50928 =
|
|
m_tlb_m_lruBit_lat_0$whas ? upd__h50955 : m_tlb_m_lruBit_rl ;
|
|
assign next_deqP___1__h13697 =
|
|
(m_freeQ_deqP == 2'd3) ? 2'd0 : m_freeQ_deqP + 2'd1 ;
|
|
assign next_deqP___1__h17657 =
|
|
(m_rqToPQ_deqP == 2'd3) ? 2'd0 : m_rqToPQ_deqP + 2'd1 ;
|
|
assign next_deqP___1__h22325 = m_ldTransRsFromPQ_deqP + 1'd1 ;
|
|
assign procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2721 =
|
|
procReq_req[425:399] == m_pendInst_0[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2724 =
|
|
procReq_req[425:399] == m_pendInst_1[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2728 =
|
|
procReq_req[425:399] == m_pendInst_2[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_865_EQ_m_pendInst__ETC___d2732 =
|
|
procReq_req[425:399] == m_pendInst_3[413:387] ;
|
|
assign procReq_req_BITS_490_TO_488_247_EQ_1_248_OR_pr_ETC___d2708 =
|
|
(procReq_req[490:488] == 3'd1 || procReq_req[490:488] == 3'd3 ||
|
|
procReq_req[490:488] == 3'd4) &&
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 ||
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 ||
|
|
IF_NOT_procReq_req_BITS_490_TO_488_247_EQ_1_24_ETC___d2706 ;
|
|
assign upd__h10027 = n__read__h100816 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h50955 =
|
|
WILL_FIRE_RL_m_tlb_m_doUpdateRep ?
|
|
MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1 :
|
|
32'd0 ;
|
|
assign upd__h8992 = n__read__h100423 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h9337 = n__read__h100554 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h9682 = n__read__h100685 & specUpdate_correctSpeculation_mask ;
|
|
assign v__h13028 =
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ?
|
|
v__h13179 :
|
|
m_freeQ_enqP ;
|
|
assign v__h13179 = (m_freeQ_enqP == 2'd3) ? 2'd0 : m_freeQ_enqP + 2'd1 ;
|
|
assign v__h16896 =
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ?
|
|
v__h17047 :
|
|
m_rqToPQ_enqP ;
|
|
assign v__h17047 = (m_rqToPQ_enqP == 2'd3) ? 2'd0 : m_rqToPQ_enqP + 2'd1 ;
|
|
assign v__h21066 =
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ?
|
|
v__h21217 :
|
|
m_ldTransRsFromPQ_enqP ;
|
|
assign v__h21217 = m_ldTransRsFromPQ_enqP + 1'd1 ;
|
|
assign v__h45375 =
|
|
(NOT_m_tlb_m_validVec_0_94_95_OR_NOT_m_tlb_m_va_ETC___d1347 ||
|
|
NOT_m_tlb_m_validVec_8_32_33_OR_NOT_m_tlb_m_va_ETC___d1354 ||
|
|
NOT_m_tlb_m_validVec_16_60_61_OR_NOT_m_tlb_m_v_ETC___d1362 ||
|
|
NOT_m_tlb_m_validVec_24_088_089_OR_NOT_m_tlb_m_ETC___d1369) ?
|
|
addIdx__h60407 :
|
|
v__h50192 ;
|
|
assign v__h50192 =
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 ?
|
|
m_tlb_m_randIdx :
|
|
v__h51720 ;
|
|
assign v__h51720 =
|
|
(INV_n__read0928__q37[0] || INV_n__read0928__q37[1] ||
|
|
INV_n__read0928__q37[2] ||
|
|
INV_n__read0928__q37[3] ||
|
|
INV_n__read0928__q37[4] ||
|
|
INV_n__read0928__q37[5] ||
|
|
INV_n__read0928__q37[6] ||
|
|
INV_n__read0928__q37[7] ||
|
|
INV_n__read0928__q37[8] ||
|
|
INV_n__read0928__q37[9] ||
|
|
INV_n__read0928__q37[10] ||
|
|
INV_n__read0928__q37[11] ||
|
|
INV_n__read0928__q37[12] ||
|
|
INV_n__read0928__q37[13] ||
|
|
INV_n__read0928__q37[14] ||
|
|
INV_n__read0928__q37[15] ||
|
|
INV_n__read0928__q37[16] ||
|
|
INV_n__read0928__q37[17] ||
|
|
INV_n__read0928__q37[18] ||
|
|
INV_n__read0928__q37[19] ||
|
|
INV_n__read0928__q37[20] ||
|
|
INV_n__read0928__q37[21] ||
|
|
INV_n__read0928__q37[22] ||
|
|
INV_n__read0928__q37[23] ||
|
|
INV_n__read0928__q37[24] ||
|
|
INV_n__read0928__q37[25] ||
|
|
INV_n__read0928__q37[26] ||
|
|
INV_n__read0928__q37[27] ||
|
|
INV_n__read0928__q37[28] ||
|
|
INV_n__read0928__q37[29] ||
|
|
INV_n__read0928__q37[30] ||
|
|
INV_n__read0928__q37[31]) ?
|
|
addIdx__h55557 :
|
|
5'd0 ;
|
|
assign val__h5329 = m_tlb_m_lruBit_rl | x__h5387 ;
|
|
assign x__h5387 = 32'd1 << m_tlb_m_updRepIdx_rl[4:0] ;
|
|
assign x__h70301 = { 8'd0, x__h70310 } ;
|
|
assign x__h90425 = { 8'd0, x__h90434 } ;
|
|
assign x_id__h21371 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[1:0] :
|
|
m_ldTransRsFromPQ_enqReq_rl[1:0] ;
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0: level__h38292 = m_ldTransRsFromPQ_data_0[3:2];
|
|
1'd1: level__h38292 = m_ldTransRsFromPQ_data_1[3:2];
|
|
endcase
|
|
end
|
|
always@(m_freeQ_deqP or
|
|
m_freeQ_data_0 or
|
|
m_freeQ_data_1 or m_freeQ_data_2 or m_freeQ_data_3)
|
|
begin
|
|
case (m_freeQ_deqP)
|
|
2'd0: idx__h73608 = m_freeQ_data_0;
|
|
2'd1: idx__h73608 = m_freeQ_data_1;
|
|
2'd2: idx__h73608 = m_freeQ_data_2;
|
|
2'd3: idx__h73608 = m_freeQ_data_3;
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 =
|
|
m_ldTransRsFromPQ_data_0[82];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 =
|
|
m_ldTransRsFromPQ_data_1[82];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 =
|
|
m_ldTransRsFromPQ_data_0[1:0];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 =
|
|
m_ldTransRsFromPQ_data_1[1:0];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0: x__h70397 = m_pendInst_0[440:375];
|
|
2'd1: x__h70397 = m_pendInst_1[440:375];
|
|
2'd2: x__h70397 = m_pendInst_2[440:375];
|
|
2'd3: x__h70397 = m_pendInst_3[440:375];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 =
|
|
m_pendInst_0[478:476];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 =
|
|
m_pendInst_1[478:476];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 =
|
|
m_pendInst_2[478:476];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594 =
|
|
m_pendInst_3[478:476];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627 =
|
|
m_ldTransRsFromPQ_data_0[6];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627 =
|
|
m_ldTransRsFromPQ_data_1[6];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623 =
|
|
!m_ldTransRsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d623 =
|
|
!m_ldTransRsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653 =
|
|
m_ldTransRsFromPQ_data_0[54:11];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653 =
|
|
m_ldTransRsFromPQ_data_1[54:11];
|
|
endcase
|
|
end
|
|
always@(level__h38292 or
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653 or
|
|
x__h70397)
|
|
begin
|
|
case (level__h38292)
|
|
2'd0:
|
|
x__h70310 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653,
|
|
x__h70397[11:0] };
|
|
2'd1:
|
|
x__h70310 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[43:9],
|
|
x__h70397[20:0] };
|
|
2'd2:
|
|
x__h70310 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d653[43:18],
|
|
x__h70397[29:0] };
|
|
2'd3: x__h70310 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_65_m_ETC___d668 =
|
|
m_ldTransRsFromPQ_data_0[5];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_65_m_ETC___d668 =
|
|
m_ldTransRsFromPQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_34_m_ETC___d637 =
|
|
m_ldTransRsFromPQ_data_0[7];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_34_m_ETC___d637 =
|
|
m_ldTransRsFromPQ_data_1[7];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_18_m_ETC___d680 =
|
|
m_ldTransRsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_18_m_ETC___d680 =
|
|
m_ldTransRsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d612 =
|
|
!m_ldTransRsFromPQ_data_0[9];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d612 =
|
|
!m_ldTransRsFromPQ_data_1[9];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d605 =
|
|
!m_ldTransRsFromPQ_data_0[10];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d605 =
|
|
!m_ldTransRsFromPQ_data_1[10];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 =
|
|
m_ldTransRsFromPQ_data_0[81:55];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d703 =
|
|
m_ldTransRsFromPQ_data_1[81:55];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 =
|
|
m_ldTransRsFromPQ_data_0[8];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_11_m_ETC___d714 =
|
|
m_ldTransRsFromPQ_data_1[8];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendPoisoned_0 or
|
|
m_pendPoisoned_1 or m_pendPoisoned_2 or m_pendPoisoned_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 =
|
|
m_pendPoisoned_0;
|
|
2'd1:
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 =
|
|
m_pendPoisoned_1;
|
|
2'd2:
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 =
|
|
m_pendPoisoned_2;
|
|
2'd3:
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 =
|
|
m_pendPoisoned_3;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_1 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_1[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_0 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_0[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q2 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q2 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q2 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q2 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_2 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_2[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q3 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_3 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_3[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_4 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_4[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_5 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_5[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_6 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_6[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_7 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_7[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_8 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_8[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_9 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_9[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_10 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_10[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_11 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_11[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_12 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_12[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_13 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_13[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_14 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_14[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_15 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_15[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_16 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_16[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_17 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_17[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_18 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_18[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_19 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_19[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_20 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_20[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_21 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_21[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_22 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_22[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_23 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_23[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_24 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_24[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_25 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_25[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_26 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_26[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_27 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_27[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_28 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_28[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_29 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_29[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_30 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_30[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0: ppn__h90430 = m_tlb_m_entryVec_0[52:9];
|
|
5'd1: ppn__h90430 = m_tlb_m_entryVec_1[52:9];
|
|
5'd2: ppn__h90430 = m_tlb_m_entryVec_2[52:9];
|
|
5'd3: ppn__h90430 = m_tlb_m_entryVec_3[52:9];
|
|
5'd4: ppn__h90430 = m_tlb_m_entryVec_4[52:9];
|
|
5'd5: ppn__h90430 = m_tlb_m_entryVec_5[52:9];
|
|
5'd6: ppn__h90430 = m_tlb_m_entryVec_6[52:9];
|
|
5'd7: ppn__h90430 = m_tlb_m_entryVec_7[52:9];
|
|
5'd8: ppn__h90430 = m_tlb_m_entryVec_8[52:9];
|
|
5'd9: ppn__h90430 = m_tlb_m_entryVec_9[52:9];
|
|
5'd10: ppn__h90430 = m_tlb_m_entryVec_10[52:9];
|
|
5'd11: ppn__h90430 = m_tlb_m_entryVec_11[52:9];
|
|
5'd12: ppn__h90430 = m_tlb_m_entryVec_12[52:9];
|
|
5'd13: ppn__h90430 = m_tlb_m_entryVec_13[52:9];
|
|
5'd14: ppn__h90430 = m_tlb_m_entryVec_14[52:9];
|
|
5'd15: ppn__h90430 = m_tlb_m_entryVec_15[52:9];
|
|
5'd16: ppn__h90430 = m_tlb_m_entryVec_16[52:9];
|
|
5'd17: ppn__h90430 = m_tlb_m_entryVec_17[52:9];
|
|
5'd18: ppn__h90430 = m_tlb_m_entryVec_18[52:9];
|
|
5'd19: ppn__h90430 = m_tlb_m_entryVec_19[52:9];
|
|
5'd20: ppn__h90430 = m_tlb_m_entryVec_20[52:9];
|
|
5'd21: ppn__h90430 = m_tlb_m_entryVec_21[52:9];
|
|
5'd22: ppn__h90430 = m_tlb_m_entryVec_22[52:9];
|
|
5'd23: ppn__h90430 = m_tlb_m_entryVec_23[52:9];
|
|
5'd24: ppn__h90430 = m_tlb_m_entryVec_24[52:9];
|
|
5'd25: ppn__h90430 = m_tlb_m_entryVec_25[52:9];
|
|
5'd26: ppn__h90430 = m_tlb_m_entryVec_26[52:9];
|
|
5'd27: ppn__h90430 = m_tlb_m_entryVec_27[52:9];
|
|
5'd28: ppn__h90430 = m_tlb_m_entryVec_28[52:9];
|
|
5'd29: ppn__h90430 = m_tlb_m_entryVec_29[52:9];
|
|
5'd30: ppn__h90430 = m_tlb_m_entryVec_30[52:9];
|
|
5'd31: ppn__h90430 = m_tlb_m_entryVec_31[52:9];
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0: level__h85474 = m_tlb_m_entryVec_0[1:0];
|
|
5'd1: level__h85474 = m_tlb_m_entryVec_1[1:0];
|
|
5'd2: level__h85474 = m_tlb_m_entryVec_2[1:0];
|
|
5'd3: level__h85474 = m_tlb_m_entryVec_3[1:0];
|
|
5'd4: level__h85474 = m_tlb_m_entryVec_4[1:0];
|
|
5'd5: level__h85474 = m_tlb_m_entryVec_5[1:0];
|
|
5'd6: level__h85474 = m_tlb_m_entryVec_6[1:0];
|
|
5'd7: level__h85474 = m_tlb_m_entryVec_7[1:0];
|
|
5'd8: level__h85474 = m_tlb_m_entryVec_8[1:0];
|
|
5'd9: level__h85474 = m_tlb_m_entryVec_9[1:0];
|
|
5'd10: level__h85474 = m_tlb_m_entryVec_10[1:0];
|
|
5'd11: level__h85474 = m_tlb_m_entryVec_11[1:0];
|
|
5'd12: level__h85474 = m_tlb_m_entryVec_12[1:0];
|
|
5'd13: level__h85474 = m_tlb_m_entryVec_13[1:0];
|
|
5'd14: level__h85474 = m_tlb_m_entryVec_14[1:0];
|
|
5'd15: level__h85474 = m_tlb_m_entryVec_15[1:0];
|
|
5'd16: level__h85474 = m_tlb_m_entryVec_16[1:0];
|
|
5'd17: level__h85474 = m_tlb_m_entryVec_17[1:0];
|
|
5'd18: level__h85474 = m_tlb_m_entryVec_18[1:0];
|
|
5'd19: level__h85474 = m_tlb_m_entryVec_19[1:0];
|
|
5'd20: level__h85474 = m_tlb_m_entryVec_20[1:0];
|
|
5'd21: level__h85474 = m_tlb_m_entryVec_21[1:0];
|
|
5'd22: level__h85474 = m_tlb_m_entryVec_22[1:0];
|
|
5'd23: level__h85474 = m_tlb_m_entryVec_23[1:0];
|
|
5'd24: level__h85474 = m_tlb_m_entryVec_24[1:0];
|
|
5'd25: level__h85474 = m_tlb_m_entryVec_25[1:0];
|
|
5'd26: level__h85474 = m_tlb_m_entryVec_26[1:0];
|
|
5'd27: level__h85474 = m_tlb_m_entryVec_27[1:0];
|
|
5'd28: level__h85474 = m_tlb_m_entryVec_28[1:0];
|
|
5'd29: level__h85474 = m_tlb_m_entryVec_29[1:0];
|
|
5'd30: level__h85474 = m_tlb_m_entryVec_30[1:0];
|
|
5'd31: level__h85474 = m_tlb_m_entryVec_31[1:0];
|
|
endcase
|
|
end
|
|
always@(level__h85474 or ppn__h90430 or procReq_req)
|
|
begin
|
|
case (level__h85474)
|
|
2'd0: x__h90434 = { ppn__h90430, procReq_req[398:387] };
|
|
2'd1: x__h90434 = { ppn__h90430[43:9], procReq_req[407:387] };
|
|
2'd2: x__h90434 = { ppn__h90430[43:18], procReq_req[416:387] };
|
|
2'd3: x__h90434 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_0[8];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_1[8];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_2[8];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_3[8];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_4[8];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_5[8];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_6[8];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_7[8];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_8[8];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_9[8];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_10[8];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_11[8];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_12[8];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_13[8];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_14[8];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_15[8];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_16[8];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_17[8];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_18[8];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_19[8];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_20[8];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_21[8];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_22[8];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_23[8];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_24[8];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_25[8];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_26[8];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_27[8];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_28[8];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_29[8];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_30[8];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_8_256_25_ETC___d2352 =
|
|
!m_tlb_m_entryVec_31[8];
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_0[7];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_1[7];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_2[7];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_3[7];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_4[7];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_5[7];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_6[7];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_7[7];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_8[7];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_9[7];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_10[7];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_11[7];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_12[7];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_13[7];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_14[7];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_15[7];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_16[7];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_17[7];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_18[7];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_19[7];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_20[7];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_21[7];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_22[7];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_23[7];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_24[7];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_25[7];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_26[7];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_27[7];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_28[7];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_29[7];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_30[7];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_7_355_35_ETC___d2420 =
|
|
!m_tlb_m_entryVec_31[7];
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_98_BIT_2_422_42_ETC___d2487 =
|
|
!m_tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_0[4];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_1[4];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_2[4];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_3[4];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_4[4];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_5[4];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_6[4];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_7[4];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_8[4];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_9[4];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_10[4];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_11[4];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_12[4];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_13[4];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_14[4];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_15[4];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_16[4];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_17[4];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_18[4];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_19[4];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_20[4];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_21[4];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_22[4];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_23[4];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_24[4];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_25[4];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_26[4];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_27[4];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_28[4];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_29[4];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_30[4];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_4_489_m_tlb__ETC___d2522 =
|
|
m_tlb_m_entryVec_31[4];
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_31 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_31[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_0[3];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_1[3];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_2[3];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_3[3];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_4[3];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_5[3];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_6[3];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_7[3];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_8[3];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_9[3];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_10[3];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_11[3];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_12[3];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_13[3];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_14[3];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_15[3];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_16[3];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_17[3];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_18[3];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_19[3];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_20[3];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_21[3];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_22[3];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_23[3];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_24[3];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_25[3];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_26[3];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_27[3];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_28[3];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_29[3];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_30[3];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_3_608_m_tlb__ETC___d2641 =
|
|
m_tlb_m_entryVec_31[3];
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_0[5];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_1[5];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_2[5];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_3[5];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_4[5];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_5[5];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_6[5];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_7[5];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_8[5];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_9[5];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_10[5];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_11[5];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_12[5];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_13[5];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_14[5];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_15[5];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_16[5];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_17[5];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_18[5];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_19[5];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_20[5];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_21[5];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_22[5];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_23[5];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_24[5];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_25[5];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_26[5];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_27[5];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_28[5];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_29[5];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_30[5];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_5_525_m_tlb__ETC___d2558 =
|
|
m_tlb_m_entryVec_31[5];
|
|
endcase
|
|
end
|
|
always@(idx__h85435 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h85435)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_98_BIT_2_422_m_tlb__ETC___d2650 =
|
|
m_tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0: x__h92718 = m_pendResp_0[69:6];
|
|
2'd1: x__h92718 = m_pendResp_1[69:6];
|
|
2'd2: x__h92718 = m_pendResp_2[69:6];
|
|
2'd3: x__h92718 = m_pendResp_3[69:6];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0: x__h98052 = m_pendInst_0[316:303];
|
|
2'd1: x__h98052 = m_pendInst_1[316:303];
|
|
2'd2: x__h98052 = m_pendInst_2[316:303];
|
|
2'd3: x__h98052 = m_pendInst_3[316:303];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0: x__h98061 = m_pendInst_0[302:289];
|
|
2'd1: x__h98061 = m_pendInst_1[302:289];
|
|
2'd2: x__h98061 = m_pendInst_2[302:289];
|
|
2'd3: x__h98061 = m_pendInst_3[302:289];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0: x__h98552 = m_pendInst_0[264:201];
|
|
2'd1: x__h98552 = m_pendInst_1[264:201];
|
|
2'd2: x__h98552 = m_pendInst_2[264:201];
|
|
2'd3: x__h98552 = m_pendInst_3[264:201];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0: x__h98589 = m_pendInst_0[200:136];
|
|
2'd1: x__h98589 = m_pendInst_1[200:136];
|
|
2'd2: x__h98589 = m_pendInst_2[200:136];
|
|
2'd3: x__h98589 = m_pendInst_3[200:136];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0: x__h98607 = m_pendInst_0[129:66];
|
|
2'd1: x__h98607 = m_pendInst_1[129:66];
|
|
2'd2: x__h98607 = m_pendInst_2[129:66];
|
|
2'd3: x__h98607 = m_pendInst_3[129:66];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0: x__h98616 = m_pendInst_0[65:1];
|
|
2'd1: x__h98616 = m_pendInst_1[65:1];
|
|
2'd2: x__h98616 = m_pendInst_2[65:1];
|
|
2'd3: x__h98616 = m_pendInst_3[65:1];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendResp_0_777_BIT_5_795_796_NOT_ETC___d2804 =
|
|
!m_pendResp_0[5];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendResp_0_777_BIT_5_795_796_NOT_ETC___d2804 =
|
|
!m_pendResp_1[5];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendResp_0_777_BIT_5_795_796_NOT_ETC___d2804 =
|
|
!m_pendResp_2[5];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendResp_0_777_BIT_5_795_796_NOT_ETC___d2804 =
|
|
!m_pendResp_3[5];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_475_815_m_pendInst_ETC___d2820 =
|
|
m_pendInst_0[475];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_475_815_m_pendInst_ETC___d2820 =
|
|
m_pendInst_1[475];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_475_815_m_pendInst_ETC___d2820 =
|
|
m_pendInst_2[475];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_475_815_m_pendInst_ETC___d2820 =
|
|
m_pendInst_3[475];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_835_NO_ETC___d2843 =
|
|
!m_pendInst_0[463];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_835_NO_ETC___d2843 =
|
|
!m_pendInst_1[463];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_835_NO_ETC___d2843 =
|
|
!m_pendInst_2[463];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_463_834_835_NO_ETC___d2843 =
|
|
!m_pendInst_3[463];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_457_859_m_pendInst_ETC___d2864 =
|
|
m_pendInst_0[457];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_457_859_m_pendInst_ETC___d2864 =
|
|
m_pendInst_1[457];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_457_859_m_pendInst_ETC___d2864 =
|
|
m_pendInst_2[457];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_457_859_m_pendInst_ETC___d2864 =
|
|
m_pendInst_3[457];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_347_036_m_pendInst_ETC___d3041 =
|
|
m_pendInst_0[347];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_347_036_m_pendInst_ETC___d3041 =
|
|
m_pendInst_1[347];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_347_036_m_pendInst_ETC___d3041 =
|
|
m_pendInst_2[347];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_347_036_m_pendInst_ETC___d3041 =
|
|
m_pendInst_3[347];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_353_000_m_pendInst_ETC___d3005 =
|
|
m_pendInst_0[353];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_353_000_m_pendInst_ETC___d3005 =
|
|
m_pendInst_1[353];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_353_000_m_pendInst_ETC___d3005 =
|
|
m_pendInst_2[353];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_353_000_m_pendInst_ETC___d3005 =
|
|
m_pendInst_3[353];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_282_TO_281_131_m__ETC___d3136 =
|
|
m_pendInst_0[282:281];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_282_TO_281_131_m__ETC___d3136 =
|
|
m_pendInst_1[282:281];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_282_TO_281_131_m__ETC___d3136 =
|
|
m_pendInst_2[282:281];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_282_TO_281_131_m__ETC___d3136 =
|
|
m_pendInst_3[282:281];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_456_865_m_pendInst_ETC___d2870 =
|
|
m_pendInst_0[456];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_456_865_m_pendInst_ETC___d2870 =
|
|
m_pendInst_1[456];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_456_865_m_pendInst_ETC___d2870 =
|
|
m_pendInst_2[456];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_456_865_m_pendInst_ETC___d2870 =
|
|
m_pendInst_3[456];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_284_119_m_pendInst_ETC___d3124 =
|
|
m_pendInst_0[284];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_284_119_m_pendInst_ETC___d3124 =
|
|
m_pendInst_1[284];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_284_119_m_pendInst_ETC___d3124 =
|
|
m_pendInst_2[284];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_284_119_m_pendInst_ETC___d3124 =
|
|
m_pendInst_3[284];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_277_152_153_NO_ETC___d3161 =
|
|
!m_pendInst_0[277];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_277_152_153_NO_ETC___d3161 =
|
|
!m_pendInst_1[277];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_277_152_153_NO_ETC___d3161 =
|
|
!m_pendInst_2[277];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_277_152_153_NO_ETC___d3161 =
|
|
!m_pendInst_3[277];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_265_177_178_NO_ETC___d3186 =
|
|
!m_pendInst_0[265];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_265_177_178_NO_ETC___d3186 =
|
|
!m_pendInst_1[265];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_265_177_178_NO_ETC___d3186 =
|
|
!m_pendInst_2[265];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_85_BIT_265_177_178_NO_ETC___d3186 =
|
|
!m_pendInst_3[265];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q33 =
|
|
m_ldTransRsFromPQ_data_0[9];
|
|
1'd1:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q33 =
|
|
m_ldTransRsFromPQ_data_1[9];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q34 =
|
|
m_ldTransRsFromPQ_data_0[10];
|
|
1'd1:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q34 =
|
|
m_ldTransRsFromPQ_data_1[10];
|
|
endcase
|
|
end
|
|
always@(SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594)
|
|
begin
|
|
case (SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d594)
|
|
3'd1, 3'd3, 3'd4:
|
|
CASE_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_8_ETC__q35 = 5'd15;
|
|
default: CASE_SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_8_ETC__q35 =
|
|
5'd13;
|
|
endcase
|
|
end
|
|
always@(procReq_req)
|
|
begin
|
|
case (procReq_req[490:488])
|
|
3'd1, 3'd3, 3'd4:
|
|
CASE_procReq_req_BITS_490_TO_488_1_15_3_15_4_1_ETC__q36 = 5'd15;
|
|
default: CASE_procReq_req_BITS_490_TO_488_1_15_3_15_4_1_ETC__q36 =
|
|
5'd13;
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_346_042_m_pendInst_ETC___d3047 =
|
|
m_pendInst_0[346];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_346_042_m_pendInst_ETC___d3047 =
|
|
m_pendInst_1[346];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_346_042_m_pendInst_ETC___d3047 =
|
|
m_pendInst_2[346];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_346_042_m_pendInst_ETC___d3047 =
|
|
m_pendInst_3[346];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_280_TO_279_137_m__ETC___d3142 =
|
|
m_pendInst_0[280:279];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_280_TO_279_137_m__ETC___d3142 =
|
|
m_pendInst_1[280:279];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_280_TO_279_137_m__ETC___d3142 =
|
|
m_pendInst_2[280:279];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_280_TO_279_137_m__ETC___d3142 =
|
|
m_pendInst_3[280:279];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_345_048_m_pendInst_ETC___d3053 =
|
|
m_pendInst_0[345];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_345_048_m_pendInst_ETC___d3053 =
|
|
m_pendInst_1[345];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_345_048_m_pendInst_ETC___d3053 =
|
|
m_pendInst_2[345];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_345_048_m_pendInst_ETC___d3053 =
|
|
m_pendInst_3[345];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_455_872_m_pendInst_ETC___d2877 =
|
|
m_pendInst_0[455];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_455_872_m_pendInst_ETC___d2877 =
|
|
m_pendInst_1[455];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_455_872_m_pendInst_ETC___d2877 =
|
|
m_pendInst_2[455];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_455_872_m_pendInst_ETC___d2877 =
|
|
m_pendInst_3[455];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_454_878_m_pendInst_ETC___d2883 =
|
|
m_pendInst_0[454];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_454_878_m_pendInst_ETC___d2883 =
|
|
m_pendInst_1[454];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_454_878_m_pendInst_ETC___d2883 =
|
|
m_pendInst_2[454];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_454_878_m_pendInst_ETC___d2883 =
|
|
m_pendInst_3[454];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_348_030_m_pendInst_ETC___d3035 =
|
|
m_pendInst_0[348];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_348_030_m_pendInst_ETC___d3035 =
|
|
m_pendInst_1[348];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_348_030_m_pendInst_ETC___d3035 =
|
|
m_pendInst_2[348];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_348_030_m_pendInst_ETC___d3035 =
|
|
m_pendInst_3[348];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_349_024_m_pendInst_ETC___d3029 =
|
|
m_pendInst_0[349];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_349_024_m_pendInst_ETC___d3029 =
|
|
m_pendInst_1[349];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_349_024_m_pendInst_ETC___d3029 =
|
|
m_pendInst_2[349];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_349_024_m_pendInst_ETC___d3029 =
|
|
m_pendInst_3[349];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_461_TO_458_851_m__ETC___d2856 =
|
|
m_pendInst_0[461:458];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_461_TO_458_851_m__ETC___d2856 =
|
|
m_pendInst_1[461:458];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_461_TO_458_851_m__ETC___d2856 =
|
|
m_pendInst_2[461:458];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_461_TO_458_851_m__ETC___d2856 =
|
|
m_pendInst_3[461:458];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_777_BITS_4_TO_0_806_m_pen_ETC___d2811 =
|
|
m_pendResp_0[4:0];
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_777_BITS_4_TO_0_806_m_pen_ETC___d2811 =
|
|
m_pendResp_1[4:0];
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_777_BITS_4_TO_0_806_m_pen_ETC___d2811 =
|
|
m_pendResp_2[4:0];
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_777_BITS_4_TO_0_806_m_pen_ETC___d2811 =
|
|
m_pendResp_3[4:0];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_283_125_m_pendInst_ETC___d3130 =
|
|
m_pendInst_0[283];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_283_125_m_pendInst_ETC___d3130 =
|
|
m_pendInst_1[283];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_283_125_m_pendInst_ETC___d3130 =
|
|
m_pendInst_2[283];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_283_125_m_pendInst_ETC___d3130 =
|
|
m_pendInst_3[283];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_453_885_m_pendInst_ETC___d2890 =
|
|
m_pendInst_0[453];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_453_885_m_pendInst_ETC___d2890 =
|
|
m_pendInst_1[453];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_453_885_m_pendInst_ETC___d2890 =
|
|
m_pendInst_2[453];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_453_885_m_pendInst_ETC___d2890 =
|
|
m_pendInst_3[453];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_452_891_m_pendInst_ETC___d2896 =
|
|
m_pendInst_0[452];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_452_891_m_pendInst_ETC___d2896 =
|
|
m_pendInst_1[452];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_452_891_m_pendInst_ETC___d2896 =
|
|
m_pendInst_2[452];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_452_891_m_pendInst_ETC___d2896 =
|
|
m_pendInst_3[452];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_351_012_m_pendInst_ETC___d3017 =
|
|
m_pendInst_0[351];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_351_012_m_pendInst_ETC___d3017 =
|
|
m_pendInst_1[351];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_351_012_m_pendInst_ETC___d3017 =
|
|
m_pendInst_2[351];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_351_012_m_pendInst_ETC___d3017 =
|
|
m_pendInst_3[351];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_350_018_m_pendInst_ETC___d3023 =
|
|
m_pendInst_0[350];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_350_018_m_pendInst_ETC___d3023 =
|
|
m_pendInst_1[350];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_350_018_m_pendInst_ETC___d3023 =
|
|
m_pendInst_2[350];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_350_018_m_pendInst_ETC___d3023 =
|
|
m_pendInst_3[350];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_451_898_m_pendInst_ETC___d2903 =
|
|
m_pendInst_0[451];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_451_898_m_pendInst_ETC___d2903 =
|
|
m_pendInst_1[451];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_451_898_m_pendInst_ETC___d2903 =
|
|
m_pendInst_2[451];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_451_898_m_pendInst_ETC___d2903 =
|
|
m_pendInst_3[451];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_352_006_m_pendInst_ETC___d3011 =
|
|
m_pendInst_0[352];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_352_006_m_pendInst_ETC___d3011 =
|
|
m_pendInst_1[352];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_352_006_m_pendInst_ETC___d3011 =
|
|
m_pendInst_2[352];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_352_006_m_pendInst_ETC___d3011 =
|
|
m_pendInst_3[352];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_450_904_m_pendInst_ETC___d2909 =
|
|
m_pendInst_0[450];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_450_904_m_pendInst_ETC___d2909 =
|
|
m_pendInst_1[450];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_450_904_m_pendInst_ETC___d2909 =
|
|
m_pendInst_2[450];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_450_904_m_pendInst_ETC___d2909 =
|
|
m_pendInst_3[450];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_288_TO_286_107_m__ETC___d3112 =
|
|
m_pendInst_0[288:286];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_288_TO_286_107_m__ETC___d3112 =
|
|
m_pendInst_1[288:286];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_288_TO_286_107_m__ETC___d3112 =
|
|
m_pendInst_2[288:286];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_288_TO_286_107_m__ETC___d3112 =
|
|
m_pendInst_3[288:286];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_285_113_m_pendInst_ETC___d3118 =
|
|
m_pendInst_0[285];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_285_113_m_pendInst_ETC___d3118 =
|
|
m_pendInst_1[285];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_285_113_m_pendInst_ETC___d3118 =
|
|
m_pendInst_2[285];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_285_113_m_pendInst_ETC___d3118 =
|
|
m_pendInst_3[285];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_449_911_m_pendInst_ETC___d2916 =
|
|
m_pendInst_0[449];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_449_911_m_pendInst_ETC___d2916 =
|
|
m_pendInst_1[449];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_449_911_m_pendInst_ETC___d2916 =
|
|
m_pendInst_2[449];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_449_911_m_pendInst_ETC___d2916 =
|
|
m_pendInst_3[449];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_448_917_m_pendInst_ETC___d2922 =
|
|
m_pendInst_0[448];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_448_917_m_pendInst_ETC___d2922 =
|
|
m_pendInst_1[448];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_448_917_m_pendInst_ETC___d2922 =
|
|
m_pendInst_2[448];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_448_917_m_pendInst_ETC___d2922 =
|
|
m_pendInst_3[448];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_355_988_m_pendInst_ETC___d2993 =
|
|
m_pendInst_0[355];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_355_988_m_pendInst_ETC___d2993 =
|
|
m_pendInst_1[355];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_355_988_m_pendInst_ETC___d2993 =
|
|
m_pendInst_2[355];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_355_988_m_pendInst_ETC___d2993 =
|
|
m_pendInst_3[355];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_354_994_m_pendInst_ETC___d2999 =
|
|
m_pendInst_0[354];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_354_994_m_pendInst_ETC___d2999 =
|
|
m_pendInst_1[354];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_354_994_m_pendInst_ETC___d2999 =
|
|
m_pendInst_2[354];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_354_994_m_pendInst_ETC___d2999 =
|
|
m_pendInst_3[354];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_276_TO_271_163_m__ETC___d3168 =
|
|
m_pendInst_0[276:271];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_276_TO_271_163_m__ETC___d3168 =
|
|
m_pendInst_1[276:271];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_276_TO_271_163_m__ETC___d3168 =
|
|
m_pendInst_2[276:271];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_276_TO_271_163_m__ETC___d3168 =
|
|
m_pendInst_3[276:271];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_270_TO_266_169_m__ETC___d3174 =
|
|
m_pendInst_0[270:266];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_270_TO_266_169_m__ETC___d3174 =
|
|
m_pendInst_1[270:266];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_270_TO_266_169_m__ETC___d3174 =
|
|
m_pendInst_2[270:266];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_270_TO_266_169_m__ETC___d3174 =
|
|
m_pendInst_3[270:266];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_474_TO_470_821_m__ETC___d2826 =
|
|
m_pendInst_0[474:470];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_474_TO_470_821_m__ETC___d2826 =
|
|
m_pendInst_1[474:470];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_474_TO_470_821_m__ETC___d2826 =
|
|
m_pendInst_2[474:470];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_474_TO_470_821_m__ETC___d2826 =
|
|
m_pendInst_3[474:470];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_447_924_m_pendInst_ETC___d2929 =
|
|
m_pendInst_0[447];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_447_924_m_pendInst_ETC___d2929 =
|
|
m_pendInst_1[447];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_447_924_m_pendInst_ETC___d2929 =
|
|
m_pendInst_2[447];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_447_924_m_pendInst_ETC___d2929 =
|
|
m_pendInst_3[447];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_469_TO_464_827_m__ETC___d2832 =
|
|
m_pendInst_0[469:464];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_469_TO_464_827_m__ETC___d2832 =
|
|
m_pendInst_1[469:464];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_469_TO_464_827_m__ETC___d2832 =
|
|
m_pendInst_2[469:464];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_469_TO_464_827_m__ETC___d2832 =
|
|
m_pendInst_3[469:464];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_446_930_m_pendInst_ETC___d2935 =
|
|
m_pendInst_0[446];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_446_930_m_pendInst_ETC___d2935 =
|
|
m_pendInst_1[446];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_446_930_m_pendInst_ETC___d2935 =
|
|
m_pendInst_2[446];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_446_930_m_pendInst_ETC___d2935 =
|
|
m_pendInst_3[446];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_445_937_m_pendInst_ETC___d2942 =
|
|
m_pendInst_0[445];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_445_937_m_pendInst_ETC___d2942 =
|
|
m_pendInst_1[445];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_445_937_m_pendInst_ETC___d2942 =
|
|
m_pendInst_2[445];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_445_937_m_pendInst_ETC___d2942 =
|
|
m_pendInst_3[445];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_444_943_m_pendInst_ETC___d2948 =
|
|
m_pendInst_0[444];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_444_943_m_pendInst_ETC___d2948 =
|
|
m_pendInst_1[444];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_444_943_m_pendInst_ETC___d2948 =
|
|
m_pendInst_2[444];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_444_943_m_pendInst_ETC___d2948 =
|
|
m_pendInst_3[444];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_356_982_m_pendInst_ETC___d2987 =
|
|
m_pendInst_0[356];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_356_982_m_pendInst_ETC___d2987 =
|
|
m_pendInst_1[356];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_356_982_m_pendInst_ETC___d2987 =
|
|
m_pendInst_2[356];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_356_982_m_pendInst_ETC___d2987 =
|
|
m_pendInst_3[356];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_360_TO_357_976_m__ETC___d2981 =
|
|
m_pendInst_0[360:357];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_360_TO_357_976_m__ETC___d2981 =
|
|
m_pendInst_1[360:357];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_360_TO_357_976_m__ETC___d2981 =
|
|
m_pendInst_2[360:357];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_360_TO_357_976_m__ETC___d2981 =
|
|
m_pendInst_3[360:357];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_443_950_m_pendInst_ETC___d2955 =
|
|
m_pendInst_0[443];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_443_950_m_pendInst_ETC___d2955 =
|
|
m_pendInst_1[443];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_443_950_m_pendInst_ETC___d2955 =
|
|
m_pendInst_2[443];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_443_950_m_pendInst_ETC___d2955 =
|
|
m_pendInst_3[443];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_442_956_m_pendInst_ETC___d2961 =
|
|
m_pendInst_0[442];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_442_956_m_pendInst_ETC___d2961 =
|
|
m_pendInst_1[442];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_442_956_m_pendInst_ETC___d2961 =
|
|
m_pendInst_2[442];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_442_956_m_pendInst_ETC___d2961 =
|
|
m_pendInst_3[442];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_322_TO_317_084_m__ETC___d3089 =
|
|
m_pendInst_0[322:317];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_322_TO_317_084_m__ETC___d3089 =
|
|
m_pendInst_1[322:317];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_322_TO_317_084_m__ETC___d3089 =
|
|
m_pendInst_2[322:317];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_322_TO_317_084_m__ETC___d3089 =
|
|
m_pendInst_3[322:317];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_341_TO_324_072_m__ETC___d3077 =
|
|
m_pendInst_0[341:324];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_341_TO_324_072_m__ETC___d3077 =
|
|
m_pendInst_1[341:324];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_341_TO_324_072_m__ETC___d3077 =
|
|
m_pendInst_2[341:324];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_341_TO_324_072_m__ETC___d3077 =
|
|
m_pendInst_3[341:324];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_344_060_m_pendInst_ETC___d3065 =
|
|
m_pendInst_0[344];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_344_060_m_pendInst_ETC___d3065 =
|
|
m_pendInst_1[344];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_344_060_m_pendInst_ETC___d3065 =
|
|
m_pendInst_2[344];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_344_060_m_pendInst_ETC___d3065 =
|
|
m_pendInst_3[344];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_323_078_m_pendInst_ETC___d3083 =
|
|
m_pendInst_0[323];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_323_078_m_pendInst_ETC___d3083 =
|
|
m_pendInst_1[323];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_323_078_m_pendInst_ETC___d3083 =
|
|
m_pendInst_2[323];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_323_078_m_pendInst_ETC___d3083 =
|
|
m_pendInst_3[323];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_343_TO_342_066_m__ETC___d3071 =
|
|
m_pendInst_0[343:342];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_343_TO_342_066_m__ETC___d3071 =
|
|
m_pendInst_1[343:342];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_343_TO_342_066_m__ETC___d3071 =
|
|
m_pendInst_2[343:342];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_343_TO_342_066_m__ETC___d3071 =
|
|
m_pendInst_3[343:342];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_0_218_m_pendInst_1_ETC___d3223 =
|
|
m_pendInst_0[0];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_0_218_m_pendInst_1_ETC___d3223 =
|
|
m_pendInst_1[0];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_0_218_m_pendInst_1_ETC___d3223 =
|
|
m_pendInst_2[0];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_0_218_m_pendInst_1_ETC___d3223 =
|
|
m_pendInst_3[0];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_374_TO_361_970_m__ETC___d2975 =
|
|
m_pendInst_0[374:361];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_374_TO_361_970_m__ETC___d2975 =
|
|
m_pendInst_1[374:361];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_374_TO_361_970_m__ETC___d2975 =
|
|
m_pendInst_2[374:361];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_374_TO_361_970_m__ETC___d2975 =
|
|
m_pendInst_3[374:361];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_135_TO_130_200_m__ETC___d3205 =
|
|
m_pendInst_0[135:130];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_135_TO_130_200_m__ETC___d3205 =
|
|
m_pendInst_1[135:130];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_135_TO_130_200_m__ETC___d3205 =
|
|
m_pendInst_2[135:130];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_135_TO_130_200_m__ETC___d3205 =
|
|
m_pendInst_3[135:130];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_441_963_m_pendInst_ETC___d2968 =
|
|
m_pendInst_0[441];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_441_963_m_pendInst_ETC___d2968 =
|
|
m_pendInst_1[441];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_441_963_m_pendInst_ETC___d2968 =
|
|
m_pendInst_2[441];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_441_963_m_pendInst_ETC___d2968 =
|
|
m_pendInst_3[441];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_440_TO_375_739_m__ETC___d2969 =
|
|
m_pendInst_0[440:375];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_440_TO_375_739_m__ETC___d2969 =
|
|
m_pendInst_1[440:375];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_440_TO_375_739_m__ETC___d2969 =
|
|
m_pendInst_2[440:375];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_440_TO_375_739_m__ETC___d2969 =
|
|
m_pendInst_3[440:375];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BIT_278_146_m_pendInst_ETC___d3151 =
|
|
m_pendInst_0[278];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BIT_278_146_m_pendInst_ETC___d3151 =
|
|
m_pendInst_1[278];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BIT_278_146_m_pendInst_ETC___d3151 =
|
|
m_pendInst_2[278];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BIT_278_146_m_pendInst_ETC___d3151 =
|
|
m_pendInst_3[278];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_462_TO_458_845_m__ETC___d2850 =
|
|
m_pendInst_0[462:458];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_462_TO_458_845_m__ETC___d2850 =
|
|
m_pendInst_1[462:458];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_462_TO_458_845_m__ETC___d2850 =
|
|
m_pendInst_2[462:458];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_462_TO_458_845_m__ETC___d2850 =
|
|
m_pendInst_3[462:458];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d2814 =
|
|
m_pendInst_0[478:476];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d2814 =
|
|
m_pendInst_1[478:476];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d2814 =
|
|
m_pendInst_2[478:476];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_85_BITS_478_TO_476_86_m_p_ETC___d2814 =
|
|
m_pendInst_3[478:476];
|
|
endcase
|
|
end
|
|
always@(idx__h93065 or
|
|
m_pendSpecBits_0_rl or
|
|
m_pendSpecBits_1_rl or m_pendSpecBits_2_rl or m_pendSpecBits_3_rl)
|
|
begin
|
|
case (idx__h93065)
|
|
2'd0:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3233 =
|
|
m_pendSpecBits_0_rl;
|
|
2'd1:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3233 =
|
|
m_pendSpecBits_1_rl;
|
|
2'd2:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3233 =
|
|
m_pendSpecBits_2_rl;
|
|
2'd3:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3233 =
|
|
m_pendSpecBits_3_rl;
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or
|
|
m_rqToPQ_data_0 or
|
|
m_rqToPQ_data_1 or m_rqToPQ_data_2 or m_rqToPQ_data_3)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_28_TO_2_249_m_ETC___d3257 =
|
|
m_rqToPQ_data_0[28:2];
|
|
2'd1:
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_28_TO_2_249_m_ETC___d3257 =
|
|
m_rqToPQ_data_1[28:2];
|
|
2'd2:
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_28_TO_2_249_m_ETC___d3257 =
|
|
m_rqToPQ_data_2[28:2];
|
|
2'd3:
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_28_TO_2_249_m_ETC___d3257 =
|
|
m_rqToPQ_data_3[28:2];
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or
|
|
m_rqToPQ_data_0 or
|
|
m_rqToPQ_data_1 or m_rqToPQ_data_2 or m_rqToPQ_data_3)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_1_TO_0_258_m__ETC___d3263 =
|
|
m_rqToPQ_data_0[1:0];
|
|
2'd1:
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_1_TO_0_258_m__ETC___d3263 =
|
|
m_rqToPQ_data_1[1:0];
|
|
2'd2:
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_1_TO_0_258_m__ETC___d3263 =
|
|
m_rqToPQ_data_2[1:0];
|
|
2'd3:
|
|
SEL_ARR_m_rqToPQ_data_0_248_BITS_1_TO_0_258_m__ETC___d3263 =
|
|
m_rqToPQ_data_3[1:0];
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_randIdx or INV_n__read0928__q37)
|
|
begin
|
|
case (m_tlb_m_randIdx)
|
|
5'd0:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[0];
|
|
5'd1:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[1];
|
|
5'd2:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[2];
|
|
5'd3:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[3];
|
|
5'd4:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[4];
|
|
5'd5:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[5];
|
|
5'd6:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[6];
|
|
5'd7:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[7];
|
|
5'd8:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[8];
|
|
5'd9:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[9];
|
|
5'd10:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[10];
|
|
5'd11:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[11];
|
|
5'd12:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[12];
|
|
5'd13:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[13];
|
|
5'd14:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[14];
|
|
5'd15:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[15];
|
|
5'd16:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[16];
|
|
5'd17:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[17];
|
|
5'd18:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[18];
|
|
5'd19:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[19];
|
|
5'd20:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[20];
|
|
5'd21:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[21];
|
|
5'd22:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[22];
|
|
5'd23:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[23];
|
|
5'd24:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[24];
|
|
5'd25:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[25];
|
|
5'd26:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[26];
|
|
5'd27:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[27];
|
|
5'd28:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[28];
|
|
5'd29:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[29];
|
|
5'd30:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[30];
|
|
5'd31:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09287_BIT_0__ETC__q38 =
|
|
INV_n__read0928__q37[31];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQInitIdx <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQInited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_data_0 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_2 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_3 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_freeQ_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 2'bxx /* unspecified value */ };
|
|
m_freeQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
80'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
2'd0 };
|
|
m_ldTransRsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
80'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
2'd0 };
|
|
m_ldTransRsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_ldTransRsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
83'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_ldTransRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_needFlush <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendSpecBits_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_pendSpecBits_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_pendSpecBits_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_pendSpecBits_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendWait_0 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 2'd0, 2'bxx /* unspecified value */ };
|
|
m_pendWait_1 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 2'd0, 2'bxx /* unspecified value */ };
|
|
m_pendWait_2 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 2'd0, 2'bxx /* unspecified value */ };
|
|
m_pendWait_3 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 2'd0, 2'bxx /* unspecified value */ };
|
|
m_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 3'bxxx /* unspecified value */ };
|
|
m_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_respForOtherReq <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 2'bxx /* unspecified value */ };
|
|
m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_2 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_3 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
29'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 32'd0;
|
|
m_tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY 5'd0;
|
|
m_tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 5'bxxxxx /* unspecified value */ };
|
|
m_tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_vm_info <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
m_waitFlushP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_flushRqToPQ_clearReq_rl$EN)
|
|
m_flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_clearReq_rl$D_IN;
|
|
if (m_flushRqToPQ_deqReq_rl$EN)
|
|
m_flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_deqReq_rl$D_IN;
|
|
if (m_flushRqToPQ_empty$EN)
|
|
m_flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_empty$D_IN;
|
|
if (m_flushRqToPQ_enqReq_rl$EN)
|
|
m_flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_enqReq_rl$D_IN;
|
|
if (m_flushRqToPQ_full$EN)
|
|
m_flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY m_flushRqToPQ_full$D_IN;
|
|
if (m_flushRsFromPQ_clearReq_rl$EN)
|
|
m_flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_clearReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_deqReq_rl$EN)
|
|
m_flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_deqReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_empty$EN)
|
|
m_flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_empty$D_IN;
|
|
if (m_flushRsFromPQ_enqReq_rl$EN)
|
|
m_flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_enqReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_full$EN)
|
|
m_flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_full$D_IN;
|
|
if (m_freeQInitIdx$EN)
|
|
m_freeQInitIdx <= `BSV_ASSIGNMENT_DELAY m_freeQInitIdx$D_IN;
|
|
if (m_freeQInited$EN)
|
|
m_freeQInited <= `BSV_ASSIGNMENT_DELAY m_freeQInited$D_IN;
|
|
if (m_freeQ_clearReq_rl$EN)
|
|
m_freeQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_freeQ_clearReq_rl$D_IN;
|
|
if (m_freeQ_data_0$EN)
|
|
m_freeQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_0$D_IN;
|
|
if (m_freeQ_data_1$EN)
|
|
m_freeQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_1$D_IN;
|
|
if (m_freeQ_data_2$EN)
|
|
m_freeQ_data_2 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_2$D_IN;
|
|
if (m_freeQ_data_3$EN)
|
|
m_freeQ_data_3 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_3$D_IN;
|
|
if (m_freeQ_deqP$EN)
|
|
m_freeQ_deqP <= `BSV_ASSIGNMENT_DELAY m_freeQ_deqP$D_IN;
|
|
if (m_freeQ_deqReq_rl$EN)
|
|
m_freeQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_freeQ_deqReq_rl$D_IN;
|
|
if (m_freeQ_empty$EN)
|
|
m_freeQ_empty <= `BSV_ASSIGNMENT_DELAY m_freeQ_empty$D_IN;
|
|
if (m_freeQ_enqP$EN)
|
|
m_freeQ_enqP <= `BSV_ASSIGNMENT_DELAY m_freeQ_enqP$D_IN;
|
|
if (m_freeQ_enqReq_rl$EN)
|
|
m_freeQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_freeQ_enqReq_rl$D_IN;
|
|
if (m_freeQ_full$EN)
|
|
m_freeQ_full <= `BSV_ASSIGNMENT_DELAY m_freeQ_full$D_IN;
|
|
if (m_ldTransRsFromPQ_clearReq_rl$EN)
|
|
m_ldTransRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_clearReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_data_0$EN)
|
|
m_ldTransRsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_data_0$D_IN;
|
|
if (m_ldTransRsFromPQ_data_1$EN)
|
|
m_ldTransRsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_data_1$D_IN;
|
|
if (m_ldTransRsFromPQ_deqP$EN)
|
|
m_ldTransRsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_deqP$D_IN;
|
|
if (m_ldTransRsFromPQ_deqReq_rl$EN)
|
|
m_ldTransRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_deqReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_empty$EN)
|
|
m_ldTransRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_empty$D_IN;
|
|
if (m_ldTransRsFromPQ_enqP$EN)
|
|
m_ldTransRsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_enqP$D_IN;
|
|
if (m_ldTransRsFromPQ_enqReq_rl$EN)
|
|
m_ldTransRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_enqReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_full$EN)
|
|
m_ldTransRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_full$D_IN;
|
|
if (m_needFlush$EN)
|
|
m_needFlush <= `BSV_ASSIGNMENT_DELAY m_needFlush$D_IN;
|
|
if (m_pendSpecBits_0_rl$EN)
|
|
m_pendSpecBits_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_0_rl$D_IN;
|
|
if (m_pendSpecBits_1_rl$EN)
|
|
m_pendSpecBits_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_1_rl$D_IN;
|
|
if (m_pendSpecBits_2_rl$EN)
|
|
m_pendSpecBits_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_2_rl$D_IN;
|
|
if (m_pendSpecBits_3_rl$EN)
|
|
m_pendSpecBits_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_3_rl$D_IN;
|
|
if (m_pendValid_0_rl$EN)
|
|
m_pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_0_rl$D_IN;
|
|
if (m_pendValid_1_rl$EN)
|
|
m_pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_1_rl$D_IN;
|
|
if (m_pendValid_2_rl$EN)
|
|
m_pendValid_2_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_2_rl$D_IN;
|
|
if (m_pendValid_3_rl$EN)
|
|
m_pendValid_3_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_3_rl$D_IN;
|
|
if (m_pendWait_0$EN)
|
|
m_pendWait_0 <= `BSV_ASSIGNMENT_DELAY m_pendWait_0$D_IN;
|
|
if (m_pendWait_1$EN)
|
|
m_pendWait_1 <= `BSV_ASSIGNMENT_DELAY m_pendWait_1$D_IN;
|
|
if (m_pendWait_2$EN)
|
|
m_pendWait_2 <= `BSV_ASSIGNMENT_DELAY m_pendWait_2$D_IN;
|
|
if (m_pendWait_3$EN)
|
|
m_pendWait_3 <= `BSV_ASSIGNMENT_DELAY m_pendWait_3$D_IN;
|
|
if (m_perfReqQ_clearReq_rl$EN)
|
|
m_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_clearReq_rl$D_IN;
|
|
if (m_perfReqQ_data_0$EN)
|
|
m_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_data_0$D_IN;
|
|
if (m_perfReqQ_deqReq_rl$EN)
|
|
m_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_deqReq_rl$D_IN;
|
|
if (m_perfReqQ_empty$EN)
|
|
m_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_empty$D_IN;
|
|
if (m_perfReqQ_enqReq_rl$EN)
|
|
m_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_enqReq_rl$D_IN;
|
|
if (m_perfReqQ_full$EN)
|
|
m_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_full$D_IN;
|
|
if (m_respForOtherReq$EN)
|
|
m_respForOtherReq <= `BSV_ASSIGNMENT_DELAY m_respForOtherReq$D_IN;
|
|
if (m_rqToPQ_clearReq_rl$EN)
|
|
m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rqToPQ_clearReq_rl$D_IN;
|
|
if (m_rqToPQ_data_0$EN)
|
|
m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_0$D_IN;
|
|
if (m_rqToPQ_data_1$EN)
|
|
m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_1$D_IN;
|
|
if (m_rqToPQ_data_2$EN)
|
|
m_rqToPQ_data_2 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_2$D_IN;
|
|
if (m_rqToPQ_data_3$EN)
|
|
m_rqToPQ_data_3 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_3$D_IN;
|
|
if (m_rqToPQ_deqP$EN)
|
|
m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqP$D_IN;
|
|
if (m_rqToPQ_deqReq_rl$EN)
|
|
m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqReq_rl$D_IN;
|
|
if (m_rqToPQ_empty$EN)
|
|
m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_empty$D_IN;
|
|
if (m_rqToPQ_enqP$EN)
|
|
m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqP$D_IN;
|
|
if (m_rqToPQ_enqReq_rl$EN)
|
|
m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqReq_rl$D_IN;
|
|
if (m_rqToPQ_full$EN)
|
|
m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_full$D_IN;
|
|
if (m_tlb_m_lruBit_rl$EN)
|
|
m_tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY m_tlb_m_lruBit_rl$D_IN;
|
|
if (m_tlb_m_randIdx$EN)
|
|
m_tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY m_tlb_m_randIdx$D_IN;
|
|
if (m_tlb_m_updRepIdx_rl$EN)
|
|
m_tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_updRepIdx_rl$D_IN;
|
|
if (m_tlb_m_validVec_0$EN)
|
|
m_tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_0$D_IN;
|
|
if (m_tlb_m_validVec_1$EN)
|
|
m_tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_1$D_IN;
|
|
if (m_tlb_m_validVec_10$EN)
|
|
m_tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_10$D_IN;
|
|
if (m_tlb_m_validVec_11$EN)
|
|
m_tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_11$D_IN;
|
|
if (m_tlb_m_validVec_12$EN)
|
|
m_tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_12$D_IN;
|
|
if (m_tlb_m_validVec_13$EN)
|
|
m_tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_13$D_IN;
|
|
if (m_tlb_m_validVec_14$EN)
|
|
m_tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_14$D_IN;
|
|
if (m_tlb_m_validVec_15$EN)
|
|
m_tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_15$D_IN;
|
|
if (m_tlb_m_validVec_16$EN)
|
|
m_tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_16$D_IN;
|
|
if (m_tlb_m_validVec_17$EN)
|
|
m_tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_17$D_IN;
|
|
if (m_tlb_m_validVec_18$EN)
|
|
m_tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_18$D_IN;
|
|
if (m_tlb_m_validVec_19$EN)
|
|
m_tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_19$D_IN;
|
|
if (m_tlb_m_validVec_2$EN)
|
|
m_tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_2$D_IN;
|
|
if (m_tlb_m_validVec_20$EN)
|
|
m_tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_20$D_IN;
|
|
if (m_tlb_m_validVec_21$EN)
|
|
m_tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_21$D_IN;
|
|
if (m_tlb_m_validVec_22$EN)
|
|
m_tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_22$D_IN;
|
|
if (m_tlb_m_validVec_23$EN)
|
|
m_tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_23$D_IN;
|
|
if (m_tlb_m_validVec_24$EN)
|
|
m_tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_24$D_IN;
|
|
if (m_tlb_m_validVec_25$EN)
|
|
m_tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_25$D_IN;
|
|
if (m_tlb_m_validVec_26$EN)
|
|
m_tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_26$D_IN;
|
|
if (m_tlb_m_validVec_27$EN)
|
|
m_tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_27$D_IN;
|
|
if (m_tlb_m_validVec_28$EN)
|
|
m_tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_28$D_IN;
|
|
if (m_tlb_m_validVec_29$EN)
|
|
m_tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_29$D_IN;
|
|
if (m_tlb_m_validVec_3$EN)
|
|
m_tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_3$D_IN;
|
|
if (m_tlb_m_validVec_30$EN)
|
|
m_tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_30$D_IN;
|
|
if (m_tlb_m_validVec_31$EN)
|
|
m_tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_31$D_IN;
|
|
if (m_tlb_m_validVec_4$EN)
|
|
m_tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_4$D_IN;
|
|
if (m_tlb_m_validVec_5$EN)
|
|
m_tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_5$D_IN;
|
|
if (m_tlb_m_validVec_6$EN)
|
|
m_tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_6$D_IN;
|
|
if (m_tlb_m_validVec_7$EN)
|
|
m_tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_7$D_IN;
|
|
if (m_tlb_m_validVec_8$EN)
|
|
m_tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_8$D_IN;
|
|
if (m_tlb_m_validVec_9$EN)
|
|
m_tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_9$D_IN;
|
|
if (m_vm_info$EN) m_vm_info <= `BSV_ASSIGNMENT_DELAY m_vm_info$D_IN;
|
|
if (m_waitFlushP$EN)
|
|
m_waitFlushP <= `BSV_ASSIGNMENT_DELAY m_waitFlushP$D_IN;
|
|
end
|
|
if (m_pendInst_0$EN)
|
|
m_pendInst_0 <= `BSV_ASSIGNMENT_DELAY m_pendInst_0$D_IN;
|
|
if (m_pendInst_1$EN)
|
|
m_pendInst_1 <= `BSV_ASSIGNMENT_DELAY m_pendInst_1$D_IN;
|
|
if (m_pendInst_2$EN)
|
|
m_pendInst_2 <= `BSV_ASSIGNMENT_DELAY m_pendInst_2$D_IN;
|
|
if (m_pendInst_3$EN)
|
|
m_pendInst_3 <= `BSV_ASSIGNMENT_DELAY m_pendInst_3$D_IN;
|
|
if (m_pendPoisoned_0$EN)
|
|
m_pendPoisoned_0 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_0$D_IN;
|
|
if (m_pendPoisoned_1$EN)
|
|
m_pendPoisoned_1 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_1$D_IN;
|
|
if (m_pendPoisoned_2$EN)
|
|
m_pendPoisoned_2 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_2$D_IN;
|
|
if (m_pendPoisoned_3$EN)
|
|
m_pendPoisoned_3 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_3$D_IN;
|
|
if (m_pendResp_0$EN)
|
|
m_pendResp_0 <= `BSV_ASSIGNMENT_DELAY m_pendResp_0$D_IN;
|
|
if (m_pendResp_1$EN)
|
|
m_pendResp_1 <= `BSV_ASSIGNMENT_DELAY m_pendResp_1$D_IN;
|
|
if (m_pendResp_2$EN)
|
|
m_pendResp_2 <= `BSV_ASSIGNMENT_DELAY m_pendResp_2$D_IN;
|
|
if (m_pendResp_3$EN)
|
|
m_pendResp_3 <= `BSV_ASSIGNMENT_DELAY m_pendResp_3$D_IN;
|
|
if (m_tlb_m_entryVec_0$EN)
|
|
m_tlb_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_0$D_IN;
|
|
if (m_tlb_m_entryVec_1$EN)
|
|
m_tlb_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_1$D_IN;
|
|
if (m_tlb_m_entryVec_10$EN)
|
|
m_tlb_m_entryVec_10 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_10$D_IN;
|
|
if (m_tlb_m_entryVec_11$EN)
|
|
m_tlb_m_entryVec_11 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_11$D_IN;
|
|
if (m_tlb_m_entryVec_12$EN)
|
|
m_tlb_m_entryVec_12 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_12$D_IN;
|
|
if (m_tlb_m_entryVec_13$EN)
|
|
m_tlb_m_entryVec_13 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_13$D_IN;
|
|
if (m_tlb_m_entryVec_14$EN)
|
|
m_tlb_m_entryVec_14 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_14$D_IN;
|
|
if (m_tlb_m_entryVec_15$EN)
|
|
m_tlb_m_entryVec_15 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_15$D_IN;
|
|
if (m_tlb_m_entryVec_16$EN)
|
|
m_tlb_m_entryVec_16 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_16$D_IN;
|
|
if (m_tlb_m_entryVec_17$EN)
|
|
m_tlb_m_entryVec_17 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_17$D_IN;
|
|
if (m_tlb_m_entryVec_18$EN)
|
|
m_tlb_m_entryVec_18 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_18$D_IN;
|
|
if (m_tlb_m_entryVec_19$EN)
|
|
m_tlb_m_entryVec_19 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_19$D_IN;
|
|
if (m_tlb_m_entryVec_2$EN)
|
|
m_tlb_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_2$D_IN;
|
|
if (m_tlb_m_entryVec_20$EN)
|
|
m_tlb_m_entryVec_20 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_20$D_IN;
|
|
if (m_tlb_m_entryVec_21$EN)
|
|
m_tlb_m_entryVec_21 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_21$D_IN;
|
|
if (m_tlb_m_entryVec_22$EN)
|
|
m_tlb_m_entryVec_22 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_22$D_IN;
|
|
if (m_tlb_m_entryVec_23$EN)
|
|
m_tlb_m_entryVec_23 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_23$D_IN;
|
|
if (m_tlb_m_entryVec_24$EN)
|
|
m_tlb_m_entryVec_24 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_24$D_IN;
|
|
if (m_tlb_m_entryVec_25$EN)
|
|
m_tlb_m_entryVec_25 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_25$D_IN;
|
|
if (m_tlb_m_entryVec_26$EN)
|
|
m_tlb_m_entryVec_26 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_26$D_IN;
|
|
if (m_tlb_m_entryVec_27$EN)
|
|
m_tlb_m_entryVec_27 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_27$D_IN;
|
|
if (m_tlb_m_entryVec_28$EN)
|
|
m_tlb_m_entryVec_28 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_28$D_IN;
|
|
if (m_tlb_m_entryVec_29$EN)
|
|
m_tlb_m_entryVec_29 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_29$D_IN;
|
|
if (m_tlb_m_entryVec_3$EN)
|
|
m_tlb_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_3$D_IN;
|
|
if (m_tlb_m_entryVec_30$EN)
|
|
m_tlb_m_entryVec_30 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_30$D_IN;
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if (m_tlb_m_entryVec_31$EN)
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|
m_tlb_m_entryVec_31 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_31$D_IN;
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if (m_tlb_m_entryVec_4$EN)
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m_tlb_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_4$D_IN;
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if (m_tlb_m_entryVec_5$EN)
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m_tlb_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_5$D_IN;
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if (m_tlb_m_entryVec_6$EN)
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m_tlb_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_6$D_IN;
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if (m_tlb_m_entryVec_7$EN)
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m_tlb_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_7$D_IN;
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if (m_tlb_m_entryVec_8$EN)
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m_tlb_m_entryVec_8 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_8$D_IN;
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if (m_tlb_m_entryVec_9$EN)
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m_tlb_m_entryVec_9 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_9$D_IN;
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end
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// synopsys translate_off
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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initial
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begin
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m_flushRqToPQ_clearReq_rl = 1'h0;
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m_flushRqToPQ_deqReq_rl = 1'h0;
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m_flushRqToPQ_empty = 1'h0;
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m_flushRqToPQ_enqReq_rl = 1'h0;
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m_flushRqToPQ_full = 1'h0;
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m_flushRsFromPQ_clearReq_rl = 1'h0;
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m_flushRsFromPQ_deqReq_rl = 1'h0;
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m_flushRsFromPQ_empty = 1'h0;
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m_flushRsFromPQ_enqReq_rl = 1'h0;
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m_flushRsFromPQ_full = 1'h0;
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m_freeQInitIdx = 2'h2;
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m_freeQInited = 1'h0;
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m_freeQ_clearReq_rl = 1'h0;
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m_freeQ_data_0 = 2'h2;
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m_freeQ_data_1 = 2'h2;
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m_freeQ_data_2 = 2'h2;
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m_freeQ_data_3 = 2'h2;
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m_freeQ_deqP = 2'h2;
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m_freeQ_deqReq_rl = 1'h0;
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m_freeQ_empty = 1'h0;
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m_freeQ_enqP = 2'h2;
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m_freeQ_enqReq_rl = 3'h2;
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m_freeQ_full = 1'h0;
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m_ldTransRsFromPQ_clearReq_rl = 1'h0;
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m_ldTransRsFromPQ_data_0 = 83'h2AAAAAAAAAAAAAAAAAAAA;
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m_ldTransRsFromPQ_data_1 = 83'h2AAAAAAAAAAAAAAAAAAAA;
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m_ldTransRsFromPQ_deqP = 1'h0;
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|
m_ldTransRsFromPQ_deqReq_rl = 1'h0;
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|
m_ldTransRsFromPQ_empty = 1'h0;
|
|
m_ldTransRsFromPQ_enqP = 1'h0;
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m_ldTransRsFromPQ_enqReq_rl = 84'hAAAAAAAAAAAAAAAAAAAAA;
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m_ldTransRsFromPQ_full = 1'h0;
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m_needFlush = 1'h0;
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m_pendInst_0 =
|
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479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
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|
m_pendInst_1 =
|
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479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
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m_pendInst_2 =
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479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
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|
m_pendInst_3 =
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479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendPoisoned_0 = 1'h0;
|
|
m_pendPoisoned_1 = 1'h0;
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|
m_pendPoisoned_2 = 1'h0;
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|
m_pendPoisoned_3 = 1'h0;
|
|
m_pendResp_0 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendResp_1 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendResp_2 = 70'h2AAAAAAAAAAAAAAAAA;
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|
m_pendResp_3 = 70'h2AAAAAAAAAAAAAAAAA;
|
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m_pendSpecBits_0_rl = 12'hAAA;
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|
m_pendSpecBits_1_rl = 12'hAAA;
|
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m_pendSpecBits_2_rl = 12'hAAA;
|
|
m_pendSpecBits_3_rl = 12'hAAA;
|
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m_pendValid_0_rl = 1'h0;
|
|
m_pendValid_1_rl = 1'h0;
|
|
m_pendValid_2_rl = 1'h0;
|
|
m_pendValid_3_rl = 1'h0;
|
|
m_pendWait_0 = 4'hA;
|
|
m_pendWait_1 = 4'hA;
|
|
m_pendWait_2 = 4'hA;
|
|
m_pendWait_3 = 4'hA;
|
|
m_perfReqQ_clearReq_rl = 1'h0;
|
|
m_perfReqQ_data_0 = 3'h2;
|
|
m_perfReqQ_deqReq_rl = 1'h0;
|
|
m_perfReqQ_empty = 1'h0;
|
|
m_perfReqQ_enqReq_rl = 4'hA;
|
|
m_perfReqQ_full = 1'h0;
|
|
m_respForOtherReq = 3'h2;
|
|
m_rqToPQ_clearReq_rl = 1'h0;
|
|
m_rqToPQ_data_0 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_1 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_2 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_3 = 29'h0AAAAAAA;
|
|
m_rqToPQ_deqP = 2'h2;
|
|
m_rqToPQ_deqReq_rl = 1'h0;
|
|
m_rqToPQ_empty = 1'h0;
|
|
m_rqToPQ_enqP = 2'h2;
|
|
m_rqToPQ_enqReq_rl = 30'h2AAAAAAA;
|
|
m_rqToPQ_full = 1'h0;
|
|
m_tlb_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_10 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_11 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_12 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_13 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_14 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_15 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_16 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_17 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_18 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_19 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_20 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_21 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_22 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_23 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_24 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_25 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_26 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_27 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_28 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_29 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_30 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_31 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_8 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_9 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_lruBit_rl = 32'hAAAAAAAA;
|
|
m_tlb_m_randIdx = 5'h0A;
|
|
m_tlb_m_updRepIdx_rl = 6'h2A;
|
|
m_tlb_m_validVec_0 = 1'h0;
|
|
m_tlb_m_validVec_1 = 1'h0;
|
|
m_tlb_m_validVec_10 = 1'h0;
|
|
m_tlb_m_validVec_11 = 1'h0;
|
|
m_tlb_m_validVec_12 = 1'h0;
|
|
m_tlb_m_validVec_13 = 1'h0;
|
|
m_tlb_m_validVec_14 = 1'h0;
|
|
m_tlb_m_validVec_15 = 1'h0;
|
|
m_tlb_m_validVec_16 = 1'h0;
|
|
m_tlb_m_validVec_17 = 1'h0;
|
|
m_tlb_m_validVec_18 = 1'h0;
|
|
m_tlb_m_validVec_19 = 1'h0;
|
|
m_tlb_m_validVec_2 = 1'h0;
|
|
m_tlb_m_validVec_20 = 1'h0;
|
|
m_tlb_m_validVec_21 = 1'h0;
|
|
m_tlb_m_validVec_22 = 1'h0;
|
|
m_tlb_m_validVec_23 = 1'h0;
|
|
m_tlb_m_validVec_24 = 1'h0;
|
|
m_tlb_m_validVec_25 = 1'h0;
|
|
m_tlb_m_validVec_26 = 1'h0;
|
|
m_tlb_m_validVec_27 = 1'h0;
|
|
m_tlb_m_validVec_28 = 1'h0;
|
|
m_tlb_m_validVec_29 = 1'h0;
|
|
m_tlb_m_validVec_3 = 1'h0;
|
|
m_tlb_m_validVec_30 = 1'h0;
|
|
m_tlb_m_validVec_31 = 1'h0;
|
|
m_tlb_m_validVec_4 = 1'h0;
|
|
m_tlb_m_validVec_5 = 1'h0;
|
|
m_tlb_m_validVec_6 = 1'h0;
|
|
m_tlb_m_validVec_7 = 1'h0;
|
|
m_tlb_m_validVec_8 = 1'h0;
|
|
m_tlb_m_validVec_9 = 1'h0;
|
|
m_vm_info = 49'h0AAAAAAAAAAAA;
|
|
m_waitFlushP = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkDTlbSynth
|
|
|