881 lines
28 KiB
Verilog
881 lines
28 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:35:55 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1
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// first_data O 43
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// RDY_first_data O 1
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// first_poisoned O 1
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// RDY_first_poisoned O 1
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 43
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_deq I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkFmaExecQ(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first_data,
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RDY_first_data,
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first_poisoned,
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RDY_first_poisoned,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [42 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first_data
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output [42 : 0] first_data;
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output RDY_first_data;
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// value method first_poisoned
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output first_poisoned;
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output RDY_first_poisoned;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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reg RDY_deq, first_poisoned;
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wire [42 : 0] first_data;
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wire RDY_enq,
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RDY_first_data,
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RDY_first_poisoned,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation;
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// inlined wires
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reg m_m_valid_for_enq_wire$wget;
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wire [11 : 0] m_m_specBits_0_lat_1$wget, m_m_specBits_1_lat_1$wget;
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wire m_m_poisoned_0_lat_0$whas,
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m_m_poisoned_1_lat_0$whas,
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m_m_poisoned_2_lat_0$whas,
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m_m_poisoned_3_lat_0$whas,
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m_m_valid_0_lat_0$whas,
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m_m_valid_0_lat_1$whas,
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m_m_valid_1_lat_0$whas,
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m_m_valid_1_lat_1$whas,
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m_m_valid_2_lat_0$whas,
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m_m_valid_2_lat_1$whas,
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m_m_valid_3_lat_0$whas,
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m_m_valid_3_lat_1$whas;
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// register m_m_deqP
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reg [1 : 0] m_m_deqP;
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wire [1 : 0] m_m_deqP$D_IN;
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wire m_m_deqP$EN;
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// register m_m_enqP
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reg [1 : 0] m_m_enqP;
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wire [1 : 0] m_m_enqP$D_IN;
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wire m_m_enqP$EN;
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// register m_m_poisoned_0_rl
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reg m_m_poisoned_0_rl;
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wire m_m_poisoned_0_rl$D_IN, m_m_poisoned_0_rl$EN;
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// register m_m_poisoned_1_rl
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reg m_m_poisoned_1_rl;
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wire m_m_poisoned_1_rl$D_IN, m_m_poisoned_1_rl$EN;
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// register m_m_poisoned_2_rl
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reg m_m_poisoned_2_rl;
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wire m_m_poisoned_2_rl$D_IN, m_m_poisoned_2_rl$EN;
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// register m_m_poisoned_3_rl
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reg m_m_poisoned_3_rl;
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wire m_m_poisoned_3_rl$D_IN, m_m_poisoned_3_rl$EN;
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// register m_m_row_0
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reg [30 : 0] m_m_row_0;
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wire [30 : 0] m_m_row_0$D_IN;
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wire m_m_row_0$EN;
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// register m_m_row_1
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reg [30 : 0] m_m_row_1;
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wire [30 : 0] m_m_row_1$D_IN;
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wire m_m_row_1$EN;
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// register m_m_row_2
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reg [30 : 0] m_m_row_2;
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wire [30 : 0] m_m_row_2$D_IN;
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wire m_m_row_2$EN;
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// register m_m_row_3
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reg [30 : 0] m_m_row_3;
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wire [30 : 0] m_m_row_3$D_IN;
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wire m_m_row_3$EN;
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// register m_m_specBits_0_rl
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reg [11 : 0] m_m_specBits_0_rl;
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wire [11 : 0] m_m_specBits_0_rl$D_IN;
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wire m_m_specBits_0_rl$EN;
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// register m_m_specBits_1_rl
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reg [11 : 0] m_m_specBits_1_rl;
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wire [11 : 0] m_m_specBits_1_rl$D_IN;
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wire m_m_specBits_1_rl$EN;
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// register m_m_specBits_2_rl
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reg [11 : 0] m_m_specBits_2_rl;
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wire [11 : 0] m_m_specBits_2_rl$D_IN;
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wire m_m_specBits_2_rl$EN;
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// register m_m_specBits_3_rl
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reg [11 : 0] m_m_specBits_3_rl;
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wire [11 : 0] m_m_specBits_3_rl$D_IN;
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wire m_m_specBits_3_rl$EN;
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// register m_m_valid_0_rl
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reg m_m_valid_0_rl;
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wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN;
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// register m_m_valid_1_rl
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reg m_m_valid_1_rl;
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wire m_m_valid_1_rl$D_IN, m_m_valid_1_rl$EN;
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// register m_m_valid_2_rl
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reg m_m_valid_2_rl;
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wire m_m_valid_2_rl$D_IN, m_m_valid_2_rl$EN;
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// register m_m_valid_3_rl
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reg m_m_valid_3_rl;
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wire m_m_valid_3_rl$D_IN, m_m_valid_3_rl$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_m_poisoned_0_canon,
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CAN_FIRE_RL_m_m_poisoned_1_canon,
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CAN_FIRE_RL_m_m_poisoned_2_canon,
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CAN_FIRE_RL_m_m_poisoned_3_canon,
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CAN_FIRE_RL_m_m_setEnqWire,
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CAN_FIRE_RL_m_m_specBits_0_canon,
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CAN_FIRE_RL_m_m_specBits_1_canon,
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CAN_FIRE_RL_m_m_specBits_2_canon,
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CAN_FIRE_RL_m_m_specBits_3_canon,
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CAN_FIRE_RL_m_m_valid_0_canon,
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CAN_FIRE_RL_m_m_valid_1_canon,
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CAN_FIRE_RL_m_m_valid_2_canon,
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CAN_FIRE_RL_m_m_valid_3_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_RL_m_m_poisoned_0_canon,
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WILL_FIRE_RL_m_m_poisoned_1_canon,
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WILL_FIRE_RL_m_m_poisoned_2_canon,
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WILL_FIRE_RL_m_m_poisoned_3_canon,
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WILL_FIRE_RL_m_m_setEnqWire,
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WILL_FIRE_RL_m_m_specBits_0_canon,
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WILL_FIRE_RL_m_m_specBits_1_canon,
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WILL_FIRE_RL_m_m_specBits_2_canon,
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WILL_FIRE_RL_m_m_specBits_3_canon,
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WILL_FIRE_RL_m_m_valid_0_canon,
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WILL_FIRE_RL_m_m_valid_1_canon,
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WILL_FIRE_RL_m_m_valid_2_canon,
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WILL_FIRE_RL_m_m_valid_3_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation;
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// remaining internal signals
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reg [11 : 0] SEL_ARR_m_m_specBits_0_rl_1_m_m_specBits_1_rl__ETC___d213;
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reg [6 : 0] SEL_ARR_m_m_row_0_11_BITS_19_TO_13_76_m_m_row__ETC___d181;
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reg [5 : 0] SEL_ARR_m_m_row_0_11_BITS_5_TO_0_03_m_m_row_1__ETC___d208;
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reg [4 : 0] SEL_ARR_m_m_row_0_11_BITS_10_TO_6_97_m_m_row_1_ETC___d202;
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reg [2 : 0] SEL_ARR_m_m_row_0_11_BITS_30_TO_28_12_m_m_row__ETC___d120;
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reg SEL_ARR_NOT_m_m_row_0_11_BIT_20_65_66_NOT_m_m__ETC___d174,
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SEL_ARR_m_m_row_0_11_BIT_11_91_m_m_row_1_13_BI_ETC___d196,
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SEL_ARR_m_m_row_0_11_BIT_12_82_m_m_row_1_13_BI_ETC___d187,
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SEL_ARR_m_m_row_0_11_BIT_21_59_m_m_row_1_13_BI_ETC___d164,
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SEL_ARR_m_m_row_0_11_BIT_22_51_m_m_row_1_13_BI_ETC___d156,
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SEL_ARR_m_m_row_0_11_BIT_23_45_m_m_row_1_13_BI_ETC___d150,
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SEL_ARR_m_m_row_0_11_BIT_24_39_m_m_row_1_13_BI_ETC___d144,
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SEL_ARR_m_m_row_0_11_BIT_25_33_m_m_row_1_13_BI_ETC___d138,
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SEL_ARR_m_m_row_0_11_BIT_26_27_m_m_row_1_13_BI_ETC___d132,
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SEL_ARR_m_m_row_0_11_BIT_27_21_m_m_row_1_13_BI_ETC___d126;
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wire [11 : 0] n__read__h8963,
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n__read__h9093,
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n__read__h9223,
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n__read__h9353,
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upd__h4230,
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upd__h4575,
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upd__h4920,
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upd__h5265;
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// action method enq
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assign RDY_enq = !m_m_valid_for_enq_wire$wget ;
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assign CAN_FIRE_enq = !m_m_valid_for_enq_wire$wget ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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always@(m_m_deqP or
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m_m_valid_0_rl or
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m_m_valid_1_rl or m_m_valid_2_rl or m_m_valid_3_rl)
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begin
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case (m_m_deqP)
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2'd0: RDY_deq = m_m_valid_0_rl;
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2'd1: RDY_deq = m_m_valid_1_rl;
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2'd2: RDY_deq = m_m_valid_2_rl;
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2'd3: RDY_deq = m_m_valid_3_rl;
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endcase
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end
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assign CAN_FIRE_deq = RDY_deq ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first_data
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assign first_data =
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{ SEL_ARR_m_m_row_0_11_BITS_30_TO_28_12_m_m_row__ETC___d120,
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SEL_ARR_m_m_row_0_11_BIT_27_21_m_m_row_1_13_BI_ETC___d126,
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SEL_ARR_m_m_row_0_11_BIT_26_27_m_m_row_1_13_BI_ETC___d132,
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SEL_ARR_m_m_row_0_11_BIT_25_33_m_m_row_1_13_BI_ETC___d138,
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SEL_ARR_m_m_row_0_11_BIT_24_39_m_m_row_1_13_BI_ETC___d144,
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SEL_ARR_m_m_row_0_11_BIT_23_45_m_m_row_1_13_BI_ETC___d150,
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SEL_ARR_m_m_row_0_11_BIT_22_51_m_m_row_1_13_BI_ETC___d156,
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SEL_ARR_m_m_row_0_11_BIT_21_59_m_m_row_1_13_BI_ETC___d164,
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!SEL_ARR_NOT_m_m_row_0_11_BIT_20_65_66_NOT_m_m__ETC___d174,
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SEL_ARR_m_m_row_0_11_BITS_19_TO_13_76_m_m_row__ETC___d181,
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SEL_ARR_m_m_row_0_11_BIT_12_82_m_m_row_1_13_BI_ETC___d187,
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SEL_ARR_m_m_row_0_11_BIT_11_91_m_m_row_1_13_BI_ETC___d196,
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SEL_ARR_m_m_row_0_11_BITS_10_TO_6_97_m_m_row_1_ETC___d202,
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SEL_ARR_m_m_row_0_11_BITS_5_TO_0_03_m_m_row_1__ETC___d208,
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SEL_ARR_m_m_specBits_0_rl_1_m_m_specBits_1_rl__ETC___d213 } ;
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assign RDY_first_data = RDY_deq ;
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// value method first_poisoned
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always@(m_m_deqP or
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m_m_poisoned_0_rl or
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m_m_poisoned_1_rl or m_m_poisoned_2_rl or m_m_poisoned_3_rl)
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begin
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case (m_m_deqP)
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2'd0: first_poisoned = m_m_poisoned_0_rl;
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2'd1: first_poisoned = m_m_poisoned_1_rl;
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2'd2: first_poisoned = m_m_poisoned_2_rl;
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2'd3: first_poisoned = m_m_poisoned_3_rl;
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endcase
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end
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assign RDY_first_poisoned = RDY_deq ;
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// action method specUpdate_incorrectSpeculation
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assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_incorrectSpeculation =
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EN_specUpdate_incorrectSpeculation ;
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// action method specUpdate_correctSpeculation
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assign RDY_specUpdate_correctSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_correctSpeculation =
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EN_specUpdate_correctSpeculation ;
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// rule RL_m_m_setEnqWire
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assign CAN_FIRE_RL_m_m_setEnqWire = 1'd1 ;
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assign WILL_FIRE_RL_m_m_setEnqWire = 1'd1 ;
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// rule RL_m_m_valid_0_canon
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assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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// rule RL_m_m_valid_1_canon
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assign CAN_FIRE_RL_m_m_valid_1_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_1_canon = 1'd1 ;
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// rule RL_m_m_valid_2_canon
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assign CAN_FIRE_RL_m_m_valid_2_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_2_canon = 1'd1 ;
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// rule RL_m_m_valid_3_canon
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assign CAN_FIRE_RL_m_m_valid_3_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_3_canon = 1'd1 ;
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// rule RL_m_m_poisoned_0_canon
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assign CAN_FIRE_RL_m_m_poisoned_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_poisoned_0_canon = 1'd1 ;
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// rule RL_m_m_poisoned_1_canon
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assign CAN_FIRE_RL_m_m_poisoned_1_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_poisoned_1_canon = 1'd1 ;
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// rule RL_m_m_poisoned_2_canon
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assign CAN_FIRE_RL_m_m_poisoned_2_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_poisoned_2_canon = 1'd1 ;
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// rule RL_m_m_poisoned_3_canon
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assign CAN_FIRE_RL_m_m_poisoned_3_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_poisoned_3_canon = 1'd1 ;
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// rule RL_m_m_specBits_0_canon
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assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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// rule RL_m_m_specBits_1_canon
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assign CAN_FIRE_RL_m_m_specBits_1_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_1_canon = 1'd1 ;
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// rule RL_m_m_specBits_2_canon
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assign CAN_FIRE_RL_m_m_specBits_2_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_2_canon = 1'd1 ;
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// rule RL_m_m_specBits_3_canon
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assign CAN_FIRE_RL_m_m_specBits_3_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_3_canon = 1'd1 ;
|
|
|
|
// inlined wires
|
|
assign m_m_valid_0_lat_0$whas = EN_deq && m_m_deqP == 2'd0 ;
|
|
assign m_m_valid_0_lat_1$whas = EN_enq && m_m_enqP == 2'd0 ;
|
|
assign m_m_valid_1_lat_0$whas = EN_deq && m_m_deqP == 2'd1 ;
|
|
assign m_m_valid_1_lat_1$whas = EN_enq && m_m_enqP == 2'd1 ;
|
|
assign m_m_valid_2_lat_0$whas = EN_deq && m_m_deqP == 2'd2 ;
|
|
assign m_m_valid_2_lat_1$whas = EN_enq && m_m_enqP == 2'd2 ;
|
|
assign m_m_valid_3_lat_0$whas = EN_deq && m_m_deqP == 2'd3 ;
|
|
assign m_m_valid_3_lat_1$whas = EN_enq && m_m_enqP == 2'd3 ;
|
|
assign m_m_poisoned_0_lat_0$whas =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_m_specBits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign m_m_poisoned_1_lat_0$whas =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_m_specBits_1_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign m_m_poisoned_2_lat_0$whas =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_m_specBits_2_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign m_m_poisoned_3_lat_0$whas =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_m_specBits_3_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign m_m_specBits_0_lat_1$wget =
|
|
n__read__h8963 & specUpdate_correctSpeculation_mask ;
|
|
assign m_m_specBits_1_lat_1$wget =
|
|
n__read__h9093 & specUpdate_correctSpeculation_mask ;
|
|
always@(m_m_enqP or
|
|
m_m_valid_0_rl or
|
|
m_m_valid_1_rl or m_m_valid_2_rl or m_m_valid_3_rl)
|
|
begin
|
|
case (m_m_enqP)
|
|
2'd0: m_m_valid_for_enq_wire$wget = m_m_valid_0_rl;
|
|
2'd1: m_m_valid_for_enq_wire$wget = m_m_valid_1_rl;
|
|
2'd2: m_m_valid_for_enq_wire$wget = m_m_valid_2_rl;
|
|
2'd3: m_m_valid_for_enq_wire$wget = m_m_valid_3_rl;
|
|
endcase
|
|
end
|
|
|
|
// register m_m_deqP
|
|
assign m_m_deqP$D_IN = (m_m_deqP == 2'd3) ? 2'd0 : m_m_deqP + 2'd1 ;
|
|
assign m_m_deqP$EN = EN_deq ;
|
|
|
|
// register m_m_enqP
|
|
assign m_m_enqP$D_IN = (m_m_enqP == 2'd3) ? 2'd0 : m_m_enqP + 2'd1 ;
|
|
assign m_m_enqP$EN = EN_enq ;
|
|
|
|
// register m_m_poisoned_0_rl
|
|
assign m_m_poisoned_0_rl$D_IN =
|
|
!m_m_valid_0_lat_1$whas &&
|
|
(m_m_poisoned_0_lat_0$whas || m_m_poisoned_0_rl) ;
|
|
assign m_m_poisoned_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_poisoned_1_rl
|
|
assign m_m_poisoned_1_rl$D_IN =
|
|
!m_m_valid_1_lat_1$whas &&
|
|
(m_m_poisoned_1_lat_0$whas || m_m_poisoned_1_rl) ;
|
|
assign m_m_poisoned_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_poisoned_2_rl
|
|
assign m_m_poisoned_2_rl$D_IN =
|
|
!m_m_valid_2_lat_1$whas &&
|
|
(m_m_poisoned_2_lat_0$whas || m_m_poisoned_2_rl) ;
|
|
assign m_m_poisoned_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_poisoned_3_rl
|
|
assign m_m_poisoned_3_rl$D_IN =
|
|
!m_m_valid_3_lat_1$whas &&
|
|
(m_m_poisoned_3_lat_0$whas || m_m_poisoned_3_rl) ;
|
|
assign m_m_poisoned_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_row_0
|
|
assign m_m_row_0$D_IN = enq_x[42:12] ;
|
|
assign m_m_row_0$EN = m_m_valid_0_lat_1$whas ;
|
|
|
|
// register m_m_row_1
|
|
assign m_m_row_1$D_IN = enq_x[42:12] ;
|
|
assign m_m_row_1$EN = m_m_valid_1_lat_1$whas ;
|
|
|
|
// register m_m_row_2
|
|
assign m_m_row_2$D_IN = enq_x[42:12] ;
|
|
assign m_m_row_2$EN = m_m_valid_2_lat_1$whas ;
|
|
|
|
// register m_m_row_3
|
|
assign m_m_row_3$D_IN = enq_x[42:12] ;
|
|
assign m_m_row_3$EN = m_m_valid_3_lat_1$whas ;
|
|
|
|
// register m_m_specBits_0_rl
|
|
assign m_m_specBits_0_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ? upd__h4230 : n__read__h8963 ;
|
|
assign m_m_specBits_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_specBits_1_rl
|
|
assign m_m_specBits_1_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ? upd__h4575 : n__read__h9093 ;
|
|
assign m_m_specBits_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_specBits_2_rl
|
|
assign m_m_specBits_2_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ? upd__h4920 : n__read__h9223 ;
|
|
assign m_m_specBits_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_specBits_3_rl
|
|
assign m_m_specBits_3_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ? upd__h5265 : n__read__h9353 ;
|
|
assign m_m_specBits_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_valid_0_rl
|
|
assign m_m_valid_0_rl$D_IN =
|
|
m_m_valid_0_lat_1$whas ||
|
|
!m_m_valid_0_lat_0$whas && m_m_valid_0_rl ;
|
|
assign m_m_valid_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_valid_1_rl
|
|
assign m_m_valid_1_rl$D_IN =
|
|
m_m_valid_1_lat_1$whas ||
|
|
!m_m_valid_1_lat_0$whas && m_m_valid_1_rl ;
|
|
assign m_m_valid_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_valid_2_rl
|
|
assign m_m_valid_2_rl$D_IN =
|
|
m_m_valid_2_lat_1$whas ||
|
|
!m_m_valid_2_lat_0$whas && m_m_valid_2_rl ;
|
|
assign m_m_valid_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_valid_3_rl
|
|
assign m_m_valid_3_rl$D_IN =
|
|
m_m_valid_3_lat_1$whas ||
|
|
!m_m_valid_3_lat_0$whas && m_m_valid_3_rl ;
|
|
assign m_m_valid_3_rl$EN = 1'd1 ;
|
|
|
|
// remaining internal signals
|
|
assign n__read__h8963 =
|
|
m_m_valid_0_lat_1$whas ? enq_x[11:0] : m_m_specBits_0_rl ;
|
|
assign n__read__h9093 =
|
|
m_m_valid_1_lat_1$whas ? enq_x[11:0] : m_m_specBits_1_rl ;
|
|
assign n__read__h9223 =
|
|
m_m_valid_2_lat_1$whas ? enq_x[11:0] : m_m_specBits_2_rl ;
|
|
assign n__read__h9353 =
|
|
m_m_valid_3_lat_1$whas ? enq_x[11:0] : m_m_specBits_3_rl ;
|
|
assign upd__h4230 = m_m_specBits_0_lat_1$wget ;
|
|
assign upd__h4575 = m_m_specBits_1_lat_1$wget ;
|
|
assign upd__h4920 = n__read__h9223 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h5265 = n__read__h9353 & specUpdate_correctSpeculation_mask ;
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_m_row_0_11_BIT_20_65_66_NOT_m_m__ETC___d174 =
|
|
!m_m_row_0[20];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_m_row_0_11_BIT_20_65_66_NOT_m_m__ETC___d174 =
|
|
!m_m_row_1[20];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_m_row_0_11_BIT_20_65_66_NOT_m_m__ETC___d174 =
|
|
!m_m_row_2[20];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_m_row_0_11_BIT_20_65_66_NOT_m_m__ETC___d174 =
|
|
!m_m_row_3[20];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_24_39_m_m_row_1_13_BI_ETC___d144 =
|
|
m_m_row_0[24];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_24_39_m_m_row_1_13_BI_ETC___d144 =
|
|
m_m_row_1[24];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_24_39_m_m_row_1_13_BI_ETC___d144 =
|
|
m_m_row_2[24];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_24_39_m_m_row_1_13_BI_ETC___d144 =
|
|
m_m_row_3[24];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_23_45_m_m_row_1_13_BI_ETC___d150 =
|
|
m_m_row_0[23];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_23_45_m_m_row_1_13_BI_ETC___d150 =
|
|
m_m_row_1[23];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_23_45_m_m_row_1_13_BI_ETC___d150 =
|
|
m_m_row_2[23];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_23_45_m_m_row_1_13_BI_ETC___d150 =
|
|
m_m_row_3[23];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_22_51_m_m_row_1_13_BI_ETC___d156 =
|
|
m_m_row_0[22];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_22_51_m_m_row_1_13_BI_ETC___d156 =
|
|
m_m_row_1[22];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_22_51_m_m_row_1_13_BI_ETC___d156 =
|
|
m_m_row_2[22];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_22_51_m_m_row_1_13_BI_ETC___d156 =
|
|
m_m_row_3[22];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_26_27_m_m_row_1_13_BI_ETC___d132 =
|
|
m_m_row_0[26];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_26_27_m_m_row_1_13_BI_ETC___d132 =
|
|
m_m_row_1[26];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_26_27_m_m_row_1_13_BI_ETC___d132 =
|
|
m_m_row_2[26];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_26_27_m_m_row_1_13_BI_ETC___d132 =
|
|
m_m_row_3[26];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_25_33_m_m_row_1_13_BI_ETC___d138 =
|
|
m_m_row_0[25];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_25_33_m_m_row_1_13_BI_ETC___d138 =
|
|
m_m_row_1[25];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_25_33_m_m_row_1_13_BI_ETC___d138 =
|
|
m_m_row_2[25];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_25_33_m_m_row_1_13_BI_ETC___d138 =
|
|
m_m_row_3[25];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BITS_19_TO_13_76_m_m_row__ETC___d181 =
|
|
m_m_row_0[19:13];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BITS_19_TO_13_76_m_m_row__ETC___d181 =
|
|
m_m_row_1[19:13];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BITS_19_TO_13_76_m_m_row__ETC___d181 =
|
|
m_m_row_2[19:13];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BITS_19_TO_13_76_m_m_row__ETC___d181 =
|
|
m_m_row_3[19:13];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_12_82_m_m_row_1_13_BI_ETC___d187 =
|
|
m_m_row_0[12];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_12_82_m_m_row_1_13_BI_ETC___d187 =
|
|
m_m_row_1[12];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_12_82_m_m_row_1_13_BI_ETC___d187 =
|
|
m_m_row_2[12];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_12_82_m_m_row_1_13_BI_ETC___d187 =
|
|
m_m_row_3[12];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_11_91_m_m_row_1_13_BI_ETC___d196 =
|
|
m_m_row_0[11];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_11_91_m_m_row_1_13_BI_ETC___d196 =
|
|
m_m_row_1[11];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_11_91_m_m_row_1_13_BI_ETC___d196 =
|
|
m_m_row_2[11];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_11_91_m_m_row_1_13_BI_ETC___d196 =
|
|
m_m_row_3[11];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BITS_10_TO_6_97_m_m_row_1_ETC___d202 =
|
|
m_m_row_0[10:6];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BITS_10_TO_6_97_m_m_row_1_ETC___d202 =
|
|
m_m_row_1[10:6];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BITS_10_TO_6_97_m_m_row_1_ETC___d202 =
|
|
m_m_row_2[10:6];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BITS_10_TO_6_97_m_m_row_1_ETC___d202 =
|
|
m_m_row_3[10:6];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BITS_5_TO_0_03_m_m_row_1__ETC___d208 =
|
|
m_m_row_0[5:0];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BITS_5_TO_0_03_m_m_row_1__ETC___d208 =
|
|
m_m_row_1[5:0];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BITS_5_TO_0_03_m_m_row_1__ETC___d208 =
|
|
m_m_row_2[5:0];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BITS_5_TO_0_03_m_m_row_1__ETC___d208 =
|
|
m_m_row_3[5:0];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_21_59_m_m_row_1_13_BI_ETC___d164 =
|
|
m_m_row_0[21];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_21_59_m_m_row_1_13_BI_ETC___d164 =
|
|
m_m_row_1[21];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_21_59_m_m_row_1_13_BI_ETC___d164 =
|
|
m_m_row_2[21];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_21_59_m_m_row_1_13_BI_ETC___d164 =
|
|
m_m_row_3[21];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BIT_27_21_m_m_row_1_13_BI_ETC___d126 =
|
|
m_m_row_0[27];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BIT_27_21_m_m_row_1_13_BI_ETC___d126 =
|
|
m_m_row_1[27];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BIT_27_21_m_m_row_1_13_BI_ETC___d126 =
|
|
m_m_row_2[27];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BIT_27_21_m_m_row_1_13_BI_ETC___d126 =
|
|
m_m_row_3[27];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or m_m_row_0 or m_m_row_1 or m_m_row_2 or m_m_row_3)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_row_0_11_BITS_30_TO_28_12_m_m_row__ETC___d120 =
|
|
m_m_row_0[30:28];
|
|
2'd1:
|
|
SEL_ARR_m_m_row_0_11_BITS_30_TO_28_12_m_m_row__ETC___d120 =
|
|
m_m_row_1[30:28];
|
|
2'd2:
|
|
SEL_ARR_m_m_row_0_11_BITS_30_TO_28_12_m_m_row__ETC___d120 =
|
|
m_m_row_2[30:28];
|
|
2'd3:
|
|
SEL_ARR_m_m_row_0_11_BITS_30_TO_28_12_m_m_row__ETC___d120 =
|
|
m_m_row_3[30:28];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP or
|
|
m_m_specBits_0_rl or
|
|
m_m_specBits_1_rl or m_m_specBits_2_rl or m_m_specBits_3_rl)
|
|
begin
|
|
case (m_m_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_m_specBits_0_rl_1_m_m_specBits_1_rl__ETC___d213 =
|
|
m_m_specBits_0_rl;
|
|
2'd1:
|
|
SEL_ARR_m_m_specBits_0_rl_1_m_m_specBits_1_rl__ETC___d213 =
|
|
m_m_specBits_1_rl;
|
|
2'd2:
|
|
SEL_ARR_m_m_specBits_0_rl_1_m_m_specBits_1_rl__ETC___d213 =
|
|
m_m_specBits_2_rl;
|
|
2'd3:
|
|
SEL_ARR_m_m_specBits_0_rl_1_m_m_specBits_1_rl__ETC___d213 =
|
|
m_m_specBits_3_rl;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_poisoned_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'bx /* unspecified value */ ;
|
|
m_m_poisoned_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'bx /* unspecified value */ ;
|
|
m_m_poisoned_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'bx /* unspecified value */ ;
|
|
m_m_poisoned_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'bx /* unspecified value */ ;
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_specBits_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_specBits_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_valid_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_valid_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_deqP$EN) m_m_deqP <= `BSV_ASSIGNMENT_DELAY m_m_deqP$D_IN;
|
|
if (m_m_enqP$EN) m_m_enqP <= `BSV_ASSIGNMENT_DELAY m_m_enqP$D_IN;
|
|
if (m_m_poisoned_0_rl$EN)
|
|
m_m_poisoned_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_poisoned_0_rl$D_IN;
|
|
if (m_m_poisoned_1_rl$EN)
|
|
m_m_poisoned_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_poisoned_1_rl$D_IN;
|
|
if (m_m_poisoned_2_rl$EN)
|
|
m_m_poisoned_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_poisoned_2_rl$D_IN;
|
|
if (m_m_poisoned_3_rl$EN)
|
|
m_m_poisoned_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_poisoned_3_rl$D_IN;
|
|
if (m_m_specBits_0_rl$EN)
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN;
|
|
if (m_m_specBits_1_rl$EN)
|
|
m_m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_1_rl$D_IN;
|
|
if (m_m_specBits_2_rl$EN)
|
|
m_m_specBits_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_2_rl$D_IN;
|
|
if (m_m_specBits_3_rl$EN)
|
|
m_m_specBits_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_3_rl$D_IN;
|
|
if (m_m_valid_0_rl$EN)
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN;
|
|
if (m_m_valid_1_rl$EN)
|
|
m_m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_1_rl$D_IN;
|
|
if (m_m_valid_2_rl$EN)
|
|
m_m_valid_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_2_rl$D_IN;
|
|
if (m_m_valid_3_rl$EN)
|
|
m_m_valid_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_3_rl$D_IN;
|
|
end
|
|
if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN;
|
|
if (m_m_row_1$EN) m_m_row_1 <= `BSV_ASSIGNMENT_DELAY m_m_row_1$D_IN;
|
|
if (m_m_row_2$EN) m_m_row_2 <= `BSV_ASSIGNMENT_DELAY m_m_row_2$D_IN;
|
|
if (m_m_row_3$EN) m_m_row_3 <= `BSV_ASSIGNMENT_DELAY m_m_row_3$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_deqP = 2'h2;
|
|
m_m_enqP = 2'h2;
|
|
m_m_poisoned_0_rl = 1'h0;
|
|
m_m_poisoned_1_rl = 1'h0;
|
|
m_m_poisoned_2_rl = 1'h0;
|
|
m_m_poisoned_3_rl = 1'h0;
|
|
m_m_row_0 = 31'h2AAAAAAA;
|
|
m_m_row_1 = 31'h2AAAAAAA;
|
|
m_m_row_2 = 31'h2AAAAAAA;
|
|
m_m_row_3 = 31'h2AAAAAAA;
|
|
m_m_specBits_0_rl = 12'hAAA;
|
|
m_m_specBits_1_rl = 12'hAAA;
|
|
m_m_specBits_2_rl = 12'hAAA;
|
|
m_m_specBits_3_rl = 12'hAAA;
|
|
m_m_valid_0_rl = 1'h0;
|
|
m_m_valid_1_rl = 1'h0;
|
|
m_m_valid_2_rl = 1'h0;
|
|
m_m_valid_3_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkFmaExecQ
|
|
|