2470 lines
100 KiB
Verilog
2470 lines
100 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:34:20 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// to_parent_rsToP_notEmpty O 1
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// RDY_to_parent_rsToP_notEmpty O 1 const
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// RDY_to_parent_rsToP_deq O 1
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// to_parent_rsToP_first O 583
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// RDY_to_parent_rsToP_first O 1
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// to_parent_rqToP_notEmpty O 1
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// RDY_to_parent_rqToP_notEmpty O 1 const
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// RDY_to_parent_rqToP_deq O 1
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// to_parent_rqToP_first O 72
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// RDY_to_parent_rqToP_first O 1
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// to_parent_fromP_notFull O 1
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// RDY_to_parent_fromP_notFull O 1 const
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// RDY_to_parent_fromP_enq O 1
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// RDY_to_proc_req_put O 1
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// to_proc_resp_get O 66
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// RDY_to_proc_resp_get O 1
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// cRqStuck_get O 68
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// RDY_cRqStuck_get O 1 const
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// pRqStuck_get O 68
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// RDY_pRqStuck_get O 1 const
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// RDY_flush O 1 const
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// flush_done O 1 const
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// RDY_flush_done O 1 const
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// RDY_setPerfStatus O 1 const
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// getPerfData O 64 const
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// RDY_getPerfData O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// to_parent_fromP_enq_x I 587
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// to_proc_req_put I 64
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// setPerfStatus_stats I 1 unused
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// getPerfData_t I 2 unused
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// EN_to_parent_rsToP_deq I 1
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// EN_to_parent_rqToP_deq I 1
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// EN_to_parent_fromP_enq I 1
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// EN_to_proc_req_put I 1
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// EN_flush I 1 unused
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// EN_setPerfStatus I 1 unused
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// EN_to_proc_resp_get I 1
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// EN_cRqStuck_get I 1 unused
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// EN_pRqStuck_get I 1 unused
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkIBankWrapper(CLK,
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RST_N,
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to_parent_rsToP_notEmpty,
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RDY_to_parent_rsToP_notEmpty,
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EN_to_parent_rsToP_deq,
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RDY_to_parent_rsToP_deq,
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to_parent_rsToP_first,
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RDY_to_parent_rsToP_first,
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to_parent_rqToP_notEmpty,
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RDY_to_parent_rqToP_notEmpty,
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EN_to_parent_rqToP_deq,
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RDY_to_parent_rqToP_deq,
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to_parent_rqToP_first,
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RDY_to_parent_rqToP_first,
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to_parent_fromP_notFull,
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RDY_to_parent_fromP_notFull,
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to_parent_fromP_enq_x,
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EN_to_parent_fromP_enq,
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RDY_to_parent_fromP_enq,
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to_proc_req_put,
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EN_to_proc_req_put,
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RDY_to_proc_req_put,
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EN_to_proc_resp_get,
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to_proc_resp_get,
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RDY_to_proc_resp_get,
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EN_cRqStuck_get,
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cRqStuck_get,
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RDY_cRqStuck_get,
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EN_pRqStuck_get,
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pRqStuck_get,
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RDY_pRqStuck_get,
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EN_flush,
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RDY_flush,
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flush_done,
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RDY_flush_done,
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setPerfStatus_stats,
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EN_setPerfStatus,
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RDY_setPerfStatus,
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getPerfData_t,
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getPerfData,
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RDY_getPerfData);
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input CLK;
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input RST_N;
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// value method to_parent_rsToP_notEmpty
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output to_parent_rsToP_notEmpty;
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output RDY_to_parent_rsToP_notEmpty;
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// action method to_parent_rsToP_deq
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input EN_to_parent_rsToP_deq;
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output RDY_to_parent_rsToP_deq;
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// value method to_parent_rsToP_first
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output [582 : 0] to_parent_rsToP_first;
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output RDY_to_parent_rsToP_first;
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// value method to_parent_rqToP_notEmpty
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output to_parent_rqToP_notEmpty;
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output RDY_to_parent_rqToP_notEmpty;
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// action method to_parent_rqToP_deq
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input EN_to_parent_rqToP_deq;
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output RDY_to_parent_rqToP_deq;
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// value method to_parent_rqToP_first
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output [71 : 0] to_parent_rqToP_first;
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output RDY_to_parent_rqToP_first;
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// value method to_parent_fromP_notFull
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output to_parent_fromP_notFull;
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output RDY_to_parent_fromP_notFull;
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// action method to_parent_fromP_enq
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input [586 : 0] to_parent_fromP_enq_x;
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input EN_to_parent_fromP_enq;
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output RDY_to_parent_fromP_enq;
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// action method to_proc_req_put
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input [63 : 0] to_proc_req_put;
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input EN_to_proc_req_put;
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output RDY_to_proc_req_put;
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// actionvalue method to_proc_resp_get
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input EN_to_proc_resp_get;
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output [65 : 0] to_proc_resp_get;
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output RDY_to_proc_resp_get;
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// actionvalue method cRqStuck_get
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input EN_cRqStuck_get;
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output [67 : 0] cRqStuck_get;
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output RDY_cRqStuck_get;
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// actionvalue method pRqStuck_get
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input EN_pRqStuck_get;
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output [67 : 0] pRqStuck_get;
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output RDY_pRqStuck_get;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// action method setPerfStatus
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input setPerfStatus_stats;
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input EN_setPerfStatus;
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output RDY_setPerfStatus;
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// value method getPerfData
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input [1 : 0] getPerfData_t;
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output [63 : 0] getPerfData;
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output RDY_getPerfData;
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// signals for module outputs
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wire [582 : 0] to_parent_rsToP_first;
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wire [71 : 0] to_parent_rqToP_first;
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wire [67 : 0] cRqStuck_get, pRqStuck_get;
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wire [65 : 0] to_proc_resp_get;
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wire [63 : 0] getPerfData;
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wire RDY_cRqStuck_get,
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RDY_flush,
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RDY_flush_done,
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RDY_getPerfData,
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RDY_pRqStuck_get,
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RDY_setPerfStatus,
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RDY_to_parent_fromP_enq,
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RDY_to_parent_fromP_notFull,
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RDY_to_parent_rqToP_deq,
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RDY_to_parent_rqToP_first,
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RDY_to_parent_rqToP_notEmpty,
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RDY_to_parent_rsToP_deq,
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RDY_to_parent_rsToP_first,
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RDY_to_parent_rsToP_notEmpty,
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RDY_to_proc_req_put,
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RDY_to_proc_resp_get,
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flush_done,
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to_parent_fromP_notFull,
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to_parent_rqToP_notEmpty,
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to_parent_rsToP_notEmpty;
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// inlined wires
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wire [587 : 0] m_fromPQ_enqReq_lat_0$wget, m_fromPQ_enqReq_lat_2$wget;
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wire [583 : 0] m_rsToPQ_enqReq_lat_0$wget, m_rsToPQ_enqReq_lat_2$wget;
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wire [72 : 0] m_rqToPQ_enqReq_lat_0$wget, m_rqToPQ_enqReq_lat_2$wget;
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wire m_fromPQ_deqReq_lat_0$whas, m_rsToPQ_enqReq_lat_0$whas;
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// register m_fromPQ_clearReq_rl
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reg m_fromPQ_clearReq_rl;
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wire m_fromPQ_clearReq_rl$D_IN, m_fromPQ_clearReq_rl$EN;
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// register m_fromPQ_data_0
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reg [586 : 0] m_fromPQ_data_0;
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wire [586 : 0] m_fromPQ_data_0$D_IN;
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wire m_fromPQ_data_0$EN;
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// register m_fromPQ_data_1
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reg [586 : 0] m_fromPQ_data_1;
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wire [586 : 0] m_fromPQ_data_1$D_IN;
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wire m_fromPQ_data_1$EN;
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// register m_fromPQ_deqP
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reg m_fromPQ_deqP;
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wire m_fromPQ_deqP$D_IN, m_fromPQ_deqP$EN;
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// register m_fromPQ_deqReq_rl
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reg m_fromPQ_deqReq_rl;
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wire m_fromPQ_deqReq_rl$D_IN, m_fromPQ_deqReq_rl$EN;
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// register m_fromPQ_empty
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reg m_fromPQ_empty;
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wire m_fromPQ_empty$D_IN, m_fromPQ_empty$EN;
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// register m_fromPQ_enqP
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reg m_fromPQ_enqP;
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wire m_fromPQ_enqP$D_IN, m_fromPQ_enqP$EN;
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// register m_fromPQ_enqReq_rl
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reg [587 : 0] m_fromPQ_enqReq_rl;
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wire [587 : 0] m_fromPQ_enqReq_rl$D_IN;
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wire m_fromPQ_enqReq_rl$EN;
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// register m_fromPQ_full
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reg m_fromPQ_full;
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wire m_fromPQ_full$D_IN, m_fromPQ_full$EN;
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// register m_rqFromCQ_data_0_rl
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reg [63 : 0] m_rqFromCQ_data_0_rl;
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wire [63 : 0] m_rqFromCQ_data_0_rl$D_IN;
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wire m_rqFromCQ_data_0_rl$EN;
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// register m_rqFromCQ_empty_rl
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reg m_rqFromCQ_empty_rl;
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wire m_rqFromCQ_empty_rl$D_IN, m_rqFromCQ_empty_rl$EN;
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// register m_rqFromCQ_full_rl
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reg m_rqFromCQ_full_rl;
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wire m_rqFromCQ_full_rl$D_IN, m_rqFromCQ_full_rl$EN;
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// register m_rqToPQ_clearReq_rl
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reg m_rqToPQ_clearReq_rl;
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wire m_rqToPQ_clearReq_rl$D_IN, m_rqToPQ_clearReq_rl$EN;
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// register m_rqToPQ_data_0
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reg [71 : 0] m_rqToPQ_data_0;
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wire [71 : 0] m_rqToPQ_data_0$D_IN;
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wire m_rqToPQ_data_0$EN;
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// register m_rqToPQ_data_1
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reg [71 : 0] m_rqToPQ_data_1;
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wire [71 : 0] m_rqToPQ_data_1$D_IN;
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wire m_rqToPQ_data_1$EN;
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// register m_rqToPQ_deqP
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reg m_rqToPQ_deqP;
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wire m_rqToPQ_deqP$D_IN, m_rqToPQ_deqP$EN;
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// register m_rqToPQ_deqReq_rl
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reg m_rqToPQ_deqReq_rl;
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wire m_rqToPQ_deqReq_rl$D_IN, m_rqToPQ_deqReq_rl$EN;
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// register m_rqToPQ_empty
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reg m_rqToPQ_empty;
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wire m_rqToPQ_empty$D_IN, m_rqToPQ_empty$EN;
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// register m_rqToPQ_enqP
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reg m_rqToPQ_enqP;
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wire m_rqToPQ_enqP$D_IN, m_rqToPQ_enqP$EN;
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// register m_rqToPQ_enqReq_rl
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reg [72 : 0] m_rqToPQ_enqReq_rl;
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wire [72 : 0] m_rqToPQ_enqReq_rl$D_IN;
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wire m_rqToPQ_enqReq_rl$EN;
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// register m_rqToPQ_full
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reg m_rqToPQ_full;
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wire m_rqToPQ_full$D_IN, m_rqToPQ_full$EN;
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// register m_rsToPQ_clearReq_rl
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reg m_rsToPQ_clearReq_rl;
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wire m_rsToPQ_clearReq_rl$D_IN, m_rsToPQ_clearReq_rl$EN;
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// register m_rsToPQ_data_0
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reg [582 : 0] m_rsToPQ_data_0;
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wire [582 : 0] m_rsToPQ_data_0$D_IN;
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wire m_rsToPQ_data_0$EN;
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// register m_rsToPQ_data_1
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reg [582 : 0] m_rsToPQ_data_1;
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wire [582 : 0] m_rsToPQ_data_1$D_IN;
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wire m_rsToPQ_data_1$EN;
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// register m_rsToPQ_deqP
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reg m_rsToPQ_deqP;
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wire m_rsToPQ_deqP$D_IN, m_rsToPQ_deqP$EN;
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// register m_rsToPQ_deqReq_rl
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reg m_rsToPQ_deqReq_rl;
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wire m_rsToPQ_deqReq_rl$D_IN, m_rsToPQ_deqReq_rl$EN;
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// register m_rsToPQ_empty
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reg m_rsToPQ_empty;
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wire m_rsToPQ_empty$D_IN, m_rsToPQ_empty$EN;
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// register m_rsToPQ_enqP
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reg m_rsToPQ_enqP;
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wire m_rsToPQ_enqP$D_IN, m_rsToPQ_enqP$EN;
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// register m_rsToPQ_enqReq_rl
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reg [583 : 0] m_rsToPQ_enqReq_rl;
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wire [583 : 0] m_rsToPQ_enqReq_rl$D_IN;
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wire m_rsToPQ_enqReq_rl$EN;
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// register m_rsToPQ_full
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reg m_rsToPQ_full;
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wire m_rsToPQ_full$D_IN, m_rsToPQ_full$EN;
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// ports of submodule m_cRqIndexQ
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wire [2 : 0] m_cRqIndexQ$D_IN, m_cRqIndexQ$D_OUT;
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wire m_cRqIndexQ$CLR,
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m_cRqIndexQ$DEQ,
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m_cRqIndexQ$EMPTY_N,
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m_cRqIndexQ$ENQ,
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m_cRqIndexQ$FULL_N;
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// ports of submodule m_cRqMshr
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wire [67 : 0] m_cRqMshr$stuck_get;
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wire [66 : 0] m_cRqMshr$sendRsToC_getResult;
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wire [65 : 0] m_cRqMshr$pipelineResp_setResult_r;
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wire [63 : 0] m_cRqMshr$getEmptyEntryInit_r,
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m_cRqMshr$pipelineResp_getRq,
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m_cRqMshr$pipelineResp_searchEndOfChain_addr,
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m_cRqMshr$sendRqToP_getRq,
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m_cRqMshr$sendRsToP_cRq_getRq;
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wire [55 : 0] m_cRqMshr$pipelineResp_setStateSlot_slot,
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m_cRqMshr$sendRqToP_getSlot,
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m_cRqMshr$sendRsToP_cRq_getSlot;
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wire [3 : 0] m_cRqMshr$pipelineResp_getSucc,
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m_cRqMshr$pipelineResp_searchEndOfChain,
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m_cRqMshr$pipelineResp_setSucc_succ;
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wire [2 : 0] m_cRqMshr$getEmptyEntryInit,
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m_cRqMshr$pipelineResp_getRq_n,
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m_cRqMshr$pipelineResp_getSlot_n,
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m_cRqMshr$pipelineResp_getState_n,
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m_cRqMshr$pipelineResp_getSucc_n,
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m_cRqMshr$pipelineResp_setResult_n,
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m_cRqMshr$pipelineResp_setStateSlot_n,
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m_cRqMshr$pipelineResp_setStateSlot_state,
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m_cRqMshr$pipelineResp_setSucc_n,
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m_cRqMshr$sendRqToP_getRq_n,
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m_cRqMshr$sendRqToP_getSlot_n,
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m_cRqMshr$sendRsToC_getResult_n,
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m_cRqMshr$sendRsToC_releaseEntry_n,
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m_cRqMshr$sendRsToP_cRq_getRq_n,
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m_cRqMshr$sendRsToP_cRq_getSlot_n;
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wire m_cRqMshr$EN_getEmptyEntryInit,
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m_cRqMshr$EN_pipelineResp_setResult,
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m_cRqMshr$EN_pipelineResp_setStateSlot,
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m_cRqMshr$EN_pipelineResp_setSucc,
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m_cRqMshr$EN_sendRsToC_releaseEntry,
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m_cRqMshr$EN_stuck_get,
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m_cRqMshr$RDY_getEmptyEntryInit,
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m_cRqMshr$RDY_sendRsToC_releaseEntry,
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m_cRqMshr$RDY_stuck_get;
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// ports of submodule m_pRqMshr
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wire [67 : 0] m_pRqMshr$stuck_get;
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wire [65 : 0] m_pRqMshr$getEmptyEntryInit_r, m_pRqMshr$sendRsToP_pRq_getRq;
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wire [1 : 0] m_pRqMshr$getEmptyEntryInit,
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m_pRqMshr$pipelineResp_getRq_n,
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m_pRqMshr$pipelineResp_releaseEntry_n,
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m_pRqMshr$pipelineResp_setDone_n,
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m_pRqMshr$sendRsToP_pRq_getRq_n,
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m_pRqMshr$sendRsToP_pRq_releaseEntry_n;
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wire m_pRqMshr$EN_getEmptyEntryInit,
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m_pRqMshr$EN_pipelineResp_releaseEntry,
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m_pRqMshr$EN_pipelineResp_setDone,
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m_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
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m_pRqMshr$EN_stuck_get,
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m_pRqMshr$RDY_getEmptyEntryInit,
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m_pRqMshr$RDY_pipelineResp_releaseEntry,
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m_pRqMshr$RDY_sendRsToP_pRq_releaseEntry,
|
|
m_pRqMshr$RDY_stuck_get;
|
|
|
|
// ports of submodule m_pipeline
|
|
reg [587 : 0] m_pipeline$send_r;
|
|
reg [573 : 0] m_pipeline$deqWrite_wrRam;
|
|
reg [3 : 0] m_pipeline$deqWrite_swapRq;
|
|
reg m_pipeline$deqWrite_updateRep;
|
|
wire [582 : 0] m_pipeline$first;
|
|
wire m_pipeline$EN_deqWrite,
|
|
m_pipeline$EN_send,
|
|
m_pipeline$RDY_deqWrite,
|
|
m_pipeline$RDY_first,
|
|
m_pipeline$RDY_send;
|
|
|
|
// ports of submodule m_rqToPIndexQ
|
|
wire [2 : 0] m_rqToPIndexQ$D_IN, m_rqToPIndexQ$D_OUT;
|
|
wire m_rqToPIndexQ$CLR,
|
|
m_rqToPIndexQ$DEQ,
|
|
m_rqToPIndexQ$EMPTY_N,
|
|
m_rqToPIndexQ$ENQ,
|
|
m_rqToPIndexQ$FULL_N;
|
|
|
|
// ports of submodule m_rqToPIndexQ_pipelineResp
|
|
wire [2 : 0] m_rqToPIndexQ_pipelineResp$D_IN,
|
|
m_rqToPIndexQ_pipelineResp$D_OUT;
|
|
wire m_rqToPIndexQ_pipelineResp$CLR,
|
|
m_rqToPIndexQ_pipelineResp$DEQ,
|
|
m_rqToPIndexQ_pipelineResp$EMPTY_N,
|
|
m_rqToPIndexQ_pipelineResp$ENQ,
|
|
m_rqToPIndexQ_pipelineResp$FULL_N;
|
|
|
|
// ports of submodule m_rqToPIndexQ_sendRsToP
|
|
wire [2 : 0] m_rqToPIndexQ_sendRsToP$D_IN, m_rqToPIndexQ_sendRsToP$D_OUT;
|
|
wire m_rqToPIndexQ_sendRsToP$CLR,
|
|
m_rqToPIndexQ_sendRsToP$DEQ,
|
|
m_rqToPIndexQ_sendRsToP$EMPTY_N,
|
|
m_rqToPIndexQ_sendRsToP$ENQ,
|
|
m_rqToPIndexQ_sendRsToP$FULL_N;
|
|
|
|
// ports of submodule m_rsToPIndexQ
|
|
wire [3 : 0] m_rsToPIndexQ$D_IN, m_rsToPIndexQ$D_OUT;
|
|
wire m_rsToPIndexQ$CLR,
|
|
m_rsToPIndexQ$DEQ,
|
|
m_rsToPIndexQ$EMPTY_N,
|
|
m_rsToPIndexQ$ENQ,
|
|
m_rsToPIndexQ$FULL_N;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_cRqTransfer,
|
|
CAN_FIRE_RL_m_fromPQ_canonicalize,
|
|
CAN_FIRE_RL_m_fromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_fromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_fromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_pRqTransfer,
|
|
CAN_FIRE_RL_m_pRsTransfer,
|
|
CAN_FIRE_RL_m_pipelineResp_cRq,
|
|
CAN_FIRE_RL_m_pipelineResp_pRq,
|
|
CAN_FIRE_RL_m_pipelineResp_pRs,
|
|
CAN_FIRE_RL_m_rqFromCQ_data_0_canon,
|
|
CAN_FIRE_RL_m_rqFromCQ_empty_canon,
|
|
CAN_FIRE_RL_m_rqFromCQ_full_canon,
|
|
CAN_FIRE_RL_m_rqIndexFromPipelineResp,
|
|
CAN_FIRE_RL_m_rqIndexFromSendRsToP,
|
|
CAN_FIRE_RL_m_rqToPQ_canonicalize,
|
|
CAN_FIRE_RL_m_rqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_rqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_rqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_rsToPQ_canonicalize,
|
|
CAN_FIRE_RL_m_rsToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_rsToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_rsToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_sendRqToP,
|
|
CAN_FIRE_RL_m_sendRsToP_cRq,
|
|
CAN_FIRE_RL_m_sendRsToP_pRq,
|
|
CAN_FIRE_cRqStuck_get,
|
|
CAN_FIRE_flush,
|
|
CAN_FIRE_pRqStuck_get,
|
|
CAN_FIRE_setPerfStatus,
|
|
CAN_FIRE_to_parent_fromP_enq,
|
|
CAN_FIRE_to_parent_rqToP_deq,
|
|
CAN_FIRE_to_parent_rsToP_deq,
|
|
CAN_FIRE_to_proc_req_put,
|
|
CAN_FIRE_to_proc_resp_get,
|
|
WILL_FIRE_RL_m_cRqTransfer,
|
|
WILL_FIRE_RL_m_fromPQ_canonicalize,
|
|
WILL_FIRE_RL_m_fromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_fromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_fromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_pRqTransfer,
|
|
WILL_FIRE_RL_m_pRsTransfer,
|
|
WILL_FIRE_RL_m_pipelineResp_cRq,
|
|
WILL_FIRE_RL_m_pipelineResp_pRq,
|
|
WILL_FIRE_RL_m_pipelineResp_pRs,
|
|
WILL_FIRE_RL_m_rqFromCQ_data_0_canon,
|
|
WILL_FIRE_RL_m_rqFromCQ_empty_canon,
|
|
WILL_FIRE_RL_m_rqFromCQ_full_canon,
|
|
WILL_FIRE_RL_m_rqIndexFromPipelineResp,
|
|
WILL_FIRE_RL_m_rqIndexFromSendRsToP,
|
|
WILL_FIRE_RL_m_rqToPQ_canonicalize,
|
|
WILL_FIRE_RL_m_rqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_rqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_rqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_rsToPQ_canonicalize,
|
|
WILL_FIRE_RL_m_rsToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_rsToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_rsToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_sendRqToP,
|
|
WILL_FIRE_RL_m_sendRsToP_cRq,
|
|
WILL_FIRE_RL_m_sendRsToP_pRq,
|
|
WILL_FIRE_cRqStuck_get,
|
|
WILL_FIRE_flush,
|
|
WILL_FIRE_pRqStuck_get,
|
|
WILL_FIRE_setPerfStatus,
|
|
WILL_FIRE_to_parent_fromP_enq,
|
|
WILL_FIRE_to_parent_rqToP_deq,
|
|
WILL_FIRE_to_parent_rsToP_deq,
|
|
WILL_FIRE_to_proc_req_put,
|
|
WILL_FIRE_to_proc_resp_get;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [587 : 0] MUX_m_pipeline$send_1__VAL_1,
|
|
MUX_m_pipeline$send_1__VAL_2,
|
|
MUX_m_pipeline$send_1__VAL_3;
|
|
wire [583 : 0] MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
|
|
wire [573 : 0] MUX_m_pipeline$deqWrite_2__VAL_1,
|
|
MUX_m_pipeline$deqWrite_2__VAL_2,
|
|
MUX_m_pipeline$deqWrite_2__VAL_3;
|
|
wire [65 : 0] MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1;
|
|
wire [55 : 0] MUX_m_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
|
|
wire [3 : 0] MUX_m_pipeline$deqWrite_1__VAL_2,
|
|
MUX_m_pipeline$deqWrite_1__VAL_3,
|
|
MUX_m_rsToPIndexQ$enq_1__VAL_1,
|
|
MUX_m_rsToPIndexQ$enq_1__VAL_2;
|
|
wire [2 : 0] MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2;
|
|
wire MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1,
|
|
MUX_m_pipeline$deqWrite_3__VAL_2,
|
|
MUX_m_rsToPIndexQ$enq_1__SEL_1,
|
|
MUX_m_rsToPIndexQ$enq_1__SEL_2;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_130__ETC__q20,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_194__ETC__q18,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_258__ETC__q17,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_322__ETC__q16,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_386__ETC__q15,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_450__ETC__q14,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_514__ETC__q13,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_66_T_ETC__q21,
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_71_T_ETC__q32,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_127__ETC__q23,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_191__ETC__q12,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_255__ETC__q11,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_319__ETC__q10,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_383__ETC__q9,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_447__ETC__q8,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_511__ETC__q7,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_582__ETC__q25,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_63_T_ETC__q24,
|
|
SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425,
|
|
addr__h42425;
|
|
reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37,
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36;
|
|
reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31,
|
|
x__h45568;
|
|
reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38,
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_5_TO_ETC__q29,
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_7_TO_ETC__q33,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_518__ETC__q26;
|
|
reg CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q28,
|
|
CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q34,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_515_1_ETC__q19,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_516_1_ETC__q6,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_517_1_ETC__q5,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_518_1_ETC__q4,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_586_1_ETC__q35,
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BIT_3_1_m_ETC__q30,
|
|
CASE_m_rsToPQ_deqP_0_NOT_m_rsToPQ_data_0_BIT_5_ETC__q27,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_512_1_ETC__q22,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_513_1_ETC__q3,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_514_1_ETC__q2,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_515_1_ETC__q1;
|
|
wire [585 : 0] IF_IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fr_ETC___d392;
|
|
wire [521 : 0] _1_CONCAT_NOT_SEL_ARR_NOT_m_fromPQ_data_0_13_BI_ETC___d509;
|
|
wire [515 : 0] SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d502,
|
|
SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d780;
|
|
wire [383 : 0] SEL_ARR_m_fromPQ_data_0_13_BITS_514_TO_451_66__ETC___d492,
|
|
SEL_ARR_m_rsToPQ_data_0_10_BITS_511_TO_448_44__ETC___d770;
|
|
wire [63 : 0] resp_addr__h45726, v__h41294, x_addr__h10523;
|
|
wire [57 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d602,
|
|
IF_m_pipeline_first__47_BITS_518_TO_516_52_EQ__ETC___d595;
|
|
wire [5 : 0] IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d600,
|
|
SEL_ARR_m_rqToPQ_data_0_84_BITS_5_TO_4_94_m_rq_ETC___d806;
|
|
wire [3 : 0] sel__h51068;
|
|
wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d615,
|
|
SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461,
|
|
SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d739,
|
|
x__h35816;
|
|
wire IF_IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fr_ETC___d360,
|
|
IF_IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fr_ETC___d369,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d213,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d222,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d227,
|
|
IF_IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsT_ETC___d121,
|
|
IF_IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsT_ETC___d130,
|
|
IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fromP_ETC___d336,
|
|
IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_NOT_m_f_ETC___d255,
|
|
IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fromP_ETC___d248,
|
|
IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d568,
|
|
IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rqToP_ETC___d189,
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__54_THEN_m_rqToP_ETC___d163,
|
|
IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d97,
|
|
IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_NOT_m_rs_ETC___d47,
|
|
IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40,
|
|
_theResult_____2__h19024,
|
|
_theResult_____2__h22970,
|
|
_theResult_____2__h40286,
|
|
m_pipeline_RDY_deqWrite__46_AND_IF_m_pipeline__ETC___d690,
|
|
m_pipeline_first__47_BITS_518_TO_516_52_EQ_m_p_ETC___d574,
|
|
m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562,
|
|
m_pipeline_first__47_BIT_519_48_AND_m_pipeline_ETC___d631,
|
|
next_deqP___1__h19213,
|
|
next_deqP___1__h23159,
|
|
next_deqP___1__h40475,
|
|
v__h10212,
|
|
v__h10363,
|
|
v__h22346,
|
|
v__h22497,
|
|
v__h31140,
|
|
v__h31291;
|
|
|
|
// value method to_parent_rsToP_notEmpty
|
|
assign to_parent_rsToP_notEmpty = !m_rsToPQ_empty ;
|
|
assign RDY_to_parent_rsToP_notEmpty = 1'd1 ;
|
|
|
|
// action method to_parent_rsToP_deq
|
|
assign RDY_to_parent_rsToP_deq = !m_rsToPQ_empty ;
|
|
assign CAN_FIRE_to_parent_rsToP_deq = !m_rsToPQ_empty ;
|
|
assign WILL_FIRE_to_parent_rsToP_deq = EN_to_parent_rsToP_deq ;
|
|
|
|
// value method to_parent_rsToP_first
|
|
assign to_parent_rsToP_first =
|
|
{ CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_582__ETC__q25,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_518__ETC__q26,
|
|
!CASE_m_rsToPQ_deqP_0_NOT_m_rsToPQ_data_0_BIT_5_ETC__q27,
|
|
SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d780 } ;
|
|
assign RDY_to_parent_rsToP_first = !m_rsToPQ_empty ;
|
|
|
|
// value method to_parent_rqToP_notEmpty
|
|
assign to_parent_rqToP_notEmpty = !m_rqToPQ_empty ;
|
|
assign RDY_to_parent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method to_parent_rqToP_deq
|
|
assign RDY_to_parent_rqToP_deq = !m_rqToPQ_empty ;
|
|
assign CAN_FIRE_to_parent_rqToP_deq = !m_rqToPQ_empty ;
|
|
assign WILL_FIRE_to_parent_rqToP_deq = EN_to_parent_rqToP_deq ;
|
|
|
|
// value method to_parent_rqToP_first
|
|
assign to_parent_rqToP_first =
|
|
{ CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_71_T_ETC__q32,
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_7_TO_ETC__q33,
|
|
SEL_ARR_m_rqToPQ_data_0_84_BITS_5_TO_4_94_m_rq_ETC___d806 } ;
|
|
assign RDY_to_parent_rqToP_first = !m_rqToPQ_empty ;
|
|
|
|
// value method to_parent_fromP_notFull
|
|
assign to_parent_fromP_notFull = !m_fromPQ_full ;
|
|
assign RDY_to_parent_fromP_notFull = 1'd1 ;
|
|
|
|
// action method to_parent_fromP_enq
|
|
assign RDY_to_parent_fromP_enq = !m_fromPQ_full ;
|
|
assign CAN_FIRE_to_parent_fromP_enq = !m_fromPQ_full ;
|
|
assign WILL_FIRE_to_parent_fromP_enq = EN_to_parent_fromP_enq ;
|
|
|
|
// action method to_proc_req_put
|
|
assign RDY_to_proc_req_put = !m_rqFromCQ_full_rl ;
|
|
assign CAN_FIRE_to_proc_req_put = !m_rqFromCQ_full_rl ;
|
|
assign WILL_FIRE_to_proc_req_put = EN_to_proc_req_put ;
|
|
|
|
// actionvalue method to_proc_resp_get
|
|
assign to_proc_resp_get = m_cRqMshr$sendRsToC_getResult[65:0] ;
|
|
assign RDY_to_proc_resp_get =
|
|
m_cRqIndexQ$EMPTY_N && m_cRqMshr$sendRsToC_getResult[66] &&
|
|
m_cRqMshr$RDY_sendRsToC_releaseEntry ;
|
|
assign CAN_FIRE_to_proc_resp_get =
|
|
m_cRqIndexQ$EMPTY_N && m_cRqMshr$sendRsToC_getResult[66] &&
|
|
m_cRqMshr$RDY_sendRsToC_releaseEntry ;
|
|
assign WILL_FIRE_to_proc_resp_get = EN_to_proc_resp_get ;
|
|
|
|
// actionvalue method cRqStuck_get
|
|
assign cRqStuck_get = m_cRqMshr$stuck_get ;
|
|
assign RDY_cRqStuck_get = m_cRqMshr$RDY_stuck_get ;
|
|
assign CAN_FIRE_cRqStuck_get = m_cRqMshr$RDY_stuck_get ;
|
|
assign WILL_FIRE_cRqStuck_get = EN_cRqStuck_get ;
|
|
|
|
// actionvalue method pRqStuck_get
|
|
assign pRqStuck_get = m_pRqMshr$stuck_get ;
|
|
assign RDY_pRqStuck_get = m_pRqMshr$RDY_stuck_get ;
|
|
assign CAN_FIRE_pRqStuck_get = m_pRqMshr$RDY_stuck_get ;
|
|
assign WILL_FIRE_pRqStuck_get = EN_pRqStuck_get ;
|
|
|
|
// action method flush
|
|
assign RDY_flush = 1'd1 ;
|
|
assign CAN_FIRE_flush = 1'd1 ;
|
|
assign WILL_FIRE_flush = EN_flush ;
|
|
|
|
// value method flush_done
|
|
assign flush_done = 1'd1 ;
|
|
assign RDY_flush_done = 1'd1 ;
|
|
|
|
// action method setPerfStatus
|
|
assign RDY_setPerfStatus = 1'd1 ;
|
|
assign CAN_FIRE_setPerfStatus = 1'd1 ;
|
|
assign WILL_FIRE_setPerfStatus = EN_setPerfStatus ;
|
|
|
|
// value method getPerfData
|
|
assign getPerfData = 64'd0 ;
|
|
assign RDY_getPerfData = 1'd1 ;
|
|
|
|
// submodule m_cRqIndexQ
|
|
SizedFIFO #(.p1width(32'd3),
|
|
.p2depth(32'd8),
|
|
.p3cntr_width(32'd3),
|
|
.guarded(32'd1)) m_cRqIndexQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_cRqIndexQ$D_IN),
|
|
.ENQ(m_cRqIndexQ$ENQ),
|
|
.DEQ(m_cRqIndexQ$DEQ),
|
|
.CLR(m_cRqIndexQ$CLR),
|
|
.D_OUT(m_cRqIndexQ$D_OUT),
|
|
.FULL_N(m_cRqIndexQ$FULL_N),
|
|
.EMPTY_N(m_cRqIndexQ$EMPTY_N));
|
|
|
|
// submodule m_cRqMshr
|
|
mkICRqMshrWrapper m_cRqMshr(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.getEmptyEntryInit_r(m_cRqMshr$getEmptyEntryInit_r),
|
|
.pipelineResp_getRq_n(m_cRqMshr$pipelineResp_getRq_n),
|
|
.pipelineResp_getSlot_n(m_cRqMshr$pipelineResp_getSlot_n),
|
|
.pipelineResp_getState_n(m_cRqMshr$pipelineResp_getState_n),
|
|
.pipelineResp_getSucc_n(m_cRqMshr$pipelineResp_getSucc_n),
|
|
.pipelineResp_searchEndOfChain_addr(m_cRqMshr$pipelineResp_searchEndOfChain_addr),
|
|
.pipelineResp_setResult_n(m_cRqMshr$pipelineResp_setResult_n),
|
|
.pipelineResp_setResult_r(m_cRqMshr$pipelineResp_setResult_r),
|
|
.pipelineResp_setStateSlot_n(m_cRqMshr$pipelineResp_setStateSlot_n),
|
|
.pipelineResp_setStateSlot_slot(m_cRqMshr$pipelineResp_setStateSlot_slot),
|
|
.pipelineResp_setStateSlot_state(m_cRqMshr$pipelineResp_setStateSlot_state),
|
|
.pipelineResp_setSucc_n(m_cRqMshr$pipelineResp_setSucc_n),
|
|
.pipelineResp_setSucc_succ(m_cRqMshr$pipelineResp_setSucc_succ),
|
|
.sendRqToP_getRq_n(m_cRqMshr$sendRqToP_getRq_n),
|
|
.sendRqToP_getSlot_n(m_cRqMshr$sendRqToP_getSlot_n),
|
|
.sendRsToC_getResult_n(m_cRqMshr$sendRsToC_getResult_n),
|
|
.sendRsToC_releaseEntry_n(m_cRqMshr$sendRsToC_releaseEntry_n),
|
|
.sendRsToP_cRq_getRq_n(m_cRqMshr$sendRsToP_cRq_getRq_n),
|
|
.sendRsToP_cRq_getSlot_n(m_cRqMshr$sendRsToP_cRq_getSlot_n),
|
|
.EN_getEmptyEntryInit(m_cRqMshr$EN_getEmptyEntryInit),
|
|
.EN_sendRsToC_releaseEntry(m_cRqMshr$EN_sendRsToC_releaseEntry),
|
|
.EN_pipelineResp_setResult(m_cRqMshr$EN_pipelineResp_setResult),
|
|
.EN_pipelineResp_setStateSlot(m_cRqMshr$EN_pipelineResp_setStateSlot),
|
|
.EN_pipelineResp_setSucc(m_cRqMshr$EN_pipelineResp_setSucc),
|
|
.EN_stuck_get(m_cRqMshr$EN_stuck_get),
|
|
.getEmptyEntryInit(m_cRqMshr$getEmptyEntryInit),
|
|
.RDY_getEmptyEntryInit(m_cRqMshr$RDY_getEmptyEntryInit),
|
|
.RDY_sendRsToC_releaseEntry(m_cRqMshr$RDY_sendRsToC_releaseEntry),
|
|
.sendRsToC_getResult(m_cRqMshr$sendRsToC_getResult),
|
|
.RDY_sendRsToC_getResult(),
|
|
.sendRsToP_cRq_getRq(m_cRqMshr$sendRsToP_cRq_getRq),
|
|
.RDY_sendRsToP_cRq_getRq(),
|
|
.sendRsToP_cRq_getSlot(m_cRqMshr$sendRsToP_cRq_getSlot),
|
|
.RDY_sendRsToP_cRq_getSlot(),
|
|
.sendRqToP_getRq(m_cRqMshr$sendRqToP_getRq),
|
|
.RDY_sendRqToP_getRq(),
|
|
.sendRqToP_getSlot(m_cRqMshr$sendRqToP_getSlot),
|
|
.RDY_sendRqToP_getSlot(),
|
|
.pipelineResp_getState(),
|
|
.RDY_pipelineResp_getState(),
|
|
.pipelineResp_getRq(m_cRqMshr$pipelineResp_getRq),
|
|
.RDY_pipelineResp_getRq(),
|
|
.pipelineResp_getSlot(),
|
|
.RDY_pipelineResp_getSlot(),
|
|
.RDY_pipelineResp_setResult(),
|
|
.RDY_pipelineResp_setStateSlot(),
|
|
.pipelineResp_getSucc(m_cRqMshr$pipelineResp_getSucc),
|
|
.RDY_pipelineResp_getSucc(),
|
|
.RDY_pipelineResp_setSucc(),
|
|
.pipelineResp_searchEndOfChain(m_cRqMshr$pipelineResp_searchEndOfChain),
|
|
.RDY_pipelineResp_searchEndOfChain(),
|
|
.emptyForFlush(),
|
|
.RDY_emptyForFlush(),
|
|
.stuck_get(m_cRqMshr$stuck_get),
|
|
.RDY_stuck_get(m_cRqMshr$RDY_stuck_get));
|
|
|
|
// submodule m_pRqMshr
|
|
mkIPRqMshrWrapper m_pRqMshr(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.getEmptyEntryInit_r(m_pRqMshr$getEmptyEntryInit_r),
|
|
.pipelineResp_getRq_n(m_pRqMshr$pipelineResp_getRq_n),
|
|
.pipelineResp_releaseEntry_n(m_pRqMshr$pipelineResp_releaseEntry_n),
|
|
.pipelineResp_setDone_n(m_pRqMshr$pipelineResp_setDone_n),
|
|
.sendRsToP_pRq_getRq_n(m_pRqMshr$sendRsToP_pRq_getRq_n),
|
|
.sendRsToP_pRq_releaseEntry_n(m_pRqMshr$sendRsToP_pRq_releaseEntry_n),
|
|
.EN_getEmptyEntryInit(m_pRqMshr$EN_getEmptyEntryInit),
|
|
.EN_sendRsToP_pRq_releaseEntry(m_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
|
|
.EN_pipelineResp_releaseEntry(m_pRqMshr$EN_pipelineResp_releaseEntry),
|
|
.EN_pipelineResp_setDone(m_pRqMshr$EN_pipelineResp_setDone),
|
|
.EN_stuck_get(m_pRqMshr$EN_stuck_get),
|
|
.getEmptyEntryInit(m_pRqMshr$getEmptyEntryInit),
|
|
.RDY_getEmptyEntryInit(m_pRqMshr$RDY_getEmptyEntryInit),
|
|
.sendRsToP_pRq_getRq(m_pRqMshr$sendRsToP_pRq_getRq),
|
|
.RDY_sendRsToP_pRq_getRq(),
|
|
.RDY_sendRsToP_pRq_releaseEntry(m_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
|
|
.pipelineResp_getRq(),
|
|
.RDY_pipelineResp_getRq(),
|
|
.RDY_pipelineResp_releaseEntry(m_pRqMshr$RDY_pipelineResp_releaseEntry),
|
|
.RDY_pipelineResp_setDone(),
|
|
.stuck_get(m_pRqMshr$stuck_get),
|
|
.RDY_stuck_get(m_pRqMshr$RDY_stuck_get));
|
|
|
|
// submodule m_pipeline
|
|
mkIPipeline m_pipeline(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.deqWrite_swapRq(m_pipeline$deqWrite_swapRq),
|
|
.deqWrite_updateRep(m_pipeline$deqWrite_updateRep),
|
|
.deqWrite_wrRam(m_pipeline$deqWrite_wrRam),
|
|
.send_r(m_pipeline$send_r),
|
|
.EN_send(m_pipeline$EN_send),
|
|
.EN_deqWrite(m_pipeline$EN_deqWrite),
|
|
.RDY_send(m_pipeline$RDY_send),
|
|
.first(m_pipeline$first),
|
|
.RDY_first(m_pipeline$RDY_first),
|
|
.RDY_deqWrite(m_pipeline$RDY_deqWrite));
|
|
|
|
// submodule m_rqToPIndexQ
|
|
SizedFIFO #(.p1width(32'd3),
|
|
.p2depth(32'd8),
|
|
.p3cntr_width(32'd3),
|
|
.guarded(32'd1)) m_rqToPIndexQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_rqToPIndexQ$D_IN),
|
|
.ENQ(m_rqToPIndexQ$ENQ),
|
|
.DEQ(m_rqToPIndexQ$DEQ),
|
|
.CLR(m_rqToPIndexQ$CLR),
|
|
.D_OUT(m_rqToPIndexQ$D_OUT),
|
|
.FULL_N(m_rqToPIndexQ$FULL_N),
|
|
.EMPTY_N(m_rqToPIndexQ$EMPTY_N));
|
|
|
|
// submodule m_rqToPIndexQ_pipelineResp
|
|
FIFO2 #(.width(32'd3),
|
|
.guarded(32'd1)) m_rqToPIndexQ_pipelineResp(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_rqToPIndexQ_pipelineResp$D_IN),
|
|
.ENQ(m_rqToPIndexQ_pipelineResp$ENQ),
|
|
.DEQ(m_rqToPIndexQ_pipelineResp$DEQ),
|
|
.CLR(m_rqToPIndexQ_pipelineResp$CLR),
|
|
.D_OUT(m_rqToPIndexQ_pipelineResp$D_OUT),
|
|
.FULL_N(m_rqToPIndexQ_pipelineResp$FULL_N),
|
|
.EMPTY_N(m_rqToPIndexQ_pipelineResp$EMPTY_N));
|
|
|
|
// submodule m_rqToPIndexQ_sendRsToP
|
|
FIFO2 #(.width(32'd3), .guarded(32'd1)) m_rqToPIndexQ_sendRsToP(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_rqToPIndexQ_sendRsToP$D_IN),
|
|
.ENQ(m_rqToPIndexQ_sendRsToP$ENQ),
|
|
.DEQ(m_rqToPIndexQ_sendRsToP$DEQ),
|
|
.CLR(m_rqToPIndexQ_sendRsToP$CLR),
|
|
.D_OUT(m_rqToPIndexQ_sendRsToP$D_OUT),
|
|
.FULL_N(m_rqToPIndexQ_sendRsToP$FULL_N),
|
|
.EMPTY_N(m_rqToPIndexQ_sendRsToP$EMPTY_N));
|
|
|
|
// submodule m_rsToPIndexQ
|
|
SizedFIFO #(.p1width(32'd4),
|
|
.p2depth(32'd12),
|
|
.p3cntr_width(32'd4),
|
|
.guarded(32'd1)) m_rsToPIndexQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_rsToPIndexQ$D_IN),
|
|
.ENQ(m_rsToPIndexQ$ENQ),
|
|
.DEQ(m_rsToPIndexQ$DEQ),
|
|
.CLR(m_rsToPIndexQ$CLR),
|
|
.D_OUT(m_rsToPIndexQ$D_OUT),
|
|
.FULL_N(m_rsToPIndexQ$FULL_N),
|
|
.EMPTY_N(m_rsToPIndexQ$EMPTY_N));
|
|
|
|
// rule RL_m_sendRsToP_cRq
|
|
assign CAN_FIRE_RL_m_sendRsToP_cRq =
|
|
!m_rsToPQ_full && m_rsToPIndexQ$EMPTY_N &&
|
|
m_rqToPIndexQ_sendRsToP$FULL_N &&
|
|
!m_rsToPIndexQ$D_OUT[3] ;
|
|
assign WILL_FIRE_RL_m_sendRsToP_cRq = CAN_FIRE_RL_m_sendRsToP_cRq ;
|
|
|
|
// rule RL_m_sendRsToP_pRq
|
|
assign CAN_FIRE_RL_m_sendRsToP_pRq =
|
|
!m_rsToPQ_full && m_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
|
|
m_rsToPIndexQ$EMPTY_N &&
|
|
m_rsToPIndexQ$D_OUT[3] ;
|
|
assign WILL_FIRE_RL_m_sendRsToP_pRq = CAN_FIRE_RL_m_sendRsToP_pRq ;
|
|
|
|
// rule RL_m_sendRqToP
|
|
assign CAN_FIRE_RL_m_sendRqToP = !m_rqToPQ_full && m_rqToPIndexQ$EMPTY_N ;
|
|
assign WILL_FIRE_RL_m_sendRqToP = CAN_FIRE_RL_m_sendRqToP ;
|
|
|
|
// rule RL_m_pipelineResp_cRq
|
|
assign CAN_FIRE_RL_m_pipelineResp_cRq =
|
|
m_pipeline$RDY_first && m_pipeline$RDY_deqWrite &&
|
|
(m_pipeline$first[519] ||
|
|
m_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d568) &&
|
|
m_pipeline$first[582:581] == 2'd0 ;
|
|
assign WILL_FIRE_RL_m_pipelineResp_cRq = CAN_FIRE_RL_m_pipelineResp_cRq ;
|
|
|
|
// rule RL_m_pipelineResp_pRs
|
|
assign CAN_FIRE_RL_m_pipelineResp_pRs =
|
|
m_pipeline$RDY_first &&
|
|
(!m_pipeline$first[519] || m_pipeline$RDY_deqWrite) &&
|
|
m_pipeline$first[582:581] != 2'd0 &&
|
|
m_pipeline$first[582:581] != 2'd1 ;
|
|
assign WILL_FIRE_RL_m_pipelineResp_pRs = CAN_FIRE_RL_m_pipelineResp_pRs ;
|
|
|
|
// rule RL_m_pipelineResp_pRq
|
|
assign CAN_FIRE_RL_m_pipelineResp_pRq =
|
|
m_pipeline$RDY_first &&
|
|
m_pipeline_RDY_deqWrite__46_AND_IF_m_pipeline__ETC___d690 &&
|
|
m_pipeline$first[582:581] == 2'd1 ;
|
|
assign WILL_FIRE_RL_m_pipelineResp_pRq = CAN_FIRE_RL_m_pipelineResp_pRq ;
|
|
|
|
// rule RL_m_pRqTransfer
|
|
assign CAN_FIRE_RL_m_pRqTransfer =
|
|
!m_fromPQ_empty && m_pipeline$RDY_send &&
|
|
m_pRqMshr$RDY_getEmptyEntryInit &&
|
|
CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q34 ;
|
|
assign WILL_FIRE_RL_m_pRqTransfer = CAN_FIRE_RL_m_pRqTransfer ;
|
|
|
|
// rule RL_m_cRqTransfer
|
|
assign CAN_FIRE_RL_m_cRqTransfer =
|
|
(EN_to_proc_req_put || !m_rqFromCQ_empty_rl) &&
|
|
m_pipeline$RDY_send &&
|
|
m_cRqMshr$RDY_getEmptyEntryInit &&
|
|
m_cRqIndexQ$FULL_N ;
|
|
assign WILL_FIRE_RL_m_cRqTransfer =
|
|
CAN_FIRE_RL_m_cRqTransfer && !WILL_FIRE_RL_m_pRsTransfer &&
|
|
!WILL_FIRE_RL_m_pRqTransfer ;
|
|
|
|
// rule RL_m_pRsTransfer
|
|
assign CAN_FIRE_RL_m_pRsTransfer =
|
|
!m_fromPQ_empty && m_pipeline$RDY_send &&
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_586_1_ETC__q35 ;
|
|
assign WILL_FIRE_RL_m_pRsTransfer = CAN_FIRE_RL_m_pRsTransfer ;
|
|
|
|
// rule RL_m_rqIndexFromPipelineResp
|
|
assign CAN_FIRE_RL_m_rqIndexFromPipelineResp =
|
|
m_rqToPIndexQ_pipelineResp$EMPTY_N && m_rqToPIndexQ$FULL_N ;
|
|
assign WILL_FIRE_RL_m_rqIndexFromPipelineResp =
|
|
CAN_FIRE_RL_m_rqIndexFromPipelineResp ;
|
|
|
|
// rule RL_m_rqIndexFromSendRsToP
|
|
assign CAN_FIRE_RL_m_rqIndexFromSendRsToP =
|
|
m_rqToPIndexQ$FULL_N && m_rqToPIndexQ_sendRsToP$EMPTY_N ;
|
|
assign WILL_FIRE_RL_m_rqIndexFromSendRsToP =
|
|
CAN_FIRE_RL_m_rqIndexFromSendRsToP &&
|
|
!WILL_FIRE_RL_m_rqIndexFromPipelineResp ;
|
|
|
|
// rule RL_m_rqFromCQ_data_0_canon
|
|
assign CAN_FIRE_RL_m_rqFromCQ_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqFromCQ_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqFromCQ_empty_canon
|
|
assign CAN_FIRE_RL_m_rqFromCQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqFromCQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqFromCQ_full_canon
|
|
assign CAN_FIRE_RL_m_rqFromCQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqFromCQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rsToPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_rsToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rsToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_rsToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_rsToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rsToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rsToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_rsToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rsToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rsToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_rsToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rsToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_fromPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_fromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_fromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_fromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_fromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_fromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_fromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_fromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_fromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_fromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_fromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_fromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 =
|
|
WILL_FIRE_RL_m_pipelineResp_pRs && m_pipeline$first[519] ;
|
|
assign MUX_m_rsToPIndexQ$enq_1__SEL_1 =
|
|
WILL_FIRE_RL_m_pipelineResp_cRq && !m_pipeline$first[519] &&
|
|
!m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
m_pipeline$first[521:520] != 2'd0 &&
|
|
!m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562 ;
|
|
assign MUX_m_rsToPIndexQ$enq_1__SEL_2 =
|
|
WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[574] ;
|
|
assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 =
|
|
{ 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0,
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36,
|
|
1'd1,
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 } ;
|
|
assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 =
|
|
m_pipeline$first[519] ?
|
|
(m_pipeline_first__47_BITS_518_TO_516_52_EQ_m_p_ETC___d574 ?
|
|
3'd3 :
|
|
3'd4) :
|
|
IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d615 ;
|
|
assign MUX_m_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
|
|
m_pipeline$first[519] ?
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 } :
|
|
(m_cRqMshr$pipelineResp_searchEndOfChain[3] ?
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 } :
|
|
((m_pipeline$first[521:520] == 2'd0 ||
|
|
m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562) ?
|
|
{ m_pipeline$first[577:575],
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd1 } :
|
|
{ m_pipeline$first[577:575],
|
|
m_pipeline$first[573:522],
|
|
1'd1 })) ;
|
|
assign MUX_m_pipeline$deqWrite_1__VAL_2 =
|
|
m_pipeline$first[519] ?
|
|
{ m_pipeline_first__47_BITS_518_TO_516_52_EQ_m_p_ETC___d574 &&
|
|
m_cRqMshr$pipelineResp_getSucc[3],
|
|
m_cRqMshr$pipelineResp_getSucc[2:0] } :
|
|
{ !m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562 &&
|
|
m_pipeline$first[521:520] != 2'd0 &&
|
|
m_cRqMshr$pipelineResp_getSucc[3],
|
|
m_cRqMshr$pipelineResp_getSucc[2:0] } ;
|
|
assign MUX_m_pipeline$deqWrite_1__VAL_3 =
|
|
{ 1'd0, 3'bxxx /* unspecified value */ } ;
|
|
assign MUX_m_pipeline$deqWrite_2__VAL_1 =
|
|
{ m_cRqMshr$pipelineResp_getRq[63:12],
|
|
m_pipeline$first[521:520],
|
|
m_cRqMshr$pipelineResp_getSucc,
|
|
m_pipeline$first[515:0] } ;
|
|
assign MUX_m_pipeline$deqWrite_2__VAL_2 =
|
|
{ m_pipeline$first[519] ?
|
|
IF_m_pipeline_first__47_BITS_518_TO_516_52_EQ__ETC___d595 :
|
|
IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d602,
|
|
m_pipeline$first[515:0] } ;
|
|
assign MUX_m_pipeline$deqWrite_2__VAL_3 =
|
|
m_pipeline$first[574] ?
|
|
m_pipeline$first[573:0] :
|
|
{ m_pipeline$first[573:522],
|
|
3'd0,
|
|
3'bxxx /* unspecified value */ ,
|
|
516'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign MUX_m_pipeline$deqWrite_3__VAL_2 =
|
|
m_pipeline$first[519] ?
|
|
m_pipeline_first__47_BITS_518_TO_516_52_EQ_m_p_ETC___d574 :
|
|
!m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562 &&
|
|
m_pipeline$first[521:520] != 2'd0 ;
|
|
assign MUX_m_pipeline$send_1__VAL_1 =
|
|
{ 2'd0,
|
|
519'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
v__h41294,
|
|
m_cRqMshr$getEmptyEntryInit } ;
|
|
assign MUX_m_pipeline$send_1__VAL_2 =
|
|
{ 2'd1,
|
|
520'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425,
|
|
m_pRqMshr$getEmptyEntryInit } ;
|
|
assign MUX_m_pipeline$send_1__VAL_3 =
|
|
{ 2'd2,
|
|
addr__h42425,
|
|
_1_CONCAT_NOT_SEL_ARR_NOT_m_fromPQ_data_0_13_BI_ETC___d509 } ;
|
|
assign MUX_m_rsToPIndexQ$enq_1__VAL_1 =
|
|
{ 1'd0, m_pipeline$first[580:578] } ;
|
|
assign MUX_m_rsToPIndexQ$enq_1__VAL_2 =
|
|
{ 1'd1, m_pipeline$first[580:578] } ;
|
|
assign MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
resp_addr__h45726,
|
|
3'd0,
|
|
516'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
m_pRqMshr$sendRsToP_pRq_getRq[65:2],
|
|
3'd0,
|
|
516'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
|
|
// inlined wires
|
|
assign m_rsToPQ_enqReq_lat_0$wget =
|
|
WILL_FIRE_RL_m_sendRsToP_cRq ?
|
|
MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign m_rsToPQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_m_sendRsToP_cRq || WILL_FIRE_RL_m_sendRsToP_pRq ;
|
|
assign m_rsToPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
583'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign m_rqToPQ_enqReq_lat_0$wget =
|
|
{ 1'd1,
|
|
m_cRqMshr$sendRqToP_getRq,
|
|
5'd2,
|
|
m_cRqMshr$sendRqToP_getSlot[55:53] } ;
|
|
assign m_rqToPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
72'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign m_fromPQ_enqReq_lat_0$wget = { 1'd1, to_parent_fromP_enq_x } ;
|
|
assign m_fromPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
587'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign m_fromPQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_m_pRsTransfer || WILL_FIRE_RL_m_pRqTransfer ;
|
|
|
|
// register m_fromPQ_clearReq_rl
|
|
assign m_fromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_fromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_fromPQ_data_0
|
|
assign m_fromPQ_data_0$D_IN =
|
|
{ IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_NOT_m_f_ETC___d255 ||
|
|
(EN_to_parent_fromP_enq ?
|
|
m_fromPQ_enqReq_lat_0$wget[586] :
|
|
m_fromPQ_enqReq_rl[586]),
|
|
IF_IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fr_ETC___d392 } ;
|
|
assign m_fromPQ_data_0$EN =
|
|
m_fromPQ_enqP == 1'd0 && !m_fromPQ_clearReq_rl &&
|
|
IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fromP_ETC___d248 ;
|
|
|
|
// register m_fromPQ_data_1
|
|
assign m_fromPQ_data_1$D_IN = m_fromPQ_data_0$D_IN ;
|
|
assign m_fromPQ_data_1$EN =
|
|
m_fromPQ_enqP == 1'd1 && !m_fromPQ_clearReq_rl &&
|
|
IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fromP_ETC___d248 ;
|
|
|
|
// register m_fromPQ_deqP
|
|
assign m_fromPQ_deqP$D_IN =
|
|
!m_fromPQ_clearReq_rl && _theResult_____2__h40286 ;
|
|
assign m_fromPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_fromPQ_deqReq_rl
|
|
assign m_fromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_fromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_fromPQ_empty
|
|
assign m_fromPQ_empty$D_IN =
|
|
m_fromPQ_clearReq_rl ||
|
|
IF_IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fr_ETC___d360 &&
|
|
IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_NOT_m_f_ETC___d255 &&
|
|
(IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fromP_ETC___d336 ||
|
|
m_fromPQ_empty) ;
|
|
assign m_fromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_fromPQ_enqP
|
|
assign m_fromPQ_enqP$D_IN = !m_fromPQ_clearReq_rl && v__h31140 ;
|
|
assign m_fromPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_fromPQ_enqReq_rl
|
|
assign m_fromPQ_enqReq_rl$D_IN =
|
|
{ m_fromPQ_enqReq_lat_2$wget[587:586],
|
|
m_fromPQ_enqReq_lat_2$wget[586] ?
|
|
m_fromPQ_enqReq_lat_2$wget[585:0] :
|
|
{ 520'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
m_fromPQ_enqReq_lat_2$wget[65:0] } } ;
|
|
assign m_fromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_fromPQ_full
|
|
assign m_fromPQ_full$D_IN =
|
|
!m_fromPQ_clearReq_rl &&
|
|
IF_IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fr_ETC___d369 ;
|
|
assign m_fromPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_rqFromCQ_data_0_rl
|
|
assign m_rqFromCQ_data_0_rl$D_IN = v__h41294 ;
|
|
assign m_rqFromCQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqFromCQ_empty_rl
|
|
assign m_rqFromCQ_empty_rl$D_IN =
|
|
WILL_FIRE_RL_m_cRqTransfer ||
|
|
!EN_to_proc_req_put && m_rqFromCQ_empty_rl ;
|
|
assign m_rqFromCQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqFromCQ_full_rl
|
|
assign m_rqFromCQ_full_rl$D_IN =
|
|
!WILL_FIRE_RL_m_cRqTransfer &&
|
|
(EN_to_proc_req_put || m_rqFromCQ_full_rl) ;
|
|
assign m_rqFromCQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_clearReq_rl
|
|
assign m_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_rqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_data_0
|
|
assign m_rqToPQ_data_0$D_IN =
|
|
CAN_FIRE_RL_m_sendRqToP ?
|
|
m_rqToPQ_enqReq_lat_0$wget[71:0] :
|
|
m_rqToPQ_enqReq_rl[71:0] ;
|
|
assign m_rqToPQ_data_0$EN =
|
|
m_rqToPQ_enqP == 1'd0 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__54_THEN_m_rqToP_ETC___d163 ;
|
|
|
|
// register m_rqToPQ_data_1
|
|
assign m_rqToPQ_data_1$D_IN =
|
|
CAN_FIRE_RL_m_sendRqToP ?
|
|
m_rqToPQ_enqReq_lat_0$wget[71:0] :
|
|
m_rqToPQ_enqReq_rl[71:0] ;
|
|
assign m_rqToPQ_data_1$EN =
|
|
m_rqToPQ_enqP == 1'd1 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__54_THEN_m_rqToP_ETC___d163 ;
|
|
|
|
// register m_rqToPQ_deqP
|
|
assign m_rqToPQ_deqP$D_IN =
|
|
!m_rqToPQ_clearReq_rl && _theResult_____2__h22970 ;
|
|
assign m_rqToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_deqReq_rl
|
|
assign m_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_rqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_empty
|
|
assign m_rqToPQ_empty$D_IN =
|
|
m_rqToPQ_clearReq_rl ||
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d227 ;
|
|
assign m_rqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_enqP
|
|
assign m_rqToPQ_enqP$D_IN = !m_rqToPQ_clearReq_rl && v__h22346 ;
|
|
assign m_rqToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_enqReq_rl
|
|
assign m_rqToPQ_enqReq_rl$D_IN = m_rqToPQ_enqReq_lat_2$wget ;
|
|
assign m_rqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_full
|
|
assign m_rqToPQ_full$D_IN =
|
|
!m_rqToPQ_clearReq_rl &&
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d222 ;
|
|
assign m_rqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_rsToPQ_clearReq_rl
|
|
assign m_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_rsToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rsToPQ_data_0
|
|
assign m_rsToPQ_data_0$D_IN =
|
|
{ x_addr__h10523,
|
|
m_rsToPQ_enqReq_lat_0$whas ?
|
|
m_rsToPQ_enqReq_lat_0$wget[518:517] :
|
|
m_rsToPQ_enqReq_rl[518:517],
|
|
IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_NOT_m_rs_ETC___d47 ||
|
|
(m_rsToPQ_enqReq_lat_0$whas ?
|
|
m_rsToPQ_enqReq_lat_0$wget[516] :
|
|
m_rsToPQ_enqReq_rl[516]),
|
|
m_rsToPQ_enqReq_lat_0$whas ?
|
|
m_rsToPQ_enqReq_lat_0$wget[515:0] :
|
|
m_rsToPQ_enqReq_rl[515:0] } ;
|
|
assign m_rsToPQ_data_0$EN =
|
|
m_rsToPQ_enqP == 1'd0 && !m_rsToPQ_clearReq_rl &&
|
|
IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ;
|
|
|
|
// register m_rsToPQ_data_1
|
|
assign m_rsToPQ_data_1$D_IN = m_rsToPQ_data_0$D_IN ;
|
|
assign m_rsToPQ_data_1$EN =
|
|
m_rsToPQ_enqP == 1'd1 && !m_rsToPQ_clearReq_rl &&
|
|
IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ;
|
|
|
|
// register m_rsToPQ_deqP
|
|
assign m_rsToPQ_deqP$D_IN =
|
|
!m_rsToPQ_clearReq_rl && _theResult_____2__h19024 ;
|
|
assign m_rsToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_rsToPQ_deqReq_rl
|
|
assign m_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_rsToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rsToPQ_empty
|
|
assign m_rsToPQ_empty$D_IN =
|
|
m_rsToPQ_clearReq_rl ||
|
|
IF_IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsT_ETC___d121 &&
|
|
IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_NOT_m_rs_ETC___d47 &&
|
|
(IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d97 ||
|
|
m_rsToPQ_empty) ;
|
|
assign m_rsToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_rsToPQ_enqP
|
|
assign m_rsToPQ_enqP$D_IN = !m_rsToPQ_clearReq_rl && v__h10212 ;
|
|
assign m_rsToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_rsToPQ_enqReq_rl
|
|
assign m_rsToPQ_enqReq_rl$D_IN = m_rsToPQ_enqReq_lat_2$wget ;
|
|
assign m_rsToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rsToPQ_full
|
|
assign m_rsToPQ_full$D_IN =
|
|
!m_rsToPQ_clearReq_rl &&
|
|
IF_IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsT_ETC___d130 ;
|
|
assign m_rsToPQ_full$EN = 1'd1 ;
|
|
|
|
// submodule m_cRqIndexQ
|
|
assign m_cRqIndexQ$D_IN = m_cRqMshr$getEmptyEntryInit ;
|
|
assign m_cRqIndexQ$ENQ = WILL_FIRE_RL_m_cRqTransfer ;
|
|
assign m_cRqIndexQ$DEQ = EN_to_proc_resp_get ;
|
|
assign m_cRqIndexQ$CLR = 1'b0 ;
|
|
|
|
// submodule m_cRqMshr
|
|
assign m_cRqMshr$getEmptyEntryInit_r = v__h41294 ;
|
|
assign m_cRqMshr$pipelineResp_getRq_n =
|
|
(m_pipeline$first[582:581] == 2'd0) ?
|
|
m_pipeline$first[580:578] :
|
|
(m_pipeline$first[519] ? m_pipeline$first[518:516] : 3'd0) ;
|
|
assign m_cRqMshr$pipelineResp_getSlot_n = 3'h0 ;
|
|
assign m_cRqMshr$pipelineResp_getState_n = 3'h0 ;
|
|
assign m_cRqMshr$pipelineResp_getSucc_n =
|
|
WILL_FIRE_RL_m_pipelineResp_pRs ?
|
|
m_pipeline$first[518:516] :
|
|
m_pipeline$first[580:578] ;
|
|
assign m_cRqMshr$pipelineResp_searchEndOfChain_addr =
|
|
m_cRqMshr$pipelineResp_getRq ;
|
|
assign m_cRqMshr$pipelineResp_setResult_n =
|
|
MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
|
|
m_pipeline$first[518:516] :
|
|
m_pipeline$first[580:578] ;
|
|
assign m_cRqMshr$pipelineResp_setResult_r =
|
|
MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
|
|
MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 :
|
|
MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 ;
|
|
assign m_cRqMshr$pipelineResp_setStateSlot_n =
|
|
MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
|
|
m_pipeline$first[518:516] :
|
|
m_pipeline$first[580:578] ;
|
|
assign m_cRqMshr$pipelineResp_setStateSlot_slot =
|
|
MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
|
|
56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ :
|
|
MUX_m_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
|
|
assign m_cRqMshr$pipelineResp_setStateSlot_state =
|
|
MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
|
|
3'd3 :
|
|
MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 ;
|
|
assign m_cRqMshr$pipelineResp_setSucc_n =
|
|
m_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
|
|
assign m_cRqMshr$pipelineResp_setSucc_succ =
|
|
MUX_m_rsToPIndexQ$enq_1__VAL_2 ;
|
|
assign m_cRqMshr$sendRqToP_getRq_n = m_rqToPIndexQ$D_OUT ;
|
|
assign m_cRqMshr$sendRqToP_getSlot_n = m_rqToPIndexQ$D_OUT ;
|
|
assign m_cRqMshr$sendRsToC_getResult_n = m_cRqIndexQ$D_OUT ;
|
|
assign m_cRqMshr$sendRsToC_releaseEntry_n = m_cRqIndexQ$D_OUT ;
|
|
assign m_cRqMshr$sendRsToP_cRq_getRq_n = m_rsToPIndexQ$D_OUT[2:0] ;
|
|
assign m_cRqMshr$sendRsToP_cRq_getSlot_n = m_rsToPIndexQ$D_OUT[2:0] ;
|
|
assign m_cRqMshr$EN_getEmptyEntryInit = WILL_FIRE_RL_m_cRqTransfer ;
|
|
assign m_cRqMshr$EN_sendRsToC_releaseEntry = EN_to_proc_resp_get ;
|
|
assign m_cRqMshr$EN_pipelineResp_setResult =
|
|
WILL_FIRE_RL_m_pipelineResp_pRs && m_pipeline$first[519] ||
|
|
WILL_FIRE_RL_m_pipelineResp_cRq &&
|
|
m_pipeline_first__47_BIT_519_48_AND_m_pipeline_ETC___d631 ;
|
|
assign m_cRqMshr$EN_pipelineResp_setStateSlot =
|
|
WILL_FIRE_RL_m_pipelineResp_pRs && m_pipeline$first[519] ||
|
|
WILL_FIRE_RL_m_pipelineResp_cRq ;
|
|
assign m_cRqMshr$EN_pipelineResp_setSucc =
|
|
WILL_FIRE_RL_m_pipelineResp_cRq &&
|
|
(m_pipeline$first[519] &&
|
|
!m_pipeline_first__47_BITS_518_TO_516_52_EQ_m_p_ETC___d574 ||
|
|
!m_pipeline$first[519] &&
|
|
m_cRqMshr$pipelineResp_searchEndOfChain[3]) ;
|
|
assign m_cRqMshr$EN_stuck_get = EN_cRqStuck_get ;
|
|
|
|
// submodule m_pRqMshr
|
|
assign m_pRqMshr$getEmptyEntryInit_r =
|
|
{ SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38 } ;
|
|
assign m_pRqMshr$pipelineResp_getRq_n = 2'h0 ;
|
|
assign m_pRqMshr$pipelineResp_releaseEntry_n = m_pipeline$first[579:578] ;
|
|
assign m_pRqMshr$pipelineResp_setDone_n = m_pipeline$first[579:578] ;
|
|
assign m_pRqMshr$sendRsToP_pRq_getRq_n = m_rsToPIndexQ$D_OUT[1:0] ;
|
|
assign m_pRqMshr$sendRsToP_pRq_releaseEntry_n = m_rsToPIndexQ$D_OUT[1:0] ;
|
|
assign m_pRqMshr$EN_getEmptyEntryInit = CAN_FIRE_RL_m_pRqTransfer ;
|
|
assign m_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
|
|
CAN_FIRE_RL_m_sendRsToP_pRq ;
|
|
assign m_pRqMshr$EN_pipelineResp_releaseEntry =
|
|
WILL_FIRE_RL_m_pipelineResp_pRq && m_pipeline$first[574] ;
|
|
assign m_pRqMshr$EN_pipelineResp_setDone = MUX_m_rsToPIndexQ$enq_1__SEL_2 ;
|
|
assign m_pRqMshr$EN_stuck_get = EN_pRqStuck_get ;
|
|
|
|
// submodule m_pipeline
|
|
always@(MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 or
|
|
m_cRqMshr$pipelineResp_getSucc or
|
|
WILL_FIRE_RL_m_pipelineResp_cRq or
|
|
MUX_m_pipeline$deqWrite_1__VAL_2 or
|
|
WILL_FIRE_RL_m_pipelineResp_pRq or MUX_m_pipeline$deqWrite_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1:
|
|
m_pipeline$deqWrite_swapRq = m_cRqMshr$pipelineResp_getSucc;
|
|
WILL_FIRE_RL_m_pipelineResp_cRq:
|
|
m_pipeline$deqWrite_swapRq = MUX_m_pipeline$deqWrite_1__VAL_2;
|
|
WILL_FIRE_RL_m_pipelineResp_pRq:
|
|
m_pipeline$deqWrite_swapRq = MUX_m_pipeline$deqWrite_1__VAL_3;
|
|
default: m_pipeline$deqWrite_swapRq = 4'bxxxx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 or
|
|
WILL_FIRE_RL_m_pipelineResp_cRq or
|
|
MUX_m_pipeline$deqWrite_3__VAL_2 or WILL_FIRE_RL_m_pipelineResp_pRq)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1:
|
|
m_pipeline$deqWrite_updateRep = 1'd1;
|
|
WILL_FIRE_RL_m_pipelineResp_cRq:
|
|
m_pipeline$deqWrite_updateRep = MUX_m_pipeline$deqWrite_3__VAL_2;
|
|
WILL_FIRE_RL_m_pipelineResp_pRq: m_pipeline$deqWrite_updateRep = 1'd0;
|
|
default: m_pipeline$deqWrite_updateRep = 1'bx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 or
|
|
MUX_m_pipeline$deqWrite_2__VAL_1 or
|
|
WILL_FIRE_RL_m_pipelineResp_cRq or
|
|
MUX_m_pipeline$deqWrite_2__VAL_2 or
|
|
WILL_FIRE_RL_m_pipelineResp_pRq or MUX_m_pipeline$deqWrite_2__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1:
|
|
m_pipeline$deqWrite_wrRam = MUX_m_pipeline$deqWrite_2__VAL_1;
|
|
WILL_FIRE_RL_m_pipelineResp_cRq:
|
|
m_pipeline$deqWrite_wrRam = MUX_m_pipeline$deqWrite_2__VAL_2;
|
|
WILL_FIRE_RL_m_pipelineResp_pRq:
|
|
m_pipeline$deqWrite_wrRam = MUX_m_pipeline$deqWrite_2__VAL_3;
|
|
default: m_pipeline$deqWrite_wrRam =
|
|
574'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(WILL_FIRE_RL_m_cRqTransfer or
|
|
MUX_m_pipeline$send_1__VAL_1 or
|
|
WILL_FIRE_RL_m_pRqTransfer or
|
|
MUX_m_pipeline$send_1__VAL_2 or
|
|
WILL_FIRE_RL_m_pRsTransfer or MUX_m_pipeline$send_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_m_cRqTransfer:
|
|
m_pipeline$send_r = MUX_m_pipeline$send_1__VAL_1;
|
|
WILL_FIRE_RL_m_pRqTransfer:
|
|
m_pipeline$send_r = MUX_m_pipeline$send_1__VAL_2;
|
|
WILL_FIRE_RL_m_pRsTransfer:
|
|
m_pipeline$send_r = MUX_m_pipeline$send_1__VAL_3;
|
|
default: m_pipeline$send_r =
|
|
588'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign m_pipeline$EN_send =
|
|
WILL_FIRE_RL_m_cRqTransfer || WILL_FIRE_RL_m_pRqTransfer ||
|
|
WILL_FIRE_RL_m_pRsTransfer ;
|
|
assign m_pipeline$EN_deqWrite =
|
|
WILL_FIRE_RL_m_pipelineResp_pRs && m_pipeline$first[519] ||
|
|
WILL_FIRE_RL_m_pipelineResp_cRq ||
|
|
WILL_FIRE_RL_m_pipelineResp_pRq ;
|
|
|
|
// submodule m_rqToPIndexQ
|
|
assign m_rqToPIndexQ$D_IN =
|
|
WILL_FIRE_RL_m_rqIndexFromPipelineResp ?
|
|
m_rqToPIndexQ_pipelineResp$D_OUT :
|
|
m_rqToPIndexQ_sendRsToP$D_OUT ;
|
|
assign m_rqToPIndexQ$ENQ =
|
|
WILL_FIRE_RL_m_rqIndexFromPipelineResp ||
|
|
WILL_FIRE_RL_m_rqIndexFromSendRsToP ;
|
|
assign m_rqToPIndexQ$DEQ = CAN_FIRE_RL_m_sendRqToP ;
|
|
assign m_rqToPIndexQ$CLR = 1'b0 ;
|
|
|
|
// submodule m_rqToPIndexQ_pipelineResp
|
|
assign m_rqToPIndexQ_pipelineResp$D_IN = m_pipeline$first[580:578] ;
|
|
assign m_rqToPIndexQ_pipelineResp$ENQ =
|
|
WILL_FIRE_RL_m_pipelineResp_cRq && !m_pipeline$first[519] &&
|
|
!m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
m_pipeline$first[521:520] == 2'd0 ;
|
|
assign m_rqToPIndexQ_pipelineResp$DEQ =
|
|
CAN_FIRE_RL_m_rqIndexFromPipelineResp ;
|
|
assign m_rqToPIndexQ_pipelineResp$CLR = 1'b0 ;
|
|
|
|
// submodule m_rqToPIndexQ_sendRsToP
|
|
assign m_rqToPIndexQ_sendRsToP$D_IN = m_rsToPIndexQ$D_OUT[2:0] ;
|
|
assign m_rqToPIndexQ_sendRsToP$ENQ = CAN_FIRE_RL_m_sendRsToP_cRq ;
|
|
assign m_rqToPIndexQ_sendRsToP$DEQ = WILL_FIRE_RL_m_rqIndexFromSendRsToP ;
|
|
assign m_rqToPIndexQ_sendRsToP$CLR = 1'b0 ;
|
|
|
|
// submodule m_rsToPIndexQ
|
|
assign m_rsToPIndexQ$D_IN =
|
|
MUX_m_rsToPIndexQ$enq_1__SEL_1 ?
|
|
MUX_m_rsToPIndexQ$enq_1__VAL_1 :
|
|
MUX_m_rsToPIndexQ$enq_1__VAL_2 ;
|
|
assign m_rsToPIndexQ$ENQ =
|
|
WILL_FIRE_RL_m_pipelineResp_cRq && !m_pipeline$first[519] &&
|
|
!m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
m_pipeline$first[521:520] != 2'd0 &&
|
|
!m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562 ||
|
|
WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[574] ;
|
|
assign m_rsToPIndexQ$DEQ =
|
|
WILL_FIRE_RL_m_sendRsToP_pRq || WILL_FIRE_RL_m_sendRsToP_cRq ;
|
|
assign m_rsToPIndexQ$CLR = 1'b0 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fr_ETC___d360 =
|
|
_theResult_____2__h40286 == v__h31140 ;
|
|
assign IF_IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fr_ETC___d369 =
|
|
IF_IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fr_ETC___d360 &&
|
|
(IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fromP_ETC___d248 ||
|
|
!m_fromPQ_deqReq_lat_0$whas && !m_fromPQ_deqReq_rl &&
|
|
m_fromPQ_full) ;
|
|
assign IF_IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fr_ETC___d392 =
|
|
(IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fromP_ETC___d248 &&
|
|
(EN_to_parent_fromP_enq ?
|
|
!m_fromPQ_enqReq_lat_0$wget[586] :
|
|
!m_fromPQ_enqReq_rl[586])) ?
|
|
{ 520'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
EN_to_parent_fromP_enq ?
|
|
m_fromPQ_enqReq_lat_0$wget[65:0] :
|
|
m_fromPQ_enqReq_rl[65:0] } :
|
|
{ EN_to_parent_fromP_enq ?
|
|
m_fromPQ_enqReq_lat_0$wget[585:522] :
|
|
m_fromPQ_enqReq_rl[585:522],
|
|
EN_to_parent_fromP_enq ?
|
|
m_fromPQ_enqReq_lat_0$wget[521:520] :
|
|
m_fromPQ_enqReq_rl[521:520],
|
|
IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_NOT_m_f_ETC___d255 ||
|
|
(EN_to_parent_fromP_enq ?
|
|
m_fromPQ_enqReq_lat_0$wget[519] :
|
|
m_fromPQ_enqReq_rl[519]),
|
|
EN_to_parent_fromP_enq ?
|
|
m_fromPQ_enqReq_lat_0$wget[518:3] :
|
|
m_fromPQ_enqReq_rl[518:3],
|
|
x__h35816 } ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d213 =
|
|
_theResult_____2__h22970 == v__h22346 ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d222 =
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d213 &&
|
|
(IF_m_rqToPQ_enqReq_lat_1_whas__54_THEN_m_rqToP_ETC___d163 ||
|
|
!EN_to_parent_rqToP_deq && !m_rqToPQ_deqReq_rl &&
|
|
m_rqToPQ_full) ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d227 =
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rq_ETC___d213 &&
|
|
(CAN_FIRE_RL_m_sendRqToP ?
|
|
!m_rqToPQ_enqReq_lat_0$wget[72] :
|
|
!m_rqToPQ_enqReq_rl[72]) &&
|
|
(IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rqToP_ETC___d189 ||
|
|
m_rqToPQ_empty) ;
|
|
assign IF_IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsT_ETC___d121 =
|
|
_theResult_____2__h19024 == v__h10212 ;
|
|
assign IF_IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsT_ETC___d130 =
|
|
IF_IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsT_ETC___d121 &&
|
|
(IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ||
|
|
!EN_to_parent_rsToP_deq && !m_rsToPQ_deqReq_rl &&
|
|
m_rsToPQ_full) ;
|
|
assign IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d602 =
|
|
m_cRqMshr$pipelineResp_searchEndOfChain[3] ?
|
|
m_pipeline$first[573:516] :
|
|
{ m_cRqMshr$pipelineResp_getRq[63:12],
|
|
IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d600 } ;
|
|
assign IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d615 =
|
|
m_cRqMshr$pipelineResp_searchEndOfChain[3] ?
|
|
3'd4 :
|
|
((m_pipeline$first[521:520] == 2'd0 ||
|
|
m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562) ?
|
|
((m_pipeline$first[521:520] == 2'd0) ? 3'd2 : 3'd3) :
|
|
3'd2) ;
|
|
assign IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fromP_ETC___d336 =
|
|
m_fromPQ_deqReq_lat_0$whas || m_fromPQ_deqReq_rl ;
|
|
assign IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_NOT_m_f_ETC___d255 =
|
|
EN_to_parent_fromP_enq ?
|
|
!m_fromPQ_enqReq_lat_0$wget[587] :
|
|
!m_fromPQ_enqReq_rl[587] ;
|
|
assign IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fromP_ETC___d248 =
|
|
EN_to_parent_fromP_enq ?
|
|
m_fromPQ_enqReq_lat_0$wget[587] :
|
|
m_fromPQ_enqReq_rl[587] ;
|
|
assign IF_m_pipeline_first__47_BITS_518_TO_516_52_EQ__ETC___d595 =
|
|
m_pipeline_first__47_BITS_518_TO_516_52_EQ_m_p_ETC___d574 ?
|
|
{ m_cRqMshr$pipelineResp_getRq[63:12],
|
|
m_pipeline$first[521:520],
|
|
m_cRqMshr$pipelineResp_getSucc } :
|
|
m_pipeline$first[573:516] ;
|
|
assign IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d568 =
|
|
(m_pipeline$first[521:520] == 2'd0 ||
|
|
m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562) ?
|
|
m_pipeline$first[521:520] != 2'd0 ||
|
|
m_rqToPIndexQ_pipelineResp$FULL_N :
|
|
m_rsToPIndexQ$FULL_N ;
|
|
assign IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d600 =
|
|
(m_pipeline$first[521:520] == 2'd0 ||
|
|
m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562) ?
|
|
{ m_pipeline$first[521:520],
|
|
m_pipeline$first[521:520] == 2'd0 ||
|
|
m_cRqMshr$pipelineResp_getSucc[3],
|
|
(m_pipeline$first[521:520] == 2'd0) ?
|
|
m_pipeline$first[580:578] :
|
|
m_cRqMshr$pipelineResp_getSucc[2:0] } :
|
|
{ 3'd1, m_pipeline$first[580:578] } ;
|
|
assign IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rqToP_ETC___d189 =
|
|
EN_to_parent_rqToP_deq || m_rqToPQ_deqReq_rl ;
|
|
assign IF_m_rqToPQ_enqReq_lat_1_whas__54_THEN_m_rqToP_ETC___d163 =
|
|
CAN_FIRE_RL_m_sendRqToP ?
|
|
m_rqToPQ_enqReq_lat_0$wget[72] :
|
|
m_rqToPQ_enqReq_rl[72] ;
|
|
assign IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d97 =
|
|
EN_to_parent_rsToP_deq || m_rsToPQ_deqReq_rl ;
|
|
assign IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_NOT_m_rs_ETC___d47 =
|
|
m_rsToPQ_enqReq_lat_0$whas ?
|
|
!m_rsToPQ_enqReq_lat_0$wget[583] :
|
|
!m_rsToPQ_enqReq_rl[583] ;
|
|
assign IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 =
|
|
m_rsToPQ_enqReq_lat_0$whas ?
|
|
m_rsToPQ_enqReq_lat_0$wget[583] :
|
|
m_rsToPQ_enqReq_rl[583] ;
|
|
assign SEL_ARR_m_fromPQ_data_0_13_BITS_514_TO_451_66__ETC___d492 =
|
|
{ CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_514__ETC__q13,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_450__ETC__q14,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_386__ETC__q15,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_322__ETC__q16,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_258__ETC__q17,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_194__ETC__q18 } ;
|
|
assign SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461 =
|
|
{ CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_518_1_ETC__q4,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_517_1_ETC__q5,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_516_1_ETC__q6 } ;
|
|
assign SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d502 =
|
|
{ SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_515_1_ETC__q19,
|
|
SEL_ARR_m_fromPQ_data_0_13_BITS_514_TO_451_66__ETC___d492,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_130__ETC__q20,
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_66_T_ETC__q21 } ;
|
|
assign SEL_ARR_m_rqToPQ_data_0_84_BITS_5_TO_4_94_m_rq_ETC___d806 =
|
|
{ CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_5_TO_ETC__q29,
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BIT_3_1_m_ETC__q30,
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31 } ;
|
|
assign SEL_ARR_m_rsToPQ_data_0_10_BITS_511_TO_448_44__ETC___d770 =
|
|
{ CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_511__ETC__q7,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_447__ETC__q8,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_383__ETC__q9,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_319__ETC__q10,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_255__ETC__q11,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_191__ETC__q12 } ;
|
|
assign SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d739 =
|
|
{ CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_515_1_ETC__q1,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_514_1_ETC__q2,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_513_1_ETC__q3 } ;
|
|
assign SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d780 =
|
|
{ SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d739,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_512_1_ETC__q22,
|
|
SEL_ARR_m_rsToPQ_data_0_10_BITS_511_TO_448_44__ETC___d770,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_127__ETC__q23,
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_63_T_ETC__q24 } ;
|
|
assign _1_CONCAT_NOT_SEL_ARR_NOT_m_fromPQ_data_0_13_BI_ETC___d509 =
|
|
{ 2'd1,
|
|
!CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q28,
|
|
SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d502,
|
|
x__h45568 } ;
|
|
assign _theResult_____2__h19024 =
|
|
IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d97 ?
|
|
next_deqP___1__h19213 :
|
|
m_rsToPQ_deqP ;
|
|
assign _theResult_____2__h22970 =
|
|
IF_m_rqToPQ_deqReq_lat_1_whas__83_THEN_m_rqToP_ETC___d189 ?
|
|
next_deqP___1__h23159 :
|
|
m_rqToPQ_deqP ;
|
|
assign _theResult_____2__h40286 =
|
|
IF_m_fromPQ_deqReq_lat_1_whas__30_THEN_m_fromP_ETC___d336 ?
|
|
next_deqP___1__h40475 :
|
|
m_fromPQ_deqP ;
|
|
assign m_pipeline_RDY_deqWrite__46_AND_IF_m_pipeline__ETC___d690 =
|
|
m_pipeline$RDY_deqWrite &&
|
|
(m_pipeline$first[574] ?
|
|
m_pRqMshr$RDY_pipelineResp_releaseEntry :
|
|
m_rsToPIndexQ$FULL_N) ;
|
|
assign m_pipeline_first__47_BITS_518_TO_516_52_EQ_m_p_ETC___d574 =
|
|
m_pipeline$first[518:516] == m_pipeline$first[580:578] ;
|
|
assign m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562 =
|
|
m_pipeline$first[573:522] ==
|
|
m_cRqMshr$pipelineResp_getRq[63:12] ;
|
|
assign m_pipeline_first__47_BIT_519_48_AND_m_pipeline_ETC___d631 =
|
|
m_pipeline$first[519] &&
|
|
m_pipeline_first__47_BITS_518_TO_516_52_EQ_m_p_ETC___d574 ||
|
|
!m_pipeline$first[519] &&
|
|
!m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
m_pipeline_first__47_BITS_573_TO_522_60_EQ_m_c_ETC___d562 &&
|
|
m_pipeline$first[521:520] != 2'd0 ;
|
|
assign next_deqP___1__h19213 = m_rsToPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h23159 = m_rqToPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h40475 = m_fromPQ_deqP + 1'd1 ;
|
|
assign resp_addr__h45726 =
|
|
{ m_cRqMshr$sendRsToP_cRq_getSlot[52:1],
|
|
m_cRqMshr$sendRsToP_cRq_getRq[11:0] } ;
|
|
assign sel__h51068 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ;
|
|
assign v__h10212 =
|
|
IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ?
|
|
v__h10363 :
|
|
m_rsToPQ_enqP ;
|
|
assign v__h10363 = m_rsToPQ_enqP + 1'd1 ;
|
|
assign v__h22346 =
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__54_THEN_m_rqToP_ETC___d163 ?
|
|
v__h22497 :
|
|
m_rqToPQ_enqP ;
|
|
assign v__h22497 = m_rqToPQ_enqP + 1'd1 ;
|
|
assign v__h31140 =
|
|
IF_m_fromPQ_enqReq_lat_1_whas__39_THEN_m_fromP_ETC___d248 ?
|
|
v__h31291 :
|
|
m_fromPQ_enqP ;
|
|
assign v__h31291 = m_fromPQ_enqP + 1'd1 ;
|
|
assign v__h41294 =
|
|
EN_to_proc_req_put ? to_proc_req_put : m_rqFromCQ_data_0_rl ;
|
|
assign x__h35816 =
|
|
EN_to_parent_fromP_enq ?
|
|
m_fromPQ_enqReq_lat_0$wget[2:0] :
|
|
m_fromPQ_enqReq_rl[2:0] ;
|
|
assign x_addr__h10523 =
|
|
m_rsToPQ_enqReq_lat_0$whas ?
|
|
m_rsToPQ_enqReq_lat_0$wget[582:519] :
|
|
m_rsToPQ_enqReq_rl[582:519] ;
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0: addr__h42425 = m_fromPQ_data_0[585:522];
|
|
1'd1: addr__h42425 = m_fromPQ_data_1[585:522];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0: x__h45568 = m_fromPQ_data_0[2:0];
|
|
1'd1: x__h45568 = m_fromPQ_data_1[2:0];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425 =
|
|
m_fromPQ_data_0[65:2];
|
|
1'd1:
|
|
SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425 =
|
|
m_fromPQ_data_1[65:2];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_515_1_ETC__q1 =
|
|
m_rsToPQ_data_0[515];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_515_1_ETC__q1 =
|
|
m_rsToPQ_data_1[515];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_514_1_ETC__q2 =
|
|
m_rsToPQ_data_0[514];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_514_1_ETC__q2 =
|
|
m_rsToPQ_data_1[514];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_513_1_ETC__q3 =
|
|
m_rsToPQ_data_0[513];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_513_1_ETC__q3 =
|
|
m_rsToPQ_data_1[513];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_518_1_ETC__q4 =
|
|
m_fromPQ_data_0[518];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_518_1_ETC__q4 =
|
|
m_fromPQ_data_1[518];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_517_1_ETC__q5 =
|
|
m_fromPQ_data_0[517];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_517_1_ETC__q5 =
|
|
m_fromPQ_data_1[517];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_516_1_ETC__q6 =
|
|
m_fromPQ_data_0[516];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_516_1_ETC__q6 =
|
|
m_fromPQ_data_1[516];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_511__ETC__q7 =
|
|
m_rsToPQ_data_0[511:448];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_511__ETC__q7 =
|
|
m_rsToPQ_data_1[511:448];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_447__ETC__q8 =
|
|
m_rsToPQ_data_0[447:384];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_447__ETC__q8 =
|
|
m_rsToPQ_data_1[447:384];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_383__ETC__q9 =
|
|
m_rsToPQ_data_0[383:320];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_383__ETC__q9 =
|
|
m_rsToPQ_data_1[383:320];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_319__ETC__q10 =
|
|
m_rsToPQ_data_0[319:256];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_319__ETC__q10 =
|
|
m_rsToPQ_data_1[319:256];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_255__ETC__q11 =
|
|
m_rsToPQ_data_0[255:192];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_255__ETC__q11 =
|
|
m_rsToPQ_data_1[255:192];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_191__ETC__q12 =
|
|
m_rsToPQ_data_0[191:128];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_191__ETC__q12 =
|
|
m_rsToPQ_data_1[191:128];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_514__ETC__q13 =
|
|
m_fromPQ_data_0[514:451];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_514__ETC__q13 =
|
|
m_fromPQ_data_1[514:451];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_450__ETC__q14 =
|
|
m_fromPQ_data_0[450:387];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_450__ETC__q14 =
|
|
m_fromPQ_data_1[450:387];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_386__ETC__q15 =
|
|
m_fromPQ_data_0[386:323];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_386__ETC__q15 =
|
|
m_fromPQ_data_1[386:323];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_322__ETC__q16 =
|
|
m_fromPQ_data_0[322:259];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_322__ETC__q16 =
|
|
m_fromPQ_data_1[322:259];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_258__ETC__q17 =
|
|
m_fromPQ_data_0[258:195];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_258__ETC__q17 =
|
|
m_fromPQ_data_1[258:195];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_194__ETC__q18 =
|
|
m_fromPQ_data_0[194:131];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_194__ETC__q18 =
|
|
m_fromPQ_data_1[194:131];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_515_1_ETC__q19 =
|
|
m_fromPQ_data_0[515];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_515_1_ETC__q19 =
|
|
m_fromPQ_data_1[515];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_130__ETC__q20 =
|
|
m_fromPQ_data_0[130:67];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_130__ETC__q20 =
|
|
m_fromPQ_data_1[130:67];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_66_T_ETC__q21 =
|
|
m_fromPQ_data_0[66:3];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_66_T_ETC__q21 =
|
|
m_fromPQ_data_1[66:3];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_512_1_ETC__q22 =
|
|
m_rsToPQ_data_0[512];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BIT_512_1_ETC__q22 =
|
|
m_rsToPQ_data_1[512];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_127__ETC__q23 =
|
|
m_rsToPQ_data_0[127:64];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_127__ETC__q23 =
|
|
m_rsToPQ_data_1[127:64];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_63_T_ETC__q24 =
|
|
m_rsToPQ_data_0[63:0];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_63_T_ETC__q24 =
|
|
m_rsToPQ_data_1[63:0];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_582__ETC__q25 =
|
|
m_rsToPQ_data_0[582:519];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_582__ETC__q25 =
|
|
m_rsToPQ_data_1[582:519];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_518__ETC__q26 =
|
|
m_rsToPQ_data_0[518:517];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_518__ETC__q26 =
|
|
m_rsToPQ_data_1[518:517];
|
|
endcase
|
|
end
|
|
always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
|
|
begin
|
|
case (m_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rsToPQ_deqP_0_NOT_m_rsToPQ_data_0_BIT_5_ETC__q27 =
|
|
!m_rsToPQ_data_0[516];
|
|
1'd1:
|
|
CASE_m_rsToPQ_deqP_0_NOT_m_rsToPQ_data_0_BIT_5_ETC__q27 =
|
|
!m_rsToPQ_data_1[516];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q28 =
|
|
!m_fromPQ_data_0[519];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q28 =
|
|
!m_fromPQ_data_1[519];
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_5_TO_ETC__q29 =
|
|
m_rqToPQ_data_0[5:4];
|
|
1'd1:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_5_TO_ETC__q29 =
|
|
m_rqToPQ_data_1[5:4];
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BIT_3_1_m_ETC__q30 =
|
|
m_rqToPQ_data_0[3];
|
|
1'd1:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BIT_3_1_m_ETC__q30 =
|
|
m_rqToPQ_data_1[3];
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31 =
|
|
m_rqToPQ_data_0[2:0];
|
|
1'd1:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31 =
|
|
m_rqToPQ_data_1[2:0];
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_71_T_ETC__q32 =
|
|
m_rqToPQ_data_0[71:8];
|
|
1'd1:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_71_T_ETC__q32 =
|
|
m_rqToPQ_data_1[71:8];
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_7_TO_ETC__q33 =
|
|
m_rqToPQ_data_0[7:6];
|
|
1'd1:
|
|
CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_7_TO_ETC__q33 =
|
|
m_rqToPQ_data_1[7:6];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q34 =
|
|
!m_fromPQ_data_0[586];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q34 =
|
|
!m_fromPQ_data_1[586];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_586_1_ETC__q35 =
|
|
m_fromPQ_data_0[586];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_586_1_ETC__q35 =
|
|
m_fromPQ_data_1[586];
|
|
endcase
|
|
end
|
|
always@(sel__h51068 or m_pipeline$first)
|
|
begin
|
|
case (sel__h51068)
|
|
4'd0:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[31:0];
|
|
4'd1:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[63:32];
|
|
4'd2:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[95:64];
|
|
4'd3:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[127:96];
|
|
4'd4:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[159:128];
|
|
4'd5:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[191:160];
|
|
4'd6:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[223:192];
|
|
4'd7:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[255:224];
|
|
4'd8:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[287:256];
|
|
4'd9:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[319:288];
|
|
4'd10:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[351:320];
|
|
4'd11:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[383:352];
|
|
4'd12:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[415:384];
|
|
4'd13:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[447:416];
|
|
4'd14:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[479:448];
|
|
4'd15:
|
|
CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
|
|
m_pipeline$first[511:480];
|
|
endcase
|
|
end
|
|
always@(m_cRqMshr$pipelineResp_getRq or m_pipeline$first)
|
|
begin
|
|
case (m_cRqMshr$pipelineResp_getRq[5:2])
|
|
4'd0:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[31:0];
|
|
4'd1:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[63:32];
|
|
4'd2:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[95:64];
|
|
4'd3:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[127:96];
|
|
4'd4:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[159:128];
|
|
4'd5:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[191:160];
|
|
4'd6:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[223:192];
|
|
4'd7:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[255:224];
|
|
4'd8:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[287:256];
|
|
4'd9:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[319:288];
|
|
4'd10:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[351:320];
|
|
4'd11:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[383:352];
|
|
4'd12:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[415:384];
|
|
4'd13:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[447:416];
|
|
4'd14:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[479:448];
|
|
4'd15:
|
|
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 =
|
|
m_pipeline$first[511:480];
|
|
endcase
|
|
end
|
|
always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
|
|
begin
|
|
case (m_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38 =
|
|
m_fromPQ_data_0[1:0];
|
|
1'd1:
|
|
CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38 =
|
|
m_fromPQ_data_1[1:0];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
520'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
66'd0 };
|
|
m_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
520'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
66'd0 };
|
|
m_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
587'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_fromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 72'd0;
|
|
m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 72'd0;
|
|
m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
72'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 67'd0,
|
|
516'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 67'd0,
|
|
516'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
583'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_fromPQ_clearReq_rl$EN)
|
|
m_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_fromPQ_clearReq_rl$D_IN;
|
|
if (m_fromPQ_data_0$EN)
|
|
m_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_fromPQ_data_0$D_IN;
|
|
if (m_fromPQ_data_1$EN)
|
|
m_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_fromPQ_data_1$D_IN;
|
|
if (m_fromPQ_deqP$EN)
|
|
m_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_fromPQ_deqP$D_IN;
|
|
if (m_fromPQ_deqReq_rl$EN)
|
|
m_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_fromPQ_deqReq_rl$D_IN;
|
|
if (m_fromPQ_empty$EN)
|
|
m_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY m_fromPQ_empty$D_IN;
|
|
if (m_fromPQ_enqP$EN)
|
|
m_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_fromPQ_enqP$D_IN;
|
|
if (m_fromPQ_enqReq_rl$EN)
|
|
m_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_fromPQ_enqReq_rl$D_IN;
|
|
if (m_fromPQ_full$EN)
|
|
m_fromPQ_full <= `BSV_ASSIGNMENT_DELAY m_fromPQ_full$D_IN;
|
|
if (m_rqFromCQ_data_0_rl$EN)
|
|
m_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rqFromCQ_data_0_rl$D_IN;
|
|
if (m_rqFromCQ_empty_rl$EN)
|
|
m_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rqFromCQ_empty_rl$D_IN;
|
|
if (m_rqFromCQ_full_rl$EN)
|
|
m_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY m_rqFromCQ_full_rl$D_IN;
|
|
if (m_rqToPQ_clearReq_rl$EN)
|
|
m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rqToPQ_clearReq_rl$D_IN;
|
|
if (m_rqToPQ_data_0$EN)
|
|
m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_0$D_IN;
|
|
if (m_rqToPQ_data_1$EN)
|
|
m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_1$D_IN;
|
|
if (m_rqToPQ_deqP$EN)
|
|
m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqP$D_IN;
|
|
if (m_rqToPQ_deqReq_rl$EN)
|
|
m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqReq_rl$D_IN;
|
|
if (m_rqToPQ_empty$EN)
|
|
m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_empty$D_IN;
|
|
if (m_rqToPQ_enqP$EN)
|
|
m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqP$D_IN;
|
|
if (m_rqToPQ_enqReq_rl$EN)
|
|
m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqReq_rl$D_IN;
|
|
if (m_rqToPQ_full$EN)
|
|
m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_full$D_IN;
|
|
if (m_rsToPQ_clearReq_rl$EN)
|
|
m_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rsToPQ_clearReq_rl$D_IN;
|
|
if (m_rsToPQ_data_0$EN)
|
|
m_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_data_0$D_IN;
|
|
if (m_rsToPQ_data_1$EN)
|
|
m_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_data_1$D_IN;
|
|
if (m_rsToPQ_deqP$EN)
|
|
m_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_deqP$D_IN;
|
|
if (m_rsToPQ_deqReq_rl$EN)
|
|
m_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_deqReq_rl$D_IN;
|
|
if (m_rsToPQ_empty$EN)
|
|
m_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_empty$D_IN;
|
|
if (m_rsToPQ_enqP$EN)
|
|
m_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_enqP$D_IN;
|
|
if (m_rsToPQ_enqReq_rl$EN)
|
|
m_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_enqReq_rl$D_IN;
|
|
if (m_rsToPQ_full$EN)
|
|
m_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_full$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_fromPQ_clearReq_rl = 1'h0;
|
|
m_fromPQ_data_0 =
|
|
587'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_fromPQ_data_1 =
|
|
587'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_fromPQ_deqP = 1'h0;
|
|
m_fromPQ_deqReq_rl = 1'h0;
|
|
m_fromPQ_empty = 1'h0;
|
|
m_fromPQ_enqP = 1'h0;
|
|
m_fromPQ_enqReq_rl =
|
|
588'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_fromPQ_full = 1'h0;
|
|
m_rqFromCQ_data_0_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_rqFromCQ_empty_rl = 1'h0;
|
|
m_rqFromCQ_full_rl = 1'h0;
|
|
m_rqToPQ_clearReq_rl = 1'h0;
|
|
m_rqToPQ_data_0 = 72'hAAAAAAAAAAAAAAAAAA;
|
|
m_rqToPQ_data_1 = 72'hAAAAAAAAAAAAAAAAAA;
|
|
m_rqToPQ_deqP = 1'h0;
|
|
m_rqToPQ_deqReq_rl = 1'h0;
|
|
m_rqToPQ_empty = 1'h0;
|
|
m_rqToPQ_enqP = 1'h0;
|
|
m_rqToPQ_enqReq_rl = 73'h0AAAAAAAAAAAAAAAAAA;
|
|
m_rqToPQ_full = 1'h0;
|
|
m_rsToPQ_clearReq_rl = 1'h0;
|
|
m_rsToPQ_data_0 =
|
|
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_rsToPQ_data_1 =
|
|
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_rsToPQ_deqP = 1'h0;
|
|
m_rsToPQ_deqReq_rl = 1'h0;
|
|
m_rsToPQ_empty = 1'h0;
|
|
m_rsToPQ_enqP = 1'h0;
|
|
m_rsToPQ_enqReq_rl =
|
|
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_rsToPQ_full = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkIBankWrapper
|
|
|