2660 lines
96 KiB
Verilog
2660 lines
96 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:34:14 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// getEmptyEntryInit O 3 reg
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// RDY_getEmptyEntryInit O 1
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// RDY_sendRsToC_releaseEntry O 1
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// sendRsToC_getResult O 67
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// RDY_sendRsToC_getResult O 1 const
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// sendRsToP_cRq_getRq O 64
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// RDY_sendRsToP_cRq_getRq O 1 const
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// sendRsToP_cRq_getSlot O 56
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// RDY_sendRsToP_cRq_getSlot O 1 const
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// sendRqToP_getRq O 64
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// RDY_sendRqToP_getRq O 1 const
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// sendRqToP_getSlot O 56
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// RDY_sendRqToP_getSlot O 1 const
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// pipelineResp_getState O 3
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// RDY_pipelineResp_getState O 1 const
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// pipelineResp_getRq O 64
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// RDY_pipelineResp_getRq O 1 const
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// pipelineResp_getSlot O 56
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// RDY_pipelineResp_getSlot O 1 const
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// RDY_pipelineResp_setResult O 1 const
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// RDY_pipelineResp_setStateSlot O 1 const
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// pipelineResp_getSucc O 4
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// RDY_pipelineResp_getSucc O 1 const
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// RDY_pipelineResp_setSucc O 1 const
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// pipelineResp_searchEndOfChain O 4
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// RDY_pipelineResp_searchEndOfChain O 1 const
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// emptyForFlush O 1
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// RDY_emptyForFlush O 1 const
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// stuck_get O 68
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// RDY_stuck_get O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// getEmptyEntryInit_r I 64
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// sendRsToC_releaseEntry_n I 3
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// sendRsToC_getResult_n I 3
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// sendRsToP_cRq_getRq_n I 3
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// sendRsToP_cRq_getSlot_n I 3
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// sendRqToP_getRq_n I 3
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// sendRqToP_getSlot_n I 3
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// pipelineResp_getState_n I 3
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// pipelineResp_getRq_n I 3
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// pipelineResp_getSlot_n I 3
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// pipelineResp_setResult_n I 3
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// pipelineResp_setResult_r I 66
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// pipelineResp_setStateSlot_n I 3
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// pipelineResp_setStateSlot_state I 3
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// pipelineResp_setStateSlot_slot I 56
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// pipelineResp_getSucc_n I 3
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// pipelineResp_setSucc_n I 3
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// pipelineResp_setSucc_succ I 4
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// pipelineResp_searchEndOfChain_addr I 64
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// EN_sendRsToC_releaseEntry I 1
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// EN_pipelineResp_setResult I 1
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// EN_pipelineResp_setStateSlot I 1
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// EN_pipelineResp_setSucc I 1
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// EN_getEmptyEntryInit I 1
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// EN_stuck_get I 1 unused
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//
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// Combinational paths from inputs to outputs:
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// (sendRsToC_getResult_n,
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// pipelineResp_setResult_n,
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// pipelineResp_setResult_r,
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// EN_pipelineResp_setResult) -> sendRsToC_getResult
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// sendRsToP_cRq_getRq_n -> sendRsToP_cRq_getRq
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// sendRsToP_cRq_getSlot_n -> sendRsToP_cRq_getSlot
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// sendRqToP_getRq_n -> sendRqToP_getRq
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// sendRqToP_getSlot_n -> sendRqToP_getSlot
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// pipelineResp_getState_n -> pipelineResp_getState
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// pipelineResp_getRq_n -> pipelineResp_getRq
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// pipelineResp_getSlot_n -> pipelineResp_getSlot
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// pipelineResp_getSucc_n -> pipelineResp_getSucc
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// pipelineResp_searchEndOfChain_addr -> pipelineResp_searchEndOfChain
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkICRqMshrWrapper(CLK,
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RST_N,
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getEmptyEntryInit_r,
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EN_getEmptyEntryInit,
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getEmptyEntryInit,
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RDY_getEmptyEntryInit,
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sendRsToC_releaseEntry_n,
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EN_sendRsToC_releaseEntry,
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RDY_sendRsToC_releaseEntry,
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sendRsToC_getResult_n,
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sendRsToC_getResult,
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RDY_sendRsToC_getResult,
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sendRsToP_cRq_getRq_n,
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sendRsToP_cRq_getRq,
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RDY_sendRsToP_cRq_getRq,
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sendRsToP_cRq_getSlot_n,
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sendRsToP_cRq_getSlot,
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RDY_sendRsToP_cRq_getSlot,
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sendRqToP_getRq_n,
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sendRqToP_getRq,
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RDY_sendRqToP_getRq,
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sendRqToP_getSlot_n,
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sendRqToP_getSlot,
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RDY_sendRqToP_getSlot,
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pipelineResp_getState_n,
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pipelineResp_getState,
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RDY_pipelineResp_getState,
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pipelineResp_getRq_n,
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pipelineResp_getRq,
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RDY_pipelineResp_getRq,
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pipelineResp_getSlot_n,
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pipelineResp_getSlot,
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RDY_pipelineResp_getSlot,
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pipelineResp_setResult_n,
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pipelineResp_setResult_r,
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EN_pipelineResp_setResult,
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RDY_pipelineResp_setResult,
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pipelineResp_setStateSlot_n,
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pipelineResp_setStateSlot_state,
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pipelineResp_setStateSlot_slot,
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EN_pipelineResp_setStateSlot,
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RDY_pipelineResp_setStateSlot,
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pipelineResp_getSucc_n,
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pipelineResp_getSucc,
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RDY_pipelineResp_getSucc,
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pipelineResp_setSucc_n,
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pipelineResp_setSucc_succ,
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EN_pipelineResp_setSucc,
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RDY_pipelineResp_setSucc,
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pipelineResp_searchEndOfChain_addr,
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pipelineResp_searchEndOfChain,
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RDY_pipelineResp_searchEndOfChain,
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emptyForFlush,
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RDY_emptyForFlush,
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EN_stuck_get,
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stuck_get,
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RDY_stuck_get);
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input CLK;
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input RST_N;
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// actionvalue method getEmptyEntryInit
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input [63 : 0] getEmptyEntryInit_r;
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input EN_getEmptyEntryInit;
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output [2 : 0] getEmptyEntryInit;
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output RDY_getEmptyEntryInit;
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// action method sendRsToC_releaseEntry
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input [2 : 0] sendRsToC_releaseEntry_n;
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input EN_sendRsToC_releaseEntry;
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output RDY_sendRsToC_releaseEntry;
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// value method sendRsToC_getResult
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input [2 : 0] sendRsToC_getResult_n;
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output [66 : 0] sendRsToC_getResult;
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output RDY_sendRsToC_getResult;
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// value method sendRsToP_cRq_getRq
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input [2 : 0] sendRsToP_cRq_getRq_n;
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output [63 : 0] sendRsToP_cRq_getRq;
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output RDY_sendRsToP_cRq_getRq;
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// value method sendRsToP_cRq_getSlot
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input [2 : 0] sendRsToP_cRq_getSlot_n;
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output [55 : 0] sendRsToP_cRq_getSlot;
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output RDY_sendRsToP_cRq_getSlot;
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// value method sendRqToP_getRq
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input [2 : 0] sendRqToP_getRq_n;
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output [63 : 0] sendRqToP_getRq;
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output RDY_sendRqToP_getRq;
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// value method sendRqToP_getSlot
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input [2 : 0] sendRqToP_getSlot_n;
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output [55 : 0] sendRqToP_getSlot;
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output RDY_sendRqToP_getSlot;
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// value method pipelineResp_getState
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input [2 : 0] pipelineResp_getState_n;
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output [2 : 0] pipelineResp_getState;
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output RDY_pipelineResp_getState;
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// value method pipelineResp_getRq
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input [2 : 0] pipelineResp_getRq_n;
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output [63 : 0] pipelineResp_getRq;
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output RDY_pipelineResp_getRq;
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// value method pipelineResp_getSlot
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input [2 : 0] pipelineResp_getSlot_n;
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output [55 : 0] pipelineResp_getSlot;
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output RDY_pipelineResp_getSlot;
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// action method pipelineResp_setResult
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input [2 : 0] pipelineResp_setResult_n;
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input [65 : 0] pipelineResp_setResult_r;
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input EN_pipelineResp_setResult;
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output RDY_pipelineResp_setResult;
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// action method pipelineResp_setStateSlot
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input [2 : 0] pipelineResp_setStateSlot_n;
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input [2 : 0] pipelineResp_setStateSlot_state;
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input [55 : 0] pipelineResp_setStateSlot_slot;
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input EN_pipelineResp_setStateSlot;
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output RDY_pipelineResp_setStateSlot;
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// value method pipelineResp_getSucc
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input [2 : 0] pipelineResp_getSucc_n;
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output [3 : 0] pipelineResp_getSucc;
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output RDY_pipelineResp_getSucc;
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// action method pipelineResp_setSucc
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input [2 : 0] pipelineResp_setSucc_n;
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input [3 : 0] pipelineResp_setSucc_succ;
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input EN_pipelineResp_setSucc;
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output RDY_pipelineResp_setSucc;
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// value method pipelineResp_searchEndOfChain
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input [63 : 0] pipelineResp_searchEndOfChain_addr;
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output [3 : 0] pipelineResp_searchEndOfChain;
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output RDY_pipelineResp_searchEndOfChain;
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// value method emptyForFlush
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output emptyForFlush;
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output RDY_emptyForFlush;
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// actionvalue method stuck_get
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input EN_stuck_get;
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output [67 : 0] stuck_get;
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output RDY_stuck_get;
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// signals for module outputs
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reg [63 : 0] pipelineResp_getRq, sendRqToP_getRq, sendRsToP_cRq_getRq;
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reg [2 : 0] pipelineResp_getState;
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wire [67 : 0] stuck_get;
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wire [66 : 0] sendRsToC_getResult;
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wire [55 : 0] pipelineResp_getSlot,
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sendRqToP_getSlot,
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sendRsToP_cRq_getSlot;
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wire [3 : 0] pipelineResp_getSucc, pipelineResp_searchEndOfChain;
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wire [2 : 0] getEmptyEntryInit;
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wire RDY_emptyForFlush,
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RDY_getEmptyEntryInit,
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RDY_pipelineResp_getRq,
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RDY_pipelineResp_getSlot,
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RDY_pipelineResp_getState,
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RDY_pipelineResp_getSucc,
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RDY_pipelineResp_searchEndOfChain,
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RDY_pipelineResp_setResult,
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RDY_pipelineResp_setStateSlot,
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RDY_pipelineResp_setSucc,
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RDY_sendRqToP_getRq,
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RDY_sendRqToP_getSlot,
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RDY_sendRsToC_getResult,
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RDY_sendRsToC_releaseEntry,
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RDY_sendRsToP_cRq_getRq,
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RDY_sendRsToP_cRq_getSlot,
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RDY_stuck_get,
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emptyForFlush;
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// inlined wires
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wire [66 : 0] m_m_resultVec_0_lat_0$wget, m_m_resultVec_0_lat_2$wget;
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wire [55 : 0] m_m_slotVec_0_lat_2$wget;
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wire m_m_resultVec_0_lat_0$whas,
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m_m_resultVec_1_lat_0$whas,
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m_m_resultVec_2_lat_0$whas,
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m_m_resultVec_3_lat_0$whas,
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m_m_resultVec_4_lat_0$whas,
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m_m_resultVec_5_lat_0$whas,
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m_m_resultVec_6_lat_0$whas,
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m_m_resultVec_7_lat_0$whas,
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m_m_stateVec_0_lat_0$whas,
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m_m_stateVec_0_lat_1$whas,
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m_m_stateVec_0_lat_2$whas,
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m_m_stateVec_1_lat_0$whas,
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m_m_stateVec_1_lat_1$whas,
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m_m_stateVec_1_lat_2$whas,
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m_m_stateVec_2_lat_0$whas,
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m_m_stateVec_2_lat_1$whas,
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m_m_stateVec_2_lat_2$whas,
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m_m_stateVec_3_lat_0$whas,
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m_m_stateVec_3_lat_1$whas,
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m_m_stateVec_3_lat_2$whas,
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m_m_stateVec_4_lat_0$whas,
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m_m_stateVec_4_lat_1$whas,
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m_m_stateVec_4_lat_2$whas,
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m_m_stateVec_5_lat_0$whas,
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m_m_stateVec_5_lat_1$whas,
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m_m_stateVec_5_lat_2$whas,
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m_m_stateVec_6_lat_0$whas,
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m_m_stateVec_6_lat_1$whas,
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m_m_stateVec_6_lat_2$whas,
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m_m_stateVec_7_lat_0$whas,
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m_m_stateVec_7_lat_1$whas,
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m_m_stateVec_7_lat_2$whas,
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m_m_succValidVec_0_lat_0$whas,
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m_m_succValidVec_1_lat_0$whas,
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m_m_succValidVec_2_lat_0$whas,
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m_m_succValidVec_3_lat_0$whas,
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m_m_succValidVec_4_lat_0$whas,
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m_m_succValidVec_5_lat_0$whas,
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m_m_succValidVec_6_lat_0$whas,
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m_m_succValidVec_7_lat_0$whas;
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// register m_m_initIdx
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reg [2 : 0] m_m_initIdx;
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wire [2 : 0] m_m_initIdx$D_IN;
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wire m_m_initIdx$EN;
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// register m_m_inited
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reg m_m_inited;
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wire m_m_inited$D_IN, m_m_inited$EN;
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// register m_m_reqVec_0_rl
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reg [63 : 0] m_m_reqVec_0_rl;
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wire [63 : 0] m_m_reqVec_0_rl$D_IN;
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wire m_m_reqVec_0_rl$EN;
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// register m_m_reqVec_1_rl
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reg [63 : 0] m_m_reqVec_1_rl;
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wire [63 : 0] m_m_reqVec_1_rl$D_IN;
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wire m_m_reqVec_1_rl$EN;
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// register m_m_reqVec_2_rl
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reg [63 : 0] m_m_reqVec_2_rl;
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wire [63 : 0] m_m_reqVec_2_rl$D_IN;
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wire m_m_reqVec_2_rl$EN;
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// register m_m_reqVec_3_rl
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reg [63 : 0] m_m_reqVec_3_rl;
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wire [63 : 0] m_m_reqVec_3_rl$D_IN;
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wire m_m_reqVec_3_rl$EN;
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// register m_m_reqVec_4_rl
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reg [63 : 0] m_m_reqVec_4_rl;
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wire [63 : 0] m_m_reqVec_4_rl$D_IN;
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wire m_m_reqVec_4_rl$EN;
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// register m_m_reqVec_5_rl
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reg [63 : 0] m_m_reqVec_5_rl;
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wire [63 : 0] m_m_reqVec_5_rl$D_IN;
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wire m_m_reqVec_5_rl$EN;
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// register m_m_reqVec_6_rl
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reg [63 : 0] m_m_reqVec_6_rl;
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wire [63 : 0] m_m_reqVec_6_rl$D_IN;
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wire m_m_reqVec_6_rl$EN;
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// register m_m_reqVec_7_rl
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reg [63 : 0] m_m_reqVec_7_rl;
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wire [63 : 0] m_m_reqVec_7_rl$D_IN;
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wire m_m_reqVec_7_rl$EN;
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// register m_m_resultVec_0_rl
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reg [66 : 0] m_m_resultVec_0_rl;
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wire [66 : 0] m_m_resultVec_0_rl$D_IN;
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wire m_m_resultVec_0_rl$EN;
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// register m_m_resultVec_1_rl
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reg [66 : 0] m_m_resultVec_1_rl;
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wire [66 : 0] m_m_resultVec_1_rl$D_IN;
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wire m_m_resultVec_1_rl$EN;
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// register m_m_resultVec_2_rl
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reg [66 : 0] m_m_resultVec_2_rl;
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wire [66 : 0] m_m_resultVec_2_rl$D_IN;
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wire m_m_resultVec_2_rl$EN;
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// register m_m_resultVec_3_rl
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reg [66 : 0] m_m_resultVec_3_rl;
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wire [66 : 0] m_m_resultVec_3_rl$D_IN;
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wire m_m_resultVec_3_rl$EN;
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// register m_m_resultVec_4_rl
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reg [66 : 0] m_m_resultVec_4_rl;
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wire [66 : 0] m_m_resultVec_4_rl$D_IN;
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wire m_m_resultVec_4_rl$EN;
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// register m_m_resultVec_5_rl
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reg [66 : 0] m_m_resultVec_5_rl;
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wire [66 : 0] m_m_resultVec_5_rl$D_IN;
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wire m_m_resultVec_5_rl$EN;
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// register m_m_resultVec_6_rl
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reg [66 : 0] m_m_resultVec_6_rl;
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wire [66 : 0] m_m_resultVec_6_rl$D_IN;
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wire m_m_resultVec_6_rl$EN;
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// register m_m_resultVec_7_rl
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reg [66 : 0] m_m_resultVec_7_rl;
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wire [66 : 0] m_m_resultVec_7_rl$D_IN;
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wire m_m_resultVec_7_rl$EN;
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// register m_m_slotVec_0_rl
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reg [55 : 0] m_m_slotVec_0_rl;
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wire [55 : 0] m_m_slotVec_0_rl$D_IN;
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wire m_m_slotVec_0_rl$EN;
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// register m_m_slotVec_1_rl
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reg [55 : 0] m_m_slotVec_1_rl;
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wire [55 : 0] m_m_slotVec_1_rl$D_IN;
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wire m_m_slotVec_1_rl$EN;
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// register m_m_slotVec_2_rl
|
|
reg [55 : 0] m_m_slotVec_2_rl;
|
|
wire [55 : 0] m_m_slotVec_2_rl$D_IN;
|
|
wire m_m_slotVec_2_rl$EN;
|
|
|
|
// register m_m_slotVec_3_rl
|
|
reg [55 : 0] m_m_slotVec_3_rl;
|
|
wire [55 : 0] m_m_slotVec_3_rl$D_IN;
|
|
wire m_m_slotVec_3_rl$EN;
|
|
|
|
// register m_m_slotVec_4_rl
|
|
reg [55 : 0] m_m_slotVec_4_rl;
|
|
wire [55 : 0] m_m_slotVec_4_rl$D_IN;
|
|
wire m_m_slotVec_4_rl$EN;
|
|
|
|
// register m_m_slotVec_5_rl
|
|
reg [55 : 0] m_m_slotVec_5_rl;
|
|
wire [55 : 0] m_m_slotVec_5_rl$D_IN;
|
|
wire m_m_slotVec_5_rl$EN;
|
|
|
|
// register m_m_slotVec_6_rl
|
|
reg [55 : 0] m_m_slotVec_6_rl;
|
|
wire [55 : 0] m_m_slotVec_6_rl$D_IN;
|
|
wire m_m_slotVec_6_rl$EN;
|
|
|
|
// register m_m_slotVec_7_rl
|
|
reg [55 : 0] m_m_slotVec_7_rl;
|
|
wire [55 : 0] m_m_slotVec_7_rl$D_IN;
|
|
wire m_m_slotVec_7_rl$EN;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
reg [2 : 0] m_m_stateVec_0_rl;
|
|
wire [2 : 0] m_m_stateVec_0_rl$D_IN;
|
|
wire m_m_stateVec_0_rl$EN;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
reg [2 : 0] m_m_stateVec_1_rl;
|
|
wire [2 : 0] m_m_stateVec_1_rl$D_IN;
|
|
wire m_m_stateVec_1_rl$EN;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
reg [2 : 0] m_m_stateVec_2_rl;
|
|
wire [2 : 0] m_m_stateVec_2_rl$D_IN;
|
|
wire m_m_stateVec_2_rl$EN;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
reg [2 : 0] m_m_stateVec_3_rl;
|
|
wire [2 : 0] m_m_stateVec_3_rl$D_IN;
|
|
wire m_m_stateVec_3_rl$EN;
|
|
|
|
// register m_m_stateVec_4_rl
|
|
reg [2 : 0] m_m_stateVec_4_rl;
|
|
wire [2 : 0] m_m_stateVec_4_rl$D_IN;
|
|
wire m_m_stateVec_4_rl$EN;
|
|
|
|
// register m_m_stateVec_5_rl
|
|
reg [2 : 0] m_m_stateVec_5_rl;
|
|
wire [2 : 0] m_m_stateVec_5_rl$D_IN;
|
|
wire m_m_stateVec_5_rl$EN;
|
|
|
|
// register m_m_stateVec_6_rl
|
|
reg [2 : 0] m_m_stateVec_6_rl;
|
|
wire [2 : 0] m_m_stateVec_6_rl$D_IN;
|
|
wire m_m_stateVec_6_rl$EN;
|
|
|
|
// register m_m_stateVec_7_rl
|
|
reg [2 : 0] m_m_stateVec_7_rl;
|
|
wire [2 : 0] m_m_stateVec_7_rl$D_IN;
|
|
wire m_m_stateVec_7_rl$EN;
|
|
|
|
// register m_m_succValidVec_0_rl
|
|
reg m_m_succValidVec_0_rl;
|
|
wire m_m_succValidVec_0_rl$D_IN, m_m_succValidVec_0_rl$EN;
|
|
|
|
// register m_m_succValidVec_1_rl
|
|
reg m_m_succValidVec_1_rl;
|
|
wire m_m_succValidVec_1_rl$D_IN, m_m_succValidVec_1_rl$EN;
|
|
|
|
// register m_m_succValidVec_2_rl
|
|
reg m_m_succValidVec_2_rl;
|
|
wire m_m_succValidVec_2_rl$D_IN, m_m_succValidVec_2_rl$EN;
|
|
|
|
// register m_m_succValidVec_3_rl
|
|
reg m_m_succValidVec_3_rl;
|
|
wire m_m_succValidVec_3_rl$D_IN, m_m_succValidVec_3_rl$EN;
|
|
|
|
// register m_m_succValidVec_4_rl
|
|
reg m_m_succValidVec_4_rl;
|
|
wire m_m_succValidVec_4_rl$D_IN, m_m_succValidVec_4_rl$EN;
|
|
|
|
// register m_m_succValidVec_5_rl
|
|
reg m_m_succValidVec_5_rl;
|
|
wire m_m_succValidVec_5_rl$D_IN, m_m_succValidVec_5_rl$EN;
|
|
|
|
// register m_m_succValidVec_6_rl
|
|
reg m_m_succValidVec_6_rl;
|
|
wire m_m_succValidVec_6_rl$D_IN, m_m_succValidVec_6_rl$EN;
|
|
|
|
// register m_m_succValidVec_7_rl
|
|
reg m_m_succValidVec_7_rl;
|
|
wire m_m_succValidVec_7_rl$D_IN, m_m_succValidVec_7_rl$EN;
|
|
|
|
// ports of submodule m_m_emptyEntryQ
|
|
wire [2 : 0] m_m_emptyEntryQ$D_IN, m_m_emptyEntryQ$D_OUT;
|
|
wire m_m_emptyEntryQ$CLR,
|
|
m_m_emptyEntryQ$DEQ,
|
|
m_m_emptyEntryQ$EMPTY_N,
|
|
m_m_emptyEntryQ$ENQ,
|
|
m_m_emptyEntryQ$FULL_N;
|
|
|
|
// ports of submodule m_m_succFile
|
|
wire [2 : 0] m_m_succFile$ADDR_1,
|
|
m_m_succFile$ADDR_2,
|
|
m_m_succFile$ADDR_3,
|
|
m_m_succFile$ADDR_4,
|
|
m_m_succFile$ADDR_5,
|
|
m_m_succFile$ADDR_IN,
|
|
m_m_succFile$D_IN,
|
|
m_m_succFile$D_OUT_1;
|
|
wire m_m_succFile$WE;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_m_initEmptyEntry,
|
|
CAN_FIRE_RL_m_m_reqVec_0_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_1_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_2_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_3_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_4_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_5_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_6_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_7_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_0_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_1_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_2_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_3_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_4_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_5_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_6_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_7_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_0_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_1_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_2_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_3_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_4_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_5_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_6_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_7_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_0_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_1_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_2_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_3_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_4_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_5_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_6_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_7_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_0_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_1_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_2_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_3_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_4_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_5_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_6_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_7_canon,
|
|
CAN_FIRE_getEmptyEntryInit,
|
|
CAN_FIRE_pipelineResp_setResult,
|
|
CAN_FIRE_pipelineResp_setStateSlot,
|
|
CAN_FIRE_pipelineResp_setSucc,
|
|
CAN_FIRE_sendRsToC_releaseEntry,
|
|
CAN_FIRE_stuck_get,
|
|
WILL_FIRE_RL_m_m_initEmptyEntry,
|
|
WILL_FIRE_RL_m_m_reqVec_0_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_1_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_2_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_3_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_4_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_5_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_6_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_7_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_0_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_1_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_2_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_3_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_4_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_5_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_6_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_7_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_0_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_1_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_2_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_3_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_4_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_5_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_6_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_7_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_0_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_1_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_2_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_3_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_4_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_5_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_6_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_7_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_0_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_1_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_2_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_3_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_4_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_5_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_6_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_7_canon,
|
|
WILL_FIRE_getEmptyEntryInit,
|
|
WILL_FIRE_pipelineResp_setResult,
|
|
WILL_FIRE_pipelineResp_setStateSlot,
|
|
WILL_FIRE_pipelineResp_setSucc,
|
|
WILL_FIRE_sendRsToC_releaseEntry,
|
|
WILL_FIRE_stuck_get;
|
|
|
|
// remaining internal signals
|
|
reg [51 : 0] x__h37139, x__h37227, x__h37437;
|
|
reg [31 : 0] SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905;
|
|
reg [2 : 0] x__h37022, x__h37190, x__h37400;
|
|
reg SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946,
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973;
|
|
wire [65 : 0] IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306,
|
|
IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374,
|
|
IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442,
|
|
IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510,
|
|
IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578,
|
|
IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646,
|
|
IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714,
|
|
IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782;
|
|
wire [31 : 0] IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280,
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302,
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348,
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370,
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416,
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438,
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484,
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506,
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552,
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574,
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620,
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642,
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688,
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710,
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756,
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778;
|
|
wire [2 : 0] IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9,
|
|
IF_m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_ETC___d1151,
|
|
IF_m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_ETC___d1152,
|
|
IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19,
|
|
IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29,
|
|
IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39,
|
|
IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49,
|
|
IF_m_m_stateVec_4_rl_7_EQ_3_043_OR_m_m_stateVe_ETC___d1148,
|
|
IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59,
|
|
IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69,
|
|
IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79;
|
|
wire NOT_m_m_stateVec_0_rl_EQ_3_87_88_AND_NOT_m_m_s_ETC___d1098,
|
|
m_m_reqVec_0_rl_7_BITS_63_TO_6_95_EQ_pipelineR_ETC___d997,
|
|
m_m_reqVec_1_rl_7_BITS_63_TO_6_009_EQ_pipeline_ETC___d1010,
|
|
m_m_reqVec_2_rl_07_BITS_63_TO_6_023_EQ_pipelin_ETC___d1024,
|
|
m_m_reqVec_3_rl_17_BITS_63_TO_6_036_EQ_pipelin_ETC___d1037,
|
|
m_m_reqVec_4_rl_27_BITS_63_TO_6_051_EQ_pipelin_ETC___d1052,
|
|
m_m_reqVec_5_rl_37_BITS_63_TO_6_064_EQ_pipelin_ETC___d1065,
|
|
m_m_reqVec_6_rl_47_BITS_63_TO_6_078_EQ_pipelin_ETC___d1079,
|
|
m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_rl_ETC___d1103,
|
|
m_m_stateVec_1_rl_7_EQ_0_003_AND_m_m_stateVec__ETC___d1159,
|
|
m_m_stateVec_1_rl_7_EQ_3_001_OR_m_m_stateVec_1_ETC___d1108,
|
|
m_m_stateVec_2_rl_7_EQ_3_015_OR_m_m_stateVec_2_ETC___d1114,
|
|
m_m_stateVec_4_rl_7_EQ_3_043_OR_m_m_stateVec_4_ETC___d1126;
|
|
|
|
// actionvalue method getEmptyEntryInit
|
|
assign getEmptyEntryInit = m_m_emptyEntryQ$D_OUT ;
|
|
assign RDY_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign CAN_FIRE_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign WILL_FIRE_getEmptyEntryInit = EN_getEmptyEntryInit ;
|
|
|
|
// action method sendRsToC_releaseEntry
|
|
assign RDY_sendRsToC_releaseEntry = m_m_inited && m_m_emptyEntryQ$FULL_N ;
|
|
assign CAN_FIRE_sendRsToC_releaseEntry =
|
|
m_m_inited && m_m_emptyEntryQ$FULL_N ;
|
|
assign WILL_FIRE_sendRsToC_releaseEntry = EN_sendRsToC_releaseEntry ;
|
|
|
|
// value method sendRsToC_getResult
|
|
assign sendRsToC_getResult =
|
|
{ !SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893,
|
|
!SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899,
|
|
!SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 } ;
|
|
assign RDY_sendRsToC_getResult = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getRq
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0: sendRsToP_cRq_getRq = m_m_reqVec_0_rl;
|
|
3'd1: sendRsToP_cRq_getRq = m_m_reqVec_1_rl;
|
|
3'd2: sendRsToP_cRq_getRq = m_m_reqVec_2_rl;
|
|
3'd3: sendRsToP_cRq_getRq = m_m_reqVec_3_rl;
|
|
3'd4: sendRsToP_cRq_getRq = m_m_reqVec_4_rl;
|
|
3'd5: sendRsToP_cRq_getRq = m_m_reqVec_5_rl;
|
|
3'd6: sendRsToP_cRq_getRq = m_m_reqVec_6_rl;
|
|
3'd7: sendRsToP_cRq_getRq = m_m_reqVec_7_rl;
|
|
endcase
|
|
end
|
|
assign RDY_sendRsToP_cRq_getRq = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getSlot
|
|
assign sendRsToP_cRq_getSlot =
|
|
{ x__h37022,
|
|
x__h37139,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 } ;
|
|
assign RDY_sendRsToP_cRq_getSlot = 1'd1 ;
|
|
|
|
// value method sendRqToP_getRq
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0: sendRqToP_getRq = m_m_reqVec_0_rl;
|
|
3'd1: sendRqToP_getRq = m_m_reqVec_1_rl;
|
|
3'd2: sendRqToP_getRq = m_m_reqVec_2_rl;
|
|
3'd3: sendRqToP_getRq = m_m_reqVec_3_rl;
|
|
3'd4: sendRqToP_getRq = m_m_reqVec_4_rl;
|
|
3'd5: sendRqToP_getRq = m_m_reqVec_5_rl;
|
|
3'd6: sendRqToP_getRq = m_m_reqVec_6_rl;
|
|
3'd7: sendRqToP_getRq = m_m_reqVec_7_rl;
|
|
endcase
|
|
end
|
|
assign RDY_sendRqToP_getRq = 1'd1 ;
|
|
|
|
// value method sendRqToP_getSlot
|
|
assign sendRqToP_getSlot =
|
|
{ x__h37190,
|
|
x__h37227,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 } ;
|
|
assign RDY_sendRqToP_getSlot = 1'd1 ;
|
|
|
|
// value method pipelineResp_getState
|
|
always@(pipelineResp_getState_n or
|
|
m_m_stateVec_0_rl or
|
|
m_m_stateVec_1_rl or
|
|
m_m_stateVec_2_rl or
|
|
m_m_stateVec_3_rl or
|
|
m_m_stateVec_4_rl or
|
|
m_m_stateVec_5_rl or m_m_stateVec_6_rl or m_m_stateVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getState_n)
|
|
3'd0: pipelineResp_getState = m_m_stateVec_0_rl;
|
|
3'd1: pipelineResp_getState = m_m_stateVec_1_rl;
|
|
3'd2: pipelineResp_getState = m_m_stateVec_2_rl;
|
|
3'd3: pipelineResp_getState = m_m_stateVec_3_rl;
|
|
3'd4: pipelineResp_getState = m_m_stateVec_4_rl;
|
|
3'd5: pipelineResp_getState = m_m_stateVec_5_rl;
|
|
3'd6: pipelineResp_getState = m_m_stateVec_6_rl;
|
|
3'd7: pipelineResp_getState = m_m_stateVec_7_rl;
|
|
endcase
|
|
end
|
|
assign RDY_pipelineResp_getState = 1'd1 ;
|
|
|
|
// value method pipelineResp_getRq
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0: pipelineResp_getRq = m_m_reqVec_0_rl;
|
|
3'd1: pipelineResp_getRq = m_m_reqVec_1_rl;
|
|
3'd2: pipelineResp_getRq = m_m_reqVec_2_rl;
|
|
3'd3: pipelineResp_getRq = m_m_reqVec_3_rl;
|
|
3'd4: pipelineResp_getRq = m_m_reqVec_4_rl;
|
|
3'd5: pipelineResp_getRq = m_m_reqVec_5_rl;
|
|
3'd6: pipelineResp_getRq = m_m_reqVec_6_rl;
|
|
3'd7: pipelineResp_getRq = m_m_reqVec_7_rl;
|
|
endcase
|
|
end
|
|
assign RDY_pipelineResp_getRq = 1'd1 ;
|
|
|
|
// value method pipelineResp_getSlot
|
|
assign pipelineResp_getSlot =
|
|
{ x__h37400,
|
|
x__h37437,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 } ;
|
|
assign RDY_pipelineResp_getSlot = 1'd1 ;
|
|
|
|
// action method pipelineResp_setResult
|
|
assign RDY_pipelineResp_setResult = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setResult = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setResult = EN_pipelineResp_setResult ;
|
|
|
|
// action method pipelineResp_setStateSlot
|
|
assign RDY_pipelineResp_setStateSlot = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setStateSlot = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setStateSlot = EN_pipelineResp_setStateSlot ;
|
|
|
|
// value method pipelineResp_getSucc
|
|
assign pipelineResp_getSucc =
|
|
{ SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973,
|
|
m_m_succFile$D_OUT_1 } ;
|
|
assign RDY_pipelineResp_getSucc = 1'd1 ;
|
|
|
|
// action method pipelineResp_setSucc
|
|
assign RDY_pipelineResp_setSucc = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setSucc = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setSucc = EN_pipelineResp_setSucc ;
|
|
|
|
// value method pipelineResp_searchEndOfChain
|
|
assign pipelineResp_searchEndOfChain =
|
|
{ NOT_m_m_stateVec_0_rl_EQ_3_87_88_AND_NOT_m_m_s_ETC___d1098,
|
|
IF_m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_ETC___d1152 } ;
|
|
assign RDY_pipelineResp_searchEndOfChain = 1'd1 ;
|
|
|
|
// value method emptyForFlush
|
|
assign emptyForFlush =
|
|
m_m_stateVec_0_rl == 3'd0 &&
|
|
m_m_stateVec_1_rl_7_EQ_0_003_AND_m_m_stateVec__ETC___d1159 ;
|
|
assign RDY_emptyForFlush = 1'd1 ;
|
|
|
|
// actionvalue method stuck_get
|
|
assign stuck_get =
|
|
68'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
assign RDY_stuck_get = 1'd0 ;
|
|
assign CAN_FIRE_stuck_get = 1'd0 ;
|
|
assign WILL_FIRE_stuck_get = EN_stuck_get ;
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
SizedFIFO #(.p1width(32'd3),
|
|
.p2depth(32'd8),
|
|
.p3cntr_width(32'd3),
|
|
.guarded(32'd1)) m_m_emptyEntryQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_m_emptyEntryQ$D_IN),
|
|
.ENQ(m_m_emptyEntryQ$ENQ),
|
|
.DEQ(m_m_emptyEntryQ$DEQ),
|
|
.CLR(m_m_emptyEntryQ$CLR),
|
|
.D_OUT(m_m_emptyEntryQ$D_OUT),
|
|
.FULL_N(m_m_emptyEntryQ$FULL_N),
|
|
.EMPTY_N(m_m_emptyEntryQ$EMPTY_N));
|
|
|
|
// submodule m_m_succFile
|
|
RegFile #(.addr_width(32'd3),
|
|
.data_width(32'd3),
|
|
.lo(3'd0),
|
|
.hi(3'd7)) m_m_succFile(.CLK(CLK),
|
|
.ADDR_1(m_m_succFile$ADDR_1),
|
|
.ADDR_2(m_m_succFile$ADDR_2),
|
|
.ADDR_3(m_m_succFile$ADDR_3),
|
|
.ADDR_4(m_m_succFile$ADDR_4),
|
|
.ADDR_5(m_m_succFile$ADDR_5),
|
|
.ADDR_IN(m_m_succFile$ADDR_IN),
|
|
.D_IN(m_m_succFile$D_IN),
|
|
.WE(m_m_succFile$WE),
|
|
.D_OUT_1(m_m_succFile$D_OUT_1),
|
|
.D_OUT_2(),
|
|
.D_OUT_3(),
|
|
.D_OUT_4(),
|
|
.D_OUT_5());
|
|
|
|
// rule RL_m_m_initEmptyEntry
|
|
assign CAN_FIRE_RL_m_m_initEmptyEntry =
|
|
m_m_emptyEntryQ$FULL_N && !m_m_inited ;
|
|
assign WILL_FIRE_RL_m_m_initEmptyEntry = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// rule RL_m_m_stateVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
|
|
|
|
// inlined wires
|
|
assign m_m_stateVec_0_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd0 ;
|
|
assign m_m_stateVec_0_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd0 ;
|
|
assign m_m_stateVec_0_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd0 ;
|
|
assign m_m_stateVec_1_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd1 ;
|
|
assign m_m_stateVec_1_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd1 ;
|
|
assign m_m_stateVec_1_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd1 ;
|
|
assign m_m_stateVec_2_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd2 ;
|
|
assign m_m_stateVec_2_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd2 ;
|
|
assign m_m_stateVec_2_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd2 ;
|
|
assign m_m_stateVec_3_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd3 ;
|
|
assign m_m_stateVec_3_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd3 ;
|
|
assign m_m_stateVec_3_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd3 ;
|
|
assign m_m_stateVec_4_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd4 ;
|
|
assign m_m_stateVec_4_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd4 ;
|
|
assign m_m_stateVec_4_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd4 ;
|
|
assign m_m_stateVec_5_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd5 ;
|
|
assign m_m_stateVec_5_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd5 ;
|
|
assign m_m_stateVec_5_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd5 ;
|
|
assign m_m_stateVec_6_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd6 ;
|
|
assign m_m_stateVec_6_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd6 ;
|
|
assign m_m_stateVec_6_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd6 ;
|
|
assign m_m_stateVec_7_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd7 ;
|
|
assign m_m_stateVec_7_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd7 ;
|
|
assign m_m_stateVec_7_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd7 ;
|
|
assign m_m_slotVec_0_lat_2$wget =
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 } ;
|
|
assign m_m_resultVec_0_lat_0$wget = { 1'd1, pipelineResp_setResult_r } ;
|
|
assign m_m_resultVec_0_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd0 ;
|
|
assign m_m_resultVec_0_lat_2$wget =
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign m_m_resultVec_1_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd1 ;
|
|
assign m_m_resultVec_2_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd2 ;
|
|
assign m_m_resultVec_3_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd3 ;
|
|
assign m_m_resultVec_4_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd4 ;
|
|
assign m_m_resultVec_5_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd5 ;
|
|
assign m_m_resultVec_6_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd6 ;
|
|
assign m_m_resultVec_7_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd7 ;
|
|
assign m_m_succValidVec_0_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd0 ;
|
|
assign m_m_succValidVec_1_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd1 ;
|
|
assign m_m_succValidVec_2_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd2 ;
|
|
assign m_m_succValidVec_3_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd3 ;
|
|
assign m_m_succValidVec_4_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd4 ;
|
|
assign m_m_succValidVec_5_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd5 ;
|
|
assign m_m_succValidVec_6_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd6 ;
|
|
assign m_m_succValidVec_7_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd7 ;
|
|
|
|
// register m_m_initIdx
|
|
assign m_m_initIdx$D_IN = m_m_initIdx + 3'd1 ;
|
|
assign m_m_initIdx$EN = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// register m_m_inited
|
|
assign m_m_inited$D_IN = 1'd1 ;
|
|
assign m_m_inited$EN =
|
|
WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 3'd7 ;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
assign m_m_reqVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_0_rl ;
|
|
assign m_m_reqVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
assign m_m_reqVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_1_rl ;
|
|
assign m_m_reqVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
assign m_m_reqVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_2_rl ;
|
|
assign m_m_reqVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
assign m_m_reqVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_3_rl ;
|
|
assign m_m_reqVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_4_rl
|
|
assign m_m_reqVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_4_rl ;
|
|
assign m_m_reqVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_5_rl
|
|
assign m_m_reqVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_5_rl ;
|
|
assign m_m_reqVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_6_rl
|
|
assign m_m_reqVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_6_rl ;
|
|
assign m_m_reqVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_7_rl
|
|
assign m_m_reqVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_7_rl ;
|
|
assign m_m_reqVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_0_rl
|
|
assign m_m_resultVec_0_rl$D_IN =
|
|
{ m_m_stateVec_0_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[66] :
|
|
(m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_0_rl[66]),
|
|
IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306 } ;
|
|
assign m_m_resultVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_1_rl
|
|
assign m_m_resultVec_1_rl$D_IN =
|
|
{ m_m_stateVec_1_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[66] :
|
|
(m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_1_rl[66]),
|
|
IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374 } ;
|
|
assign m_m_resultVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_2_rl
|
|
assign m_m_resultVec_2_rl$D_IN =
|
|
{ m_m_stateVec_2_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[66] :
|
|
(m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_2_rl[66]),
|
|
IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442 } ;
|
|
assign m_m_resultVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_3_rl
|
|
assign m_m_resultVec_3_rl$D_IN =
|
|
{ m_m_stateVec_3_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[66] :
|
|
(m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_3_rl[66]),
|
|
IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510 } ;
|
|
assign m_m_resultVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_4_rl
|
|
assign m_m_resultVec_4_rl$D_IN =
|
|
{ m_m_stateVec_4_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[66] :
|
|
(m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_4_rl[66]),
|
|
IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578 } ;
|
|
assign m_m_resultVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_5_rl
|
|
assign m_m_resultVec_5_rl$D_IN =
|
|
{ m_m_stateVec_5_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[66] :
|
|
(m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_5_rl[66]),
|
|
IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646 } ;
|
|
assign m_m_resultVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_6_rl
|
|
assign m_m_resultVec_6_rl$D_IN =
|
|
{ m_m_stateVec_6_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[66] :
|
|
(m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_6_rl[66]),
|
|
IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714 } ;
|
|
assign m_m_resultVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_7_rl
|
|
assign m_m_resultVec_7_rl$D_IN =
|
|
{ m_m_stateVec_7_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[66] :
|
|
(m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_7_rl[66]),
|
|
IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782 } ;
|
|
assign m_m_resultVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_0_rl
|
|
assign m_m_slotVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
(m_m_stateVec_0_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_0_rl) ;
|
|
assign m_m_slotVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_1_rl
|
|
assign m_m_slotVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
(m_m_stateVec_1_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_1_rl) ;
|
|
assign m_m_slotVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_2_rl
|
|
assign m_m_slotVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
(m_m_stateVec_2_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_2_rl) ;
|
|
assign m_m_slotVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_3_rl
|
|
assign m_m_slotVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
(m_m_stateVec_3_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_3_rl) ;
|
|
assign m_m_slotVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_4_rl
|
|
assign m_m_slotVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
(m_m_stateVec_4_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_4_rl) ;
|
|
assign m_m_slotVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_5_rl
|
|
assign m_m_slotVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
(m_m_stateVec_5_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_5_rl) ;
|
|
assign m_m_slotVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_6_rl
|
|
assign m_m_slotVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
(m_m_stateVec_6_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_6_rl) ;
|
|
assign m_m_slotVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_7_rl
|
|
assign m_m_slotVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
(m_m_stateVec_7_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_7_rl) ;
|
|
assign m_m_slotVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
assign m_m_stateVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9 ;
|
|
assign m_m_stateVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
assign m_m_stateVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19 ;
|
|
assign m_m_stateVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
assign m_m_stateVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29 ;
|
|
assign m_m_stateVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
assign m_m_stateVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39 ;
|
|
assign m_m_stateVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_4_rl
|
|
assign m_m_stateVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49 ;
|
|
assign m_m_stateVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_5_rl
|
|
assign m_m_stateVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59 ;
|
|
assign m_m_stateVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_6_rl
|
|
assign m_m_stateVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69 ;
|
|
assign m_m_stateVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_7_rl
|
|
assign m_m_stateVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79 ;
|
|
assign m_m_stateVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_0_rl
|
|
assign m_m_succValidVec_0_rl$D_IN =
|
|
!m_m_stateVec_0_lat_2$whas &&
|
|
(m_m_succValidVec_0_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_0_rl) ;
|
|
assign m_m_succValidVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_1_rl
|
|
assign m_m_succValidVec_1_rl$D_IN =
|
|
!m_m_stateVec_1_lat_2$whas &&
|
|
(m_m_succValidVec_1_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_1_rl) ;
|
|
assign m_m_succValidVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_2_rl
|
|
assign m_m_succValidVec_2_rl$D_IN =
|
|
!m_m_stateVec_2_lat_2$whas &&
|
|
(m_m_succValidVec_2_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_2_rl) ;
|
|
assign m_m_succValidVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_3_rl
|
|
assign m_m_succValidVec_3_rl$D_IN =
|
|
!m_m_stateVec_3_lat_2$whas &&
|
|
(m_m_succValidVec_3_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_3_rl) ;
|
|
assign m_m_succValidVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_4_rl
|
|
assign m_m_succValidVec_4_rl$D_IN =
|
|
!m_m_stateVec_4_lat_2$whas &&
|
|
(m_m_succValidVec_4_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_4_rl) ;
|
|
assign m_m_succValidVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_5_rl
|
|
assign m_m_succValidVec_5_rl$D_IN =
|
|
!m_m_stateVec_5_lat_2$whas &&
|
|
(m_m_succValidVec_5_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_5_rl) ;
|
|
assign m_m_succValidVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_6_rl
|
|
assign m_m_succValidVec_6_rl$D_IN =
|
|
!m_m_stateVec_6_lat_2$whas &&
|
|
(m_m_succValidVec_6_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_6_rl) ;
|
|
assign m_m_succValidVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_7_rl
|
|
assign m_m_succValidVec_7_rl$D_IN =
|
|
!m_m_stateVec_7_lat_2$whas &&
|
|
(m_m_succValidVec_7_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_7_rl) ;
|
|
assign m_m_succValidVec_7_rl$EN = 1'd1 ;
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
assign m_m_emptyEntryQ$D_IN =
|
|
EN_sendRsToC_releaseEntry ?
|
|
sendRsToC_releaseEntry_n :
|
|
m_m_initIdx ;
|
|
assign m_m_emptyEntryQ$ENQ =
|
|
EN_sendRsToC_releaseEntry || WILL_FIRE_RL_m_m_initEmptyEntry ;
|
|
assign m_m_emptyEntryQ$DEQ = EN_getEmptyEntryInit ;
|
|
assign m_m_emptyEntryQ$CLR = 1'b0 ;
|
|
|
|
// submodule m_m_succFile
|
|
assign m_m_succFile$ADDR_1 = pipelineResp_getSucc_n ;
|
|
assign m_m_succFile$ADDR_2 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_3 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_4 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_5 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_IN = pipelineResp_setSucc_n ;
|
|
assign m_m_succFile$D_IN = pipelineResp_setSucc_succ[2:0] ;
|
|
assign m_m_succFile$WE = EN_pipelineResp_setSucc ;
|
|
|
|
// remaining internal signals
|
|
assign IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_0_rl[64:33] ;
|
|
assign IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_0_rl[31:0] ;
|
|
assign IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306 =
|
|
{ m_m_stateVec_0_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[65] :
|
|
(m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_0_rl[65]),
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[64:33] :
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280,
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[32] :
|
|
(m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_0_rl[32]),
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[31:0] :
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 } ;
|
|
assign IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_1_rl[64:33] ;
|
|
assign IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_1_rl[31:0] ;
|
|
assign IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374 =
|
|
{ m_m_stateVec_1_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[65] :
|
|
(m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_1_rl[65]),
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[64:33] :
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348,
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[32] :
|
|
(m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_1_rl[32]),
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[31:0] :
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 } ;
|
|
assign IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_2_rl[64:33] ;
|
|
assign IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_2_rl[31:0] ;
|
|
assign IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442 =
|
|
{ m_m_stateVec_2_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[65] :
|
|
(m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_2_rl[65]),
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[64:33] :
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416,
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[32] :
|
|
(m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_2_rl[32]),
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[31:0] :
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 } ;
|
|
assign IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_3_rl[64:33] ;
|
|
assign IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_3_rl[31:0] ;
|
|
assign IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510 =
|
|
{ m_m_stateVec_3_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[65] :
|
|
(m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_3_rl[65]),
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[64:33] :
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484,
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[32] :
|
|
(m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_3_rl[32]),
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[31:0] :
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 } ;
|
|
assign IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_4_rl[64:33] ;
|
|
assign IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_4_rl[31:0] ;
|
|
assign IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578 =
|
|
{ m_m_stateVec_4_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[65] :
|
|
(m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_4_rl[65]),
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[64:33] :
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552,
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[32] :
|
|
(m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_4_rl[32]),
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[31:0] :
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 } ;
|
|
assign IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_5_rl[64:33] ;
|
|
assign IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_5_rl[31:0] ;
|
|
assign IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646 =
|
|
{ m_m_stateVec_5_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[65] :
|
|
(m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_5_rl[65]),
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[64:33] :
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620,
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[32] :
|
|
(m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_5_rl[32]),
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[31:0] :
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 } ;
|
|
assign IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_6_rl[64:33] ;
|
|
assign IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_6_rl[31:0] ;
|
|
assign IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714 =
|
|
{ m_m_stateVec_6_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[65] :
|
|
(m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_6_rl[65]),
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[64:33] :
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688,
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[32] :
|
|
(m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_6_rl[32]),
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[31:0] :
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 } ;
|
|
assign IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_7_rl[64:33] ;
|
|
assign IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_7_rl[31:0] ;
|
|
assign IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782 =
|
|
{ m_m_stateVec_7_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[65] :
|
|
(m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_7_rl[65]),
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[64:33] :
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756,
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[32] :
|
|
(m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_7_rl[32]),
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
m_m_resultVec_0_lat_2$wget[31:0] :
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778 } ;
|
|
assign IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9 =
|
|
m_m_stateVec_0_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_0_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_0_rl) ;
|
|
assign IF_m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_ETC___d1151 =
|
|
(m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_rl_ETC___d1103 &&
|
|
m_m_stateVec_1_rl_7_EQ_3_001_OR_m_m_stateVec_1_ETC___d1108) ?
|
|
(m_m_stateVec_2_rl_7_EQ_3_015_OR_m_m_stateVec_2_ETC___d1114 ?
|
|
3'd3 :
|
|
3'd2) :
|
|
(m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_rl_ETC___d1103 ?
|
|
3'd1 :
|
|
3'd0) ;
|
|
assign IF_m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_ETC___d1152 =
|
|
(m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_rl_ETC___d1103 &&
|
|
m_m_stateVec_1_rl_7_EQ_3_001_OR_m_m_stateVec_1_ETC___d1108 &&
|
|
m_m_stateVec_2_rl_7_EQ_3_015_OR_m_m_stateVec_2_ETC___d1114 &&
|
|
(m_m_stateVec_3_rl == 3'd3 || m_m_stateVec_3_rl == 3'd0 ||
|
|
m_m_stateVec_3_rl == 3'd1 ||
|
|
!m_m_reqVec_3_rl_17_BITS_63_TO_6_036_EQ_pipelin_ETC___d1037 ||
|
|
m_m_succValidVec_3_rl)) ?
|
|
IF_m_m_stateVec_4_rl_7_EQ_3_043_OR_m_m_stateVe_ETC___d1148 :
|
|
IF_m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_ETC___d1151 ;
|
|
assign IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19 =
|
|
m_m_stateVec_1_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_1_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_1_rl) ;
|
|
assign IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29 =
|
|
m_m_stateVec_2_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_2_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_2_rl) ;
|
|
assign IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39 =
|
|
m_m_stateVec_3_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_3_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_3_rl) ;
|
|
assign IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49 =
|
|
m_m_stateVec_4_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_4_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_4_rl) ;
|
|
assign IF_m_m_stateVec_4_rl_7_EQ_3_043_OR_m_m_stateVe_ETC___d1148 =
|
|
(m_m_stateVec_4_rl_7_EQ_3_043_OR_m_m_stateVec_4_ETC___d1126 &&
|
|
(m_m_stateVec_5_rl == 3'd3 || m_m_stateVec_5_rl == 3'd0 ||
|
|
m_m_stateVec_5_rl == 3'd1 ||
|
|
!m_m_reqVec_5_rl_37_BITS_63_TO_6_064_EQ_pipelin_ETC___d1065 ||
|
|
m_m_succValidVec_5_rl)) ?
|
|
((m_m_stateVec_6_rl == 3'd3 || m_m_stateVec_6_rl == 3'd0 ||
|
|
m_m_stateVec_6_rl == 3'd1 ||
|
|
!m_m_reqVec_6_rl_47_BITS_63_TO_6_078_EQ_pipelin_ETC___d1079 ||
|
|
m_m_succValidVec_6_rl) ?
|
|
3'd7 :
|
|
3'd6) :
|
|
(m_m_stateVec_4_rl_7_EQ_3_043_OR_m_m_stateVec_4_ETC___d1126 ?
|
|
3'd5 :
|
|
3'd4) ;
|
|
assign IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59 =
|
|
m_m_stateVec_5_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_5_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_5_rl) ;
|
|
assign IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69 =
|
|
m_m_stateVec_6_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_6_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_6_rl) ;
|
|
assign IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79 =
|
|
m_m_stateVec_7_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_7_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_7_rl) ;
|
|
assign NOT_m_m_stateVec_0_rl_EQ_3_87_88_AND_NOT_m_m_s_ETC___d1098 =
|
|
m_m_stateVec_0_rl != 3'd3 && m_m_stateVec_0_rl != 3'd0 &&
|
|
m_m_stateVec_0_rl != 3'd1 &&
|
|
m_m_reqVec_0_rl_7_BITS_63_TO_6_95_EQ_pipelineR_ETC___d997 &&
|
|
!m_m_succValidVec_0_rl ||
|
|
m_m_stateVec_1_rl != 3'd3 && m_m_stateVec_1_rl != 3'd0 &&
|
|
m_m_stateVec_1_rl != 3'd1 &&
|
|
m_m_reqVec_1_rl_7_BITS_63_TO_6_009_EQ_pipeline_ETC___d1010 &&
|
|
!m_m_succValidVec_1_rl ||
|
|
m_m_stateVec_2_rl != 3'd3 && m_m_stateVec_2_rl != 3'd0 &&
|
|
m_m_stateVec_2_rl != 3'd1 &&
|
|
m_m_reqVec_2_rl_07_BITS_63_TO_6_023_EQ_pipelin_ETC___d1024 &&
|
|
!m_m_succValidVec_2_rl ||
|
|
m_m_stateVec_3_rl != 3'd3 && m_m_stateVec_3_rl != 3'd0 &&
|
|
m_m_stateVec_3_rl != 3'd1 &&
|
|
m_m_reqVec_3_rl_17_BITS_63_TO_6_036_EQ_pipelin_ETC___d1037 &&
|
|
!m_m_succValidVec_3_rl ||
|
|
m_m_stateVec_4_rl != 3'd3 && m_m_stateVec_4_rl != 3'd0 &&
|
|
m_m_stateVec_4_rl != 3'd1 &&
|
|
m_m_reqVec_4_rl_27_BITS_63_TO_6_051_EQ_pipelin_ETC___d1052 &&
|
|
!m_m_succValidVec_4_rl ||
|
|
m_m_stateVec_5_rl != 3'd3 && m_m_stateVec_5_rl != 3'd0 &&
|
|
m_m_stateVec_5_rl != 3'd1 &&
|
|
m_m_reqVec_5_rl_37_BITS_63_TO_6_064_EQ_pipelin_ETC___d1065 &&
|
|
!m_m_succValidVec_5_rl ||
|
|
m_m_stateVec_6_rl != 3'd3 && m_m_stateVec_6_rl != 3'd0 &&
|
|
m_m_stateVec_6_rl != 3'd1 &&
|
|
m_m_reqVec_6_rl_47_BITS_63_TO_6_078_EQ_pipelin_ETC___d1079 &&
|
|
!m_m_succValidVec_6_rl ||
|
|
m_m_stateVec_7_rl != 3'd3 && m_m_stateVec_7_rl != 3'd0 &&
|
|
m_m_stateVec_7_rl != 3'd1 &&
|
|
m_m_reqVec_7_rl[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] &&
|
|
!m_m_succValidVec_7_rl ;
|
|
assign m_m_reqVec_0_rl_7_BITS_63_TO_6_95_EQ_pipelineR_ETC___d997 =
|
|
m_m_reqVec_0_rl[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign m_m_reqVec_1_rl_7_BITS_63_TO_6_009_EQ_pipeline_ETC___d1010 =
|
|
m_m_reqVec_1_rl[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign m_m_reqVec_2_rl_07_BITS_63_TO_6_023_EQ_pipelin_ETC___d1024 =
|
|
m_m_reqVec_2_rl[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign m_m_reqVec_3_rl_17_BITS_63_TO_6_036_EQ_pipelin_ETC___d1037 =
|
|
m_m_reqVec_3_rl[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign m_m_reqVec_4_rl_27_BITS_63_TO_6_051_EQ_pipelin_ETC___d1052 =
|
|
m_m_reqVec_4_rl[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign m_m_reqVec_5_rl_37_BITS_63_TO_6_064_EQ_pipelin_ETC___d1065 =
|
|
m_m_reqVec_5_rl[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign m_m_reqVec_6_rl_47_BITS_63_TO_6_078_EQ_pipelin_ETC___d1079 =
|
|
m_m_reqVec_6_rl[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign m_m_stateVec_0_rl_EQ_3_87_OR_m_m_stateVec_0_rl_ETC___d1103 =
|
|
m_m_stateVec_0_rl == 3'd3 || m_m_stateVec_0_rl == 3'd0 ||
|
|
m_m_stateVec_0_rl == 3'd1 ||
|
|
!m_m_reqVec_0_rl_7_BITS_63_TO_6_95_EQ_pipelineR_ETC___d997 ||
|
|
m_m_succValidVec_0_rl ;
|
|
assign m_m_stateVec_1_rl_7_EQ_0_003_AND_m_m_stateVec__ETC___d1159 =
|
|
m_m_stateVec_1_rl == 3'd0 && m_m_stateVec_2_rl == 3'd0 &&
|
|
m_m_stateVec_3_rl == 3'd0 &&
|
|
m_m_stateVec_4_rl == 3'd0 &&
|
|
m_m_stateVec_5_rl == 3'd0 &&
|
|
m_m_stateVec_6_rl == 3'd0 &&
|
|
m_m_stateVec_7_rl == 3'd0 ;
|
|
assign m_m_stateVec_1_rl_7_EQ_3_001_OR_m_m_stateVec_1_ETC___d1108 =
|
|
m_m_stateVec_1_rl == 3'd3 || m_m_stateVec_1_rl == 3'd0 ||
|
|
m_m_stateVec_1_rl == 3'd1 ||
|
|
!m_m_reqVec_1_rl_7_BITS_63_TO_6_009_EQ_pipeline_ETC___d1010 ||
|
|
m_m_succValidVec_1_rl ;
|
|
assign m_m_stateVec_2_rl_7_EQ_3_015_OR_m_m_stateVec_2_ETC___d1114 =
|
|
m_m_stateVec_2_rl == 3'd3 || m_m_stateVec_2_rl == 3'd0 ||
|
|
m_m_stateVec_2_rl == 3'd1 ||
|
|
!m_m_reqVec_2_rl_07_BITS_63_TO_6_023_EQ_pipelin_ETC___d1024 ||
|
|
m_m_succValidVec_2_rl ;
|
|
assign m_m_stateVec_4_rl_7_EQ_3_043_OR_m_m_stateVec_4_ETC___d1126 =
|
|
m_m_stateVec_4_rl == 3'd3 || m_m_stateVec_4_rl == 3'd0 ||
|
|
m_m_stateVec_4_rl == 3'd1 ||
|
|
!m_m_reqVec_4_rl_27_BITS_63_TO_6_051_EQ_pipelin_ETC___d1052 ||
|
|
m_m_succValidVec_4_rl ;
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0: x__h37139 = m_m_slotVec_0_rl[52:1];
|
|
3'd1: x__h37139 = m_m_slotVec_1_rl[52:1];
|
|
3'd2: x__h37139 = m_m_slotVec_2_rl[52:1];
|
|
3'd3: x__h37139 = m_m_slotVec_3_rl[52:1];
|
|
3'd4: x__h37139 = m_m_slotVec_4_rl[52:1];
|
|
3'd5: x__h37139 = m_m_slotVec_5_rl[52:1];
|
|
3'd6: x__h37139 = m_m_slotVec_6_rl[52:1];
|
|
3'd7: x__h37139 = m_m_slotVec_7_rl[52:1];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0: x__h37227 = m_m_slotVec_0_rl[52:1];
|
|
3'd1: x__h37227 = m_m_slotVec_1_rl[52:1];
|
|
3'd2: x__h37227 = m_m_slotVec_2_rl[52:1];
|
|
3'd3: x__h37227 = m_m_slotVec_3_rl[52:1];
|
|
3'd4: x__h37227 = m_m_slotVec_4_rl[52:1];
|
|
3'd5: x__h37227 = m_m_slotVec_5_rl[52:1];
|
|
3'd6: x__h37227 = m_m_slotVec_6_rl[52:1];
|
|
3'd7: x__h37227 = m_m_slotVec_7_rl[52:1];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0: x__h37437 = m_m_slotVec_0_rl[52:1];
|
|
3'd1: x__h37437 = m_m_slotVec_1_rl[52:1];
|
|
3'd2: x__h37437 = m_m_slotVec_2_rl[52:1];
|
|
3'd3: x__h37437 = m_m_slotVec_3_rl[52:1];
|
|
3'd4: x__h37437 = m_m_slotVec_4_rl[52:1];
|
|
3'd5: x__h37437 = m_m_slotVec_5_rl[52:1];
|
|
3'd6: x__h37437 = m_m_slotVec_6_rl[52:1];
|
|
3'd7: x__h37437 = m_m_slotVec_7_rl[52:1];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0: x__h37022 = m_m_slotVec_0_rl[55:53];
|
|
3'd1: x__h37022 = m_m_slotVec_1_rl[55:53];
|
|
3'd2: x__h37022 = m_m_slotVec_2_rl[55:53];
|
|
3'd3: x__h37022 = m_m_slotVec_3_rl[55:53];
|
|
3'd4: x__h37022 = m_m_slotVec_4_rl[55:53];
|
|
3'd5: x__h37022 = m_m_slotVec_5_rl[55:53];
|
|
3'd6: x__h37022 = m_m_slotVec_6_rl[55:53];
|
|
3'd7: x__h37022 = m_m_slotVec_7_rl[55:53];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0: x__h37190 = m_m_slotVec_0_rl[55:53];
|
|
3'd1: x__h37190 = m_m_slotVec_1_rl[55:53];
|
|
3'd2: x__h37190 = m_m_slotVec_2_rl[55:53];
|
|
3'd3: x__h37190 = m_m_slotVec_3_rl[55:53];
|
|
3'd4: x__h37190 = m_m_slotVec_4_rl[55:53];
|
|
3'd5: x__h37190 = m_m_slotVec_5_rl[55:53];
|
|
3'd6: x__h37190 = m_m_slotVec_6_rl[55:53];
|
|
3'd7: x__h37190 = m_m_slotVec_7_rl[55:53];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0: x__h37400 = m_m_slotVec_0_rl[55:53];
|
|
3'd1: x__h37400 = m_m_slotVec_1_rl[55:53];
|
|
3'd2: x__h37400 = m_m_slotVec_2_rl[55:53];
|
|
3'd3: x__h37400 = m_m_slotVec_3_rl[55:53];
|
|
3'd4: x__h37400 = m_m_slotVec_4_rl[55:53];
|
|
3'd5: x__h37400 = m_m_slotVec_5_rl[55:53];
|
|
3'd6: x__h37400 = m_m_slotVec_6_rl[55:53];
|
|
3'd7: x__h37400 = m_m_slotVec_7_rl[55:53];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSucc_n or
|
|
m_m_succValidVec_0_rl or
|
|
m_m_succValidVec_1_rl or
|
|
m_m_succValidVec_2_rl or
|
|
m_m_succValidVec_3_rl or
|
|
m_m_succValidVec_4_rl or
|
|
m_m_succValidVec_5_rl or
|
|
m_m_succValidVec_6_rl or m_m_succValidVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSucc_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973 =
|
|
m_m_succValidVec_0_rl;
|
|
3'd1:
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973 =
|
|
m_m_succValidVec_1_rl;
|
|
3'd2:
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973 =
|
|
m_m_succValidVec_2_rl;
|
|
3'd3:
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973 =
|
|
m_m_succValidVec_3_rl;
|
|
3'd4:
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973 =
|
|
m_m_succValidVec_4_rl;
|
|
3'd5:
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973 =
|
|
m_m_succValidVec_5_rl;
|
|
3'd6:
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973 =
|
|
m_m_succValidVec_6_rl;
|
|
3'd7:
|
|
SEL_ARR_m_m_succValidVec_0_rl_91_m_m_succValid_ETC___d973 =
|
|
m_m_succValidVec_7_rl;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 =
|
|
m_m_slotVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 =
|
|
m_m_slotVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 =
|
|
m_m_slotVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 =
|
|
m_m_slotVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 =
|
|
m_m_slotVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 =
|
|
m_m_slotVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 =
|
|
m_m_slotVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d939 =
|
|
m_m_slotVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 =
|
|
m_m_slotVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 =
|
|
m_m_slotVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 =
|
|
m_m_slotVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 =
|
|
m_m_slotVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 =
|
|
m_m_slotVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 =
|
|
m_m_slotVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 =
|
|
m_m_slotVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d942 =
|
|
m_m_slotVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 =
|
|
m_m_slotVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 =
|
|
m_m_slotVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 =
|
|
m_m_slotVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 =
|
|
m_m_slotVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 =
|
|
m_m_slotVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 =
|
|
m_m_slotVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 =
|
|
m_m_slotVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_30_m_m_slotV_ETC___d946 =
|
|
m_m_slotVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
m_m_resultVec_0_lat_0$whas or
|
|
m_m_resultVec_0_lat_0$wget or
|
|
m_m_resultVec_0_rl or
|
|
m_m_resultVec_1_lat_0$whas or
|
|
m_m_resultVec_1_rl or
|
|
m_m_resultVec_2_lat_0$whas or
|
|
m_m_resultVec_2_rl or
|
|
m_m_resultVec_3_lat_0$whas or
|
|
m_m_resultVec_3_rl or
|
|
m_m_resultVec_4_lat_0$whas or
|
|
m_m_resultVec_4_rl or
|
|
m_m_resultVec_5_lat_0$whas or
|
|
m_m_resultVec_5_rl or
|
|
m_m_resultVec_6_lat_0$whas or
|
|
m_m_resultVec_6_rl or
|
|
m_m_resultVec_7_lat_0$whas or m_m_resultVec_7_rl)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_0_rl[66];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_1_rl[66];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_2_rl[66];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_3_rl[66];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_4_rl[66];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_5_rl[66];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_6_rl[66];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d893 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_7_rl[66];
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
m_m_resultVec_0_lat_0$whas or
|
|
m_m_resultVec_0_lat_0$wget or
|
|
m_m_resultVec_0_rl or
|
|
m_m_resultVec_1_lat_0$whas or
|
|
m_m_resultVec_1_rl or
|
|
m_m_resultVec_2_lat_0$whas or
|
|
m_m_resultVec_2_rl or
|
|
m_m_resultVec_3_lat_0$whas or
|
|
m_m_resultVec_3_rl or
|
|
m_m_resultVec_4_lat_0$whas or
|
|
m_m_resultVec_4_rl or
|
|
m_m_resultVec_5_lat_0$whas or
|
|
m_m_resultVec_5_rl or
|
|
m_m_resultVec_6_lat_0$whas or
|
|
m_m_resultVec_6_rl or
|
|
m_m_resultVec_7_lat_0$whas or m_m_resultVec_7_rl)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_0_rl[65];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_1_rl[65];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_2_rl[65];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_3_rl[65];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_4_rl[65];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_5_rl[65];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_6_rl[65];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d896 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_7_rl[65];
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
m_m_resultVec_0_lat_0$whas or
|
|
m_m_resultVec_0_lat_0$wget or
|
|
m_m_resultVec_0_rl or
|
|
m_m_resultVec_1_lat_0$whas or
|
|
m_m_resultVec_1_rl or
|
|
m_m_resultVec_2_lat_0$whas or
|
|
m_m_resultVec_2_rl or
|
|
m_m_resultVec_3_lat_0$whas or
|
|
m_m_resultVec_3_rl or
|
|
m_m_resultVec_4_lat_0$whas or
|
|
m_m_resultVec_4_rl or
|
|
m_m_resultVec_5_lat_0$whas or
|
|
m_m_resultVec_5_rl or
|
|
m_m_resultVec_6_lat_0$whas or
|
|
m_m_resultVec_6_rl or
|
|
m_m_resultVec_7_lat_0$whas or m_m_resultVec_7_rl)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_0_rl[32];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_1_rl[32];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_2_rl[32];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_3_rl[32];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_4_rl[32];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_5_rl[32];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_6_rl[32];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d902 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_7_rl[32];
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280 or
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348 or
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416 or
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484 or
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552 or
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620 or
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688 or
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899 =
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899 =
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899 =
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899 =
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899 =
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899 =
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899 =
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d899 =
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756;
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 or
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 or
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 or
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 or
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 or
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 or
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 or
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 =
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 =
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 =
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 =
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 =
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 =
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 =
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d905 =
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_resultVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_m_resultVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_m_resultVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_m_resultVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_m_resultVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_m_resultVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_m_resultVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_m_resultVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_initIdx$EN)
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY m_m_initIdx$D_IN;
|
|
if (m_m_inited$EN)
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY m_m_inited$D_IN;
|
|
if (m_m_reqVec_0_rl$EN)
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_0_rl$D_IN;
|
|
if (m_m_reqVec_1_rl$EN)
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_1_rl$D_IN;
|
|
if (m_m_reqVec_2_rl$EN)
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_2_rl$D_IN;
|
|
if (m_m_reqVec_3_rl$EN)
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_3_rl$D_IN;
|
|
if (m_m_reqVec_4_rl$EN)
|
|
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_4_rl$D_IN;
|
|
if (m_m_reqVec_5_rl$EN)
|
|
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_5_rl$D_IN;
|
|
if (m_m_reqVec_6_rl$EN)
|
|
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_6_rl$D_IN;
|
|
if (m_m_reqVec_7_rl$EN)
|
|
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_7_rl$D_IN;
|
|
if (m_m_resultVec_0_rl$EN)
|
|
m_m_resultVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_0_rl$D_IN;
|
|
if (m_m_resultVec_1_rl$EN)
|
|
m_m_resultVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_1_rl$D_IN;
|
|
if (m_m_resultVec_2_rl$EN)
|
|
m_m_resultVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_2_rl$D_IN;
|
|
if (m_m_resultVec_3_rl$EN)
|
|
m_m_resultVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_3_rl$D_IN;
|
|
if (m_m_resultVec_4_rl$EN)
|
|
m_m_resultVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_4_rl$D_IN;
|
|
if (m_m_resultVec_5_rl$EN)
|
|
m_m_resultVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_5_rl$D_IN;
|
|
if (m_m_resultVec_6_rl$EN)
|
|
m_m_resultVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_6_rl$D_IN;
|
|
if (m_m_resultVec_7_rl$EN)
|
|
m_m_resultVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_7_rl$D_IN;
|
|
if (m_m_slotVec_0_rl$EN)
|
|
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_0_rl$D_IN;
|
|
if (m_m_slotVec_1_rl$EN)
|
|
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_1_rl$D_IN;
|
|
if (m_m_slotVec_2_rl$EN)
|
|
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_2_rl$D_IN;
|
|
if (m_m_slotVec_3_rl$EN)
|
|
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_3_rl$D_IN;
|
|
if (m_m_slotVec_4_rl$EN)
|
|
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_4_rl$D_IN;
|
|
if (m_m_slotVec_5_rl$EN)
|
|
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_5_rl$D_IN;
|
|
if (m_m_slotVec_6_rl$EN)
|
|
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_6_rl$D_IN;
|
|
if (m_m_slotVec_7_rl$EN)
|
|
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_7_rl$D_IN;
|
|
if (m_m_stateVec_0_rl$EN)
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_0_rl$D_IN;
|
|
if (m_m_stateVec_1_rl$EN)
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_1_rl$D_IN;
|
|
if (m_m_stateVec_2_rl$EN)
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_2_rl$D_IN;
|
|
if (m_m_stateVec_3_rl$EN)
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_3_rl$D_IN;
|
|
if (m_m_stateVec_4_rl$EN)
|
|
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_4_rl$D_IN;
|
|
if (m_m_stateVec_5_rl$EN)
|
|
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_5_rl$D_IN;
|
|
if (m_m_stateVec_6_rl$EN)
|
|
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_6_rl$D_IN;
|
|
if (m_m_stateVec_7_rl$EN)
|
|
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_7_rl$D_IN;
|
|
if (m_m_succValidVec_0_rl$EN)
|
|
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_0_rl$D_IN;
|
|
if (m_m_succValidVec_1_rl$EN)
|
|
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_1_rl$D_IN;
|
|
if (m_m_succValidVec_2_rl$EN)
|
|
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_2_rl$D_IN;
|
|
if (m_m_succValidVec_3_rl$EN)
|
|
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_3_rl$D_IN;
|
|
if (m_m_succValidVec_4_rl$EN)
|
|
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_4_rl$D_IN;
|
|
if (m_m_succValidVec_5_rl$EN)
|
|
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_5_rl$D_IN;
|
|
if (m_m_succValidVec_6_rl$EN)
|
|
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_6_rl$D_IN;
|
|
if (m_m_succValidVec_7_rl$EN)
|
|
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_7_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_initIdx = 3'h2;
|
|
m_m_inited = 1'h0;
|
|
m_m_reqVec_0_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_4_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_5_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_6_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_7_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_0_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_1_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_2_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_3_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_4_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_5_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_6_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_7_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_slotVec_0_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_1_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_2_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_3_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_4_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_5_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_6_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_7_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_stateVec_0_rl = 3'h2;
|
|
m_m_stateVec_1_rl = 3'h2;
|
|
m_m_stateVec_2_rl = 3'h2;
|
|
m_m_stateVec_3_rl = 3'h2;
|
|
m_m_stateVec_4_rl = 3'h2;
|
|
m_m_stateVec_5_rl = 3'h2;
|
|
m_m_stateVec_6_rl = 3'h2;
|
|
m_m_stateVec_7_rl = 3'h2;
|
|
m_m_succValidVec_0_rl = 1'h0;
|
|
m_m_succValidVec_1_rl = 1'h0;
|
|
m_m_succValidVec_2_rl = 1'h0;
|
|
m_m_succValidVec_3_rl = 1'h0;
|
|
m_m_succValidVec_4_rl = 1'h0;
|
|
m_m_succValidVec_5_rl = 1'h0;
|
|
m_m_succValidVec_6_rl = 1'h0;
|
|
m_m_succValidVec_7_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkICRqMshrWrapper
|
|
|