5417 lines
212 KiB
Verilog
5417 lines
212 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:28:37 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// flush_done O 1
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// RDY_flush_done O 1 const
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// RDY_flush O 1
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// RDY_updateVMInfo O 1 const
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// noPendingReq O 1
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// RDY_noPendingReq O 1 const
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// RDY_to_proc_request_put O 1
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// to_proc_response_get O 70
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// RDY_to_proc_response_get O 1
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// toParent_rqToP_notEmpty O 1
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// RDY_toParent_rqToP_notEmpty O 1 const
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// RDY_toParent_rqToP_deq O 1
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// toParent_rqToP_first O 27
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// RDY_toParent_rqToP_first O 1
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// toParent_rsFromP_notFull O 1
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// RDY_toParent_rsFromP_notFull O 1 const
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// RDY_toParent_rsFromP_enq O 1
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// RDY_toParent_flush_request_get O 1
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// RDY_toParent_flush_response_put O 1
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// RDY_perf_setStatus O 1 const
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// RDY_perf_req O 1
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// perf_resp O 67
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// RDY_perf_resp O 1
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// perf_respValid O 1
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// RDY_perf_respValid O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// updateVMInfo_vm I 49 reg
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// to_proc_request_put I 64
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// toParent_rsFromP_enq_x I 81
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// perf_setStatus_doStats I 1 unused
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// perf_req_r I 3
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// EN_flush I 1
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// EN_updateVMInfo I 1
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// EN_to_proc_request_put I 1
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// EN_toParent_rqToP_deq I 1
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// EN_toParent_rsFromP_enq I 1
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// EN_toParent_flush_request_get I 1
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// EN_toParent_flush_response_put I 1
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// EN_perf_setStatus I 1 unused
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// EN_perf_req I 1
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// EN_to_proc_response_get I 1
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// EN_perf_resp I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkITlb(CLK,
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RST_N,
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flush_done,
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RDY_flush_done,
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EN_flush,
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RDY_flush,
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updateVMInfo_vm,
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EN_updateVMInfo,
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RDY_updateVMInfo,
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noPendingReq,
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RDY_noPendingReq,
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to_proc_request_put,
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EN_to_proc_request_put,
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RDY_to_proc_request_put,
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EN_to_proc_response_get,
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to_proc_response_get,
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RDY_to_proc_response_get,
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toParent_rqToP_notEmpty,
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RDY_toParent_rqToP_notEmpty,
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EN_toParent_rqToP_deq,
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RDY_toParent_rqToP_deq,
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toParent_rqToP_first,
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RDY_toParent_rqToP_first,
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toParent_rsFromP_notFull,
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RDY_toParent_rsFromP_notFull,
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toParent_rsFromP_enq_x,
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EN_toParent_rsFromP_enq,
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RDY_toParent_rsFromP_enq,
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EN_toParent_flush_request_get,
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RDY_toParent_flush_request_get,
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EN_toParent_flush_response_put,
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RDY_toParent_flush_response_put,
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perf_setStatus_doStats,
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EN_perf_setStatus,
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RDY_perf_setStatus,
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perf_req_r,
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EN_perf_req,
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RDY_perf_req,
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EN_perf_resp,
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perf_resp,
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RDY_perf_resp,
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perf_respValid,
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RDY_perf_respValid);
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input CLK;
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input RST_N;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// action method updateVMInfo
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input [48 : 0] updateVMInfo_vm;
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input EN_updateVMInfo;
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output RDY_updateVMInfo;
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// value method noPendingReq
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output noPendingReq;
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output RDY_noPendingReq;
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// action method to_proc_request_put
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input [63 : 0] to_proc_request_put;
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input EN_to_proc_request_put;
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output RDY_to_proc_request_put;
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// actionvalue method to_proc_response_get
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input EN_to_proc_response_get;
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output [69 : 0] to_proc_response_get;
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output RDY_to_proc_response_get;
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// value method toParent_rqToP_notEmpty
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output toParent_rqToP_notEmpty;
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output RDY_toParent_rqToP_notEmpty;
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// action method toParent_rqToP_deq
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input EN_toParent_rqToP_deq;
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output RDY_toParent_rqToP_deq;
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// value method toParent_rqToP_first
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output [26 : 0] toParent_rqToP_first;
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output RDY_toParent_rqToP_first;
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// value method toParent_rsFromP_notFull
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output toParent_rsFromP_notFull;
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output RDY_toParent_rsFromP_notFull;
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// action method toParent_rsFromP_enq
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input [80 : 0] toParent_rsFromP_enq_x;
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input EN_toParent_rsFromP_enq;
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output RDY_toParent_rsFromP_enq;
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// action method toParent_flush_request_get
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input EN_toParent_flush_request_get;
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output RDY_toParent_flush_request_get;
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// action method toParent_flush_response_put
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input EN_toParent_flush_response_put;
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output RDY_toParent_flush_response_put;
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// action method perf_setStatus
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input perf_setStatus_doStats;
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input EN_perf_setStatus;
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output RDY_perf_setStatus;
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// action method perf_req
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input [2 : 0] perf_req_r;
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input EN_perf_req;
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output RDY_perf_req;
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// actionvalue method perf_resp
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input EN_perf_resp;
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output [66 : 0] perf_resp;
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output RDY_perf_resp;
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// value method perf_respValid
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output perf_respValid;
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output RDY_perf_respValid;
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// signals for module outputs
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reg [26 : 0] toParent_rqToP_first;
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wire [69 : 0] to_proc_response_get;
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wire [66 : 0] perf_resp;
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wire RDY_flush,
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RDY_flush_done,
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RDY_noPendingReq,
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RDY_perf_req,
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RDY_perf_resp,
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RDY_perf_respValid,
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RDY_perf_setStatus,
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RDY_toParent_flush_request_get,
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RDY_toParent_flush_response_put,
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RDY_toParent_rqToP_deq,
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RDY_toParent_rqToP_first,
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RDY_toParent_rqToP_notEmpty,
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RDY_toParent_rsFromP_enq,
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RDY_toParent_rsFromP_notFull,
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RDY_to_proc_request_put,
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RDY_to_proc_response_get,
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RDY_updateVMInfo,
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flush_done,
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noPendingReq,
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perf_respValid,
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toParent_rqToP_notEmpty,
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toParent_rsFromP_notFull;
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// inlined wires
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wire [81 : 0] rsFromPQ_enqReq_lat_0$wget, rsFromPQ_enqReq_lat_2$wget;
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wire [70 : 0] hitQ_enqReq_lat_0$wget, hitQ_enqReq_lat_2$wget;
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wire [27 : 0] rqToPQ_enqReq_lat_0$wget, rqToPQ_enqReq_lat_2$wget;
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wire [5 : 0] tlb_m_updRepIdx_lat_0$wget, tlb_m_updRepIdx_lat_1$wget;
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wire [3 : 0] perfReqQ_enqReq_lat_0$wget, perfReqQ_enqReq_lat_2$wget;
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wire hitQ_enqReq_lat_0$whas,
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tlb_m_lruBit_lat_0$whas,
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tlb_m_updRepIdx_lat_0$whas,
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tlb_m_updRepIdx_lat_1$whas;
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// register flushRqToPQ_clearReq_rl
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reg flushRqToPQ_clearReq_rl;
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wire flushRqToPQ_clearReq_rl$D_IN, flushRqToPQ_clearReq_rl$EN;
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// register flushRqToPQ_deqReq_rl
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reg flushRqToPQ_deqReq_rl;
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wire flushRqToPQ_deqReq_rl$D_IN, flushRqToPQ_deqReq_rl$EN;
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// register flushRqToPQ_empty
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reg flushRqToPQ_empty;
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wire flushRqToPQ_empty$D_IN, flushRqToPQ_empty$EN;
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// register flushRqToPQ_enqReq_rl
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reg flushRqToPQ_enqReq_rl;
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wire flushRqToPQ_enqReq_rl$D_IN, flushRqToPQ_enqReq_rl$EN;
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// register flushRqToPQ_full
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reg flushRqToPQ_full;
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wire flushRqToPQ_full$D_IN, flushRqToPQ_full$EN;
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// register flushRsFromPQ_clearReq_rl
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reg flushRsFromPQ_clearReq_rl;
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wire flushRsFromPQ_clearReq_rl$D_IN, flushRsFromPQ_clearReq_rl$EN;
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// register flushRsFromPQ_deqReq_rl
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reg flushRsFromPQ_deqReq_rl;
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wire flushRsFromPQ_deqReq_rl$D_IN, flushRsFromPQ_deqReq_rl$EN;
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// register flushRsFromPQ_empty
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reg flushRsFromPQ_empty;
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wire flushRsFromPQ_empty$D_IN, flushRsFromPQ_empty$EN;
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// register flushRsFromPQ_enqReq_rl
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reg flushRsFromPQ_enqReq_rl;
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wire flushRsFromPQ_enqReq_rl$D_IN, flushRsFromPQ_enqReq_rl$EN;
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// register flushRsFromPQ_full
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reg flushRsFromPQ_full;
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wire flushRsFromPQ_full$D_IN, flushRsFromPQ_full$EN;
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// register hitQ_clearReq_rl
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reg hitQ_clearReq_rl;
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wire hitQ_clearReq_rl$D_IN, hitQ_clearReq_rl$EN;
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// register hitQ_data_0
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reg [69 : 0] hitQ_data_0;
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wire [69 : 0] hitQ_data_0$D_IN;
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wire hitQ_data_0$EN;
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// register hitQ_data_1
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reg [69 : 0] hitQ_data_1;
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wire [69 : 0] hitQ_data_1$D_IN;
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wire hitQ_data_1$EN;
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// register hitQ_deqP
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reg hitQ_deqP;
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wire hitQ_deqP$D_IN, hitQ_deqP$EN;
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// register hitQ_deqReq_rl
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reg hitQ_deqReq_rl;
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wire hitQ_deqReq_rl$D_IN, hitQ_deqReq_rl$EN;
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// register hitQ_empty
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reg hitQ_empty;
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wire hitQ_empty$D_IN, hitQ_empty$EN;
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// register hitQ_enqP
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reg hitQ_enqP;
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wire hitQ_enqP$D_IN, hitQ_enqP$EN;
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// register hitQ_enqReq_rl
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reg [70 : 0] hitQ_enqReq_rl;
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wire [70 : 0] hitQ_enqReq_rl$D_IN;
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wire hitQ_enqReq_rl$EN;
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// register hitQ_full
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reg hitQ_full;
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wire hitQ_full$D_IN, hitQ_full$EN;
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// register miss
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reg [64 : 0] miss;
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wire [64 : 0] miss$D_IN;
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wire miss$EN;
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// register needFlush
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reg needFlush;
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wire needFlush$D_IN, needFlush$EN;
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// register perfReqQ_clearReq_rl
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reg perfReqQ_clearReq_rl;
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wire perfReqQ_clearReq_rl$D_IN, perfReqQ_clearReq_rl$EN;
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// register perfReqQ_data_0
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reg [2 : 0] perfReqQ_data_0;
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wire [2 : 0] perfReqQ_data_0$D_IN;
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wire perfReqQ_data_0$EN;
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// register perfReqQ_deqReq_rl
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reg perfReqQ_deqReq_rl;
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wire perfReqQ_deqReq_rl$D_IN, perfReqQ_deqReq_rl$EN;
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// register perfReqQ_empty
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reg perfReqQ_empty;
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wire perfReqQ_empty$D_IN, perfReqQ_empty$EN;
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// register perfReqQ_enqReq_rl
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reg [3 : 0] perfReqQ_enqReq_rl;
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wire [3 : 0] perfReqQ_enqReq_rl$D_IN;
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wire perfReqQ_enqReq_rl$EN;
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// register perfReqQ_full
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reg perfReqQ_full;
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wire perfReqQ_full$D_IN, perfReqQ_full$EN;
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// register rqToPQ_clearReq_rl
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reg rqToPQ_clearReq_rl;
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wire rqToPQ_clearReq_rl$D_IN, rqToPQ_clearReq_rl$EN;
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// register rqToPQ_data_0
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reg [26 : 0] rqToPQ_data_0;
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wire [26 : 0] rqToPQ_data_0$D_IN;
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wire rqToPQ_data_0$EN;
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// register rqToPQ_data_1
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reg [26 : 0] rqToPQ_data_1;
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wire [26 : 0] rqToPQ_data_1$D_IN;
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wire rqToPQ_data_1$EN;
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// register rqToPQ_deqP
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reg rqToPQ_deqP;
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wire rqToPQ_deqP$D_IN, rqToPQ_deqP$EN;
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// register rqToPQ_deqReq_rl
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reg rqToPQ_deqReq_rl;
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wire rqToPQ_deqReq_rl$D_IN, rqToPQ_deqReq_rl$EN;
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// register rqToPQ_empty
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reg rqToPQ_empty;
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wire rqToPQ_empty$D_IN, rqToPQ_empty$EN;
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// register rqToPQ_enqP
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reg rqToPQ_enqP;
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wire rqToPQ_enqP$D_IN, rqToPQ_enqP$EN;
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// register rqToPQ_enqReq_rl
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reg [27 : 0] rqToPQ_enqReq_rl;
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wire [27 : 0] rqToPQ_enqReq_rl$D_IN;
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wire rqToPQ_enqReq_rl$EN;
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// register rqToPQ_full
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reg rqToPQ_full;
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wire rqToPQ_full$D_IN, rqToPQ_full$EN;
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// register rsFromPQ_clearReq_rl
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reg rsFromPQ_clearReq_rl;
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wire rsFromPQ_clearReq_rl$D_IN, rsFromPQ_clearReq_rl$EN;
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// register rsFromPQ_data_0
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reg [80 : 0] rsFromPQ_data_0;
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wire [80 : 0] rsFromPQ_data_0$D_IN;
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wire rsFromPQ_data_0$EN;
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// register rsFromPQ_data_1
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reg [80 : 0] rsFromPQ_data_1;
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wire [80 : 0] rsFromPQ_data_1$D_IN;
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wire rsFromPQ_data_1$EN;
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// register rsFromPQ_deqP
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reg rsFromPQ_deqP;
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wire rsFromPQ_deqP$D_IN, rsFromPQ_deqP$EN;
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// register rsFromPQ_deqReq_rl
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reg rsFromPQ_deqReq_rl;
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wire rsFromPQ_deqReq_rl$D_IN, rsFromPQ_deqReq_rl$EN;
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// register rsFromPQ_empty
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reg rsFromPQ_empty;
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wire rsFromPQ_empty$D_IN, rsFromPQ_empty$EN;
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// register rsFromPQ_enqP
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reg rsFromPQ_enqP;
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wire rsFromPQ_enqP$D_IN, rsFromPQ_enqP$EN;
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// register rsFromPQ_enqReq_rl
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reg [81 : 0] rsFromPQ_enqReq_rl;
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wire [81 : 0] rsFromPQ_enqReq_rl$D_IN;
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wire rsFromPQ_enqReq_rl$EN;
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// register rsFromPQ_full
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reg rsFromPQ_full;
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wire rsFromPQ_full$D_IN, rsFromPQ_full$EN;
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// register tlb_m_entryVec_0
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reg [79 : 0] tlb_m_entryVec_0;
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wire [79 : 0] tlb_m_entryVec_0$D_IN;
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wire tlb_m_entryVec_0$EN;
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// register tlb_m_entryVec_1
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reg [79 : 0] tlb_m_entryVec_1;
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wire [79 : 0] tlb_m_entryVec_1$D_IN;
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wire tlb_m_entryVec_1$EN;
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// register tlb_m_entryVec_10
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reg [79 : 0] tlb_m_entryVec_10;
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wire [79 : 0] tlb_m_entryVec_10$D_IN;
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wire tlb_m_entryVec_10$EN;
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// register tlb_m_entryVec_11
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reg [79 : 0] tlb_m_entryVec_11;
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wire [79 : 0] tlb_m_entryVec_11$D_IN;
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wire tlb_m_entryVec_11$EN;
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// register tlb_m_entryVec_12
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reg [79 : 0] tlb_m_entryVec_12;
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wire [79 : 0] tlb_m_entryVec_12$D_IN;
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wire tlb_m_entryVec_12$EN;
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// register tlb_m_entryVec_13
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reg [79 : 0] tlb_m_entryVec_13;
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wire [79 : 0] tlb_m_entryVec_13$D_IN;
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wire tlb_m_entryVec_13$EN;
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// register tlb_m_entryVec_14
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reg [79 : 0] tlb_m_entryVec_14;
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wire [79 : 0] tlb_m_entryVec_14$D_IN;
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wire tlb_m_entryVec_14$EN;
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// register tlb_m_entryVec_15
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reg [79 : 0] tlb_m_entryVec_15;
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wire [79 : 0] tlb_m_entryVec_15$D_IN;
|
|
wire tlb_m_entryVec_15$EN;
|
|
|
|
// register tlb_m_entryVec_16
|
|
reg [79 : 0] tlb_m_entryVec_16;
|
|
wire [79 : 0] tlb_m_entryVec_16$D_IN;
|
|
wire tlb_m_entryVec_16$EN;
|
|
|
|
// register tlb_m_entryVec_17
|
|
reg [79 : 0] tlb_m_entryVec_17;
|
|
wire [79 : 0] tlb_m_entryVec_17$D_IN;
|
|
wire tlb_m_entryVec_17$EN;
|
|
|
|
// register tlb_m_entryVec_18
|
|
reg [79 : 0] tlb_m_entryVec_18;
|
|
wire [79 : 0] tlb_m_entryVec_18$D_IN;
|
|
wire tlb_m_entryVec_18$EN;
|
|
|
|
// register tlb_m_entryVec_19
|
|
reg [79 : 0] tlb_m_entryVec_19;
|
|
wire [79 : 0] tlb_m_entryVec_19$D_IN;
|
|
wire tlb_m_entryVec_19$EN;
|
|
|
|
// register tlb_m_entryVec_2
|
|
reg [79 : 0] tlb_m_entryVec_2;
|
|
wire [79 : 0] tlb_m_entryVec_2$D_IN;
|
|
wire tlb_m_entryVec_2$EN;
|
|
|
|
// register tlb_m_entryVec_20
|
|
reg [79 : 0] tlb_m_entryVec_20;
|
|
wire [79 : 0] tlb_m_entryVec_20$D_IN;
|
|
wire tlb_m_entryVec_20$EN;
|
|
|
|
// register tlb_m_entryVec_21
|
|
reg [79 : 0] tlb_m_entryVec_21;
|
|
wire [79 : 0] tlb_m_entryVec_21$D_IN;
|
|
wire tlb_m_entryVec_21$EN;
|
|
|
|
// register tlb_m_entryVec_22
|
|
reg [79 : 0] tlb_m_entryVec_22;
|
|
wire [79 : 0] tlb_m_entryVec_22$D_IN;
|
|
wire tlb_m_entryVec_22$EN;
|
|
|
|
// register tlb_m_entryVec_23
|
|
reg [79 : 0] tlb_m_entryVec_23;
|
|
wire [79 : 0] tlb_m_entryVec_23$D_IN;
|
|
wire tlb_m_entryVec_23$EN;
|
|
|
|
// register tlb_m_entryVec_24
|
|
reg [79 : 0] tlb_m_entryVec_24;
|
|
wire [79 : 0] tlb_m_entryVec_24$D_IN;
|
|
wire tlb_m_entryVec_24$EN;
|
|
|
|
// register tlb_m_entryVec_25
|
|
reg [79 : 0] tlb_m_entryVec_25;
|
|
wire [79 : 0] tlb_m_entryVec_25$D_IN;
|
|
wire tlb_m_entryVec_25$EN;
|
|
|
|
// register tlb_m_entryVec_26
|
|
reg [79 : 0] tlb_m_entryVec_26;
|
|
wire [79 : 0] tlb_m_entryVec_26$D_IN;
|
|
wire tlb_m_entryVec_26$EN;
|
|
|
|
// register tlb_m_entryVec_27
|
|
reg [79 : 0] tlb_m_entryVec_27;
|
|
wire [79 : 0] tlb_m_entryVec_27$D_IN;
|
|
wire tlb_m_entryVec_27$EN;
|
|
|
|
// register tlb_m_entryVec_28
|
|
reg [79 : 0] tlb_m_entryVec_28;
|
|
wire [79 : 0] tlb_m_entryVec_28$D_IN;
|
|
wire tlb_m_entryVec_28$EN;
|
|
|
|
// register tlb_m_entryVec_29
|
|
reg [79 : 0] tlb_m_entryVec_29;
|
|
wire [79 : 0] tlb_m_entryVec_29$D_IN;
|
|
wire tlb_m_entryVec_29$EN;
|
|
|
|
// register tlb_m_entryVec_3
|
|
reg [79 : 0] tlb_m_entryVec_3;
|
|
wire [79 : 0] tlb_m_entryVec_3$D_IN;
|
|
wire tlb_m_entryVec_3$EN;
|
|
|
|
// register tlb_m_entryVec_30
|
|
reg [79 : 0] tlb_m_entryVec_30;
|
|
wire [79 : 0] tlb_m_entryVec_30$D_IN;
|
|
wire tlb_m_entryVec_30$EN;
|
|
|
|
// register tlb_m_entryVec_31
|
|
reg [79 : 0] tlb_m_entryVec_31;
|
|
wire [79 : 0] tlb_m_entryVec_31$D_IN;
|
|
wire tlb_m_entryVec_31$EN;
|
|
|
|
// register tlb_m_entryVec_4
|
|
reg [79 : 0] tlb_m_entryVec_4;
|
|
wire [79 : 0] tlb_m_entryVec_4$D_IN;
|
|
wire tlb_m_entryVec_4$EN;
|
|
|
|
// register tlb_m_entryVec_5
|
|
reg [79 : 0] tlb_m_entryVec_5;
|
|
wire [79 : 0] tlb_m_entryVec_5$D_IN;
|
|
wire tlb_m_entryVec_5$EN;
|
|
|
|
// register tlb_m_entryVec_6
|
|
reg [79 : 0] tlb_m_entryVec_6;
|
|
wire [79 : 0] tlb_m_entryVec_6$D_IN;
|
|
wire tlb_m_entryVec_6$EN;
|
|
|
|
// register tlb_m_entryVec_7
|
|
reg [79 : 0] tlb_m_entryVec_7;
|
|
wire [79 : 0] tlb_m_entryVec_7$D_IN;
|
|
wire tlb_m_entryVec_7$EN;
|
|
|
|
// register tlb_m_entryVec_8
|
|
reg [79 : 0] tlb_m_entryVec_8;
|
|
wire [79 : 0] tlb_m_entryVec_8$D_IN;
|
|
wire tlb_m_entryVec_8$EN;
|
|
|
|
// register tlb_m_entryVec_9
|
|
reg [79 : 0] tlb_m_entryVec_9;
|
|
wire [79 : 0] tlb_m_entryVec_9$D_IN;
|
|
wire tlb_m_entryVec_9$EN;
|
|
|
|
// register tlb_m_lruBit_rl
|
|
reg [31 : 0] tlb_m_lruBit_rl;
|
|
wire [31 : 0] tlb_m_lruBit_rl$D_IN;
|
|
wire tlb_m_lruBit_rl$EN;
|
|
|
|
// register tlb_m_randIdx
|
|
reg [4 : 0] tlb_m_randIdx;
|
|
wire [4 : 0] tlb_m_randIdx$D_IN;
|
|
wire tlb_m_randIdx$EN;
|
|
|
|
// register tlb_m_updRepIdx_rl
|
|
reg [5 : 0] tlb_m_updRepIdx_rl;
|
|
wire [5 : 0] tlb_m_updRepIdx_rl$D_IN;
|
|
wire tlb_m_updRepIdx_rl$EN;
|
|
|
|
// register tlb_m_validVec_0
|
|
reg tlb_m_validVec_0;
|
|
wire tlb_m_validVec_0$D_IN, tlb_m_validVec_0$EN;
|
|
|
|
// register tlb_m_validVec_1
|
|
reg tlb_m_validVec_1;
|
|
wire tlb_m_validVec_1$D_IN, tlb_m_validVec_1$EN;
|
|
|
|
// register tlb_m_validVec_10
|
|
reg tlb_m_validVec_10;
|
|
wire tlb_m_validVec_10$D_IN, tlb_m_validVec_10$EN;
|
|
|
|
// register tlb_m_validVec_11
|
|
reg tlb_m_validVec_11;
|
|
wire tlb_m_validVec_11$D_IN, tlb_m_validVec_11$EN;
|
|
|
|
// register tlb_m_validVec_12
|
|
reg tlb_m_validVec_12;
|
|
wire tlb_m_validVec_12$D_IN, tlb_m_validVec_12$EN;
|
|
|
|
// register tlb_m_validVec_13
|
|
reg tlb_m_validVec_13;
|
|
wire tlb_m_validVec_13$D_IN, tlb_m_validVec_13$EN;
|
|
|
|
// register tlb_m_validVec_14
|
|
reg tlb_m_validVec_14;
|
|
wire tlb_m_validVec_14$D_IN, tlb_m_validVec_14$EN;
|
|
|
|
// register tlb_m_validVec_15
|
|
reg tlb_m_validVec_15;
|
|
wire tlb_m_validVec_15$D_IN, tlb_m_validVec_15$EN;
|
|
|
|
// register tlb_m_validVec_16
|
|
reg tlb_m_validVec_16;
|
|
wire tlb_m_validVec_16$D_IN, tlb_m_validVec_16$EN;
|
|
|
|
// register tlb_m_validVec_17
|
|
reg tlb_m_validVec_17;
|
|
wire tlb_m_validVec_17$D_IN, tlb_m_validVec_17$EN;
|
|
|
|
// register tlb_m_validVec_18
|
|
reg tlb_m_validVec_18;
|
|
wire tlb_m_validVec_18$D_IN, tlb_m_validVec_18$EN;
|
|
|
|
// register tlb_m_validVec_19
|
|
reg tlb_m_validVec_19;
|
|
wire tlb_m_validVec_19$D_IN, tlb_m_validVec_19$EN;
|
|
|
|
// register tlb_m_validVec_2
|
|
reg tlb_m_validVec_2;
|
|
wire tlb_m_validVec_2$D_IN, tlb_m_validVec_2$EN;
|
|
|
|
// register tlb_m_validVec_20
|
|
reg tlb_m_validVec_20;
|
|
wire tlb_m_validVec_20$D_IN, tlb_m_validVec_20$EN;
|
|
|
|
// register tlb_m_validVec_21
|
|
reg tlb_m_validVec_21;
|
|
wire tlb_m_validVec_21$D_IN, tlb_m_validVec_21$EN;
|
|
|
|
// register tlb_m_validVec_22
|
|
reg tlb_m_validVec_22;
|
|
wire tlb_m_validVec_22$D_IN, tlb_m_validVec_22$EN;
|
|
|
|
// register tlb_m_validVec_23
|
|
reg tlb_m_validVec_23;
|
|
wire tlb_m_validVec_23$D_IN, tlb_m_validVec_23$EN;
|
|
|
|
// register tlb_m_validVec_24
|
|
reg tlb_m_validVec_24;
|
|
wire tlb_m_validVec_24$D_IN, tlb_m_validVec_24$EN;
|
|
|
|
// register tlb_m_validVec_25
|
|
reg tlb_m_validVec_25;
|
|
wire tlb_m_validVec_25$D_IN, tlb_m_validVec_25$EN;
|
|
|
|
// register tlb_m_validVec_26
|
|
reg tlb_m_validVec_26;
|
|
wire tlb_m_validVec_26$D_IN, tlb_m_validVec_26$EN;
|
|
|
|
// register tlb_m_validVec_27
|
|
reg tlb_m_validVec_27;
|
|
wire tlb_m_validVec_27$D_IN, tlb_m_validVec_27$EN;
|
|
|
|
// register tlb_m_validVec_28
|
|
reg tlb_m_validVec_28;
|
|
wire tlb_m_validVec_28$D_IN, tlb_m_validVec_28$EN;
|
|
|
|
// register tlb_m_validVec_29
|
|
reg tlb_m_validVec_29;
|
|
wire tlb_m_validVec_29$D_IN, tlb_m_validVec_29$EN;
|
|
|
|
// register tlb_m_validVec_3
|
|
reg tlb_m_validVec_3;
|
|
wire tlb_m_validVec_3$D_IN, tlb_m_validVec_3$EN;
|
|
|
|
// register tlb_m_validVec_30
|
|
reg tlb_m_validVec_30;
|
|
wire tlb_m_validVec_30$D_IN, tlb_m_validVec_30$EN;
|
|
|
|
// register tlb_m_validVec_31
|
|
reg tlb_m_validVec_31;
|
|
wire tlb_m_validVec_31$D_IN, tlb_m_validVec_31$EN;
|
|
|
|
// register tlb_m_validVec_4
|
|
reg tlb_m_validVec_4;
|
|
wire tlb_m_validVec_4$D_IN, tlb_m_validVec_4$EN;
|
|
|
|
// register tlb_m_validVec_5
|
|
reg tlb_m_validVec_5;
|
|
wire tlb_m_validVec_5$D_IN, tlb_m_validVec_5$EN;
|
|
|
|
// register tlb_m_validVec_6
|
|
reg tlb_m_validVec_6;
|
|
wire tlb_m_validVec_6$D_IN, tlb_m_validVec_6$EN;
|
|
|
|
// register tlb_m_validVec_7
|
|
reg tlb_m_validVec_7;
|
|
wire tlb_m_validVec_7$D_IN, tlb_m_validVec_7$EN;
|
|
|
|
// register tlb_m_validVec_8
|
|
reg tlb_m_validVec_8;
|
|
wire tlb_m_validVec_8$D_IN, tlb_m_validVec_8$EN;
|
|
|
|
// register tlb_m_validVec_9
|
|
reg tlb_m_validVec_9;
|
|
wire tlb_m_validVec_9$D_IN, tlb_m_validVec_9$EN;
|
|
|
|
// register vm_info
|
|
reg [48 : 0] vm_info;
|
|
wire [48 : 0] vm_info$D_IN;
|
|
wire vm_info$EN;
|
|
|
|
// register waitFlushP
|
|
reg waitFlushP;
|
|
wire waitFlushP$D_IN, waitFlushP$EN;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_doFinishFlush,
|
|
CAN_FIRE_RL_doRsFromP,
|
|
CAN_FIRE_RL_doStartFlush,
|
|
CAN_FIRE_RL_flushRqToPQ_canonicalize,
|
|
CAN_FIRE_RL_flushRqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_flushRqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_flushRqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_flushRsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_hitQ_canonicalize,
|
|
CAN_FIRE_RL_hitQ_clearReq_canon,
|
|
CAN_FIRE_RL_hitQ_deqReq_canon,
|
|
CAN_FIRE_RL_hitQ_enqReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_canonicalize,
|
|
CAN_FIRE_RL_perfReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_canonicalize,
|
|
CAN_FIRE_RL_rqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_rsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_set_no_pending,
|
|
CAN_FIRE_RL_tlb_m_doUpdateRep,
|
|
CAN_FIRE_RL_tlb_m_incRandIdx,
|
|
CAN_FIRE_RL_tlb_m_lruBit_canon,
|
|
CAN_FIRE_RL_tlb_m_updRepIdx_canon,
|
|
CAN_FIRE_flush,
|
|
CAN_FIRE_perf_req,
|
|
CAN_FIRE_perf_resp,
|
|
CAN_FIRE_perf_setStatus,
|
|
CAN_FIRE_toParent_flush_request_get,
|
|
CAN_FIRE_toParent_flush_response_put,
|
|
CAN_FIRE_toParent_rqToP_deq,
|
|
CAN_FIRE_toParent_rsFromP_enq,
|
|
CAN_FIRE_to_proc_request_put,
|
|
CAN_FIRE_to_proc_response_get,
|
|
CAN_FIRE_updateVMInfo,
|
|
WILL_FIRE_RL_doFinishFlush,
|
|
WILL_FIRE_RL_doRsFromP,
|
|
WILL_FIRE_RL_doStartFlush,
|
|
WILL_FIRE_RL_flushRqToPQ_canonicalize,
|
|
WILL_FIRE_RL_flushRqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_flushRqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_flushRqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_flushRsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_hitQ_canonicalize,
|
|
WILL_FIRE_RL_hitQ_clearReq_canon,
|
|
WILL_FIRE_RL_hitQ_deqReq_canon,
|
|
WILL_FIRE_RL_hitQ_enqReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_canonicalize,
|
|
WILL_FIRE_RL_perfReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_canonicalize,
|
|
WILL_FIRE_RL_rqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_rsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_set_no_pending,
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep,
|
|
WILL_FIRE_RL_tlb_m_incRandIdx,
|
|
WILL_FIRE_RL_tlb_m_lruBit_canon,
|
|
WILL_FIRE_RL_tlb_m_updRepIdx_canon,
|
|
WILL_FIRE_flush,
|
|
WILL_FIRE_perf_req,
|
|
WILL_FIRE_perf_resp,
|
|
WILL_FIRE_perf_setStatus,
|
|
WILL_FIRE_toParent_flush_request_get,
|
|
WILL_FIRE_toParent_flush_response_put,
|
|
WILL_FIRE_toParent_rqToP_deq,
|
|
WILL_FIRE_toParent_rsFromP_enq,
|
|
WILL_FIRE_to_proc_request_put,
|
|
WILL_FIRE_to_proc_response_get,
|
|
WILL_FIRE_updateVMInfo;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [70 : 0] MUX_hitQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_2;
|
|
wire [64 : 0] MUX_miss$write_1__VAL_1, MUX_miss$write_1__VAL_2;
|
|
wire [31 : 0] MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1;
|
|
wire [5 : 0] MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1,
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2;
|
|
wire MUX_hitQ_enqReq_lat_0$wset_1__SEL_1,
|
|
MUX_miss$write_1__SEL_1,
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1,
|
|
MUX_tlb_m_validVec_0$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_1$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_10$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_11$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_12$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_13$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_14$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_15$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_16$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_17$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_18$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_19$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_2$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_20$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_21$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_22$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_23$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_24$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_25$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_26$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_27$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_28$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_29$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_3$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_30$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_31$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_4$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_5$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_6$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_7$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_8$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_9$write_1__SEL_1,
|
|
MUX_waitFlushP$write_1__SEL_1;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] x__h73823;
|
|
reg [55 : 0] x__h64088, x__h73598;
|
|
reg [43 : 0] SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556,
|
|
ppn__h73594;
|
|
reg [26 : 0] CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q4,
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q13,
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q14,
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q15,
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q16,
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q17,
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q18,
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q19,
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q20,
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q21,
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q22,
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q3,
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q23,
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q24,
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q25,
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q26,
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q27,
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q28,
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q29,
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q30,
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q31,
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q32,
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q5,
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q33,
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q34,
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q6,
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q7,
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q8,
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q9,
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q10,
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q11,
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q12,
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942;
|
|
reg [4 : 0] CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_1_hit_ETC__q2;
|
|
reg [1 : 0] level__h32531, level__h68877;
|
|
reg CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q1,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q36,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q35,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q37,
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538,
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171,
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526,
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104,
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022,
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921;
|
|
wire [69 : 0] IF_vm_info_43_BIT_46_79_THEN_IF_SEL_ARR_tlb_m__ETC___d2195;
|
|
wire [63 : 0] x__h64080, x__h73590, x__h8655;
|
|
wire [31 : 0] INV_n__read4856__q38,
|
|
n__read__h44856,
|
|
upd__h44883,
|
|
val__h5317,
|
|
x__h5375;
|
|
wire [8 : 0] SEL_ARR_rsFromPQ_data_0_21_BIT_8_457_rsFromPQ__ETC___d1468;
|
|
wire [4 : 0] IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1891,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1893,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1895,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1897,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1899,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1901,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1903,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1905,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1907,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1909,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1911,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1913,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1915,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1917,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1919,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27,
|
|
IF_tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_ETC___d776,
|
|
IF_tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_ETC___d777,
|
|
IF_tlb_m_validVec_12_62_AND_tlb_m_validVec_13__ETC___d766,
|
|
IF_tlb_m_validVec_16_75_AND_tlb_m_validVec_17__ETC___d761,
|
|
IF_tlb_m_validVec_16_75_AND_tlb_m_validVec_17__ETC___d762,
|
|
IF_tlb_m_validVec_20_86_AND_tlb_m_validVec_21__ETC___d758,
|
|
IF_tlb_m_validVec_24_98_AND_tlb_m_validVec_25__ETC___d754,
|
|
IF_tlb_m_validVec_24_98_AND_tlb_m_validVec_25__ETC___d755,
|
|
IF_tlb_m_validVec_28_09_AND_tlb_m_validVec_29__ETC___d751,
|
|
IF_tlb_m_validVec_4_39_AND_tlb_m_validVec_5_41_ETC___d773,
|
|
IF_tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_ETC___d769,
|
|
IF_tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_ETC___d770,
|
|
addIdx__h49485,
|
|
addIdx__h54335,
|
|
idx__h68863,
|
|
v__h39303,
|
|
v__h44120,
|
|
v__h45648;
|
|
wire [3 : 0] SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d1466;
|
|
wire IF_IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_ETC___d2174,
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d125,
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d134,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d215,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d224,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d229,
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d316,
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d325,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1825,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1826,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1827,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1828,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1829,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1830,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1831,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1832,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1833,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1834,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1835,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1836,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1837,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1838,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1839,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1840,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1841,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1842,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1843,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1844,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1845,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1846,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1847,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1848,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1849,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1850,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1851,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1852,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1853,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1854,
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1855,
|
|
IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqReq__ETC___d101,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52,
|
|
IF_perfReqQ_enqReq_lat_1_whas__42_THEN_perfReq_ETC___d451,
|
|
IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_de_ETC___d191,
|
|
IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165,
|
|
IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFromP_ETC___d292,
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_NOT_rsF_ETC___d257,
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250,
|
|
IF_tlb_m_entryVec_10_075_BITS_1_TO_0_079_EQ_0__ETC___d1583,
|
|
IF_tlb_m_entryVec_11_088_BITS_1_TO_0_092_EQ_0__ETC___d1593,
|
|
IF_tlb_m_entryVec_12_101_BITS_1_TO_0_105_EQ_0__ETC___d1603,
|
|
IF_tlb_m_entryVec_13_114_BITS_1_TO_0_118_EQ_0__ETC___d1613,
|
|
IF_tlb_m_entryVec_14_127_BITS_1_TO_0_131_EQ_0__ETC___d1623,
|
|
IF_tlb_m_entryVec_15_140_BITS_1_TO_0_144_EQ_0__ETC___d1633,
|
|
IF_tlb_m_entryVec_16_153_BITS_1_TO_0_157_EQ_0__ETC___d1643,
|
|
IF_tlb_m_entryVec_17_166_BITS_1_TO_0_170_EQ_0__ETC___d1653,
|
|
IF_tlb_m_entryVec_18_179_BITS_1_TO_0_183_EQ_0__ETC___d1663,
|
|
IF_tlb_m_entryVec_19_192_BITS_1_TO_0_196_EQ_0__ETC___d1673,
|
|
IF_tlb_m_entryVec_1_58_BITS_1_TO_0_62_EQ_0_487_ETC___d1493,
|
|
IF_tlb_m_entryVec_20_205_BITS_1_TO_0_209_EQ_0__ETC___d1683,
|
|
IF_tlb_m_entryVec_21_218_BITS_1_TO_0_222_EQ_0__ETC___d1693,
|
|
IF_tlb_m_entryVec_22_231_BITS_1_TO_0_235_EQ_0__ETC___d1703,
|
|
IF_tlb_m_entryVec_23_244_BITS_1_TO_0_248_EQ_0__ETC___d1713,
|
|
IF_tlb_m_entryVec_24_257_BITS_1_TO_0_261_EQ_0__ETC___d1723,
|
|
IF_tlb_m_entryVec_25_270_BITS_1_TO_0_274_EQ_0__ETC___d1733,
|
|
IF_tlb_m_entryVec_26_283_BITS_1_TO_0_287_EQ_0__ETC___d1743,
|
|
IF_tlb_m_entryVec_27_296_BITS_1_TO_0_300_EQ_0__ETC___d1753,
|
|
IF_tlb_m_entryVec_28_309_BITS_1_TO_0_313_EQ_0__ETC___d1763,
|
|
IF_tlb_m_entryVec_29_322_BITS_1_TO_0_326_EQ_0__ETC___d1773,
|
|
IF_tlb_m_entryVec_2_71_BITS_1_TO_0_75_EQ_0_497_ETC___d1503,
|
|
IF_tlb_m_entryVec_30_335_BITS_1_TO_0_339_EQ_0__ETC___d1783,
|
|
IF_tlb_m_entryVec_31_348_BITS_1_TO_0_352_EQ_0__ETC___d1793,
|
|
IF_tlb_m_entryVec_3_84_BITS_1_TO_0_88_EQ_0_507_ETC___d1513,
|
|
IF_tlb_m_entryVec_4_97_BITS_1_TO_0_001_EQ_0_51_ETC___d1523,
|
|
IF_tlb_m_entryVec_5_010_BITS_1_TO_0_014_EQ_0_5_ETC___d1533,
|
|
IF_tlb_m_entryVec_6_023_BITS_1_TO_0_027_EQ_0_5_ETC___d1543,
|
|
IF_tlb_m_entryVec_7_036_BITS_1_TO_0_040_EQ_0_5_ETC___d1553,
|
|
IF_tlb_m_entryVec_8_049_BITS_1_TO_0_053_EQ_0_5_ETC___d1563,
|
|
IF_tlb_m_entryVec_9_062_BITS_1_TO_0_066_EQ_0_5_ETC___d1573,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17,
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609,
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922__ETC___d2178,
|
|
NOT_SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46__ETC___d582,
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d589,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1486,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1506,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1526,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1546,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1566,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1586,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1606,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1626,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1646,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1666,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1686,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1706,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1726,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1746,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1766,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1786,
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_tlb_m_validV_ETC___d650,
|
|
NOT_tlb_m_validVec_11_58_59_OR_NOT_tlb_m_entry_ETC___d1380,
|
|
NOT_tlb_m_validVec_13_64_65_OR_NOT_tlb_m_entry_ETC___d1378,
|
|
NOT_tlb_m_validVec_15_69_70_OR_NOT_tlb_m_entry_ETC___d1376,
|
|
NOT_tlb_m_validVec_16_75_76_OR_NOT_tlb_m_valid_ETC___d697,
|
|
NOT_tlb_m_validVec_17_77_78_OR_NOT_tlb_m_entry_ETC___d1374,
|
|
NOT_tlb_m_validVec_19_82_83_OR_NOT_tlb_m_entry_ETC___d1372,
|
|
NOT_tlb_m_validVec_1_30_31_OR_NOT_tlb_m_entryV_ETC___d1390,
|
|
NOT_tlb_m_validVec_21_88_89_OR_NOT_tlb_m_entry_ETC___d1370,
|
|
NOT_tlb_m_validVec_23_93_94_OR_NOT_tlb_m_entry_ETC___d1368,
|
|
NOT_tlb_m_validVec_24_98_99_OR_NOT_tlb_m_valid_ETC___d720,
|
|
NOT_tlb_m_validVec_25_00_01_OR_NOT_tlb_m_entry_ETC___d1366,
|
|
NOT_tlb_m_validVec_27_05_06_OR_NOT_tlb_m_entry_ETC___d1364,
|
|
NOT_tlb_m_validVec_29_11_12_OR_NOT_tlb_m_entry_ETC___d1362,
|
|
NOT_tlb_m_validVec_3_35_36_OR_NOT_tlb_m_entryV_ETC___d1388,
|
|
NOT_tlb_m_validVec_5_41_42_OR_NOT_tlb_m_entryV_ETC___d1386,
|
|
NOT_tlb_m_validVec_7_46_47_OR_NOT_tlb_m_entryV_ETC___d1384,
|
|
NOT_tlb_m_validVec_8_51_52_OR_NOT_tlb_m_validV_ETC___d673,
|
|
NOT_tlb_m_validVec_9_53_54_OR_NOT_tlb_m_entryV_ETC___d1382,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d587,
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46_rsFr_ETC___d604,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392,
|
|
_theResult_____2__h12659,
|
|
_theResult_____2__h17274,
|
|
_theResult_____2__h9023,
|
|
next_deqP___1__h12848,
|
|
next_deqP___1__h17463,
|
|
next_deqP___1__h9212,
|
|
tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_23_ETC___d729,
|
|
tlb_m_validVec_16_75_AND_tlb_m_validVec_17_77__ETC___d744,
|
|
tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_30_ETC___d736,
|
|
v__h12287,
|
|
v__h12438,
|
|
v__h16232,
|
|
v__h16383,
|
|
v__h8385,
|
|
v__h8536,
|
|
vm_info_43_BIT_46_79_AND_IF_NOT_tlb_m_validVec_ETC___d2198,
|
|
vm_info_43_BIT_46_79_AND_NOT_tlb_m_validVec_0__ETC___d2203;
|
|
|
|
// value method flush_done
|
|
assign flush_done = !needFlush ;
|
|
assign RDY_flush_done = 1'd1 ;
|
|
|
|
// action method flush
|
|
assign RDY_flush = !needFlush ;
|
|
assign CAN_FIRE_flush = !needFlush ;
|
|
assign WILL_FIRE_flush = EN_flush ;
|
|
|
|
// action method updateVMInfo
|
|
assign RDY_updateVMInfo = 1'd1 ;
|
|
assign CAN_FIRE_updateVMInfo = 1'd1 ;
|
|
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
|
|
|
|
// value method noPendingReq
|
|
assign noPendingReq = !miss[64] ;
|
|
assign RDY_noPendingReq = 1'd1 ;
|
|
|
|
// action method to_proc_request_put
|
|
assign RDY_to_proc_request_put =
|
|
!needFlush && !miss[64] && !hitQ_full && !rqToPQ_full &&
|
|
(!vm_info[46] ||
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d589) ;
|
|
assign CAN_FIRE_to_proc_request_put = RDY_to_proc_request_put ;
|
|
assign WILL_FIRE_to_proc_request_put = EN_to_proc_request_put ;
|
|
|
|
// actionvalue method to_proc_response_get
|
|
assign to_proc_response_get =
|
|
{ x__h73823,
|
|
!CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q1,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_1_hit_ETC__q2 } ;
|
|
assign RDY_to_proc_response_get = !hitQ_empty ;
|
|
assign CAN_FIRE_to_proc_response_get = !hitQ_empty ;
|
|
assign WILL_FIRE_to_proc_response_get = EN_to_proc_response_get ;
|
|
|
|
// value method toParent_rqToP_notEmpty
|
|
assign toParent_rqToP_notEmpty = !rqToPQ_empty ;
|
|
assign RDY_toParent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method toParent_rqToP_deq
|
|
assign RDY_toParent_rqToP_deq = !rqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_rqToP_deq = !rqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_rqToP_deq = EN_toParent_rqToP_deq ;
|
|
|
|
// value method toParent_rqToP_first
|
|
always@(rqToPQ_deqP or rqToPQ_data_0 or rqToPQ_data_1)
|
|
begin
|
|
case (rqToPQ_deqP)
|
|
1'd0: toParent_rqToP_first = rqToPQ_data_0;
|
|
1'd1: toParent_rqToP_first = rqToPQ_data_1;
|
|
endcase
|
|
end
|
|
assign RDY_toParent_rqToP_first = !rqToPQ_empty ;
|
|
|
|
// value method toParent_rsFromP_notFull
|
|
assign toParent_rsFromP_notFull = !rsFromPQ_full ;
|
|
assign RDY_toParent_rsFromP_notFull = 1'd1 ;
|
|
|
|
// action method toParent_rsFromP_enq
|
|
assign RDY_toParent_rsFromP_enq = !rsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_rsFromP_enq = !rsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_rsFromP_enq = EN_toParent_rsFromP_enq ;
|
|
|
|
// action method toParent_flush_request_get
|
|
assign RDY_toParent_flush_request_get = !flushRqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_flush_request_get = !flushRqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_flush_request_get =
|
|
EN_toParent_flush_request_get ;
|
|
|
|
// action method toParent_flush_response_put
|
|
assign RDY_toParent_flush_response_put = !flushRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_flush_response_put = !flushRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_flush_response_put =
|
|
EN_toParent_flush_response_put ;
|
|
|
|
// action method perf_setStatus
|
|
assign RDY_perf_setStatus = 1'd1 ;
|
|
assign CAN_FIRE_perf_setStatus = 1'd1 ;
|
|
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
|
|
|
|
// action method perf_req
|
|
assign RDY_perf_req = !perfReqQ_full ;
|
|
assign CAN_FIRE_perf_req = !perfReqQ_full ;
|
|
assign WILL_FIRE_perf_req = EN_perf_req ;
|
|
|
|
// actionvalue method perf_resp
|
|
assign perf_resp = { perfReqQ_data_0, 64'd0 } ;
|
|
assign RDY_perf_resp = !perfReqQ_empty ;
|
|
assign CAN_FIRE_perf_resp = !perfReqQ_empty ;
|
|
assign WILL_FIRE_perf_resp = EN_perf_resp ;
|
|
|
|
// value method perf_respValid
|
|
assign perf_respValid = !perfReqQ_empty ;
|
|
assign RDY_perf_respValid = 1'd1 ;
|
|
|
|
// rule RL_doStartFlush
|
|
assign CAN_FIRE_RL_doStartFlush =
|
|
!flushRqToPQ_full && needFlush && !waitFlushP && !miss[64] ;
|
|
assign WILL_FIRE_RL_doStartFlush = CAN_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doFinishFlush
|
|
assign CAN_FIRE_RL_doFinishFlush =
|
|
!flushRsFromPQ_empty && needFlush && waitFlushP && !miss[64] ;
|
|
assign WILL_FIRE_RL_doFinishFlush = CAN_FIRE_RL_doFinishFlush ;
|
|
|
|
// rule RL_set_no_pending
|
|
assign CAN_FIRE_RL_set_no_pending = 1'd1 ;
|
|
assign WILL_FIRE_RL_set_no_pending = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_doUpdateRep
|
|
assign CAN_FIRE_RL_tlb_m_doUpdateRep =
|
|
!CAN_FIRE_RL_doStartFlush && tlb_m_updRepIdx_rl[5] ;
|
|
assign WILL_FIRE_RL_tlb_m_doUpdateRep =
|
|
CAN_FIRE_RL_tlb_m_doUpdateRep && !WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doRsFromP
|
|
assign CAN_FIRE_RL_doRsFromP =
|
|
!hitQ_full && !rsFromPQ_empty &&
|
|
(!SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 ||
|
|
!SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 ||
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d587 ||
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d589) &&
|
|
miss[64] ;
|
|
assign WILL_FIRE_RL_doRsFromP = CAN_FIRE_RL_doRsFromP ;
|
|
|
|
// rule RL_tlb_m_incRandIdx
|
|
assign CAN_FIRE_RL_tlb_m_incRandIdx = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_incRandIdx = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_lruBit_canon
|
|
assign CAN_FIRE_RL_tlb_m_lruBit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_lruBit_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_updRepIdx_canon
|
|
assign CAN_FIRE_RL_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_canonicalize
|
|
assign CAN_FIRE_RL_hitQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_hitQ_enqReq_canon
|
|
assign CAN_FIRE_RL_hitQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_deqReq_canon
|
|
assign CAN_FIRE_RL_hitQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_clearReq_canon
|
|
assign CAN_FIRE_RL_hitQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_rqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_rsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_flushRqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__SEL_1 =
|
|
EN_to_proc_request_put &&
|
|
(IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1855 ||
|
|
!vm_info[46]) ;
|
|
assign MUX_miss$write_1__SEL_1 =
|
|
EN_to_proc_request_put &&
|
|
vm_info_43_BIT_46_79_AND_NOT_tlb_m_validVec_0__ETC___d2203 ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd0 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd1 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_10$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd10 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_11$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd11 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_12$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd12 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_13$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd13 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_14$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd14 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_15$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd15 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_16$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd16 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_17$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd17 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_18$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd18 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_19$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd19 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_2$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_20$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd20 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_21$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd21 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_22$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd22 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_23$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd23 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_24$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd24 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_25$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd25 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_26$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd26 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_27$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd27 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_28$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd28 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_29$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd29 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd3 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_30$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd30 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_31$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd31 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_4$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd4 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_5$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd5 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_6$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd6 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_7$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd7 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_8$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd8 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_tlb_m_validVec_9$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd9 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ;
|
|
assign MUX_waitFlushP$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doFinishFlush || EN_flush ;
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
IF_vm_info_43_BIT_46_79_THEN_IF_SEL_ARR_tlb_m__ETC___d2195 } ;
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 ?
|
|
((SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609) ?
|
|
{ x__h64080, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
{ 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
6'd44 }) :
|
|
{ 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
6'd44 } } ;
|
|
assign MUX_miss$write_1__VAL_1 = { 1'd1, to_proc_request_put } ;
|
|
assign MUX_miss$write_1__VAL_2 =
|
|
{ 1'd0,
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1 =
|
|
(val__h5317 == 32'hFFFFFFFF) ? x__h5375 : val__h5317 ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, v__h39303 } ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, idx__h68863 } ;
|
|
|
|
// inlined wires
|
|
assign tlb_m_lruBit_lat_0$whas =
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep || WILL_FIRE_RL_doStartFlush ;
|
|
assign tlb_m_updRepIdx_lat_0$wget =
|
|
{ 1'd0, 5'bxxxxx /* unspecified value */ } ;
|
|
assign tlb_m_updRepIdx_lat_0$whas =
|
|
WILL_FIRE_RL_doStartFlush || WILL_FIRE_RL_tlb_m_doUpdateRep ;
|
|
assign tlb_m_updRepIdx_lat_1$wget =
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 ?
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 :
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 ;
|
|
assign tlb_m_updRepIdx_lat_1$whas =
|
|
WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
EN_to_proc_request_put &&
|
|
vm_info_43_BIT_46_79_AND_IF_NOT_tlb_m_validVec_ETC___d2198 ;
|
|
assign hitQ_enqReq_lat_0$wget =
|
|
MUX_hitQ_enqReq_lat_0$wset_1__SEL_1 ?
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign hitQ_enqReq_lat_0$whas =
|
|
EN_to_proc_request_put &&
|
|
(IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1855 ||
|
|
!vm_info[46]) ||
|
|
WILL_FIRE_RL_doRsFromP ;
|
|
assign hitQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
70'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign rqToPQ_enqReq_lat_0$wget = { 1'd1, to_proc_request_put[38:12] } ;
|
|
assign rqToPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
27'bxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign rsFromPQ_enqReq_lat_0$wget = { 1'd1, toParent_rsFromP_enq_x } ;
|
|
assign rsFromPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
assign perfReqQ_enqReq_lat_2$wget =
|
|
{ 1'd0, 3'bxxx /* unspecified value */ } ;
|
|
|
|
// register flushRqToPQ_clearReq_rl
|
|
assign flushRqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_deqReq_rl
|
|
assign flushRqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_empty
|
|
assign flushRqToPQ_empty$D_IN =
|
|
flushRqToPQ_clearReq_rl ||
|
|
!CAN_FIRE_RL_doStartFlush && !flushRqToPQ_enqReq_rl &&
|
|
(EN_toParent_flush_request_get || flushRqToPQ_deqReq_rl ||
|
|
flushRqToPQ_empty) ;
|
|
assign flushRqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_enqReq_rl
|
|
assign flushRqToPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_full
|
|
assign flushRqToPQ_full$D_IN =
|
|
!flushRqToPQ_clearReq_rl &&
|
|
(CAN_FIRE_RL_doStartFlush || flushRqToPQ_enqReq_rl ||
|
|
!EN_toParent_flush_request_get && !flushRqToPQ_deqReq_rl &&
|
|
flushRqToPQ_full) ;
|
|
assign flushRqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_clearReq_rl
|
|
assign flushRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_deqReq_rl
|
|
assign flushRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_empty
|
|
assign flushRsFromPQ_empty$D_IN =
|
|
flushRsFromPQ_clearReq_rl ||
|
|
!EN_toParent_flush_response_put && !flushRsFromPQ_enqReq_rl &&
|
|
(CAN_FIRE_RL_doFinishFlush || flushRsFromPQ_deqReq_rl ||
|
|
flushRsFromPQ_empty) ;
|
|
assign flushRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_enqReq_rl
|
|
assign flushRsFromPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_full
|
|
assign flushRsFromPQ_full$D_IN =
|
|
!flushRsFromPQ_clearReq_rl &&
|
|
(EN_toParent_flush_response_put || flushRsFromPQ_enqReq_rl ||
|
|
!CAN_FIRE_RL_doFinishFlush && !flushRsFromPQ_deqReq_rl &&
|
|
flushRsFromPQ_full) ;
|
|
assign flushRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register hitQ_clearReq_rl
|
|
assign hitQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign hitQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_data_0
|
|
assign hitQ_data_0$D_IN =
|
|
{ x__h8655,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 ||
|
|
(hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[5] :
|
|
hitQ_enqReq_rl[5]),
|
|
hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[4:0] :
|
|
hitQ_enqReq_rl[4:0] } ;
|
|
assign hitQ_data_0$EN =
|
|
hitQ_enqP == 1'd0 && !hitQ_clearReq_rl &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ;
|
|
|
|
// register hitQ_data_1
|
|
assign hitQ_data_1$D_IN = hitQ_data_0$D_IN ;
|
|
assign hitQ_data_1$EN =
|
|
hitQ_enqP == 1'd1 && !hitQ_clearReq_rl &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ;
|
|
|
|
// register hitQ_deqP
|
|
assign hitQ_deqP$D_IN = !hitQ_clearReq_rl && _theResult_____2__h9023 ;
|
|
assign hitQ_deqP$EN = 1'd1 ;
|
|
|
|
// register hitQ_deqReq_rl
|
|
assign hitQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign hitQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_empty
|
|
assign hitQ_empty$D_IN =
|
|
hitQ_clearReq_rl ||
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d125 &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 &&
|
|
(IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqReq__ETC___d101 ||
|
|
hitQ_empty) ;
|
|
assign hitQ_empty$EN = 1'd1 ;
|
|
|
|
// register hitQ_enqP
|
|
assign hitQ_enqP$D_IN = !hitQ_clearReq_rl && v__h8385 ;
|
|
assign hitQ_enqP$EN = 1'd1 ;
|
|
|
|
// register hitQ_enqReq_rl
|
|
assign hitQ_enqReq_rl$D_IN = hitQ_enqReq_lat_2$wget ;
|
|
assign hitQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_full
|
|
assign hitQ_full$D_IN =
|
|
!hitQ_clearReq_rl &&
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d134 ;
|
|
assign hitQ_full$EN = 1'd1 ;
|
|
|
|
// register miss
|
|
assign miss$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
MUX_miss$write_1__VAL_1 :
|
|
MUX_miss$write_1__VAL_2 ;
|
|
assign miss$EN =
|
|
EN_to_proc_request_put &&
|
|
vm_info_43_BIT_46_79_AND_NOT_tlb_m_validVec_0__ETC___d2203 ||
|
|
WILL_FIRE_RL_doRsFromP ;
|
|
|
|
// register needFlush
|
|
assign needFlush$D_IN = !WILL_FIRE_RL_doFinishFlush ;
|
|
assign needFlush$EN = MUX_waitFlushP$write_1__SEL_1 ;
|
|
|
|
// register perfReqQ_clearReq_rl
|
|
assign perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_data_0
|
|
assign perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[2:0] :
|
|
perfReqQ_enqReq_rl[2:0] ;
|
|
assign perfReqQ_data_0$EN =
|
|
!perfReqQ_clearReq_rl &&
|
|
IF_perfReqQ_enqReq_lat_1_whas__42_THEN_perfReq_ETC___d451 ;
|
|
|
|
// register perfReqQ_deqReq_rl
|
|
assign perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_empty
|
|
assign perfReqQ_empty$D_IN =
|
|
perfReqQ_clearReq_rl ||
|
|
(EN_perf_req ?
|
|
!perfReqQ_enqReq_lat_0$wget[3] :
|
|
!perfReqQ_enqReq_rl[3]) &&
|
|
(EN_perf_resp || perfReqQ_deqReq_rl || perfReqQ_empty) ;
|
|
assign perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_enqReq_rl
|
|
assign perfReqQ_enqReq_rl$D_IN = perfReqQ_enqReq_lat_2$wget ;
|
|
assign perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_full
|
|
assign perfReqQ_full$D_IN =
|
|
!perfReqQ_clearReq_rl &&
|
|
(IF_perfReqQ_enqReq_lat_1_whas__42_THEN_perfReq_ETC___d451 ||
|
|
!EN_perf_resp && !perfReqQ_deqReq_rl && perfReqQ_full) ;
|
|
assign perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_clearReq_rl
|
|
assign rqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign rqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_data_0
|
|
assign rqToPQ_data_0$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[26:0] :
|
|
rqToPQ_enqReq_rl[26:0] ;
|
|
assign rqToPQ_data_0$EN =
|
|
rqToPQ_enqP == 1'd0 && !rqToPQ_clearReq_rl &&
|
|
IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 ;
|
|
|
|
// register rqToPQ_data_1
|
|
assign rqToPQ_data_1$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[26:0] :
|
|
rqToPQ_enqReq_rl[26:0] ;
|
|
assign rqToPQ_data_1$EN =
|
|
rqToPQ_enqP == 1'd1 && !rqToPQ_clearReq_rl &&
|
|
IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 ;
|
|
|
|
// register rqToPQ_deqP
|
|
assign rqToPQ_deqP$D_IN = !rqToPQ_clearReq_rl && _theResult_____2__h12659 ;
|
|
assign rqToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_deqReq_rl
|
|
assign rqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign rqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_empty
|
|
assign rqToPQ_empty$D_IN =
|
|
rqToPQ_clearReq_rl ||
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d229 ;
|
|
assign rqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_enqP
|
|
assign rqToPQ_enqP$D_IN = !rqToPQ_clearReq_rl && v__h12287 ;
|
|
assign rqToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_enqReq_rl
|
|
assign rqToPQ_enqReq_rl$D_IN = rqToPQ_enqReq_lat_2$wget ;
|
|
assign rqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_full
|
|
assign rqToPQ_full$D_IN =
|
|
!rqToPQ_clearReq_rl &&
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d224 ;
|
|
assign rqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_clearReq_rl
|
|
assign rsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign rsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_data_0
|
|
assign rsFromPQ_data_0$D_IN =
|
|
{ IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_NOT_rsF_ETC___d257 ||
|
|
(EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[80] :
|
|
rsFromPQ_enqReq_rl[80]),
|
|
EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[79:0] :
|
|
rsFromPQ_enqReq_rl[79:0] } ;
|
|
assign rsFromPQ_data_0$EN =
|
|
rsFromPQ_enqP == 1'd0 && !rsFromPQ_clearReq_rl &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 ;
|
|
|
|
// register rsFromPQ_data_1
|
|
assign rsFromPQ_data_1$D_IN = rsFromPQ_data_0$D_IN ;
|
|
assign rsFromPQ_data_1$EN =
|
|
rsFromPQ_enqP == 1'd1 && !rsFromPQ_clearReq_rl &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 ;
|
|
|
|
// register rsFromPQ_deqP
|
|
assign rsFromPQ_deqP$D_IN =
|
|
!rsFromPQ_clearReq_rl && _theResult_____2__h17274 ;
|
|
assign rsFromPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_deqReq_rl
|
|
assign rsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign rsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_empty
|
|
assign rsFromPQ_empty$D_IN =
|
|
rsFromPQ_clearReq_rl ||
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d316 &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_NOT_rsF_ETC___d257 &&
|
|
(IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFromP_ETC___d292 ||
|
|
rsFromPQ_empty) ;
|
|
assign rsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_enqP
|
|
assign rsFromPQ_enqP$D_IN = !rsFromPQ_clearReq_rl && v__h16232 ;
|
|
assign rsFromPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_enqReq_rl
|
|
assign rsFromPQ_enqReq_rl$D_IN = rsFromPQ_enqReq_lat_2$wget ;
|
|
assign rsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_full
|
|
assign rsFromPQ_full$D_IN =
|
|
!rsFromPQ_clearReq_rl &&
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d325 ;
|
|
assign rsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register tlb_m_entryVec_0
|
|
assign tlb_m_entryVec_0$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_0$EN = MUX_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_1
|
|
assign tlb_m_entryVec_1$D_IN =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942,
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_8_457_rsFromPQ__ETC___d1468 } ;
|
|
assign tlb_m_entryVec_1$EN = MUX_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_10
|
|
assign tlb_m_entryVec_10$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_10$EN = MUX_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_11
|
|
assign tlb_m_entryVec_11$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_11$EN = MUX_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_12
|
|
assign tlb_m_entryVec_12$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_12$EN = MUX_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_13
|
|
assign tlb_m_entryVec_13$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_13$EN = MUX_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_14
|
|
assign tlb_m_entryVec_14$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_14$EN = MUX_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_15
|
|
assign tlb_m_entryVec_15$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_15$EN = MUX_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_16
|
|
assign tlb_m_entryVec_16$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_16$EN = MUX_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_17
|
|
assign tlb_m_entryVec_17$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_17$EN = MUX_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_18
|
|
assign tlb_m_entryVec_18$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_18$EN = MUX_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_19
|
|
assign tlb_m_entryVec_19$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_19$EN = MUX_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_2
|
|
assign tlb_m_entryVec_2$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_2$EN = MUX_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_20
|
|
assign tlb_m_entryVec_20$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_20$EN = MUX_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_21
|
|
assign tlb_m_entryVec_21$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_21$EN = MUX_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_22
|
|
assign tlb_m_entryVec_22$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_22$EN = MUX_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_23
|
|
assign tlb_m_entryVec_23$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_23$EN = MUX_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_24
|
|
assign tlb_m_entryVec_24$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_24$EN = MUX_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_25
|
|
assign tlb_m_entryVec_25$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_25$EN = MUX_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_26
|
|
assign tlb_m_entryVec_26$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_26$EN = MUX_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_27
|
|
assign tlb_m_entryVec_27$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_27$EN = MUX_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_28
|
|
assign tlb_m_entryVec_28$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_28$EN = MUX_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_29
|
|
assign tlb_m_entryVec_29$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_29$EN = MUX_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_3
|
|
assign tlb_m_entryVec_3$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_3$EN = MUX_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_30
|
|
assign tlb_m_entryVec_30$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_30$EN = MUX_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_31
|
|
assign tlb_m_entryVec_31$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_31$EN = MUX_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_4
|
|
assign tlb_m_entryVec_4$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_4$EN = MUX_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_5
|
|
assign tlb_m_entryVec_5$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_5$EN = MUX_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_6
|
|
assign tlb_m_entryVec_6$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_6$EN = MUX_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_7
|
|
assign tlb_m_entryVec_7$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_7$EN = MUX_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_8
|
|
assign tlb_m_entryVec_8$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_8$EN = MUX_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_9
|
|
assign tlb_m_entryVec_9$D_IN = tlb_m_entryVec_1$D_IN ;
|
|
assign tlb_m_entryVec_9$EN = MUX_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_lruBit_rl
|
|
assign tlb_m_lruBit_rl$D_IN = n__read__h44856 ;
|
|
assign tlb_m_lruBit_rl$EN = 1'd1 ;
|
|
|
|
// register tlb_m_randIdx
|
|
assign tlb_m_randIdx$D_IN = tlb_m_randIdx + 5'd1 ;
|
|
assign tlb_m_randIdx$EN = 1'd1 ;
|
|
|
|
// register tlb_m_updRepIdx_rl
|
|
assign tlb_m_updRepIdx_rl$D_IN =
|
|
{ IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27 } ;
|
|
assign tlb_m_updRepIdx_rl$EN = 1'd1 ;
|
|
|
|
// register tlb_m_validVec_0
|
|
assign tlb_m_validVec_0$D_IN = MUX_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_0$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd0 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_1
|
|
assign tlb_m_validVec_1$D_IN = MUX_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_1$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd1 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_10
|
|
assign tlb_m_validVec_10$D_IN = MUX_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_10$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd10 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_11
|
|
assign tlb_m_validVec_11$D_IN = MUX_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_11$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd11 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_12
|
|
assign tlb_m_validVec_12$D_IN = MUX_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_12$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd12 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_13
|
|
assign tlb_m_validVec_13$D_IN = MUX_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_13$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd13 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_14
|
|
assign tlb_m_validVec_14$D_IN = MUX_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_14$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd14 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_15
|
|
assign tlb_m_validVec_15$D_IN = MUX_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_15$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd15 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_16
|
|
assign tlb_m_validVec_16$D_IN = MUX_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_16$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd16 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_17
|
|
assign tlb_m_validVec_17$D_IN = MUX_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_17$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd17 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_18
|
|
assign tlb_m_validVec_18$D_IN = MUX_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_18$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd18 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_19
|
|
assign tlb_m_validVec_19$D_IN = MUX_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_19$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd19 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_2
|
|
assign tlb_m_validVec_2$D_IN = MUX_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_2$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_20
|
|
assign tlb_m_validVec_20$D_IN = MUX_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_20$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd20 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_21
|
|
assign tlb_m_validVec_21$D_IN = MUX_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_21$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd21 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_22
|
|
assign tlb_m_validVec_22$D_IN = MUX_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_22$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd22 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_23
|
|
assign tlb_m_validVec_23$D_IN = MUX_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_23$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd23 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_24
|
|
assign tlb_m_validVec_24$D_IN = MUX_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_24$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd24 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_25
|
|
assign tlb_m_validVec_25$D_IN = MUX_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_25$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd25 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_26
|
|
assign tlb_m_validVec_26$D_IN = MUX_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_26$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd26 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_27
|
|
assign tlb_m_validVec_27$D_IN = MUX_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_27$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd27 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_28
|
|
assign tlb_m_validVec_28$D_IN = MUX_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_28$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd28 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_29
|
|
assign tlb_m_validVec_29$D_IN = MUX_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_29$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd29 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_3
|
|
assign tlb_m_validVec_3$D_IN = MUX_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_3$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd3 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_30
|
|
assign tlb_m_validVec_30$D_IN = MUX_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_30$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd30 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_31
|
|
assign tlb_m_validVec_31$D_IN = MUX_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_31$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd31 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_4
|
|
assign tlb_m_validVec_4$D_IN = MUX_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_4$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd4 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_5
|
|
assign tlb_m_validVec_5$D_IN = MUX_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_5$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd5 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_6
|
|
assign tlb_m_validVec_6$D_IN = MUX_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_6$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd6 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_7
|
|
assign tlb_m_validVec_7$D_IN = MUX_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_7$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd7 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_8
|
|
assign tlb_m_validVec_8$D_IN = MUX_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_8$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd8 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_9
|
|
assign tlb_m_validVec_9$D_IN = MUX_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_9$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39303 == 5'd9 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register vm_info
|
|
assign vm_info$D_IN = updateVMInfo_vm ;
|
|
assign vm_info$EN = EN_updateVMInfo ;
|
|
|
|
// register waitFlushP
|
|
assign waitFlushP$D_IN = !MUX_waitFlushP$write_1__SEL_1 ;
|
|
assign waitFlushP$EN =
|
|
WILL_FIRE_RL_doFinishFlush || EN_flush ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_ETC___d2174 =
|
|
(level__h68877 == 2'd0 ||
|
|
((level__h68877 == 2'd1) ?
|
|
ppn__h73594[8:0] == 9'd0 :
|
|
level__h68877 == 2'd2 && ppn__h73594[17:0] == 18'd0)) &&
|
|
(!SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 ||
|
|
!SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171) ;
|
|
assign IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d125 =
|
|
_theResult_____2__h9023 == v__h8385 ;
|
|
assign IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d134 =
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d125 &&
|
|
(IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ||
|
|
!EN_to_proc_response_get && !hitQ_deqReq_rl && hitQ_full) ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d215 =
|
|
_theResult_____2__h12659 == v__h12287 ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d224 =
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d215 &&
|
|
(IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 ||
|
|
!EN_toParent_rqToP_deq && !rqToPQ_deqReq_rl && rqToPQ_full) ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d229 =
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d215 &&
|
|
(MUX_miss$write_1__SEL_1 ?
|
|
!rqToPQ_enqReq_lat_0$wget[27] :
|
|
!rqToPQ_enqReq_rl[27]) &&
|
|
(IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_de_ETC___d191 ||
|
|
rqToPQ_empty) ;
|
|
assign IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d316 =
|
|
_theResult_____2__h17274 == v__h16232 ;
|
|
assign IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d325 =
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d316 &&
|
|
(IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 ||
|
|
!CAN_FIRE_RL_doRsFromP && !rsFromPQ_deqReq_rl &&
|
|
rsFromPQ_full) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1825 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1486 ?
|
|
tlb_m_validVec_1 &&
|
|
IF_tlb_m_entryVec_1_58_BITS_1_TO_0_62_EQ_0_487_ETC___d1493 :
|
|
tlb_m_validVec_0 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1826 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1486 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_58_BITS_1_TO_0_62_EQ_0_487_ETC___d1493)) ?
|
|
tlb_m_validVec_2 &&
|
|
IF_tlb_m_entryVec_2_71_BITS_1_TO_0_75_EQ_0_497_ETC___d1503 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1825 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1827 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1506 ?
|
|
tlb_m_validVec_3 &&
|
|
IF_tlb_m_entryVec_3_84_BITS_1_TO_0_88_EQ_0_507_ETC___d1513 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1826 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1828 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1506 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_84_BITS_1_TO_0_88_EQ_0_507_ETC___d1513)) ?
|
|
tlb_m_validVec_4 &&
|
|
IF_tlb_m_entryVec_4_97_BITS_1_TO_0_001_EQ_0_51_ETC___d1523 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1827 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1829 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1526 ?
|
|
tlb_m_validVec_5 &&
|
|
IF_tlb_m_entryVec_5_010_BITS_1_TO_0_014_EQ_0_5_ETC___d1533 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1828 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1830 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1526 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_010_BITS_1_TO_0_014_EQ_0_5_ETC___d1533)) ?
|
|
tlb_m_validVec_6 &&
|
|
IF_tlb_m_entryVec_6_023_BITS_1_TO_0_027_EQ_0_5_ETC___d1543 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1829 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1831 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1546 ?
|
|
tlb_m_validVec_7 &&
|
|
IF_tlb_m_entryVec_7_036_BITS_1_TO_0_040_EQ_0_5_ETC___d1553 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1830 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1832 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1546 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_036_BITS_1_TO_0_040_EQ_0_5_ETC___d1553)) ?
|
|
tlb_m_validVec_8 &&
|
|
IF_tlb_m_entryVec_8_049_BITS_1_TO_0_053_EQ_0_5_ETC___d1563 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1831 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1833 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1566 ?
|
|
tlb_m_validVec_9 &&
|
|
IF_tlb_m_entryVec_9_062_BITS_1_TO_0_066_EQ_0_5_ETC___d1573 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1832 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1834 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1566 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_062_BITS_1_TO_0_066_EQ_0_5_ETC___d1573)) ?
|
|
tlb_m_validVec_10 &&
|
|
IF_tlb_m_entryVec_10_075_BITS_1_TO_0_079_EQ_0__ETC___d1583 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1833 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1835 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1586 ?
|
|
tlb_m_validVec_11 &&
|
|
IF_tlb_m_entryVec_11_088_BITS_1_TO_0_092_EQ_0__ETC___d1593 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1834 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1836 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1586 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_088_BITS_1_TO_0_092_EQ_0__ETC___d1593)) ?
|
|
tlb_m_validVec_12 &&
|
|
IF_tlb_m_entryVec_12_101_BITS_1_TO_0_105_EQ_0__ETC___d1603 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1835 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1837 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1606 ?
|
|
tlb_m_validVec_13 &&
|
|
IF_tlb_m_entryVec_13_114_BITS_1_TO_0_118_EQ_0__ETC___d1613 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1836 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1838 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1606 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_114_BITS_1_TO_0_118_EQ_0__ETC___d1613)) ?
|
|
tlb_m_validVec_14 &&
|
|
IF_tlb_m_entryVec_14_127_BITS_1_TO_0_131_EQ_0__ETC___d1623 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1837 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1839 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1626 ?
|
|
tlb_m_validVec_15 &&
|
|
IF_tlb_m_entryVec_15_140_BITS_1_TO_0_144_EQ_0__ETC___d1633 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1838 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1840 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1626 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_140_BITS_1_TO_0_144_EQ_0__ETC___d1633)) ?
|
|
tlb_m_validVec_16 &&
|
|
IF_tlb_m_entryVec_16_153_BITS_1_TO_0_157_EQ_0__ETC___d1643 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1839 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1841 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1646 ?
|
|
tlb_m_validVec_17 &&
|
|
IF_tlb_m_entryVec_17_166_BITS_1_TO_0_170_EQ_0__ETC___d1653 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1840 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1842 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1646 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_166_BITS_1_TO_0_170_EQ_0__ETC___d1653)) ?
|
|
tlb_m_validVec_18 &&
|
|
IF_tlb_m_entryVec_18_179_BITS_1_TO_0_183_EQ_0__ETC___d1663 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1841 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1843 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1666 ?
|
|
tlb_m_validVec_19 &&
|
|
IF_tlb_m_entryVec_19_192_BITS_1_TO_0_196_EQ_0__ETC___d1673 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1842 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1844 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1666 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_192_BITS_1_TO_0_196_EQ_0__ETC___d1673)) ?
|
|
tlb_m_validVec_20 &&
|
|
IF_tlb_m_entryVec_20_205_BITS_1_TO_0_209_EQ_0__ETC___d1683 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1843 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1845 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1686 ?
|
|
tlb_m_validVec_21 &&
|
|
IF_tlb_m_entryVec_21_218_BITS_1_TO_0_222_EQ_0__ETC___d1693 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1844 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1846 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1686 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_218_BITS_1_TO_0_222_EQ_0__ETC___d1693)) ?
|
|
tlb_m_validVec_22 &&
|
|
IF_tlb_m_entryVec_22_231_BITS_1_TO_0_235_EQ_0__ETC___d1703 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1845 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1847 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1706 ?
|
|
tlb_m_validVec_23 &&
|
|
IF_tlb_m_entryVec_23_244_BITS_1_TO_0_248_EQ_0__ETC___d1713 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1846 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1848 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1706 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_244_BITS_1_TO_0_248_EQ_0__ETC___d1713)) ?
|
|
tlb_m_validVec_24 &&
|
|
IF_tlb_m_entryVec_24_257_BITS_1_TO_0_261_EQ_0__ETC___d1723 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1847 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1849 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1726 ?
|
|
tlb_m_validVec_25 &&
|
|
IF_tlb_m_entryVec_25_270_BITS_1_TO_0_274_EQ_0__ETC___d1733 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1848 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1850 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1726 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_270_BITS_1_TO_0_274_EQ_0__ETC___d1733)) ?
|
|
tlb_m_validVec_26 &&
|
|
IF_tlb_m_entryVec_26_283_BITS_1_TO_0_287_EQ_0__ETC___d1743 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1849 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1851 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1746 ?
|
|
tlb_m_validVec_27 &&
|
|
IF_tlb_m_entryVec_27_296_BITS_1_TO_0_300_EQ_0__ETC___d1753 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1850 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1852 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1746 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_296_BITS_1_TO_0_300_EQ_0__ETC___d1753)) ?
|
|
tlb_m_validVec_28 &&
|
|
IF_tlb_m_entryVec_28_309_BITS_1_TO_0_313_EQ_0__ETC___d1763 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1851 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1853 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1766 ?
|
|
tlb_m_validVec_29 &&
|
|
IF_tlb_m_entryVec_29_322_BITS_1_TO_0_326_EQ_0__ETC___d1773 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1852 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1854 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1766 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_322_BITS_1_TO_0_326_EQ_0__ETC___d1773)) ?
|
|
tlb_m_validVec_30 &&
|
|
IF_tlb_m_entryVec_30_335_BITS_1_TO_0_339_EQ_0__ETC___d1783 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1853 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1855 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1786 ?
|
|
tlb_m_validVec_31 &&
|
|
IF_tlb_m_entryVec_31_348_BITS_1_TO_0_352_EQ_0__ETC___d1793 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1854 ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1891 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1486 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_58_BITS_1_TO_0_62_EQ_0_487_ETC___d1493)) ?
|
|
5'd2 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1486 ?
|
|
5'd1 :
|
|
5'd0) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1893 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1506 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_84_BITS_1_TO_0_88_EQ_0_507_ETC___d1513)) ?
|
|
5'd4 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1506 ?
|
|
5'd3 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1891) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1895 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1526 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_010_BITS_1_TO_0_014_EQ_0_5_ETC___d1533)) ?
|
|
5'd6 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1526 ?
|
|
5'd5 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1893) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1897 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1546 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_036_BITS_1_TO_0_040_EQ_0_5_ETC___d1553)) ?
|
|
5'd8 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1546 ?
|
|
5'd7 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1895) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1899 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1566 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_062_BITS_1_TO_0_066_EQ_0_5_ETC___d1573)) ?
|
|
5'd10 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1566 ?
|
|
5'd9 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1897) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1901 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1586 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_088_BITS_1_TO_0_092_EQ_0__ETC___d1593)) ?
|
|
5'd12 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1586 ?
|
|
5'd11 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1899) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1903 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1606 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_114_BITS_1_TO_0_118_EQ_0__ETC___d1613)) ?
|
|
5'd14 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1606 ?
|
|
5'd13 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1901) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1905 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1626 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_140_BITS_1_TO_0_144_EQ_0__ETC___d1633)) ?
|
|
5'd16 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1626 ?
|
|
5'd15 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1903) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1907 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1646 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_166_BITS_1_TO_0_170_EQ_0__ETC___d1653)) ?
|
|
5'd18 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1646 ?
|
|
5'd17 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1905) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1909 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1666 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_192_BITS_1_TO_0_196_EQ_0__ETC___d1673)) ?
|
|
5'd20 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1666 ?
|
|
5'd19 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1907) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1911 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1686 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_218_BITS_1_TO_0_222_EQ_0__ETC___d1693)) ?
|
|
5'd22 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1686 ?
|
|
5'd21 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1909) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1913 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1706 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_244_BITS_1_TO_0_248_EQ_0__ETC___d1713)) ?
|
|
5'd24 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1706 ?
|
|
5'd23 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1911) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1915 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1726 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_270_BITS_1_TO_0_274_EQ_0__ETC___d1733)) ?
|
|
5'd26 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1726 ?
|
|
5'd25 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1913) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1917 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1746 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_296_BITS_1_TO_0_300_EQ_0__ETC___d1753)) ?
|
|
5'd28 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1746 ?
|
|
5'd27 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1915) ;
|
|
assign IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1919 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1766 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_322_BITS_1_TO_0_326_EQ_0__ETC___d1773)) ?
|
|
5'd30 :
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1766 ?
|
|
5'd29 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1917) ;
|
|
assign IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqReq__ETC___d101 =
|
|
EN_to_proc_response_get || hitQ_deqReq_rl ;
|
|
assign IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
!hitQ_enqReq_lat_0$wget[70] :
|
|
!hitQ_enqReq_rl[70] ;
|
|
assign IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[70] :
|
|
hitQ_enqReq_rl[70] ;
|
|
assign IF_perfReqQ_enqReq_lat_1_whas__42_THEN_perfReq_ETC___d451 =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[3] :
|
|
perfReqQ_enqReq_rl[3] ;
|
|
assign IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_de_ETC___d191 =
|
|
EN_toParent_rqToP_deq || rqToPQ_deqReq_rl ;
|
|
assign IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[27] :
|
|
rqToPQ_enqReq_rl[27] ;
|
|
assign IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFromP_ETC___d292 =
|
|
CAN_FIRE_RL_doRsFromP || rsFromPQ_deqReq_rl ;
|
|
assign IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_NOT_rsF_ETC___d257 =
|
|
EN_toParent_rsFromP_enq ?
|
|
!rsFromPQ_enqReq_lat_0$wget[81] :
|
|
!rsFromPQ_enqReq_rl[81] ;
|
|
assign IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 =
|
|
EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[81] :
|
|
rsFromPQ_enqReq_rl[81] ;
|
|
assign IF_tlb_m_entryVec_10_075_BITS_1_TO_0_079_EQ_0__ETC___d1583 =
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q13 ==
|
|
tlb_m_entryVec_10[79:53] ;
|
|
assign IF_tlb_m_entryVec_11_088_BITS_1_TO_0_092_EQ_0__ETC___d1593 =
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q14 ==
|
|
tlb_m_entryVec_11[79:53] ;
|
|
assign IF_tlb_m_entryVec_12_101_BITS_1_TO_0_105_EQ_0__ETC___d1603 =
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q15 ==
|
|
tlb_m_entryVec_12[79:53] ;
|
|
assign IF_tlb_m_entryVec_13_114_BITS_1_TO_0_118_EQ_0__ETC___d1613 =
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q16 ==
|
|
tlb_m_entryVec_13[79:53] ;
|
|
assign IF_tlb_m_entryVec_14_127_BITS_1_TO_0_131_EQ_0__ETC___d1623 =
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q17 ==
|
|
tlb_m_entryVec_14[79:53] ;
|
|
assign IF_tlb_m_entryVec_15_140_BITS_1_TO_0_144_EQ_0__ETC___d1633 =
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q18 ==
|
|
tlb_m_entryVec_15[79:53] ;
|
|
assign IF_tlb_m_entryVec_16_153_BITS_1_TO_0_157_EQ_0__ETC___d1643 =
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q19 ==
|
|
tlb_m_entryVec_16[79:53] ;
|
|
assign IF_tlb_m_entryVec_17_166_BITS_1_TO_0_170_EQ_0__ETC___d1653 =
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q20 ==
|
|
tlb_m_entryVec_17[79:53] ;
|
|
assign IF_tlb_m_entryVec_18_179_BITS_1_TO_0_183_EQ_0__ETC___d1663 =
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q21 ==
|
|
tlb_m_entryVec_18[79:53] ;
|
|
assign IF_tlb_m_entryVec_19_192_BITS_1_TO_0_196_EQ_0__ETC___d1673 =
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q22 ==
|
|
tlb_m_entryVec_19[79:53] ;
|
|
assign IF_tlb_m_entryVec_1_58_BITS_1_TO_0_62_EQ_0_487_ETC___d1493 =
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q3 ==
|
|
tlb_m_entryVec_1[79:53] ;
|
|
assign IF_tlb_m_entryVec_20_205_BITS_1_TO_0_209_EQ_0__ETC___d1683 =
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q23 ==
|
|
tlb_m_entryVec_20[79:53] ;
|
|
assign IF_tlb_m_entryVec_21_218_BITS_1_TO_0_222_EQ_0__ETC___d1693 =
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q24 ==
|
|
tlb_m_entryVec_21[79:53] ;
|
|
assign IF_tlb_m_entryVec_22_231_BITS_1_TO_0_235_EQ_0__ETC___d1703 =
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q25 ==
|
|
tlb_m_entryVec_22[79:53] ;
|
|
assign IF_tlb_m_entryVec_23_244_BITS_1_TO_0_248_EQ_0__ETC___d1713 =
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q26 ==
|
|
tlb_m_entryVec_23[79:53] ;
|
|
assign IF_tlb_m_entryVec_24_257_BITS_1_TO_0_261_EQ_0__ETC___d1723 =
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q27 ==
|
|
tlb_m_entryVec_24[79:53] ;
|
|
assign IF_tlb_m_entryVec_25_270_BITS_1_TO_0_274_EQ_0__ETC___d1733 =
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q28 ==
|
|
tlb_m_entryVec_25[79:53] ;
|
|
assign IF_tlb_m_entryVec_26_283_BITS_1_TO_0_287_EQ_0__ETC___d1743 =
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q29 ==
|
|
tlb_m_entryVec_26[79:53] ;
|
|
assign IF_tlb_m_entryVec_27_296_BITS_1_TO_0_300_EQ_0__ETC___d1753 =
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q30 ==
|
|
tlb_m_entryVec_27[79:53] ;
|
|
assign IF_tlb_m_entryVec_28_309_BITS_1_TO_0_313_EQ_0__ETC___d1763 =
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q31 ==
|
|
tlb_m_entryVec_28[79:53] ;
|
|
assign IF_tlb_m_entryVec_29_322_BITS_1_TO_0_326_EQ_0__ETC___d1773 =
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q32 ==
|
|
tlb_m_entryVec_29[79:53] ;
|
|
assign IF_tlb_m_entryVec_2_71_BITS_1_TO_0_75_EQ_0_497_ETC___d1503 =
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q5 ==
|
|
tlb_m_entryVec_2[79:53] ;
|
|
assign IF_tlb_m_entryVec_30_335_BITS_1_TO_0_339_EQ_0__ETC___d1783 =
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q33 ==
|
|
tlb_m_entryVec_30[79:53] ;
|
|
assign IF_tlb_m_entryVec_31_348_BITS_1_TO_0_352_EQ_0__ETC___d1793 =
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q34 ==
|
|
tlb_m_entryVec_31[79:53] ;
|
|
assign IF_tlb_m_entryVec_3_84_BITS_1_TO_0_88_EQ_0_507_ETC___d1513 =
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q6 ==
|
|
tlb_m_entryVec_3[79:53] ;
|
|
assign IF_tlb_m_entryVec_4_97_BITS_1_TO_0_001_EQ_0_51_ETC___d1523 =
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q7 ==
|
|
tlb_m_entryVec_4[79:53] ;
|
|
assign IF_tlb_m_entryVec_5_010_BITS_1_TO_0_014_EQ_0_5_ETC___d1533 =
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q8 ==
|
|
tlb_m_entryVec_5[79:53] ;
|
|
assign IF_tlb_m_entryVec_6_023_BITS_1_TO_0_027_EQ_0_5_ETC___d1543 =
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q9 ==
|
|
tlb_m_entryVec_6[79:53] ;
|
|
assign IF_tlb_m_entryVec_7_036_BITS_1_TO_0_040_EQ_0_5_ETC___d1553 =
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q10 ==
|
|
tlb_m_entryVec_7[79:53] ;
|
|
assign IF_tlb_m_entryVec_8_049_BITS_1_TO_0_053_EQ_0_5_ETC___d1563 =
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q11 ==
|
|
tlb_m_entryVec_8[79:53] ;
|
|
assign IF_tlb_m_entryVec_9_062_BITS_1_TO_0_066_EQ_0_5_ETC___d1573 =
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q12 ==
|
|
tlb_m_entryVec_9[79:53] ;
|
|
assign IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17 =
|
|
tlb_m_updRepIdx_lat_1$whas ?
|
|
tlb_m_updRepIdx_lat_1$wget[5] :
|
|
(tlb_m_updRepIdx_lat_0$whas ?
|
|
tlb_m_updRepIdx_lat_0$wget[5] :
|
|
tlb_m_updRepIdx_rl[5]) ;
|
|
assign IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27 =
|
|
tlb_m_updRepIdx_lat_1$whas ?
|
|
tlb_m_updRepIdx_lat_1$wget[4:0] :
|
|
(tlb_m_updRepIdx_lat_0$whas ?
|
|
tlb_m_updRepIdx_lat_0$wget[4:0] :
|
|
tlb_m_updRepIdx_rl[4:0]) ;
|
|
assign IF_tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_ETC___d776 =
|
|
(tlb_m_validVec_0 && tlb_m_validVec_1) ?
|
|
(tlb_m_validVec_2 ? 5'd3 : 5'd2) :
|
|
(tlb_m_validVec_0 ? 5'd1 : 5'd0) ;
|
|
assign IF_tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_ETC___d777 =
|
|
(tlb_m_validVec_0 && tlb_m_validVec_1 && tlb_m_validVec_2 &&
|
|
tlb_m_validVec_3) ?
|
|
IF_tlb_m_validVec_4_39_AND_tlb_m_validVec_5_41_ETC___d773 :
|
|
IF_tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_ETC___d776 ;
|
|
assign IF_tlb_m_validVec_12_62_AND_tlb_m_validVec_13__ETC___d766 =
|
|
(tlb_m_validVec_12 && tlb_m_validVec_13) ?
|
|
(tlb_m_validVec_14 ? 5'd15 : 5'd14) :
|
|
(tlb_m_validVec_12 ? 5'd13 : 5'd12) ;
|
|
assign IF_tlb_m_validVec_16_75_AND_tlb_m_validVec_17__ETC___d761 =
|
|
(tlb_m_validVec_16 && tlb_m_validVec_17) ?
|
|
(tlb_m_validVec_18 ? 5'd19 : 5'd18) :
|
|
(tlb_m_validVec_16 ? 5'd17 : 5'd16) ;
|
|
assign IF_tlb_m_validVec_16_75_AND_tlb_m_validVec_17__ETC___d762 =
|
|
(tlb_m_validVec_16 && tlb_m_validVec_17 && tlb_m_validVec_18 &&
|
|
tlb_m_validVec_19) ?
|
|
IF_tlb_m_validVec_20_86_AND_tlb_m_validVec_21__ETC___d758 :
|
|
IF_tlb_m_validVec_16_75_AND_tlb_m_validVec_17__ETC___d761 ;
|
|
assign IF_tlb_m_validVec_20_86_AND_tlb_m_validVec_21__ETC___d758 =
|
|
(tlb_m_validVec_20 && tlb_m_validVec_21) ?
|
|
(tlb_m_validVec_22 ? 5'd23 : 5'd22) :
|
|
(tlb_m_validVec_20 ? 5'd21 : 5'd20) ;
|
|
assign IF_tlb_m_validVec_24_98_AND_tlb_m_validVec_25__ETC___d754 =
|
|
(tlb_m_validVec_24 && tlb_m_validVec_25) ?
|
|
(tlb_m_validVec_26 ? 5'd27 : 5'd26) :
|
|
(tlb_m_validVec_24 ? 5'd25 : 5'd24) ;
|
|
assign IF_tlb_m_validVec_24_98_AND_tlb_m_validVec_25__ETC___d755 =
|
|
(tlb_m_validVec_24 && tlb_m_validVec_25 && tlb_m_validVec_26 &&
|
|
tlb_m_validVec_27) ?
|
|
IF_tlb_m_validVec_28_09_AND_tlb_m_validVec_29__ETC___d751 :
|
|
IF_tlb_m_validVec_24_98_AND_tlb_m_validVec_25__ETC___d754 ;
|
|
assign IF_tlb_m_validVec_28_09_AND_tlb_m_validVec_29__ETC___d751 =
|
|
(tlb_m_validVec_28 && tlb_m_validVec_29) ?
|
|
(tlb_m_validVec_30 ? 5'd31 : 5'd30) :
|
|
(tlb_m_validVec_28 ? 5'd29 : 5'd28) ;
|
|
assign IF_tlb_m_validVec_4_39_AND_tlb_m_validVec_5_41_ETC___d773 =
|
|
(tlb_m_validVec_4 && tlb_m_validVec_5) ?
|
|
(tlb_m_validVec_6 ? 5'd7 : 5'd6) :
|
|
(tlb_m_validVec_4 ? 5'd5 : 5'd4) ;
|
|
assign IF_tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_ETC___d769 =
|
|
(tlb_m_validVec_8 && tlb_m_validVec_9) ?
|
|
(tlb_m_validVec_10 ? 5'd11 : 5'd10) :
|
|
(tlb_m_validVec_8 ? 5'd9 : 5'd8) ;
|
|
assign IF_tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_ETC___d770 =
|
|
(tlb_m_validVec_8 && tlb_m_validVec_9 && tlb_m_validVec_10 &&
|
|
tlb_m_validVec_11) ?
|
|
IF_tlb_m_validVec_12_62_AND_tlb_m_validVec_13__ETC___d766 :
|
|
IF_tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_ETC___d769 ;
|
|
assign IF_vm_info_43_BIT_46_79_THEN_IF_SEL_ARR_tlb_m__ETC___d2195 =
|
|
vm_info[46] ?
|
|
((SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 &&
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922__ETC___d2178) ?
|
|
{ x__h73590, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
{ 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
6'd44 }) :
|
|
{ to_proc_request_put,
|
|
1'd0,
|
|
5'bxxxxx /* unspecified value */ } ;
|
|
assign INV_n__read4856__q38 = ~n__read__h44856 ;
|
|
assign NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609 =
|
|
!SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538 &&
|
|
(SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542 ?
|
|
vm_info[48:47] != 2'd1 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46_rsFr_ETC___d604 :
|
|
vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46_rsFr_ETC___d604) ;
|
|
assign NOT_SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922__ETC___d2178 =
|
|
!SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 &&
|
|
(SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 ?
|
|
vm_info[48:47] != 2'd1 &&
|
|
IF_IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_ETC___d2174 :
|
|
vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_ETC___d2174) ;
|
|
assign NOT_SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46__ETC___d582 =
|
|
level__h32531 != 2'd0 &&
|
|
((level__h32531 == 2'd1) ?
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[8:0] !=
|
|
9'd0 :
|
|
level__h32531 != 2'd2 ||
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571 &&
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577 ||
|
|
!vm_info[46] ;
|
|
assign NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d589 =
|
|
!CAN_FIRE_RL_doStartFlush &&
|
|
(tlb_m_updRepIdx_lat_0$whas ?
|
|
!tlb_m_updRepIdx_lat_0$wget[5] :
|
|
!tlb_m_updRepIdx_rl[5]) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1486 =
|
|
!tlb_m_validVec_0 ||
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q4 !=
|
|
tlb_m_entryVec_0[79:53] ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1506 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1486 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_58_BITS_1_TO_0_62_EQ_0_487_ETC___d1493) &&
|
|
(!tlb_m_validVec_2 ||
|
|
!IF_tlb_m_entryVec_2_71_BITS_1_TO_0_75_EQ_0_497_ETC___d1503) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1526 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1506 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_84_BITS_1_TO_0_88_EQ_0_507_ETC___d1513) &&
|
|
(!tlb_m_validVec_4 ||
|
|
!IF_tlb_m_entryVec_4_97_BITS_1_TO_0_001_EQ_0_51_ETC___d1523) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1546 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1526 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_010_BITS_1_TO_0_014_EQ_0_5_ETC___d1533) &&
|
|
(!tlb_m_validVec_6 ||
|
|
!IF_tlb_m_entryVec_6_023_BITS_1_TO_0_027_EQ_0_5_ETC___d1543) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1566 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1546 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_036_BITS_1_TO_0_040_EQ_0_5_ETC___d1553) &&
|
|
(!tlb_m_validVec_8 ||
|
|
!IF_tlb_m_entryVec_8_049_BITS_1_TO_0_053_EQ_0_5_ETC___d1563) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1586 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1566 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_062_BITS_1_TO_0_066_EQ_0_5_ETC___d1573) &&
|
|
(!tlb_m_validVec_10 ||
|
|
!IF_tlb_m_entryVec_10_075_BITS_1_TO_0_079_EQ_0__ETC___d1583) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1606 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1586 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_088_BITS_1_TO_0_092_EQ_0__ETC___d1593) &&
|
|
(!tlb_m_validVec_12 ||
|
|
!IF_tlb_m_entryVec_12_101_BITS_1_TO_0_105_EQ_0__ETC___d1603) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1626 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1606 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_114_BITS_1_TO_0_118_EQ_0__ETC___d1613) &&
|
|
(!tlb_m_validVec_14 ||
|
|
!IF_tlb_m_entryVec_14_127_BITS_1_TO_0_131_EQ_0__ETC___d1623) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1646 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1626 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_140_BITS_1_TO_0_144_EQ_0__ETC___d1633) &&
|
|
(!tlb_m_validVec_16 ||
|
|
!IF_tlb_m_entryVec_16_153_BITS_1_TO_0_157_EQ_0__ETC___d1643) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1666 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1646 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_166_BITS_1_TO_0_170_EQ_0__ETC___d1653) &&
|
|
(!tlb_m_validVec_18 ||
|
|
!IF_tlb_m_entryVec_18_179_BITS_1_TO_0_183_EQ_0__ETC___d1663) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1686 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1666 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_192_BITS_1_TO_0_196_EQ_0__ETC___d1673) &&
|
|
(!tlb_m_validVec_20 ||
|
|
!IF_tlb_m_entryVec_20_205_BITS_1_TO_0_209_EQ_0__ETC___d1683) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1706 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1686 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_218_BITS_1_TO_0_222_EQ_0__ETC___d1693) &&
|
|
(!tlb_m_validVec_22 ||
|
|
!IF_tlb_m_entryVec_22_231_BITS_1_TO_0_235_EQ_0__ETC___d1703) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1726 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1706 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_244_BITS_1_TO_0_248_EQ_0__ETC___d1713) &&
|
|
(!tlb_m_validVec_24 ||
|
|
!IF_tlb_m_entryVec_24_257_BITS_1_TO_0_261_EQ_0__ETC___d1723) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1746 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1726 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_270_BITS_1_TO_0_274_EQ_0__ETC___d1733) &&
|
|
(!tlb_m_validVec_26 ||
|
|
!IF_tlb_m_entryVec_26_283_BITS_1_TO_0_287_EQ_0__ETC___d1743) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1766 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1746 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_296_BITS_1_TO_0_300_EQ_0__ETC___d1753) &&
|
|
(!tlb_m_validVec_28 ||
|
|
!IF_tlb_m_entryVec_28_309_BITS_1_TO_0_313_EQ_0__ETC___d1763) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1786 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1766 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_322_BITS_1_TO_0_326_EQ_0__ETC___d1773) &&
|
|
(!tlb_m_validVec_30 ||
|
|
!IF_tlb_m_entryVec_30_335_BITS_1_TO_0_339_EQ_0__ETC___d1783) ;
|
|
assign NOT_tlb_m_validVec_0_28_29_OR_NOT_tlb_m_validV_ETC___d650 =
|
|
!tlb_m_validVec_0 || !tlb_m_validVec_1 || !tlb_m_validVec_2 ||
|
|
!tlb_m_validVec_3 ||
|
|
!tlb_m_validVec_4 ||
|
|
!tlb_m_validVec_5 ||
|
|
!tlb_m_validVec_6 ||
|
|
!tlb_m_validVec_7 ;
|
|
assign NOT_tlb_m_validVec_11_58_59_OR_NOT_tlb_m_entry_ETC___d1380 =
|
|
(!tlb_m_validVec_11 ||
|
|
tlb_m_entryVec_11[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_11[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_11[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_12 ||
|
|
tlb_m_entryVec_12[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_12[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_12[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_13_64_65_OR_NOT_tlb_m_entry_ETC___d1378 ;
|
|
assign NOT_tlb_m_validVec_13_64_65_OR_NOT_tlb_m_entry_ETC___d1378 =
|
|
(!tlb_m_validVec_13 ||
|
|
tlb_m_entryVec_13[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_13[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_13[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_14 ||
|
|
tlb_m_entryVec_14[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_14[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_14[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_15_69_70_OR_NOT_tlb_m_entry_ETC___d1376 ;
|
|
assign NOT_tlb_m_validVec_15_69_70_OR_NOT_tlb_m_entry_ETC___d1376 =
|
|
(!tlb_m_validVec_15 ||
|
|
tlb_m_entryVec_15[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_15[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_15[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_16 ||
|
|
tlb_m_entryVec_16[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_16[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_16[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_17_77_78_OR_NOT_tlb_m_entry_ETC___d1374 ;
|
|
assign NOT_tlb_m_validVec_16_75_76_OR_NOT_tlb_m_valid_ETC___d697 =
|
|
!tlb_m_validVec_16 || !tlb_m_validVec_17 || !tlb_m_validVec_18 ||
|
|
!tlb_m_validVec_19 ||
|
|
!tlb_m_validVec_20 ||
|
|
!tlb_m_validVec_21 ||
|
|
!tlb_m_validVec_22 ||
|
|
!tlb_m_validVec_23 ;
|
|
assign NOT_tlb_m_validVec_17_77_78_OR_NOT_tlb_m_entry_ETC___d1374 =
|
|
(!tlb_m_validVec_17 ||
|
|
tlb_m_entryVec_17[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_17[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_17[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_18 ||
|
|
tlb_m_entryVec_18[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_18[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_18[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_19_82_83_OR_NOT_tlb_m_entry_ETC___d1372 ;
|
|
assign NOT_tlb_m_validVec_19_82_83_OR_NOT_tlb_m_entry_ETC___d1372 =
|
|
(!tlb_m_validVec_19 ||
|
|
tlb_m_entryVec_19[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_19[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_19[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_20 ||
|
|
tlb_m_entryVec_20[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_20[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_20[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_21_88_89_OR_NOT_tlb_m_entry_ETC___d1370 ;
|
|
assign NOT_tlb_m_validVec_1_30_31_OR_NOT_tlb_m_entryV_ETC___d1390 =
|
|
(!tlb_m_validVec_1 ||
|
|
tlb_m_entryVec_1[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_1[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_1[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_2 ||
|
|
tlb_m_entryVec_2[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_2[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_2[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_3_35_36_OR_NOT_tlb_m_entryV_ETC___d1388 ;
|
|
assign NOT_tlb_m_validVec_21_88_89_OR_NOT_tlb_m_entry_ETC___d1370 =
|
|
(!tlb_m_validVec_21 ||
|
|
tlb_m_entryVec_21[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_21[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_21[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_22 ||
|
|
tlb_m_entryVec_22[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_22[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_22[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_23_93_94_OR_NOT_tlb_m_entry_ETC___d1368 ;
|
|
assign NOT_tlb_m_validVec_23_93_94_OR_NOT_tlb_m_entry_ETC___d1368 =
|
|
(!tlb_m_validVec_23 ||
|
|
tlb_m_entryVec_23[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_23[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_23[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_24 ||
|
|
tlb_m_entryVec_24[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_24[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_24[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_25_00_01_OR_NOT_tlb_m_entry_ETC___d1366 ;
|
|
assign NOT_tlb_m_validVec_24_98_99_OR_NOT_tlb_m_valid_ETC___d720 =
|
|
!tlb_m_validVec_24 || !tlb_m_validVec_25 || !tlb_m_validVec_26 ||
|
|
!tlb_m_validVec_27 ||
|
|
!tlb_m_validVec_28 ||
|
|
!tlb_m_validVec_29 ||
|
|
!tlb_m_validVec_30 ||
|
|
!tlb_m_validVec_31 ;
|
|
assign NOT_tlb_m_validVec_25_00_01_OR_NOT_tlb_m_entry_ETC___d1366 =
|
|
(!tlb_m_validVec_25 ||
|
|
tlb_m_entryVec_25[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_25[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_25[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_26 ||
|
|
tlb_m_entryVec_26[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_26[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_26[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_27_05_06_OR_NOT_tlb_m_entry_ETC___d1364 ;
|
|
assign NOT_tlb_m_validVec_27_05_06_OR_NOT_tlb_m_entry_ETC___d1364 =
|
|
(!tlb_m_validVec_27 ||
|
|
tlb_m_entryVec_27[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_27[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_27[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_28 ||
|
|
tlb_m_entryVec_28[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_28[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_28[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_29_11_12_OR_NOT_tlb_m_entry_ETC___d1362 ;
|
|
assign NOT_tlb_m_validVec_29_11_12_OR_NOT_tlb_m_entry_ETC___d1362 =
|
|
(!tlb_m_validVec_29 ||
|
|
tlb_m_entryVec_29[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_29[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_29[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_30 ||
|
|
tlb_m_entryVec_30[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_30[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_30[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_31 ||
|
|
tlb_m_entryVec_31[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_31[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_31[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) ;
|
|
assign NOT_tlb_m_validVec_3_35_36_OR_NOT_tlb_m_entryV_ETC___d1388 =
|
|
(!tlb_m_validVec_3 ||
|
|
tlb_m_entryVec_3[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_3[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_3[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_4 ||
|
|
tlb_m_entryVec_4[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_4[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_4[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_5_41_42_OR_NOT_tlb_m_entryV_ETC___d1386 ;
|
|
assign NOT_tlb_m_validVec_5_41_42_OR_NOT_tlb_m_entryV_ETC___d1386 =
|
|
(!tlb_m_validVec_5 ||
|
|
tlb_m_entryVec_5[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_5[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_5[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_6 ||
|
|
tlb_m_entryVec_6[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_6[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_6[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_7_46_47_OR_NOT_tlb_m_entryV_ETC___d1384 ;
|
|
assign NOT_tlb_m_validVec_7_46_47_OR_NOT_tlb_m_entryV_ETC___d1384 =
|
|
(!tlb_m_validVec_7 ||
|
|
tlb_m_entryVec_7[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_7[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_7[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_8 ||
|
|
tlb_m_entryVec_8[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_8[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_8[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_9_53_54_OR_NOT_tlb_m_entryV_ETC___d1382 ;
|
|
assign NOT_tlb_m_validVec_8_51_52_OR_NOT_tlb_m_validV_ETC___d673 =
|
|
!tlb_m_validVec_8 || !tlb_m_validVec_9 || !tlb_m_validVec_10 ||
|
|
!tlb_m_validVec_11 ||
|
|
!tlb_m_validVec_12 ||
|
|
!tlb_m_validVec_13 ||
|
|
!tlb_m_validVec_14 ||
|
|
!tlb_m_validVec_15 ;
|
|
assign NOT_tlb_m_validVec_9_53_54_OR_NOT_tlb_m_entryV_ETC___d1382 =
|
|
(!tlb_m_validVec_9 ||
|
|
tlb_m_entryVec_9[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_9[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_9[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
(!tlb_m_validVec_10 ||
|
|
tlb_m_entryVec_10[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_10[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_10[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_11_58_59_OR_NOT_tlb_m_entry_ETC___d1380 ;
|
|
assign SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d587 =
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538 ||
|
|
(SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542 ?
|
|
vm_info[48:47] == 2'd1 ||
|
|
NOT_SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46__ETC___d582 :
|
|
vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46__ETC___d582) ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46_rsFr_ETC___d604 =
|
|
(level__h32531 == 2'd0 ||
|
|
((level__h32531 == 2'd1) ?
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[8:0] ==
|
|
9'd0 :
|
|
level__h32531 == 2'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[17:0] ==
|
|
18'd0)) &&
|
|
(!SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571 ||
|
|
!SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577) &&
|
|
vm_info[46] ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d1466 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q35,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q36 } ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1392 =
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609 &&
|
|
(!tlb_m_validVec_0 ||
|
|
tlb_m_entryVec_0[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 ||
|
|
tlb_m_entryVec_0[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_0[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953) &&
|
|
NOT_tlb_m_validVec_1_30_31_OR_NOT_tlb_m_entryV_ETC___d1390 ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_8_457_rsFromPQ__ETC___d1468 =
|
|
{ CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q37,
|
|
1'd1,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d1466,
|
|
level__h32531 } ;
|
|
assign _theResult_____2__h12659 =
|
|
IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_de_ETC___d191 ?
|
|
next_deqP___1__h12848 :
|
|
rqToPQ_deqP ;
|
|
assign _theResult_____2__h17274 =
|
|
IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFromP_ETC___d292 ?
|
|
next_deqP___1__h17463 :
|
|
rsFromPQ_deqP ;
|
|
assign _theResult_____2__h9023 =
|
|
IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqReq__ETC___d101 ?
|
|
next_deqP___1__h9212 :
|
|
hitQ_deqP ;
|
|
assign addIdx__h49485 =
|
|
(!INV_n__read4856__q38[0] && !INV_n__read4856__q38[1] &&
|
|
!INV_n__read4856__q38[2] &&
|
|
!INV_n__read4856__q38[3] &&
|
|
!INV_n__read4856__q38[4] &&
|
|
!INV_n__read4856__q38[5] &&
|
|
!INV_n__read4856__q38[6] &&
|
|
!INV_n__read4856__q38[7] &&
|
|
!INV_n__read4856__q38[8] &&
|
|
!INV_n__read4856__q38[9] &&
|
|
!INV_n__read4856__q38[10] &&
|
|
!INV_n__read4856__q38[11] &&
|
|
!INV_n__read4856__q38[12] &&
|
|
!INV_n__read4856__q38[13] &&
|
|
!INV_n__read4856__q38[14] &&
|
|
!INV_n__read4856__q38[15]) ?
|
|
((!INV_n__read4856__q38[16] && !INV_n__read4856__q38[17] &&
|
|
!INV_n__read4856__q38[18] &&
|
|
!INV_n__read4856__q38[19] &&
|
|
!INV_n__read4856__q38[20] &&
|
|
!INV_n__read4856__q38[21] &&
|
|
!INV_n__read4856__q38[22] &&
|
|
!INV_n__read4856__q38[23]) ?
|
|
((!INV_n__read4856__q38[24] && !INV_n__read4856__q38[25] &&
|
|
!INV_n__read4856__q38[26] &&
|
|
!INV_n__read4856__q38[27]) ?
|
|
((!INV_n__read4856__q38[28] &&
|
|
!INV_n__read4856__q38[29]) ?
|
|
(INV_n__read4856__q38[30] ? 5'd30 : 5'd31) :
|
|
(INV_n__read4856__q38[28] ? 5'd28 : 5'd29)) :
|
|
((!INV_n__read4856__q38[24] &&
|
|
!INV_n__read4856__q38[25]) ?
|
|
(INV_n__read4856__q38[26] ? 5'd26 : 5'd27) :
|
|
(INV_n__read4856__q38[24] ? 5'd24 : 5'd25))) :
|
|
((!INV_n__read4856__q38[16] && !INV_n__read4856__q38[17] &&
|
|
!INV_n__read4856__q38[18] &&
|
|
!INV_n__read4856__q38[19]) ?
|
|
((!INV_n__read4856__q38[20] &&
|
|
!INV_n__read4856__q38[21]) ?
|
|
(INV_n__read4856__q38[22] ? 5'd22 : 5'd23) :
|
|
(INV_n__read4856__q38[20] ? 5'd20 : 5'd21)) :
|
|
((!INV_n__read4856__q38[16] &&
|
|
!INV_n__read4856__q38[17]) ?
|
|
(INV_n__read4856__q38[18] ? 5'd18 : 5'd19) :
|
|
(INV_n__read4856__q38[16] ? 5'd16 : 5'd17)))) :
|
|
((!INV_n__read4856__q38[0] && !INV_n__read4856__q38[1] &&
|
|
!INV_n__read4856__q38[2] &&
|
|
!INV_n__read4856__q38[3] &&
|
|
!INV_n__read4856__q38[4] &&
|
|
!INV_n__read4856__q38[5] &&
|
|
!INV_n__read4856__q38[6] &&
|
|
!INV_n__read4856__q38[7]) ?
|
|
((!INV_n__read4856__q38[8] && !INV_n__read4856__q38[9] &&
|
|
!INV_n__read4856__q38[10] &&
|
|
!INV_n__read4856__q38[11]) ?
|
|
((!INV_n__read4856__q38[12] &&
|
|
!INV_n__read4856__q38[13]) ?
|
|
(INV_n__read4856__q38[14] ? 5'd14 : 5'd15) :
|
|
(INV_n__read4856__q38[12] ? 5'd12 : 5'd13)) :
|
|
((!INV_n__read4856__q38[8] && !INV_n__read4856__q38[9]) ?
|
|
(INV_n__read4856__q38[10] ? 5'd10 : 5'd11) :
|
|
(INV_n__read4856__q38[8] ? 5'd8 : 5'd9))) :
|
|
((!INV_n__read4856__q38[0] && !INV_n__read4856__q38[1] &&
|
|
!INV_n__read4856__q38[2] &&
|
|
!INV_n__read4856__q38[3]) ?
|
|
((!INV_n__read4856__q38[4] && !INV_n__read4856__q38[5]) ?
|
|
(INV_n__read4856__q38[6] ? 5'd6 : 5'd7) :
|
|
(INV_n__read4856__q38[4] ? 5'd4 : 5'd5)) :
|
|
((!INV_n__read4856__q38[0] && !INV_n__read4856__q38[1]) ?
|
|
(INV_n__read4856__q38[2] ? 5'd2 : 5'd3) :
|
|
(INV_n__read4856__q38[0] ? 5'd0 : 5'd1)))) ;
|
|
assign addIdx__h54335 =
|
|
(tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_23_ETC___d729 &&
|
|
tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_30_ETC___d736) ?
|
|
(tlb_m_validVec_16_75_AND_tlb_m_validVec_17_77__ETC___d744 ?
|
|
IF_tlb_m_validVec_24_98_AND_tlb_m_validVec_25__ETC___d755 :
|
|
IF_tlb_m_validVec_16_75_AND_tlb_m_validVec_17__ETC___d762) :
|
|
(tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_23_ETC___d729 ?
|
|
IF_tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_ETC___d770 :
|
|
IF_tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_ETC___d777) ;
|
|
assign idx__h68863 =
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1786 ?
|
|
5'd31 :
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1919 ;
|
|
assign n__read__h44856 =
|
|
tlb_m_lruBit_lat_0$whas ? upd__h44883 : tlb_m_lruBit_rl ;
|
|
assign next_deqP___1__h12848 = rqToPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h17463 = rsFromPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h9212 = hitQ_deqP + 1'd1 ;
|
|
assign tlb_m_validVec_0_28_AND_tlb_m_validVec_1_30_23_ETC___d729 =
|
|
tlb_m_validVec_0 && tlb_m_validVec_1 && tlb_m_validVec_2 &&
|
|
tlb_m_validVec_3 &&
|
|
tlb_m_validVec_4 &&
|
|
tlb_m_validVec_5 &&
|
|
tlb_m_validVec_6 &&
|
|
tlb_m_validVec_7 ;
|
|
assign tlb_m_validVec_16_75_AND_tlb_m_validVec_17_77__ETC___d744 =
|
|
tlb_m_validVec_16 && tlb_m_validVec_17 && tlb_m_validVec_18 &&
|
|
tlb_m_validVec_19 &&
|
|
tlb_m_validVec_20 &&
|
|
tlb_m_validVec_21 &&
|
|
tlb_m_validVec_22 &&
|
|
tlb_m_validVec_23 ;
|
|
assign tlb_m_validVec_8_51_AND_tlb_m_validVec_9_53_30_ETC___d736 =
|
|
tlb_m_validVec_8 && tlb_m_validVec_9 && tlb_m_validVec_10 &&
|
|
tlb_m_validVec_11 &&
|
|
tlb_m_validVec_12 &&
|
|
tlb_m_validVec_13 &&
|
|
tlb_m_validVec_14 &&
|
|
tlb_m_validVec_15 ;
|
|
assign upd__h44883 =
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep ?
|
|
MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1 :
|
|
32'd0 ;
|
|
assign v__h12287 =
|
|
IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 ?
|
|
v__h12438 :
|
|
rqToPQ_enqP ;
|
|
assign v__h12438 = rqToPQ_enqP + 1'd1 ;
|
|
assign v__h16232 =
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 ?
|
|
v__h16383 :
|
|
rsFromPQ_enqP ;
|
|
assign v__h16383 = rsFromPQ_enqP + 1'd1 ;
|
|
assign v__h39303 =
|
|
(NOT_tlb_m_validVec_0_28_29_OR_NOT_tlb_m_validV_ETC___d650 ||
|
|
NOT_tlb_m_validVec_8_51_52_OR_NOT_tlb_m_validV_ETC___d673 ||
|
|
NOT_tlb_m_validVec_16_75_76_OR_NOT_tlb_m_valid_ETC___d697 ||
|
|
NOT_tlb_m_validVec_24_98_99_OR_NOT_tlb_m_valid_ETC___d720) ?
|
|
addIdx__h54335 :
|
|
v__h44120 ;
|
|
assign v__h44120 =
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 ?
|
|
tlb_m_randIdx :
|
|
v__h45648 ;
|
|
assign v__h45648 =
|
|
(INV_n__read4856__q38[0] || INV_n__read4856__q38[1] ||
|
|
INV_n__read4856__q38[2] ||
|
|
INV_n__read4856__q38[3] ||
|
|
INV_n__read4856__q38[4] ||
|
|
INV_n__read4856__q38[5] ||
|
|
INV_n__read4856__q38[6] ||
|
|
INV_n__read4856__q38[7] ||
|
|
INV_n__read4856__q38[8] ||
|
|
INV_n__read4856__q38[9] ||
|
|
INV_n__read4856__q38[10] ||
|
|
INV_n__read4856__q38[11] ||
|
|
INV_n__read4856__q38[12] ||
|
|
INV_n__read4856__q38[13] ||
|
|
INV_n__read4856__q38[14] ||
|
|
INV_n__read4856__q38[15] ||
|
|
INV_n__read4856__q38[16] ||
|
|
INV_n__read4856__q38[17] ||
|
|
INV_n__read4856__q38[18] ||
|
|
INV_n__read4856__q38[19] ||
|
|
INV_n__read4856__q38[20] ||
|
|
INV_n__read4856__q38[21] ||
|
|
INV_n__read4856__q38[22] ||
|
|
INV_n__read4856__q38[23] ||
|
|
INV_n__read4856__q38[24] ||
|
|
INV_n__read4856__q38[25] ||
|
|
INV_n__read4856__q38[26] ||
|
|
INV_n__read4856__q38[27] ||
|
|
INV_n__read4856__q38[28] ||
|
|
INV_n__read4856__q38[29] ||
|
|
INV_n__read4856__q38[30] ||
|
|
INV_n__read4856__q38[31]) ?
|
|
addIdx__h49485 :
|
|
5'd0 ;
|
|
assign v__h8385 =
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ?
|
|
v__h8536 :
|
|
hitQ_enqP ;
|
|
assign v__h8536 = hitQ_enqP + 1'd1 ;
|
|
assign val__h5317 = tlb_m_lruBit_rl | x__h5375 ;
|
|
assign vm_info_43_BIT_46_79_AND_IF_NOT_tlb_m_validVec_ETC___d2198 =
|
|
vm_info[46] &&
|
|
IF_NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m__ETC___d1855 &&
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 &&
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922__ETC___d2178 ;
|
|
assign vm_info_43_BIT_46_79_AND_NOT_tlb_m_validVec_0__ETC___d2203 =
|
|
vm_info[46] &&
|
|
NOT_tlb_m_validVec_0_28_29_OR_NOT_IF_tlb_m_ent_ETC___d1786 &&
|
|
(!tlb_m_validVec_31 ||
|
|
!IF_tlb_m_entryVec_31_348_BITS_1_TO_0_352_EQ_0__ETC___d1793) ;
|
|
assign x__h5375 = 32'd1 << tlb_m_updRepIdx_rl[4:0] ;
|
|
assign x__h64080 = { 8'd0, x__h64088 } ;
|
|
assign x__h73590 = { 8'd0, x__h73598 } ;
|
|
assign x__h8655 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[69:6] :
|
|
hitQ_enqReq_rl[69:6] ;
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0: level__h32531 = rsFromPQ_data_0[1:0];
|
|
1'd1: level__h32531 = rsFromPQ_data_1[1:0];
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0: x__h73823 = hitQ_data_0[69:6];
|
|
1'd1: x__h73823 = hitQ_data_1[69:6];
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q1 =
|
|
!hitQ_data_0[5];
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q1 =
|
|
!hitQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_1_hit_ETC__q2 =
|
|
hitQ_data_0[4:0];
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_1_hit_ETC__q2 =
|
|
hitQ_data_1[4:0];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 =
|
|
rsFromPQ_data_0[80];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 =
|
|
rsFromPQ_data_1[80];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 =
|
|
rsFromPQ_data_0[7];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 =
|
|
rsFromPQ_data_1[7];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556 =
|
|
rsFromPQ_data_0[52:9];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556 =
|
|
rsFromPQ_data_1[52:9];
|
|
endcase
|
|
end
|
|
always@(level__h32531 or
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556 or miss)
|
|
begin
|
|
case (level__h32531)
|
|
2'd0:
|
|
x__h64088 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556,
|
|
miss[11:0] };
|
|
2'd1:
|
|
x__h64088 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[43:9],
|
|
miss[20:0] };
|
|
2'd2:
|
|
x__h64088 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[43:18],
|
|
miss[29:0] };
|
|
2'd3: x__h64088 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571 =
|
|
rsFromPQ_data_0[3];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571 =
|
|
rsFromPQ_data_1[3];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577 =
|
|
!rsFromPQ_data_0[2];
|
|
1'd1:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577 =
|
|
!rsFromPQ_data_1[2];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542 =
|
|
rsFromPQ_data_0[5];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542 =
|
|
rsFromPQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538 =
|
|
!rsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538 =
|
|
!rsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 =
|
|
rsFromPQ_data_0[79:53];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_39_rs_ETC___d942 =
|
|
rsFromPQ_data_1[79:53];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953 =
|
|
rsFromPQ_data_0[6];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_50_rsFromPQ_d_ETC___d953 =
|
|
rsFromPQ_data_1[6];
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_1 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_1[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q3 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q3 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q3 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q3 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_0 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_0[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q4 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q4 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q4 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q4 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_2 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_2[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q5 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_3 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_3[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q6 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_4 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_4[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q7 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_5 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_5[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q8 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_6 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_6[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q9 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_7 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_7[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q10 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_8 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_8[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q11 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q11 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q11 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q11 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_9 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_9[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q12 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q12 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q12 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q12 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_10 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_10[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q13 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q13 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q13 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q13 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_11 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_11[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q14 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q14 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q14 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q14 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_12 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_12[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q15 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_13 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_13[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q16 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_14 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_14[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q17 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_15 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_15[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q18 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_16 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_16[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q19 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_17 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_17[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q20 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_18 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_18[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q21 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_19 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_19[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q22 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_20 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_20[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q23 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_21 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_21[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q24 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_22 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_22[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q25 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_23 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_23[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q26 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_24 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_24[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q27 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_25 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_25[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q28 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_26 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_26[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q29 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_27 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_27[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q30 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_28 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_28[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q31 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_29 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_29[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q32 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_30 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_30[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q33 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q33 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q33 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q33 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_31 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_31[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q34 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q34 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q34 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q34 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h68863 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h68863)
|
|
5'd0: ppn__h73594 = tlb_m_entryVec_0[52:9];
|
|
5'd1: ppn__h73594 = tlb_m_entryVec_1[52:9];
|
|
5'd2: ppn__h73594 = tlb_m_entryVec_2[52:9];
|
|
5'd3: ppn__h73594 = tlb_m_entryVec_3[52:9];
|
|
5'd4: ppn__h73594 = tlb_m_entryVec_4[52:9];
|
|
5'd5: ppn__h73594 = tlb_m_entryVec_5[52:9];
|
|
5'd6: ppn__h73594 = tlb_m_entryVec_6[52:9];
|
|
5'd7: ppn__h73594 = tlb_m_entryVec_7[52:9];
|
|
5'd8: ppn__h73594 = tlb_m_entryVec_8[52:9];
|
|
5'd9: ppn__h73594 = tlb_m_entryVec_9[52:9];
|
|
5'd10: ppn__h73594 = tlb_m_entryVec_10[52:9];
|
|
5'd11: ppn__h73594 = tlb_m_entryVec_11[52:9];
|
|
5'd12: ppn__h73594 = tlb_m_entryVec_12[52:9];
|
|
5'd13: ppn__h73594 = tlb_m_entryVec_13[52:9];
|
|
5'd14: ppn__h73594 = tlb_m_entryVec_14[52:9];
|
|
5'd15: ppn__h73594 = tlb_m_entryVec_15[52:9];
|
|
5'd16: ppn__h73594 = tlb_m_entryVec_16[52:9];
|
|
5'd17: ppn__h73594 = tlb_m_entryVec_17[52:9];
|
|
5'd18: ppn__h73594 = tlb_m_entryVec_18[52:9];
|
|
5'd19: ppn__h73594 = tlb_m_entryVec_19[52:9];
|
|
5'd20: ppn__h73594 = tlb_m_entryVec_20[52:9];
|
|
5'd21: ppn__h73594 = tlb_m_entryVec_21[52:9];
|
|
5'd22: ppn__h73594 = tlb_m_entryVec_22[52:9];
|
|
5'd23: ppn__h73594 = tlb_m_entryVec_23[52:9];
|
|
5'd24: ppn__h73594 = tlb_m_entryVec_24[52:9];
|
|
5'd25: ppn__h73594 = tlb_m_entryVec_25[52:9];
|
|
5'd26: ppn__h73594 = tlb_m_entryVec_26[52:9];
|
|
5'd27: ppn__h73594 = tlb_m_entryVec_27[52:9];
|
|
5'd28: ppn__h73594 = tlb_m_entryVec_28[52:9];
|
|
5'd29: ppn__h73594 = tlb_m_entryVec_29[52:9];
|
|
5'd30: ppn__h73594 = tlb_m_entryVec_30[52:9];
|
|
5'd31: ppn__h73594 = tlb_m_entryVec_31[52:9];
|
|
endcase
|
|
end
|
|
always@(idx__h68863 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h68863)
|
|
5'd0: level__h68877 = tlb_m_entryVec_0[1:0];
|
|
5'd1: level__h68877 = tlb_m_entryVec_1[1:0];
|
|
5'd2: level__h68877 = tlb_m_entryVec_2[1:0];
|
|
5'd3: level__h68877 = tlb_m_entryVec_3[1:0];
|
|
5'd4: level__h68877 = tlb_m_entryVec_4[1:0];
|
|
5'd5: level__h68877 = tlb_m_entryVec_5[1:0];
|
|
5'd6: level__h68877 = tlb_m_entryVec_6[1:0];
|
|
5'd7: level__h68877 = tlb_m_entryVec_7[1:0];
|
|
5'd8: level__h68877 = tlb_m_entryVec_8[1:0];
|
|
5'd9: level__h68877 = tlb_m_entryVec_9[1:0];
|
|
5'd10: level__h68877 = tlb_m_entryVec_10[1:0];
|
|
5'd11: level__h68877 = tlb_m_entryVec_11[1:0];
|
|
5'd12: level__h68877 = tlb_m_entryVec_12[1:0];
|
|
5'd13: level__h68877 = tlb_m_entryVec_13[1:0];
|
|
5'd14: level__h68877 = tlb_m_entryVec_14[1:0];
|
|
5'd15: level__h68877 = tlb_m_entryVec_15[1:0];
|
|
5'd16: level__h68877 = tlb_m_entryVec_16[1:0];
|
|
5'd17: level__h68877 = tlb_m_entryVec_17[1:0];
|
|
5'd18: level__h68877 = tlb_m_entryVec_18[1:0];
|
|
5'd19: level__h68877 = tlb_m_entryVec_19[1:0];
|
|
5'd20: level__h68877 = tlb_m_entryVec_20[1:0];
|
|
5'd21: level__h68877 = tlb_m_entryVec_21[1:0];
|
|
5'd22: level__h68877 = tlb_m_entryVec_22[1:0];
|
|
5'd23: level__h68877 = tlb_m_entryVec_23[1:0];
|
|
5'd24: level__h68877 = tlb_m_entryVec_24[1:0];
|
|
5'd25: level__h68877 = tlb_m_entryVec_25[1:0];
|
|
5'd26: level__h68877 = tlb_m_entryVec_26[1:0];
|
|
5'd27: level__h68877 = tlb_m_entryVec_27[1:0];
|
|
5'd28: level__h68877 = tlb_m_entryVec_28[1:0];
|
|
5'd29: level__h68877 = tlb_m_entryVec_29[1:0];
|
|
5'd30: level__h68877 = tlb_m_entryVec_30[1:0];
|
|
5'd31: level__h68877 = tlb_m_entryVec_31[1:0];
|
|
endcase
|
|
end
|
|
always@(level__h68877 or ppn__h73594 or to_proc_request_put)
|
|
begin
|
|
case (level__h68877)
|
|
2'd0: x__h73598 = { ppn__h73594, to_proc_request_put[11:0] };
|
|
2'd1: x__h73598 = { ppn__h73594[43:9], to_proc_request_put[20:0] };
|
|
2'd2: x__h73598 = { ppn__h73594[43:18], to_proc_request_put[29:0] };
|
|
2'd3: x__h73598 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h68863 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h68863)
|
|
5'd0:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_0[4];
|
|
5'd1:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_1[4];
|
|
5'd2:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_2[4];
|
|
5'd3:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_3[4];
|
|
5'd4:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_4[4];
|
|
5'd5:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_5[4];
|
|
5'd6:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_6[4];
|
|
5'd7:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_7[4];
|
|
5'd8:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_8[4];
|
|
5'd9:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_9[4];
|
|
5'd10:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_10[4];
|
|
5'd11:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_11[4];
|
|
5'd12:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_12[4];
|
|
5'd13:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_13[4];
|
|
5'd14:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_14[4];
|
|
5'd15:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_15[4];
|
|
5'd16:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_16[4];
|
|
5'd17:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_17[4];
|
|
5'd18:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_18[4];
|
|
5'd19:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_19[4];
|
|
5'd20:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_20[4];
|
|
5'd21:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_21[4];
|
|
5'd22:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_22[4];
|
|
5'd23:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_23[4];
|
|
5'd24:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_24[4];
|
|
5'd25:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_25[4];
|
|
5'd26:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_26[4];
|
|
5'd27:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_27[4];
|
|
5'd28:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_28[4];
|
|
5'd29:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_29[4];
|
|
5'd30:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_30[4];
|
|
5'd31:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_4_922_923__ETC___d1987 =
|
|
!tlb_m_entryVec_31[4];
|
|
endcase
|
|
end
|
|
always@(idx__h68863 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h68863)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_0[3];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_1[3];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_2[3];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_3[3];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_4[3];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_5[3];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_6[3];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_7[3];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_8[3];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_9[3];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_10[3];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_11[3];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_12[3];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_13[3];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_14[3];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_15[3];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_16[3];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_17[3];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_18[3];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_19[3];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_20[3];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_21[3];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_22[3];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_23[3];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_24[3];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_25[3];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_26[3];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_27[3];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_28[3];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_29[3];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_30[3];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_3_071_tlb_m_en_ETC___d2104 =
|
|
tlb_m_entryVec_31[3];
|
|
endcase
|
|
end
|
|
always@(idx__h68863 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h68863)
|
|
5'd0:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_37_BIT_2_106_107__ETC___d2171 =
|
|
!tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h68863 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h68863)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_0[5];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_1[5];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_2[5];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_3[5];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_4[5];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_5[5];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_6[5];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_7[5];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_8[5];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_9[5];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_10[5];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_11[5];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_12[5];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_13[5];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_14[5];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_15[5];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_16[5];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_17[5];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_18[5];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_19[5];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_20[5];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_21[5];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_22[5];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_23[5];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_24[5];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_25[5];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_26[5];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_27[5];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_28[5];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_29[5];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_30[5];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_5_989_tlb_m_en_ETC___d2022 =
|
|
tlb_m_entryVec_31[5];
|
|
endcase
|
|
end
|
|
always@(idx__h68863 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h68863)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_0[7];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_1[7];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_2[7];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_3[7];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_4[7];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_5[7];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_6[7];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_7[7];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_8[7];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_9[7];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_10[7];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_11[7];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_12[7];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_13[7];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_14[7];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_15[7];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_16[7];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_17[7];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_18[7];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_19[7];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_20[7];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_21[7];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_22[7];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_23[7];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_24[7];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_25[7];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_26[7];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_27[7];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_28[7];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_29[7];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_30[7];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_37_BIT_7_857_tlb_m_en_ETC___d1921 =
|
|
tlb_m_entryVec_31[7];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q35 =
|
|
rsFromPQ_data_0[4];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q35 =
|
|
rsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q36 =
|
|
rsFromPQ_data_0[2];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q36 =
|
|
rsFromPQ_data_1[2];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q37 =
|
|
rsFromPQ_data_0[8];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q37 =
|
|
rsFromPQ_data_1[8];
|
|
endcase
|
|
end
|
|
always@(tlb_m_randIdx or INV_n__read4856__q38)
|
|
begin
|
|
case (tlb_m_randIdx)
|
|
5'd0:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[0];
|
|
5'd1:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[1];
|
|
5'd2:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[2];
|
|
5'd3:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[3];
|
|
5'd4:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[4];
|
|
5'd5:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[5];
|
|
5'd6:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[6];
|
|
5'd7:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[7];
|
|
5'd8:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[8];
|
|
5'd9:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[9];
|
|
5'd10:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[10];
|
|
5'd11:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[11];
|
|
5'd12:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[12];
|
|
5'd13:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[13];
|
|
5'd14:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[14];
|
|
5'd15:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[15];
|
|
5'd16:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[16];
|
|
5'd17:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[17];
|
|
5'd18:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[18];
|
|
5'd19:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[19];
|
|
5'd20:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[20];
|
|
5'd21:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[21];
|
|
5'd22:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[22];
|
|
5'd23:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[23];
|
|
5'd24:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[24];
|
|
5'd25:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[25];
|
|
5'd26:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[26];
|
|
5'd27:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[27];
|
|
5'd28:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[28];
|
|
5'd29:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[29];
|
|
5'd30:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[30];
|
|
5'd31:
|
|
CASE_tlb_m_randIdx_0_INV_n__read48568_BIT_0_1__ETC__q39 =
|
|
INV_n__read4856__q38[31];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 65'd0, 5'bxxxxx /* unspecified value */ };
|
|
hitQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 65'd0, 5'bxxxxx /* unspecified value */ };
|
|
hitQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
hitQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
70'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
hitQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
miss <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
needFlush <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 3'bxxx /* unspecified value */ };
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 27'd0;
|
|
rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 27'd0;
|
|
rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
27'bxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
rqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
80'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
rsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
80'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
rsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
rsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 32'd0;
|
|
tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY 5'd0;
|
|
tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 5'bxxxxx /* unspecified value */ };
|
|
tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
vm_info <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
waitFlushP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (flushRqToPQ_clearReq_rl$EN)
|
|
flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_clearReq_rl$D_IN;
|
|
if (flushRqToPQ_deqReq_rl$EN)
|
|
flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_deqReq_rl$D_IN;
|
|
if (flushRqToPQ_empty$EN)
|
|
flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY flushRqToPQ_empty$D_IN;
|
|
if (flushRqToPQ_enqReq_rl$EN)
|
|
flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_enqReq_rl$D_IN;
|
|
if (flushRqToPQ_full$EN)
|
|
flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY flushRqToPQ_full$D_IN;
|
|
if (flushRsFromPQ_clearReq_rl$EN)
|
|
flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_clearReq_rl$D_IN;
|
|
if (flushRsFromPQ_deqReq_rl$EN)
|
|
flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_deqReq_rl$D_IN;
|
|
if (flushRsFromPQ_empty$EN)
|
|
flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_empty$D_IN;
|
|
if (flushRsFromPQ_enqReq_rl$EN)
|
|
flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_enqReq_rl$D_IN;
|
|
if (flushRsFromPQ_full$EN)
|
|
flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY flushRsFromPQ_full$D_IN;
|
|
if (hitQ_clearReq_rl$EN)
|
|
hitQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_clearReq_rl$D_IN;
|
|
if (hitQ_data_0$EN)
|
|
hitQ_data_0 <= `BSV_ASSIGNMENT_DELAY hitQ_data_0$D_IN;
|
|
if (hitQ_data_1$EN)
|
|
hitQ_data_1 <= `BSV_ASSIGNMENT_DELAY hitQ_data_1$D_IN;
|
|
if (hitQ_deqP$EN) hitQ_deqP <= `BSV_ASSIGNMENT_DELAY hitQ_deqP$D_IN;
|
|
if (hitQ_deqReq_rl$EN)
|
|
hitQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_deqReq_rl$D_IN;
|
|
if (hitQ_empty$EN)
|
|
hitQ_empty <= `BSV_ASSIGNMENT_DELAY hitQ_empty$D_IN;
|
|
if (hitQ_enqP$EN) hitQ_enqP <= `BSV_ASSIGNMENT_DELAY hitQ_enqP$D_IN;
|
|
if (hitQ_enqReq_rl$EN)
|
|
hitQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_enqReq_rl$D_IN;
|
|
if (hitQ_full$EN) hitQ_full <= `BSV_ASSIGNMENT_DELAY hitQ_full$D_IN;
|
|
if (miss$EN) miss <= `BSV_ASSIGNMENT_DELAY miss$D_IN;
|
|
if (needFlush$EN) needFlush <= `BSV_ASSIGNMENT_DELAY needFlush$D_IN;
|
|
if (perfReqQ_clearReq_rl$EN)
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
perfReqQ_clearReq_rl$D_IN;
|
|
if (perfReqQ_data_0$EN)
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY perfReqQ_data_0$D_IN;
|
|
if (perfReqQ_deqReq_rl$EN)
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_deqReq_rl$D_IN;
|
|
if (perfReqQ_empty$EN)
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY perfReqQ_empty$D_IN;
|
|
if (perfReqQ_enqReq_rl$EN)
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN;
|
|
if (perfReqQ_full$EN)
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN;
|
|
if (rqToPQ_clearReq_rl$EN)
|
|
rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_clearReq_rl$D_IN;
|
|
if (rqToPQ_data_0$EN)
|
|
rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY rqToPQ_data_0$D_IN;
|
|
if (rqToPQ_data_1$EN)
|
|
rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY rqToPQ_data_1$D_IN;
|
|
if (rqToPQ_deqP$EN)
|
|
rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY rqToPQ_deqP$D_IN;
|
|
if (rqToPQ_deqReq_rl$EN)
|
|
rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_deqReq_rl$D_IN;
|
|
if (rqToPQ_empty$EN)
|
|
rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY rqToPQ_empty$D_IN;
|
|
if (rqToPQ_enqP$EN)
|
|
rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY rqToPQ_enqP$D_IN;
|
|
if (rqToPQ_enqReq_rl$EN)
|
|
rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_enqReq_rl$D_IN;
|
|
if (rqToPQ_full$EN)
|
|
rqToPQ_full <= `BSV_ASSIGNMENT_DELAY rqToPQ_full$D_IN;
|
|
if (rsFromPQ_clearReq_rl$EN)
|
|
rsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
rsFromPQ_clearReq_rl$D_IN;
|
|
if (rsFromPQ_data_0$EN)
|
|
rsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY rsFromPQ_data_0$D_IN;
|
|
if (rsFromPQ_data_1$EN)
|
|
rsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY rsFromPQ_data_1$D_IN;
|
|
if (rsFromPQ_deqP$EN)
|
|
rsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY rsFromPQ_deqP$D_IN;
|
|
if (rsFromPQ_deqReq_rl$EN)
|
|
rsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY rsFromPQ_deqReq_rl$D_IN;
|
|
if (rsFromPQ_empty$EN)
|
|
rsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY rsFromPQ_empty$D_IN;
|
|
if (rsFromPQ_enqP$EN)
|
|
rsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY rsFromPQ_enqP$D_IN;
|
|
if (rsFromPQ_enqReq_rl$EN)
|
|
rsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY rsFromPQ_enqReq_rl$D_IN;
|
|
if (rsFromPQ_full$EN)
|
|
rsFromPQ_full <= `BSV_ASSIGNMENT_DELAY rsFromPQ_full$D_IN;
|
|
if (tlb_m_lruBit_rl$EN)
|
|
tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY tlb_m_lruBit_rl$D_IN;
|
|
if (tlb_m_randIdx$EN)
|
|
tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY tlb_m_randIdx$D_IN;
|
|
if (tlb_m_updRepIdx_rl$EN)
|
|
tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY tlb_m_updRepIdx_rl$D_IN;
|
|
if (tlb_m_validVec_0$EN)
|
|
tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_0$D_IN;
|
|
if (tlb_m_validVec_1$EN)
|
|
tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_1$D_IN;
|
|
if (tlb_m_validVec_10$EN)
|
|
tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_10$D_IN;
|
|
if (tlb_m_validVec_11$EN)
|
|
tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_11$D_IN;
|
|
if (tlb_m_validVec_12$EN)
|
|
tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_12$D_IN;
|
|
if (tlb_m_validVec_13$EN)
|
|
tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_13$D_IN;
|
|
if (tlb_m_validVec_14$EN)
|
|
tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_14$D_IN;
|
|
if (tlb_m_validVec_15$EN)
|
|
tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_15$D_IN;
|
|
if (tlb_m_validVec_16$EN)
|
|
tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_16$D_IN;
|
|
if (tlb_m_validVec_17$EN)
|
|
tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_17$D_IN;
|
|
if (tlb_m_validVec_18$EN)
|
|
tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_18$D_IN;
|
|
if (tlb_m_validVec_19$EN)
|
|
tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_19$D_IN;
|
|
if (tlb_m_validVec_2$EN)
|
|
tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_2$D_IN;
|
|
if (tlb_m_validVec_20$EN)
|
|
tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_20$D_IN;
|
|
if (tlb_m_validVec_21$EN)
|
|
tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_21$D_IN;
|
|
if (tlb_m_validVec_22$EN)
|
|
tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_22$D_IN;
|
|
if (tlb_m_validVec_23$EN)
|
|
tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_23$D_IN;
|
|
if (tlb_m_validVec_24$EN)
|
|
tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_24$D_IN;
|
|
if (tlb_m_validVec_25$EN)
|
|
tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_25$D_IN;
|
|
if (tlb_m_validVec_26$EN)
|
|
tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_26$D_IN;
|
|
if (tlb_m_validVec_27$EN)
|
|
tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_27$D_IN;
|
|
if (tlb_m_validVec_28$EN)
|
|
tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_28$D_IN;
|
|
if (tlb_m_validVec_29$EN)
|
|
tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_29$D_IN;
|
|
if (tlb_m_validVec_3$EN)
|
|
tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_3$D_IN;
|
|
if (tlb_m_validVec_30$EN)
|
|
tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_30$D_IN;
|
|
if (tlb_m_validVec_31$EN)
|
|
tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_31$D_IN;
|
|
if (tlb_m_validVec_4$EN)
|
|
tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_4$D_IN;
|
|
if (tlb_m_validVec_5$EN)
|
|
tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_5$D_IN;
|
|
if (tlb_m_validVec_6$EN)
|
|
tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_6$D_IN;
|
|
if (tlb_m_validVec_7$EN)
|
|
tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_7$D_IN;
|
|
if (tlb_m_validVec_8$EN)
|
|
tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_8$D_IN;
|
|
if (tlb_m_validVec_9$EN)
|
|
tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_9$D_IN;
|
|
if (vm_info$EN) vm_info <= `BSV_ASSIGNMENT_DELAY vm_info$D_IN;
|
|
if (waitFlushP$EN)
|
|
waitFlushP <= `BSV_ASSIGNMENT_DELAY waitFlushP$D_IN;
|
|
end
|
|
if (tlb_m_entryVec_0$EN)
|
|
tlb_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_0$D_IN;
|
|
if (tlb_m_entryVec_1$EN)
|
|
tlb_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_1$D_IN;
|
|
if (tlb_m_entryVec_10$EN)
|
|
tlb_m_entryVec_10 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_10$D_IN;
|
|
if (tlb_m_entryVec_11$EN)
|
|
tlb_m_entryVec_11 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_11$D_IN;
|
|
if (tlb_m_entryVec_12$EN)
|
|
tlb_m_entryVec_12 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_12$D_IN;
|
|
if (tlb_m_entryVec_13$EN)
|
|
tlb_m_entryVec_13 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_13$D_IN;
|
|
if (tlb_m_entryVec_14$EN)
|
|
tlb_m_entryVec_14 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_14$D_IN;
|
|
if (tlb_m_entryVec_15$EN)
|
|
tlb_m_entryVec_15 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_15$D_IN;
|
|
if (tlb_m_entryVec_16$EN)
|
|
tlb_m_entryVec_16 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_16$D_IN;
|
|
if (tlb_m_entryVec_17$EN)
|
|
tlb_m_entryVec_17 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_17$D_IN;
|
|
if (tlb_m_entryVec_18$EN)
|
|
tlb_m_entryVec_18 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_18$D_IN;
|
|
if (tlb_m_entryVec_19$EN)
|
|
tlb_m_entryVec_19 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_19$D_IN;
|
|
if (tlb_m_entryVec_2$EN)
|
|
tlb_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_2$D_IN;
|
|
if (tlb_m_entryVec_20$EN)
|
|
tlb_m_entryVec_20 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_20$D_IN;
|
|
if (tlb_m_entryVec_21$EN)
|
|
tlb_m_entryVec_21 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_21$D_IN;
|
|
if (tlb_m_entryVec_22$EN)
|
|
tlb_m_entryVec_22 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_22$D_IN;
|
|
if (tlb_m_entryVec_23$EN)
|
|
tlb_m_entryVec_23 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_23$D_IN;
|
|
if (tlb_m_entryVec_24$EN)
|
|
tlb_m_entryVec_24 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_24$D_IN;
|
|
if (tlb_m_entryVec_25$EN)
|
|
tlb_m_entryVec_25 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_25$D_IN;
|
|
if (tlb_m_entryVec_26$EN)
|
|
tlb_m_entryVec_26 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_26$D_IN;
|
|
if (tlb_m_entryVec_27$EN)
|
|
tlb_m_entryVec_27 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_27$D_IN;
|
|
if (tlb_m_entryVec_28$EN)
|
|
tlb_m_entryVec_28 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_28$D_IN;
|
|
if (tlb_m_entryVec_29$EN)
|
|
tlb_m_entryVec_29 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_29$D_IN;
|
|
if (tlb_m_entryVec_3$EN)
|
|
tlb_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_3$D_IN;
|
|
if (tlb_m_entryVec_30$EN)
|
|
tlb_m_entryVec_30 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_30$D_IN;
|
|
if (tlb_m_entryVec_31$EN)
|
|
tlb_m_entryVec_31 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_31$D_IN;
|
|
if (tlb_m_entryVec_4$EN)
|
|
tlb_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_4$D_IN;
|
|
if (tlb_m_entryVec_5$EN)
|
|
tlb_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_5$D_IN;
|
|
if (tlb_m_entryVec_6$EN)
|
|
tlb_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_6$D_IN;
|
|
if (tlb_m_entryVec_7$EN)
|
|
tlb_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_7$D_IN;
|
|
if (tlb_m_entryVec_8$EN)
|
|
tlb_m_entryVec_8 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_8$D_IN;
|
|
if (tlb_m_entryVec_9$EN)
|
|
tlb_m_entryVec_9 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_9$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
flushRqToPQ_clearReq_rl = 1'h0;
|
|
flushRqToPQ_deqReq_rl = 1'h0;
|
|
flushRqToPQ_empty = 1'h0;
|
|
flushRqToPQ_enqReq_rl = 1'h0;
|
|
flushRqToPQ_full = 1'h0;
|
|
flushRsFromPQ_clearReq_rl = 1'h0;
|
|
flushRsFromPQ_deqReq_rl = 1'h0;
|
|
flushRsFromPQ_empty = 1'h0;
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flushRsFromPQ_enqReq_rl = 1'h0;
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flushRsFromPQ_full = 1'h0;
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hitQ_clearReq_rl = 1'h0;
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hitQ_data_0 = 70'h2AAAAAAAAAAAAAAAAA;
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hitQ_data_1 = 70'h2AAAAAAAAAAAAAAAAA;
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hitQ_deqP = 1'h0;
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hitQ_deqReq_rl = 1'h0;
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hitQ_empty = 1'h0;
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hitQ_enqP = 1'h0;
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hitQ_enqReq_rl = 71'h2AAAAAAAAAAAAAAAAA;
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hitQ_full = 1'h0;
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miss = 65'h0AAAAAAAAAAAAAAAA;
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needFlush = 1'h0;
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perfReqQ_clearReq_rl = 1'h0;
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perfReqQ_data_0 = 3'h2;
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perfReqQ_deqReq_rl = 1'h0;
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perfReqQ_empty = 1'h0;
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perfReqQ_enqReq_rl = 4'hA;
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perfReqQ_full = 1'h0;
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rqToPQ_clearReq_rl = 1'h0;
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rqToPQ_data_0 = 27'h2AAAAAA;
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rqToPQ_data_1 = 27'h2AAAAAA;
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rqToPQ_deqP = 1'h0;
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|
rqToPQ_deqReq_rl = 1'h0;
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|
rqToPQ_empty = 1'h0;
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rqToPQ_enqP = 1'h0;
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|
rqToPQ_enqReq_rl = 28'hAAAAAAA;
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|
rqToPQ_full = 1'h0;
|
|
rsFromPQ_clearReq_rl = 1'h0;
|
|
rsFromPQ_data_0 = 81'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_data_1 = 81'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_deqP = 1'h0;
|
|
rsFromPQ_deqReq_rl = 1'h0;
|
|
rsFromPQ_empty = 1'h0;
|
|
rsFromPQ_enqP = 1'h0;
|
|
rsFromPQ_enqReq_rl = 82'h2AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_full = 1'h0;
|
|
tlb_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_10 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_11 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_12 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_13 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_14 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_15 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_16 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_17 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_18 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_19 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_20 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_21 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_22 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_23 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_24 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_25 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_26 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_27 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_28 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_29 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_30 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_31 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_8 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_9 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_lruBit_rl = 32'hAAAAAAAA;
|
|
tlb_m_randIdx = 5'h0A;
|
|
tlb_m_updRepIdx_rl = 6'h2A;
|
|
tlb_m_validVec_0 = 1'h0;
|
|
tlb_m_validVec_1 = 1'h0;
|
|
tlb_m_validVec_10 = 1'h0;
|
|
tlb_m_validVec_11 = 1'h0;
|
|
tlb_m_validVec_12 = 1'h0;
|
|
tlb_m_validVec_13 = 1'h0;
|
|
tlb_m_validVec_14 = 1'h0;
|
|
tlb_m_validVec_15 = 1'h0;
|
|
tlb_m_validVec_16 = 1'h0;
|
|
tlb_m_validVec_17 = 1'h0;
|
|
tlb_m_validVec_18 = 1'h0;
|
|
tlb_m_validVec_19 = 1'h0;
|
|
tlb_m_validVec_2 = 1'h0;
|
|
tlb_m_validVec_20 = 1'h0;
|
|
tlb_m_validVec_21 = 1'h0;
|
|
tlb_m_validVec_22 = 1'h0;
|
|
tlb_m_validVec_23 = 1'h0;
|
|
tlb_m_validVec_24 = 1'h0;
|
|
tlb_m_validVec_25 = 1'h0;
|
|
tlb_m_validVec_26 = 1'h0;
|
|
tlb_m_validVec_27 = 1'h0;
|
|
tlb_m_validVec_28 = 1'h0;
|
|
tlb_m_validVec_29 = 1'h0;
|
|
tlb_m_validVec_3 = 1'h0;
|
|
tlb_m_validVec_30 = 1'h0;
|
|
tlb_m_validVec_31 = 1'h0;
|
|
tlb_m_validVec_4 = 1'h0;
|
|
tlb_m_validVec_5 = 1'h0;
|
|
tlb_m_validVec_6 = 1'h0;
|
|
tlb_m_validVec_7 = 1'h0;
|
|
tlb_m_validVec_8 = 1'h0;
|
|
tlb_m_validVec_9 = 1'h0;
|
|
vm_info = 49'h0AAAAAAAAAAAA;
|
|
waitFlushP = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkITlb
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