4970 lines
197 KiB
Verilog
4970 lines
197 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:33:46 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_updateVMInfo O 1 const
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// RDY_toChildren_rqFromC_put O 1
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// toChildren_rsToC_notEmpty O 1
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// RDY_toChildren_rsToC_notEmpty O 1 const
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// RDY_toChildren_rsToC_deq O 1
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// toChildren_rsToC_first O 84
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// RDY_toChildren_rsToC_first O 1
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// RDY_toChildren_iTlbReqFlush_put O 1
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// RDY_toChildren_dTlbReqFlush_put O 1
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// RDY_toChildren_flushDone_get O 1
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// toMem_memReq_notEmpty O 1
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// RDY_toMem_memReq_notEmpty O 1 const
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// RDY_toMem_memReq_deq O 1
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// toMem_memReq_first O 65
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// RDY_toMem_memReq_first O 1
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// toMem_respLd_notFull O 1
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// RDY_toMem_respLd_notFull O 1 const
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// RDY_toMem_respLd_enq O 1
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// RDY_perf_setStatus O 1 const
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// RDY_perf_req O 1
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// perf_resp O 68
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// RDY_perf_resp O 1
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// perf_respValid O 1
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// RDY_perf_respValid O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// updateVMInfo_vmI I 49 reg
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// updateVMInfo_vmD I 49 reg
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// toChildren_rqFromC_put I 30
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// toMem_respLd_enq_x I 65
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// perf_setStatus_doStats I 1 unused
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// perf_req_r I 4
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// EN_updateVMInfo I 1
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// EN_toChildren_rqFromC_put I 1
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// EN_toChildren_rsToC_deq I 1
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// EN_toChildren_iTlbReqFlush_put I 1
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// EN_toChildren_dTlbReqFlush_put I 1
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// EN_toChildren_flushDone_get I 1
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// EN_toMem_memReq_deq I 1
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// EN_toMem_respLd_enq I 1
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// EN_perf_setStatus I 1 unused
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// EN_perf_req I 1
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// EN_perf_resp I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkL2Tlb(CLK,
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RST_N,
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updateVMInfo_vmI,
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updateVMInfo_vmD,
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EN_updateVMInfo,
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RDY_updateVMInfo,
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toChildren_rqFromC_put,
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EN_toChildren_rqFromC_put,
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RDY_toChildren_rqFromC_put,
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toChildren_rsToC_notEmpty,
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RDY_toChildren_rsToC_notEmpty,
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EN_toChildren_rsToC_deq,
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RDY_toChildren_rsToC_deq,
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toChildren_rsToC_first,
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RDY_toChildren_rsToC_first,
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EN_toChildren_iTlbReqFlush_put,
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RDY_toChildren_iTlbReqFlush_put,
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EN_toChildren_dTlbReqFlush_put,
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RDY_toChildren_dTlbReqFlush_put,
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EN_toChildren_flushDone_get,
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RDY_toChildren_flushDone_get,
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toMem_memReq_notEmpty,
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RDY_toMem_memReq_notEmpty,
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EN_toMem_memReq_deq,
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RDY_toMem_memReq_deq,
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toMem_memReq_first,
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RDY_toMem_memReq_first,
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toMem_respLd_notFull,
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RDY_toMem_respLd_notFull,
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toMem_respLd_enq_x,
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EN_toMem_respLd_enq,
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RDY_toMem_respLd_enq,
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perf_setStatus_doStats,
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EN_perf_setStatus,
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RDY_perf_setStatus,
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perf_req_r,
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EN_perf_req,
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RDY_perf_req,
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EN_perf_resp,
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perf_resp,
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RDY_perf_resp,
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perf_respValid,
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RDY_perf_respValid);
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input CLK;
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input RST_N;
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// action method updateVMInfo
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input [48 : 0] updateVMInfo_vmI;
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input [48 : 0] updateVMInfo_vmD;
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input EN_updateVMInfo;
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output RDY_updateVMInfo;
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// action method toChildren_rqFromC_put
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input [29 : 0] toChildren_rqFromC_put;
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input EN_toChildren_rqFromC_put;
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output RDY_toChildren_rqFromC_put;
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// value method toChildren_rsToC_notEmpty
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output toChildren_rsToC_notEmpty;
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output RDY_toChildren_rsToC_notEmpty;
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// action method toChildren_rsToC_deq
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input EN_toChildren_rsToC_deq;
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output RDY_toChildren_rsToC_deq;
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// value method toChildren_rsToC_first
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output [83 : 0] toChildren_rsToC_first;
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output RDY_toChildren_rsToC_first;
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// action method toChildren_iTlbReqFlush_put
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input EN_toChildren_iTlbReqFlush_put;
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output RDY_toChildren_iTlbReqFlush_put;
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// action method toChildren_dTlbReqFlush_put
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input EN_toChildren_dTlbReqFlush_put;
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output RDY_toChildren_dTlbReqFlush_put;
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// action method toChildren_flushDone_get
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input EN_toChildren_flushDone_get;
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output RDY_toChildren_flushDone_get;
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// value method toMem_memReq_notEmpty
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output toMem_memReq_notEmpty;
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output RDY_toMem_memReq_notEmpty;
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// action method toMem_memReq_deq
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input EN_toMem_memReq_deq;
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output RDY_toMem_memReq_deq;
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// value method toMem_memReq_first
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output [64 : 0] toMem_memReq_first;
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output RDY_toMem_memReq_first;
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// value method toMem_respLd_notFull
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output toMem_respLd_notFull;
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output RDY_toMem_respLd_notFull;
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// action method toMem_respLd_enq
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input [64 : 0] toMem_respLd_enq_x;
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input EN_toMem_respLd_enq;
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output RDY_toMem_respLd_enq;
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// action method perf_setStatus
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input perf_setStatus_doStats;
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input EN_perf_setStatus;
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output RDY_perf_setStatus;
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// action method perf_req
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input [3 : 0] perf_req_r;
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input EN_perf_req;
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output RDY_perf_req;
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// actionvalue method perf_resp
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input EN_perf_resp;
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output [67 : 0] perf_resp;
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output RDY_perf_resp;
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// value method perf_respValid
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output perf_respValid;
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output RDY_perf_respValid;
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// signals for module outputs
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wire [83 : 0] toChildren_rsToC_first;
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wire [67 : 0] perf_resp;
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wire [64 : 0] toMem_memReq_first;
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wire RDY_perf_req,
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RDY_perf_resp,
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RDY_perf_respValid,
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RDY_perf_setStatus,
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RDY_toChildren_dTlbReqFlush_put,
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RDY_toChildren_flushDone_get,
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RDY_toChildren_iTlbReqFlush_put,
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RDY_toChildren_rqFromC_put,
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RDY_toChildren_rsToC_deq,
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RDY_toChildren_rsToC_first,
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RDY_toChildren_rsToC_notEmpty,
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RDY_toMem_memReq_deq,
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RDY_toMem_memReq_first,
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RDY_toMem_memReq_notEmpty,
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RDY_toMem_respLd_enq,
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RDY_toMem_respLd_notFull,
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RDY_updateVMInfo,
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perf_respValid,
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toChildren_rsToC_notEmpty,
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toMem_memReq_notEmpty,
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toMem_respLd_notFull;
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// inlined wires
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wire [83 : 0] rsToCQ_data_0_lat_0$wget;
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wire [81 : 0] tlb4KB_m_pendReq_lat_0$wget, tlb4KB_m_pendReq_lat_1$wget;
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wire [65 : 0] memReqQ_enqReq_lat_0$wget,
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memReqQ_enqReq_lat_2$wget,
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respLdQ_enqReq_lat_0$wget;
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wire [8 : 0] tlb4KB_m_pendIndex$wget;
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wire [4 : 0] perfReqQ_enqReq_lat_0$wget, perfReqQ_enqReq_lat_2$wget;
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wire [3 : 0] tlbMG_m_updRepIdx_lat_0$wget, tlbMG_m_updRepIdx_lat_1$wget;
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wire [2 : 0] pendWait_0_lat_0$wget, pendWait_1_lat_0$wget;
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wire memReqQ_enqReq_lat_0$whas,
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pendValid_0_lat_0$whas,
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pendValid_0_lat_1$whas,
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pendValid_1_lat_0$whas,
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pendValid_1_lat_1$whas,
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pendWait_0_lat_0$whas,
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pendWait_1_lat_0$whas,
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respLdQ_deqReq_lat_0$whas,
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rsToCQ_data_0_lat_0$whas,
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tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas,
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tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas,
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tlbMG_m_lruBit_lat_0$whas,
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tlbMG_m_updRepIdx_lat_1$whas,
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transCacheReqQ_enqP_lat_0$whas;
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// register dFlushReq
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reg dFlushReq;
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wire dFlushReq$D_IN, dFlushReq$EN;
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// register flushDoneQ_clearReq_rl
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reg flushDoneQ_clearReq_rl;
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wire flushDoneQ_clearReq_rl$D_IN, flushDoneQ_clearReq_rl$EN;
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// register flushDoneQ_deqReq_rl
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reg flushDoneQ_deqReq_rl;
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wire flushDoneQ_deqReq_rl$D_IN, flushDoneQ_deqReq_rl$EN;
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// register flushDoneQ_empty
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reg flushDoneQ_empty;
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wire flushDoneQ_empty$D_IN, flushDoneQ_empty$EN;
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// register flushDoneQ_enqReq_rl
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reg flushDoneQ_enqReq_rl;
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wire flushDoneQ_enqReq_rl$D_IN, flushDoneQ_enqReq_rl$EN;
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// register flushDoneQ_full
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reg flushDoneQ_full;
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wire flushDoneQ_full$D_IN, flushDoneQ_full$EN;
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// register iFlushReq
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reg iFlushReq;
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wire iFlushReq$D_IN, iFlushReq$EN;
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// register memReqQ_clearReq_rl
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reg memReqQ_clearReq_rl;
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wire memReqQ_clearReq_rl$D_IN, memReqQ_clearReq_rl$EN;
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// register memReqQ_data_0
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reg [64 : 0] memReqQ_data_0;
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wire [64 : 0] memReqQ_data_0$D_IN;
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wire memReqQ_data_0$EN;
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// register memReqQ_data_1
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reg [64 : 0] memReqQ_data_1;
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wire [64 : 0] memReqQ_data_1$D_IN;
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wire memReqQ_data_1$EN;
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// register memReqQ_deqP
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reg memReqQ_deqP;
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wire memReqQ_deqP$D_IN, memReqQ_deqP$EN;
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// register memReqQ_deqReq_rl
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reg memReqQ_deqReq_rl;
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wire memReqQ_deqReq_rl$D_IN, memReqQ_deqReq_rl$EN;
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// register memReqQ_empty
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reg memReqQ_empty;
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wire memReqQ_empty$D_IN, memReqQ_empty$EN;
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// register memReqQ_enqP
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reg memReqQ_enqP;
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wire memReqQ_enqP$D_IN, memReqQ_enqP$EN;
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// register memReqQ_enqReq_rl
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reg [65 : 0] memReqQ_enqReq_rl;
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wire [65 : 0] memReqQ_enqReq_rl$D_IN;
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wire memReqQ_enqReq_rl$EN;
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// register memReqQ_full
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reg memReqQ_full;
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wire memReqQ_full$D_IN, memReqQ_full$EN;
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// register pendReq_0
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reg [29 : 0] pendReq_0;
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wire [29 : 0] pendReq_0$D_IN;
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wire pendReq_0$EN;
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// register pendReq_1
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reg [29 : 0] pendReq_1;
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wire [29 : 0] pendReq_1$D_IN;
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wire pendReq_1$EN;
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// register pendValid_0_rl
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reg pendValid_0_rl;
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wire pendValid_0_rl$D_IN, pendValid_0_rl$EN;
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// register pendValid_1_rl
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reg pendValid_1_rl;
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wire pendValid_1_rl$D_IN, pendValid_1_rl$EN;
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// register pendWait_0_rl
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reg [2 : 0] pendWait_0_rl;
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wire [2 : 0] pendWait_0_rl$D_IN;
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wire pendWait_0_rl$EN;
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// register pendWait_1_rl
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reg [2 : 0] pendWait_1_rl;
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wire [2 : 0] pendWait_1_rl$D_IN;
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wire pendWait_1_rl$EN;
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// register pendWalkAddr_0
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reg [63 : 0] pendWalkAddr_0;
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wire [63 : 0] pendWalkAddr_0$D_IN;
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wire pendWalkAddr_0$EN;
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// register pendWalkAddr_1
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reg [63 : 0] pendWalkAddr_1;
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wire [63 : 0] pendWalkAddr_1$D_IN;
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wire pendWalkAddr_1$EN;
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// register pendWalkLevel_0
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reg [1 : 0] pendWalkLevel_0;
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wire [1 : 0] pendWalkLevel_0$D_IN;
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wire pendWalkLevel_0$EN;
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// register pendWalkLevel_1
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reg [1 : 0] pendWalkLevel_1;
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wire [1 : 0] pendWalkLevel_1$D_IN;
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wire pendWalkLevel_1$EN;
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// register perfReqQ_clearReq_rl
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reg perfReqQ_clearReq_rl;
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wire perfReqQ_clearReq_rl$D_IN, perfReqQ_clearReq_rl$EN;
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// register perfReqQ_data_0
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reg [3 : 0] perfReqQ_data_0;
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wire [3 : 0] perfReqQ_data_0$D_IN;
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wire perfReqQ_data_0$EN;
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// register perfReqQ_deqReq_rl
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reg perfReqQ_deqReq_rl;
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wire perfReqQ_deqReq_rl$D_IN, perfReqQ_deqReq_rl$EN;
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// register perfReqQ_empty
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reg perfReqQ_empty;
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wire perfReqQ_empty$D_IN, perfReqQ_empty$EN;
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// register perfReqQ_enqReq_rl
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reg [4 : 0] perfReqQ_enqReq_rl;
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wire [4 : 0] perfReqQ_enqReq_rl$D_IN;
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wire perfReqQ_enqReq_rl$EN;
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// register perfReqQ_full
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reg perfReqQ_full;
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wire perfReqQ_full$D_IN, perfReqQ_full$EN;
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// register respForOtherReq
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reg [1 : 0] respForOtherReq;
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wire [1 : 0] respForOtherReq$D_IN;
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wire respForOtherReq$EN;
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// register respLdQ_clearReq_rl
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reg respLdQ_clearReq_rl;
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wire respLdQ_clearReq_rl$D_IN, respLdQ_clearReq_rl$EN;
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// register respLdQ_data_0
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reg [64 : 0] respLdQ_data_0;
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wire [64 : 0] respLdQ_data_0$D_IN;
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wire respLdQ_data_0$EN;
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// register respLdQ_data_1
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reg [64 : 0] respLdQ_data_1;
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wire [64 : 0] respLdQ_data_1$D_IN;
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wire respLdQ_data_1$EN;
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// register respLdQ_deqP
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reg respLdQ_deqP;
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wire respLdQ_deqP$D_IN, respLdQ_deqP$EN;
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// register respLdQ_deqReq_rl
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reg respLdQ_deqReq_rl;
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wire respLdQ_deqReq_rl$D_IN, respLdQ_deqReq_rl$EN;
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// register respLdQ_empty
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reg respLdQ_empty;
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wire respLdQ_empty$D_IN, respLdQ_empty$EN;
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// register respLdQ_enqP
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reg respLdQ_enqP;
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wire respLdQ_enqP$D_IN, respLdQ_enqP$EN;
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// register respLdQ_enqReq_rl
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reg [65 : 0] respLdQ_enqReq_rl;
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wire [65 : 0] respLdQ_enqReq_rl$D_IN;
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wire respLdQ_enqReq_rl$EN;
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// register respLdQ_full
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reg respLdQ_full;
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wire respLdQ_full$D_IN, respLdQ_full$EN;
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// register rqFromCQ_data_0_rl
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reg [29 : 0] rqFromCQ_data_0_rl;
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wire [29 : 0] rqFromCQ_data_0_rl$D_IN;
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wire rqFromCQ_data_0_rl$EN;
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// register rqFromCQ_empty_rl
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reg rqFromCQ_empty_rl;
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wire rqFromCQ_empty_rl$D_IN, rqFromCQ_empty_rl$EN;
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// register rqFromCQ_full_rl
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reg rqFromCQ_full_rl;
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wire rqFromCQ_full_rl$D_IN, rqFromCQ_full_rl$EN;
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// register rsToCQ_data_0_rl
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reg [83 : 0] rsToCQ_data_0_rl;
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wire [83 : 0] rsToCQ_data_0_rl$D_IN;
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wire rsToCQ_data_0_rl$EN;
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// register rsToCQ_empty_rl
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reg rsToCQ_empty_rl;
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wire rsToCQ_empty_rl$D_IN, rsToCQ_empty_rl$EN;
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// register rsToCQ_full_rl
|
|
reg rsToCQ_full_rl;
|
|
wire rsToCQ_full_rl$D_IN, rsToCQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_flushIdx
|
|
reg [7 : 0] tlb4KB_m_flushIdx;
|
|
wire [7 : 0] tlb4KB_m_flushIdx$D_IN;
|
|
wire tlb4KB_m_flushIdx$EN;
|
|
|
|
// register tlb4KB_m_pendReq_rl
|
|
reg [81 : 0] tlb4KB_m_pendReq_rl;
|
|
wire [81 : 0] tlb4KB_m_pendReq_rl$D_IN;
|
|
wire tlb4KB_m_pendReq_rl$EN;
|
|
|
|
// register tlb4KB_m_repRam_rdReqQ_empty_rl
|
|
reg tlb4KB_m_repRam_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_repRam_rdReqQ_full_rl
|
|
reg tlb4KB_m_repRam_rdReqQ_full_rl;
|
|
wire tlb4KB_m_repRam_rdReqQ_full_rl$D_IN, tlb4KB_m_repRam_rdReqQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_state
|
|
reg tlb4KB_m_state;
|
|
wire tlb4KB_m_state$D_IN, tlb4KB_m_state$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_0_rdReqQ_empty_rl
|
|
reg tlb4KB_m_tlbRam_0_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_0_rdReqQ_full_rl
|
|
reg tlb4KB_m_tlbRam_0_rdReqQ_full_rl;
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_1_rdReqQ_empty_rl
|
|
reg tlb4KB_m_tlbRam_1_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_1_rdReqQ_full_rl
|
|
reg tlb4KB_m_tlbRam_1_rdReqQ_full_rl;
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_2_rdReqQ_empty_rl
|
|
reg tlb4KB_m_tlbRam_2_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_2_rdReqQ_full_rl
|
|
reg tlb4KB_m_tlbRam_2_rdReqQ_full_rl;
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_3_rdReqQ_empty_rl
|
|
reg tlb4KB_m_tlbRam_3_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_3_rdReqQ_full_rl
|
|
reg tlb4KB_m_tlbRam_3_rdReqQ_full_rl;
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN;
|
|
|
|
// register tlbMG_m_entryVec_0
|
|
reg [79 : 0] tlbMG_m_entryVec_0;
|
|
wire [79 : 0] tlbMG_m_entryVec_0$D_IN;
|
|
wire tlbMG_m_entryVec_0$EN;
|
|
|
|
// register tlbMG_m_entryVec_1
|
|
reg [79 : 0] tlbMG_m_entryVec_1;
|
|
wire [79 : 0] tlbMG_m_entryVec_1$D_IN;
|
|
wire tlbMG_m_entryVec_1$EN;
|
|
|
|
// register tlbMG_m_entryVec_2
|
|
reg [79 : 0] tlbMG_m_entryVec_2;
|
|
wire [79 : 0] tlbMG_m_entryVec_2$D_IN;
|
|
wire tlbMG_m_entryVec_2$EN;
|
|
|
|
// register tlbMG_m_entryVec_3
|
|
reg [79 : 0] tlbMG_m_entryVec_3;
|
|
wire [79 : 0] tlbMG_m_entryVec_3$D_IN;
|
|
wire tlbMG_m_entryVec_3$EN;
|
|
|
|
// register tlbMG_m_entryVec_4
|
|
reg [79 : 0] tlbMG_m_entryVec_4;
|
|
wire [79 : 0] tlbMG_m_entryVec_4$D_IN;
|
|
wire tlbMG_m_entryVec_4$EN;
|
|
|
|
// register tlbMG_m_entryVec_5
|
|
reg [79 : 0] tlbMG_m_entryVec_5;
|
|
wire [79 : 0] tlbMG_m_entryVec_5$D_IN;
|
|
wire tlbMG_m_entryVec_5$EN;
|
|
|
|
// register tlbMG_m_entryVec_6
|
|
reg [79 : 0] tlbMG_m_entryVec_6;
|
|
wire [79 : 0] tlbMG_m_entryVec_6$D_IN;
|
|
wire tlbMG_m_entryVec_6$EN;
|
|
|
|
// register tlbMG_m_entryVec_7
|
|
reg [79 : 0] tlbMG_m_entryVec_7;
|
|
wire [79 : 0] tlbMG_m_entryVec_7$D_IN;
|
|
wire tlbMG_m_entryVec_7$EN;
|
|
|
|
// register tlbMG_m_lruBit_rl
|
|
reg [7 : 0] tlbMG_m_lruBit_rl;
|
|
wire [7 : 0] tlbMG_m_lruBit_rl$D_IN;
|
|
wire tlbMG_m_lruBit_rl$EN;
|
|
|
|
// register tlbMG_m_randIdx
|
|
reg [2 : 0] tlbMG_m_randIdx;
|
|
wire [2 : 0] tlbMG_m_randIdx$D_IN;
|
|
wire tlbMG_m_randIdx$EN;
|
|
|
|
// register tlbMG_m_updRepIdx_rl
|
|
reg [3 : 0] tlbMG_m_updRepIdx_rl;
|
|
wire [3 : 0] tlbMG_m_updRepIdx_rl$D_IN;
|
|
wire tlbMG_m_updRepIdx_rl$EN;
|
|
|
|
// register tlbMG_m_validVec_0
|
|
reg tlbMG_m_validVec_0;
|
|
wire tlbMG_m_validVec_0$D_IN, tlbMG_m_validVec_0$EN;
|
|
|
|
// register tlbMG_m_validVec_1
|
|
reg tlbMG_m_validVec_1;
|
|
wire tlbMG_m_validVec_1$D_IN, tlbMG_m_validVec_1$EN;
|
|
|
|
// register tlbMG_m_validVec_2
|
|
reg tlbMG_m_validVec_2;
|
|
wire tlbMG_m_validVec_2$D_IN, tlbMG_m_validVec_2$EN;
|
|
|
|
// register tlbMG_m_validVec_3
|
|
reg tlbMG_m_validVec_3;
|
|
wire tlbMG_m_validVec_3$D_IN, tlbMG_m_validVec_3$EN;
|
|
|
|
// register tlbMG_m_validVec_4
|
|
reg tlbMG_m_validVec_4;
|
|
wire tlbMG_m_validVec_4$D_IN, tlbMG_m_validVec_4$EN;
|
|
|
|
// register tlbMG_m_validVec_5
|
|
reg tlbMG_m_validVec_5;
|
|
wire tlbMG_m_validVec_5$D_IN, tlbMG_m_validVec_5$EN;
|
|
|
|
// register tlbMG_m_validVec_6
|
|
reg tlbMG_m_validVec_6;
|
|
wire tlbMG_m_validVec_6$D_IN, tlbMG_m_validVec_6$EN;
|
|
|
|
// register tlbMG_m_validVec_7
|
|
reg tlbMG_m_validVec_7;
|
|
wire tlbMG_m_validVec_7$D_IN, tlbMG_m_validVec_7$EN;
|
|
|
|
// register tlbReqQ_data_0
|
|
reg tlbReqQ_data_0;
|
|
wire tlbReqQ_data_0$D_IN, tlbReqQ_data_0$EN;
|
|
|
|
// register tlbReqQ_empty_rl
|
|
reg tlbReqQ_empty_rl;
|
|
wire tlbReqQ_empty_rl$D_IN, tlbReqQ_empty_rl$EN;
|
|
|
|
// register tlbReqQ_full_rl
|
|
reg tlbReqQ_full_rl;
|
|
wire tlbReqQ_full_rl$D_IN, tlbReqQ_full_rl$EN;
|
|
|
|
// register transCacheReqQ_data_0
|
|
reg transCacheReqQ_data_0;
|
|
wire transCacheReqQ_data_0$D_IN, transCacheReqQ_data_0$EN;
|
|
|
|
// register transCacheReqQ_empty_rl
|
|
reg transCacheReqQ_empty_rl;
|
|
wire transCacheReqQ_empty_rl$D_IN, transCacheReqQ_empty_rl$EN;
|
|
|
|
// register transCacheReqQ_full_rl
|
|
reg transCacheReqQ_full_rl;
|
|
wire transCacheReqQ_full_rl$D_IN, transCacheReqQ_full_rl$EN;
|
|
|
|
// register vm_info_D
|
|
reg [48 : 0] vm_info_D;
|
|
wire [48 : 0] vm_info_D$D_IN;
|
|
wire vm_info_D$EN;
|
|
|
|
// register vm_info_I
|
|
reg [48 : 0] vm_info_I;
|
|
wire [48 : 0] vm_info_I$D_IN;
|
|
wire vm_info_I$EN;
|
|
|
|
// register waitFlushDone
|
|
reg waitFlushDone;
|
|
wire waitFlushDone$D_IN, waitFlushDone$EN;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_bram
|
|
reg [7 : 0] tlb4KB_m_repRam_bram$ADDRA, tlb4KB_m_repRam_bram$DIA;
|
|
wire [7 : 0] tlb4KB_m_repRam_bram$ADDRB,
|
|
tlb4KB_m_repRam_bram$DIB,
|
|
tlb4KB_m_repRam_bram$DOB;
|
|
wire tlb4KB_m_repRam_bram$ENA,
|
|
tlb4KB_m_repRam_bram$ENB,
|
|
tlb4KB_m_repRam_bram$WEA,
|
|
tlb4KB_m_repRam_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_bram
|
|
wire [80 : 0] tlb4KB_m_tlbRam_0_bram$DIA,
|
|
tlb4KB_m_tlbRam_0_bram$DIB,
|
|
tlb4KB_m_tlbRam_0_bram$DOB;
|
|
wire [7 : 0] tlb4KB_m_tlbRam_0_bram$ADDRA, tlb4KB_m_tlbRam_0_bram$ADDRB;
|
|
wire tlb4KB_m_tlbRam_0_bram$ENA,
|
|
tlb4KB_m_tlbRam_0_bram$ENB,
|
|
tlb4KB_m_tlbRam_0_bram$WEA,
|
|
tlb4KB_m_tlbRam_0_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_bram
|
|
wire [80 : 0] tlb4KB_m_tlbRam_1_bram$DIA,
|
|
tlb4KB_m_tlbRam_1_bram$DIB,
|
|
tlb4KB_m_tlbRam_1_bram$DOB;
|
|
wire [7 : 0] tlb4KB_m_tlbRam_1_bram$ADDRA, tlb4KB_m_tlbRam_1_bram$ADDRB;
|
|
wire tlb4KB_m_tlbRam_1_bram$ENA,
|
|
tlb4KB_m_tlbRam_1_bram$ENB,
|
|
tlb4KB_m_tlbRam_1_bram$WEA,
|
|
tlb4KB_m_tlbRam_1_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_bram
|
|
wire [80 : 0] tlb4KB_m_tlbRam_2_bram$DIA,
|
|
tlb4KB_m_tlbRam_2_bram$DIB,
|
|
tlb4KB_m_tlbRam_2_bram$DOB;
|
|
wire [7 : 0] tlb4KB_m_tlbRam_2_bram$ADDRA, tlb4KB_m_tlbRam_2_bram$ADDRB;
|
|
wire tlb4KB_m_tlbRam_2_bram$ENA,
|
|
tlb4KB_m_tlbRam_2_bram$ENB,
|
|
tlb4KB_m_tlbRam_2_bram$WEA,
|
|
tlb4KB_m_tlbRam_2_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_bram
|
|
wire [80 : 0] tlb4KB_m_tlbRam_3_bram$DIA,
|
|
tlb4KB_m_tlbRam_3_bram$DIB,
|
|
tlb4KB_m_tlbRam_3_bram$DOB;
|
|
wire [7 : 0] tlb4KB_m_tlbRam_3_bram$ADDRA, tlb4KB_m_tlbRam_3_bram$ADDRB;
|
|
wire tlb4KB_m_tlbRam_3_bram$ENA,
|
|
tlb4KB_m_tlbRam_3_bram$ENB,
|
|
tlb4KB_m_tlbRam_3_bram$WEA,
|
|
tlb4KB_m_tlbRam_3_bram$WEB;
|
|
|
|
// ports of submodule transCache
|
|
wire [45 : 0] transCache$resp;
|
|
wire [43 : 0] transCache$addEntry_ppn;
|
|
wire [26 : 0] transCache$addEntry_vpn, transCache$req_vpn;
|
|
wire [1 : 0] transCache$addEntry_level;
|
|
wire transCache$EN_addEntry,
|
|
transCache$EN_deqResp,
|
|
transCache$EN_flush,
|
|
transCache$EN_req,
|
|
transCache$RDY_addEntry,
|
|
transCache$RDY_deqResp,
|
|
transCache$RDY_req,
|
|
transCache$RDY_resp,
|
|
transCache$flush_done;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_doPageWalk,
|
|
CAN_FIRE_RL_doStartFlush,
|
|
CAN_FIRE_RL_doTlbReq,
|
|
CAN_FIRE_RL_doTlbResp,
|
|
CAN_FIRE_RL_doTranslationCacheResp,
|
|
CAN_FIRE_RL_doWaitFlush,
|
|
CAN_FIRE_RL_flushDoneQ_canonicalize,
|
|
CAN_FIRE_RL_flushDoneQ_clearReq_canon,
|
|
CAN_FIRE_RL_flushDoneQ_deqReq_canon,
|
|
CAN_FIRE_RL_flushDoneQ_enqReq_canon,
|
|
CAN_FIRE_RL_memReqQ_canonicalize,
|
|
CAN_FIRE_RL_memReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_memReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_memReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_pendValid_0_canon,
|
|
CAN_FIRE_RL_pendValid_1_canon,
|
|
CAN_FIRE_RL_pendWait_0_canon,
|
|
CAN_FIRE_RL_pendWait_1_canon,
|
|
CAN_FIRE_RL_perfReqQ_canonicalize,
|
|
CAN_FIRE_RL_perfReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_respLdQ_canonicalize,
|
|
CAN_FIRE_RL_respLdQ_clearReq_canon,
|
|
CAN_FIRE_RL_respLdQ_deqReq_canon,
|
|
CAN_FIRE_RL_respLdQ_enqReq_canon,
|
|
CAN_FIRE_RL_rqFromCQ_data_0_canon,
|
|
CAN_FIRE_RL_rqFromCQ_empty_canon,
|
|
CAN_FIRE_RL_rqFromCQ_full_canon,
|
|
CAN_FIRE_RL_rsToCQ_data_0_canon,
|
|
CAN_FIRE_RL_rsToCQ_empty_canon,
|
|
CAN_FIRE_RL_rsToCQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_doAddEntry,
|
|
CAN_FIRE_RL_tlb4KB_m_doFlush,
|
|
CAN_FIRE_RL_tlb4KB_m_pendReq_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_setPendIndex,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlbMG_m_doUpdateRep,
|
|
CAN_FIRE_RL_tlbMG_m_incRandIdx,
|
|
CAN_FIRE_RL_tlbMG_m_lruBit_canon,
|
|
CAN_FIRE_RL_tlbMG_m_updRepIdx_canon,
|
|
CAN_FIRE_RL_tlbReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlbReqQ_full_canon,
|
|
CAN_FIRE_RL_transCacheReqQ_empty_canon,
|
|
CAN_FIRE_RL_transCacheReqQ_full_canon,
|
|
CAN_FIRE_perf_req,
|
|
CAN_FIRE_perf_resp,
|
|
CAN_FIRE_perf_setStatus,
|
|
CAN_FIRE_toChildren_dTlbReqFlush_put,
|
|
CAN_FIRE_toChildren_flushDone_get,
|
|
CAN_FIRE_toChildren_iTlbReqFlush_put,
|
|
CAN_FIRE_toChildren_rqFromC_put,
|
|
CAN_FIRE_toChildren_rsToC_deq,
|
|
CAN_FIRE_toMem_memReq_deq,
|
|
CAN_FIRE_toMem_respLd_enq,
|
|
CAN_FIRE_updateVMInfo,
|
|
WILL_FIRE_RL_doPageWalk,
|
|
WILL_FIRE_RL_doStartFlush,
|
|
WILL_FIRE_RL_doTlbReq,
|
|
WILL_FIRE_RL_doTlbResp,
|
|
WILL_FIRE_RL_doTranslationCacheResp,
|
|
WILL_FIRE_RL_doWaitFlush,
|
|
WILL_FIRE_RL_flushDoneQ_canonicalize,
|
|
WILL_FIRE_RL_flushDoneQ_clearReq_canon,
|
|
WILL_FIRE_RL_flushDoneQ_deqReq_canon,
|
|
WILL_FIRE_RL_flushDoneQ_enqReq_canon,
|
|
WILL_FIRE_RL_memReqQ_canonicalize,
|
|
WILL_FIRE_RL_memReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_memReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_memReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_pendValid_0_canon,
|
|
WILL_FIRE_RL_pendValid_1_canon,
|
|
WILL_FIRE_RL_pendWait_0_canon,
|
|
WILL_FIRE_RL_pendWait_1_canon,
|
|
WILL_FIRE_RL_perfReqQ_canonicalize,
|
|
WILL_FIRE_RL_perfReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_respLdQ_canonicalize,
|
|
WILL_FIRE_RL_respLdQ_clearReq_canon,
|
|
WILL_FIRE_RL_respLdQ_deqReq_canon,
|
|
WILL_FIRE_RL_respLdQ_enqReq_canon,
|
|
WILL_FIRE_RL_rqFromCQ_data_0_canon,
|
|
WILL_FIRE_RL_rqFromCQ_empty_canon,
|
|
WILL_FIRE_RL_rqFromCQ_full_canon,
|
|
WILL_FIRE_RL_rsToCQ_data_0_canon,
|
|
WILL_FIRE_RL_rsToCQ_empty_canon,
|
|
WILL_FIRE_RL_rsToCQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry,
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush,
|
|
WILL_FIRE_RL_tlb4KB_m_pendReq_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_setPendIndex,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlbMG_m_doUpdateRep,
|
|
WILL_FIRE_RL_tlbMG_m_incRandIdx,
|
|
WILL_FIRE_RL_tlbMG_m_lruBit_canon,
|
|
WILL_FIRE_RL_tlbMG_m_updRepIdx_canon,
|
|
WILL_FIRE_RL_tlbReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlbReqQ_full_canon,
|
|
WILL_FIRE_RL_transCacheReqQ_empty_canon,
|
|
WILL_FIRE_RL_transCacheReqQ_full_canon,
|
|
WILL_FIRE_perf_req,
|
|
WILL_FIRE_perf_resp,
|
|
WILL_FIRE_perf_setStatus,
|
|
WILL_FIRE_toChildren_dTlbReqFlush_put,
|
|
WILL_FIRE_toChildren_flushDone_get,
|
|
WILL_FIRE_toChildren_iTlbReqFlush_put,
|
|
WILL_FIRE_toChildren_rqFromC_put,
|
|
WILL_FIRE_toChildren_rsToC_deq,
|
|
WILL_FIRE_toMem_memReq_deq,
|
|
WILL_FIRE_toMem_respLd_enq,
|
|
WILL_FIRE_updateVMInfo;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [83 : 0] MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1,
|
|
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2;
|
|
wire [81 : 0] MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1,
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2;
|
|
wire [80 : 0] MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1,
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_2;
|
|
wire [65 : 0] MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2;
|
|
wire [7 : 0] MUX_tlb4KB_m_flushIdx$write_1__VAL_1,
|
|
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1,
|
|
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3,
|
|
MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1;
|
|
wire [3 : 0] MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1,
|
|
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2;
|
|
wire [2 : 0] MUX_pendWait_0_lat_0$wset_1__VAL_1,
|
|
MUX_pendWait_0_lat_0$wset_1__VAL_2,
|
|
MUX_pendWait_1_lat_0$wset_1__VAL_1,
|
|
MUX_pendWait_1_lat_0$wset_1__VAL_2;
|
|
wire MUX_memReqQ_enqReq_lat_0$wset_1__SEL_1,
|
|
MUX_pendWait_0_lat_0$wset_1__SEL_1,
|
|
MUX_pendWait_1_lat_0$wset_1__SEL_1,
|
|
MUX_rsToCQ_data_0_lat_0$wset_1__SEL_1,
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1,
|
|
MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1,
|
|
MUX_tlb4KB_m_state$write_1__SEL_1,
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1,
|
|
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1,
|
|
MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1,
|
|
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1,
|
|
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_0$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_1$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_2$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_3$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_4$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_5$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_6$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_7$write_1__SEL_1;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1,
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412;
|
|
reg [43 : 0] SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1246,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161,
|
|
masked_ppn__h65874;
|
|
reg [26 : 0] CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn3918__ETC__q4,
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn3918__ETC__q5,
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn3918__ETC__q8,
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn3918__ETC__q10,
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn3918__ETC__q12,
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn3918__ETC__q14,
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn3918__ETC__q15,
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn3918__ETC__q16,
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1358,
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1240,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151,
|
|
masked_vpn__h65873,
|
|
vpn__h53918;
|
|
reg [8 : 0] x__h63417, x__h65508;
|
|
reg [1 : 0] CASE_idx4702_0_pendReq_0_BITS_28_TO_27_1_pendR_ETC__q18,
|
|
CASE_tlbReqQ_data_0_0_pendReq_0_BITS_28_TO_27__ETC__q17,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1293,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236,
|
|
walkLevel__h65400;
|
|
reg CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2,
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q6,
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q7,
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q9,
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q11,
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q13,
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20,
|
|
CASE_transCacheReqQ_data_0_0_NOT_pendReq_0_BIT_ETC__q3,
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903,
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d1407,
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d884,
|
|
SEL_ARR_NOT_respLdQ_data_0_400_BIT_0_401_447_N_ETC___d1450,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1252,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1258,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1260,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1266,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1272,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1278,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1284,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171,
|
|
def__h64929;
|
|
wire [80 : 0] IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138;
|
|
wire [79 : 0] IF_IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_t_ETC___d1296,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136;
|
|
wire [63 : 0] baseAddr__h63103,
|
|
newPTBase__h65402,
|
|
newPTEAddr__h65403,
|
|
pteAddr__h63104;
|
|
wire [55 : 0] x__h63376, x__h65491;
|
|
wire [43 : 0] basePpn__h63372, rootPPN__h63102;
|
|
wire [26 : 0] IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130;
|
|
wire [7 : 0] IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d237,
|
|
INV_n__read1326__q19,
|
|
n__read__h71326,
|
|
upd__h71353,
|
|
val__h20096,
|
|
x__h20154;
|
|
wire [2 : 0] IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1145,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1147,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1149,
|
|
IF_tlbMG_m_updRepIdx_lat_1_whas__74_THEN_tlbMG_ETC___d293,
|
|
IF_tlbMG_m_validVec_0_93_AND_tlbMG_m_validVec__ETC___d1604,
|
|
IF_tlbMG_m_validVec_4_94_AND_tlbMG_m_validVec__ETC___d1601,
|
|
_dfoo30,
|
|
_dfoo32,
|
|
_dfoo34,
|
|
_dfoo36,
|
|
addIdx__h72563,
|
|
addIdx__h73829,
|
|
idx__h55354,
|
|
v__h69837,
|
|
v__h71094,
|
|
v__h71542;
|
|
wire [1 : 0] IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d1324,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d1325,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d233,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d234,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1113,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d220,
|
|
newWalkLevel__h65401,
|
|
w__h55979,
|
|
way__h16259,
|
|
way__h61664;
|
|
wire IF_IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BI_ETC___d1122,
|
|
IF_IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NO_ETC___d1126,
|
|
IF_IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NO_ETC___d1494,
|
|
IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d629,
|
|
IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d638,
|
|
IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d643,
|
|
IF_IF_pendValid_0_lat_0_whas__01_THEN_pendVali_ETC___d852,
|
|
IF_IF_respForOtherReq_397_BIT_1_398_THEN_NOT_r_ETC___d1455,
|
|
IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d714,
|
|
IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d723,
|
|
IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d728,
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d1009,
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932,
|
|
IF_NOT_SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_ETC___d1492,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1109,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1110,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1111,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d214,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d215,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d216,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AN_ETC___d1123,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1006,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1032,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1124,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d957,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d981,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1079,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1080,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1081,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1082,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1083,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1084,
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085,
|
|
IF_NOT_transCacheReqQ_data_0_337_338_OR_NOT_pe_ETC___d1380,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1525,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1555,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1581,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1586,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d891,
|
|
IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1458,
|
|
IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1489,
|
|
IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1531,
|
|
IF_memReqQ_deqReq_lat_1_whas__99_THEN_memReqQ__ETC___d605,
|
|
IF_memReqQ_enqReq_lat_1_whas__70_THEN_memReqQ__ETC___d579,
|
|
IF_pendWait_0_rl_21_BITS_2_TO_1_22_EQ_0_23_OR__ETC___d1508,
|
|
IF_perfReqQ_enqReq_lat_1_whas__39_THEN_perfReq_ETC___d748,
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430,
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1451,
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1568,
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_respForO_ETC___d1515,
|
|
IF_respLdQ_deqReq_lat_1_whas__84_THEN_respLdQ__ETC___d690,
|
|
IF_respLdQ_enqReq_lat_1_whas__55_THEN_respLdQ__ETC___d664,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120,
|
|
IF_tlb4KB_m_repRam_rdReqQ_full_lat_0_whas__5_T_ETC___d839,
|
|
IF_tlb4KB_m_tlbRam_0_rdReqQ_full_lat_0_whas__5_ETC___d827,
|
|
IF_tlb4KB_m_tlbRam_1_rdReqQ_full_lat_0_whas__5_ETC___d830,
|
|
IF_tlb4KB_m_tlbRam_2_rdReqQ_full_lat_0_whas__5_ETC___d833,
|
|
IF_tlb4KB_m_tlbRam_3_rdReqQ_full_lat_0_whas__5_ETC___d836,
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917,
|
|
IF_tlbMG_m_entryVec_1_22_BITS_1_TO_0_23_EQ_0_2_ETC___d940,
|
|
IF_tlbMG_m_entryVec_2_47_BITS_1_TO_0_48_EQ_0_4_ETC___d964,
|
|
IF_tlbMG_m_entryVec_3_71_BITS_1_TO_0_72_EQ_0_7_ETC___d989,
|
|
IF_tlbMG_m_entryVec_4_96_BITS_1_TO_0_97_EQ_0_9_ETC___d1015,
|
|
IF_tlbMG_m_entryVec_5_022_BITS_1_TO_0_023_EQ_0_ETC___d1042,
|
|
IF_tlbMG_m_entryVec_6_048_BITS_1_TO_0_049_EQ_0_ETC___d1057,
|
|
IF_tlbMG_m_entryVec_7_062_BITS_1_TO_0_063_EQ_0_ETC___d1071,
|
|
IF_tlbMG_m_updRepIdx_lat_0_whas__77_THEN_NOT_t_ETC___d287,
|
|
IF_tlbMG_m_updRepIdx_lat_1_whas__74_THEN_tlbMG_ETC___d283,
|
|
IF_tlbReqQ_full_lat_0_whas__20_THEN_NOT_tlbReq_ETC___d854,
|
|
IF_transCacheReqQ_data_0_337_AND_pendWait_0_rl_ETC___d1372,
|
|
IF_transCache_RDY_resp__334_AND_transCache_res_ETC___d1346,
|
|
NOT_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel__ETC___d1490,
|
|
NOT_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel__ETC___d1725,
|
|
NOT_tlb4KB_m_pendIndex_wget__17_BIT_8_18_19_OR_ETC___d1486,
|
|
NOT_tlb4KB_m_pendIndex_wget__17_BIT_8_18_19_OR_ETC___d860,
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d1104,
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d189,
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d201,
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258,
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AND_N_ETC___d1096,
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AND_t_ETC___d1099,
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_rl_7_54_AND_ETC___d1131,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d1086,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d944,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d968,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d984,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1018,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1060,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1311,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1332,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967,
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_tlbMG_m_va_ETC___d1594,
|
|
NOT_tlbMG_m_validVec_1_20_21_OR_NOT_tlbMG_m_en_ETC___d1723,
|
|
NOT_tlbMG_m_validVec_3_69_70_OR_NOT_tlbMG_m_en_ETC___d1721,
|
|
NOT_tlbMG_m_validVec_5_020_021_OR_NOT_tlbMG_m__ETC___d1719,
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1534,
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1560,
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1571,
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728,
|
|
_dfoo21,
|
|
_dfoo23,
|
|
_dfoo33,
|
|
_dfoo35,
|
|
_dfoo45,
|
|
_dfoo47,
|
|
_dfoo49,
|
|
_dfoo5,
|
|
_dfoo51,
|
|
_dfoo7,
|
|
_theResult_____2__h38323,
|
|
_theResult_____2__h41934,
|
|
idx__h64702,
|
|
next_deqP___1__h38512,
|
|
next_deqP___1__h42123,
|
|
pendWait_0_rl_21_BITS_2_TO_1_22_EQ_0_23_OR_pen_ETC___d1517,
|
|
pendWait_1_rl_49_BIT_0_61_EQ_SEL_ARR_respLdQ_d_ETC___d1505,
|
|
pendWalkAddr_0_349_EQ_0_CONCAT_IF_transCache_r_ETC___d1366,
|
|
pendWalkAddr_1_377_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1453,
|
|
tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d1316,
|
|
tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d222,
|
|
tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d238,
|
|
tlb4KB_m_state_46_AND_IF_tlb4KB_m_pendReq_lat__ETC___d816,
|
|
tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089,
|
|
tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d1092,
|
|
tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d182,
|
|
tlb4KB_m_tlbRam_1_bram_b_read__78_BIT_6_84_EQ__ETC___d185,
|
|
tlb4KB_m_tlbRam_2_bram_b_read__90_BITS_79_TO_5_ETC___d1101,
|
|
tlb4KB_m_tlbRam_2_bram_b_read__90_BITS_79_TO_5_ETC___d194,
|
|
tlb4KB_m_tlbRam_2_bram_b_read__90_BIT_6_96_EQ__ETC___d197,
|
|
tlb4KB_m_tlbRam_3_bram_b_read__02_BITS_79_TO_5_ETC___d1105,
|
|
tlb4KB_m_tlbRam_3_bram_b_read__02_BITS_79_TO_5_ETC___d205,
|
|
tlb4KB_m_tlbRam_3_bram_b_read__02_BIT_6_06_EQ__ETC___d207,
|
|
transCacheReqQ_empty_rl_32_OR_NOT_transCacheRe_ETC___d1383,
|
|
transCache_resp__342_BITS_45_TO_44_343_ULT_2___d1344,
|
|
v__h37913,
|
|
v__h38064,
|
|
v__h41524,
|
|
v__h41675,
|
|
v__h47401;
|
|
|
|
// action method updateVMInfo
|
|
assign RDY_updateVMInfo = 1'd1 ;
|
|
assign CAN_FIRE_updateVMInfo = 1'd1 ;
|
|
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
|
|
|
|
// action method toChildren_rqFromC_put
|
|
assign RDY_toChildren_rqFromC_put = !rqFromCQ_full_rl ;
|
|
assign CAN_FIRE_toChildren_rqFromC_put = !rqFromCQ_full_rl ;
|
|
assign WILL_FIRE_toChildren_rqFromC_put = EN_toChildren_rqFromC_put ;
|
|
|
|
// value method toChildren_rsToC_notEmpty
|
|
assign toChildren_rsToC_notEmpty = RDY_toChildren_rsToC_first ;
|
|
assign RDY_toChildren_rsToC_notEmpty = 1'd1 ;
|
|
|
|
// action method toChildren_rsToC_deq
|
|
assign RDY_toChildren_rsToC_deq = RDY_toChildren_rsToC_first ;
|
|
assign CAN_FIRE_toChildren_rsToC_deq = RDY_toChildren_rsToC_first ;
|
|
assign WILL_FIRE_toChildren_rsToC_deq = EN_toChildren_rsToC_deq ;
|
|
|
|
// value method toChildren_rsToC_first
|
|
assign toChildren_rsToC_first =
|
|
{ rsToCQ_data_0_lat_0$whas ?
|
|
rsToCQ_data_0_lat_0$wget[83] :
|
|
rsToCQ_data_0_rl[83],
|
|
rsToCQ_data_0_lat_0$whas ?
|
|
rsToCQ_data_0_lat_0$wget[82:81] :
|
|
rsToCQ_data_0_rl[82:81],
|
|
rsToCQ_data_0_lat_0$whas ?
|
|
rsToCQ_data_0_lat_0$wget[80] :
|
|
rsToCQ_data_0_rl[80],
|
|
rsToCQ_data_0_lat_0$whas ?
|
|
rsToCQ_data_0_lat_0$wget[79:0] :
|
|
rsToCQ_data_0_rl[79:0] } ;
|
|
assign RDY_toChildren_rsToC_first =
|
|
rsToCQ_data_0_lat_0$whas ? !1'd0 : !rsToCQ_empty_rl ;
|
|
|
|
// action method toChildren_iTlbReqFlush_put
|
|
assign RDY_toChildren_iTlbReqFlush_put = !iFlushReq ;
|
|
assign CAN_FIRE_toChildren_iTlbReqFlush_put = !iFlushReq ;
|
|
assign WILL_FIRE_toChildren_iTlbReqFlush_put =
|
|
EN_toChildren_iTlbReqFlush_put ;
|
|
|
|
// action method toChildren_dTlbReqFlush_put
|
|
assign RDY_toChildren_dTlbReqFlush_put = !dFlushReq ;
|
|
assign CAN_FIRE_toChildren_dTlbReqFlush_put = !dFlushReq ;
|
|
assign WILL_FIRE_toChildren_dTlbReqFlush_put =
|
|
EN_toChildren_dTlbReqFlush_put ;
|
|
|
|
// action method toChildren_flushDone_get
|
|
assign RDY_toChildren_flushDone_get = !flushDoneQ_empty ;
|
|
assign CAN_FIRE_toChildren_flushDone_get = !flushDoneQ_empty ;
|
|
assign WILL_FIRE_toChildren_flushDone_get = EN_toChildren_flushDone_get ;
|
|
|
|
// value method toMem_memReq_notEmpty
|
|
assign toMem_memReq_notEmpty = !memReqQ_empty ;
|
|
assign RDY_toMem_memReq_notEmpty = 1'd1 ;
|
|
|
|
// action method toMem_memReq_deq
|
|
assign RDY_toMem_memReq_deq = !memReqQ_empty ;
|
|
assign CAN_FIRE_toMem_memReq_deq = !memReqQ_empty ;
|
|
assign WILL_FIRE_toMem_memReq_deq = EN_toMem_memReq_deq ;
|
|
|
|
// value method toMem_memReq_first
|
|
assign toMem_memReq_first =
|
|
{ CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1,
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 } ;
|
|
assign RDY_toMem_memReq_first = !memReqQ_empty ;
|
|
|
|
// value method toMem_respLd_notFull
|
|
assign toMem_respLd_notFull = !respLdQ_full ;
|
|
assign RDY_toMem_respLd_notFull = 1'd1 ;
|
|
|
|
// action method toMem_respLd_enq
|
|
assign RDY_toMem_respLd_enq = !respLdQ_full ;
|
|
assign CAN_FIRE_toMem_respLd_enq = !respLdQ_full ;
|
|
assign WILL_FIRE_toMem_respLd_enq = EN_toMem_respLd_enq ;
|
|
|
|
// action method perf_setStatus
|
|
assign RDY_perf_setStatus = 1'd1 ;
|
|
assign CAN_FIRE_perf_setStatus = 1'd1 ;
|
|
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
|
|
|
|
// action method perf_req
|
|
assign RDY_perf_req = !perfReqQ_full ;
|
|
assign CAN_FIRE_perf_req = !perfReqQ_full ;
|
|
assign WILL_FIRE_perf_req = EN_perf_req ;
|
|
|
|
// actionvalue method perf_resp
|
|
assign perf_resp = { perfReqQ_data_0, 64'd0 } ;
|
|
assign RDY_perf_resp = !perfReqQ_empty ;
|
|
assign CAN_FIRE_perf_resp = !perfReqQ_empty ;
|
|
assign WILL_FIRE_perf_resp = EN_perf_resp ;
|
|
|
|
// value method perf_respValid
|
|
assign perf_respValid = !perfReqQ_empty ;
|
|
assign RDY_perf_respValid = 1'd1 ;
|
|
|
|
// submodule tlb4KB_m_repRam_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd8),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_repRam_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_repRam_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_repRam_bram$ADDRB),
|
|
.DIA(tlb4KB_m_repRam_bram$DIA),
|
|
.DIB(tlb4KB_m_repRam_bram$DIB),
|
|
.WEA(tlb4KB_m_repRam_bram$WEA),
|
|
.WEB(tlb4KB_m_repRam_bram$WEB),
|
|
.ENA(tlb4KB_m_repRam_bram$ENA),
|
|
.ENB(tlb4KB_m_repRam_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_repRam_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd81),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_0_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_tlbRam_0_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_tlbRam_0_bram$ADDRB),
|
|
.DIA(tlb4KB_m_tlbRam_0_bram$DIA),
|
|
.DIB(tlb4KB_m_tlbRam_0_bram$DIB),
|
|
.WEA(tlb4KB_m_tlbRam_0_bram$WEA),
|
|
.WEB(tlb4KB_m_tlbRam_0_bram$WEB),
|
|
.ENA(tlb4KB_m_tlbRam_0_bram$ENA),
|
|
.ENB(tlb4KB_m_tlbRam_0_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_tlbRam_0_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd81),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_1_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_tlbRam_1_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_tlbRam_1_bram$ADDRB),
|
|
.DIA(tlb4KB_m_tlbRam_1_bram$DIA),
|
|
.DIB(tlb4KB_m_tlbRam_1_bram$DIB),
|
|
.WEA(tlb4KB_m_tlbRam_1_bram$WEA),
|
|
.WEB(tlb4KB_m_tlbRam_1_bram$WEB),
|
|
.ENA(tlb4KB_m_tlbRam_1_bram$ENA),
|
|
.ENB(tlb4KB_m_tlbRam_1_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_tlbRam_1_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd81),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_2_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_tlbRam_2_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_tlbRam_2_bram$ADDRB),
|
|
.DIA(tlb4KB_m_tlbRam_2_bram$DIA),
|
|
.DIB(tlb4KB_m_tlbRam_2_bram$DIB),
|
|
.WEA(tlb4KB_m_tlbRam_2_bram$WEA),
|
|
.WEB(tlb4KB_m_tlbRam_2_bram$WEB),
|
|
.ENA(tlb4KB_m_tlbRam_2_bram$ENA),
|
|
.ENB(tlb4KB_m_tlbRam_2_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_tlbRam_2_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd81),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_3_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_tlbRam_3_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_tlbRam_3_bram$ADDRB),
|
|
.DIA(tlb4KB_m_tlbRam_3_bram$DIA),
|
|
.DIB(tlb4KB_m_tlbRam_3_bram$DIB),
|
|
.WEA(tlb4KB_m_tlbRam_3_bram$WEA),
|
|
.WEB(tlb4KB_m_tlbRam_3_bram$WEB),
|
|
.ENA(tlb4KB_m_tlbRam_3_bram$ENA),
|
|
.ENB(tlb4KB_m_tlbRam_3_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_tlbRam_3_bram$DOB));
|
|
|
|
// submodule transCache
|
|
mkSplitTransCache transCache(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.addEntry_level(transCache$addEntry_level),
|
|
.addEntry_ppn(transCache$addEntry_ppn),
|
|
.addEntry_vpn(transCache$addEntry_vpn),
|
|
.req_vpn(transCache$req_vpn),
|
|
.EN_req(transCache$EN_req),
|
|
.EN_deqResp(transCache$EN_deqResp),
|
|
.EN_addEntry(transCache$EN_addEntry),
|
|
.EN_flush(transCache$EN_flush),
|
|
.RDY_req(transCache$RDY_req),
|
|
.resp(transCache$resp),
|
|
.RDY_resp(transCache$RDY_resp),
|
|
.RDY_deqResp(transCache$RDY_deqResp),
|
|
.RDY_addEntry(transCache$RDY_addEntry),
|
|
.RDY_flush(),
|
|
.flush_done(transCache$flush_done),
|
|
.RDY_flush_done());
|
|
|
|
// rule RL_doStartFlush
|
|
assign CAN_FIRE_RL_doStartFlush =
|
|
tlb4KB_m_state && !tlb4KB_m_pendReq_rl[81] && iFlushReq &&
|
|
dFlushReq &&
|
|
!waitFlushDone ;
|
|
assign WILL_FIRE_RL_doStartFlush = CAN_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doWaitFlush
|
|
assign CAN_FIRE_RL_doWaitFlush =
|
|
!flushDoneQ_full && iFlushReq && dFlushReq && waitFlushDone &&
|
|
tlb4KB_m_state &&
|
|
transCache$flush_done ;
|
|
assign WILL_FIRE_RL_doWaitFlush = CAN_FIRE_RL_doWaitFlush ;
|
|
|
|
// rule RL_doTranslationCacheResp
|
|
assign CAN_FIRE_RL_doTranslationCacheResp =
|
|
transCache$RDY_resp && transCache$RDY_deqResp &&
|
|
!transCacheReqQ_empty_rl &&
|
|
transCacheReqQ_empty_rl_32_OR_NOT_transCacheRe_ETC___d1383 ;
|
|
assign WILL_FIRE_RL_doTranslationCacheResp =
|
|
CAN_FIRE_RL_doTranslationCacheResp ;
|
|
|
|
// rule RL_tlb4KB_m_setPendIndex
|
|
assign CAN_FIRE_RL_tlb4KB_m_setPendIndex = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_setPendIndex = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_doAddEntry
|
|
assign CAN_FIRE_RL_tlb4KB_m_doAddEntry =
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_empty_rl &&
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_empty_rl &&
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_empty_rl &&
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_empty_rl &&
|
|
!tlb4KB_m_repRam_rdReqQ_empty_rl &&
|
|
tlb4KB_m_state &&
|
|
tlb4KB_m_pendReq_rl[81] &&
|
|
tlb4KB_m_pendReq_rl[80] ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_doAddEntry = CAN_FIRE_RL_tlb4KB_m_doAddEntry ;
|
|
|
|
// rule RL_tlbMG_m_doUpdateRep
|
|
assign CAN_FIRE_RL_tlbMG_m_doUpdateRep =
|
|
!CAN_FIRE_RL_doStartFlush && tlbMG_m_updRepIdx_rl[3] ;
|
|
assign WILL_FIRE_RL_tlbMG_m_doUpdateRep =
|
|
CAN_FIRE_RL_tlbMG_m_doUpdateRep && !WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doTlbResp
|
|
assign CAN_FIRE_RL_doTlbResp =
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_empty_rl &&
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_empty_rl &&
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_rl_7_54_AND_ETC___d1131 ;
|
|
assign WILL_FIRE_RL_doTlbResp = CAN_FIRE_RL_doTlbResp ;
|
|
|
|
// rule RL_doPageWalk
|
|
assign CAN_FIRE_RL_doPageWalk =
|
|
!respLdQ_empty &&
|
|
IF_IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NO_ETC___d1494 &&
|
|
tlbReqQ_empty_rl &&
|
|
transCacheReqQ_empty_rl ;
|
|
assign WILL_FIRE_RL_doPageWalk =
|
|
CAN_FIRE_RL_doPageWalk && !WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_tlb4KB_m_doFlush
|
|
assign CAN_FIRE_RL_tlb4KB_m_doFlush = !tlb4KB_m_state ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_doFlush = CAN_FIRE_RL_tlb4KB_m_doFlush ;
|
|
|
|
// rule RL_doTlbReq
|
|
assign CAN_FIRE_RL_doTlbReq =
|
|
tlb4KB_m_state_46_AND_IF_tlb4KB_m_pendReq_lat__ETC___d816 &&
|
|
NOT_tlb4KB_m_pendIndex_wget__17_BIT_8_18_19_OR_ETC___d860 &&
|
|
(!iFlushReq || !dFlushReq) &&
|
|
respLdQ_empty ;
|
|
assign WILL_FIRE_RL_doTlbReq = CAN_FIRE_RL_doTlbReq ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_repRam_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_repRam_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_pendReq_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_pendReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_pendReq_canon = 1'd1 ;
|
|
|
|
// rule RL_tlbMG_m_incRandIdx
|
|
assign CAN_FIRE_RL_tlbMG_m_incRandIdx = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbMG_m_incRandIdx = 1'd1 ;
|
|
|
|
// rule RL_tlbMG_m_lruBit_canon
|
|
assign CAN_FIRE_RL_tlbMG_m_lruBit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbMG_m_lruBit_canon = 1'd1 ;
|
|
|
|
// rule RL_tlbMG_m_updRepIdx_canon
|
|
assign CAN_FIRE_RL_tlbMG_m_updRepIdx_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbMG_m_updRepIdx_canon = 1'd1 ;
|
|
|
|
// rule RL_tlbReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlbReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlbReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlbReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_transCacheReqQ_empty_canon
|
|
assign CAN_FIRE_RL_transCacheReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_transCacheReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_transCacheReqQ_full_canon
|
|
assign CAN_FIRE_RL_transCacheReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_transCacheReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_flushDoneQ_canonicalize
|
|
assign CAN_FIRE_RL_flushDoneQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushDoneQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_flushDoneQ_enqReq_canon
|
|
assign CAN_FIRE_RL_flushDoneQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushDoneQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushDoneQ_deqReq_canon
|
|
assign CAN_FIRE_RL_flushDoneQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushDoneQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushDoneQ_clearReq_canon
|
|
assign CAN_FIRE_RL_flushDoneQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushDoneQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqFromCQ_data_0_canon
|
|
assign CAN_FIRE_RL_rqFromCQ_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqFromCQ_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_rqFromCQ_empty_canon
|
|
assign CAN_FIRE_RL_rqFromCQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqFromCQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_rqFromCQ_full_canon
|
|
assign CAN_FIRE_RL_rqFromCQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqFromCQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_rsToCQ_data_0_canon
|
|
assign CAN_FIRE_RL_rsToCQ_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsToCQ_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_rsToCQ_empty_canon
|
|
assign CAN_FIRE_RL_rsToCQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsToCQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_rsToCQ_full_canon
|
|
assign CAN_FIRE_RL_rsToCQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsToCQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_pendValid_0_canon
|
|
assign CAN_FIRE_RL_pendValid_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendValid_0_canon = 1'd1 ;
|
|
|
|
// rule RL_pendValid_1_canon
|
|
assign CAN_FIRE_RL_pendValid_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendValid_1_canon = 1'd1 ;
|
|
|
|
// rule RL_pendWait_0_canon
|
|
assign CAN_FIRE_RL_pendWait_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendWait_0_canon = 1'd1 ;
|
|
|
|
// rule RL_pendWait_1_canon
|
|
assign CAN_FIRE_RL_pendWait_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendWait_1_canon = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_canonicalize
|
|
assign CAN_FIRE_RL_memReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respLdQ_canonicalize
|
|
assign CAN_FIRE_RL_respLdQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_respLdQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_respLdQ_enqReq_canon
|
|
assign CAN_FIRE_RL_respLdQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respLdQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respLdQ_deqReq_canon
|
|
assign CAN_FIRE_RL_respLdQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respLdQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respLdQ_clearReq_canon
|
|
assign CAN_FIRE_RL_respLdQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respLdQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_memReqQ_enqReq_lat_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
!IF_NOT_transCacheReqQ_data_0_337_338_OR_NOT_pe_ETC___d1380 ;
|
|
assign MUX_pendWait_0_lat_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ;
|
|
assign MUX_pendWait_1_lat_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ;
|
|
assign MUX_rsToCQ_data_0_lat_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
(IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d891 ||
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 ||
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1111) ;
|
|
assign MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1586 ;
|
|
assign MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 &&
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1311 ;
|
|
assign MUX_tlb4KB_m_state$write_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush && tlb4KB_m_flushIdx == 8'd255 ;
|
|
assign MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd0 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 ;
|
|
assign MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd1 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 ;
|
|
assign MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd2 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 ;
|
|
assign MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd3 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 ;
|
|
assign MUX_tlbMG_m_updRepIdx_lat_1$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 ;
|
|
assign MUX_tlbMG_m_validVec_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign MUX_tlbMG_m_validVec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign MUX_tlbMG_m_validVec_2$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd2 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign MUX_tlbMG_m_validVec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd3 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign MUX_tlbMG_m_validVec_4$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd4 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign MUX_tlbMG_m_validVec_5$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd5 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign MUX_tlbMG_m_validVec_6$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd6 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign MUX_tlbMG_m_validVec_7$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd7 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1, pteAddr__h63104, transCacheReqQ_data_0 } ;
|
|
assign MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1, newPTEAddr__h65403, idx__h64702 } ;
|
|
assign MUX_pendWait_0_lat_0$wset_1__VAL_1 =
|
|
(transCacheReqQ_data_0 == 1'd0 &&
|
|
IF_NOT_transCacheReqQ_data_0_337_338_OR_NOT_pe_ETC___d1380) ?
|
|
{ 2'd2,
|
|
!transCacheReqQ_data_0 || pendWait_0_rl[2:1] != 2'd1 ||
|
|
!pendWalkAddr_0_349_EQ_0_CONCAT_IF_transCache_r_ETC___d1366 } :
|
|
{ 2'd1, 1'bx /* unspecified value */ } ;
|
|
assign MUX_pendWait_0_lat_0$wset_1__VAL_2 =
|
|
(idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408) ?
|
|
{ 2'd0, 1'bx /* unspecified value */ } :
|
|
((idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1555) ?
|
|
{ 2'd0, 1'bx /* unspecified value */ } :
|
|
_dfoo36) ;
|
|
assign MUX_pendWait_1_lat_0$wset_1__VAL_1 =
|
|
(transCacheReqQ_data_0 == 1'd1 &&
|
|
IF_NOT_transCacheReqQ_data_0_337_338_OR_NOT_pe_ETC___d1380) ?
|
|
{ 2'd2,
|
|
!transCacheReqQ_data_0 || pendWait_0_rl[2:1] != 2'd1 ||
|
|
!pendWalkAddr_0_349_EQ_0_CONCAT_IF_transCache_r_ETC___d1366 } :
|
|
{ 2'd1, 1'bx /* unspecified value */ } ;
|
|
assign MUX_pendWait_1_lat_0$wset_1__VAL_2 =
|
|
(idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408) ?
|
|
{ 2'd0, 1'bx /* unspecified value */ } :
|
|
((idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1555) ?
|
|
{ 2'd0, 1'bx /* unspecified value */ } :
|
|
_dfoo34) ;
|
|
assign MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1 =
|
|
{ !SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d884,
|
|
CASE_tlbReqQ_data_0_0_pendReq_0_BITS_28_TO_27__ETC__q17,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142,
|
|
IF_IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_t_ETC___d1296 } ;
|
|
assign MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2 =
|
|
{ !SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d1407,
|
|
CASE_idx4702_0_pendReq_0_BITS_28_TO_27_1_pendR_ETC__q18,
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1534,
|
|
masked_vpn__h65873,
|
|
masked_ppn__h65874,
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[7:1],
|
|
walkLevel__h65400 } ;
|
|
assign MUX_tlb4KB_m_flushIdx$write_1__VAL_1 = tlb4KB_m_flushIdx + 8'd1 ;
|
|
assign MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1 =
|
|
{ 2'd3,
|
|
masked_vpn__h65873,
|
|
masked_ppn__h65874,
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[7:1],
|
|
walkLevel__h65400 } ;
|
|
assign MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2 =
|
|
{ 2'd2,
|
|
53'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418 } ;
|
|
assign MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1 =
|
|
{ IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d1324,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d1325,
|
|
tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d1316 ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[1:0],
|
|
way__h61664 } ;
|
|
assign MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3 =
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d216 ?
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d237 :
|
|
{ (!tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d238 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] !=
|
|
tlb4KB_m_repRam_bram$DOB[7:6] &&
|
|
tlb4KB_m_repRam_bram$DOB[5:4] !=
|
|
tlb4KB_m_repRam_bram$DOB[7:6]) ?
|
|
tlb4KB_m_repRam_bram$DOB[5:4] :
|
|
tlb4KB_m_repRam_bram$DOB[7:6],
|
|
(!tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d238 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] !=
|
|
tlb4KB_m_repRam_bram$DOB[7:6]) ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[5:4],
|
|
tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d238 ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[1:0],
|
|
tlb4KB_m_repRam_bram$DOB[7:6] } ;
|
|
assign MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 =
|
|
{ 1'd1, tlb4KB_m_pendReq_rl[79:0] } ;
|
|
assign MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_2 =
|
|
{ 1'd0,
|
|
80'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1 =
|
|
(val__h20096 == 8'd255) ? x__h20154 : val__h20096 ;
|
|
assign MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, idx__h55354 } ;
|
|
assign MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, v__h69837 } ;
|
|
|
|
// inlined wires
|
|
assign tlb4KB_m_pendReq_lat_0$wget =
|
|
{ 1'd0,
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign tlb4KB_m_pendReq_lat_1$wget =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1 :
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2 ;
|
|
assign tlbMG_m_lruBit_lat_0$whas =
|
|
WILL_FIRE_RL_tlbMG_m_doUpdateRep || WILL_FIRE_RL_doStartFlush ;
|
|
assign tlbMG_m_updRepIdx_lat_0$wget =
|
|
{ 1'd0, 3'bxxx /* unspecified value */ } ;
|
|
assign tlbMG_m_updRepIdx_lat_1$wget =
|
|
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__SEL_1 ?
|
|
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1 :
|
|
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2 ;
|
|
assign tlbMG_m_updRepIdx_lat_1$whas =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 ||
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ;
|
|
assign rsToCQ_data_0_lat_0$wget =
|
|
MUX_rsToCQ_data_0_lat_0$wset_1__SEL_1 ?
|
|
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1 :
|
|
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2 ;
|
|
assign rsToCQ_data_0_lat_0$whas =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
(IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d891 ||
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 ||
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1111) ||
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1525 ;
|
|
assign pendValid_0_lat_0$whas =
|
|
WILL_FIRE_RL_doTlbResp && _dfoo7 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo51 ;
|
|
assign pendValid_0_lat_1$whas = WILL_FIRE_RL_doTlbReq && v__h47401 == 1'd0 ;
|
|
assign pendValid_1_lat_0$whas =
|
|
WILL_FIRE_RL_doTlbResp && _dfoo5 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo49 ;
|
|
assign pendValid_1_lat_1$whas = WILL_FIRE_RL_doTlbReq && v__h47401 == 1'd1 ;
|
|
assign pendWait_0_lat_0$wget =
|
|
MUX_pendWait_0_lat_0$wset_1__SEL_1 ?
|
|
MUX_pendWait_0_lat_0$wset_1__VAL_1 :
|
|
MUX_pendWait_0_lat_0$wset_1__VAL_2 ;
|
|
assign pendWait_0_lat_0$whas =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo47 ;
|
|
assign pendWait_1_lat_0$wget =
|
|
MUX_pendWait_1_lat_0$wset_1__SEL_1 ?
|
|
MUX_pendWait_1_lat_0$wset_1__VAL_1 :
|
|
MUX_pendWait_1_lat_0$wset_1__VAL_2 ;
|
|
assign pendWait_1_lat_0$whas =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo45 ;
|
|
assign memReqQ_enqReq_lat_0$wget =
|
|
MUX_memReqQ_enqReq_lat_0$wset_1__SEL_1 ?
|
|
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign memReqQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
!IF_NOT_transCacheReqQ_data_0_337_338_OR_NOT_pe_ETC___d1380 ||
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1571 ;
|
|
assign memReqQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
65'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign respLdQ_enqReq_lat_0$wget = { 1'd1, toMem_respLd_enq_x } ;
|
|
assign respLdQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
pendWait_0_rl_21_BITS_2_TO_1_22_EQ_0_23_OR_pen_ETC___d1517 ;
|
|
assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
assign perfReqQ_enqReq_lat_2$wget =
|
|
{ 1'd0, 4'bxxxx /* unspecified value */ } ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1586 ||
|
|
WILL_FIRE_RL_doTlbReq ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas =
|
|
WILL_FIRE_RL_doTlbResp || WILL_FIRE_RL_tlb4KB_m_doAddEntry ;
|
|
assign transCacheReqQ_enqP_lat_0$whas =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 &&
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1332 ;
|
|
assign tlb4KB_m_pendIndex$wget =
|
|
{ tlb4KB_m_pendReq_rl[81],
|
|
tlb4KB_m_pendReq_rl[80] ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_pendReq_rl[7:0] } ;
|
|
|
|
// register dFlushReq
|
|
assign dFlushReq$D_IN = !WILL_FIRE_RL_doWaitFlush ;
|
|
assign dFlushReq$EN =
|
|
WILL_FIRE_RL_doWaitFlush || EN_toChildren_dTlbReqFlush_put ;
|
|
|
|
// register flushDoneQ_clearReq_rl
|
|
assign flushDoneQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign flushDoneQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushDoneQ_deqReq_rl
|
|
assign flushDoneQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign flushDoneQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushDoneQ_empty
|
|
assign flushDoneQ_empty$D_IN =
|
|
flushDoneQ_clearReq_rl ||
|
|
!CAN_FIRE_RL_doWaitFlush && !flushDoneQ_enqReq_rl &&
|
|
(EN_toChildren_flushDone_get || flushDoneQ_deqReq_rl ||
|
|
flushDoneQ_empty) ;
|
|
assign flushDoneQ_empty$EN = 1'd1 ;
|
|
|
|
// register flushDoneQ_enqReq_rl
|
|
assign flushDoneQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign flushDoneQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushDoneQ_full
|
|
assign flushDoneQ_full$D_IN =
|
|
!flushDoneQ_clearReq_rl &&
|
|
(CAN_FIRE_RL_doWaitFlush || flushDoneQ_enqReq_rl ||
|
|
!EN_toChildren_flushDone_get && !flushDoneQ_deqReq_rl &&
|
|
flushDoneQ_full) ;
|
|
assign flushDoneQ_full$EN = 1'd1 ;
|
|
|
|
// register iFlushReq
|
|
assign iFlushReq$D_IN = !WILL_FIRE_RL_doWaitFlush ;
|
|
assign iFlushReq$EN =
|
|
WILL_FIRE_RL_doWaitFlush || EN_toChildren_iTlbReqFlush_put ;
|
|
|
|
// register memReqQ_clearReq_rl
|
|
assign memReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign memReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_data_0
|
|
assign memReqQ_data_0$D_IN =
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[64:0] :
|
|
memReqQ_enqReq_rl[64:0] ;
|
|
assign memReqQ_data_0$EN =
|
|
memReqQ_enqP == 1'd0 && !memReqQ_clearReq_rl &&
|
|
IF_memReqQ_enqReq_lat_1_whas__70_THEN_memReqQ__ETC___d579 ;
|
|
|
|
// register memReqQ_data_1
|
|
assign memReqQ_data_1$D_IN =
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[64:0] :
|
|
memReqQ_enqReq_rl[64:0] ;
|
|
assign memReqQ_data_1$EN =
|
|
memReqQ_enqP == 1'd1 && !memReqQ_clearReq_rl &&
|
|
IF_memReqQ_enqReq_lat_1_whas__70_THEN_memReqQ__ETC___d579 ;
|
|
|
|
// register memReqQ_deqP
|
|
assign memReqQ_deqP$D_IN =
|
|
!memReqQ_clearReq_rl && _theResult_____2__h38323 ;
|
|
assign memReqQ_deqP$EN = 1'd1 ;
|
|
|
|
// register memReqQ_deqReq_rl
|
|
assign memReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign memReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_empty
|
|
assign memReqQ_empty$D_IN =
|
|
memReqQ_clearReq_rl ||
|
|
IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d643 ;
|
|
assign memReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register memReqQ_enqP
|
|
assign memReqQ_enqP$D_IN = !memReqQ_clearReq_rl && v__h37913 ;
|
|
assign memReqQ_enqP$EN = 1'd1 ;
|
|
|
|
// register memReqQ_enqReq_rl
|
|
assign memReqQ_enqReq_rl$D_IN = memReqQ_enqReq_lat_2$wget ;
|
|
assign memReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_full
|
|
assign memReqQ_full$D_IN =
|
|
!memReqQ_clearReq_rl &&
|
|
IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d638 ;
|
|
assign memReqQ_full$EN = 1'd1 ;
|
|
|
|
// register pendReq_0
|
|
assign pendReq_0$D_IN =
|
|
{ EN_toChildren_rqFromC_put ?
|
|
toChildren_rqFromC_put[29] :
|
|
rqFromCQ_data_0_rl[29],
|
|
EN_toChildren_rqFromC_put ?
|
|
toChildren_rqFromC_put[28:27] :
|
|
rqFromCQ_data_0_rl[28:27],
|
|
IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418 } ;
|
|
assign pendReq_0$EN = pendValid_0_lat_1$whas ;
|
|
|
|
// register pendReq_1
|
|
assign pendReq_1$D_IN = pendReq_0$D_IN ;
|
|
assign pendReq_1$EN = pendValid_1_lat_1$whas ;
|
|
|
|
// register pendValid_0_rl
|
|
assign pendValid_0_rl$D_IN = pendValid_0_lat_1$whas || v__h47401 ;
|
|
assign pendValid_0_rl$EN = 1'd1 ;
|
|
|
|
// register pendValid_1_rl
|
|
assign pendValid_1_rl$D_IN =
|
|
pendValid_1_lat_1$whas ||
|
|
(pendValid_1_lat_0$whas ? 1'd0 : pendValid_1_rl) ;
|
|
assign pendValid_1_rl$EN = 1'd1 ;
|
|
|
|
// register pendWait_0_rl
|
|
assign pendWait_0_rl$D_IN =
|
|
(pendWait_0_lat_0$whas ?
|
|
pendWait_0_lat_0$wget[2:1] == 2'd0 :
|
|
pendWait_0_rl[2:1] == 2'd0) ?
|
|
{ 2'd0, 1'bx /* unspecified value */ } :
|
|
((pendWait_0_lat_0$whas ?
|
|
pendWait_0_lat_0$wget[2:1] == 2'd1 :
|
|
pendWait_0_rl[2:1] == 2'd1) ?
|
|
{ 2'd1, 1'bx /* unspecified value */ } :
|
|
{ 2'd2,
|
|
pendWait_0_lat_0$whas ?
|
|
pendWait_0_lat_0$wget[0] :
|
|
pendWait_0_rl[0] }) ;
|
|
assign pendWait_0_rl$EN = 1'd1 ;
|
|
|
|
// register pendWait_1_rl
|
|
assign pendWait_1_rl$D_IN =
|
|
(pendWait_1_lat_0$whas ?
|
|
pendWait_1_lat_0$wget[2:1] == 2'd0 :
|
|
pendWait_1_rl[2:1] == 2'd0) ?
|
|
{ 2'd0, 1'bx /* unspecified value */ } :
|
|
((pendWait_1_lat_0$whas ?
|
|
pendWait_1_lat_0$wget[2:1] == 2'd1 :
|
|
pendWait_1_rl[2:1] == 2'd1) ?
|
|
{ 2'd1, 1'bx /* unspecified value */ } :
|
|
{ 2'd2,
|
|
pendWait_1_lat_0$whas ?
|
|
pendWait_1_lat_0$wget[0] :
|
|
pendWait_1_rl[0] }) ;
|
|
assign pendWait_1_rl$EN = 1'd1 ;
|
|
|
|
// register pendWalkAddr_0
|
|
assign pendWalkAddr_0$D_IN =
|
|
MUX_pendWait_0_lat_0$wset_1__SEL_1 ?
|
|
pteAddr__h63104 :
|
|
newPTEAddr__h65403 ;
|
|
assign pendWalkAddr_0$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ||
|
|
WILL_FIRE_RL_doPageWalk && idx__h64702 == 1'd0 ;
|
|
|
|
// register pendWalkAddr_1
|
|
assign pendWalkAddr_1$D_IN =
|
|
MUX_pendWait_1_lat_0$wset_1__SEL_1 ?
|
|
pteAddr__h63104 :
|
|
newPTEAddr__h65403 ;
|
|
assign pendWalkAddr_1$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ||
|
|
WILL_FIRE_RL_doPageWalk && idx__h64702 == 1'd1 ;
|
|
|
|
// register pendWalkLevel_0
|
|
assign pendWalkLevel_0$D_IN =
|
|
MUX_pendWait_0_lat_0$wset_1__SEL_1 ?
|
|
transCache$resp[45:44] :
|
|
newWalkLevel__h65401 ;
|
|
assign pendWalkLevel_0$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ||
|
|
WILL_FIRE_RL_doPageWalk && idx__h64702 == 1'd0 ;
|
|
|
|
// register pendWalkLevel_1
|
|
assign pendWalkLevel_1$D_IN =
|
|
MUX_pendWait_1_lat_0$wset_1__SEL_1 ?
|
|
transCache$resp[45:44] :
|
|
newWalkLevel__h65401 ;
|
|
assign pendWalkLevel_1$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ||
|
|
WILL_FIRE_RL_doPageWalk && idx__h64702 == 1'd1 ;
|
|
|
|
// register perfReqQ_clearReq_rl
|
|
assign perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_data_0
|
|
assign perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[3:0] :
|
|
perfReqQ_enqReq_rl[3:0] ;
|
|
assign perfReqQ_data_0$EN =
|
|
!perfReqQ_clearReq_rl &&
|
|
IF_perfReqQ_enqReq_lat_1_whas__39_THEN_perfReq_ETC___d748 ;
|
|
|
|
// register perfReqQ_deqReq_rl
|
|
assign perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_empty
|
|
assign perfReqQ_empty$D_IN =
|
|
perfReqQ_clearReq_rl ||
|
|
(EN_perf_req ?
|
|
!perfReqQ_enqReq_lat_0$wget[4] :
|
|
!perfReqQ_enqReq_rl[4]) &&
|
|
(EN_perf_resp || perfReqQ_deqReq_rl || perfReqQ_empty) ;
|
|
assign perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_enqReq_rl
|
|
assign perfReqQ_enqReq_rl$D_IN = perfReqQ_enqReq_lat_2$wget ;
|
|
assign perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_full
|
|
assign perfReqQ_full$D_IN =
|
|
!perfReqQ_clearReq_rl &&
|
|
(IF_perfReqQ_enqReq_lat_1_whas__39_THEN_perfReq_ETC___d748 ||
|
|
!EN_perf_resp && !perfReqQ_deqReq_rl && perfReqQ_full) ;
|
|
assign perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register respForOtherReq
|
|
assign respForOtherReq$D_IN =
|
|
{ IF_pendWait_0_rl_21_BITS_2_TO_1_22_EQ_0_23_OR__ETC___d1508,
|
|
pendWait_0_rl[2:1] == 2'd0 || pendWait_0_rl[2:1] == 2'd1 ||
|
|
pendWait_0_rl[0] != def__h64929 ||
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430 } ;
|
|
assign respForOtherReq$EN = WILL_FIRE_RL_doPageWalk ;
|
|
|
|
// register respLdQ_clearReq_rl
|
|
assign respLdQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign respLdQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register respLdQ_data_0
|
|
assign respLdQ_data_0$D_IN =
|
|
EN_toMem_respLd_enq ?
|
|
respLdQ_enqReq_lat_0$wget[64:0] :
|
|
respLdQ_enqReq_rl[64:0] ;
|
|
assign respLdQ_data_0$EN =
|
|
respLdQ_enqP == 1'd0 && !respLdQ_clearReq_rl &&
|
|
IF_respLdQ_enqReq_lat_1_whas__55_THEN_respLdQ__ETC___d664 ;
|
|
|
|
// register respLdQ_data_1
|
|
assign respLdQ_data_1$D_IN =
|
|
EN_toMem_respLd_enq ?
|
|
respLdQ_enqReq_lat_0$wget[64:0] :
|
|
respLdQ_enqReq_rl[64:0] ;
|
|
assign respLdQ_data_1$EN =
|
|
respLdQ_enqP == 1'd1 && !respLdQ_clearReq_rl &&
|
|
IF_respLdQ_enqReq_lat_1_whas__55_THEN_respLdQ__ETC___d664 ;
|
|
|
|
// register respLdQ_deqP
|
|
assign respLdQ_deqP$D_IN =
|
|
!respLdQ_clearReq_rl && _theResult_____2__h41934 ;
|
|
assign respLdQ_deqP$EN = 1'd1 ;
|
|
|
|
// register respLdQ_deqReq_rl
|
|
assign respLdQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign respLdQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register respLdQ_empty
|
|
assign respLdQ_empty$D_IN =
|
|
respLdQ_clearReq_rl ||
|
|
IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d728 ;
|
|
assign respLdQ_empty$EN = 1'd1 ;
|
|
|
|
// register respLdQ_enqP
|
|
assign respLdQ_enqP$D_IN = !respLdQ_clearReq_rl && v__h41524 ;
|
|
assign respLdQ_enqP$EN = 1'd1 ;
|
|
|
|
// register respLdQ_enqReq_rl
|
|
assign respLdQ_enqReq_rl$D_IN = memReqQ_enqReq_lat_2$wget ;
|
|
assign respLdQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register respLdQ_full
|
|
assign respLdQ_full$D_IN =
|
|
!respLdQ_clearReq_rl &&
|
|
IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d723 ;
|
|
assign respLdQ_full$EN = 1'd1 ;
|
|
|
|
// register rqFromCQ_data_0_rl
|
|
assign rqFromCQ_data_0_rl$D_IN = pendReq_0$D_IN ;
|
|
assign rqFromCQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register rqFromCQ_empty_rl
|
|
assign rqFromCQ_empty_rl$D_IN =
|
|
CAN_FIRE_RL_doTlbReq ||
|
|
!EN_toChildren_rqFromC_put && rqFromCQ_empty_rl ;
|
|
assign rqFromCQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register rqFromCQ_full_rl
|
|
assign rqFromCQ_full_rl$D_IN =
|
|
!CAN_FIRE_RL_doTlbReq &&
|
|
(EN_toChildren_rqFromC_put || rqFromCQ_full_rl) ;
|
|
assign rqFromCQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register rsToCQ_data_0_rl
|
|
assign rsToCQ_data_0_rl$D_IN = toChildren_rsToC_first ;
|
|
assign rsToCQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register rsToCQ_empty_rl
|
|
assign rsToCQ_empty_rl$D_IN =
|
|
EN_toChildren_rsToC_deq ||
|
|
(rsToCQ_data_0_lat_0$whas ? 1'd0 : rsToCQ_empty_rl) ;
|
|
assign rsToCQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register rsToCQ_full_rl
|
|
assign rsToCQ_full_rl$D_IN =
|
|
!EN_toChildren_rsToC_deq &&
|
|
(rsToCQ_data_0_lat_0$whas ? 1'd1 : rsToCQ_full_rl) ;
|
|
assign rsToCQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_flushIdx
|
|
assign tlb4KB_m_flushIdx$D_IN =
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ?
|
|
MUX_tlb4KB_m_flushIdx$write_1__VAL_1 :
|
|
8'd0 ;
|
|
assign tlb4KB_m_flushIdx$EN =
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush || WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb4KB_m_pendReq_rl
|
|
assign tlb4KB_m_pendReq_rl$D_IN =
|
|
{ IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138 } ;
|
|
assign tlb4KB_m_pendReq_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_repRam_rdReqQ_empty_rl
|
|
assign tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_repRam_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_repRam_rdReqQ_full_rl
|
|
assign tlb4KB_m_repRam_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas &&
|
|
tlb4KB_m_repRam_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_repRam_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_state
|
|
assign tlb4KB_m_state$D_IN = MUX_tlb4KB_m_state$write_1__SEL_1 ;
|
|
assign tlb4KB_m_state$EN =
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush && tlb4KB_m_flushIdx == 8'd255 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb4KB_m_tlbRam_0_rdReqQ_empty_rl
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_0_rdReqQ_full_rl
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas &&
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_1_rdReqQ_empty_rl
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_1_rdReqQ_full_rl
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas &&
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_2_rdReqQ_empty_rl
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_2_rdReqQ_full_rl
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas &&
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_3_rdReqQ_empty_rl
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_3_rdReqQ_full_rl
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas &&
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlbMG_m_entryVec_0
|
|
assign tlbMG_m_entryVec_0$D_IN =
|
|
{ masked_vpn__h65873,
|
|
masked_ppn__h65874,
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[7:1],
|
|
walkLevel__h65400 } ;
|
|
assign tlbMG_m_entryVec_0$EN = MUX_tlbMG_m_validVec_0$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_1
|
|
assign tlbMG_m_entryVec_1$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_1$EN = MUX_tlbMG_m_validVec_1$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_2
|
|
assign tlbMG_m_entryVec_2$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_2$EN = MUX_tlbMG_m_validVec_2$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_3
|
|
assign tlbMG_m_entryVec_3$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_3$EN = MUX_tlbMG_m_validVec_3$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_4
|
|
assign tlbMG_m_entryVec_4$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_4$EN = MUX_tlbMG_m_validVec_4$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_5
|
|
assign tlbMG_m_entryVec_5$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_5$EN = MUX_tlbMG_m_validVec_5$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_6
|
|
assign tlbMG_m_entryVec_6$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_6$EN = MUX_tlbMG_m_validVec_6$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_7
|
|
assign tlbMG_m_entryVec_7$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_7$EN = MUX_tlbMG_m_validVec_7$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_lruBit_rl
|
|
assign tlbMG_m_lruBit_rl$D_IN = n__read__h71326 ;
|
|
assign tlbMG_m_lruBit_rl$EN = 1'd1 ;
|
|
|
|
// register tlbMG_m_randIdx
|
|
assign tlbMG_m_randIdx$D_IN = tlbMG_m_randIdx + 3'd1 ;
|
|
assign tlbMG_m_randIdx$EN = 1'd1 ;
|
|
|
|
// register tlbMG_m_updRepIdx_rl
|
|
assign tlbMG_m_updRepIdx_rl$D_IN =
|
|
{ IF_tlbMG_m_updRepIdx_lat_1_whas__74_THEN_tlbMG_ETC___d283,
|
|
IF_tlbMG_m_updRepIdx_lat_1_whas__74_THEN_tlbMG_ETC___d293 } ;
|
|
assign tlbMG_m_updRepIdx_rl$EN = 1'd1 ;
|
|
|
|
// register tlbMG_m_validVec_0
|
|
assign tlbMG_m_validVec_0$D_IN = MUX_tlbMG_m_validVec_0$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_0$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_1
|
|
assign tlbMG_m_validVec_1$D_IN = MUX_tlbMG_m_validVec_1$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_1$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_2
|
|
assign tlbMG_m_validVec_2$D_IN = MUX_tlbMG_m_validVec_2$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_2$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd2 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_3
|
|
assign tlbMG_m_validVec_3$D_IN = MUX_tlbMG_m_validVec_3$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_3$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd3 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_4
|
|
assign tlbMG_m_validVec_4$D_IN = MUX_tlbMG_m_validVec_4$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_4$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd4 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_5
|
|
assign tlbMG_m_validVec_5$D_IN = MUX_tlbMG_m_validVec_5$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_5$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd5 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_6
|
|
assign tlbMG_m_validVec_6$D_IN = MUX_tlbMG_m_validVec_6$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_6$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd6 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_7
|
|
assign tlbMG_m_validVec_7$D_IN = MUX_tlbMG_m_validVec_7$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_7$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h69837 == 3'd7 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbReqQ_data_0
|
|
assign tlbReqQ_data_0$D_IN = v__h47401 ;
|
|
assign tlbReqQ_data_0$EN = CAN_FIRE_RL_doTlbReq ;
|
|
|
|
// register tlbReqQ_empty_rl
|
|
assign tlbReqQ_empty_rl$D_IN =
|
|
!CAN_FIRE_RL_doTlbReq &&
|
|
(CAN_FIRE_RL_doTlbResp || tlbReqQ_empty_rl) ;
|
|
assign tlbReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlbReqQ_full_rl
|
|
assign tlbReqQ_full_rl$D_IN =
|
|
CAN_FIRE_RL_doTlbReq ||
|
|
!CAN_FIRE_RL_doTlbResp && tlbReqQ_full_rl ;
|
|
assign tlbReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register transCacheReqQ_data_0
|
|
assign transCacheReqQ_data_0$D_IN = tlbReqQ_data_0 ;
|
|
assign transCacheReqQ_data_0$EN = transCacheReqQ_enqP_lat_0$whas ;
|
|
|
|
// register transCacheReqQ_empty_rl
|
|
assign transCacheReqQ_empty_rl$D_IN =
|
|
!transCacheReqQ_enqP_lat_0$whas &&
|
|
(CAN_FIRE_RL_doTranslationCacheResp || transCacheReqQ_empty_rl) ;
|
|
assign transCacheReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register transCacheReqQ_full_rl
|
|
assign transCacheReqQ_full_rl$D_IN =
|
|
transCacheReqQ_enqP_lat_0$whas ||
|
|
!CAN_FIRE_RL_doTranslationCacheResp && transCacheReqQ_full_rl ;
|
|
assign transCacheReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register vm_info_D
|
|
assign vm_info_D$D_IN = updateVMInfo_vmD ;
|
|
assign vm_info_D$EN = EN_updateVMInfo ;
|
|
|
|
// register vm_info_I
|
|
assign vm_info_I$D_IN = updateVMInfo_vmI ;
|
|
assign vm_info_I$EN = EN_updateVMInfo ;
|
|
|
|
// register waitFlushDone
|
|
assign waitFlushDone$D_IN = !WILL_FIRE_RL_doWaitFlush ;
|
|
assign waitFlushDone$EN =
|
|
WILL_FIRE_RL_doWaitFlush || WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// submodule tlb4KB_m_repRam_bram
|
|
always@(MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 or
|
|
tlb4KB_m_pendReq_rl or
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush or
|
|
tlb4KB_m_flushIdx or WILL_FIRE_RL_tlb4KB_m_doAddEntry)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1:
|
|
tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_pendReq_rl[7:0];
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush:
|
|
tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_flushIdx;
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry:
|
|
tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_pendReq_rl[60:53];
|
|
default: tlb4KB_m_repRam_bram$ADDRA =
|
|
8'bxxxxxxxx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign tlb4KB_m_repRam_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
masked_vpn__h65873[7:0] :
|
|
IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418[7:0] ;
|
|
always@(MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 or
|
|
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1 or
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush or
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry or
|
|
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1:
|
|
tlb4KB_m_repRam_bram$DIA = MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1;
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush: tlb4KB_m_repRam_bram$DIA = 8'd228;
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry:
|
|
tlb4KB_m_repRam_bram$DIA = MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3;
|
|
default: tlb4KB_m_repRam_bram$DIA =
|
|
8'bxxxxxxxx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign tlb4KB_m_repRam_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
8'bxxxxxxxx /* unspecified value */ :
|
|
8'bxxxxxxxx /* unspecified value */ ;
|
|
assign tlb4KB_m_repRam_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_repRam_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_repRam_bram$ENA =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 &&
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1311 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ||
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry ;
|
|
assign tlb4KB_m_repRam_bram$ENB = tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_bram
|
|
assign tlb4KB_m_tlbRam_0_bram$ADDRA =
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_flushIdx ;
|
|
assign tlb4KB_m_tlbRam_0_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
masked_vpn__h65873[7:0] :
|
|
IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418[7:0] ;
|
|
assign tlb4KB_m_tlbRam_0_bram$DIA =
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 ?
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_2 ;
|
|
assign tlb4KB_m_tlbRam_0_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ :
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
assign tlb4KB_m_tlbRam_0_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_0_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_tlbRam_0_bram$ENA =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd0 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ;
|
|
assign tlb4KB_m_tlbRam_0_bram$ENB =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_bram
|
|
assign tlb4KB_m_tlbRam_1_bram$ADDRA =
|
|
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_flushIdx ;
|
|
assign tlb4KB_m_tlbRam_1_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
masked_vpn__h65873[7:0] :
|
|
IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418[7:0] ;
|
|
assign tlb4KB_m_tlbRam_1_bram$DIA =
|
|
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 ?
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_2 ;
|
|
assign tlb4KB_m_tlbRam_1_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ :
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
assign tlb4KB_m_tlbRam_1_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_1_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_tlbRam_1_bram$ENA =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd1 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ;
|
|
assign tlb4KB_m_tlbRam_1_bram$ENB =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_bram
|
|
assign tlb4KB_m_tlbRam_2_bram$ADDRA =
|
|
MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_flushIdx ;
|
|
assign tlb4KB_m_tlbRam_2_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
masked_vpn__h65873[7:0] :
|
|
IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418[7:0] ;
|
|
assign tlb4KB_m_tlbRam_2_bram$DIA =
|
|
MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 ?
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_2 ;
|
|
assign tlb4KB_m_tlbRam_2_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ :
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
assign tlb4KB_m_tlbRam_2_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_2_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_tlbRam_2_bram$ENA =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd2 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ;
|
|
assign tlb4KB_m_tlbRam_2_bram$ENB =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_bram
|
|
assign tlb4KB_m_tlbRam_3_bram$ADDRA =
|
|
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_flushIdx ;
|
|
assign tlb4KB_m_tlbRam_3_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
masked_vpn__h65873[7:0] :
|
|
IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418[7:0] ;
|
|
assign tlb4KB_m_tlbRam_3_bram$DIA =
|
|
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 ?
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_2 ;
|
|
assign tlb4KB_m_tlbRam_3_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__SEL_1 ?
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ :
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
assign tlb4KB_m_tlbRam_3_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_3_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_tlbRam_3_bram$ENA =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd3 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ;
|
|
assign tlb4KB_m_tlbRam_3_bram$ENB =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule transCache
|
|
assign transCache$addEntry_level = walkLevel__h65400 ;
|
|
assign transCache$addEntry_ppn =
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[53:10] ;
|
|
assign transCache$addEntry_vpn =
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435 ;
|
|
assign transCache$req_vpn = vpn__h53918 ;
|
|
assign transCache$EN_req =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 &&
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1332 ;
|
|
assign transCache$EN_deqResp = CAN_FIRE_RL_doTranslationCacheResp ;
|
|
assign transCache$EN_addEntry =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2] &&
|
|
walkLevel__h65400 != 2'd0 ;
|
|
assign transCache$EN_flush = CAN_FIRE_RL_doStartFlush ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BI_ETC___d1122 =
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1111 ?
|
|
!rsToCQ_full_rl :
|
|
(CAN_FIRE_RL_doTranslationCacheResp ||
|
|
!transCacheReqQ_full_rl) &&
|
|
transCache$RDY_req ;
|
|
assign IF_IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_t_ETC___d1296 =
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 ?
|
|
{ SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231,
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 } :
|
|
{ SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1240,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1246,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1252,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1258,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1260,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1266,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1272,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1278,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1284,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1293 } ;
|
|
assign IF_IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NO_ETC___d1126 =
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d891 ?
|
|
!rsToCQ_full_rl :
|
|
!CAN_FIRE_RL_doStartFlush &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1124 ;
|
|
assign IF_IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NO_ETC___d1494 =
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408 ?
|
|
!rsToCQ_full_rl :
|
|
(SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] ?
|
|
IF_NOT_SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_ETC___d1492 :
|
|
!rsToCQ_full_rl) ;
|
|
assign IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d629 =
|
|
_theResult_____2__h38323 == v__h37913 ;
|
|
assign IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d638 =
|
|
IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d629 &&
|
|
(IF_memReqQ_enqReq_lat_1_whas__70_THEN_memReqQ__ETC___d579 ||
|
|
!EN_toMem_memReq_deq && !memReqQ_deqReq_rl && memReqQ_full) ;
|
|
assign IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d643 =
|
|
IF_IF_memReqQ_deqReq_lat_1_whas__99_THEN_memRe_ETC___d629 &&
|
|
(memReqQ_enqReq_lat_0$whas ?
|
|
!memReqQ_enqReq_lat_0$wget[65] :
|
|
!memReqQ_enqReq_rl[65]) &&
|
|
(IF_memReqQ_deqReq_lat_1_whas__99_THEN_memReqQ__ETC___d605 ||
|
|
memReqQ_empty) ;
|
|
assign IF_IF_pendValid_0_lat_0_whas__01_THEN_pendVali_ETC___d852 =
|
|
v__h47401 ?
|
|
(pendValid_1_lat_0$whas ? !1'd0 : !pendValid_1_rl) :
|
|
(pendValid_0_lat_0$whas ? !1'd0 : !pendValid_0_rl) ;
|
|
assign IF_IF_respForOtherReq_397_BIT_1_398_THEN_NOT_r_ETC___d1455 =
|
|
(IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430 ||
|
|
pendWait_0_rl[2:1] != 2'd1 ||
|
|
pendWalkAddr_0 != newPTEAddr__h65403) ?
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1451 &&
|
|
pendWait_1_rl[2:1] == 2'd1 &&
|
|
pendWalkAddr_1_377_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1453 :
|
|
idx__h64702 ;
|
|
assign IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d714 =
|
|
_theResult_____2__h41934 == v__h41524 ;
|
|
assign IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d723 =
|
|
IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d714 &&
|
|
(IF_respLdQ_enqReq_lat_1_whas__55_THEN_respLdQ__ETC___d664 ||
|
|
!respLdQ_deqReq_lat_0$whas && !respLdQ_deqReq_rl &&
|
|
respLdQ_full) ;
|
|
assign IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d728 =
|
|
IF_IF_respLdQ_deqReq_lat_1_whas__84_THEN_respL_ETC___d714 &&
|
|
(EN_toMem_respLd_enq ?
|
|
!respLdQ_enqReq_lat_0$wget[65] :
|
|
!respLdQ_enqReq_rl[65]) &&
|
|
(IF_respLdQ_deqReq_lat_1_whas__84_THEN_respLdQ__ETC___d690 ||
|
|
respLdQ_empty) ;
|
|
assign IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d1009 =
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d957 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d981 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1006 ;
|
|
assign IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932 =
|
|
(IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903 &&
|
|
tlbMG_m_validVec_0 &&
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917) ?
|
|
!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903 :
|
|
!tlbMG_m_validVec_1 ||
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 ;
|
|
assign IF_NOT_SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_ETC___d1492 =
|
|
(!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2]) ?
|
|
IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1458 :
|
|
!rsToCQ_full_rl &&
|
|
NOT_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel__ETC___d1490 ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d1324 =
|
|
(!tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d1316 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] != way__h61664 &&
|
|
tlb4KB_m_repRam_bram$DOB[5:4] != way__h61664) ?
|
|
tlb4KB_m_repRam_bram$DOB[5:4] :
|
|
tlb4KB_m_repRam_bram$DOB[7:6] ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d1325 =
|
|
(!tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d1316 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] != way__h61664) ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[5:4] ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d233 =
|
|
(!tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d222 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] != way__h16259 &&
|
|
tlb4KB_m_repRam_bram$DOB[5:4] != way__h16259) ?
|
|
tlb4KB_m_repRam_bram$DOB[5:4] :
|
|
tlb4KB_m_repRam_bram$DOB[7:6] ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d234 =
|
|
(!tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d222 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] != way__h16259) ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[5:4] ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d237 =
|
|
{ IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d233,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__17_BITS_1__ETC___d234,
|
|
tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d222 ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[1:0],
|
|
way__h16259 } ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1109 =
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089) ?
|
|
tlb4KB_m_tlbRam_1_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d1092 :
|
|
tlb4KB_m_tlbRam_0_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1110 =
|
|
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d1092)) ?
|
|
tlb4KB_m_tlbRam_2_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_2_bram_b_read__90_BITS_79_TO_5_ETC___d1101 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1109 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1111 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d1104 ?
|
|
tlb4KB_m_tlbRam_3_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_3_bram_b_read__02_BITS_79_TO_5_ETC___d1105 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1110 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1113 =
|
|
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d1092)) ?
|
|
2'd2 :
|
|
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089) ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d214 =
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
|
|
tlb4KB_m_pendReq_rl[79:53] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) ?
|
|
tlb4KB_m_tlbRam_1_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d182 &&
|
|
tlb4KB_m_tlbRam_1_bram_b_read__78_BIT_6_84_EQ__ETC___d185 :
|
|
tlb4KB_m_tlbRam_0_bram$DOB[80] ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d215 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d189 ?
|
|
tlb4KB_m_tlbRam_2_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_2_bram_b_read__90_BITS_79_TO_5_ETC___d194 &&
|
|
tlb4KB_m_tlbRam_2_bram_b_read__90_BIT_6_96_EQ__ETC___d197 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d214 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d216 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d201 ?
|
|
tlb4KB_m_tlbRam_3_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_3_bram_b_read__02_BITS_79_TO_5_ETC___d205 &&
|
|
tlb4KB_m_tlbRam_3_bram_b_read__02_BIT_6_06_EQ__ETC___d207 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d215 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d220 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d189 ?
|
|
2'd2 :
|
|
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
|
|
tlb4KB_m_pendReq_rl[79:53] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AN_ETC___d1123 =
|
|
(NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AND_N_ETC___d1096 ?
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_empty_rl :
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AND_t_ETC___d1099) &&
|
|
IF_IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BI_ETC___d1122 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1006 =
|
|
(NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d984 &&
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967 &&
|
|
(!tlbMG_m_validVec_3 ||
|
|
!IF_tlbMG_m_entryVec_3_71_BITS_1_TO_0_72_EQ_0_7_ETC___d989)) ?
|
|
!tlbMG_m_validVec_4 ||
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q11 :
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d984 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1032 =
|
|
((!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903) &&
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d1009 &&
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1018) ?
|
|
!tlbMG_m_validVec_5 ||
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q13 :
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903) &&
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d1009 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1124 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d1086 ?
|
|
!rsToCQ_full_rl &&
|
|
IF_tlbMG_m_updRepIdx_lat_0_whas__77_THEN_NOT_t_ETC___d287 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AN_ETC___d1123 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d957 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d944 ?
|
|
!tlbMG_m_validVec_2 ||
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q7 :
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903) &&
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d981 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d968 ?
|
|
!tlbMG_m_validVec_3 ||
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q9 :
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903) &&
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d957 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1079 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917) ?
|
|
tlbMG_m_validVec_1 &&
|
|
IF_tlbMG_m_entryVec_1_22_BITS_1_TO_0_23_EQ_0_2_ETC___d940 :
|
|
tlbMG_m_validVec_0 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1080 =
|
|
((!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917) &&
|
|
(!tlbMG_m_validVec_1 ||
|
|
!IF_tlbMG_m_entryVec_1_22_BITS_1_TO_0_23_EQ_0_2_ETC___d940)) ?
|
|
tlbMG_m_validVec_2 &&
|
|
IF_tlbMG_m_entryVec_2_47_BITS_1_TO_0_48_EQ_0_4_ETC___d964 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1079 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1081 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967 ?
|
|
tlbMG_m_validVec_3 &&
|
|
IF_tlbMG_m_entryVec_3_71_BITS_1_TO_0_72_EQ_0_7_ETC___d989 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1080 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1082 =
|
|
(NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967 &&
|
|
(!tlbMG_m_validVec_3 ||
|
|
!IF_tlbMG_m_entryVec_3_71_BITS_1_TO_0_72_EQ_0_7_ETC___d989)) ?
|
|
tlbMG_m_validVec_4 &&
|
|
IF_tlbMG_m_entryVec_4_96_BITS_1_TO_0_97_EQ_0_9_ETC___d1015 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1081 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1083 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1018 ?
|
|
tlbMG_m_validVec_5 &&
|
|
IF_tlbMG_m_entryVec_5_022_BITS_1_TO_0_023_EQ_0_ETC___d1042 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1082 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1084 =
|
|
(NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1018 &&
|
|
(!tlbMG_m_validVec_5 ||
|
|
!IF_tlbMG_m_entryVec_5_022_BITS_1_TO_0_023_EQ_0_ETC___d1042)) ?
|
|
tlbMG_m_validVec_6 &&
|
|
IF_tlbMG_m_entryVec_6_048_BITS_1_TO_0_049_EQ_0_ETC___d1057 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1083 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1060 ?
|
|
tlbMG_m_validVec_7 &&
|
|
IF_tlbMG_m_entryVec_7_062_BITS_1_TO_0_063_EQ_0_ETC___d1071 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1084 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1145 =
|
|
((!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917) &&
|
|
(!tlbMG_m_validVec_1 ||
|
|
!IF_tlbMG_m_entryVec_1_22_BITS_1_TO_0_23_EQ_0_2_ETC___d940)) ?
|
|
3'd2 :
|
|
((!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917) ?
|
|
3'd1 :
|
|
3'd0) ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1147 =
|
|
(NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967 &&
|
|
(!tlbMG_m_validVec_3 ||
|
|
!IF_tlbMG_m_entryVec_3_71_BITS_1_TO_0_72_EQ_0_7_ETC___d989)) ?
|
|
3'd4 :
|
|
(NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967 ?
|
|
3'd3 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1145) ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1149 =
|
|
(NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1018 &&
|
|
(!tlbMG_m_validVec_5 ||
|
|
!IF_tlbMG_m_entryVec_5_022_BITS_1_TO_0_023_EQ_0_ETC___d1042)) ?
|
|
3'd6 :
|
|
(NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1018 ?
|
|
3'd5 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1147) ;
|
|
assign IF_NOT_transCacheReqQ_data_0_337_338_OR_NOT_pe_ETC___d1380 =
|
|
(!transCacheReqQ_data_0 || pendWait_0_rl[2:1] != 2'd1 ||
|
|
!pendWalkAddr_0_349_EQ_0_CONCAT_IF_transCache_r_ETC___d1366) ?
|
|
!transCacheReqQ_data_0 && pendWait_1_rl[2:1] == 2'd1 &&
|
|
pendWalkAddr_1 == pteAddr__h63104 :
|
|
transCacheReqQ_data_0 ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 =
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d884 ?
|
|
vm_info_I[46] :
|
|
vm_info_D[46] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408 =
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d1407 ?
|
|
!vm_info_I[46] :
|
|
!vm_info_D[46] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1525 =
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408 ||
|
|
walkLevel__h65400 == 2'd0 ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2] ||
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 =
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d1407 ?
|
|
vm_info_I[46] :
|
|
vm_info_D[46] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1555 =
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2] &&
|
|
walkLevel__h65400 == 2'd0 ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1581 =
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] &&
|
|
(SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2]) &&
|
|
walkLevel__h65400 != 2'd0 &&
|
|
((walkLevel__h65400 == 2'd1) ?
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[18:10] !=
|
|
9'd0 :
|
|
walkLevel__h65400 != 2'd2 ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[27:10] !=
|
|
18'd0) ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1586 =
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] &&
|
|
(SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2]) &&
|
|
walkLevel__h65400 == 2'd0 ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d891 =
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d884 ?
|
|
!vm_info_I[46] :
|
|
!vm_info_D[46] ;
|
|
assign IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1458 =
|
|
(walkLevel__h65400 == 2'd0) ?
|
|
!rsToCQ_full_rl :
|
|
transCache$RDY_addEntry &&
|
|
(IF_IF_respForOtherReq_397_BIT_1_398_THEN_NOT_r_ETC___d1455 ||
|
|
!memReqQ_full) ;
|
|
assign IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1489 =
|
|
(walkLevel__h65400 == 2'd0) ?
|
|
tlb4KB_m_state_46_AND_IF_tlb4KB_m_pendReq_lat__ETC___d816 &&
|
|
NOT_tlb4KB_m_pendIndex_wget__17_BIT_8_18_19_OR_ETC___d1486 :
|
|
!CAN_FIRE_RL_doStartFlush &&
|
|
IF_tlbMG_m_updRepIdx_lat_0_whas__77_THEN_NOT_t_ETC___d287 ;
|
|
assign IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1531 =
|
|
(walkLevel__h65400 == 2'd1) ?
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[18:10] ==
|
|
9'd0 :
|
|
walkLevel__h65400 == 2'd2 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[27:10] ==
|
|
18'd0 ;
|
|
assign IF_memReqQ_deqReq_lat_1_whas__99_THEN_memReqQ__ETC___d605 =
|
|
EN_toMem_memReq_deq || memReqQ_deqReq_rl ;
|
|
assign IF_memReqQ_enqReq_lat_1_whas__70_THEN_memReqQ__ETC___d579 =
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[65] :
|
|
memReqQ_enqReq_rl[65] ;
|
|
assign IF_pendWait_0_rl_21_BITS_2_TO_1_22_EQ_0_23_OR__ETC___d1508 =
|
|
(pendWait_0_rl[2:1] == 2'd0 || pendWait_0_rl[2:1] == 2'd1 ||
|
|
pendWait_0_rl[0] != def__h64929 ||
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430) ?
|
|
pendWait_1_rl[2:1] != 2'd0 && pendWait_1_rl[2:1] != 2'd1 &&
|
|
pendWait_1_rl_49_BIT_0_61_EQ_SEL_ARR_respLdQ_d_ETC___d1505 &&
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1451 :
|
|
idx__h64702 ;
|
|
assign IF_perfReqQ_enqReq_lat_1_whas__39_THEN_perfReq_ETC___d748 =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[4] :
|
|
perfReqQ_enqReq_rl[4] ;
|
|
assign IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430 =
|
|
respForOtherReq[1] ? !respForOtherReq[0] : !def__h64929 ;
|
|
assign IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1451 =
|
|
respForOtherReq[1] ?
|
|
!respForOtherReq[0] :
|
|
SEL_ARR_NOT_respLdQ_data_0_400_BIT_0_401_447_N_ETC___d1450 ;
|
|
assign IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1568 =
|
|
(IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430 ||
|
|
pendWait_0_rl[2:1] != 2'd1 ||
|
|
pendWalkAddr_0 != newPTEAddr__h65403) &&
|
|
(IF_respForOtherReq_397_BIT_1_398_THEN_respForO_ETC___d1515 ||
|
|
pendWait_1_rl[2:1] != 2'd1 ||
|
|
!pendWalkAddr_1_377_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1453) ;
|
|
assign IF_respForOtherReq_397_BIT_1_398_THEN_respForO_ETC___d1515 =
|
|
respForOtherReq[1] ?
|
|
respForOtherReq[0] :
|
|
!SEL_ARR_NOT_respLdQ_data_0_400_BIT_0_401_447_N_ETC___d1450 ;
|
|
assign IF_respLdQ_deqReq_lat_1_whas__84_THEN_respLdQ__ETC___d690 =
|
|
respLdQ_deqReq_lat_0$whas || respLdQ_deqReq_rl ;
|
|
assign IF_respLdQ_enqReq_lat_1_whas__55_THEN_respLdQ__ETC___d664 =
|
|
EN_toMem_respLd_enq ?
|
|
respLdQ_enqReq_lat_0$wget[65] :
|
|
respLdQ_enqReq_rl[65] ;
|
|
assign IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418 =
|
|
EN_toChildren_rqFromC_put ?
|
|
toChildren_rqFromC_put[26:0] :
|
|
rqFromCQ_data_0_rl[26:0] ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
!tlb4KB_m_pendReq_lat_1$wget[80] :
|
|
(tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ?
|
|
!tlb4KB_m_pendReq_lat_0$wget[80] :
|
|
!tlb4KB_m_pendReq_rl[80]) ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_1$wget[81] :
|
|
(tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_0$wget[81] :
|
|
tlb4KB_m_pendReq_rl[81]) ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_1$wget[80] :
|
|
(tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_0$wget[80] :
|
|
tlb4KB_m_pendReq_rl[80]) ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_1$wget[26:0] :
|
|
(tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_0$wget[26:0] :
|
|
tlb4KB_m_pendReq_rl[26:0]) ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_1$wget[79:0] :
|
|
(tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_0$wget[79:0] :
|
|
tlb4KB_m_pendReq_rl[79:0]) ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138 =
|
|
{ IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125 ?
|
|
{ 53'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130 } :
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136 } ;
|
|
assign IF_tlb4KB_m_repRam_rdReqQ_full_lat_0_whas__5_T_ETC___d839 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
!tlb4KB_m_repRam_rdReqQ_full_rl ;
|
|
assign IF_tlb4KB_m_tlbRam_0_rdReqQ_full_lat_0_whas__5_ETC___d827 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_full_rl ;
|
|
assign IF_tlb4KB_m_tlbRam_1_rdReqQ_full_lat_0_whas__5_ETC___d830 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_full_rl ;
|
|
assign IF_tlb4KB_m_tlbRam_2_rdReqQ_full_lat_0_whas__5_ETC___d833 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_full_rl ;
|
|
assign IF_tlb4KB_m_tlbRam_3_rdReqQ_full_lat_0_whas__5_ETC___d836 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ||
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_full_rl ;
|
|
assign IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917 =
|
|
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn3918__ETC__q4 ==
|
|
tlbMG_m_entryVec_0[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_1_22_BITS_1_TO_0_23_EQ_0_2_ETC___d940 =
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn3918__ETC__q5 ==
|
|
tlbMG_m_entryVec_1[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_2_47_BITS_1_TO_0_48_EQ_0_4_ETC___d964 =
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn3918__ETC__q8 ==
|
|
tlbMG_m_entryVec_2[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_3_71_BITS_1_TO_0_72_EQ_0_7_ETC___d989 =
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn3918__ETC__q10 ==
|
|
tlbMG_m_entryVec_3[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_4_96_BITS_1_TO_0_97_EQ_0_9_ETC___d1015 =
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn3918__ETC__q12 ==
|
|
tlbMG_m_entryVec_4[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_5_022_BITS_1_TO_0_023_EQ_0_ETC___d1042 =
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn3918__ETC__q14 ==
|
|
tlbMG_m_entryVec_5[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_6_048_BITS_1_TO_0_049_EQ_0_ETC___d1057 =
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn3918__ETC__q15 ==
|
|
tlbMG_m_entryVec_6[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_7_062_BITS_1_TO_0_063_EQ_0_ETC___d1071 =
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn3918__ETC__q16 ==
|
|
tlbMG_m_entryVec_7[79:53] ;
|
|
assign IF_tlbMG_m_updRepIdx_lat_0_whas__77_THEN_NOT_t_ETC___d287 =
|
|
tlbMG_m_lruBit_lat_0$whas ?
|
|
!tlbMG_m_updRepIdx_lat_0$wget[3] :
|
|
!tlbMG_m_updRepIdx_rl[3] ;
|
|
assign IF_tlbMG_m_updRepIdx_lat_1_whas__74_THEN_tlbMG_ETC___d283 =
|
|
tlbMG_m_updRepIdx_lat_1$whas ?
|
|
tlbMG_m_updRepIdx_lat_1$wget[3] :
|
|
(tlbMG_m_lruBit_lat_0$whas ?
|
|
tlbMG_m_updRepIdx_lat_0$wget[3] :
|
|
tlbMG_m_updRepIdx_rl[3]) ;
|
|
assign IF_tlbMG_m_updRepIdx_lat_1_whas__74_THEN_tlbMG_ETC___d293 =
|
|
tlbMG_m_updRepIdx_lat_1$whas ?
|
|
tlbMG_m_updRepIdx_lat_1$wget[2:0] :
|
|
(tlbMG_m_lruBit_lat_0$whas ?
|
|
tlbMG_m_updRepIdx_lat_0$wget[2:0] :
|
|
tlbMG_m_updRepIdx_rl[2:0]) ;
|
|
assign IF_tlbMG_m_validVec_0_93_AND_tlbMG_m_validVec__ETC___d1604 =
|
|
(tlbMG_m_validVec_0 && tlbMG_m_validVec_1) ?
|
|
(tlbMG_m_validVec_2 ? 3'd3 : 3'd2) :
|
|
(tlbMG_m_validVec_0 ? 3'd1 : 3'd0) ;
|
|
assign IF_tlbMG_m_validVec_4_94_AND_tlbMG_m_validVec__ETC___d1601 =
|
|
(tlbMG_m_validVec_4 && tlbMG_m_validVec_5) ?
|
|
(tlbMG_m_validVec_6 ? 3'd7 : 3'd6) :
|
|
(tlbMG_m_validVec_4 ? 3'd5 : 3'd4) ;
|
|
assign IF_tlbReqQ_full_lat_0_whas__20_THEN_NOT_tlbReq_ETC___d854 =
|
|
(CAN_FIRE_RL_doTlbResp || !tlbReqQ_full_rl) &&
|
|
(EN_toChildren_rqFromC_put || !rqFromCQ_empty_rl) &&
|
|
IF_IF_pendValid_0_lat_0_whas__01_THEN_pendVali_ETC___d852 ;
|
|
assign IF_transCacheReqQ_data_0_337_AND_pendWait_0_rl_ETC___d1372 =
|
|
(transCacheReqQ_data_0 && pendWait_0_rl[2:1] == 2'd1 &&
|
|
pendWalkAddr_0_349_EQ_0_CONCAT_IF_transCache_r_ETC___d1366) ?
|
|
IF_transCache_RDY_resp__334_AND_transCache_res_ETC___d1346 :
|
|
transCacheReqQ_data_0 || pendWait_1_rl[2:1] != 2'd1 ||
|
|
IF_transCache_RDY_resp__334_AND_transCache_res_ETC___d1346 ;
|
|
assign IF_transCache_RDY_resp__334_AND_transCache_res_ETC___d1346 =
|
|
(transCache$RDY_resp &&
|
|
transCache_resp__342_BITS_45_TO_44_343_ULT_2___d1344) ?
|
|
transCache$RDY_resp :
|
|
!transCacheReqQ_empty_rl ;
|
|
assign INV_n__read1326__q19 = ~n__read__h71326 ;
|
|
assign NOT_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel__ETC___d1490 =
|
|
walkLevel__h65400 != 2'd0 &&
|
|
((walkLevel__h65400 == 2'd1) ?
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[18:10] !=
|
|
9'd0 :
|
|
walkLevel__h65400 != 2'd2 ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[27:10] !=
|
|
18'd0) ||
|
|
IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1489 ;
|
|
assign NOT_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel__ETC___d1725 =
|
|
walkLevel__h65400 != 2'd0 &&
|
|
(!tlbMG_m_validVec_0 ||
|
|
tlbMG_m_entryVec_0[79:53] != masked_vpn__h65873 ||
|
|
tlbMG_m_entryVec_0[1:0] != walkLevel__h65400 ||
|
|
tlbMG_m_entryVec_0[6] !=
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[5]) &&
|
|
NOT_tlbMG_m_validVec_1_20_21_OR_NOT_tlbMG_m_en_ETC___d1723 ;
|
|
assign NOT_tlb4KB_m_pendIndex_wget__17_BIT_8_18_19_OR_ETC___d1486 =
|
|
(!tlb4KB_m_pendIndex$wget[8] ||
|
|
tlb4KB_m_pendIndex$wget[7:0] != masked_vpn__h65873[7:0]) &&
|
|
IF_tlb4KB_m_tlbRam_0_rdReqQ_full_lat_0_whas__5_ETC___d827 &&
|
|
IF_tlb4KB_m_tlbRam_1_rdReqQ_full_lat_0_whas__5_ETC___d830 &&
|
|
IF_tlb4KB_m_tlbRam_2_rdReqQ_full_lat_0_whas__5_ETC___d833 &&
|
|
IF_tlb4KB_m_tlbRam_3_rdReqQ_full_lat_0_whas__5_ETC___d836 &&
|
|
IF_tlb4KB_m_repRam_rdReqQ_full_lat_0_whas__5_T_ETC___d839 ;
|
|
assign NOT_tlb4KB_m_pendIndex_wget__17_BIT_8_18_19_OR_ETC___d860 =
|
|
(!tlb4KB_m_pendIndex$wget[8] ||
|
|
tlb4KB_m_pendIndex$wget[7:0] !=
|
|
IF_rqFromCQ_data_0_lat_0_whas__97_THEN_rqFromC_ETC___d418[7:0]) &&
|
|
IF_tlb4KB_m_tlbRam_0_rdReqQ_full_lat_0_whas__5_ETC___d827 &&
|
|
IF_tlb4KB_m_tlbRam_1_rdReqQ_full_lat_0_whas__5_ETC___d830 &&
|
|
IF_tlb4KB_m_tlbRam_2_rdReqQ_full_lat_0_whas__5_ETC___d833 &&
|
|
IF_tlb4KB_m_tlbRam_3_rdReqQ_full_lat_0_whas__5_ETC___d836 &&
|
|
IF_tlb4KB_m_repRam_rdReqQ_full_lat_0_whas__5_T_ETC___d839 &&
|
|
IF_tlbReqQ_full_lat_0_whas__20_THEN_NOT_tlbReq_ETC___d854 ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d1104 =
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d1092) &&
|
|
(!tlb4KB_m_tlbRam_2_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_2_bram_b_read__90_BITS_79_TO_5_ETC___d1101) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d189 =
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
|
|
tlb4KB_m_pendReq_rl[79:53] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d182 ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__78_BIT_6_84_EQ__ETC___d185) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d201 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d189 &&
|
|
(!tlb4KB_m_tlbRam_2_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_2_bram_b_read__90_BITS_79_TO_5_ETC___d194 ||
|
|
!tlb4KB_m_tlbRam_2_bram_b_read__90_BIT_6_96_EQ__ETC___d197) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d258 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d201 &&
|
|
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_3_bram_b_read__02_BITS_79_TO_5_ETC___d205 ||
|
|
!tlb4KB_m_tlbRam_3_bram_b_read__02_BIT_6_06_EQ__ETC___d207) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AND_N_ETC___d1096 =
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_empty_rl &&
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_empty_rl &&
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d1092) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_rl_52_AND_t_ETC___d1099 =
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_empty_rl &&
|
|
(tlb4KB_m_tlbRam_0_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089 ||
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_empty_rl) ;
|
|
assign NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_rl_7_54_AND_ETC___d1131 =
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_empty_rl &&
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_empty_rl &&
|
|
!tlb4KB_m_repRam_rdReqQ_empty_rl &&
|
|
!tlbReqQ_empty_rl &&
|
|
tlb4KB_m_state &&
|
|
tlb4KB_m_pendReq_rl[81] &&
|
|
!tlb4KB_m_pendReq_rl[80] &&
|
|
IF_IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NO_ETC___d1126 ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d1086 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903) &&
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d957 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d981 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1006 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d1032 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d944 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903) &&
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932 &&
|
|
(!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917) &&
|
|
(!tlbMG_m_validVec_1 ||
|
|
!IF_tlbMG_m_entryVec_1_22_BITS_1_TO_0_23_EQ_0_2_ETC___d940) ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d968 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903) &&
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d957 &&
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967 ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m_ent_ETC___d984 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903) &&
|
|
IF_IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ__ETC___d932 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d957 &&
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_IF_tlbMG_m__ETC___d981 ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1018 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967 &&
|
|
(!tlbMG_m_validVec_3 ||
|
|
!IF_tlbMG_m_entryVec_3_71_BITS_1_TO_0_72_EQ_0_7_ETC___d989) &&
|
|
(!tlbMG_m_validVec_4 ||
|
|
!IF_tlbMG_m_entryVec_4_96_BITS_1_TO_0_97_EQ_0_9_ETC___d1015) ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1060 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1018 &&
|
|
(!tlbMG_m_validVec_5 ||
|
|
!IF_tlbMG_m_entryVec_5_022_BITS_1_TO_0_023_EQ_0_ETC___d1042) &&
|
|
(!tlbMG_m_validVec_6 ||
|
|
!IF_tlbMG_m_entryVec_6_048_BITS_1_TO_0_049_EQ_0_ETC___d1057) ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1311 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1060 &&
|
|
(!tlbMG_m_validVec_7 ||
|
|
!IF_tlbMG_m_entryVec_7_062_BITS_1_TO_0_063_EQ_0_ETC___d1071) &&
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1111 ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1332 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1060 &&
|
|
(!tlbMG_m_validVec_7 ||
|
|
!IF_tlbMG_m_entryVec_7_062_BITS_1_TO_0_063_EQ_0_ETC___d1071) &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d1104 &&
|
|
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_3_bram_b_read__02_BITS_79_TO_5_ETC___d1105) ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d967 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d917) &&
|
|
(!tlbMG_m_validVec_1 ||
|
|
!IF_tlbMG_m_entryVec_1_22_BITS_1_TO_0_23_EQ_0_2_ETC___d940) &&
|
|
(!tlbMG_m_validVec_2 ||
|
|
!IF_tlbMG_m_entryVec_2_47_BITS_1_TO_0_48_EQ_0_4_ETC___d964) ;
|
|
assign NOT_tlbMG_m_validVec_0_93_94_OR_NOT_tlbMG_m_va_ETC___d1594 =
|
|
!tlbMG_m_validVec_0 || !tlbMG_m_validVec_1 ||
|
|
!tlbMG_m_validVec_2 ||
|
|
!tlbMG_m_validVec_3 ||
|
|
!tlbMG_m_validVec_4 ||
|
|
!tlbMG_m_validVec_5 ||
|
|
!tlbMG_m_validVec_6 ||
|
|
!tlbMG_m_validVec_7 ;
|
|
assign NOT_tlbMG_m_validVec_1_20_21_OR_NOT_tlbMG_m_en_ETC___d1723 =
|
|
(!tlbMG_m_validVec_1 ||
|
|
tlbMG_m_entryVec_1[79:53] != masked_vpn__h65873 ||
|
|
tlbMG_m_entryVec_1[1:0] != walkLevel__h65400 ||
|
|
tlbMG_m_entryVec_1[6] !=
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[5]) &&
|
|
(!tlbMG_m_validVec_2 ||
|
|
tlbMG_m_entryVec_2[79:53] != masked_vpn__h65873 ||
|
|
tlbMG_m_entryVec_2[1:0] != walkLevel__h65400 ||
|
|
tlbMG_m_entryVec_2[6] !=
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[5]) &&
|
|
NOT_tlbMG_m_validVec_3_69_70_OR_NOT_tlbMG_m_en_ETC___d1721 ;
|
|
assign NOT_tlbMG_m_validVec_3_69_70_OR_NOT_tlbMG_m_en_ETC___d1721 =
|
|
(!tlbMG_m_validVec_3 ||
|
|
tlbMG_m_entryVec_3[79:53] != masked_vpn__h65873 ||
|
|
tlbMG_m_entryVec_3[1:0] != walkLevel__h65400 ||
|
|
tlbMG_m_entryVec_3[6] !=
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[5]) &&
|
|
(!tlbMG_m_validVec_4 ||
|
|
tlbMG_m_entryVec_4[79:53] != masked_vpn__h65873 ||
|
|
tlbMG_m_entryVec_4[1:0] != walkLevel__h65400 ||
|
|
tlbMG_m_entryVec_4[6] !=
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[5]) &&
|
|
NOT_tlbMG_m_validVec_5_020_021_OR_NOT_tlbMG_m__ETC___d1719 ;
|
|
assign NOT_tlbMG_m_validVec_5_020_021_OR_NOT_tlbMG_m__ETC___d1719 =
|
|
(!tlbMG_m_validVec_5 ||
|
|
tlbMG_m_entryVec_5[79:53] != masked_vpn__h65873 ||
|
|
tlbMG_m_entryVec_5[1:0] != walkLevel__h65400 ||
|
|
tlbMG_m_entryVec_5[6] !=
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[5]) &&
|
|
(!tlbMG_m_validVec_6 ||
|
|
tlbMG_m_entryVec_6[79:53] != masked_vpn__h65873 ||
|
|
tlbMG_m_entryVec_6[1:0] != walkLevel__h65400 ||
|
|
tlbMG_m_entryVec_6[6] !=
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[5]) &&
|
|
(!tlbMG_m_validVec_7 ||
|
|
tlbMG_m_entryVec_7[79:53] != masked_vpn__h65873 ||
|
|
tlbMG_m_entryVec_7[1:0] != walkLevel__h65400 ||
|
|
tlbMG_m_entryVec_7[6] !=
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[5]) ;
|
|
assign SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1534 =
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] &&
|
|
(SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2]) &&
|
|
(walkLevel__h65400 == 2'd0 ||
|
|
IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1531) ;
|
|
assign SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1560 =
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2] &&
|
|
walkLevel__h65400 != 2'd0 &&
|
|
IF_IF_respForOtherReq_397_BIT_1_398_THEN_NOT_r_ETC___d1455 ;
|
|
assign SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1571 =
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] &&
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2] &&
|
|
walkLevel__h65400 != 2'd0 &&
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1568 ;
|
|
assign SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1728 =
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0] &&
|
|
(SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[3] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[1] ||
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[2]) &&
|
|
IF_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel_1_ETC___d1531 &&
|
|
NOT_SEL_ARR_pendWalkLevel_0_422_pendWalkLevel__ETC___d1725 ;
|
|
assign _dfoo21 =
|
|
idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1581 ||
|
|
idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
(SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1534 ||
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0]) ;
|
|
assign _dfoo23 =
|
|
idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1581 ||
|
|
idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
(SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1534 ||
|
|
!SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[0]) ;
|
|
assign _dfoo30 =
|
|
(idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1571) ?
|
|
{ 2'd1, 1'bx /* unspecified value */ } :
|
|
((idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1581) ?
|
|
{ 2'd0, 1'bx /* unspecified value */ } :
|
|
{ 2'd0, 1'bx /* unspecified value */ }) ;
|
|
assign _dfoo32 =
|
|
(idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1571) ?
|
|
{ 2'd1, 1'bx /* unspecified value */ } :
|
|
((idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1581) ?
|
|
{ 2'd0, 1'bx /* unspecified value */ } :
|
|
{ 2'd0, 1'bx /* unspecified value */ }) ;
|
|
assign _dfoo33 =
|
|
idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1560 ||
|
|
idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1571 ||
|
|
_dfoo21 ;
|
|
assign _dfoo34 =
|
|
(idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1560) ?
|
|
{ 2'd2,
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430 ||
|
|
pendWait_0_rl[2:1] != 2'd1 ||
|
|
pendWalkAddr_0 != newPTEAddr__h65403 } :
|
|
_dfoo30 ;
|
|
assign _dfoo35 =
|
|
idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1560 ||
|
|
idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1571 ||
|
|
_dfoo23 ;
|
|
assign _dfoo36 =
|
|
(idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1529 &&
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1560) ?
|
|
{ 2'd2,
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430 ||
|
|
pendWait_0_rl[2:1] != 2'd1 ||
|
|
pendWalkAddr_0 != newPTEAddr__h65403 } :
|
|
_dfoo32 ;
|
|
assign _dfoo45 =
|
|
idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408 ||
|
|
idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1555 ||
|
|
_dfoo33 ;
|
|
assign _dfoo47 =
|
|
idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408 ||
|
|
idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1555 ||
|
|
_dfoo35 ;
|
|
assign _dfoo49 =
|
|
idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408 ||
|
|
idx__h64702 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1555 ||
|
|
_dfoo21 ;
|
|
assign _dfoo5 =
|
|
tlbReqQ_data_0 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d891 ||
|
|
tlbReqQ_data_0 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 &&
|
|
(IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 ||
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1311) ;
|
|
assign _dfoo51 =
|
|
idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1408 ||
|
|
idx__h64702 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1555 ||
|
|
_dfoo23 ;
|
|
assign _dfoo7 =
|
|
tlbReqQ_data_0 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d891 ||
|
|
tlbReqQ_data_0 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_p_ETC___d1142 &&
|
|
(IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1085 ||
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1311) ;
|
|
assign _theResult_____2__h38323 =
|
|
IF_memReqQ_deqReq_lat_1_whas__99_THEN_memReqQ__ETC___d605 ?
|
|
next_deqP___1__h38512 :
|
|
memReqQ_deqP ;
|
|
assign _theResult_____2__h41934 =
|
|
IF_respLdQ_deqReq_lat_1_whas__84_THEN_respLdQ__ETC___d690 ?
|
|
next_deqP___1__h42123 :
|
|
respLdQ_deqP ;
|
|
assign addIdx__h72563 =
|
|
(!INV_n__read1326__q19[0] && !INV_n__read1326__q19[1] &&
|
|
!INV_n__read1326__q19[2] &&
|
|
!INV_n__read1326__q19[3]) ?
|
|
((!INV_n__read1326__q19[4] && !INV_n__read1326__q19[5]) ?
|
|
(INV_n__read1326__q19[6] ? 3'd6 : 3'd7) :
|
|
(INV_n__read1326__q19[4] ? 3'd4 : 3'd5)) :
|
|
((!INV_n__read1326__q19[0] && !INV_n__read1326__q19[1]) ?
|
|
(INV_n__read1326__q19[2] ? 3'd2 : 3'd3) :
|
|
(INV_n__read1326__q19[0] ? 3'd0 : 3'd1)) ;
|
|
assign addIdx__h73829 =
|
|
(tlbMG_m_validVec_0 && tlbMG_m_validVec_1 &&
|
|
tlbMG_m_validVec_2 &&
|
|
tlbMG_m_validVec_3) ?
|
|
IF_tlbMG_m_validVec_4_94_AND_tlbMG_m_validVec__ETC___d1601 :
|
|
IF_tlbMG_m_validVec_0_93_AND_tlbMG_m_validVec__ETC___d1604 ;
|
|
assign baseAddr__h63103 = { 8'd0, x__h63376 } ;
|
|
assign basePpn__h63372 =
|
|
transCache_resp__342_BITS_45_TO_44_343_ULT_2___d1344 ?
|
|
transCache$resp[43:0] :
|
|
rootPPN__h63102 ;
|
|
assign idx__h55354 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbMG_m_ETC___d1060 ?
|
|
3'd7 :
|
|
IF_NOT_tlbMG_m_validVec_0_93_94_OR_NOT_IF_tlbM_ETC___d1149 ;
|
|
assign idx__h64702 = respForOtherReq[1] ? respForOtherReq[0] : def__h64929 ;
|
|
assign n__read__h71326 =
|
|
tlbMG_m_lruBit_lat_0$whas ? upd__h71353 : tlbMG_m_lruBit_rl ;
|
|
assign newPTBase__h65402 = { 8'd0, x__h65491 } ;
|
|
assign newPTEAddr__h65403 = newPTBase__h65402 + { 52'd0, x__h65508, 3'd0 } ;
|
|
assign newWalkLevel__h65401 = walkLevel__h65400 - 2'd1 ;
|
|
assign next_deqP___1__h38512 = memReqQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h42123 = respLdQ_deqP + 1'd1 ;
|
|
assign pendWait_0_rl_21_BITS_2_TO_1_22_EQ_0_23_OR_pen_ETC___d1517 =
|
|
(pendWait_0_rl[2:1] == 2'd0 || pendWait_0_rl[2:1] == 2'd1 ||
|
|
pendWait_0_rl[0] != def__h64929 ||
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_NOT_resp_ETC___d1430) &&
|
|
(pendWait_1_rl[2:1] == 2'd0 || pendWait_1_rl[2:1] == 2'd1 ||
|
|
!pendWait_1_rl_49_BIT_0_61_EQ_SEL_ARR_respLdQ_d_ETC___d1505 ||
|
|
IF_respForOtherReq_397_BIT_1_398_THEN_respForO_ETC___d1515) ;
|
|
assign pendWait_1_rl_49_BIT_0_61_EQ_SEL_ARR_respLdQ_d_ETC___d1505 =
|
|
pendWait_1_rl[0] == def__h64929 ;
|
|
assign pendWalkAddr_0_349_EQ_0_CONCAT_IF_transCache_r_ETC___d1366 =
|
|
pendWalkAddr_0 == pteAddr__h63104 ;
|
|
assign pendWalkAddr_1_377_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1453 =
|
|
pendWalkAddr_1 == newPTEAddr__h65403 ;
|
|
assign pteAddr__h63104 = baseAddr__h63103 + { 52'd0, x__h63417, 3'd0 } ;
|
|
assign rootPPN__h63102 =
|
|
CASE_transCacheReqQ_data_0_0_NOT_pendReq_0_BIT_ETC__q3 ?
|
|
vm_info_I[43:0] :
|
|
vm_info_D[43:0] ;
|
|
assign tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d1316 =
|
|
tlb4KB_m_repRam_bram$DOB[1:0] == way__h61664 ;
|
|
assign tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d222 =
|
|
tlb4KB_m_repRam_bram$DOB[1:0] == way__h16259 ;
|
|
assign tlb4KB_m_repRam_bram_b_read__17_BITS_1_TO_0_18_ETC___d238 =
|
|
tlb4KB_m_repRam_bram$DOB[1:0] == tlb4KB_m_repRam_bram$DOB[7:6] ;
|
|
assign tlb4KB_m_state_46_AND_IF_tlb4KB_m_pendReq_lat__ETC___d816 =
|
|
tlb4KB_m_state &&
|
|
(tlb4KB_m_tlbRam_0_rdReqQ_deqP_lat_0$whas ?
|
|
!tlb4KB_m_pendReq_lat_0$wget[81] :
|
|
!tlb4KB_m_pendReq_rl[81]) ;
|
|
assign tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_79_TO_5_ETC___d1089 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
|
|
assign tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d1092 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
|
|
assign tlb4KB_m_tlbRam_1_bram_b_read__78_BITS_79_TO_5_ETC___d182 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
|
|
assign tlb4KB_m_tlbRam_1_bram_b_read__78_BIT_6_84_EQ__ETC___d185 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
|
|
assign tlb4KB_m_tlbRam_2_bram_b_read__90_BITS_79_TO_5_ETC___d1101 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
|
|
assign tlb4KB_m_tlbRam_2_bram_b_read__90_BITS_79_TO_5_ETC___d194 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
|
|
assign tlb4KB_m_tlbRam_2_bram_b_read__90_BIT_6_96_EQ__ETC___d197 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
|
|
assign tlb4KB_m_tlbRam_3_bram_b_read__02_BITS_79_TO_5_ETC___d1105 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
|
|
assign tlb4KB_m_tlbRam_3_bram_b_read__02_BITS_79_TO_5_ETC___d205 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
|
|
assign tlb4KB_m_tlbRam_3_bram_b_read__02_BIT_6_06_EQ__ETC___d207 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
|
|
assign transCacheReqQ_empty_rl_32_OR_NOT_transCacheRe_ETC___d1383 =
|
|
(transCacheReqQ_empty_rl || !transCacheReqQ_data_0 ||
|
|
pendWait_0_rl[2:1] != 2'd1 ||
|
|
IF_transCache_RDY_resp__334_AND_transCache_res_ETC___d1346) &&
|
|
IF_transCacheReqQ_data_0_337_AND_pendWait_0_rl_ETC___d1372 &&
|
|
IF_NOT_transCacheReqQ_data_0_337_338_OR_NOT_pe_ETC___d1380 ||
|
|
!memReqQ_full ;
|
|
assign transCache_resp__342_BITS_45_TO_44_343_ULT_2___d1344 =
|
|
transCache$resp[45:44] < 2'd2 ;
|
|
assign upd__h71353 =
|
|
WILL_FIRE_RL_tlbMG_m_doUpdateRep ?
|
|
MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1 :
|
|
8'd0 ;
|
|
assign v__h37913 =
|
|
IF_memReqQ_enqReq_lat_1_whas__70_THEN_memReqQ__ETC___d579 ?
|
|
v__h38064 :
|
|
memReqQ_enqP ;
|
|
assign v__h38064 = memReqQ_enqP + 1'd1 ;
|
|
assign v__h41524 =
|
|
IF_respLdQ_enqReq_lat_1_whas__55_THEN_respLdQ__ETC___d664 ?
|
|
v__h41675 :
|
|
respLdQ_enqP ;
|
|
assign v__h41675 = respLdQ_enqP + 1'd1 ;
|
|
assign v__h47401 = pendValid_0_lat_0$whas ? 1'd0 : pendValid_0_rl ;
|
|
assign v__h69837 =
|
|
NOT_tlbMG_m_validVec_0_93_94_OR_NOT_tlbMG_m_va_ETC___d1594 ?
|
|
addIdx__h73829 :
|
|
v__h71094 ;
|
|
assign v__h71094 =
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 ?
|
|
tlbMG_m_randIdx :
|
|
v__h71542 ;
|
|
assign v__h71542 =
|
|
(INV_n__read1326__q19[0] || INV_n__read1326__q19[1] ||
|
|
INV_n__read1326__q19[2] ||
|
|
INV_n__read1326__q19[3] ||
|
|
INV_n__read1326__q19[4] ||
|
|
INV_n__read1326__q19[5] ||
|
|
INV_n__read1326__q19[6] ||
|
|
INV_n__read1326__q19[7]) ?
|
|
addIdx__h72563 :
|
|
3'd0 ;
|
|
assign val__h20096 = tlbMG_m_lruBit_rl | x__h20154 ;
|
|
assign w__h55979 = way__h61664 ;
|
|
assign way__h16259 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d201 ?
|
|
2'd3 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d220 ;
|
|
assign way__h61664 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_80_6_ETC___d1104 ?
|
|
2'd3 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT_8_ETC___d1113 ;
|
|
assign x__h20154 = 8'd1 << tlbMG_m_updRepIdx_rl[2:0] ;
|
|
assign x__h63376 = { basePpn__h63372, 12'd0 } ;
|
|
assign x__h65491 =
|
|
{ SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[53:10],
|
|
12'd0 } ;
|
|
always@(memReqQ_deqP or memReqQ_data_0 or memReqQ_data_1)
|
|
begin
|
|
case (memReqQ_deqP)
|
|
1'd0:
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1 =
|
|
memReqQ_data_0[64:1];
|
|
1'd1:
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1 =
|
|
memReqQ_data_1[64:1];
|
|
endcase
|
|
end
|
|
always@(memReqQ_deqP or memReqQ_data_0 or memReqQ_data_1)
|
|
begin
|
|
case (memReqQ_deqP)
|
|
1'd0:
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 =
|
|
memReqQ_data_0[0];
|
|
1'd1:
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 =
|
|
memReqQ_data_1[0];
|
|
endcase
|
|
end
|
|
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
|
|
begin
|
|
case (respLdQ_deqP)
|
|
1'd0: def__h64929 = respLdQ_data_0[0];
|
|
1'd1: def__h64929 = respLdQ_data_1[0];
|
|
endcase
|
|
end
|
|
always@(idx__h64702 or pendWalkLevel_0 or pendWalkLevel_1)
|
|
begin
|
|
case (idx__h64702)
|
|
1'd0: walkLevel__h65400 = pendWalkLevel_0;
|
|
1'd1: walkLevel__h65400 = pendWalkLevel_1;
|
|
endcase
|
|
end
|
|
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (tlbReqQ_data_0)
|
|
1'd0: vpn__h53918 = pendReq_0[26:0];
|
|
1'd1: vpn__h53918 = pendReq_1[26:0];
|
|
endcase
|
|
end
|
|
always@(transCacheReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (transCacheReqQ_data_0)
|
|
1'd0:
|
|
CASE_transCacheReqQ_data_0_0_NOT_pendReq_0_BIT_ETC__q3 =
|
|
!pendReq_0[29];
|
|
1'd1:
|
|
CASE_transCacheReqQ_data_0_0_NOT_pendReq_0_BIT_ETC__q3 =
|
|
!pendReq_1[29];
|
|
endcase
|
|
end
|
|
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (tlbReqQ_data_0)
|
|
1'd0:
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d884 =
|
|
!pendReq_0[29];
|
|
1'd1:
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d884 =
|
|
!pendReq_1[29];
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_0 or vpn__h53918)
|
|
begin
|
|
case (tlbMG_m_entryVec_0[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn3918__ETC__q4 =
|
|
vpn__h53918;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn3918__ETC__q4 =
|
|
{ vpn__h53918[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn3918__ETC__q4 =
|
|
{ vpn__h53918[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn3918__ETC__q4 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_0 or tlbReqQ_empty_rl)
|
|
begin
|
|
case (tlbMG_m_entryVec_0[1:0])
|
|
2'd0, 2'd1:
|
|
IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903 =
|
|
!tlbReqQ_empty_rl;
|
|
default: IF_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_EQ_0_9_ETC___d903 =
|
|
tlbMG_m_entryVec_0[1:0] != 2'd2 || !tlbReqQ_empty_rl;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_1 or vpn__h53918)
|
|
begin
|
|
case (tlbMG_m_entryVec_1[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn3918__ETC__q5 =
|
|
vpn__h53918;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn3918__ETC__q5 =
|
|
{ vpn__h53918[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn3918__ETC__q5 =
|
|
{ vpn__h53918[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn3918__ETC__q5 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_1 or tlbReqQ_empty_rl)
|
|
begin
|
|
case (tlbMG_m_entryVec_1[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 =
|
|
!tlbReqQ_empty_rl;
|
|
default: CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 =
|
|
tlbMG_m_entryVec_1[1:0] != 2'd2 || !tlbReqQ_empty_rl;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_2 or tlbReqQ_empty_rl)
|
|
begin
|
|
case (tlbMG_m_entryVec_2[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q7 =
|
|
!tlbReqQ_empty_rl;
|
|
default: CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q7 =
|
|
tlbMG_m_entryVec_2[1:0] != 2'd2 || !tlbReqQ_empty_rl;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_2 or vpn__h53918)
|
|
begin
|
|
case (tlbMG_m_entryVec_2[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn3918__ETC__q8 =
|
|
vpn__h53918;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn3918__ETC__q8 =
|
|
{ vpn__h53918[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn3918__ETC__q8 =
|
|
{ vpn__h53918[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn3918__ETC__q8 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_3 or tlbReqQ_empty_rl)
|
|
begin
|
|
case (tlbMG_m_entryVec_3[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q9 =
|
|
!tlbReqQ_empty_rl;
|
|
default: CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q9 =
|
|
tlbMG_m_entryVec_3[1:0] != 2'd2 || !tlbReqQ_empty_rl;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_3 or vpn__h53918)
|
|
begin
|
|
case (tlbMG_m_entryVec_3[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn3918__ETC__q10 =
|
|
vpn__h53918;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn3918__ETC__q10 =
|
|
{ vpn__h53918[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn3918__ETC__q10 =
|
|
{ vpn__h53918[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn3918__ETC__q10 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_4 or tlbReqQ_empty_rl)
|
|
begin
|
|
case (tlbMG_m_entryVec_4[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q11 =
|
|
!tlbReqQ_empty_rl;
|
|
default: CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q11 =
|
|
tlbMG_m_entryVec_4[1:0] != 2'd2 || !tlbReqQ_empty_rl;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_4 or vpn__h53918)
|
|
begin
|
|
case (tlbMG_m_entryVec_4[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn3918__ETC__q12 =
|
|
vpn__h53918;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn3918__ETC__q12 =
|
|
{ vpn__h53918[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn3918__ETC__q12 =
|
|
{ vpn__h53918[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn3918__ETC__q12 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_5 or tlbReqQ_empty_rl)
|
|
begin
|
|
case (tlbMG_m_entryVec_5[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q13 =
|
|
!tlbReqQ_empty_rl;
|
|
default: CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q13 =
|
|
tlbMG_m_entryVec_5[1:0] != 2'd2 || !tlbReqQ_empty_rl;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_5 or vpn__h53918)
|
|
begin
|
|
case (tlbMG_m_entryVec_5[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn3918__ETC__q14 =
|
|
vpn__h53918;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn3918__ETC__q14 =
|
|
{ vpn__h53918[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn3918__ETC__q14 =
|
|
{ vpn__h53918[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn3918__ETC__q14 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_6 or vpn__h53918)
|
|
begin
|
|
case (tlbMG_m_entryVec_6[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn3918__ETC__q15 =
|
|
vpn__h53918;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn3918__ETC__q15 =
|
|
{ vpn__h53918[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn3918__ETC__q15 =
|
|
{ vpn__h53918[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn3918__ETC__q15 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_7 or vpn__h53918)
|
|
begin
|
|
case (tlbMG_m_entryVec_7[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn3918__ETC__q16 =
|
|
vpn__h53918;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn3918__ETC__q16 =
|
|
{ vpn__h53918[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn3918__ETC__q16 =
|
|
{ vpn__h53918[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn3918__ETC__q16 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201 =
|
|
tlbMG_m_entryVec_0[5];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201 =
|
|
tlbMG_m_entryVec_1[5];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201 =
|
|
tlbMG_m_entryVec_2[5];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201 =
|
|
tlbMG_m_entryVec_3[5];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201 =
|
|
tlbMG_m_entryVec_4[5];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201 =
|
|
tlbMG_m_entryVec_5[5];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201 =
|
|
tlbMG_m_entryVec_6[5];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_5_192_tlbMG__ETC___d1201 =
|
|
tlbMG_m_entryVec_7[5];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171 =
|
|
tlbMG_m_entryVec_0[8];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171 =
|
|
tlbMG_m_entryVec_1[8];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171 =
|
|
tlbMG_m_entryVec_2[8];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171 =
|
|
tlbMG_m_entryVec_3[8];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171 =
|
|
tlbMG_m_entryVec_4[8];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171 =
|
|
tlbMG_m_entryVec_5[8];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171 =
|
|
tlbMG_m_entryVec_6[8];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_8_162_tlbMG__ETC___d1171 =
|
|
tlbMG_m_entryVec_7[8];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1278 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[3];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1278 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[3];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1278 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[3];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1278 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[3];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221 =
|
|
tlbMG_m_entryVec_0[3];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221 =
|
|
tlbMG_m_entryVec_1[3];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221 =
|
|
tlbMG_m_entryVec_2[3];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221 =
|
|
tlbMG_m_entryVec_3[3];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221 =
|
|
tlbMG_m_entryVec_4[3];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221 =
|
|
tlbMG_m_entryVec_5[3];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221 =
|
|
tlbMG_m_entryVec_6[3];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_3_212_tlbMG__ETC___d1221 =
|
|
tlbMG_m_entryVec_7[3];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1266 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[5];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1266 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[5];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1266 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[5];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1266 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[5];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1258 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[7];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1258 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[7];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1258 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[7];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1258 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[7];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181 =
|
|
tlbMG_m_entryVec_0[7];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181 =
|
|
tlbMG_m_entryVec_1[7];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181 =
|
|
tlbMG_m_entryVec_2[7];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181 =
|
|
tlbMG_m_entryVec_3[7];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181 =
|
|
tlbMG_m_entryVec_4[7];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181 =
|
|
tlbMG_m_entryVec_5[7];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181 =
|
|
tlbMG_m_entryVec_6[7];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_7_172_tlbMG__ETC___d1181 =
|
|
tlbMG_m_entryVec_7[7];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1252 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[8];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1252 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[8];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1252 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[8];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1252 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[8];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1240 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1240 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[79:53];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1240 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[79:53];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1240 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[79:53];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151 =
|
|
tlbMG_m_entryVec_0[79:53];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151 =
|
|
tlbMG_m_entryVec_1[79:53];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151 =
|
|
tlbMG_m_entryVec_2[79:53];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151 =
|
|
tlbMG_m_entryVec_3[79:53];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151 =
|
|
tlbMG_m_entryVec_4[79:53];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151 =
|
|
tlbMG_m_entryVec_5[79:53];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151 =
|
|
tlbMG_m_entryVec_6[79:53];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_79_TO_53_16_ETC___d1151 =
|
|
tlbMG_m_entryVec_7[79:53];
|
|
endcase
|
|
end
|
|
always@(transCacheReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (transCacheReqQ_data_0)
|
|
1'd0:
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1358 =
|
|
pendReq_0[26:0];
|
|
1'd1:
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1358 =
|
|
pendReq_1[26:0];
|
|
endcase
|
|
end
|
|
always@(transCache$resp or
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1358)
|
|
begin
|
|
case (transCache$resp[45:44])
|
|
2'd0:
|
|
x__h63417 =
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1358[8:0];
|
|
2'd1:
|
|
x__h63417 =
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1358[17:9];
|
|
2'd2:
|
|
x__h63417 =
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1358[26:18];
|
|
2'd3: x__h63417 = 9'bxxxxxxxxx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(idx__h64702 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (idx__h64702)
|
|
1'd0:
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d1407 =
|
|
!pendReq_0[29];
|
|
1'd1:
|
|
SEL_ARR_NOT_pendReq_0_76_BIT_29_77_78_NOT_pend_ETC___d1407 =
|
|
!pendReq_1[29];
|
|
endcase
|
|
end
|
|
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
|
|
begin
|
|
case (respLdQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412 =
|
|
respLdQ_data_0[64:1];
|
|
1'd1:
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412 =
|
|
respLdQ_data_1[64:1];
|
|
endcase
|
|
end
|
|
always@(walkLevel__h65400 or
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412)
|
|
begin
|
|
case (walkLevel__h65400)
|
|
2'd0:
|
|
masked_ppn__h65874 =
|
|
SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[53:10];
|
|
2'd1:
|
|
masked_ppn__h65874 =
|
|
{ SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[53:19],
|
|
9'd0 };
|
|
2'd2:
|
|
masked_ppn__h65874 =
|
|
{ SEL_ARR_respLdQ_data_0_400_BITS_64_TO_1_409_re_ETC___d1412[53:28],
|
|
18'd0 };
|
|
2'd3: masked_ppn__h65874 = 44'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h64702 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (idx__h64702)
|
|
1'd0:
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435 =
|
|
pendReq_0[26:0];
|
|
1'd1:
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435 =
|
|
pendReq_1[26:0];
|
|
endcase
|
|
end
|
|
always@(newWalkLevel__h65401 or
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435)
|
|
begin
|
|
case (newWalkLevel__h65401)
|
|
2'd0:
|
|
x__h65508 =
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435[8:0];
|
|
2'd1:
|
|
x__h65508 =
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435[17:9];
|
|
2'd2:
|
|
x__h65508 =
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435[26:18];
|
|
2'd3: x__h65508 = 9'bxxxxxxxxx /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(walkLevel__h65400 or
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435)
|
|
begin
|
|
case (walkLevel__h65400)
|
|
2'd0:
|
|
masked_vpn__h65873 =
|
|
SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435;
|
|
2'd1:
|
|
masked_vpn__h65873 =
|
|
{ SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435[26:9],
|
|
9'd0 };
|
|
2'd2:
|
|
masked_vpn__h65873 =
|
|
{ SEL_ARR_pendReq_0_76_BITS_26_TO_0_05_pendReq_1_ETC___d1435[26:18],
|
|
18'd0 };
|
|
2'd3: masked_vpn__h65873 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
|
|
begin
|
|
case (respLdQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_respLdQ_data_0_400_BIT_0_401_447_N_ETC___d1450 =
|
|
!respLdQ_data_0[0];
|
|
1'd1:
|
|
SEL_ARR_NOT_respLdQ_data_0_400_BIT_0_401_447_N_ETC___d1450 =
|
|
!respLdQ_data_1[0];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1284 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[2];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1284 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[2];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1284 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[2];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1284 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[2];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231 =
|
|
tlbMG_m_entryVec_0[2];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231 =
|
|
tlbMG_m_entryVec_1[2];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231 =
|
|
tlbMG_m_entryVec_2[2];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231 =
|
|
tlbMG_m_entryVec_3[2];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231 =
|
|
tlbMG_m_entryVec_4[2];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231 =
|
|
tlbMG_m_entryVec_5[2];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231 =
|
|
tlbMG_m_entryVec_6[2];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_2_222_tlbMG__ETC___d1231 =
|
|
tlbMG_m_entryVec_7[2];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211 =
|
|
tlbMG_m_entryVec_0[4];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211 =
|
|
tlbMG_m_entryVec_1[4];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211 =
|
|
tlbMG_m_entryVec_2[4];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211 =
|
|
tlbMG_m_entryVec_3[4];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211 =
|
|
tlbMG_m_entryVec_4[4];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211 =
|
|
tlbMG_m_entryVec_5[4];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211 =
|
|
tlbMG_m_entryVec_6[4];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_4_202_tlbMG__ETC___d1211 =
|
|
tlbMG_m_entryVec_7[4];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1272 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[4];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1272 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[4];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1272 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[4];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1272 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[4];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1260 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[6];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1260 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[6];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1260 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[6];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BIT__ETC___d1260 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[6];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191 =
|
|
tlbMG_m_entryVec_0[6];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191 =
|
|
tlbMG_m_entryVec_1[6];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191 =
|
|
tlbMG_m_entryVec_2[6];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191 =
|
|
tlbMG_m_entryVec_3[6];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191 =
|
|
tlbMG_m_entryVec_4[6];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191 =
|
|
tlbMG_m_entryVec_5[6];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191 =
|
|
tlbMG_m_entryVec_6[6];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BIT_6_182_tlbMG__ETC___d1191 =
|
|
tlbMG_m_entryVec_7[6];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 =
|
|
tlbMG_m_entryVec_0[1:0];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 =
|
|
tlbMG_m_entryVec_1[1:0];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 =
|
|
tlbMG_m_entryVec_2[1:0];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 =
|
|
tlbMG_m_entryVec_3[1:0];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 =
|
|
tlbMG_m_entryVec_4[1:0];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 =
|
|
tlbMG_m_entryVec_5[1:0];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 =
|
|
tlbMG_m_entryVec_6[1:0];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_1_TO_0_96_t_ETC___d1236 =
|
|
tlbMG_m_entryVec_7[1:0];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1293 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[1:0];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1293 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[1:0];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1293 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[1:0];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1293 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[1:0];
|
|
endcase
|
|
end
|
|
always@(w__h55979 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h55979)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1246 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[52:9];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1246 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[52:9];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1246 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[52:9];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__65_BITS_ETC___d1246 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[52:9];
|
|
endcase
|
|
end
|
|
always@(idx__h55354 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h55354)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161 =
|
|
tlbMG_m_entryVec_0[52:9];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161 =
|
|
tlbMG_m_entryVec_1[52:9];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161 =
|
|
tlbMG_m_entryVec_2[52:9];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161 =
|
|
tlbMG_m_entryVec_3[52:9];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161 =
|
|
tlbMG_m_entryVec_4[52:9];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161 =
|
|
tlbMG_m_entryVec_5[52:9];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161 =
|
|
tlbMG_m_entryVec_6[52:9];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_95_BITS_52_TO_9_152_ETC___d1161 =
|
|
tlbMG_m_entryVec_7[52:9];
|
|
endcase
|
|
end
|
|
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (tlbReqQ_data_0)
|
|
1'd0:
|
|
CASE_tlbReqQ_data_0_0_pendReq_0_BITS_28_TO_27__ETC__q17 =
|
|
pendReq_0[28:27];
|
|
1'd1:
|
|
CASE_tlbReqQ_data_0_0_pendReq_0_BITS_28_TO_27__ETC__q17 =
|
|
pendReq_1[28:27];
|
|
endcase
|
|
end
|
|
always@(idx__h64702 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (idx__h64702)
|
|
1'd0:
|
|
CASE_idx4702_0_pendReq_0_BITS_28_TO_27_1_pendR_ETC__q18 =
|
|
pendReq_0[28:27];
|
|
1'd1:
|
|
CASE_idx4702_0_pendReq_0_BITS_28_TO_27_1_pendR_ETC__q18 =
|
|
pendReq_1[28:27];
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_randIdx or INV_n__read1326__q19)
|
|
begin
|
|
case (tlbMG_m_randIdx)
|
|
3'd0:
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 =
|
|
INV_n__read1326__q19[0];
|
|
3'd1:
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 =
|
|
INV_n__read1326__q19[1];
|
|
3'd2:
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 =
|
|
INV_n__read1326__q19[2];
|
|
3'd3:
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 =
|
|
INV_n__read1326__q19[3];
|
|
3'd4:
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 =
|
|
INV_n__read1326__q19[4];
|
|
3'd5:
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 =
|
|
INV_n__read1326__q19[5];
|
|
3'd6:
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 =
|
|
INV_n__read1326__q19[6];
|
|
3'd7:
|
|
CASE_tlbMG_m_randIdx_0_INV_n__read13269_BIT_0__ETC__q20 =
|
|
INV_n__read1326__q19[7];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
dFlushReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushDoneQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushDoneQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushDoneQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
flushDoneQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushDoneQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
iFlushReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
memReqQ_data_1 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
memReqQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
memReqQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
65'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
memReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendWait_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 2'd0, 1'bx /* unspecified value */ };
|
|
pendWait_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 2'd0, 1'bx /* unspecified value */ };
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 4'bxxxx /* unspecified value */ };
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respForOtherReq <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 1'bx /* unspecified value */ };
|
|
respLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
respLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
respLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
respLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
65'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
respLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsToCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
84'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
rsToCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rsToCQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_flushIdx <= `BSV_ASSIGNMENT_DELAY 8'd0;
|
|
tlb4KB_m_pendReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_repRam_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 8'd0;
|
|
tlbMG_m_randIdx <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
tlbMG_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 3'bxxx /* unspecified value */ };
|
|
tlbMG_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlbReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
transCacheReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
transCacheReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
transCacheReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
vm_info_D <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
vm_info_I <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
waitFlushDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (dFlushReq$EN) dFlushReq <= `BSV_ASSIGNMENT_DELAY dFlushReq$D_IN;
|
|
if (flushDoneQ_clearReq_rl$EN)
|
|
flushDoneQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushDoneQ_clearReq_rl$D_IN;
|
|
if (flushDoneQ_deqReq_rl$EN)
|
|
flushDoneQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushDoneQ_deqReq_rl$D_IN;
|
|
if (flushDoneQ_empty$EN)
|
|
flushDoneQ_empty <= `BSV_ASSIGNMENT_DELAY flushDoneQ_empty$D_IN;
|
|
if (flushDoneQ_enqReq_rl$EN)
|
|
flushDoneQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushDoneQ_enqReq_rl$D_IN;
|
|
if (flushDoneQ_full$EN)
|
|
flushDoneQ_full <= `BSV_ASSIGNMENT_DELAY flushDoneQ_full$D_IN;
|
|
if (iFlushReq$EN) iFlushReq <= `BSV_ASSIGNMENT_DELAY iFlushReq$D_IN;
|
|
if (memReqQ_clearReq_rl$EN)
|
|
memReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
memReqQ_clearReq_rl$D_IN;
|
|
if (memReqQ_data_0$EN)
|
|
memReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY memReqQ_data_0$D_IN;
|
|
if (memReqQ_data_1$EN)
|
|
memReqQ_data_1 <= `BSV_ASSIGNMENT_DELAY memReqQ_data_1$D_IN;
|
|
if (memReqQ_deqP$EN)
|
|
memReqQ_deqP <= `BSV_ASSIGNMENT_DELAY memReqQ_deqP$D_IN;
|
|
if (memReqQ_deqReq_rl$EN)
|
|
memReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY memReqQ_deqReq_rl$D_IN;
|
|
if (memReqQ_empty$EN)
|
|
memReqQ_empty <= `BSV_ASSIGNMENT_DELAY memReqQ_empty$D_IN;
|
|
if (memReqQ_enqP$EN)
|
|
memReqQ_enqP <= `BSV_ASSIGNMENT_DELAY memReqQ_enqP$D_IN;
|
|
if (memReqQ_enqReq_rl$EN)
|
|
memReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY memReqQ_enqReq_rl$D_IN;
|
|
if (memReqQ_full$EN)
|
|
memReqQ_full <= `BSV_ASSIGNMENT_DELAY memReqQ_full$D_IN;
|
|
if (pendValid_0_rl$EN)
|
|
pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY pendValid_0_rl$D_IN;
|
|
if (pendValid_1_rl$EN)
|
|
pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY pendValid_1_rl$D_IN;
|
|
if (pendWait_0_rl$EN)
|
|
pendWait_0_rl <= `BSV_ASSIGNMENT_DELAY pendWait_0_rl$D_IN;
|
|
if (pendWait_1_rl$EN)
|
|
pendWait_1_rl <= `BSV_ASSIGNMENT_DELAY pendWait_1_rl$D_IN;
|
|
if (perfReqQ_clearReq_rl$EN)
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
perfReqQ_clearReq_rl$D_IN;
|
|
if (perfReqQ_data_0$EN)
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY perfReqQ_data_0$D_IN;
|
|
if (perfReqQ_deqReq_rl$EN)
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_deqReq_rl$D_IN;
|
|
if (perfReqQ_empty$EN)
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY perfReqQ_empty$D_IN;
|
|
if (perfReqQ_enqReq_rl$EN)
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN;
|
|
if (perfReqQ_full$EN)
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN;
|
|
if (respForOtherReq$EN)
|
|
respForOtherReq <= `BSV_ASSIGNMENT_DELAY respForOtherReq$D_IN;
|
|
if (respLdQ_clearReq_rl$EN)
|
|
respLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
respLdQ_clearReq_rl$D_IN;
|
|
if (respLdQ_data_0$EN)
|
|
respLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY respLdQ_data_0$D_IN;
|
|
if (respLdQ_data_1$EN)
|
|
respLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY respLdQ_data_1$D_IN;
|
|
if (respLdQ_deqP$EN)
|
|
respLdQ_deqP <= `BSV_ASSIGNMENT_DELAY respLdQ_deqP$D_IN;
|
|
if (respLdQ_deqReq_rl$EN)
|
|
respLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY respLdQ_deqReq_rl$D_IN;
|
|
if (respLdQ_empty$EN)
|
|
respLdQ_empty <= `BSV_ASSIGNMENT_DELAY respLdQ_empty$D_IN;
|
|
if (respLdQ_enqP$EN)
|
|
respLdQ_enqP <= `BSV_ASSIGNMENT_DELAY respLdQ_enqP$D_IN;
|
|
if (respLdQ_enqReq_rl$EN)
|
|
respLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY respLdQ_enqReq_rl$D_IN;
|
|
if (respLdQ_full$EN)
|
|
respLdQ_full <= `BSV_ASSIGNMENT_DELAY respLdQ_full$D_IN;
|
|
if (rqFromCQ_data_0_rl$EN)
|
|
rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_data_0_rl$D_IN;
|
|
if (rqFromCQ_empty_rl$EN)
|
|
rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_empty_rl$D_IN;
|
|
if (rqFromCQ_full_rl$EN)
|
|
rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_full_rl$D_IN;
|
|
if (rsToCQ_data_0_rl$EN)
|
|
rsToCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_data_0_rl$D_IN;
|
|
if (rsToCQ_empty_rl$EN)
|
|
rsToCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_empty_rl$D_IN;
|
|
if (rsToCQ_full_rl$EN)
|
|
rsToCQ_full_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_full_rl$D_IN;
|
|
if (tlb4KB_m_flushIdx$EN)
|
|
tlb4KB_m_flushIdx <= `BSV_ASSIGNMENT_DELAY tlb4KB_m_flushIdx$D_IN;
|
|
if (tlb4KB_m_pendReq_rl$EN)
|
|
tlb4KB_m_pendReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_pendReq_rl$D_IN;
|
|
if (tlb4KB_m_repRam_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_repRam_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_repRam_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_repRam_rdReqQ_full_rl$D_IN;
|
|
if (tlb4KB_m_state$EN)
|
|
tlb4KB_m_state <= `BSV_ASSIGNMENT_DELAY tlb4KB_m_state$D_IN;
|
|
if (tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN;
|
|
if (tlbMG_m_lruBit_rl$EN)
|
|
tlbMG_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY tlbMG_m_lruBit_rl$D_IN;
|
|
if (tlbMG_m_randIdx$EN)
|
|
tlbMG_m_randIdx <= `BSV_ASSIGNMENT_DELAY tlbMG_m_randIdx$D_IN;
|
|
if (tlbMG_m_updRepIdx_rl$EN)
|
|
tlbMG_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlbMG_m_updRepIdx_rl$D_IN;
|
|
if (tlbMG_m_validVec_0$EN)
|
|
tlbMG_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_0$D_IN;
|
|
if (tlbMG_m_validVec_1$EN)
|
|
tlbMG_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_1$D_IN;
|
|
if (tlbMG_m_validVec_2$EN)
|
|
tlbMG_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_2$D_IN;
|
|
if (tlbMG_m_validVec_3$EN)
|
|
tlbMG_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_3$D_IN;
|
|
if (tlbMG_m_validVec_4$EN)
|
|
tlbMG_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_4$D_IN;
|
|
if (tlbMG_m_validVec_5$EN)
|
|
tlbMG_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_5$D_IN;
|
|
if (tlbMG_m_validVec_6$EN)
|
|
tlbMG_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_6$D_IN;
|
|
if (tlbMG_m_validVec_7$EN)
|
|
tlbMG_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_7$D_IN;
|
|
if (tlbReqQ_data_0$EN)
|
|
tlbReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY tlbReqQ_data_0$D_IN;
|
|
if (tlbReqQ_empty_rl$EN)
|
|
tlbReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY tlbReqQ_empty_rl$D_IN;
|
|
if (tlbReqQ_full_rl$EN)
|
|
tlbReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY tlbReqQ_full_rl$D_IN;
|
|
if (transCacheReqQ_data_0$EN)
|
|
transCacheReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
transCacheReqQ_data_0$D_IN;
|
|
if (transCacheReqQ_empty_rl$EN)
|
|
transCacheReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
transCacheReqQ_empty_rl$D_IN;
|
|
if (transCacheReqQ_full_rl$EN)
|
|
transCacheReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
transCacheReqQ_full_rl$D_IN;
|
|
if (vm_info_D$EN) vm_info_D <= `BSV_ASSIGNMENT_DELAY vm_info_D$D_IN;
|
|
if (vm_info_I$EN) vm_info_I <= `BSV_ASSIGNMENT_DELAY vm_info_I$D_IN;
|
|
if (waitFlushDone$EN)
|
|
waitFlushDone <= `BSV_ASSIGNMENT_DELAY waitFlushDone$D_IN;
|
|
end
|
|
if (pendReq_0$EN) pendReq_0 <= `BSV_ASSIGNMENT_DELAY pendReq_0$D_IN;
|
|
if (pendReq_1$EN) pendReq_1 <= `BSV_ASSIGNMENT_DELAY pendReq_1$D_IN;
|
|
if (pendWalkAddr_0$EN)
|
|
pendWalkAddr_0 <= `BSV_ASSIGNMENT_DELAY pendWalkAddr_0$D_IN;
|
|
if (pendWalkAddr_1$EN)
|
|
pendWalkAddr_1 <= `BSV_ASSIGNMENT_DELAY pendWalkAddr_1$D_IN;
|
|
if (pendWalkLevel_0$EN)
|
|
pendWalkLevel_0 <= `BSV_ASSIGNMENT_DELAY pendWalkLevel_0$D_IN;
|
|
if (pendWalkLevel_1$EN)
|
|
pendWalkLevel_1 <= `BSV_ASSIGNMENT_DELAY pendWalkLevel_1$D_IN;
|
|
if (tlbMG_m_entryVec_0$EN)
|
|
tlbMG_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_0$D_IN;
|
|
if (tlbMG_m_entryVec_1$EN)
|
|
tlbMG_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_1$D_IN;
|
|
if (tlbMG_m_entryVec_2$EN)
|
|
tlbMG_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_2$D_IN;
|
|
if (tlbMG_m_entryVec_3$EN)
|
|
tlbMG_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_3$D_IN;
|
|
if (tlbMG_m_entryVec_4$EN)
|
|
tlbMG_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_4$D_IN;
|
|
if (tlbMG_m_entryVec_5$EN)
|
|
tlbMG_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_5$D_IN;
|
|
if (tlbMG_m_entryVec_6$EN)
|
|
tlbMG_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_6$D_IN;
|
|
if (tlbMG_m_entryVec_7$EN)
|
|
tlbMG_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_7$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
dFlushReq = 1'h0;
|
|
flushDoneQ_clearReq_rl = 1'h0;
|
|
flushDoneQ_deqReq_rl = 1'h0;
|
|
flushDoneQ_empty = 1'h0;
|
|
flushDoneQ_enqReq_rl = 1'h0;
|
|
flushDoneQ_full = 1'h0;
|
|
iFlushReq = 1'h0;
|
|
memReqQ_clearReq_rl = 1'h0;
|
|
memReqQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
|
|
memReqQ_data_1 = 65'h0AAAAAAAAAAAAAAAA;
|
|
memReqQ_deqP = 1'h0;
|
|
memReqQ_deqReq_rl = 1'h0;
|
|
memReqQ_empty = 1'h0;
|
|
memReqQ_enqP = 1'h0;
|
|
memReqQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
memReqQ_full = 1'h0;
|
|
pendReq_0 = 30'h2AAAAAAA;
|
|
pendReq_1 = 30'h2AAAAAAA;
|
|
pendValid_0_rl = 1'h0;
|
|
pendValid_1_rl = 1'h0;
|
|
pendWait_0_rl = 3'h2;
|
|
pendWait_1_rl = 3'h2;
|
|
pendWalkAddr_0 = 64'hAAAAAAAAAAAAAAAA;
|
|
pendWalkAddr_1 = 64'hAAAAAAAAAAAAAAAA;
|
|
pendWalkLevel_0 = 2'h2;
|
|
pendWalkLevel_1 = 2'h2;
|
|
perfReqQ_clearReq_rl = 1'h0;
|
|
perfReqQ_data_0 = 4'hA;
|
|
perfReqQ_deqReq_rl = 1'h0;
|
|
perfReqQ_empty = 1'h0;
|
|
perfReqQ_enqReq_rl = 5'h0A;
|
|
perfReqQ_full = 1'h0;
|
|
respForOtherReq = 2'h2;
|
|
respLdQ_clearReq_rl = 1'h0;
|
|
respLdQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
|
|
respLdQ_data_1 = 65'h0AAAAAAAAAAAAAAAA;
|
|
respLdQ_deqP = 1'h0;
|
|
respLdQ_deqReq_rl = 1'h0;
|
|
respLdQ_empty = 1'h0;
|
|
respLdQ_enqP = 1'h0;
|
|
respLdQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
respLdQ_full = 1'h0;
|
|
rqFromCQ_data_0_rl = 30'h2AAAAAAA;
|
|
rqFromCQ_empty_rl = 1'h0;
|
|
rqFromCQ_full_rl = 1'h0;
|
|
rsToCQ_data_0_rl = 84'hAAAAAAAAAAAAAAAAAAAAA;
|
|
rsToCQ_empty_rl = 1'h0;
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rsToCQ_full_rl = 1'h0;
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tlb4KB_m_flushIdx = 8'hAA;
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tlb4KB_m_pendReq_rl = 82'h2AAAAAAAAAAAAAAAAAAAA;
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tlb4KB_m_repRam_rdReqQ_empty_rl = 1'h0;
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tlb4KB_m_repRam_rdReqQ_full_rl = 1'h0;
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tlb4KB_m_state = 1'h0;
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tlb4KB_m_tlbRam_0_rdReqQ_empty_rl = 1'h0;
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tlb4KB_m_tlbRam_0_rdReqQ_full_rl = 1'h0;
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tlb4KB_m_tlbRam_1_rdReqQ_empty_rl = 1'h0;
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tlb4KB_m_tlbRam_1_rdReqQ_full_rl = 1'h0;
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tlb4KB_m_tlbRam_2_rdReqQ_empty_rl = 1'h0;
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tlb4KB_m_tlbRam_2_rdReqQ_full_rl = 1'h0;
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tlb4KB_m_tlbRam_3_rdReqQ_empty_rl = 1'h0;
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tlb4KB_m_tlbRam_3_rdReqQ_full_rl = 1'h0;
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tlbMG_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
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tlbMG_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
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tlbMG_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
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tlbMG_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
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tlbMG_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
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tlbMG_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
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tlbMG_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
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tlbMG_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
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tlbMG_m_lruBit_rl = 8'hAA;
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tlbMG_m_randIdx = 3'h2;
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tlbMG_m_updRepIdx_rl = 4'hA;
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tlbMG_m_validVec_0 = 1'h0;
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tlbMG_m_validVec_1 = 1'h0;
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tlbMG_m_validVec_2 = 1'h0;
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tlbMG_m_validVec_3 = 1'h0;
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tlbMG_m_validVec_4 = 1'h0;
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tlbMG_m_validVec_5 = 1'h0;
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tlbMG_m_validVec_6 = 1'h0;
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tlbMG_m_validVec_7 = 1'h0;
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tlbReqQ_data_0 = 1'h0;
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tlbReqQ_empty_rl = 1'h0;
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tlbReqQ_full_rl = 1'h0;
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transCacheReqQ_data_0 = 1'h0;
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transCacheReqQ_empty_rl = 1'h0;
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transCacheReqQ_full_rl = 1'h0;
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vm_info_D = 49'h0AAAAAAAAAAAA;
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vm_info_I = 49'h0AAAAAAAAAAAA;
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waitFlushDone = 1'h0;
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end
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`endif // BSV_NO_INITIAL_BLOCKS
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// synopsys translate_on
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endmodule // mkL2Tlb
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