520 lines
15 KiB
Verilog
520 lines
15 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:32:23 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// ras_0_first O 129
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// RDY_ras_0_first O 1 const
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// RDY_ras_0_popPush O 1 const
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// ras_1_first O 129
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// RDY_ras_1_first O 1 const
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// RDY_ras_1_popPush O 1 const
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// RDY_flush O 1 const
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// flush_done O 1 const
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// RDY_flush_done O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// ras_0_popPush_pop I 1
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// ras_0_popPush_pushAddr I 130
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// ras_1_popPush_pop I 1
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// ras_1_popPush_pushAddr I 130
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// EN_ras_0_popPush I 1
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// EN_ras_1_popPush I 1
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// EN_flush I 1 unused
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//
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// Combinational paths from inputs to outputs:
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// (ras_0_popPush_pop, ras_0_popPush_pushAddr, EN_ras_0_popPush) -> ras_1_first
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkRas(CLK,
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RST_N,
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ras_0_first,
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RDY_ras_0_first,
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ras_0_popPush_pop,
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ras_0_popPush_pushAddr,
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EN_ras_0_popPush,
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RDY_ras_0_popPush,
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ras_1_first,
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RDY_ras_1_first,
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ras_1_popPush_pop,
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ras_1_popPush_pushAddr,
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EN_ras_1_popPush,
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RDY_ras_1_popPush,
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EN_flush,
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RDY_flush,
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flush_done,
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RDY_flush_done);
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input CLK;
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input RST_N;
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// value method ras_0_first
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output [128 : 0] ras_0_first;
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output RDY_ras_0_first;
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// action method ras_0_popPush
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input ras_0_popPush_pop;
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input [129 : 0] ras_0_popPush_pushAddr;
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input EN_ras_0_popPush;
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output RDY_ras_0_popPush;
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// value method ras_1_first
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output [128 : 0] ras_1_first;
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output RDY_ras_1_first;
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// action method ras_1_popPush
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input ras_1_popPush_pop;
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input [129 : 0] ras_1_popPush_pushAddr;
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input EN_ras_1_popPush;
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output RDY_ras_1_popPush;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// signals for module outputs
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reg [128 : 0] ras_0_first, ras_1_first;
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wire RDY_flush,
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RDY_flush_done,
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RDY_ras_0_first,
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RDY_ras_0_popPush,
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RDY_ras_1_first,
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RDY_ras_1_popPush,
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flush_done;
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// inlined wires
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wire stack_0_lat_0$whas,
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stack_0_lat_1$whas,
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stack_1_lat_0$whas,
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stack_1_lat_1$whas,
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stack_2_lat_0$whas,
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stack_2_lat_1$whas,
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stack_3_lat_0$whas,
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stack_3_lat_1$whas,
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stack_4_lat_0$whas,
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stack_4_lat_1$whas,
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stack_5_lat_0$whas,
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stack_5_lat_1$whas,
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stack_6_lat_0$whas,
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stack_6_lat_1$whas,
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stack_7_lat_0$whas,
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stack_7_lat_1$whas;
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// register head_rl
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reg [2 : 0] head_rl;
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wire [2 : 0] head_rl$D_IN;
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wire head_rl$EN;
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// register stack_0_rl
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reg [128 : 0] stack_0_rl;
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wire [128 : 0] stack_0_rl$D_IN;
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wire stack_0_rl$EN;
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// register stack_1_rl
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reg [128 : 0] stack_1_rl;
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wire [128 : 0] stack_1_rl$D_IN;
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wire stack_1_rl$EN;
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// register stack_2_rl
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reg [128 : 0] stack_2_rl;
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wire [128 : 0] stack_2_rl$D_IN;
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wire stack_2_rl$EN;
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// register stack_3_rl
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reg [128 : 0] stack_3_rl;
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wire [128 : 0] stack_3_rl$D_IN;
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wire stack_3_rl$EN;
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// register stack_4_rl
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reg [128 : 0] stack_4_rl;
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wire [128 : 0] stack_4_rl$D_IN;
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wire stack_4_rl$EN;
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// register stack_5_rl
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reg [128 : 0] stack_5_rl;
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wire [128 : 0] stack_5_rl$D_IN;
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wire stack_5_rl$EN;
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// register stack_6_rl
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reg [128 : 0] stack_6_rl;
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wire [128 : 0] stack_6_rl$D_IN;
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wire stack_6_rl$EN;
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// register stack_7_rl
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reg [128 : 0] stack_7_rl;
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wire [128 : 0] stack_7_rl$D_IN;
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wire stack_7_rl$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_head_canon,
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CAN_FIRE_RL_stack_0_canon,
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CAN_FIRE_RL_stack_1_canon,
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CAN_FIRE_RL_stack_2_canon,
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CAN_FIRE_RL_stack_3_canon,
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CAN_FIRE_RL_stack_4_canon,
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CAN_FIRE_RL_stack_5_canon,
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CAN_FIRE_RL_stack_6_canon,
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CAN_FIRE_RL_stack_7_canon,
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CAN_FIRE_flush,
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CAN_FIRE_ras_0_popPush,
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CAN_FIRE_ras_1_popPush,
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WILL_FIRE_RL_head_canon,
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WILL_FIRE_RL_stack_0_canon,
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WILL_FIRE_RL_stack_1_canon,
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WILL_FIRE_RL_stack_2_canon,
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WILL_FIRE_RL_stack_3_canon,
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WILL_FIRE_RL_stack_4_canon,
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WILL_FIRE_RL_stack_5_canon,
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WILL_FIRE_RL_stack_6_canon,
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WILL_FIRE_RL_stack_7_canon,
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WILL_FIRE_flush,
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WILL_FIRE_ras_0_popPush,
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WILL_FIRE_ras_1_popPush;
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// remaining internal signals
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wire [128 : 0] n__read__h6276,
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n__read__h6278,
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n__read__h6280,
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n__read__h6282,
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n__read__h6284,
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n__read__h6286,
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n__read__h6288,
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n__read__h6290;
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wire [2 : 0] _theResult____h5853,
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_theResult____h6601,
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h___1__h5927,
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h___1__h6672,
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upd__h4823,
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upd__h6245,
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v__h5897,
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v__h6645,
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x__h6201;
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// value method ras_0_first
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always@(head_rl or
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stack_0_rl or
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stack_1_rl or
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stack_2_rl or
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stack_3_rl or stack_4_rl or stack_5_rl or stack_6_rl or stack_7_rl)
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begin
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case (head_rl)
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3'd0: ras_0_first = stack_0_rl;
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3'd1: ras_0_first = stack_1_rl;
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3'd2: ras_0_first = stack_2_rl;
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3'd3: ras_0_first = stack_3_rl;
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3'd4: ras_0_first = stack_4_rl;
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3'd5: ras_0_first = stack_5_rl;
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3'd6: ras_0_first = stack_6_rl;
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3'd7: ras_0_first = stack_7_rl;
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endcase
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end
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assign RDY_ras_0_first = 1'd1 ;
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// action method ras_0_popPush
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assign RDY_ras_0_popPush = 1'd1 ;
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assign CAN_FIRE_ras_0_popPush = 1'd1 ;
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assign WILL_FIRE_ras_0_popPush = EN_ras_0_popPush ;
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// value method ras_1_first
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always@(x__h6201 or
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n__read__h6276 or
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n__read__h6278 or
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n__read__h6280 or
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n__read__h6282 or
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n__read__h6284 or
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n__read__h6286 or n__read__h6288 or n__read__h6290)
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begin
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case (x__h6201)
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3'd0: ras_1_first = n__read__h6276;
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3'd1: ras_1_first = n__read__h6278;
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3'd2: ras_1_first = n__read__h6280;
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3'd3: ras_1_first = n__read__h6282;
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3'd4: ras_1_first = n__read__h6284;
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3'd5: ras_1_first = n__read__h6286;
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3'd6: ras_1_first = n__read__h6288;
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3'd7: ras_1_first = n__read__h6290;
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endcase
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end
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assign RDY_ras_1_first = 1'd1 ;
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// action method ras_1_popPush
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assign RDY_ras_1_popPush = 1'd1 ;
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assign CAN_FIRE_ras_1_popPush = 1'd1 ;
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assign WILL_FIRE_ras_1_popPush = EN_ras_1_popPush ;
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// action method flush
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assign RDY_flush = 1'd1 ;
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assign CAN_FIRE_flush = 1'd1 ;
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assign WILL_FIRE_flush = EN_flush ;
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// value method flush_done
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assign flush_done = 1'd1 ;
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assign RDY_flush_done = 1'd1 ;
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// rule RL_stack_0_canon
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assign CAN_FIRE_RL_stack_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_stack_0_canon = 1'd1 ;
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// rule RL_stack_1_canon
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assign CAN_FIRE_RL_stack_1_canon = 1'd1 ;
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assign WILL_FIRE_RL_stack_1_canon = 1'd1 ;
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// rule RL_stack_2_canon
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assign CAN_FIRE_RL_stack_2_canon = 1'd1 ;
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assign WILL_FIRE_RL_stack_2_canon = 1'd1 ;
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// rule RL_stack_3_canon
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assign CAN_FIRE_RL_stack_3_canon = 1'd1 ;
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assign WILL_FIRE_RL_stack_3_canon = 1'd1 ;
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// rule RL_stack_4_canon
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assign CAN_FIRE_RL_stack_4_canon = 1'd1 ;
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assign WILL_FIRE_RL_stack_4_canon = 1'd1 ;
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// rule RL_stack_5_canon
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assign CAN_FIRE_RL_stack_5_canon = 1'd1 ;
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assign WILL_FIRE_RL_stack_5_canon = 1'd1 ;
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// rule RL_stack_6_canon
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assign CAN_FIRE_RL_stack_6_canon = 1'd1 ;
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assign WILL_FIRE_RL_stack_6_canon = 1'd1 ;
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// rule RL_stack_7_canon
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assign CAN_FIRE_RL_stack_7_canon = 1'd1 ;
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assign WILL_FIRE_RL_stack_7_canon = 1'd1 ;
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// rule RL_head_canon
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assign CAN_FIRE_RL_head_canon = 1'd1 ;
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assign WILL_FIRE_RL_head_canon = 1'd1 ;
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// inlined wires
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assign stack_0_lat_0$whas =
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EN_ras_0_popPush && v__h5897 == 3'd0 &&
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ras_0_popPush_pushAddr[129] ;
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assign stack_0_lat_1$whas =
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EN_ras_1_popPush && v__h6645 == 3'd0 &&
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ras_1_popPush_pushAddr[129] ;
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assign stack_1_lat_0$whas =
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EN_ras_0_popPush && v__h5897 == 3'd1 &&
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ras_0_popPush_pushAddr[129] ;
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assign stack_1_lat_1$whas =
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EN_ras_1_popPush && v__h6645 == 3'd1 &&
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ras_1_popPush_pushAddr[129] ;
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assign stack_2_lat_0$whas =
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EN_ras_0_popPush && v__h5897 == 3'd2 &&
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ras_0_popPush_pushAddr[129] ;
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assign stack_2_lat_1$whas =
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EN_ras_1_popPush && v__h6645 == 3'd2 &&
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ras_1_popPush_pushAddr[129] ;
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assign stack_3_lat_0$whas =
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EN_ras_0_popPush && v__h5897 == 3'd3 &&
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ras_0_popPush_pushAddr[129] ;
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assign stack_3_lat_1$whas =
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EN_ras_1_popPush && v__h6645 == 3'd3 &&
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ras_1_popPush_pushAddr[129] ;
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assign stack_4_lat_0$whas =
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EN_ras_0_popPush && v__h5897 == 3'd4 &&
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ras_0_popPush_pushAddr[129] ;
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assign stack_4_lat_1$whas =
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EN_ras_1_popPush && v__h6645 == 3'd4 &&
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ras_1_popPush_pushAddr[129] ;
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assign stack_5_lat_0$whas =
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EN_ras_0_popPush && v__h5897 == 3'd5 &&
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ras_0_popPush_pushAddr[129] ;
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assign stack_5_lat_1$whas =
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EN_ras_1_popPush && v__h6645 == 3'd5 &&
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ras_1_popPush_pushAddr[129] ;
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assign stack_6_lat_0$whas =
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EN_ras_0_popPush && v__h5897 == 3'd6 &&
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ras_0_popPush_pushAddr[129] ;
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assign stack_6_lat_1$whas =
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EN_ras_1_popPush && v__h6645 == 3'd6 &&
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ras_1_popPush_pushAddr[129] ;
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assign stack_7_lat_0$whas =
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EN_ras_0_popPush && v__h5897 == 3'd7 &&
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ras_0_popPush_pushAddr[129] ;
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assign stack_7_lat_1$whas =
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EN_ras_1_popPush && v__h6645 == 3'd7 &&
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ras_1_popPush_pushAddr[129] ;
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// register head_rl
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assign head_rl$D_IN = EN_ras_1_popPush ? upd__h4823 : x__h6201 ;
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assign head_rl$EN = 1'd1 ;
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// register stack_0_rl
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assign stack_0_rl$D_IN =
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stack_0_lat_1$whas ?
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ras_1_popPush_pushAddr[128:0] :
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n__read__h6276 ;
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assign stack_0_rl$EN = 1'd1 ;
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// register stack_1_rl
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assign stack_1_rl$D_IN =
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stack_1_lat_1$whas ?
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ras_1_popPush_pushAddr[128:0] :
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n__read__h6278 ;
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assign stack_1_rl$EN = 1'd1 ;
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// register stack_2_rl
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assign stack_2_rl$D_IN =
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stack_2_lat_1$whas ?
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ras_1_popPush_pushAddr[128:0] :
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n__read__h6280 ;
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assign stack_2_rl$EN = 1'd1 ;
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// register stack_3_rl
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assign stack_3_rl$D_IN =
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stack_3_lat_1$whas ?
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ras_1_popPush_pushAddr[128:0] :
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n__read__h6282 ;
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assign stack_3_rl$EN = 1'd1 ;
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// register stack_4_rl
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assign stack_4_rl$D_IN =
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stack_4_lat_1$whas ?
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ras_1_popPush_pushAddr[128:0] :
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n__read__h6284 ;
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assign stack_4_rl$EN = 1'd1 ;
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// register stack_5_rl
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assign stack_5_rl$D_IN =
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stack_5_lat_1$whas ?
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ras_1_popPush_pushAddr[128:0] :
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n__read__h6286 ;
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assign stack_5_rl$EN = 1'd1 ;
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// register stack_6_rl
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assign stack_6_rl$D_IN =
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stack_6_lat_1$whas ?
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ras_1_popPush_pushAddr[128:0] :
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n__read__h6288 ;
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assign stack_6_rl$EN = 1'd1 ;
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// register stack_7_rl
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assign stack_7_rl$D_IN =
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stack_7_lat_1$whas ?
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ras_1_popPush_pushAddr[128:0] :
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n__read__h6290 ;
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assign stack_7_rl$EN = 1'd1 ;
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// remaining internal signals
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assign _theResult____h5853 = ras_0_popPush_pop ? h___1__h5927 : head_rl ;
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assign _theResult____h6601 = ras_1_popPush_pop ? h___1__h6672 : x__h6201 ;
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assign h___1__h5927 = head_rl - 3'd1 ;
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assign h___1__h6672 = x__h6201 - 3'd1 ;
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assign n__read__h6276 =
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stack_0_lat_0$whas ? ras_0_popPush_pushAddr[128:0] : stack_0_rl ;
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assign n__read__h6278 =
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stack_1_lat_0$whas ? ras_0_popPush_pushAddr[128:0] : stack_1_rl ;
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assign n__read__h6280 =
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stack_2_lat_0$whas ? ras_0_popPush_pushAddr[128:0] : stack_2_rl ;
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assign n__read__h6282 =
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stack_3_lat_0$whas ? ras_0_popPush_pushAddr[128:0] : stack_3_rl ;
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assign n__read__h6284 =
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stack_4_lat_0$whas ? ras_0_popPush_pushAddr[128:0] : stack_4_rl ;
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assign n__read__h6286 =
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stack_5_lat_0$whas ? ras_0_popPush_pushAddr[128:0] : stack_5_rl ;
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assign n__read__h6288 =
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stack_6_lat_0$whas ? ras_0_popPush_pushAddr[128:0] : stack_6_rl ;
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assign n__read__h6290 =
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stack_7_lat_0$whas ? ras_0_popPush_pushAddr[128:0] : stack_7_rl ;
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assign upd__h4823 =
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ras_1_popPush_pushAddr[129] ? v__h6645 : _theResult____h6601 ;
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assign upd__h6245 =
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ras_0_popPush_pushAddr[129] ? v__h5897 : _theResult____h5853 ;
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assign v__h5897 = _theResult____h5853 + 3'd1 ;
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assign v__h6645 = _theResult____h6601 + 3'd1 ;
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assign x__h6201 = EN_ras_0_popPush ? upd__h6245 : head_rl ;
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
head_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
stack_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h000001FFFFC0180040000000000000000;
|
|
stack_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h000001FFFFC0180040000000000000000;
|
|
stack_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h000001FFFFC0180040000000000000000;
|
|
stack_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h000001FFFFC0180040000000000000000;
|
|
stack_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h000001FFFFC0180040000000000000000;
|
|
stack_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h000001FFFFC0180040000000000000000;
|
|
stack_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h000001FFFFC0180040000000000000000;
|
|
stack_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h000001FFFFC0180040000000000000000;
|
|
end
|
|
else
|
|
begin
|
|
if (head_rl$EN) head_rl <= `BSV_ASSIGNMENT_DELAY head_rl$D_IN;
|
|
if (stack_0_rl$EN)
|
|
stack_0_rl <= `BSV_ASSIGNMENT_DELAY stack_0_rl$D_IN;
|
|
if (stack_1_rl$EN)
|
|
stack_1_rl <= `BSV_ASSIGNMENT_DELAY stack_1_rl$D_IN;
|
|
if (stack_2_rl$EN)
|
|
stack_2_rl <= `BSV_ASSIGNMENT_DELAY stack_2_rl$D_IN;
|
|
if (stack_3_rl$EN)
|
|
stack_3_rl <= `BSV_ASSIGNMENT_DELAY stack_3_rl$D_IN;
|
|
if (stack_4_rl$EN)
|
|
stack_4_rl <= `BSV_ASSIGNMENT_DELAY stack_4_rl$D_IN;
|
|
if (stack_5_rl$EN)
|
|
stack_5_rl <= `BSV_ASSIGNMENT_DELAY stack_5_rl$D_IN;
|
|
if (stack_6_rl$EN)
|
|
stack_6_rl <= `BSV_ASSIGNMENT_DELAY stack_6_rl$D_IN;
|
|
if (stack_7_rl$EN)
|
|
stack_7_rl <= `BSV_ASSIGNMENT_DELAY stack_7_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
head_rl = 3'h2;
|
|
stack_0_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
stack_1_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
stack_2_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
stack_3_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
stack_4_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
stack_5_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
stack_6_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
stack_7_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkRas
|
|
|