11251 lines
421 KiB
Verilog
11251 lines
421 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:32:08 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// canEnq O 1
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// RDY_canEnq O 1 const
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// RDY_setRobEnqTime O 1 const
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// dispatchData O 155
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// RDY_dispatchData O 1
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// RDY_doDispatch O 1
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// RDY_setRegReady_0_put O 1 const
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// RDY_setRegReady_1_put O 1 const
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// RDY_setRegReady_2_put O 1 const
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// RDY_setRegReady_3_put O 1 const
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// RDY_setRegReady_4_put O 1 const
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// approximateCount O 5 reg
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// RDY_approximateCount O 1 const
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// isFull_ehrPort0 O 1
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// RDY_isFull_ehrPort0 O 1 const
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 155
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// setRobEnqTime_t I 6
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// setRegReady_0_put I 8
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// setRegReady_1_put I 8
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// setRegReady_2_put I 8
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// setRegReady_3_put I 8
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// setRegReady_4_put I 8
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_setRobEnqTime I 1
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// EN_doDispatch I 1
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// EN_setRegReady_0_put I 1
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// EN_setRegReady_1_put I 1
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// EN_setRegReady_2_put I 1
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// EN_setRegReady_3_put I 1
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// EN_setRegReady_4_put I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// Combinational paths from inputs to outputs:
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// (setRobEnqTime_t, EN_setRobEnqTime) -> dispatchData
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// (setRobEnqTime_t, EN_setRobEnqTime) -> RDY_dispatchData
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// (setRobEnqTime_t, EN_setRobEnqTime) -> RDY_doDispatch
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkReservationStationMem(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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canEnq,
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RDY_canEnq,
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setRobEnqTime_t,
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EN_setRobEnqTime,
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RDY_setRobEnqTime,
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dispatchData,
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RDY_dispatchData,
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EN_doDispatch,
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RDY_doDispatch,
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setRegReady_0_put,
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EN_setRegReady_0_put,
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RDY_setRegReady_0_put,
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setRegReady_1_put,
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EN_setRegReady_1_put,
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RDY_setRegReady_1_put,
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setRegReady_2_put,
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EN_setRegReady_2_put,
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RDY_setRegReady_2_put,
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setRegReady_3_put,
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EN_setRegReady_3_put,
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RDY_setRegReady_3_put,
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setRegReady_4_put,
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EN_setRegReady_4_put,
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RDY_setRegReady_4_put,
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approximateCount,
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RDY_approximateCount,
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isFull_ehrPort0,
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RDY_isFull_ehrPort0,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [154 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// value method canEnq
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output canEnq;
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output RDY_canEnq;
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// action method setRobEnqTime
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input [5 : 0] setRobEnqTime_t;
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input EN_setRobEnqTime;
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output RDY_setRobEnqTime;
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// value method dispatchData
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output [154 : 0] dispatchData;
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output RDY_dispatchData;
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// action method doDispatch
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input EN_doDispatch;
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output RDY_doDispatch;
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// action method setRegReady_0_put
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input [7 : 0] setRegReady_0_put;
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input EN_setRegReady_0_put;
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output RDY_setRegReady_0_put;
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// action method setRegReady_1_put
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input [7 : 0] setRegReady_1_put;
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input EN_setRegReady_1_put;
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output RDY_setRegReady_1_put;
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// action method setRegReady_2_put
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input [7 : 0] setRegReady_2_put;
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input EN_setRegReady_2_put;
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output RDY_setRegReady_2_put;
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// action method setRegReady_3_put
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input [7 : 0] setRegReady_3_put;
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input EN_setRegReady_3_put;
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output RDY_setRegReady_3_put;
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// action method setRegReady_4_put
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input [7 : 0] setRegReady_4_put;
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input EN_setRegReady_4_put;
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output RDY_setRegReady_4_put;
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// value method approximateCount
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output [4 : 0] approximateCount;
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output RDY_approximateCount;
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// value method isFull_ehrPort0
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output isFull_ehrPort0;
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output RDY_isFull_ehrPort0;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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reg RDY_doDispatch;
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wire [154 : 0] dispatchData;
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wire [4 : 0] approximateCount;
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wire RDY_approximateCount,
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RDY_canEnq,
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RDY_dispatchData,
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RDY_enq,
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RDY_isFull_ehrPort0,
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RDY_setRegReady_0_put,
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RDY_setRegReady_1_put,
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RDY_setRegReady_2_put,
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RDY_setRegReady_3_put,
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RDY_setRegReady_4_put,
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RDY_setRobEnqTime,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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canEnq,
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isFull_ehrPort0;
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// inlined wires
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wire [4 : 0] m_enqP_wire$wget;
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wire [3 : 0] m_regs_ready_0_lat_0$wget,
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m_regs_ready_0_lat_1$wget,
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m_regs_ready_0_lat_2$wget,
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m_regs_ready_0_lat_3$wget,
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m_regs_ready_0_lat_4$wget,
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m_regs_ready_10_lat_0$wget,
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m_regs_ready_10_lat_1$wget,
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m_regs_ready_10_lat_2$wget,
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m_regs_ready_10_lat_3$wget,
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m_regs_ready_10_lat_4$wget,
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m_regs_ready_11_lat_0$wget,
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m_regs_ready_11_lat_1$wget,
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m_regs_ready_11_lat_2$wget,
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m_regs_ready_11_lat_3$wget,
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m_regs_ready_11_lat_4$wget,
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m_regs_ready_12_lat_0$wget,
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m_regs_ready_12_lat_1$wget,
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m_regs_ready_12_lat_2$wget,
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m_regs_ready_12_lat_3$wget,
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m_regs_ready_12_lat_4$wget,
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m_regs_ready_13_lat_0$wget,
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m_regs_ready_13_lat_1$wget,
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m_regs_ready_13_lat_2$wget,
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m_regs_ready_13_lat_3$wget,
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m_regs_ready_13_lat_4$wget,
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m_regs_ready_14_lat_0$wget,
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m_regs_ready_14_lat_1$wget,
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m_regs_ready_14_lat_2$wget,
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m_regs_ready_14_lat_3$wget,
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m_regs_ready_14_lat_4$wget,
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m_regs_ready_15_lat_0$wget,
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m_regs_ready_15_lat_1$wget,
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m_regs_ready_15_lat_2$wget,
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m_regs_ready_15_lat_3$wget,
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m_regs_ready_15_lat_4$wget,
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m_regs_ready_1_lat_0$wget,
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m_regs_ready_1_lat_1$wget,
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m_regs_ready_1_lat_2$wget,
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m_regs_ready_1_lat_3$wget,
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m_regs_ready_1_lat_4$wget,
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m_regs_ready_2_lat_0$wget,
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m_regs_ready_2_lat_1$wget,
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m_regs_ready_2_lat_2$wget,
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m_regs_ready_2_lat_3$wget,
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m_regs_ready_2_lat_4$wget,
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m_regs_ready_3_lat_0$wget,
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m_regs_ready_3_lat_1$wget,
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m_regs_ready_3_lat_2$wget,
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m_regs_ready_3_lat_3$wget,
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m_regs_ready_3_lat_4$wget,
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m_regs_ready_4_lat_0$wget,
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m_regs_ready_4_lat_1$wget,
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m_regs_ready_4_lat_2$wget,
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m_regs_ready_4_lat_3$wget,
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m_regs_ready_4_lat_4$wget,
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m_regs_ready_5_lat_0$wget,
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m_regs_ready_5_lat_1$wget,
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m_regs_ready_5_lat_2$wget,
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m_regs_ready_5_lat_3$wget,
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m_regs_ready_5_lat_4$wget,
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m_regs_ready_6_lat_0$wget,
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m_regs_ready_6_lat_1$wget,
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m_regs_ready_6_lat_2$wget,
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m_regs_ready_6_lat_3$wget,
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m_regs_ready_6_lat_4$wget,
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m_regs_ready_7_lat_0$wget,
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m_regs_ready_7_lat_1$wget,
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m_regs_ready_7_lat_2$wget,
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m_regs_ready_7_lat_3$wget,
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m_regs_ready_7_lat_4$wget,
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m_regs_ready_8_lat_0$wget,
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m_regs_ready_8_lat_1$wget,
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m_regs_ready_8_lat_2$wget,
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m_regs_ready_8_lat_3$wget,
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m_regs_ready_8_lat_4$wget,
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m_regs_ready_9_lat_0$wget,
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m_regs_ready_9_lat_1$wget,
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m_regs_ready_9_lat_2$wget,
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m_regs_ready_9_lat_3$wget,
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m_regs_ready_9_lat_4$wget;
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wire m_ready_wire_0$wget,
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m_ready_wire_1$wget,
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m_ready_wire_10$wget,
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m_ready_wire_11$wget,
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m_ready_wire_12$wget,
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m_ready_wire_13$wget,
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m_ready_wire_14$wget,
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m_ready_wire_15$wget,
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m_ready_wire_2$wget,
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m_ready_wire_3$wget,
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m_ready_wire_4$wget,
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m_ready_wire_5$wget,
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m_ready_wire_6$wget,
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m_ready_wire_7$wget,
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m_ready_wire_8$wget,
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m_ready_wire_9$wget,
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m_valid_0_lat_0$whas,
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m_valid_0_lat_1$whas,
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m_valid_10_lat_0$whas,
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m_valid_10_lat_1$whas,
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m_valid_11_lat_0$whas,
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m_valid_11_lat_1$whas,
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m_valid_12_lat_0$whas,
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m_valid_12_lat_1$whas,
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m_valid_13_lat_0$whas,
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m_valid_13_lat_1$whas,
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m_valid_14_lat_0$whas,
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m_valid_14_lat_1$whas,
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m_valid_15_lat_0$whas,
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m_valid_15_lat_1$whas,
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m_valid_1_lat_0$whas,
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m_valid_1_lat_1$whas,
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m_valid_2_lat_0$whas,
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m_valid_2_lat_1$whas,
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m_valid_3_lat_0$whas,
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m_valid_3_lat_1$whas,
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m_valid_4_lat_0$whas,
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m_valid_4_lat_1$whas,
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m_valid_5_lat_0$whas,
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m_valid_5_lat_1$whas,
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m_valid_6_lat_0$whas,
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m_valid_6_lat_1$whas,
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m_valid_7_lat_0$whas,
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m_valid_7_lat_1$whas,
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m_valid_8_lat_0$whas,
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m_valid_8_lat_1$whas,
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m_valid_9_lat_0$whas,
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m_valid_9_lat_1$whas;
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// register m_data_0
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reg [88 : 0] m_data_0;
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wire [88 : 0] m_data_0$D_IN;
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wire m_data_0$EN;
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// register m_data_1
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reg [88 : 0] m_data_1;
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wire [88 : 0] m_data_1$D_IN;
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wire m_data_1$EN;
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// register m_data_10
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reg [88 : 0] m_data_10;
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wire [88 : 0] m_data_10$D_IN;
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wire m_data_10$EN;
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// register m_data_11
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reg [88 : 0] m_data_11;
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wire [88 : 0] m_data_11$D_IN;
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wire m_data_11$EN;
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// register m_data_12
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reg [88 : 0] m_data_12;
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wire [88 : 0] m_data_12$D_IN;
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wire m_data_12$EN;
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// register m_data_13
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reg [88 : 0] m_data_13;
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wire [88 : 0] m_data_13$D_IN;
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wire m_data_13$EN;
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// register m_data_14
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reg [88 : 0] m_data_14;
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wire [88 : 0] m_data_14$D_IN;
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wire m_data_14$EN;
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// register m_data_15
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reg [88 : 0] m_data_15;
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wire [88 : 0] m_data_15$D_IN;
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wire m_data_15$EN;
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// register m_data_2
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reg [88 : 0] m_data_2;
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wire [88 : 0] m_data_2$D_IN;
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wire m_data_2$EN;
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// register m_data_3
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reg [88 : 0] m_data_3;
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wire [88 : 0] m_data_3$D_IN;
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wire m_data_3$EN;
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// register m_data_4
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reg [88 : 0] m_data_4;
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wire [88 : 0] m_data_4$D_IN;
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wire m_data_4$EN;
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// register m_data_5
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reg [88 : 0] m_data_5;
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wire [88 : 0] m_data_5$D_IN;
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wire m_data_5$EN;
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// register m_data_6
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reg [88 : 0] m_data_6;
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wire [88 : 0] m_data_6$D_IN;
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wire m_data_6$EN;
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// register m_data_7
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reg [88 : 0] m_data_7;
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wire [88 : 0] m_data_7$D_IN;
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wire m_data_7$EN;
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// register m_data_8
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reg [88 : 0] m_data_8;
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wire [88 : 0] m_data_8$D_IN;
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wire m_data_8$EN;
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// register m_data_9
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reg [88 : 0] m_data_9;
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wire [88 : 0] m_data_9$D_IN;
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wire m_data_9$EN;
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// register m_regs_0
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reg [32 : 0] m_regs_0;
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wire [32 : 0] m_regs_0$D_IN;
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wire m_regs_0$EN;
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// register m_regs_1
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reg [32 : 0] m_regs_1;
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wire [32 : 0] m_regs_1$D_IN;
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wire m_regs_1$EN;
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// register m_regs_10
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reg [32 : 0] m_regs_10;
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wire [32 : 0] m_regs_10$D_IN;
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wire m_regs_10$EN;
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// register m_regs_11
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reg [32 : 0] m_regs_11;
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wire [32 : 0] m_regs_11$D_IN;
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wire m_regs_11$EN;
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// register m_regs_12
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reg [32 : 0] m_regs_12;
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wire [32 : 0] m_regs_12$D_IN;
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wire m_regs_12$EN;
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// register m_regs_13
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reg [32 : 0] m_regs_13;
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wire [32 : 0] m_regs_13$D_IN;
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wire m_regs_13$EN;
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// register m_regs_14
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reg [32 : 0] m_regs_14;
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wire [32 : 0] m_regs_14$D_IN;
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wire m_regs_14$EN;
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// register m_regs_15
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reg [32 : 0] m_regs_15;
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wire [32 : 0] m_regs_15$D_IN;
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wire m_regs_15$EN;
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// register m_regs_2
|
|
reg [32 : 0] m_regs_2;
|
|
wire [32 : 0] m_regs_2$D_IN;
|
|
wire m_regs_2$EN;
|
|
|
|
// register m_regs_3
|
|
reg [32 : 0] m_regs_3;
|
|
wire [32 : 0] m_regs_3$D_IN;
|
|
wire m_regs_3$EN;
|
|
|
|
// register m_regs_4
|
|
reg [32 : 0] m_regs_4;
|
|
wire [32 : 0] m_regs_4$D_IN;
|
|
wire m_regs_4$EN;
|
|
|
|
// register m_regs_5
|
|
reg [32 : 0] m_regs_5;
|
|
wire [32 : 0] m_regs_5$D_IN;
|
|
wire m_regs_5$EN;
|
|
|
|
// register m_regs_6
|
|
reg [32 : 0] m_regs_6;
|
|
wire [32 : 0] m_regs_6$D_IN;
|
|
wire m_regs_6$EN;
|
|
|
|
// register m_regs_7
|
|
reg [32 : 0] m_regs_7;
|
|
wire [32 : 0] m_regs_7$D_IN;
|
|
wire m_regs_7$EN;
|
|
|
|
// register m_regs_8
|
|
reg [32 : 0] m_regs_8;
|
|
wire [32 : 0] m_regs_8$D_IN;
|
|
wire m_regs_8$EN;
|
|
|
|
// register m_regs_9
|
|
reg [32 : 0] m_regs_9;
|
|
wire [32 : 0] m_regs_9$D_IN;
|
|
wire m_regs_9$EN;
|
|
|
|
// register m_regs_ready_0_rl
|
|
reg [3 : 0] m_regs_ready_0_rl;
|
|
wire [3 : 0] m_regs_ready_0_rl$D_IN;
|
|
wire m_regs_ready_0_rl$EN;
|
|
|
|
// register m_regs_ready_10_rl
|
|
reg [3 : 0] m_regs_ready_10_rl;
|
|
wire [3 : 0] m_regs_ready_10_rl$D_IN;
|
|
wire m_regs_ready_10_rl$EN;
|
|
|
|
// register m_regs_ready_11_rl
|
|
reg [3 : 0] m_regs_ready_11_rl;
|
|
wire [3 : 0] m_regs_ready_11_rl$D_IN;
|
|
wire m_regs_ready_11_rl$EN;
|
|
|
|
// register m_regs_ready_12_rl
|
|
reg [3 : 0] m_regs_ready_12_rl;
|
|
wire [3 : 0] m_regs_ready_12_rl$D_IN;
|
|
wire m_regs_ready_12_rl$EN;
|
|
|
|
// register m_regs_ready_13_rl
|
|
reg [3 : 0] m_regs_ready_13_rl;
|
|
wire [3 : 0] m_regs_ready_13_rl$D_IN;
|
|
wire m_regs_ready_13_rl$EN;
|
|
|
|
// register m_regs_ready_14_rl
|
|
reg [3 : 0] m_regs_ready_14_rl;
|
|
wire [3 : 0] m_regs_ready_14_rl$D_IN;
|
|
wire m_regs_ready_14_rl$EN;
|
|
|
|
// register m_regs_ready_15_rl
|
|
reg [3 : 0] m_regs_ready_15_rl;
|
|
wire [3 : 0] m_regs_ready_15_rl$D_IN;
|
|
wire m_regs_ready_15_rl$EN;
|
|
|
|
// register m_regs_ready_1_rl
|
|
reg [3 : 0] m_regs_ready_1_rl;
|
|
wire [3 : 0] m_regs_ready_1_rl$D_IN;
|
|
wire m_regs_ready_1_rl$EN;
|
|
|
|
// register m_regs_ready_2_rl
|
|
reg [3 : 0] m_regs_ready_2_rl;
|
|
wire [3 : 0] m_regs_ready_2_rl$D_IN;
|
|
wire m_regs_ready_2_rl$EN;
|
|
|
|
// register m_regs_ready_3_rl
|
|
reg [3 : 0] m_regs_ready_3_rl;
|
|
wire [3 : 0] m_regs_ready_3_rl$D_IN;
|
|
wire m_regs_ready_3_rl$EN;
|
|
|
|
// register m_regs_ready_4_rl
|
|
reg [3 : 0] m_regs_ready_4_rl;
|
|
wire [3 : 0] m_regs_ready_4_rl$D_IN;
|
|
wire m_regs_ready_4_rl$EN;
|
|
|
|
// register m_regs_ready_5_rl
|
|
reg [3 : 0] m_regs_ready_5_rl;
|
|
wire [3 : 0] m_regs_ready_5_rl$D_IN;
|
|
wire m_regs_ready_5_rl$EN;
|
|
|
|
// register m_regs_ready_6_rl
|
|
reg [3 : 0] m_regs_ready_6_rl;
|
|
wire [3 : 0] m_regs_ready_6_rl$D_IN;
|
|
wire m_regs_ready_6_rl$EN;
|
|
|
|
// register m_regs_ready_7_rl
|
|
reg [3 : 0] m_regs_ready_7_rl;
|
|
wire [3 : 0] m_regs_ready_7_rl$D_IN;
|
|
wire m_regs_ready_7_rl$EN;
|
|
|
|
// register m_regs_ready_8_rl
|
|
reg [3 : 0] m_regs_ready_8_rl;
|
|
wire [3 : 0] m_regs_ready_8_rl$D_IN;
|
|
wire m_regs_ready_8_rl$EN;
|
|
|
|
// register m_regs_ready_9_rl
|
|
reg [3 : 0] m_regs_ready_9_rl;
|
|
wire [3 : 0] m_regs_ready_9_rl$D_IN;
|
|
wire m_regs_ready_9_rl$EN;
|
|
|
|
// register m_spec_bits_0_rl
|
|
reg [11 : 0] m_spec_bits_0_rl;
|
|
wire [11 : 0] m_spec_bits_0_rl$D_IN;
|
|
wire m_spec_bits_0_rl$EN;
|
|
|
|
// register m_spec_bits_10_rl
|
|
reg [11 : 0] m_spec_bits_10_rl;
|
|
wire [11 : 0] m_spec_bits_10_rl$D_IN;
|
|
wire m_spec_bits_10_rl$EN;
|
|
|
|
// register m_spec_bits_11_rl
|
|
reg [11 : 0] m_spec_bits_11_rl;
|
|
wire [11 : 0] m_spec_bits_11_rl$D_IN;
|
|
wire m_spec_bits_11_rl$EN;
|
|
|
|
// register m_spec_bits_12_rl
|
|
reg [11 : 0] m_spec_bits_12_rl;
|
|
wire [11 : 0] m_spec_bits_12_rl$D_IN;
|
|
wire m_spec_bits_12_rl$EN;
|
|
|
|
// register m_spec_bits_13_rl
|
|
reg [11 : 0] m_spec_bits_13_rl;
|
|
wire [11 : 0] m_spec_bits_13_rl$D_IN;
|
|
wire m_spec_bits_13_rl$EN;
|
|
|
|
// register m_spec_bits_14_rl
|
|
reg [11 : 0] m_spec_bits_14_rl;
|
|
wire [11 : 0] m_spec_bits_14_rl$D_IN;
|
|
wire m_spec_bits_14_rl$EN;
|
|
|
|
// register m_spec_bits_15_rl
|
|
reg [11 : 0] m_spec_bits_15_rl;
|
|
wire [11 : 0] m_spec_bits_15_rl$D_IN;
|
|
wire m_spec_bits_15_rl$EN;
|
|
|
|
// register m_spec_bits_1_rl
|
|
reg [11 : 0] m_spec_bits_1_rl;
|
|
wire [11 : 0] m_spec_bits_1_rl$D_IN;
|
|
wire m_spec_bits_1_rl$EN;
|
|
|
|
// register m_spec_bits_2_rl
|
|
reg [11 : 0] m_spec_bits_2_rl;
|
|
wire [11 : 0] m_spec_bits_2_rl$D_IN;
|
|
wire m_spec_bits_2_rl$EN;
|
|
|
|
// register m_spec_bits_3_rl
|
|
reg [11 : 0] m_spec_bits_3_rl;
|
|
wire [11 : 0] m_spec_bits_3_rl$D_IN;
|
|
wire m_spec_bits_3_rl$EN;
|
|
|
|
// register m_spec_bits_4_rl
|
|
reg [11 : 0] m_spec_bits_4_rl;
|
|
wire [11 : 0] m_spec_bits_4_rl$D_IN;
|
|
wire m_spec_bits_4_rl$EN;
|
|
|
|
// register m_spec_bits_5_rl
|
|
reg [11 : 0] m_spec_bits_5_rl;
|
|
wire [11 : 0] m_spec_bits_5_rl$D_IN;
|
|
wire m_spec_bits_5_rl$EN;
|
|
|
|
// register m_spec_bits_6_rl
|
|
reg [11 : 0] m_spec_bits_6_rl;
|
|
wire [11 : 0] m_spec_bits_6_rl$D_IN;
|
|
wire m_spec_bits_6_rl$EN;
|
|
|
|
// register m_spec_bits_7_rl
|
|
reg [11 : 0] m_spec_bits_7_rl;
|
|
wire [11 : 0] m_spec_bits_7_rl$D_IN;
|
|
wire m_spec_bits_7_rl$EN;
|
|
|
|
// register m_spec_bits_8_rl
|
|
reg [11 : 0] m_spec_bits_8_rl;
|
|
wire [11 : 0] m_spec_bits_8_rl$D_IN;
|
|
wire m_spec_bits_8_rl$EN;
|
|
|
|
// register m_spec_bits_9_rl
|
|
reg [11 : 0] m_spec_bits_9_rl;
|
|
wire [11 : 0] m_spec_bits_9_rl$D_IN;
|
|
wire m_spec_bits_9_rl$EN;
|
|
|
|
// register m_spec_tag_0
|
|
reg [4 : 0] m_spec_tag_0;
|
|
wire [4 : 0] m_spec_tag_0$D_IN;
|
|
wire m_spec_tag_0$EN;
|
|
|
|
// register m_spec_tag_1
|
|
reg [4 : 0] m_spec_tag_1;
|
|
wire [4 : 0] m_spec_tag_1$D_IN;
|
|
wire m_spec_tag_1$EN;
|
|
|
|
// register m_spec_tag_10
|
|
reg [4 : 0] m_spec_tag_10;
|
|
wire [4 : 0] m_spec_tag_10$D_IN;
|
|
wire m_spec_tag_10$EN;
|
|
|
|
// register m_spec_tag_11
|
|
reg [4 : 0] m_spec_tag_11;
|
|
wire [4 : 0] m_spec_tag_11$D_IN;
|
|
wire m_spec_tag_11$EN;
|
|
|
|
// register m_spec_tag_12
|
|
reg [4 : 0] m_spec_tag_12;
|
|
wire [4 : 0] m_spec_tag_12$D_IN;
|
|
wire m_spec_tag_12$EN;
|
|
|
|
// register m_spec_tag_13
|
|
reg [4 : 0] m_spec_tag_13;
|
|
wire [4 : 0] m_spec_tag_13$D_IN;
|
|
wire m_spec_tag_13$EN;
|
|
|
|
// register m_spec_tag_14
|
|
reg [4 : 0] m_spec_tag_14;
|
|
wire [4 : 0] m_spec_tag_14$D_IN;
|
|
wire m_spec_tag_14$EN;
|
|
|
|
// register m_spec_tag_15
|
|
reg [4 : 0] m_spec_tag_15;
|
|
wire [4 : 0] m_spec_tag_15$D_IN;
|
|
wire m_spec_tag_15$EN;
|
|
|
|
// register m_spec_tag_2
|
|
reg [4 : 0] m_spec_tag_2;
|
|
wire [4 : 0] m_spec_tag_2$D_IN;
|
|
wire m_spec_tag_2$EN;
|
|
|
|
// register m_spec_tag_3
|
|
reg [4 : 0] m_spec_tag_3;
|
|
wire [4 : 0] m_spec_tag_3$D_IN;
|
|
wire m_spec_tag_3$EN;
|
|
|
|
// register m_spec_tag_4
|
|
reg [4 : 0] m_spec_tag_4;
|
|
wire [4 : 0] m_spec_tag_4$D_IN;
|
|
wire m_spec_tag_4$EN;
|
|
|
|
// register m_spec_tag_5
|
|
reg [4 : 0] m_spec_tag_5;
|
|
wire [4 : 0] m_spec_tag_5$D_IN;
|
|
wire m_spec_tag_5$EN;
|
|
|
|
// register m_spec_tag_6
|
|
reg [4 : 0] m_spec_tag_6;
|
|
wire [4 : 0] m_spec_tag_6$D_IN;
|
|
wire m_spec_tag_6$EN;
|
|
|
|
// register m_spec_tag_7
|
|
reg [4 : 0] m_spec_tag_7;
|
|
wire [4 : 0] m_spec_tag_7$D_IN;
|
|
wire m_spec_tag_7$EN;
|
|
|
|
// register m_spec_tag_8
|
|
reg [4 : 0] m_spec_tag_8;
|
|
wire [4 : 0] m_spec_tag_8$D_IN;
|
|
wire m_spec_tag_8$EN;
|
|
|
|
// register m_spec_tag_9
|
|
reg [4 : 0] m_spec_tag_9;
|
|
wire [4 : 0] m_spec_tag_9$D_IN;
|
|
wire m_spec_tag_9$EN;
|
|
|
|
// register m_tag_0
|
|
reg [11 : 0] m_tag_0;
|
|
wire [11 : 0] m_tag_0$D_IN;
|
|
wire m_tag_0$EN;
|
|
|
|
// register m_tag_1
|
|
reg [11 : 0] m_tag_1;
|
|
wire [11 : 0] m_tag_1$D_IN;
|
|
wire m_tag_1$EN;
|
|
|
|
// register m_tag_10
|
|
reg [11 : 0] m_tag_10;
|
|
wire [11 : 0] m_tag_10$D_IN;
|
|
wire m_tag_10$EN;
|
|
|
|
// register m_tag_11
|
|
reg [11 : 0] m_tag_11;
|
|
wire [11 : 0] m_tag_11$D_IN;
|
|
wire m_tag_11$EN;
|
|
|
|
// register m_tag_12
|
|
reg [11 : 0] m_tag_12;
|
|
wire [11 : 0] m_tag_12$D_IN;
|
|
wire m_tag_12$EN;
|
|
|
|
// register m_tag_13
|
|
reg [11 : 0] m_tag_13;
|
|
wire [11 : 0] m_tag_13$D_IN;
|
|
wire m_tag_13$EN;
|
|
|
|
// register m_tag_14
|
|
reg [11 : 0] m_tag_14;
|
|
wire [11 : 0] m_tag_14$D_IN;
|
|
wire m_tag_14$EN;
|
|
|
|
// register m_tag_15
|
|
reg [11 : 0] m_tag_15;
|
|
wire [11 : 0] m_tag_15$D_IN;
|
|
wire m_tag_15$EN;
|
|
|
|
// register m_tag_2
|
|
reg [11 : 0] m_tag_2;
|
|
wire [11 : 0] m_tag_2$D_IN;
|
|
wire m_tag_2$EN;
|
|
|
|
// register m_tag_3
|
|
reg [11 : 0] m_tag_3;
|
|
wire [11 : 0] m_tag_3$D_IN;
|
|
wire m_tag_3$EN;
|
|
|
|
// register m_tag_4
|
|
reg [11 : 0] m_tag_4;
|
|
wire [11 : 0] m_tag_4$D_IN;
|
|
wire m_tag_4$EN;
|
|
|
|
// register m_tag_5
|
|
reg [11 : 0] m_tag_5;
|
|
wire [11 : 0] m_tag_5$D_IN;
|
|
wire m_tag_5$EN;
|
|
|
|
// register m_tag_6
|
|
reg [11 : 0] m_tag_6;
|
|
wire [11 : 0] m_tag_6$D_IN;
|
|
wire m_tag_6$EN;
|
|
|
|
// register m_tag_7
|
|
reg [11 : 0] m_tag_7;
|
|
wire [11 : 0] m_tag_7$D_IN;
|
|
wire m_tag_7$EN;
|
|
|
|
// register m_tag_8
|
|
reg [11 : 0] m_tag_8;
|
|
wire [11 : 0] m_tag_8$D_IN;
|
|
wire m_tag_8$EN;
|
|
|
|
// register m_tag_9
|
|
reg [11 : 0] m_tag_9;
|
|
wire [11 : 0] m_tag_9$D_IN;
|
|
wire m_tag_9$EN;
|
|
|
|
// register m_validEntryCount
|
|
reg [4 : 0] m_validEntryCount;
|
|
wire [4 : 0] m_validEntryCount$D_IN;
|
|
wire m_validEntryCount$EN;
|
|
|
|
// register m_valid_0_rl
|
|
reg m_valid_0_rl;
|
|
wire m_valid_0_rl$D_IN, m_valid_0_rl$EN;
|
|
|
|
// register m_valid_10_rl
|
|
reg m_valid_10_rl;
|
|
wire m_valid_10_rl$D_IN, m_valid_10_rl$EN;
|
|
|
|
// register m_valid_11_rl
|
|
reg m_valid_11_rl;
|
|
wire m_valid_11_rl$D_IN, m_valid_11_rl$EN;
|
|
|
|
// register m_valid_12_rl
|
|
reg m_valid_12_rl;
|
|
wire m_valid_12_rl$D_IN, m_valid_12_rl$EN;
|
|
|
|
// register m_valid_13_rl
|
|
reg m_valid_13_rl;
|
|
wire m_valid_13_rl$D_IN, m_valid_13_rl$EN;
|
|
|
|
// register m_valid_14_rl
|
|
reg m_valid_14_rl;
|
|
wire m_valid_14_rl$D_IN, m_valid_14_rl$EN;
|
|
|
|
// register m_valid_15_rl
|
|
reg m_valid_15_rl;
|
|
wire m_valid_15_rl$D_IN, m_valid_15_rl$EN;
|
|
|
|
// register m_valid_1_rl
|
|
reg m_valid_1_rl;
|
|
wire m_valid_1_rl$D_IN, m_valid_1_rl$EN;
|
|
|
|
// register m_valid_2_rl
|
|
reg m_valid_2_rl;
|
|
wire m_valid_2_rl$D_IN, m_valid_2_rl$EN;
|
|
|
|
// register m_valid_3_rl
|
|
reg m_valid_3_rl;
|
|
wire m_valid_3_rl$D_IN, m_valid_3_rl$EN;
|
|
|
|
// register m_valid_4_rl
|
|
reg m_valid_4_rl;
|
|
wire m_valid_4_rl$D_IN, m_valid_4_rl$EN;
|
|
|
|
// register m_valid_5_rl
|
|
reg m_valid_5_rl;
|
|
wire m_valid_5_rl$D_IN, m_valid_5_rl$EN;
|
|
|
|
// register m_valid_6_rl
|
|
reg m_valid_6_rl;
|
|
wire m_valid_6_rl$D_IN, m_valid_6_rl$EN;
|
|
|
|
// register m_valid_7_rl
|
|
reg m_valid_7_rl;
|
|
wire m_valid_7_rl$D_IN, m_valid_7_rl$EN;
|
|
|
|
// register m_valid_8_rl
|
|
reg m_valid_8_rl;
|
|
wire m_valid_8_rl$D_IN, m_valid_8_rl$EN;
|
|
|
|
// register m_valid_9_rl
|
|
reg m_valid_9_rl;
|
|
wire m_valid_9_rl$D_IN, m_valid_9_rl$EN;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_regs_ready_0_canon,
|
|
CAN_FIRE_RL_m_regs_ready_10_canon,
|
|
CAN_FIRE_RL_m_regs_ready_11_canon,
|
|
CAN_FIRE_RL_m_regs_ready_12_canon,
|
|
CAN_FIRE_RL_m_regs_ready_13_canon,
|
|
CAN_FIRE_RL_m_regs_ready_14_canon,
|
|
CAN_FIRE_RL_m_regs_ready_15_canon,
|
|
CAN_FIRE_RL_m_regs_ready_1_canon,
|
|
CAN_FIRE_RL_m_regs_ready_2_canon,
|
|
CAN_FIRE_RL_m_regs_ready_3_canon,
|
|
CAN_FIRE_RL_m_regs_ready_4_canon,
|
|
CAN_FIRE_RL_m_regs_ready_5_canon,
|
|
CAN_FIRE_RL_m_regs_ready_6_canon,
|
|
CAN_FIRE_RL_m_regs_ready_7_canon,
|
|
CAN_FIRE_RL_m_regs_ready_8_canon,
|
|
CAN_FIRE_RL_m_regs_ready_9_canon,
|
|
CAN_FIRE_RL_m_setReadyWire,
|
|
CAN_FIRE_RL_m_setWireForEnq,
|
|
CAN_FIRE_RL_m_spec_bits_0_canon,
|
|
CAN_FIRE_RL_m_spec_bits_10_canon,
|
|
CAN_FIRE_RL_m_spec_bits_11_canon,
|
|
CAN_FIRE_RL_m_spec_bits_12_canon,
|
|
CAN_FIRE_RL_m_spec_bits_13_canon,
|
|
CAN_FIRE_RL_m_spec_bits_14_canon,
|
|
CAN_FIRE_RL_m_spec_bits_15_canon,
|
|
CAN_FIRE_RL_m_spec_bits_1_canon,
|
|
CAN_FIRE_RL_m_spec_bits_2_canon,
|
|
CAN_FIRE_RL_m_spec_bits_3_canon,
|
|
CAN_FIRE_RL_m_spec_bits_4_canon,
|
|
CAN_FIRE_RL_m_spec_bits_5_canon,
|
|
CAN_FIRE_RL_m_spec_bits_6_canon,
|
|
CAN_FIRE_RL_m_spec_bits_7_canon,
|
|
CAN_FIRE_RL_m_spec_bits_8_canon,
|
|
CAN_FIRE_RL_m_spec_bits_9_canon,
|
|
CAN_FIRE_RL_m_valid_0_canon,
|
|
CAN_FIRE_RL_m_valid_10_canon,
|
|
CAN_FIRE_RL_m_valid_11_canon,
|
|
CAN_FIRE_RL_m_valid_12_canon,
|
|
CAN_FIRE_RL_m_valid_13_canon,
|
|
CAN_FIRE_RL_m_valid_14_canon,
|
|
CAN_FIRE_RL_m_valid_15_canon,
|
|
CAN_FIRE_RL_m_valid_1_canon,
|
|
CAN_FIRE_RL_m_valid_2_canon,
|
|
CAN_FIRE_RL_m_valid_3_canon,
|
|
CAN_FIRE_RL_m_valid_4_canon,
|
|
CAN_FIRE_RL_m_valid_5_canon,
|
|
CAN_FIRE_RL_m_valid_6_canon,
|
|
CAN_FIRE_RL_m_valid_7_canon,
|
|
CAN_FIRE_RL_m_valid_8_canon,
|
|
CAN_FIRE_RL_m_valid_9_canon,
|
|
CAN_FIRE_doDispatch,
|
|
CAN_FIRE_enq,
|
|
CAN_FIRE_setRegReady_0_put,
|
|
CAN_FIRE_setRegReady_1_put,
|
|
CAN_FIRE_setRegReady_2_put,
|
|
CAN_FIRE_setRegReady_3_put,
|
|
CAN_FIRE_setRegReady_4_put,
|
|
CAN_FIRE_setRobEnqTime,
|
|
CAN_FIRE_specUpdate_correctSpeculation,
|
|
CAN_FIRE_specUpdate_incorrectSpeculation,
|
|
WILL_FIRE_RL_m_regs_ready_0_canon,
|
|
WILL_FIRE_RL_m_regs_ready_10_canon,
|
|
WILL_FIRE_RL_m_regs_ready_11_canon,
|
|
WILL_FIRE_RL_m_regs_ready_12_canon,
|
|
WILL_FIRE_RL_m_regs_ready_13_canon,
|
|
WILL_FIRE_RL_m_regs_ready_14_canon,
|
|
WILL_FIRE_RL_m_regs_ready_15_canon,
|
|
WILL_FIRE_RL_m_regs_ready_1_canon,
|
|
WILL_FIRE_RL_m_regs_ready_2_canon,
|
|
WILL_FIRE_RL_m_regs_ready_3_canon,
|
|
WILL_FIRE_RL_m_regs_ready_4_canon,
|
|
WILL_FIRE_RL_m_regs_ready_5_canon,
|
|
WILL_FIRE_RL_m_regs_ready_6_canon,
|
|
WILL_FIRE_RL_m_regs_ready_7_canon,
|
|
WILL_FIRE_RL_m_regs_ready_8_canon,
|
|
WILL_FIRE_RL_m_regs_ready_9_canon,
|
|
WILL_FIRE_RL_m_setReadyWire,
|
|
WILL_FIRE_RL_m_setWireForEnq,
|
|
WILL_FIRE_RL_m_spec_bits_0_canon,
|
|
WILL_FIRE_RL_m_spec_bits_10_canon,
|
|
WILL_FIRE_RL_m_spec_bits_11_canon,
|
|
WILL_FIRE_RL_m_spec_bits_12_canon,
|
|
WILL_FIRE_RL_m_spec_bits_13_canon,
|
|
WILL_FIRE_RL_m_spec_bits_14_canon,
|
|
WILL_FIRE_RL_m_spec_bits_15_canon,
|
|
WILL_FIRE_RL_m_spec_bits_1_canon,
|
|
WILL_FIRE_RL_m_spec_bits_2_canon,
|
|
WILL_FIRE_RL_m_spec_bits_3_canon,
|
|
WILL_FIRE_RL_m_spec_bits_4_canon,
|
|
WILL_FIRE_RL_m_spec_bits_5_canon,
|
|
WILL_FIRE_RL_m_spec_bits_6_canon,
|
|
WILL_FIRE_RL_m_spec_bits_7_canon,
|
|
WILL_FIRE_RL_m_spec_bits_8_canon,
|
|
WILL_FIRE_RL_m_spec_bits_9_canon,
|
|
WILL_FIRE_RL_m_valid_0_canon,
|
|
WILL_FIRE_RL_m_valid_10_canon,
|
|
WILL_FIRE_RL_m_valid_11_canon,
|
|
WILL_FIRE_RL_m_valid_12_canon,
|
|
WILL_FIRE_RL_m_valid_13_canon,
|
|
WILL_FIRE_RL_m_valid_14_canon,
|
|
WILL_FIRE_RL_m_valid_15_canon,
|
|
WILL_FIRE_RL_m_valid_1_canon,
|
|
WILL_FIRE_RL_m_valid_2_canon,
|
|
WILL_FIRE_RL_m_valid_3_canon,
|
|
WILL_FIRE_RL_m_valid_4_canon,
|
|
WILL_FIRE_RL_m_valid_5_canon,
|
|
WILL_FIRE_RL_m_valid_6_canon,
|
|
WILL_FIRE_RL_m_valid_7_canon,
|
|
WILL_FIRE_RL_m_valid_8_canon,
|
|
WILL_FIRE_RL_m_valid_9_canon,
|
|
WILL_FIRE_doDispatch,
|
|
WILL_FIRE_enq,
|
|
WILL_FIRE_setRegReady_0_put,
|
|
WILL_FIRE_setRegReady_1_put,
|
|
WILL_FIRE_setRegReady_2_put,
|
|
WILL_FIRE_setRegReady_3_put,
|
|
WILL_FIRE_setRegReady_4_put,
|
|
WILL_FIRE_setRobEnqTime,
|
|
WILL_FIRE_specUpdate_correctSpeculation,
|
|
WILL_FIRE_specUpdate_incorrectSpeculation;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire MUX_m_valid_0_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_10_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_11_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_12_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_13_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_14_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_15_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_1_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_2_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_3_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_4_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_5_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_6_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_7_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_8_lat_0$wset_1__SEL_2,
|
|
MUX_m_valid_9_lat_0$wset_1__SEL_2;
|
|
|
|
// remaining internal signals
|
|
reg [31 : 0] SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034;
|
|
reg [11 : 0] SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014;
|
|
reg [6 : 0] SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996,
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997,
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897,
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842,
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788,
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951;
|
|
reg [5 : 0] SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011,
|
|
x__h62947,
|
|
x__h62980;
|
|
reg [4 : 0] SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087,
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009;
|
|
reg [3 : 0] SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105,
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083;
|
|
reg [2 : 0] SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630,
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612,
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016;
|
|
reg [1 : 0] SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594;
|
|
reg SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068,
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878,
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823,
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769,
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932,
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990,
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995,
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717,
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648,
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576,
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558,
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540,
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522,
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504,
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486,
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468,
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450,
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432,
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414,
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396,
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378,
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360,
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342,
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324,
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306,
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288,
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270,
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252,
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234,
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216,
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198,
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180,
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162,
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144,
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126,
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969,
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991;
|
|
wire [11 : 0] n__read__h100114,
|
|
n__read__h100243,
|
|
n__read__h100372,
|
|
n__read__h100501,
|
|
n__read__h100630,
|
|
n__read__h100759,
|
|
n__read__h100888,
|
|
n__read__h101017,
|
|
n__read__h101134,
|
|
n__read__h99211,
|
|
n__read__h99340,
|
|
n__read__h99469,
|
|
n__read__h99598,
|
|
n__read__h99727,
|
|
n__read__h99856,
|
|
n__read__h99985,
|
|
upd__h11253,
|
|
upd__h11598,
|
|
upd__h11943,
|
|
upd__h12288,
|
|
upd__h12633,
|
|
upd__h12978,
|
|
upd__h13323,
|
|
upd__h13668,
|
|
upd__h14013,
|
|
upd__h14358,
|
|
upd__h14703,
|
|
upd__h15048,
|
|
upd__h15393,
|
|
upd__h15738,
|
|
upd__h16083,
|
|
upd__h16428;
|
|
wire [6 : 0] IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836,
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906,
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912,
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918,
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924,
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930,
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936,
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842,
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853,
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859,
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870,
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876,
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882,
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888,
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894,
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
wire [5 : 0] NOT_SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_ETC___d1108,
|
|
x__read__h33622;
|
|
wire [3 : 0] IF_NOT_m_valid_11_rl_2_60_OR_NOT_m_ready_wire__ETC___d976,
|
|
IF_NOT_m_valid_13_rl_6_64_OR_NOT_m_ready_wire__ETC___d988,
|
|
IF_NOT_m_valid_15_rl_10_67_OR_NOT_m_ready_wire_ETC___d993,
|
|
IF_NOT_m_valid_1_rl_2_42_OR_NOT_m_ready_wire_1_ETC___d845,
|
|
IF_NOT_m_valid_3_rl_6_45_OR_NOT_m_ready_wire_3_ETC___d862,
|
|
IF_NOT_m_valid_5_rl_0_49_OR_NOT_m_ready_wire_5_ETC___d947,
|
|
IF_NOT_m_valid_7_rl_4_52_OR_NOT_m_ready_wire_7_ETC___d952,
|
|
IF_NOT_m_valid_9_rl_8_57_OR_NOT_m_ready_wire_9_ETC___d971,
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1000,
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1007,
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1014,
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d942,
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d959,
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d966,
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d983,
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d239,
|
|
IF_m_regs_ready_0_lat_3_whas__29_THEN_m_regs_r_ETC___d241,
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d429,
|
|
IF_m_regs_ready_10_lat_3_whas__19_THEN_m_regs__ETC___d431,
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d448,
|
|
IF_m_regs_ready_11_lat_3_whas__38_THEN_m_regs__ETC___d450,
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d467,
|
|
IF_m_regs_ready_12_lat_3_whas__57_THEN_m_regs__ETC___d469,
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d486,
|
|
IF_m_regs_ready_13_lat_3_whas__76_THEN_m_regs__ETC___d488,
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d505,
|
|
IF_m_regs_ready_14_lat_3_whas__95_THEN_m_regs__ETC___d507,
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d524,
|
|
IF_m_regs_ready_15_lat_3_whas__14_THEN_m_regs__ETC___d526,
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d258,
|
|
IF_m_regs_ready_1_lat_3_whas__48_THEN_m_regs_r_ETC___d260,
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d277,
|
|
IF_m_regs_ready_2_lat_3_whas__67_THEN_m_regs_r_ETC___d279,
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d296,
|
|
IF_m_regs_ready_3_lat_3_whas__86_THEN_m_regs_r_ETC___d298,
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d315,
|
|
IF_m_regs_ready_4_lat_3_whas__05_THEN_m_regs_r_ETC___d317,
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d334,
|
|
IF_m_regs_ready_5_lat_3_whas__24_THEN_m_regs_r_ETC___d336,
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d353,
|
|
IF_m_regs_ready_6_lat_3_whas__43_THEN_m_regs_r_ETC___d355,
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d372,
|
|
IF_m_regs_ready_7_lat_3_whas__62_THEN_m_regs_r_ETC___d374,
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d391,
|
|
IF_m_regs_ready_8_lat_3_whas__81_THEN_m_regs_r_ETC___d393,
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d410,
|
|
IF_m_regs_ready_9_lat_3_whas__00_THEN_m_regs_r_ETC___d412,
|
|
IF_m_valid_0_rl_AND_m_valid_1_rl_2_72_AND_m_va_ETC___d700,
|
|
IF_m_valid_0_rl_AND_m_valid_1_rl_2_72_THEN_IF__ETC___d699,
|
|
IF_m_valid_12_rl_9_AND_m_valid_13_rl_6_82_THEN_ETC___d689,
|
|
IF_m_valid_4_rl_3_AND_m_valid_5_rl_0_75_THEN_I_ETC___d696,
|
|
IF_m_valid_8_rl_1_AND_m_valid_9_rl_8_79_AND_m__ETC___d693,
|
|
IF_m_valid_8_rl_1_AND_m_valid_9_rl_8_79_THEN_I_ETC___d692,
|
|
a__h54195,
|
|
a__h54213,
|
|
a__h54225,
|
|
a__h58090,
|
|
a__h58594,
|
|
a__h58606,
|
|
a__h58999,
|
|
b__h54196,
|
|
b__h54214,
|
|
b__h54226,
|
|
b__h58091,
|
|
b__h58595,
|
|
b__h58607,
|
|
b__h59000,
|
|
idx__h53445;
|
|
wire [1 : 0] NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3826,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3854,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3882,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3910,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3938,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3966,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3994,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4022,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4050,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4078,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4106,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4134,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4162,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4190,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4218,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4246;
|
|
wire IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2453,
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2461,
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2469,
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2472,
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2904,
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2912,
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2920,
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2923,
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3355,
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3363,
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3371,
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3374,
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2733,
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2741,
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2749,
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2752,
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3184,
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3192,
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3200,
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3203,
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3635,
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3643,
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3651,
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3654,
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2761,
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2769,
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2777,
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2780,
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3212,
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3220,
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3228,
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3231,
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3663,
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3671,
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3679,
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3682,
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2789,
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2797,
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2805,
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2808,
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3240,
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3248,
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3256,
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3259,
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3691,
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3699,
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3707,
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3710,
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2817,
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2825,
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2833,
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2836,
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3268,
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3276,
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3284,
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3287,
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3719,
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3727,
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3735,
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3738,
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2845,
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2853,
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2861,
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2864,
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3296,
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3304,
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3312,
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3315,
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3747,
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3755,
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3763,
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3766,
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2873,
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2881,
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2889,
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2892,
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3324,
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3332,
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3340,
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3343,
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3775,
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3783,
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3791,
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3794,
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2481,
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2489,
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2497,
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2500,
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2932,
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2940,
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2948,
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2951,
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3383,
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3391,
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3399,
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3402,
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2509,
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2517,
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2525,
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2528,
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2960,
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2968,
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2976,
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2979,
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3411,
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3419,
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3427,
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3430,
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2537,
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2545,
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2553,
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2556,
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d2988,
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d2996,
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d3004,
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d3007,
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3439,
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3447,
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3455,
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3458,
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2565,
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2573,
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2581,
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2584,
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3016,
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3024,
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3032,
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3035,
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3467,
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3475,
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3483,
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3486,
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2593,
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2601,
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2609,
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2612,
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3044,
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3052,
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3060,
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3063,
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3495,
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3503,
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3511,
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3514,
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2621,
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2629,
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2637,
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2640,
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3072,
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3080,
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3088,
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3091,
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3523,
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3531,
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3539,
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3542,
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2649,
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2657,
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2665,
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2668,
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3100,
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3108,
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3116,
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3119,
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3551,
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3559,
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3567,
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3570,
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2677,
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2685,
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2693,
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2696,
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3128,
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3136,
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3144,
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3147,
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3579,
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3587,
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3595,
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3598,
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2705,
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2713,
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2721,
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2724,
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3156,
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3164,
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3172,
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3175,
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3607,
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3615,
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3623,
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3626,
|
|
NOT_m_valid_0_rl_41_OR_NOT_m_valid_1_rl_2_42_4_ETC___d655,
|
|
NOT_m_valid_8_rl_1_56_OR_NOT_m_valid_9_rl_8_57_ETC___d670,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3807,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3815,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3823,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3835,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3843,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3851,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3863,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3871,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3879,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3891,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3899,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3907,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3919,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3927,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3935,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3947,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3955,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3963,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3975,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3983,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3991,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4003,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4011,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4019,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4031,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4039,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4047,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4059,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4067,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4075,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4087,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4095,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4103,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4115,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4123,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4131,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4143,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4151,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4159,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4171,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4179,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4187,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4199,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4207,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4215,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4227,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4235,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4243,
|
|
m_valid_0_rl_AND_m_valid_1_rl_2_72_AND_m_valid_ETC___d678,
|
|
m_valid_3_rl_6_AND_m_valid_4_rl_3_AND_m_valid__ETC___d4258,
|
|
m_valid_9_rl_8_AND_m_valid_10_rl_5_AND_m_valid_ETC___d4252;
|
|
|
|
// action method enq
|
|
assign RDY_enq = m_enqP_wire$wget[4] ;
|
|
assign CAN_FIRE_enq = m_enqP_wire$wget[4] ;
|
|
assign WILL_FIRE_enq = EN_enq ;
|
|
|
|
// value method canEnq
|
|
assign canEnq = m_enqP_wire$wget[4] ;
|
|
assign RDY_canEnq = 1'd1 ;
|
|
|
|
// action method setRobEnqTime
|
|
assign RDY_setRobEnqTime = 1'd1 ;
|
|
assign CAN_FIRE_setRobEnqTime = 1'd1 ;
|
|
assign WILL_FIRE_setRobEnqTime = EN_setRobEnqTime ;
|
|
|
|
// value method dispatchData
|
|
assign dispatchData =
|
|
{ SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016,
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034,
|
|
NOT_SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_ETC___d1108,
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126,
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144,
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162,
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180,
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198,
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216,
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234,
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252,
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270,
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288,
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306,
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324,
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342,
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360,
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378,
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396,
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414,
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432,
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450,
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468,
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486,
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504,
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522,
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540,
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558,
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576,
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594,
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612,
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630,
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648,
|
|
x__h62947,
|
|
x__h62980,
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717,
|
|
!SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769,
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788,
|
|
!SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823,
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842,
|
|
!SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878,
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897,
|
|
!SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932,
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951,
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969,
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991,
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009,
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011,
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014,
|
|
!SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064,
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083,
|
|
4'd15 } ;
|
|
assign RDY_dispatchData = RDY_doDispatch ;
|
|
|
|
// action method doDispatch
|
|
always@(idx__h53445 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0: RDY_doDispatch = m_valid_0_rl && m_ready_wire_0$wget;
|
|
4'd1: RDY_doDispatch = m_valid_1_rl && m_ready_wire_1$wget;
|
|
4'd2: RDY_doDispatch = m_valid_2_rl && m_ready_wire_2$wget;
|
|
4'd3: RDY_doDispatch = m_valid_3_rl && m_ready_wire_3$wget;
|
|
4'd4: RDY_doDispatch = m_valid_4_rl && m_ready_wire_4$wget;
|
|
4'd5: RDY_doDispatch = m_valid_5_rl && m_ready_wire_5$wget;
|
|
4'd6: RDY_doDispatch = m_valid_6_rl && m_ready_wire_6$wget;
|
|
4'd7: RDY_doDispatch = m_valid_7_rl && m_ready_wire_7$wget;
|
|
4'd8: RDY_doDispatch = m_valid_8_rl && m_ready_wire_8$wget;
|
|
4'd9: RDY_doDispatch = m_valid_9_rl && m_ready_wire_9$wget;
|
|
4'd10: RDY_doDispatch = m_valid_10_rl && m_ready_wire_10$wget;
|
|
4'd11: RDY_doDispatch = m_valid_11_rl && m_ready_wire_11$wget;
|
|
4'd12: RDY_doDispatch = m_valid_12_rl && m_ready_wire_12$wget;
|
|
4'd13: RDY_doDispatch = m_valid_13_rl && m_ready_wire_13$wget;
|
|
4'd14: RDY_doDispatch = m_valid_14_rl && m_ready_wire_14$wget;
|
|
4'd15: RDY_doDispatch = m_valid_15_rl && m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
assign CAN_FIRE_doDispatch = RDY_doDispatch ;
|
|
assign WILL_FIRE_doDispatch = EN_doDispatch ;
|
|
|
|
// action method setRegReady_0_put
|
|
assign RDY_setRegReady_0_put = 1'd1 ;
|
|
assign CAN_FIRE_setRegReady_0_put = 1'd1 ;
|
|
assign WILL_FIRE_setRegReady_0_put = EN_setRegReady_0_put ;
|
|
|
|
// action method setRegReady_1_put
|
|
assign RDY_setRegReady_1_put = 1'd1 ;
|
|
assign CAN_FIRE_setRegReady_1_put = 1'd1 ;
|
|
assign WILL_FIRE_setRegReady_1_put = EN_setRegReady_1_put ;
|
|
|
|
// action method setRegReady_2_put
|
|
assign RDY_setRegReady_2_put = 1'd1 ;
|
|
assign CAN_FIRE_setRegReady_2_put = 1'd1 ;
|
|
assign WILL_FIRE_setRegReady_2_put = EN_setRegReady_2_put ;
|
|
|
|
// action method setRegReady_3_put
|
|
assign RDY_setRegReady_3_put = 1'd1 ;
|
|
assign CAN_FIRE_setRegReady_3_put = 1'd1 ;
|
|
assign WILL_FIRE_setRegReady_3_put = EN_setRegReady_3_put ;
|
|
|
|
// action method setRegReady_4_put
|
|
assign RDY_setRegReady_4_put = 1'd1 ;
|
|
assign CAN_FIRE_setRegReady_4_put = 1'd1 ;
|
|
assign WILL_FIRE_setRegReady_4_put = EN_setRegReady_4_put ;
|
|
|
|
// value method approximateCount
|
|
assign approximateCount = m_validEntryCount ;
|
|
assign RDY_approximateCount = 1'd1 ;
|
|
|
|
// value method isFull_ehrPort0
|
|
assign isFull_ehrPort0 =
|
|
m_valid_0_rl && m_valid_1_rl && m_valid_2_rl &&
|
|
m_valid_3_rl_6_AND_m_valid_4_rl_3_AND_m_valid__ETC___d4258 ;
|
|
assign RDY_isFull_ehrPort0 = 1'd1 ;
|
|
|
|
// action method specUpdate_incorrectSpeculation
|
|
assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_specUpdate_incorrectSpeculation =
|
|
EN_specUpdate_incorrectSpeculation ;
|
|
|
|
// action method specUpdate_correctSpeculation
|
|
assign RDY_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_specUpdate_correctSpeculation =
|
|
EN_specUpdate_correctSpeculation ;
|
|
|
|
// rule RL_m_setReadyWire
|
|
assign CAN_FIRE_RL_m_setReadyWire = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_setReadyWire = 1'd1 ;
|
|
|
|
// rule RL_m_setWireForEnq
|
|
assign CAN_FIRE_RL_m_setWireForEnq = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_setWireForEnq = 1'd1 ;
|
|
|
|
// rule RL_m_valid_0_canon
|
|
assign CAN_FIRE_RL_m_valid_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_1_canon
|
|
assign CAN_FIRE_RL_m_valid_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_2_canon
|
|
assign CAN_FIRE_RL_m_valid_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_3_canon
|
|
assign CAN_FIRE_RL_m_valid_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_4_canon
|
|
assign CAN_FIRE_RL_m_valid_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_5_canon
|
|
assign CAN_FIRE_RL_m_valid_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_6_canon
|
|
assign CAN_FIRE_RL_m_valid_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_7_canon
|
|
assign CAN_FIRE_RL_m_valid_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_8_canon
|
|
assign CAN_FIRE_RL_m_valid_8_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_8_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_9_canon
|
|
assign CAN_FIRE_RL_m_valid_9_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_9_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_10_canon
|
|
assign CAN_FIRE_RL_m_valid_10_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_10_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_11_canon
|
|
assign CAN_FIRE_RL_m_valid_11_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_11_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_12_canon
|
|
assign CAN_FIRE_RL_m_valid_12_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_12_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_13_canon
|
|
assign CAN_FIRE_RL_m_valid_13_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_13_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_14_canon
|
|
assign CAN_FIRE_RL_m_valid_14_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_14_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_15_canon
|
|
assign CAN_FIRE_RL_m_valid_15_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_15_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_0_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_1_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_2_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_3_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_4_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_5_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_6_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_7_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_8_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_8_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_8_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_9_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_9_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_9_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_10_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_10_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_10_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_11_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_11_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_11_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_12_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_12_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_12_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_13_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_13_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_13_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_14_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_14_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_14_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_15_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_15_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_15_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_0_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_1_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_2_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_3_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_4_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_5_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_6_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_7_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_8_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_8_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_8_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_9_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_9_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_9_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_10_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_10_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_10_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_11_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_11_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_11_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_12_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_12_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_12_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_13_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_13_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_13_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_14_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_14_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_14_canon = 1'd1 ;
|
|
|
|
// rule RL_m_regs_ready_15_canon
|
|
assign CAN_FIRE_RL_m_regs_ready_15_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_regs_ready_15_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_valid_0_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_10_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_10_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_11_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_11_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_12_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_12_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_13_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_13_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_14_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_14_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_15_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_15_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_1_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_1_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_2_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_2_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_3_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_3_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_4_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_4_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_5_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_5_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_6_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_6_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_7_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_7_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_8_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_8_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_valid_9_lat_0$wset_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_spec_bits_9_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
|
|
// inlined wires
|
|
assign m_valid_0_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd0 ||
|
|
MUX_m_valid_0_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_0_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd0 ;
|
|
assign m_valid_1_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd1 ||
|
|
MUX_m_valid_1_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_1_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd1 ;
|
|
assign m_valid_2_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd2 ||
|
|
MUX_m_valid_2_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_2_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd2 ;
|
|
assign m_valid_3_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd3 ||
|
|
MUX_m_valid_3_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_3_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd3 ;
|
|
assign m_valid_4_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd4 ||
|
|
MUX_m_valid_4_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_4_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd4 ;
|
|
assign m_valid_5_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd5 ||
|
|
MUX_m_valid_5_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_5_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd5 ;
|
|
assign m_valid_6_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd6 ||
|
|
MUX_m_valid_6_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_6_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd6 ;
|
|
assign m_valid_7_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd7 ||
|
|
MUX_m_valid_7_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_7_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd7 ;
|
|
assign m_valid_8_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd8 ||
|
|
MUX_m_valid_8_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_8_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd8 ;
|
|
assign m_valid_9_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd9 ||
|
|
MUX_m_valid_9_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_9_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd9 ;
|
|
assign m_valid_10_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd10 ||
|
|
MUX_m_valid_10_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_10_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd10 ;
|
|
assign m_valid_11_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd11 ||
|
|
MUX_m_valid_11_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_11_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd11 ;
|
|
assign m_valid_12_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd12 ||
|
|
MUX_m_valid_12_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_12_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd12 ;
|
|
assign m_valid_13_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd13 ||
|
|
MUX_m_valid_13_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_13_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd13 ;
|
|
assign m_valid_14_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd14 ||
|
|
MUX_m_valid_14_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_14_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd14 ;
|
|
assign m_valid_15_lat_0$whas =
|
|
EN_doDispatch && idx__h53445 == 4'd15 ||
|
|
MUX_m_valid_15_lat_0$wset_1__SEL_2 ;
|
|
assign m_valid_15_lat_1$whas = EN_enq && m_enqP_wire$wget[3:0] == 4'd15 ;
|
|
assign m_regs_ready_0_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_0[32] ||
|
|
setRegReady_0_put[7] && m_regs_0[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_0[31:25] ||
|
|
m_regs_ready_0_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_0[24] ||
|
|
setRegReady_0_put[7] && m_regs_0[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_0[23:17] ||
|
|
m_regs_ready_0_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_0[16] ||
|
|
setRegReady_0_put[7] && m_regs_0[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_0[15:9] ||
|
|
m_regs_ready_0_rl[1],
|
|
m_regs_ready_0_rl[0] } ;
|
|
assign m_regs_ready_0_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_0[32] ||
|
|
setRegReady_1_put[7] && m_regs_0[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_0[31:25] ||
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2453,
|
|
!setRegReady_1_put[7] && !m_regs_0[24] ||
|
|
setRegReady_1_put[7] && m_regs_0[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_0[23:17] ||
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2461,
|
|
!setRegReady_1_put[7] && !m_regs_0[16] ||
|
|
setRegReady_1_put[7] && m_regs_0[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_0[15:9] ||
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2469,
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2472 } ;
|
|
assign m_regs_ready_0_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_0[32] ||
|
|
setRegReady_2_put[7] && m_regs_0[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_0[31:25] ||
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2904,
|
|
!setRegReady_2_put[7] && !m_regs_0[24] ||
|
|
setRegReady_2_put[7] && m_regs_0[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_0[23:17] ||
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2912,
|
|
!setRegReady_2_put[7] && !m_regs_0[16] ||
|
|
setRegReady_2_put[7] && m_regs_0[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_0[15:9] ||
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2920,
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2923 } ;
|
|
assign m_regs_ready_0_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_0[32] ||
|
|
setRegReady_3_put[7] && m_regs_0[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_0[31:25] ||
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3355,
|
|
!setRegReady_3_put[7] && !m_regs_0[24] ||
|
|
setRegReady_3_put[7] && m_regs_0[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_0[23:17] ||
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3363,
|
|
!setRegReady_3_put[7] && !m_regs_0[16] ||
|
|
setRegReady_3_put[7] && m_regs_0[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_0[15:9] ||
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3371,
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3374 } ;
|
|
assign m_regs_ready_0_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3807,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3815,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3826 } ;
|
|
assign m_regs_ready_1_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_1[32] ||
|
|
setRegReady_0_put[7] && m_regs_1[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_1[31:25] ||
|
|
m_regs_ready_1_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_1[24] ||
|
|
setRegReady_0_put[7] && m_regs_1[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_1[23:17] ||
|
|
m_regs_ready_1_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_1[16] ||
|
|
setRegReady_0_put[7] && m_regs_1[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_1[15:9] ||
|
|
m_regs_ready_1_rl[1],
|
|
m_regs_ready_1_rl[0] } ;
|
|
assign m_regs_ready_1_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_1[32] ||
|
|
setRegReady_1_put[7] && m_regs_1[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_1[31:25] ||
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2481,
|
|
!setRegReady_1_put[7] && !m_regs_1[24] ||
|
|
setRegReady_1_put[7] && m_regs_1[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_1[23:17] ||
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2489,
|
|
!setRegReady_1_put[7] && !m_regs_1[16] ||
|
|
setRegReady_1_put[7] && m_regs_1[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_1[15:9] ||
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2497,
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2500 } ;
|
|
assign m_regs_ready_1_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_1[32] ||
|
|
setRegReady_2_put[7] && m_regs_1[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_1[31:25] ||
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2932,
|
|
!setRegReady_2_put[7] && !m_regs_1[24] ||
|
|
setRegReady_2_put[7] && m_regs_1[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_1[23:17] ||
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2940,
|
|
!setRegReady_2_put[7] && !m_regs_1[16] ||
|
|
setRegReady_2_put[7] && m_regs_1[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_1[15:9] ||
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2948,
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2951 } ;
|
|
assign m_regs_ready_1_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_1[32] ||
|
|
setRegReady_3_put[7] && m_regs_1[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_1[31:25] ||
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3383,
|
|
!setRegReady_3_put[7] && !m_regs_1[24] ||
|
|
setRegReady_3_put[7] && m_regs_1[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_1[23:17] ||
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3391,
|
|
!setRegReady_3_put[7] && !m_regs_1[16] ||
|
|
setRegReady_3_put[7] && m_regs_1[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_1[15:9] ||
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3399,
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3402 } ;
|
|
assign m_regs_ready_1_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3835,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3843,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3854 } ;
|
|
assign m_regs_ready_2_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_2[32] ||
|
|
setRegReady_0_put[7] && m_regs_2[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_2[31:25] ||
|
|
m_regs_ready_2_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_2[24] ||
|
|
setRegReady_0_put[7] && m_regs_2[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_2[23:17] ||
|
|
m_regs_ready_2_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_2[16] ||
|
|
setRegReady_0_put[7] && m_regs_2[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_2[15:9] ||
|
|
m_regs_ready_2_rl[1],
|
|
m_regs_ready_2_rl[0] } ;
|
|
assign m_regs_ready_2_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_2[32] ||
|
|
setRegReady_1_put[7] && m_regs_2[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_2[31:25] ||
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2509,
|
|
!setRegReady_1_put[7] && !m_regs_2[24] ||
|
|
setRegReady_1_put[7] && m_regs_2[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_2[23:17] ||
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2517,
|
|
!setRegReady_1_put[7] && !m_regs_2[16] ||
|
|
setRegReady_1_put[7] && m_regs_2[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_2[15:9] ||
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2525,
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2528 } ;
|
|
assign m_regs_ready_2_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_2[32] ||
|
|
setRegReady_2_put[7] && m_regs_2[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_2[31:25] ||
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2960,
|
|
!setRegReady_2_put[7] && !m_regs_2[24] ||
|
|
setRegReady_2_put[7] && m_regs_2[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_2[23:17] ||
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2968,
|
|
!setRegReady_2_put[7] && !m_regs_2[16] ||
|
|
setRegReady_2_put[7] && m_regs_2[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_2[15:9] ||
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2976,
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2979 } ;
|
|
assign m_regs_ready_2_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_2[32] ||
|
|
setRegReady_3_put[7] && m_regs_2[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_2[31:25] ||
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3411,
|
|
!setRegReady_3_put[7] && !m_regs_2[24] ||
|
|
setRegReady_3_put[7] && m_regs_2[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_2[23:17] ||
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3419,
|
|
!setRegReady_3_put[7] && !m_regs_2[16] ||
|
|
setRegReady_3_put[7] && m_regs_2[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_2[15:9] ||
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3427,
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3430 } ;
|
|
assign m_regs_ready_2_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3863,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3871,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3882 } ;
|
|
assign m_regs_ready_3_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_3[32] ||
|
|
setRegReady_0_put[7] && m_regs_3[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_3[31:25] ||
|
|
m_regs_ready_3_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_3[24] ||
|
|
setRegReady_0_put[7] && m_regs_3[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_3[23:17] ||
|
|
m_regs_ready_3_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_3[16] ||
|
|
setRegReady_0_put[7] && m_regs_3[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_3[15:9] ||
|
|
m_regs_ready_3_rl[1],
|
|
m_regs_ready_3_rl[0] } ;
|
|
assign m_regs_ready_3_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_3[32] ||
|
|
setRegReady_1_put[7] && m_regs_3[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_3[31:25] ||
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2537,
|
|
!setRegReady_1_put[7] && !m_regs_3[24] ||
|
|
setRegReady_1_put[7] && m_regs_3[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_3[23:17] ||
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2545,
|
|
!setRegReady_1_put[7] && !m_regs_3[16] ||
|
|
setRegReady_1_put[7] && m_regs_3[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_3[15:9] ||
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2553,
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2556 } ;
|
|
assign m_regs_ready_3_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_3[32] ||
|
|
setRegReady_2_put[7] && m_regs_3[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_3[31:25] ||
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d2988,
|
|
!setRegReady_2_put[7] && !m_regs_3[24] ||
|
|
setRegReady_2_put[7] && m_regs_3[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_3[23:17] ||
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d2996,
|
|
!setRegReady_2_put[7] && !m_regs_3[16] ||
|
|
setRegReady_2_put[7] && m_regs_3[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_3[15:9] ||
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d3004,
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d3007 } ;
|
|
assign m_regs_ready_3_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_3[32] ||
|
|
setRegReady_3_put[7] && m_regs_3[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_3[31:25] ||
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3439,
|
|
!setRegReady_3_put[7] && !m_regs_3[24] ||
|
|
setRegReady_3_put[7] && m_regs_3[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_3[23:17] ||
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3447,
|
|
!setRegReady_3_put[7] && !m_regs_3[16] ||
|
|
setRegReady_3_put[7] && m_regs_3[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_3[15:9] ||
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3455,
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3458 } ;
|
|
assign m_regs_ready_3_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3891,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3899,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3910 } ;
|
|
assign m_regs_ready_4_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_4[32] ||
|
|
setRegReady_0_put[7] && m_regs_4[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_4[31:25] ||
|
|
m_regs_ready_4_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_4[24] ||
|
|
setRegReady_0_put[7] && m_regs_4[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_4[23:17] ||
|
|
m_regs_ready_4_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_4[16] ||
|
|
setRegReady_0_put[7] && m_regs_4[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_4[15:9] ||
|
|
m_regs_ready_4_rl[1],
|
|
m_regs_ready_4_rl[0] } ;
|
|
assign m_regs_ready_4_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_4[32] ||
|
|
setRegReady_1_put[7] && m_regs_4[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_4[31:25] ||
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2565,
|
|
!setRegReady_1_put[7] && !m_regs_4[24] ||
|
|
setRegReady_1_put[7] && m_regs_4[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_4[23:17] ||
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2573,
|
|
!setRegReady_1_put[7] && !m_regs_4[16] ||
|
|
setRegReady_1_put[7] && m_regs_4[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_4[15:9] ||
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2581,
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2584 } ;
|
|
assign m_regs_ready_4_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_4[32] ||
|
|
setRegReady_2_put[7] && m_regs_4[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_4[31:25] ||
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3016,
|
|
!setRegReady_2_put[7] && !m_regs_4[24] ||
|
|
setRegReady_2_put[7] && m_regs_4[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_4[23:17] ||
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3024,
|
|
!setRegReady_2_put[7] && !m_regs_4[16] ||
|
|
setRegReady_2_put[7] && m_regs_4[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_4[15:9] ||
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3032,
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3035 } ;
|
|
assign m_regs_ready_4_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_4[32] ||
|
|
setRegReady_3_put[7] && m_regs_4[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_4[31:25] ||
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3467,
|
|
!setRegReady_3_put[7] && !m_regs_4[24] ||
|
|
setRegReady_3_put[7] && m_regs_4[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_4[23:17] ||
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3475,
|
|
!setRegReady_3_put[7] && !m_regs_4[16] ||
|
|
setRegReady_3_put[7] && m_regs_4[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_4[15:9] ||
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3483,
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3486 } ;
|
|
assign m_regs_ready_4_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3919,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3927,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3938 } ;
|
|
assign m_regs_ready_5_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_5[32] ||
|
|
setRegReady_0_put[7] && m_regs_5[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_5[31:25] ||
|
|
m_regs_ready_5_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_5[24] ||
|
|
setRegReady_0_put[7] && m_regs_5[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_5[23:17] ||
|
|
m_regs_ready_5_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_5[16] ||
|
|
setRegReady_0_put[7] && m_regs_5[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_5[15:9] ||
|
|
m_regs_ready_5_rl[1],
|
|
m_regs_ready_5_rl[0] } ;
|
|
assign m_regs_ready_5_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_5[32] ||
|
|
setRegReady_1_put[7] && m_regs_5[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_5[31:25] ||
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2593,
|
|
!setRegReady_1_put[7] && !m_regs_5[24] ||
|
|
setRegReady_1_put[7] && m_regs_5[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_5[23:17] ||
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2601,
|
|
!setRegReady_1_put[7] && !m_regs_5[16] ||
|
|
setRegReady_1_put[7] && m_regs_5[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_5[15:9] ||
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2609,
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2612 } ;
|
|
assign m_regs_ready_5_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_5[32] ||
|
|
setRegReady_2_put[7] && m_regs_5[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_5[31:25] ||
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3044,
|
|
!setRegReady_2_put[7] && !m_regs_5[24] ||
|
|
setRegReady_2_put[7] && m_regs_5[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_5[23:17] ||
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3052,
|
|
!setRegReady_2_put[7] && !m_regs_5[16] ||
|
|
setRegReady_2_put[7] && m_regs_5[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_5[15:9] ||
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3060,
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3063 } ;
|
|
assign m_regs_ready_5_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_5[32] ||
|
|
setRegReady_3_put[7] && m_regs_5[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_5[31:25] ||
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3495,
|
|
!setRegReady_3_put[7] && !m_regs_5[24] ||
|
|
setRegReady_3_put[7] && m_regs_5[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_5[23:17] ||
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3503,
|
|
!setRegReady_3_put[7] && !m_regs_5[16] ||
|
|
setRegReady_3_put[7] && m_regs_5[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_5[15:9] ||
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3511,
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3514 } ;
|
|
assign m_regs_ready_5_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3947,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3955,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3966 } ;
|
|
assign m_regs_ready_6_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_6[32] ||
|
|
setRegReady_0_put[7] && m_regs_6[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_6[31:25] ||
|
|
m_regs_ready_6_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_6[24] ||
|
|
setRegReady_0_put[7] && m_regs_6[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_6[23:17] ||
|
|
m_regs_ready_6_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_6[16] ||
|
|
setRegReady_0_put[7] && m_regs_6[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_6[15:9] ||
|
|
m_regs_ready_6_rl[1],
|
|
m_regs_ready_6_rl[0] } ;
|
|
assign m_regs_ready_6_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_6[32] ||
|
|
setRegReady_1_put[7] && m_regs_6[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_6[31:25] ||
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2621,
|
|
!setRegReady_1_put[7] && !m_regs_6[24] ||
|
|
setRegReady_1_put[7] && m_regs_6[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_6[23:17] ||
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2629,
|
|
!setRegReady_1_put[7] && !m_regs_6[16] ||
|
|
setRegReady_1_put[7] && m_regs_6[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_6[15:9] ||
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2637,
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2640 } ;
|
|
assign m_regs_ready_6_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_6[32] ||
|
|
setRegReady_2_put[7] && m_regs_6[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_6[31:25] ||
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3072,
|
|
!setRegReady_2_put[7] && !m_regs_6[24] ||
|
|
setRegReady_2_put[7] && m_regs_6[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_6[23:17] ||
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3080,
|
|
!setRegReady_2_put[7] && !m_regs_6[16] ||
|
|
setRegReady_2_put[7] && m_regs_6[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_6[15:9] ||
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3088,
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3091 } ;
|
|
assign m_regs_ready_6_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_6[32] ||
|
|
setRegReady_3_put[7] && m_regs_6[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_6[31:25] ||
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3523,
|
|
!setRegReady_3_put[7] && !m_regs_6[24] ||
|
|
setRegReady_3_put[7] && m_regs_6[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_6[23:17] ||
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3531,
|
|
!setRegReady_3_put[7] && !m_regs_6[16] ||
|
|
setRegReady_3_put[7] && m_regs_6[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_6[15:9] ||
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3539,
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3542 } ;
|
|
assign m_regs_ready_6_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3975,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3983,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3994 } ;
|
|
assign m_regs_ready_7_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_7[32] ||
|
|
setRegReady_0_put[7] && m_regs_7[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_7[31:25] ||
|
|
m_regs_ready_7_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_7[24] ||
|
|
setRegReady_0_put[7] && m_regs_7[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_7[23:17] ||
|
|
m_regs_ready_7_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_7[16] ||
|
|
setRegReady_0_put[7] && m_regs_7[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_7[15:9] ||
|
|
m_regs_ready_7_rl[1],
|
|
m_regs_ready_7_rl[0] } ;
|
|
assign m_regs_ready_7_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_7[32] ||
|
|
setRegReady_1_put[7] && m_regs_7[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_7[31:25] ||
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2649,
|
|
!setRegReady_1_put[7] && !m_regs_7[24] ||
|
|
setRegReady_1_put[7] && m_regs_7[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_7[23:17] ||
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2657,
|
|
!setRegReady_1_put[7] && !m_regs_7[16] ||
|
|
setRegReady_1_put[7] && m_regs_7[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_7[15:9] ||
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2665,
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2668 } ;
|
|
assign m_regs_ready_7_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_7[32] ||
|
|
setRegReady_2_put[7] && m_regs_7[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_7[31:25] ||
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3100,
|
|
!setRegReady_2_put[7] && !m_regs_7[24] ||
|
|
setRegReady_2_put[7] && m_regs_7[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_7[23:17] ||
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3108,
|
|
!setRegReady_2_put[7] && !m_regs_7[16] ||
|
|
setRegReady_2_put[7] && m_regs_7[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_7[15:9] ||
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3116,
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3119 } ;
|
|
assign m_regs_ready_7_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_7[32] ||
|
|
setRegReady_3_put[7] && m_regs_7[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_7[31:25] ||
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3551,
|
|
!setRegReady_3_put[7] && !m_regs_7[24] ||
|
|
setRegReady_3_put[7] && m_regs_7[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_7[23:17] ||
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3559,
|
|
!setRegReady_3_put[7] && !m_regs_7[16] ||
|
|
setRegReady_3_put[7] && m_regs_7[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_7[15:9] ||
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3567,
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3570 } ;
|
|
assign m_regs_ready_7_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4003,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4011,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4022 } ;
|
|
assign m_regs_ready_8_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_8[32] ||
|
|
setRegReady_0_put[7] && m_regs_8[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_8[31:25] ||
|
|
m_regs_ready_8_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_8[24] ||
|
|
setRegReady_0_put[7] && m_regs_8[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_8[23:17] ||
|
|
m_regs_ready_8_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_8[16] ||
|
|
setRegReady_0_put[7] && m_regs_8[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_8[15:9] ||
|
|
m_regs_ready_8_rl[1],
|
|
m_regs_ready_8_rl[0] } ;
|
|
assign m_regs_ready_8_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_8[32] ||
|
|
setRegReady_1_put[7] && m_regs_8[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_8[31:25] ||
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2677,
|
|
!setRegReady_1_put[7] && !m_regs_8[24] ||
|
|
setRegReady_1_put[7] && m_regs_8[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_8[23:17] ||
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2685,
|
|
!setRegReady_1_put[7] && !m_regs_8[16] ||
|
|
setRegReady_1_put[7] && m_regs_8[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_8[15:9] ||
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2693,
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2696 } ;
|
|
assign m_regs_ready_8_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_8[32] ||
|
|
setRegReady_2_put[7] && m_regs_8[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_8[31:25] ||
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3128,
|
|
!setRegReady_2_put[7] && !m_regs_8[24] ||
|
|
setRegReady_2_put[7] && m_regs_8[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_8[23:17] ||
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3136,
|
|
!setRegReady_2_put[7] && !m_regs_8[16] ||
|
|
setRegReady_2_put[7] && m_regs_8[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_8[15:9] ||
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3144,
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3147 } ;
|
|
assign m_regs_ready_8_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_8[32] ||
|
|
setRegReady_3_put[7] && m_regs_8[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_8[31:25] ||
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3579,
|
|
!setRegReady_3_put[7] && !m_regs_8[24] ||
|
|
setRegReady_3_put[7] && m_regs_8[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_8[23:17] ||
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3587,
|
|
!setRegReady_3_put[7] && !m_regs_8[16] ||
|
|
setRegReady_3_put[7] && m_regs_8[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_8[15:9] ||
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3595,
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3598 } ;
|
|
assign m_regs_ready_8_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4031,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4039,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4050 } ;
|
|
assign m_regs_ready_9_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_9[32] ||
|
|
setRegReady_0_put[7] && m_regs_9[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_9[31:25] ||
|
|
m_regs_ready_9_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_9[24] ||
|
|
setRegReady_0_put[7] && m_regs_9[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_9[23:17] ||
|
|
m_regs_ready_9_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_9[16] ||
|
|
setRegReady_0_put[7] && m_regs_9[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_9[15:9] ||
|
|
m_regs_ready_9_rl[1],
|
|
m_regs_ready_9_rl[0] } ;
|
|
assign m_regs_ready_9_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_9[32] ||
|
|
setRegReady_1_put[7] && m_regs_9[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_9[31:25] ||
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2705,
|
|
!setRegReady_1_put[7] && !m_regs_9[24] ||
|
|
setRegReady_1_put[7] && m_regs_9[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_9[23:17] ||
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2713,
|
|
!setRegReady_1_put[7] && !m_regs_9[16] ||
|
|
setRegReady_1_put[7] && m_regs_9[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_9[15:9] ||
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2721,
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2724 } ;
|
|
assign m_regs_ready_9_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_9[32] ||
|
|
setRegReady_2_put[7] && m_regs_9[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_9[31:25] ||
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3156,
|
|
!setRegReady_2_put[7] && !m_regs_9[24] ||
|
|
setRegReady_2_put[7] && m_regs_9[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_9[23:17] ||
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3164,
|
|
!setRegReady_2_put[7] && !m_regs_9[16] ||
|
|
setRegReady_2_put[7] && m_regs_9[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_9[15:9] ||
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3172,
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3175 } ;
|
|
assign m_regs_ready_9_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_9[32] ||
|
|
setRegReady_3_put[7] && m_regs_9[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_9[31:25] ||
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3607,
|
|
!setRegReady_3_put[7] && !m_regs_9[24] ||
|
|
setRegReady_3_put[7] && m_regs_9[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_9[23:17] ||
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3615,
|
|
!setRegReady_3_put[7] && !m_regs_9[16] ||
|
|
setRegReady_3_put[7] && m_regs_9[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_9[15:9] ||
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3623,
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3626 } ;
|
|
assign m_regs_ready_9_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4059,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4067,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4078 } ;
|
|
assign m_regs_ready_10_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_10[32] ||
|
|
setRegReady_0_put[7] && m_regs_10[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_10[31:25] ||
|
|
m_regs_ready_10_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_10[24] ||
|
|
setRegReady_0_put[7] && m_regs_10[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_10[23:17] ||
|
|
m_regs_ready_10_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_10[16] ||
|
|
setRegReady_0_put[7] && m_regs_10[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_10[15:9] ||
|
|
m_regs_ready_10_rl[1],
|
|
m_regs_ready_10_rl[0] } ;
|
|
assign m_regs_ready_10_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_10[32] ||
|
|
setRegReady_1_put[7] && m_regs_10[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_10[31:25] ||
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2733,
|
|
!setRegReady_1_put[7] && !m_regs_10[24] ||
|
|
setRegReady_1_put[7] && m_regs_10[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_10[23:17] ||
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2741,
|
|
!setRegReady_1_put[7] && !m_regs_10[16] ||
|
|
setRegReady_1_put[7] && m_regs_10[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_10[15:9] ||
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2749,
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2752 } ;
|
|
assign m_regs_ready_10_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_10[32] ||
|
|
setRegReady_2_put[7] && m_regs_10[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_10[31:25] ||
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3184,
|
|
!setRegReady_2_put[7] && !m_regs_10[24] ||
|
|
setRegReady_2_put[7] && m_regs_10[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_10[23:17] ||
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3192,
|
|
!setRegReady_2_put[7] && !m_regs_10[16] ||
|
|
setRegReady_2_put[7] && m_regs_10[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_10[15:9] ||
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3200,
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3203 } ;
|
|
assign m_regs_ready_10_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_10[32] ||
|
|
setRegReady_3_put[7] && m_regs_10[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_10[31:25] ||
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3635,
|
|
!setRegReady_3_put[7] && !m_regs_10[24] ||
|
|
setRegReady_3_put[7] && m_regs_10[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_10[23:17] ||
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3643,
|
|
!setRegReady_3_put[7] && !m_regs_10[16] ||
|
|
setRegReady_3_put[7] && m_regs_10[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_10[15:9] ||
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3651,
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3654 } ;
|
|
assign m_regs_ready_10_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4087,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4095,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4106 } ;
|
|
assign m_regs_ready_11_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_11[32] ||
|
|
setRegReady_0_put[7] && m_regs_11[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_11[31:25] ||
|
|
m_regs_ready_11_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_11[24] ||
|
|
setRegReady_0_put[7] && m_regs_11[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_11[23:17] ||
|
|
m_regs_ready_11_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_11[16] ||
|
|
setRegReady_0_put[7] && m_regs_11[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_11[15:9] ||
|
|
m_regs_ready_11_rl[1],
|
|
m_regs_ready_11_rl[0] } ;
|
|
assign m_regs_ready_11_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_11[32] ||
|
|
setRegReady_1_put[7] && m_regs_11[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_11[31:25] ||
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2761,
|
|
!setRegReady_1_put[7] && !m_regs_11[24] ||
|
|
setRegReady_1_put[7] && m_regs_11[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_11[23:17] ||
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2769,
|
|
!setRegReady_1_put[7] && !m_regs_11[16] ||
|
|
setRegReady_1_put[7] && m_regs_11[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_11[15:9] ||
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2777,
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2780 } ;
|
|
assign m_regs_ready_11_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_11[32] ||
|
|
setRegReady_2_put[7] && m_regs_11[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_11[31:25] ||
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3212,
|
|
!setRegReady_2_put[7] && !m_regs_11[24] ||
|
|
setRegReady_2_put[7] && m_regs_11[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_11[23:17] ||
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3220,
|
|
!setRegReady_2_put[7] && !m_regs_11[16] ||
|
|
setRegReady_2_put[7] && m_regs_11[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_11[15:9] ||
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3228,
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3231 } ;
|
|
assign m_regs_ready_11_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_11[32] ||
|
|
setRegReady_3_put[7] && m_regs_11[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_11[31:25] ||
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3663,
|
|
!setRegReady_3_put[7] && !m_regs_11[24] ||
|
|
setRegReady_3_put[7] && m_regs_11[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_11[23:17] ||
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3671,
|
|
!setRegReady_3_put[7] && !m_regs_11[16] ||
|
|
setRegReady_3_put[7] && m_regs_11[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_11[15:9] ||
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3679,
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3682 } ;
|
|
assign m_regs_ready_11_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4115,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4123,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4134 } ;
|
|
assign m_regs_ready_12_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_12[32] ||
|
|
setRegReady_0_put[7] && m_regs_12[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_12[31:25] ||
|
|
m_regs_ready_12_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_12[24] ||
|
|
setRegReady_0_put[7] && m_regs_12[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_12[23:17] ||
|
|
m_regs_ready_12_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_12[16] ||
|
|
setRegReady_0_put[7] && m_regs_12[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_12[15:9] ||
|
|
m_regs_ready_12_rl[1],
|
|
m_regs_ready_12_rl[0] } ;
|
|
assign m_regs_ready_12_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_12[32] ||
|
|
setRegReady_1_put[7] && m_regs_12[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_12[31:25] ||
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2789,
|
|
!setRegReady_1_put[7] && !m_regs_12[24] ||
|
|
setRegReady_1_put[7] && m_regs_12[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_12[23:17] ||
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2797,
|
|
!setRegReady_1_put[7] && !m_regs_12[16] ||
|
|
setRegReady_1_put[7] && m_regs_12[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_12[15:9] ||
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2805,
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2808 } ;
|
|
assign m_regs_ready_12_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_12[32] ||
|
|
setRegReady_2_put[7] && m_regs_12[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_12[31:25] ||
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3240,
|
|
!setRegReady_2_put[7] && !m_regs_12[24] ||
|
|
setRegReady_2_put[7] && m_regs_12[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_12[23:17] ||
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3248,
|
|
!setRegReady_2_put[7] && !m_regs_12[16] ||
|
|
setRegReady_2_put[7] && m_regs_12[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_12[15:9] ||
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3256,
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3259 } ;
|
|
assign m_regs_ready_12_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_12[32] ||
|
|
setRegReady_3_put[7] && m_regs_12[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_12[31:25] ||
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3691,
|
|
!setRegReady_3_put[7] && !m_regs_12[24] ||
|
|
setRegReady_3_put[7] && m_regs_12[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_12[23:17] ||
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3699,
|
|
!setRegReady_3_put[7] && !m_regs_12[16] ||
|
|
setRegReady_3_put[7] && m_regs_12[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_12[15:9] ||
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3707,
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3710 } ;
|
|
assign m_regs_ready_12_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4143,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4151,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4162 } ;
|
|
assign m_regs_ready_13_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_13[32] ||
|
|
setRegReady_0_put[7] && m_regs_13[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_13[31:25] ||
|
|
m_regs_ready_13_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_13[24] ||
|
|
setRegReady_0_put[7] && m_regs_13[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_13[23:17] ||
|
|
m_regs_ready_13_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_13[16] ||
|
|
setRegReady_0_put[7] && m_regs_13[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_13[15:9] ||
|
|
m_regs_ready_13_rl[1],
|
|
m_regs_ready_13_rl[0] } ;
|
|
assign m_regs_ready_13_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_13[32] ||
|
|
setRegReady_1_put[7] && m_regs_13[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_13[31:25] ||
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2817,
|
|
!setRegReady_1_put[7] && !m_regs_13[24] ||
|
|
setRegReady_1_put[7] && m_regs_13[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_13[23:17] ||
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2825,
|
|
!setRegReady_1_put[7] && !m_regs_13[16] ||
|
|
setRegReady_1_put[7] && m_regs_13[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_13[15:9] ||
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2833,
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2836 } ;
|
|
assign m_regs_ready_13_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_13[32] ||
|
|
setRegReady_2_put[7] && m_regs_13[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_13[31:25] ||
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3268,
|
|
!setRegReady_2_put[7] && !m_regs_13[24] ||
|
|
setRegReady_2_put[7] && m_regs_13[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_13[23:17] ||
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3276,
|
|
!setRegReady_2_put[7] && !m_regs_13[16] ||
|
|
setRegReady_2_put[7] && m_regs_13[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_13[15:9] ||
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3284,
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3287 } ;
|
|
assign m_regs_ready_13_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_13[32] ||
|
|
setRegReady_3_put[7] && m_regs_13[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_13[31:25] ||
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3719,
|
|
!setRegReady_3_put[7] && !m_regs_13[24] ||
|
|
setRegReady_3_put[7] && m_regs_13[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_13[23:17] ||
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3727,
|
|
!setRegReady_3_put[7] && !m_regs_13[16] ||
|
|
setRegReady_3_put[7] && m_regs_13[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_13[15:9] ||
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3735,
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3738 } ;
|
|
assign m_regs_ready_13_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4171,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4179,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4190 } ;
|
|
assign m_regs_ready_14_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_14[32] ||
|
|
setRegReady_0_put[7] && m_regs_14[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_14[31:25] ||
|
|
m_regs_ready_14_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_14[24] ||
|
|
setRegReady_0_put[7] && m_regs_14[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_14[23:17] ||
|
|
m_regs_ready_14_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_14[16] ||
|
|
setRegReady_0_put[7] && m_regs_14[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_14[15:9] ||
|
|
m_regs_ready_14_rl[1],
|
|
m_regs_ready_14_rl[0] } ;
|
|
assign m_regs_ready_14_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_14[32] ||
|
|
setRegReady_1_put[7] && m_regs_14[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_14[31:25] ||
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2845,
|
|
!setRegReady_1_put[7] && !m_regs_14[24] ||
|
|
setRegReady_1_put[7] && m_regs_14[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_14[23:17] ||
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2853,
|
|
!setRegReady_1_put[7] && !m_regs_14[16] ||
|
|
setRegReady_1_put[7] && m_regs_14[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_14[15:9] ||
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2861,
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2864 } ;
|
|
assign m_regs_ready_14_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_14[32] ||
|
|
setRegReady_2_put[7] && m_regs_14[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_14[31:25] ||
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3296,
|
|
!setRegReady_2_put[7] && !m_regs_14[24] ||
|
|
setRegReady_2_put[7] && m_regs_14[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_14[23:17] ||
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3304,
|
|
!setRegReady_2_put[7] && !m_regs_14[16] ||
|
|
setRegReady_2_put[7] && m_regs_14[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_14[15:9] ||
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3312,
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3315 } ;
|
|
assign m_regs_ready_14_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_14[32] ||
|
|
setRegReady_3_put[7] && m_regs_14[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_14[31:25] ||
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3747,
|
|
!setRegReady_3_put[7] && !m_regs_14[24] ||
|
|
setRegReady_3_put[7] && m_regs_14[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_14[23:17] ||
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3755,
|
|
!setRegReady_3_put[7] && !m_regs_14[16] ||
|
|
setRegReady_3_put[7] && m_regs_14[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_14[15:9] ||
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3763,
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3766 } ;
|
|
assign m_regs_ready_14_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4199,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4207,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4218 } ;
|
|
assign m_regs_ready_15_lat_0$wget =
|
|
{ !setRegReady_0_put[7] && !m_regs_15[32] ||
|
|
setRegReady_0_put[7] && m_regs_15[32] &&
|
|
setRegReady_0_put[6:0] == m_regs_15[31:25] ||
|
|
m_regs_ready_15_rl[3],
|
|
!setRegReady_0_put[7] && !m_regs_15[24] ||
|
|
setRegReady_0_put[7] && m_regs_15[24] &&
|
|
setRegReady_0_put[6:0] == m_regs_15[23:17] ||
|
|
m_regs_ready_15_rl[2],
|
|
!setRegReady_0_put[7] && !m_regs_15[16] ||
|
|
setRegReady_0_put[7] && m_regs_15[16] &&
|
|
setRegReady_0_put[6:0] == m_regs_15[15:9] ||
|
|
m_regs_ready_15_rl[1],
|
|
m_regs_ready_15_rl[0] } ;
|
|
assign m_regs_ready_15_lat_1$wget =
|
|
{ !setRegReady_1_put[7] && !m_regs_15[32] ||
|
|
setRegReady_1_put[7] && m_regs_15[32] &&
|
|
setRegReady_1_put[6:0] == m_regs_15[31:25] ||
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2873,
|
|
!setRegReady_1_put[7] && !m_regs_15[24] ||
|
|
setRegReady_1_put[7] && m_regs_15[24] &&
|
|
setRegReady_1_put[6:0] == m_regs_15[23:17] ||
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2881,
|
|
!setRegReady_1_put[7] && !m_regs_15[16] ||
|
|
setRegReady_1_put[7] && m_regs_15[16] &&
|
|
setRegReady_1_put[6:0] == m_regs_15[15:9] ||
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2889,
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2892 } ;
|
|
assign m_regs_ready_15_lat_2$wget =
|
|
{ !setRegReady_2_put[7] && !m_regs_15[32] ||
|
|
setRegReady_2_put[7] && m_regs_15[32] &&
|
|
setRegReady_2_put[6:0] == m_regs_15[31:25] ||
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3324,
|
|
!setRegReady_2_put[7] && !m_regs_15[24] ||
|
|
setRegReady_2_put[7] && m_regs_15[24] &&
|
|
setRegReady_2_put[6:0] == m_regs_15[23:17] ||
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3332,
|
|
!setRegReady_2_put[7] && !m_regs_15[16] ||
|
|
setRegReady_2_put[7] && m_regs_15[16] &&
|
|
setRegReady_2_put[6:0] == m_regs_15[15:9] ||
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3340,
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3343 } ;
|
|
assign m_regs_ready_15_lat_3$wget =
|
|
{ !setRegReady_3_put[7] && !m_regs_15[32] ||
|
|
setRegReady_3_put[7] && m_regs_15[32] &&
|
|
setRegReady_3_put[6:0] == m_regs_15[31:25] ||
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3775,
|
|
!setRegReady_3_put[7] && !m_regs_15[24] ||
|
|
setRegReady_3_put[7] && m_regs_15[24] &&
|
|
setRegReady_3_put[6:0] == m_regs_15[23:17] ||
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3783,
|
|
!setRegReady_3_put[7] && !m_regs_15[16] ||
|
|
setRegReady_3_put[7] && m_regs_15[16] &&
|
|
setRegReady_3_put[6:0] == m_regs_15[15:9] ||
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3791,
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3794 } ;
|
|
assign m_regs_ready_15_lat_4$wget =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4227,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4235,
|
|
NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4246 } ;
|
|
assign m_ready_wire_0$wget =
|
|
m_regs_ready_0_rl[3] && m_regs_ready_0_rl[2] &&
|
|
m_regs_ready_0_rl[1] &&
|
|
m_regs_ready_0_rl[0] ;
|
|
assign m_ready_wire_1$wget =
|
|
m_regs_ready_1_rl[3] && m_regs_ready_1_rl[2] &&
|
|
m_regs_ready_1_rl[1] &&
|
|
m_regs_ready_1_rl[0] ;
|
|
assign m_ready_wire_2$wget =
|
|
m_regs_ready_2_rl[3] && m_regs_ready_2_rl[2] &&
|
|
m_regs_ready_2_rl[1] &&
|
|
m_regs_ready_2_rl[0] ;
|
|
assign m_ready_wire_3$wget =
|
|
m_regs_ready_3_rl[3] && m_regs_ready_3_rl[2] &&
|
|
m_regs_ready_3_rl[1] &&
|
|
m_regs_ready_3_rl[0] ;
|
|
assign m_ready_wire_4$wget =
|
|
m_regs_ready_4_rl[3] && m_regs_ready_4_rl[2] &&
|
|
m_regs_ready_4_rl[1] &&
|
|
m_regs_ready_4_rl[0] ;
|
|
assign m_ready_wire_5$wget =
|
|
m_regs_ready_5_rl[3] && m_regs_ready_5_rl[2] &&
|
|
m_regs_ready_5_rl[1] &&
|
|
m_regs_ready_5_rl[0] ;
|
|
assign m_ready_wire_6$wget =
|
|
m_regs_ready_6_rl[3] && m_regs_ready_6_rl[2] &&
|
|
m_regs_ready_6_rl[1] &&
|
|
m_regs_ready_6_rl[0] ;
|
|
assign m_ready_wire_7$wget =
|
|
m_regs_ready_7_rl[3] && m_regs_ready_7_rl[2] &&
|
|
m_regs_ready_7_rl[1] &&
|
|
m_regs_ready_7_rl[0] ;
|
|
assign m_ready_wire_8$wget =
|
|
m_regs_ready_8_rl[3] && m_regs_ready_8_rl[2] &&
|
|
m_regs_ready_8_rl[1] &&
|
|
m_regs_ready_8_rl[0] ;
|
|
assign m_ready_wire_9$wget =
|
|
m_regs_ready_9_rl[3] && m_regs_ready_9_rl[2] &&
|
|
m_regs_ready_9_rl[1] &&
|
|
m_regs_ready_9_rl[0] ;
|
|
assign m_ready_wire_10$wget =
|
|
m_regs_ready_10_rl[3] && m_regs_ready_10_rl[2] &&
|
|
m_regs_ready_10_rl[1] &&
|
|
m_regs_ready_10_rl[0] ;
|
|
assign m_ready_wire_11$wget =
|
|
m_regs_ready_11_rl[3] && m_regs_ready_11_rl[2] &&
|
|
m_regs_ready_11_rl[1] &&
|
|
m_regs_ready_11_rl[0] ;
|
|
assign m_ready_wire_12$wget =
|
|
m_regs_ready_12_rl[3] && m_regs_ready_12_rl[2] &&
|
|
m_regs_ready_12_rl[1] &&
|
|
m_regs_ready_12_rl[0] ;
|
|
assign m_ready_wire_13$wget =
|
|
m_regs_ready_13_rl[3] && m_regs_ready_13_rl[2] &&
|
|
m_regs_ready_13_rl[1] &&
|
|
m_regs_ready_13_rl[0] ;
|
|
assign m_ready_wire_14$wget =
|
|
m_regs_ready_14_rl[3] && m_regs_ready_14_rl[2] &&
|
|
m_regs_ready_14_rl[1] &&
|
|
m_regs_ready_14_rl[0] ;
|
|
assign m_ready_wire_15$wget =
|
|
m_regs_ready_15_rl[3] && m_regs_ready_15_rl[2] &&
|
|
m_regs_ready_15_rl[1] &&
|
|
m_regs_ready_15_rl[0] ;
|
|
assign m_enqP_wire$wget =
|
|
{ NOT_m_valid_0_rl_41_OR_NOT_m_valid_1_rl_2_42_4_ETC___d655 ||
|
|
NOT_m_valid_8_rl_1_56_OR_NOT_m_valid_9_rl_8_57_ETC___d670,
|
|
m_valid_0_rl_AND_m_valid_1_rl_2_72_AND_m_valid_ETC___d678 ?
|
|
IF_m_valid_8_rl_1_AND_m_valid_9_rl_8_79_AND_m__ETC___d693 :
|
|
IF_m_valid_0_rl_AND_m_valid_1_rl_2_72_AND_m_va_ETC___d700 } ;
|
|
|
|
// register m_data_0
|
|
assign m_data_0$D_IN = enq_x[154:66] ;
|
|
assign m_data_0$EN = m_valid_0_lat_1$whas ;
|
|
|
|
// register m_data_1
|
|
assign m_data_1$D_IN = enq_x[154:66] ;
|
|
assign m_data_1$EN = m_valid_1_lat_1$whas ;
|
|
|
|
// register m_data_10
|
|
assign m_data_10$D_IN = enq_x[154:66] ;
|
|
assign m_data_10$EN = m_valid_10_lat_1$whas ;
|
|
|
|
// register m_data_11
|
|
assign m_data_11$D_IN = enq_x[154:66] ;
|
|
assign m_data_11$EN = m_valid_11_lat_1$whas ;
|
|
|
|
// register m_data_12
|
|
assign m_data_12$D_IN = enq_x[154:66] ;
|
|
assign m_data_12$EN = m_valid_12_lat_1$whas ;
|
|
|
|
// register m_data_13
|
|
assign m_data_13$D_IN = enq_x[154:66] ;
|
|
assign m_data_13$EN = m_valid_13_lat_1$whas ;
|
|
|
|
// register m_data_14
|
|
assign m_data_14$D_IN = enq_x[154:66] ;
|
|
assign m_data_14$EN = m_valid_14_lat_1$whas ;
|
|
|
|
// register m_data_15
|
|
assign m_data_15$D_IN = enq_x[154:66] ;
|
|
assign m_data_15$EN = m_valid_15_lat_1$whas ;
|
|
|
|
// register m_data_2
|
|
assign m_data_2$D_IN = enq_x[154:66] ;
|
|
assign m_data_2$EN = m_valid_2_lat_1$whas ;
|
|
|
|
// register m_data_3
|
|
assign m_data_3$D_IN = enq_x[154:66] ;
|
|
assign m_data_3$EN = m_valid_3_lat_1$whas ;
|
|
|
|
// register m_data_4
|
|
assign m_data_4$D_IN = enq_x[154:66] ;
|
|
assign m_data_4$EN = m_valid_4_lat_1$whas ;
|
|
|
|
// register m_data_5
|
|
assign m_data_5$D_IN = enq_x[154:66] ;
|
|
assign m_data_5$EN = m_valid_5_lat_1$whas ;
|
|
|
|
// register m_data_6
|
|
assign m_data_6$D_IN = enq_x[154:66] ;
|
|
assign m_data_6$EN = m_valid_6_lat_1$whas ;
|
|
|
|
// register m_data_7
|
|
assign m_data_7$D_IN = enq_x[154:66] ;
|
|
assign m_data_7$EN = m_valid_7_lat_1$whas ;
|
|
|
|
// register m_data_8
|
|
assign m_data_8$D_IN = enq_x[154:66] ;
|
|
assign m_data_8$EN = m_valid_8_lat_1$whas ;
|
|
|
|
// register m_data_9
|
|
assign m_data_9$D_IN = enq_x[154:66] ;
|
|
assign m_data_9$EN = m_valid_9_lat_1$whas ;
|
|
|
|
// register m_regs_0
|
|
assign m_regs_0$D_IN = enq_x[65:33] ;
|
|
assign m_regs_0$EN = m_valid_0_lat_1$whas ;
|
|
|
|
// register m_regs_1
|
|
assign m_regs_1$D_IN = enq_x[65:33] ;
|
|
assign m_regs_1$EN = m_valid_1_lat_1$whas ;
|
|
|
|
// register m_regs_10
|
|
assign m_regs_10$D_IN = enq_x[65:33] ;
|
|
assign m_regs_10$EN = m_valid_10_lat_1$whas ;
|
|
|
|
// register m_regs_11
|
|
assign m_regs_11$D_IN = enq_x[65:33] ;
|
|
assign m_regs_11$EN = m_valid_11_lat_1$whas ;
|
|
|
|
// register m_regs_12
|
|
assign m_regs_12$D_IN = enq_x[65:33] ;
|
|
assign m_regs_12$EN = m_valid_12_lat_1$whas ;
|
|
|
|
// register m_regs_13
|
|
assign m_regs_13$D_IN = enq_x[65:33] ;
|
|
assign m_regs_13$EN = m_valid_13_lat_1$whas ;
|
|
|
|
// register m_regs_14
|
|
assign m_regs_14$D_IN = enq_x[65:33] ;
|
|
assign m_regs_14$EN = m_valid_14_lat_1$whas ;
|
|
|
|
// register m_regs_15
|
|
assign m_regs_15$D_IN = enq_x[65:33] ;
|
|
assign m_regs_15$EN = m_valid_15_lat_1$whas ;
|
|
|
|
// register m_regs_2
|
|
assign m_regs_2$D_IN = enq_x[65:33] ;
|
|
assign m_regs_2$EN = m_valid_2_lat_1$whas ;
|
|
|
|
// register m_regs_3
|
|
assign m_regs_3$D_IN = enq_x[65:33] ;
|
|
assign m_regs_3$EN = m_valid_3_lat_1$whas ;
|
|
|
|
// register m_regs_4
|
|
assign m_regs_4$D_IN = enq_x[65:33] ;
|
|
assign m_regs_4$EN = m_valid_4_lat_1$whas ;
|
|
|
|
// register m_regs_5
|
|
assign m_regs_5$D_IN = enq_x[65:33] ;
|
|
assign m_regs_5$EN = m_valid_5_lat_1$whas ;
|
|
|
|
// register m_regs_6
|
|
assign m_regs_6$D_IN = enq_x[65:33] ;
|
|
assign m_regs_6$EN = m_valid_6_lat_1$whas ;
|
|
|
|
// register m_regs_7
|
|
assign m_regs_7$D_IN = enq_x[65:33] ;
|
|
assign m_regs_7$EN = m_valid_7_lat_1$whas ;
|
|
|
|
// register m_regs_8
|
|
assign m_regs_8$D_IN = enq_x[65:33] ;
|
|
assign m_regs_8$EN = m_valid_8_lat_1$whas ;
|
|
|
|
// register m_regs_9
|
|
assign m_regs_9$D_IN = enq_x[65:33] ;
|
|
assign m_regs_9$EN = m_valid_9_lat_1$whas ;
|
|
|
|
// register m_regs_ready_0_rl
|
|
assign m_regs_ready_0_rl$D_IN =
|
|
m_valid_0_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_0_lat_4$wget :
|
|
IF_m_regs_ready_0_lat_3_whas__29_THEN_m_regs_r_ETC___d241) ;
|
|
assign m_regs_ready_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_10_rl
|
|
assign m_regs_ready_10_rl$D_IN =
|
|
m_valid_10_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_10_lat_4$wget :
|
|
IF_m_regs_ready_10_lat_3_whas__19_THEN_m_regs__ETC___d431) ;
|
|
assign m_regs_ready_10_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_11_rl
|
|
assign m_regs_ready_11_rl$D_IN =
|
|
m_valid_11_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_11_lat_4$wget :
|
|
IF_m_regs_ready_11_lat_3_whas__38_THEN_m_regs__ETC___d450) ;
|
|
assign m_regs_ready_11_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_12_rl
|
|
assign m_regs_ready_12_rl$D_IN =
|
|
m_valid_12_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_12_lat_4$wget :
|
|
IF_m_regs_ready_12_lat_3_whas__57_THEN_m_regs__ETC___d469) ;
|
|
assign m_regs_ready_12_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_13_rl
|
|
assign m_regs_ready_13_rl$D_IN =
|
|
m_valid_13_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_13_lat_4$wget :
|
|
IF_m_regs_ready_13_lat_3_whas__76_THEN_m_regs__ETC___d488) ;
|
|
assign m_regs_ready_13_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_14_rl
|
|
assign m_regs_ready_14_rl$D_IN =
|
|
m_valid_14_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_14_lat_4$wget :
|
|
IF_m_regs_ready_14_lat_3_whas__95_THEN_m_regs__ETC___d507) ;
|
|
assign m_regs_ready_14_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_15_rl
|
|
assign m_regs_ready_15_rl$D_IN =
|
|
m_valid_15_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_15_lat_4$wget :
|
|
IF_m_regs_ready_15_lat_3_whas__14_THEN_m_regs__ETC___d526) ;
|
|
assign m_regs_ready_15_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_1_rl
|
|
assign m_regs_ready_1_rl$D_IN =
|
|
m_valid_1_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_1_lat_4$wget :
|
|
IF_m_regs_ready_1_lat_3_whas__48_THEN_m_regs_r_ETC___d260) ;
|
|
assign m_regs_ready_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_2_rl
|
|
assign m_regs_ready_2_rl$D_IN =
|
|
m_valid_2_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_2_lat_4$wget :
|
|
IF_m_regs_ready_2_lat_3_whas__67_THEN_m_regs_r_ETC___d279) ;
|
|
assign m_regs_ready_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_3_rl
|
|
assign m_regs_ready_3_rl$D_IN =
|
|
m_valid_3_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_3_lat_4$wget :
|
|
IF_m_regs_ready_3_lat_3_whas__86_THEN_m_regs_r_ETC___d298) ;
|
|
assign m_regs_ready_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_4_rl
|
|
assign m_regs_ready_4_rl$D_IN =
|
|
m_valid_4_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_4_lat_4$wget :
|
|
IF_m_regs_ready_4_lat_3_whas__05_THEN_m_regs_r_ETC___d317) ;
|
|
assign m_regs_ready_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_5_rl
|
|
assign m_regs_ready_5_rl$D_IN =
|
|
m_valid_5_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_5_lat_4$wget :
|
|
IF_m_regs_ready_5_lat_3_whas__24_THEN_m_regs_r_ETC___d336) ;
|
|
assign m_regs_ready_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_6_rl
|
|
assign m_regs_ready_6_rl$D_IN =
|
|
m_valid_6_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_6_lat_4$wget :
|
|
IF_m_regs_ready_6_lat_3_whas__43_THEN_m_regs_r_ETC___d355) ;
|
|
assign m_regs_ready_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_7_rl
|
|
assign m_regs_ready_7_rl$D_IN =
|
|
m_valid_7_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_7_lat_4$wget :
|
|
IF_m_regs_ready_7_lat_3_whas__62_THEN_m_regs_r_ETC___d374) ;
|
|
assign m_regs_ready_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_8_rl
|
|
assign m_regs_ready_8_rl$D_IN =
|
|
m_valid_8_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_8_lat_4$wget :
|
|
IF_m_regs_ready_8_lat_3_whas__81_THEN_m_regs_r_ETC___d393) ;
|
|
assign m_regs_ready_8_rl$EN = 1'd1 ;
|
|
|
|
// register m_regs_ready_9_rl
|
|
assign m_regs_ready_9_rl$D_IN =
|
|
m_valid_9_lat_1$whas ?
|
|
enq_x[3:0] :
|
|
(EN_setRegReady_4_put ?
|
|
m_regs_ready_9_lat_4$wget :
|
|
IF_m_regs_ready_9_lat_3_whas__00_THEN_m_regs_r_ETC___d412) ;
|
|
assign m_regs_ready_9_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_0_rl
|
|
assign m_spec_bits_0_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h11253 :
|
|
n__read__h99211 ;
|
|
assign m_spec_bits_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_10_rl
|
|
assign m_spec_bits_10_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h14703 :
|
|
n__read__h100501 ;
|
|
assign m_spec_bits_10_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_11_rl
|
|
assign m_spec_bits_11_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h15048 :
|
|
n__read__h100630 ;
|
|
assign m_spec_bits_11_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_12_rl
|
|
assign m_spec_bits_12_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h15393 :
|
|
n__read__h100759 ;
|
|
assign m_spec_bits_12_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_13_rl
|
|
assign m_spec_bits_13_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h15738 :
|
|
n__read__h100888 ;
|
|
assign m_spec_bits_13_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_14_rl
|
|
assign m_spec_bits_14_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h16083 :
|
|
n__read__h101017 ;
|
|
assign m_spec_bits_14_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_15_rl
|
|
assign m_spec_bits_15_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h16428 :
|
|
n__read__h101134 ;
|
|
assign m_spec_bits_15_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_1_rl
|
|
assign m_spec_bits_1_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h11598 :
|
|
n__read__h99340 ;
|
|
assign m_spec_bits_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_2_rl
|
|
assign m_spec_bits_2_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h11943 :
|
|
n__read__h99469 ;
|
|
assign m_spec_bits_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_3_rl
|
|
assign m_spec_bits_3_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h12288 :
|
|
n__read__h99598 ;
|
|
assign m_spec_bits_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_4_rl
|
|
assign m_spec_bits_4_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h12633 :
|
|
n__read__h99727 ;
|
|
assign m_spec_bits_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_5_rl
|
|
assign m_spec_bits_5_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h12978 :
|
|
n__read__h99856 ;
|
|
assign m_spec_bits_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_6_rl
|
|
assign m_spec_bits_6_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h13323 :
|
|
n__read__h99985 ;
|
|
assign m_spec_bits_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_7_rl
|
|
assign m_spec_bits_7_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h13668 :
|
|
n__read__h100114 ;
|
|
assign m_spec_bits_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_8_rl
|
|
assign m_spec_bits_8_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h14013 :
|
|
n__read__h100243 ;
|
|
assign m_spec_bits_8_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_bits_9_rl
|
|
assign m_spec_bits_9_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h14358 :
|
|
n__read__h100372 ;
|
|
assign m_spec_bits_9_rl$EN = 1'd1 ;
|
|
|
|
// register m_spec_tag_0
|
|
assign m_spec_tag_0$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_0$EN = m_valid_0_lat_1$whas ;
|
|
|
|
// register m_spec_tag_1
|
|
assign m_spec_tag_1$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_1$EN = m_valid_1_lat_1$whas ;
|
|
|
|
// register m_spec_tag_10
|
|
assign m_spec_tag_10$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_10$EN = m_valid_10_lat_1$whas ;
|
|
|
|
// register m_spec_tag_11
|
|
assign m_spec_tag_11$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_11$EN = m_valid_11_lat_1$whas ;
|
|
|
|
// register m_spec_tag_12
|
|
assign m_spec_tag_12$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_12$EN = m_valid_12_lat_1$whas ;
|
|
|
|
// register m_spec_tag_13
|
|
assign m_spec_tag_13$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_13$EN = m_valid_13_lat_1$whas ;
|
|
|
|
// register m_spec_tag_14
|
|
assign m_spec_tag_14$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_14$EN = m_valid_14_lat_1$whas ;
|
|
|
|
// register m_spec_tag_15
|
|
assign m_spec_tag_15$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_15$EN = m_valid_15_lat_1$whas ;
|
|
|
|
// register m_spec_tag_2
|
|
assign m_spec_tag_2$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_2$EN = m_valid_2_lat_1$whas ;
|
|
|
|
// register m_spec_tag_3
|
|
assign m_spec_tag_3$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_3$EN = m_valid_3_lat_1$whas ;
|
|
|
|
// register m_spec_tag_4
|
|
assign m_spec_tag_4$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_4$EN = m_valid_4_lat_1$whas ;
|
|
|
|
// register m_spec_tag_5
|
|
assign m_spec_tag_5$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_5$EN = m_valid_5_lat_1$whas ;
|
|
|
|
// register m_spec_tag_6
|
|
assign m_spec_tag_6$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_6$EN = m_valid_6_lat_1$whas ;
|
|
|
|
// register m_spec_tag_7
|
|
assign m_spec_tag_7$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_7$EN = m_valid_7_lat_1$whas ;
|
|
|
|
// register m_spec_tag_8
|
|
assign m_spec_tag_8$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_8$EN = m_valid_8_lat_1$whas ;
|
|
|
|
// register m_spec_tag_9
|
|
assign m_spec_tag_9$D_IN = enq_x[8:4] ;
|
|
assign m_spec_tag_9$EN = m_valid_9_lat_1$whas ;
|
|
|
|
// register m_tag_0
|
|
assign m_tag_0$D_IN = enq_x[32:21] ;
|
|
assign m_tag_0$EN = m_valid_0_lat_1$whas ;
|
|
|
|
// register m_tag_1
|
|
assign m_tag_1$D_IN = enq_x[32:21] ;
|
|
assign m_tag_1$EN = m_valid_1_lat_1$whas ;
|
|
|
|
// register m_tag_10
|
|
assign m_tag_10$D_IN = enq_x[32:21] ;
|
|
assign m_tag_10$EN = m_valid_10_lat_1$whas ;
|
|
|
|
// register m_tag_11
|
|
assign m_tag_11$D_IN = enq_x[32:21] ;
|
|
assign m_tag_11$EN = m_valid_11_lat_1$whas ;
|
|
|
|
// register m_tag_12
|
|
assign m_tag_12$D_IN = enq_x[32:21] ;
|
|
assign m_tag_12$EN = m_valid_12_lat_1$whas ;
|
|
|
|
// register m_tag_13
|
|
assign m_tag_13$D_IN = enq_x[32:21] ;
|
|
assign m_tag_13$EN = m_valid_13_lat_1$whas ;
|
|
|
|
// register m_tag_14
|
|
assign m_tag_14$D_IN = enq_x[32:21] ;
|
|
assign m_tag_14$EN = m_valid_14_lat_1$whas ;
|
|
|
|
// register m_tag_15
|
|
assign m_tag_15$D_IN = enq_x[32:21] ;
|
|
assign m_tag_15$EN = m_valid_15_lat_1$whas ;
|
|
|
|
// register m_tag_2
|
|
assign m_tag_2$D_IN = enq_x[32:21] ;
|
|
assign m_tag_2$EN = m_valid_2_lat_1$whas ;
|
|
|
|
// register m_tag_3
|
|
assign m_tag_3$D_IN = enq_x[32:21] ;
|
|
assign m_tag_3$EN = m_valid_3_lat_1$whas ;
|
|
|
|
// register m_tag_4
|
|
assign m_tag_4$D_IN = enq_x[32:21] ;
|
|
assign m_tag_4$EN = m_valid_4_lat_1$whas ;
|
|
|
|
// register m_tag_5
|
|
assign m_tag_5$D_IN = enq_x[32:21] ;
|
|
assign m_tag_5$EN = m_valid_5_lat_1$whas ;
|
|
|
|
// register m_tag_6
|
|
assign m_tag_6$D_IN = enq_x[32:21] ;
|
|
assign m_tag_6$EN = m_valid_6_lat_1$whas ;
|
|
|
|
// register m_tag_7
|
|
assign m_tag_7$D_IN = enq_x[32:21] ;
|
|
assign m_tag_7$EN = m_valid_7_lat_1$whas ;
|
|
|
|
// register m_tag_8
|
|
assign m_tag_8$D_IN = enq_x[32:21] ;
|
|
assign m_tag_8$EN = m_valid_8_lat_1$whas ;
|
|
|
|
// register m_tag_9
|
|
assign m_tag_9$D_IN = enq_x[32:21] ;
|
|
assign m_tag_9$EN = m_valid_9_lat_1$whas ;
|
|
|
|
// register m_validEntryCount
|
|
assign m_validEntryCount$D_IN = 5'h0 ;
|
|
assign m_validEntryCount$EN = 1'b0 ;
|
|
|
|
// register m_valid_0_rl
|
|
assign m_valid_0_rl$D_IN =
|
|
m_valid_0_lat_1$whas ||
|
|
(m_valid_0_lat_0$whas ? 1'd0 : m_valid_0_rl) ;
|
|
assign m_valid_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_10_rl
|
|
assign m_valid_10_rl$D_IN =
|
|
m_valid_10_lat_1$whas ||
|
|
(m_valid_10_lat_0$whas ? 1'd0 : m_valid_10_rl) ;
|
|
assign m_valid_10_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_11_rl
|
|
assign m_valid_11_rl$D_IN =
|
|
m_valid_11_lat_1$whas ||
|
|
(m_valid_11_lat_0$whas ? 1'd0 : m_valid_11_rl) ;
|
|
assign m_valid_11_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_12_rl
|
|
assign m_valid_12_rl$D_IN =
|
|
m_valid_12_lat_1$whas ||
|
|
(m_valid_12_lat_0$whas ? 1'd0 : m_valid_12_rl) ;
|
|
assign m_valid_12_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_13_rl
|
|
assign m_valid_13_rl$D_IN =
|
|
m_valid_13_lat_1$whas ||
|
|
(m_valid_13_lat_0$whas ? 1'd0 : m_valid_13_rl) ;
|
|
assign m_valid_13_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_14_rl
|
|
assign m_valid_14_rl$D_IN =
|
|
m_valid_14_lat_1$whas ||
|
|
(m_valid_14_lat_0$whas ? 1'd0 : m_valid_14_rl) ;
|
|
assign m_valid_14_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_15_rl
|
|
assign m_valid_15_rl$D_IN =
|
|
m_valid_15_lat_1$whas ||
|
|
(m_valid_15_lat_0$whas ? 1'd0 : m_valid_15_rl) ;
|
|
assign m_valid_15_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_1_rl
|
|
assign m_valid_1_rl$D_IN =
|
|
m_valid_1_lat_1$whas ||
|
|
(m_valid_1_lat_0$whas ? 1'd0 : m_valid_1_rl) ;
|
|
assign m_valid_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_2_rl
|
|
assign m_valid_2_rl$D_IN =
|
|
m_valid_2_lat_1$whas ||
|
|
(m_valid_2_lat_0$whas ? 1'd0 : m_valid_2_rl) ;
|
|
assign m_valid_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_3_rl
|
|
assign m_valid_3_rl$D_IN =
|
|
m_valid_3_lat_1$whas ||
|
|
(m_valid_3_lat_0$whas ? 1'd0 : m_valid_3_rl) ;
|
|
assign m_valid_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_4_rl
|
|
assign m_valid_4_rl$D_IN =
|
|
m_valid_4_lat_1$whas ||
|
|
(m_valid_4_lat_0$whas ? 1'd0 : m_valid_4_rl) ;
|
|
assign m_valid_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_5_rl
|
|
assign m_valid_5_rl$D_IN =
|
|
m_valid_5_lat_1$whas ||
|
|
(m_valid_5_lat_0$whas ? 1'd0 : m_valid_5_rl) ;
|
|
assign m_valid_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_6_rl
|
|
assign m_valid_6_rl$D_IN =
|
|
m_valid_6_lat_1$whas ||
|
|
(m_valid_6_lat_0$whas ? 1'd0 : m_valid_6_rl) ;
|
|
assign m_valid_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_7_rl
|
|
assign m_valid_7_rl$D_IN =
|
|
m_valid_7_lat_1$whas ||
|
|
(m_valid_7_lat_0$whas ? 1'd0 : m_valid_7_rl) ;
|
|
assign m_valid_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_8_rl
|
|
assign m_valid_8_rl$D_IN =
|
|
m_valid_8_lat_1$whas ||
|
|
(m_valid_8_lat_0$whas ? 1'd0 : m_valid_8_rl) ;
|
|
assign m_valid_8_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_9_rl
|
|
assign m_valid_9_rl$D_IN =
|
|
m_valid_9_lat_1$whas ||
|
|
(m_valid_9_lat_0$whas ? 1'd0 : m_valid_9_rl) ;
|
|
assign m_valid_9_rl$EN = 1'd1 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_NOT_m_valid_11_rl_2_60_OR_NOT_m_ready_wire__ETC___d976 =
|
|
(!m_valid_11_rl || !m_ready_wire_11$wget ||
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 <
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912) ?
|
|
4'd10 :
|
|
4'd11 ;
|
|
assign IF_NOT_m_valid_13_rl_6_64_OR_NOT_m_ready_wire__ETC___d988 =
|
|
(!m_valid_13_rl || !m_ready_wire_13$wget ||
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 <
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924) ?
|
|
4'd12 :
|
|
4'd13 ;
|
|
assign IF_NOT_m_valid_15_rl_10_67_OR_NOT_m_ready_wire_ETC___d993 =
|
|
(!m_valid_15_rl || !m_ready_wire_15$wget ||
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 <
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936) ?
|
|
4'd14 :
|
|
4'd15 ;
|
|
assign IF_NOT_m_valid_1_rl_2_42_OR_NOT_m_ready_wire_1_ETC___d845 =
|
|
(!m_valid_1_rl || !m_ready_wire_1$wget ||
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 <
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842) ?
|
|
4'd0 :
|
|
4'd1 ;
|
|
assign IF_NOT_m_valid_3_rl_6_45_OR_NOT_m_ready_wire_3_ETC___d862 =
|
|
(!m_valid_3_rl || !m_ready_wire_3$wget ||
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 <
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859) ?
|
|
4'd2 :
|
|
4'd3 ;
|
|
assign IF_NOT_m_valid_5_rl_0_49_OR_NOT_m_ready_wire_5_ETC___d947 =
|
|
(!m_valid_5_rl || !m_ready_wire_5$wget ||
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 <
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876) ?
|
|
4'd4 :
|
|
4'd5 ;
|
|
assign IF_NOT_m_valid_7_rl_4_52_OR_NOT_m_ready_wire_7_ETC___d952 =
|
|
(!m_valid_7_rl || !m_ready_wire_7$wget ||
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 <
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888) ?
|
|
4'd6 :
|
|
4'd7 ;
|
|
assign IF_NOT_m_valid_9_rl_8_57_OR_NOT_m_ready_wire_9_ETC___d971 =
|
|
(!m_valid_9_rl || !m_ready_wire_9$wget ||
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 <
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900) ?
|
|
4'd8 :
|
|
4'd9 ;
|
|
assign IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1000 =
|
|
(SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 ||
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 <
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997) ?
|
|
a__h58999 :
|
|
b__h59000 ;
|
|
assign IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1007 =
|
|
(SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 ||
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 <
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004) ?
|
|
a__h58594 :
|
|
b__h58595 ;
|
|
assign IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1014 =
|
|
(SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 ||
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 <
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011) ?
|
|
a__h54195 :
|
|
b__h54196 ;
|
|
assign IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d942 =
|
|
(SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 ||
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 <
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939) ?
|
|
a__h54225 :
|
|
b__h54226 ;
|
|
assign IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d959 =
|
|
(SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 ||
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 <
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956) ?
|
|
a__h58090 :
|
|
b__h58091 ;
|
|
assign IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d966 =
|
|
(SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 ||
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 <
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963) ?
|
|
a__h54213 :
|
|
b__h54214 ;
|
|
assign IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d983 =
|
|
(SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 ||
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 <
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980) ?
|
|
a__h58606 :
|
|
b__h58607 ;
|
|
assign IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2453 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_0_lat_0$wget[3] :
|
|
m_regs_ready_0_rl[3] ;
|
|
assign IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2461 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_0_lat_0$wget[2] :
|
|
m_regs_ready_0_rl[2] ;
|
|
assign IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2469 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_0_lat_0$wget[1] :
|
|
m_regs_ready_0_rl[1] ;
|
|
assign IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2472 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_0_lat_0$wget[0] :
|
|
m_regs_ready_0_rl[0] ;
|
|
assign IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d239 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_0_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_0_lat_0$wget :
|
|
m_regs_ready_0_rl) ;
|
|
assign IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2904 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_0_lat_1$wget[3] :
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2453 ;
|
|
assign IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2912 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_0_lat_1$wget[2] :
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2461 ;
|
|
assign IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2920 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_0_lat_1$wget[1] :
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2469 ;
|
|
assign IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2923 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_0_lat_1$wget[0] :
|
|
IF_m_regs_ready_0_lat_0_whas__35_THEN_m_regs_r_ETC___d2472 ;
|
|
assign IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3355 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_0_lat_2$wget[3] :
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2904 ;
|
|
assign IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3363 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_0_lat_2$wget[2] :
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2912 ;
|
|
assign IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3371 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_0_lat_2$wget[1] :
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2920 ;
|
|
assign IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3374 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_0_lat_2$wget[0] :
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d2923 ;
|
|
assign IF_m_regs_ready_0_lat_3_whas__29_THEN_m_regs_r_ETC___d241 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_0_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_0_lat_2$wget :
|
|
IF_m_regs_ready_0_lat_1_whas__33_THEN_m_regs_r_ETC___d239) ;
|
|
assign IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2733 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_10_lat_0$wget[3] :
|
|
m_regs_ready_10_rl[3] ;
|
|
assign IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2741 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_10_lat_0$wget[2] :
|
|
m_regs_ready_10_rl[2] ;
|
|
assign IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2749 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_10_lat_0$wget[1] :
|
|
m_regs_ready_10_rl[1] ;
|
|
assign IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2752 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_10_lat_0$wget[0] :
|
|
m_regs_ready_10_rl[0] ;
|
|
assign IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3184 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_10_lat_1$wget[3] :
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2733 ;
|
|
assign IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3192 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_10_lat_1$wget[2] :
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2741 ;
|
|
assign IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3200 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_10_lat_1$wget[1] :
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2749 ;
|
|
assign IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3203 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_10_lat_1$wget[0] :
|
|
IF_m_regs_ready_10_lat_0_whas__25_THEN_m_regs__ETC___d2752 ;
|
|
assign IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d429 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_10_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_10_lat_0$wget :
|
|
m_regs_ready_10_rl) ;
|
|
assign IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3635 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_10_lat_2$wget[3] :
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3184 ;
|
|
assign IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3643 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_10_lat_2$wget[2] :
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3192 ;
|
|
assign IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3651 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_10_lat_2$wget[1] :
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3200 ;
|
|
assign IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3654 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_10_lat_2$wget[0] :
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d3203 ;
|
|
assign IF_m_regs_ready_10_lat_3_whas__19_THEN_m_regs__ETC___d431 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_10_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_10_lat_2$wget :
|
|
IF_m_regs_ready_10_lat_1_whas__23_THEN_m_regs__ETC___d429) ;
|
|
assign IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2761 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_11_lat_0$wget[3] :
|
|
m_regs_ready_11_rl[3] ;
|
|
assign IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2769 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_11_lat_0$wget[2] :
|
|
m_regs_ready_11_rl[2] ;
|
|
assign IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2777 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_11_lat_0$wget[1] :
|
|
m_regs_ready_11_rl[1] ;
|
|
assign IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2780 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_11_lat_0$wget[0] :
|
|
m_regs_ready_11_rl[0] ;
|
|
assign IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3212 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_11_lat_1$wget[3] :
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2761 ;
|
|
assign IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3220 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_11_lat_1$wget[2] :
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2769 ;
|
|
assign IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3228 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_11_lat_1$wget[1] :
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2777 ;
|
|
assign IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3231 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_11_lat_1$wget[0] :
|
|
IF_m_regs_ready_11_lat_0_whas__44_THEN_m_regs__ETC___d2780 ;
|
|
assign IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d448 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_11_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_11_lat_0$wget :
|
|
m_regs_ready_11_rl) ;
|
|
assign IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3663 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_11_lat_2$wget[3] :
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3212 ;
|
|
assign IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3671 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_11_lat_2$wget[2] :
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3220 ;
|
|
assign IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3679 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_11_lat_2$wget[1] :
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3228 ;
|
|
assign IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3682 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_11_lat_2$wget[0] :
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d3231 ;
|
|
assign IF_m_regs_ready_11_lat_3_whas__38_THEN_m_regs__ETC___d450 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_11_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_11_lat_2$wget :
|
|
IF_m_regs_ready_11_lat_1_whas__42_THEN_m_regs__ETC___d448) ;
|
|
assign IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2789 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_12_lat_0$wget[3] :
|
|
m_regs_ready_12_rl[3] ;
|
|
assign IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2797 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_12_lat_0$wget[2] :
|
|
m_regs_ready_12_rl[2] ;
|
|
assign IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2805 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_12_lat_0$wget[1] :
|
|
m_regs_ready_12_rl[1] ;
|
|
assign IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2808 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_12_lat_0$wget[0] :
|
|
m_regs_ready_12_rl[0] ;
|
|
assign IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3240 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_12_lat_1$wget[3] :
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2789 ;
|
|
assign IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3248 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_12_lat_1$wget[2] :
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2797 ;
|
|
assign IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3256 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_12_lat_1$wget[1] :
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2805 ;
|
|
assign IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3259 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_12_lat_1$wget[0] :
|
|
IF_m_regs_ready_12_lat_0_whas__63_THEN_m_regs__ETC___d2808 ;
|
|
assign IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d467 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_12_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_12_lat_0$wget :
|
|
m_regs_ready_12_rl) ;
|
|
assign IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3691 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_12_lat_2$wget[3] :
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3240 ;
|
|
assign IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3699 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_12_lat_2$wget[2] :
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3248 ;
|
|
assign IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3707 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_12_lat_2$wget[1] :
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3256 ;
|
|
assign IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3710 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_12_lat_2$wget[0] :
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d3259 ;
|
|
assign IF_m_regs_ready_12_lat_3_whas__57_THEN_m_regs__ETC___d469 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_12_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_12_lat_2$wget :
|
|
IF_m_regs_ready_12_lat_1_whas__61_THEN_m_regs__ETC___d467) ;
|
|
assign IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2817 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_13_lat_0$wget[3] :
|
|
m_regs_ready_13_rl[3] ;
|
|
assign IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2825 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_13_lat_0$wget[2] :
|
|
m_regs_ready_13_rl[2] ;
|
|
assign IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2833 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_13_lat_0$wget[1] :
|
|
m_regs_ready_13_rl[1] ;
|
|
assign IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2836 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_13_lat_0$wget[0] :
|
|
m_regs_ready_13_rl[0] ;
|
|
assign IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3268 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_13_lat_1$wget[3] :
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2817 ;
|
|
assign IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3276 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_13_lat_1$wget[2] :
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2825 ;
|
|
assign IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3284 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_13_lat_1$wget[1] :
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2833 ;
|
|
assign IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3287 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_13_lat_1$wget[0] :
|
|
IF_m_regs_ready_13_lat_0_whas__82_THEN_m_regs__ETC___d2836 ;
|
|
assign IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d486 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_13_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_13_lat_0$wget :
|
|
m_regs_ready_13_rl) ;
|
|
assign IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3719 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_13_lat_2$wget[3] :
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3268 ;
|
|
assign IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3727 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_13_lat_2$wget[2] :
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3276 ;
|
|
assign IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3735 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_13_lat_2$wget[1] :
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3284 ;
|
|
assign IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3738 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_13_lat_2$wget[0] :
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d3287 ;
|
|
assign IF_m_regs_ready_13_lat_3_whas__76_THEN_m_regs__ETC___d488 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_13_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_13_lat_2$wget :
|
|
IF_m_regs_ready_13_lat_1_whas__80_THEN_m_regs__ETC___d486) ;
|
|
assign IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2845 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_14_lat_0$wget[3] :
|
|
m_regs_ready_14_rl[3] ;
|
|
assign IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2853 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_14_lat_0$wget[2] :
|
|
m_regs_ready_14_rl[2] ;
|
|
assign IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2861 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_14_lat_0$wget[1] :
|
|
m_regs_ready_14_rl[1] ;
|
|
assign IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2864 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_14_lat_0$wget[0] :
|
|
m_regs_ready_14_rl[0] ;
|
|
assign IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3296 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_14_lat_1$wget[3] :
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2845 ;
|
|
assign IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3304 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_14_lat_1$wget[2] :
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2853 ;
|
|
assign IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3312 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_14_lat_1$wget[1] :
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2861 ;
|
|
assign IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3315 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_14_lat_1$wget[0] :
|
|
IF_m_regs_ready_14_lat_0_whas__01_THEN_m_regs__ETC___d2864 ;
|
|
assign IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d505 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_14_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_14_lat_0$wget :
|
|
m_regs_ready_14_rl) ;
|
|
assign IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3747 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_14_lat_2$wget[3] :
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3296 ;
|
|
assign IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3755 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_14_lat_2$wget[2] :
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3304 ;
|
|
assign IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3763 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_14_lat_2$wget[1] :
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3312 ;
|
|
assign IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3766 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_14_lat_2$wget[0] :
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d3315 ;
|
|
assign IF_m_regs_ready_14_lat_3_whas__95_THEN_m_regs__ETC___d507 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_14_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_14_lat_2$wget :
|
|
IF_m_regs_ready_14_lat_1_whas__99_THEN_m_regs__ETC___d505) ;
|
|
assign IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2873 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_15_lat_0$wget[3] :
|
|
m_regs_ready_15_rl[3] ;
|
|
assign IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2881 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_15_lat_0$wget[2] :
|
|
m_regs_ready_15_rl[2] ;
|
|
assign IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2889 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_15_lat_0$wget[1] :
|
|
m_regs_ready_15_rl[1] ;
|
|
assign IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2892 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_15_lat_0$wget[0] :
|
|
m_regs_ready_15_rl[0] ;
|
|
assign IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3324 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_15_lat_1$wget[3] :
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2873 ;
|
|
assign IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3332 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_15_lat_1$wget[2] :
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2881 ;
|
|
assign IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3340 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_15_lat_1$wget[1] :
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2889 ;
|
|
assign IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3343 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_15_lat_1$wget[0] :
|
|
IF_m_regs_ready_15_lat_0_whas__20_THEN_m_regs__ETC___d2892 ;
|
|
assign IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d524 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_15_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_15_lat_0$wget :
|
|
m_regs_ready_15_rl) ;
|
|
assign IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3775 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_15_lat_2$wget[3] :
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3324 ;
|
|
assign IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3783 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_15_lat_2$wget[2] :
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3332 ;
|
|
assign IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3791 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_15_lat_2$wget[1] :
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3340 ;
|
|
assign IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3794 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_15_lat_2$wget[0] :
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d3343 ;
|
|
assign IF_m_regs_ready_15_lat_3_whas__14_THEN_m_regs__ETC___d526 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_15_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_15_lat_2$wget :
|
|
IF_m_regs_ready_15_lat_1_whas__18_THEN_m_regs__ETC___d524) ;
|
|
assign IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2481 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_1_lat_0$wget[3] :
|
|
m_regs_ready_1_rl[3] ;
|
|
assign IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2489 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_1_lat_0$wget[2] :
|
|
m_regs_ready_1_rl[2] ;
|
|
assign IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2497 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_1_lat_0$wget[1] :
|
|
m_regs_ready_1_rl[1] ;
|
|
assign IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2500 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_1_lat_0$wget[0] :
|
|
m_regs_ready_1_rl[0] ;
|
|
assign IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d258 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_1_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_1_lat_0$wget :
|
|
m_regs_ready_1_rl) ;
|
|
assign IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2932 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_1_lat_1$wget[3] :
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2481 ;
|
|
assign IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2940 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_1_lat_1$wget[2] :
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2489 ;
|
|
assign IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2948 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_1_lat_1$wget[1] :
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2497 ;
|
|
assign IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2951 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_1_lat_1$wget[0] :
|
|
IF_m_regs_ready_1_lat_0_whas__54_THEN_m_regs_r_ETC___d2500 ;
|
|
assign IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3383 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_1_lat_2$wget[3] :
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2932 ;
|
|
assign IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3391 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_1_lat_2$wget[2] :
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2940 ;
|
|
assign IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3399 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_1_lat_2$wget[1] :
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2948 ;
|
|
assign IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3402 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_1_lat_2$wget[0] :
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d2951 ;
|
|
assign IF_m_regs_ready_1_lat_3_whas__48_THEN_m_regs_r_ETC___d260 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_1_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_1_lat_2$wget :
|
|
IF_m_regs_ready_1_lat_1_whas__52_THEN_m_regs_r_ETC___d258) ;
|
|
assign IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2509 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_2_lat_0$wget[3] :
|
|
m_regs_ready_2_rl[3] ;
|
|
assign IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2517 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_2_lat_0$wget[2] :
|
|
m_regs_ready_2_rl[2] ;
|
|
assign IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2525 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_2_lat_0$wget[1] :
|
|
m_regs_ready_2_rl[1] ;
|
|
assign IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2528 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_2_lat_0$wget[0] :
|
|
m_regs_ready_2_rl[0] ;
|
|
assign IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d277 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_2_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_2_lat_0$wget :
|
|
m_regs_ready_2_rl) ;
|
|
assign IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2960 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_2_lat_1$wget[3] :
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2509 ;
|
|
assign IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2968 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_2_lat_1$wget[2] :
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2517 ;
|
|
assign IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2976 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_2_lat_1$wget[1] :
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2525 ;
|
|
assign IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2979 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_2_lat_1$wget[0] :
|
|
IF_m_regs_ready_2_lat_0_whas__73_THEN_m_regs_r_ETC___d2528 ;
|
|
assign IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3411 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_2_lat_2$wget[3] :
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2960 ;
|
|
assign IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3419 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_2_lat_2$wget[2] :
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2968 ;
|
|
assign IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3427 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_2_lat_2$wget[1] :
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2976 ;
|
|
assign IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3430 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_2_lat_2$wget[0] :
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d2979 ;
|
|
assign IF_m_regs_ready_2_lat_3_whas__67_THEN_m_regs_r_ETC___d279 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_2_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_2_lat_2$wget :
|
|
IF_m_regs_ready_2_lat_1_whas__71_THEN_m_regs_r_ETC___d277) ;
|
|
assign IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2537 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_3_lat_0$wget[3] :
|
|
m_regs_ready_3_rl[3] ;
|
|
assign IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2545 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_3_lat_0$wget[2] :
|
|
m_regs_ready_3_rl[2] ;
|
|
assign IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2553 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_3_lat_0$wget[1] :
|
|
m_regs_ready_3_rl[1] ;
|
|
assign IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2556 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_3_lat_0$wget[0] :
|
|
m_regs_ready_3_rl[0] ;
|
|
assign IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d296 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_3_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_3_lat_0$wget :
|
|
m_regs_ready_3_rl) ;
|
|
assign IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d2988 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_3_lat_1$wget[3] :
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2537 ;
|
|
assign IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d2996 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_3_lat_1$wget[2] :
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2545 ;
|
|
assign IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d3004 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_3_lat_1$wget[1] :
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2553 ;
|
|
assign IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d3007 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_3_lat_1$wget[0] :
|
|
IF_m_regs_ready_3_lat_0_whas__92_THEN_m_regs_r_ETC___d2556 ;
|
|
assign IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3439 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_3_lat_2$wget[3] :
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d2988 ;
|
|
assign IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3447 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_3_lat_2$wget[2] :
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d2996 ;
|
|
assign IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3455 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_3_lat_2$wget[1] :
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d3004 ;
|
|
assign IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3458 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_3_lat_2$wget[0] :
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d3007 ;
|
|
assign IF_m_regs_ready_3_lat_3_whas__86_THEN_m_regs_r_ETC___d298 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_3_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_3_lat_2$wget :
|
|
IF_m_regs_ready_3_lat_1_whas__90_THEN_m_regs_r_ETC___d296) ;
|
|
assign IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2565 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_4_lat_0$wget[3] :
|
|
m_regs_ready_4_rl[3] ;
|
|
assign IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2573 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_4_lat_0$wget[2] :
|
|
m_regs_ready_4_rl[2] ;
|
|
assign IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2581 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_4_lat_0$wget[1] :
|
|
m_regs_ready_4_rl[1] ;
|
|
assign IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2584 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_4_lat_0$wget[0] :
|
|
m_regs_ready_4_rl[0] ;
|
|
assign IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3016 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_4_lat_1$wget[3] :
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2565 ;
|
|
assign IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3024 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_4_lat_1$wget[2] :
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2573 ;
|
|
assign IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3032 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_4_lat_1$wget[1] :
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2581 ;
|
|
assign IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3035 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_4_lat_1$wget[0] :
|
|
IF_m_regs_ready_4_lat_0_whas__11_THEN_m_regs_r_ETC___d2584 ;
|
|
assign IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d315 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_4_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_4_lat_0$wget :
|
|
m_regs_ready_4_rl) ;
|
|
assign IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3467 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_4_lat_2$wget[3] :
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3016 ;
|
|
assign IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3475 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_4_lat_2$wget[2] :
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3024 ;
|
|
assign IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3483 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_4_lat_2$wget[1] :
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3032 ;
|
|
assign IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3486 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_4_lat_2$wget[0] :
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d3035 ;
|
|
assign IF_m_regs_ready_4_lat_3_whas__05_THEN_m_regs_r_ETC___d317 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_4_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_4_lat_2$wget :
|
|
IF_m_regs_ready_4_lat_1_whas__09_THEN_m_regs_r_ETC___d315) ;
|
|
assign IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2593 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_5_lat_0$wget[3] :
|
|
m_regs_ready_5_rl[3] ;
|
|
assign IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2601 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_5_lat_0$wget[2] :
|
|
m_regs_ready_5_rl[2] ;
|
|
assign IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2609 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_5_lat_0$wget[1] :
|
|
m_regs_ready_5_rl[1] ;
|
|
assign IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2612 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_5_lat_0$wget[0] :
|
|
m_regs_ready_5_rl[0] ;
|
|
assign IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3044 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_5_lat_1$wget[3] :
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2593 ;
|
|
assign IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3052 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_5_lat_1$wget[2] :
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2601 ;
|
|
assign IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3060 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_5_lat_1$wget[1] :
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2609 ;
|
|
assign IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3063 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_5_lat_1$wget[0] :
|
|
IF_m_regs_ready_5_lat_0_whas__30_THEN_m_regs_r_ETC___d2612 ;
|
|
assign IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d334 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_5_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_5_lat_0$wget :
|
|
m_regs_ready_5_rl) ;
|
|
assign IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3495 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_5_lat_2$wget[3] :
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3044 ;
|
|
assign IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3503 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_5_lat_2$wget[2] :
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3052 ;
|
|
assign IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3511 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_5_lat_2$wget[1] :
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3060 ;
|
|
assign IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3514 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_5_lat_2$wget[0] :
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d3063 ;
|
|
assign IF_m_regs_ready_5_lat_3_whas__24_THEN_m_regs_r_ETC___d336 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_5_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_5_lat_2$wget :
|
|
IF_m_regs_ready_5_lat_1_whas__28_THEN_m_regs_r_ETC___d334) ;
|
|
assign IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2621 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_6_lat_0$wget[3] :
|
|
m_regs_ready_6_rl[3] ;
|
|
assign IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2629 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_6_lat_0$wget[2] :
|
|
m_regs_ready_6_rl[2] ;
|
|
assign IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2637 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_6_lat_0$wget[1] :
|
|
m_regs_ready_6_rl[1] ;
|
|
assign IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2640 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_6_lat_0$wget[0] :
|
|
m_regs_ready_6_rl[0] ;
|
|
assign IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3072 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_6_lat_1$wget[3] :
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2621 ;
|
|
assign IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3080 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_6_lat_1$wget[2] :
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2629 ;
|
|
assign IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3088 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_6_lat_1$wget[1] :
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2637 ;
|
|
assign IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3091 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_6_lat_1$wget[0] :
|
|
IF_m_regs_ready_6_lat_0_whas__49_THEN_m_regs_r_ETC___d2640 ;
|
|
assign IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d353 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_6_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_6_lat_0$wget :
|
|
m_regs_ready_6_rl) ;
|
|
assign IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3523 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_6_lat_2$wget[3] :
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3072 ;
|
|
assign IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3531 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_6_lat_2$wget[2] :
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3080 ;
|
|
assign IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3539 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_6_lat_2$wget[1] :
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3088 ;
|
|
assign IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3542 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_6_lat_2$wget[0] :
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d3091 ;
|
|
assign IF_m_regs_ready_6_lat_3_whas__43_THEN_m_regs_r_ETC___d355 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_6_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_6_lat_2$wget :
|
|
IF_m_regs_ready_6_lat_1_whas__47_THEN_m_regs_r_ETC___d353) ;
|
|
assign IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2649 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_7_lat_0$wget[3] :
|
|
m_regs_ready_7_rl[3] ;
|
|
assign IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2657 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_7_lat_0$wget[2] :
|
|
m_regs_ready_7_rl[2] ;
|
|
assign IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2665 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_7_lat_0$wget[1] :
|
|
m_regs_ready_7_rl[1] ;
|
|
assign IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2668 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_7_lat_0$wget[0] :
|
|
m_regs_ready_7_rl[0] ;
|
|
assign IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3100 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_7_lat_1$wget[3] :
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2649 ;
|
|
assign IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3108 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_7_lat_1$wget[2] :
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2657 ;
|
|
assign IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3116 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_7_lat_1$wget[1] :
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2665 ;
|
|
assign IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3119 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_7_lat_1$wget[0] :
|
|
IF_m_regs_ready_7_lat_0_whas__68_THEN_m_regs_r_ETC___d2668 ;
|
|
assign IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d372 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_7_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_7_lat_0$wget :
|
|
m_regs_ready_7_rl) ;
|
|
assign IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3551 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_7_lat_2$wget[3] :
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3100 ;
|
|
assign IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3559 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_7_lat_2$wget[2] :
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3108 ;
|
|
assign IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3567 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_7_lat_2$wget[1] :
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3116 ;
|
|
assign IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3570 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_7_lat_2$wget[0] :
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d3119 ;
|
|
assign IF_m_regs_ready_7_lat_3_whas__62_THEN_m_regs_r_ETC___d374 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_7_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_7_lat_2$wget :
|
|
IF_m_regs_ready_7_lat_1_whas__66_THEN_m_regs_r_ETC___d372) ;
|
|
assign IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2677 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_8_lat_0$wget[3] :
|
|
m_regs_ready_8_rl[3] ;
|
|
assign IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2685 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_8_lat_0$wget[2] :
|
|
m_regs_ready_8_rl[2] ;
|
|
assign IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2693 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_8_lat_0$wget[1] :
|
|
m_regs_ready_8_rl[1] ;
|
|
assign IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2696 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_8_lat_0$wget[0] :
|
|
m_regs_ready_8_rl[0] ;
|
|
assign IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3128 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_8_lat_1$wget[3] :
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2677 ;
|
|
assign IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3136 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_8_lat_1$wget[2] :
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2685 ;
|
|
assign IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3144 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_8_lat_1$wget[1] :
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2693 ;
|
|
assign IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3147 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_8_lat_1$wget[0] :
|
|
IF_m_regs_ready_8_lat_0_whas__87_THEN_m_regs_r_ETC___d2696 ;
|
|
assign IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d391 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_8_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_8_lat_0$wget :
|
|
m_regs_ready_8_rl) ;
|
|
assign IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3579 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_8_lat_2$wget[3] :
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3128 ;
|
|
assign IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3587 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_8_lat_2$wget[2] :
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3136 ;
|
|
assign IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3595 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_8_lat_2$wget[1] :
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3144 ;
|
|
assign IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3598 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_8_lat_2$wget[0] :
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d3147 ;
|
|
assign IF_m_regs_ready_8_lat_3_whas__81_THEN_m_regs_r_ETC___d393 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_8_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_8_lat_2$wget :
|
|
IF_m_regs_ready_8_lat_1_whas__85_THEN_m_regs_r_ETC___d391) ;
|
|
assign IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2705 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_9_lat_0$wget[3] :
|
|
m_regs_ready_9_rl[3] ;
|
|
assign IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2713 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_9_lat_0$wget[2] :
|
|
m_regs_ready_9_rl[2] ;
|
|
assign IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2721 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_9_lat_0$wget[1] :
|
|
m_regs_ready_9_rl[1] ;
|
|
assign IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2724 =
|
|
EN_setRegReady_0_put ?
|
|
m_regs_ready_9_lat_0$wget[0] :
|
|
m_regs_ready_9_rl[0] ;
|
|
assign IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3156 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_9_lat_1$wget[3] :
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2705 ;
|
|
assign IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3164 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_9_lat_1$wget[2] :
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2713 ;
|
|
assign IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3172 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_9_lat_1$wget[1] :
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2721 ;
|
|
assign IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3175 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_9_lat_1$wget[0] :
|
|
IF_m_regs_ready_9_lat_0_whas__06_THEN_m_regs_r_ETC___d2724 ;
|
|
assign IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d410 =
|
|
EN_setRegReady_1_put ?
|
|
m_regs_ready_9_lat_1$wget :
|
|
(EN_setRegReady_0_put ?
|
|
m_regs_ready_9_lat_0$wget :
|
|
m_regs_ready_9_rl) ;
|
|
assign IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3607 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_9_lat_2$wget[3] :
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3156 ;
|
|
assign IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3615 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_9_lat_2$wget[2] :
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3164 ;
|
|
assign IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3623 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_9_lat_2$wget[1] :
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3172 ;
|
|
assign IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3626 =
|
|
EN_setRegReady_2_put ?
|
|
m_regs_ready_9_lat_2$wget[0] :
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d3175 ;
|
|
assign IF_m_regs_ready_9_lat_3_whas__00_THEN_m_regs_r_ETC___d412 =
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_9_lat_3$wget :
|
|
(EN_setRegReady_2_put ?
|
|
m_regs_ready_9_lat_2$wget :
|
|
IF_m_regs_ready_9_lat_1_whas__04_THEN_m_regs_r_ETC___d410) ;
|
|
assign IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 =
|
|
(m_tag_0[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_0[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_0[5:0] } ;
|
|
assign IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 =
|
|
(m_tag_10[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_10[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_10[5:0] } ;
|
|
assign IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 =
|
|
(m_tag_11[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_11[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_11[5:0] } ;
|
|
assign IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 =
|
|
(m_tag_12[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_12[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_12[5:0] } ;
|
|
assign IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 =
|
|
(m_tag_13[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_13[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_13[5:0] } ;
|
|
assign IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 =
|
|
(m_tag_14[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_14[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_14[5:0] } ;
|
|
assign IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936 =
|
|
(m_tag_15[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_15[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_15[5:0] } ;
|
|
assign IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 =
|
|
(m_tag_1[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_1[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_1[5:0] } ;
|
|
assign IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 =
|
|
(m_tag_2[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_2[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_2[5:0] } ;
|
|
assign IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 =
|
|
(m_tag_3[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_3[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_3[5:0] } ;
|
|
assign IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 =
|
|
(m_tag_4[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_4[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_4[5:0] } ;
|
|
assign IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 =
|
|
(m_tag_5[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_5[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_5[5:0] } ;
|
|
assign IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 =
|
|
(m_tag_6[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_6[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_6[5:0] } ;
|
|
assign IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 =
|
|
(m_tag_7[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_7[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_7[5:0] } ;
|
|
assign IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 =
|
|
(m_tag_8[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_8[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_8[5:0] } ;
|
|
assign IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 =
|
|
(m_tag_9[5:0] < x__read__h33622) ?
|
|
{ 1'd0, m_tag_9[5:0] } + 7'd64 :
|
|
{ 1'd0, m_tag_9[5:0] } ;
|
|
assign IF_m_valid_0_rl_AND_m_valid_1_rl_2_72_AND_m_va_ETC___d700 =
|
|
(m_valid_0_rl && m_valid_1_rl && m_valid_2_rl && m_valid_3_rl) ?
|
|
IF_m_valid_4_rl_3_AND_m_valid_5_rl_0_75_THEN_I_ETC___d696 :
|
|
IF_m_valid_0_rl_AND_m_valid_1_rl_2_72_THEN_IF__ETC___d699 ;
|
|
assign IF_m_valid_0_rl_AND_m_valid_1_rl_2_72_THEN_IF__ETC___d699 =
|
|
(m_valid_0_rl && m_valid_1_rl) ?
|
|
(m_valid_2_rl ? 4'd3 : 4'd2) :
|
|
(m_valid_0_rl ? 4'd1 : 4'd0) ;
|
|
assign IF_m_valid_12_rl_9_AND_m_valid_13_rl_6_82_THEN_ETC___d689 =
|
|
(m_valid_12_rl && m_valid_13_rl) ?
|
|
(m_valid_14_rl ? 4'd15 : 4'd14) :
|
|
(m_valid_12_rl ? 4'd13 : 4'd12) ;
|
|
assign IF_m_valid_4_rl_3_AND_m_valid_5_rl_0_75_THEN_I_ETC___d696 =
|
|
(m_valid_4_rl && m_valid_5_rl) ?
|
|
(m_valid_6_rl ? 4'd7 : 4'd6) :
|
|
(m_valid_4_rl ? 4'd5 : 4'd4) ;
|
|
assign IF_m_valid_8_rl_1_AND_m_valid_9_rl_8_79_AND_m__ETC___d693 =
|
|
(m_valid_8_rl && m_valid_9_rl && m_valid_10_rl &&
|
|
m_valid_11_rl) ?
|
|
IF_m_valid_12_rl_9_AND_m_valid_13_rl_6_82_THEN_ETC___d689 :
|
|
IF_m_valid_8_rl_1_AND_m_valid_9_rl_8_79_THEN_I_ETC___d692 ;
|
|
assign IF_m_valid_8_rl_1_AND_m_valid_9_rl_8_79_THEN_I_ETC___d692 =
|
|
(m_valid_8_rl && m_valid_9_rl) ?
|
|
(m_valid_10_rl ? 4'd11 : 4'd10) :
|
|
(m_valid_8_rl ? 4'd9 : 4'd8) ;
|
|
assign NOT_SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_ETC___d1108 =
|
|
{ !SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068,
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 ?
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 :
|
|
{ 1'bx /* unspecified value */ ,
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 } } ;
|
|
assign NOT_m_valid_0_rl_41_OR_NOT_m_valid_1_rl_2_42_4_ETC___d655 =
|
|
!m_valid_0_rl || !m_valid_1_rl || !m_valid_2_rl ||
|
|
!m_valid_3_rl ||
|
|
!m_valid_4_rl ||
|
|
!m_valid_5_rl ||
|
|
!m_valid_6_rl ||
|
|
!m_valid_7_rl ;
|
|
assign NOT_m_valid_8_rl_1_56_OR_NOT_m_valid_9_rl_8_57_ETC___d670 =
|
|
!m_valid_8_rl || !m_valid_9_rl || !m_valid_10_rl ||
|
|
!m_valid_11_rl ||
|
|
!m_valid_12_rl ||
|
|
!m_valid_13_rl ||
|
|
!m_valid_14_rl ||
|
|
!m_valid_15_rl ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3807 =
|
|
!setRegReady_4_put[7] && !m_regs_0[32] ||
|
|
setRegReady_4_put[7] && m_regs_0[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_0[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_0_lat_3$wget[3] :
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3355) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3815 =
|
|
!setRegReady_4_put[7] && !m_regs_0[24] ||
|
|
setRegReady_4_put[7] && m_regs_0[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_0[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_0_lat_3$wget[2] :
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3363) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3823 =
|
|
!setRegReady_4_put[7] && !m_regs_0[16] ||
|
|
setRegReady_4_put[7] && m_regs_0[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_0[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_0_lat_3$wget[1] :
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3371) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3826 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3823,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_0_lat_3$wget[0] :
|
|
IF_m_regs_ready_0_lat_2_whas__31_THEN_m_regs_r_ETC___d3374 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3835 =
|
|
!setRegReady_4_put[7] && !m_regs_1[32] ||
|
|
setRegReady_4_put[7] && m_regs_1[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_1[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_1_lat_3$wget[3] :
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3383) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3843 =
|
|
!setRegReady_4_put[7] && !m_regs_1[24] ||
|
|
setRegReady_4_put[7] && m_regs_1[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_1[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_1_lat_3$wget[2] :
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3391) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3851 =
|
|
!setRegReady_4_put[7] && !m_regs_1[16] ||
|
|
setRegReady_4_put[7] && m_regs_1[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_1[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_1_lat_3$wget[1] :
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3399) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3854 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3851,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_1_lat_3$wget[0] :
|
|
IF_m_regs_ready_1_lat_2_whas__50_THEN_m_regs_r_ETC___d3402 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3863 =
|
|
!setRegReady_4_put[7] && !m_regs_2[32] ||
|
|
setRegReady_4_put[7] && m_regs_2[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_2[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_2_lat_3$wget[3] :
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3411) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3871 =
|
|
!setRegReady_4_put[7] && !m_regs_2[24] ||
|
|
setRegReady_4_put[7] && m_regs_2[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_2[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_2_lat_3$wget[2] :
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3419) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3879 =
|
|
!setRegReady_4_put[7] && !m_regs_2[16] ||
|
|
setRegReady_4_put[7] && m_regs_2[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_2[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_2_lat_3$wget[1] :
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3427) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3882 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3879,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_2_lat_3$wget[0] :
|
|
IF_m_regs_ready_2_lat_2_whas__69_THEN_m_regs_r_ETC___d3430 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3891 =
|
|
!setRegReady_4_put[7] && !m_regs_3[32] ||
|
|
setRegReady_4_put[7] && m_regs_3[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_3[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_3_lat_3$wget[3] :
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3439) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3899 =
|
|
!setRegReady_4_put[7] && !m_regs_3[24] ||
|
|
setRegReady_4_put[7] && m_regs_3[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_3[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_3_lat_3$wget[2] :
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3447) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3907 =
|
|
!setRegReady_4_put[7] && !m_regs_3[16] ||
|
|
setRegReady_4_put[7] && m_regs_3[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_3[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_3_lat_3$wget[1] :
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3455) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3910 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3907,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_3_lat_3$wget[0] :
|
|
IF_m_regs_ready_3_lat_2_whas__88_THEN_m_regs_r_ETC___d3458 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3919 =
|
|
!setRegReady_4_put[7] && !m_regs_4[32] ||
|
|
setRegReady_4_put[7] && m_regs_4[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_4[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_4_lat_3$wget[3] :
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3467) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3927 =
|
|
!setRegReady_4_put[7] && !m_regs_4[24] ||
|
|
setRegReady_4_put[7] && m_regs_4[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_4[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_4_lat_3$wget[2] :
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3475) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3935 =
|
|
!setRegReady_4_put[7] && !m_regs_4[16] ||
|
|
setRegReady_4_put[7] && m_regs_4[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_4[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_4_lat_3$wget[1] :
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3483) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3938 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3935,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_4_lat_3$wget[0] :
|
|
IF_m_regs_ready_4_lat_2_whas__07_THEN_m_regs_r_ETC___d3486 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3947 =
|
|
!setRegReady_4_put[7] && !m_regs_5[32] ||
|
|
setRegReady_4_put[7] && m_regs_5[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_5[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_5_lat_3$wget[3] :
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3495) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3955 =
|
|
!setRegReady_4_put[7] && !m_regs_5[24] ||
|
|
setRegReady_4_put[7] && m_regs_5[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_5[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_5_lat_3$wget[2] :
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3503) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3963 =
|
|
!setRegReady_4_put[7] && !m_regs_5[16] ||
|
|
setRegReady_4_put[7] && m_regs_5[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_5[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_5_lat_3$wget[1] :
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3511) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3966 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3963,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_5_lat_3$wget[0] :
|
|
IF_m_regs_ready_5_lat_2_whas__26_THEN_m_regs_r_ETC___d3514 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3975 =
|
|
!setRegReady_4_put[7] && !m_regs_6[32] ||
|
|
setRegReady_4_put[7] && m_regs_6[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_6[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_6_lat_3$wget[3] :
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3523) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3983 =
|
|
!setRegReady_4_put[7] && !m_regs_6[24] ||
|
|
setRegReady_4_put[7] && m_regs_6[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_6[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_6_lat_3$wget[2] :
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3531) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3991 =
|
|
!setRegReady_4_put[7] && !m_regs_6[16] ||
|
|
setRegReady_4_put[7] && m_regs_6[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_6[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_6_lat_3$wget[1] :
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3539) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3994 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d3991,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_6_lat_3$wget[0] :
|
|
IF_m_regs_ready_6_lat_2_whas__45_THEN_m_regs_r_ETC___d3542 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4003 =
|
|
!setRegReady_4_put[7] && !m_regs_7[32] ||
|
|
setRegReady_4_put[7] && m_regs_7[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_7[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_7_lat_3$wget[3] :
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3551) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4011 =
|
|
!setRegReady_4_put[7] && !m_regs_7[24] ||
|
|
setRegReady_4_put[7] && m_regs_7[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_7[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_7_lat_3$wget[2] :
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3559) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4019 =
|
|
!setRegReady_4_put[7] && !m_regs_7[16] ||
|
|
setRegReady_4_put[7] && m_regs_7[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_7[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_7_lat_3$wget[1] :
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3567) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4022 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4019,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_7_lat_3$wget[0] :
|
|
IF_m_regs_ready_7_lat_2_whas__64_THEN_m_regs_r_ETC___d3570 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4031 =
|
|
!setRegReady_4_put[7] && !m_regs_8[32] ||
|
|
setRegReady_4_put[7] && m_regs_8[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_8[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_8_lat_3$wget[3] :
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3579) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4039 =
|
|
!setRegReady_4_put[7] && !m_regs_8[24] ||
|
|
setRegReady_4_put[7] && m_regs_8[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_8[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_8_lat_3$wget[2] :
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3587) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4047 =
|
|
!setRegReady_4_put[7] && !m_regs_8[16] ||
|
|
setRegReady_4_put[7] && m_regs_8[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_8[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_8_lat_3$wget[1] :
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3595) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4050 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4047,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_8_lat_3$wget[0] :
|
|
IF_m_regs_ready_8_lat_2_whas__83_THEN_m_regs_r_ETC___d3598 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4059 =
|
|
!setRegReady_4_put[7] && !m_regs_9[32] ||
|
|
setRegReady_4_put[7] && m_regs_9[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_9[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_9_lat_3$wget[3] :
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3607) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4067 =
|
|
!setRegReady_4_put[7] && !m_regs_9[24] ||
|
|
setRegReady_4_put[7] && m_regs_9[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_9[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_9_lat_3$wget[2] :
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3615) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4075 =
|
|
!setRegReady_4_put[7] && !m_regs_9[16] ||
|
|
setRegReady_4_put[7] && m_regs_9[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_9[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_9_lat_3$wget[1] :
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3623) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4078 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4075,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_9_lat_3$wget[0] :
|
|
IF_m_regs_ready_9_lat_2_whas__02_THEN_m_regs_r_ETC___d3626 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4087 =
|
|
!setRegReady_4_put[7] && !m_regs_10[32] ||
|
|
setRegReady_4_put[7] && m_regs_10[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_10[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_10_lat_3$wget[3] :
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3635) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4095 =
|
|
!setRegReady_4_put[7] && !m_regs_10[24] ||
|
|
setRegReady_4_put[7] && m_regs_10[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_10[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_10_lat_3$wget[2] :
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3643) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4103 =
|
|
!setRegReady_4_put[7] && !m_regs_10[16] ||
|
|
setRegReady_4_put[7] && m_regs_10[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_10[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_10_lat_3$wget[1] :
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3651) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4106 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4103,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_10_lat_3$wget[0] :
|
|
IF_m_regs_ready_10_lat_2_whas__21_THEN_m_regs__ETC___d3654 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4115 =
|
|
!setRegReady_4_put[7] && !m_regs_11[32] ||
|
|
setRegReady_4_put[7] && m_regs_11[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_11[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_11_lat_3$wget[3] :
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3663) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4123 =
|
|
!setRegReady_4_put[7] && !m_regs_11[24] ||
|
|
setRegReady_4_put[7] && m_regs_11[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_11[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_11_lat_3$wget[2] :
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3671) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4131 =
|
|
!setRegReady_4_put[7] && !m_regs_11[16] ||
|
|
setRegReady_4_put[7] && m_regs_11[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_11[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_11_lat_3$wget[1] :
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3679) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4134 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4131,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_11_lat_3$wget[0] :
|
|
IF_m_regs_ready_11_lat_2_whas__40_THEN_m_regs__ETC___d3682 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4143 =
|
|
!setRegReady_4_put[7] && !m_regs_12[32] ||
|
|
setRegReady_4_put[7] && m_regs_12[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_12[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_12_lat_3$wget[3] :
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3691) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4151 =
|
|
!setRegReady_4_put[7] && !m_regs_12[24] ||
|
|
setRegReady_4_put[7] && m_regs_12[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_12[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_12_lat_3$wget[2] :
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3699) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4159 =
|
|
!setRegReady_4_put[7] && !m_regs_12[16] ||
|
|
setRegReady_4_put[7] && m_regs_12[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_12[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_12_lat_3$wget[1] :
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3707) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4162 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4159,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_12_lat_3$wget[0] :
|
|
IF_m_regs_ready_12_lat_2_whas__59_THEN_m_regs__ETC___d3710 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4171 =
|
|
!setRegReady_4_put[7] && !m_regs_13[32] ||
|
|
setRegReady_4_put[7] && m_regs_13[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_13[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_13_lat_3$wget[3] :
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3719) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4179 =
|
|
!setRegReady_4_put[7] && !m_regs_13[24] ||
|
|
setRegReady_4_put[7] && m_regs_13[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_13[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_13_lat_3$wget[2] :
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3727) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4187 =
|
|
!setRegReady_4_put[7] && !m_regs_13[16] ||
|
|
setRegReady_4_put[7] && m_regs_13[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_13[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_13_lat_3$wget[1] :
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3735) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4190 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4187,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_13_lat_3$wget[0] :
|
|
IF_m_regs_ready_13_lat_2_whas__78_THEN_m_regs__ETC___d3738 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4199 =
|
|
!setRegReady_4_put[7] && !m_regs_14[32] ||
|
|
setRegReady_4_put[7] && m_regs_14[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_14[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_14_lat_3$wget[3] :
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3747) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4207 =
|
|
!setRegReady_4_put[7] && !m_regs_14[24] ||
|
|
setRegReady_4_put[7] && m_regs_14[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_14[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_14_lat_3$wget[2] :
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3755) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4215 =
|
|
!setRegReady_4_put[7] && !m_regs_14[16] ||
|
|
setRegReady_4_put[7] && m_regs_14[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_14[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_14_lat_3$wget[1] :
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3763) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4218 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4215,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_14_lat_3$wget[0] :
|
|
IF_m_regs_ready_14_lat_2_whas__97_THEN_m_regs__ETC___d3766 } ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4227 =
|
|
!setRegReady_4_put[7] && !m_regs_15[32] ||
|
|
setRegReady_4_put[7] && m_regs_15[32] &&
|
|
setRegReady_4_put[6:0] == m_regs_15[31:25] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_15_lat_3$wget[3] :
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3775) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4235 =
|
|
!setRegReady_4_put[7] && !m_regs_15[24] ||
|
|
setRegReady_4_put[7] && m_regs_15[24] &&
|
|
setRegReady_4_put[6:0] == m_regs_15[23:17] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_15_lat_3$wget[2] :
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3783) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4243 =
|
|
!setRegReady_4_put[7] && !m_regs_15[16] ||
|
|
setRegReady_4_put[7] && m_regs_15[16] &&
|
|
setRegReady_4_put[6:0] == m_regs_15[15:9] ||
|
|
(EN_setRegReady_3_put ?
|
|
m_regs_ready_15_lat_3$wget[1] :
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3791) ;
|
|
assign NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4246 =
|
|
{ NOT_setRegReady_4_put_BIT_7_797_798_AND_NOT_m__ETC___d4243,
|
|
EN_setRegReady_3_put ?
|
|
m_regs_ready_15_lat_3$wget[0] :
|
|
IF_m_regs_ready_15_lat_2_whas__16_THEN_m_regs__ETC___d3794 } ;
|
|
assign a__h54195 =
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 ?
|
|
b__h54214 :
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d966 ;
|
|
assign a__h54213 =
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 ?
|
|
b__h54226 :
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d942 ;
|
|
assign a__h54225 =
|
|
(!m_valid_0_rl || !m_ready_wire_0$wget) ?
|
|
4'd1 :
|
|
IF_NOT_m_valid_1_rl_2_42_OR_NOT_m_ready_wire_1_ETC___d845 ;
|
|
assign a__h58090 =
|
|
(!m_valid_4_rl || !m_ready_wire_4$wget) ?
|
|
4'd5 :
|
|
IF_NOT_m_valid_5_rl_0_49_OR_NOT_m_ready_wire_5_ETC___d947 ;
|
|
assign a__h58594 =
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 ?
|
|
b__h58607 :
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d983 ;
|
|
assign a__h58606 =
|
|
(!m_valid_8_rl || !m_ready_wire_8$wget) ?
|
|
4'd9 :
|
|
IF_NOT_m_valid_9_rl_8_57_OR_NOT_m_ready_wire_9_ETC___d971 ;
|
|
assign a__h58999 =
|
|
(!m_valid_12_rl || !m_ready_wire_12$wget) ?
|
|
4'd13 :
|
|
IF_NOT_m_valid_13_rl_6_64_OR_NOT_m_ready_wire__ETC___d988 ;
|
|
assign b__h54196 =
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 ?
|
|
b__h58595 :
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1007 ;
|
|
assign b__h54214 =
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 ?
|
|
b__h58091 :
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d959 ;
|
|
assign b__h54226 =
|
|
(!m_valid_2_rl || !m_ready_wire_2$wget) ?
|
|
4'd3 :
|
|
IF_NOT_m_valid_3_rl_6_45_OR_NOT_m_ready_wire_3_ETC___d862 ;
|
|
assign b__h58091 =
|
|
(!m_valid_6_rl || !m_ready_wire_6$wget) ?
|
|
4'd7 :
|
|
IF_NOT_m_valid_7_rl_4_52_OR_NOT_m_ready_wire_7_ETC___d952 ;
|
|
assign b__h58595 =
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 ?
|
|
b__h59000 :
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1000 ;
|
|
assign b__h58607 =
|
|
(!m_valid_10_rl || !m_ready_wire_10$wget) ?
|
|
4'd11 :
|
|
IF_NOT_m_valid_11_rl_2_60_OR_NOT_m_ready_wire__ETC___d976 ;
|
|
assign b__h59000 =
|
|
(!m_valid_14_rl || !m_ready_wire_14$wget) ?
|
|
4'd15 :
|
|
IF_NOT_m_valid_15_rl_10_67_OR_NOT_m_ready_wire_ETC___d993 ;
|
|
assign idx__h53445 =
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 ?
|
|
b__h54196 :
|
|
IF_SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready__ETC___d1014 ;
|
|
assign m_valid_0_rl_AND_m_valid_1_rl_2_72_AND_m_valid_ETC___d678 =
|
|
m_valid_0_rl && m_valid_1_rl && m_valid_2_rl && m_valid_3_rl &&
|
|
m_valid_4_rl &&
|
|
m_valid_5_rl &&
|
|
m_valid_6_rl &&
|
|
m_valid_7_rl ;
|
|
assign m_valid_3_rl_6_AND_m_valid_4_rl_3_AND_m_valid__ETC___d4258 =
|
|
m_valid_3_rl && m_valid_4_rl && m_valid_5_rl && m_valid_6_rl &&
|
|
m_valid_7_rl &&
|
|
m_valid_8_rl &&
|
|
m_valid_9_rl_8_AND_m_valid_10_rl_5_AND_m_valid_ETC___d4252 ;
|
|
assign m_valid_9_rl_8_AND_m_valid_10_rl_5_AND_m_valid_ETC___d4252 =
|
|
m_valid_9_rl && m_valid_10_rl && m_valid_11_rl &&
|
|
m_valid_12_rl &&
|
|
m_valid_13_rl &&
|
|
m_valid_14_rl &&
|
|
m_valid_15_rl ;
|
|
assign n__read__h100114 =
|
|
m_valid_7_lat_1$whas ? enq_x[20:9] : m_spec_bits_7_rl ;
|
|
assign n__read__h100243 =
|
|
m_valid_8_lat_1$whas ? enq_x[20:9] : m_spec_bits_8_rl ;
|
|
assign n__read__h100372 =
|
|
m_valid_9_lat_1$whas ? enq_x[20:9] : m_spec_bits_9_rl ;
|
|
assign n__read__h100501 =
|
|
m_valid_10_lat_1$whas ? enq_x[20:9] : m_spec_bits_10_rl ;
|
|
assign n__read__h100630 =
|
|
m_valid_11_lat_1$whas ? enq_x[20:9] : m_spec_bits_11_rl ;
|
|
assign n__read__h100759 =
|
|
m_valid_12_lat_1$whas ? enq_x[20:9] : m_spec_bits_12_rl ;
|
|
assign n__read__h100888 =
|
|
m_valid_13_lat_1$whas ? enq_x[20:9] : m_spec_bits_13_rl ;
|
|
assign n__read__h101017 =
|
|
m_valid_14_lat_1$whas ? enq_x[20:9] : m_spec_bits_14_rl ;
|
|
assign n__read__h101134 =
|
|
m_valid_15_lat_1$whas ? enq_x[20:9] : m_spec_bits_15_rl ;
|
|
assign n__read__h99211 =
|
|
m_valid_0_lat_1$whas ? enq_x[20:9] : m_spec_bits_0_rl ;
|
|
assign n__read__h99340 =
|
|
m_valid_1_lat_1$whas ? enq_x[20:9] : m_spec_bits_1_rl ;
|
|
assign n__read__h99469 =
|
|
m_valid_2_lat_1$whas ? enq_x[20:9] : m_spec_bits_2_rl ;
|
|
assign n__read__h99598 =
|
|
m_valid_3_lat_1$whas ? enq_x[20:9] : m_spec_bits_3_rl ;
|
|
assign n__read__h99727 =
|
|
m_valid_4_lat_1$whas ? enq_x[20:9] : m_spec_bits_4_rl ;
|
|
assign n__read__h99856 =
|
|
m_valid_5_lat_1$whas ? enq_x[20:9] : m_spec_bits_5_rl ;
|
|
assign n__read__h99985 =
|
|
m_valid_6_lat_1$whas ? enq_x[20:9] : m_spec_bits_6_rl ;
|
|
assign upd__h11253 = n__read__h99211 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h11598 = n__read__h99340 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h11943 = n__read__h99469 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h12288 = n__read__h99598 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h12633 = n__read__h99727 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h12978 = n__read__h99856 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h13323 = n__read__h99985 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h13668 = n__read__h100114 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h14013 = n__read__h100243 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h14358 = n__read__h100372 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h14703 = n__read__h100501 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h15048 = n__read__h100630 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h15393 = n__read__h100759 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h15738 = n__read__h100888 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h16083 = n__read__h101017 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h16428 = n__read__h101134 & specUpdate_correctSpeculation_mask ;
|
|
assign x__read__h33622 = EN_setRobEnqTime ? setRobEnqTime_t : 6'd0 ;
|
|
always@(a__h54225 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (a__h54225)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d938 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(b__h54226 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (b__h54226)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d939 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(a__h58090 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (a__h58090)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d955 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(b__h58091 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (b__h58091)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d956 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(a__h58606 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (a__h58606)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d979 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(b__h58607 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (b__h58607)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d980 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(a__h58999 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (a__h58999)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d996 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(b__h54226 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (b__h54226)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d864 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(a__h54225 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (a__h54225)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d847 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(b__h58091 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (b__h58091)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d954 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(a__h58090 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (a__h58090)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d949 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(a__h54213 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (a__h54213)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d962 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(b__h54214 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (b__h54214)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d961 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(b__h54214 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (b__h54214)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d963 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(a__h54213 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (a__h54213)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d944 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(b__h58607 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (b__h58607)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d978 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(a__h58606 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (a__h58606)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d973 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(b__h59000 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (b__h59000)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d995 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(b__h59000 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (b__h59000)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d997 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(a__h58999 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (a__h58999)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d990 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(a__h58594 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (a__h58594)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1003 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(b__h58595 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (b__h58595)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1002 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(b__h58595 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (b__h58595)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1004 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(a__h58594 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (a__h58594)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d985 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(a__h54195 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (a__h54195)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1010 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(b__h54196 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (b__h54196)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d1009 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(b__h54196 or
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836 or
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842 or
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853 or
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859 or
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870 or
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876 or
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882 or
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888 or
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894 or
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900 or
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906 or
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912 or
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918 or
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924 or
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930 or
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936)
|
|
begin
|
|
case (b__h54196)
|
|
4'd0:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m_robEnqTi_ETC___d836;
|
|
4'd1:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_1_37_BITS_5_TO_0_38_ULT_IF_m_robEnqTi_ETC___d842;
|
|
4'd2:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_2_48_BITS_5_TO_0_49_ULT_IF_m_robEnqTi_ETC___d853;
|
|
4'd3:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_3_54_BITS_5_TO_0_55_ULT_IF_m_robEnqTi_ETC___d859;
|
|
4'd4:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_4_65_BITS_5_TO_0_66_ULT_IF_m_robEnqTi_ETC___d870;
|
|
4'd5:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_5_71_BITS_5_TO_0_72_ULT_IF_m_robEnqTi_ETC___d876;
|
|
4'd6:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_6_77_BITS_5_TO_0_78_ULT_IF_m_robEnqTi_ETC___d882;
|
|
4'd7:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_7_83_BITS_5_TO_0_84_ULT_IF_m_robEnqTi_ETC___d888;
|
|
4'd8:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_8_89_BITS_5_TO_0_90_ULT_IF_m_robEnqTi_ETC___d894;
|
|
4'd9:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_9_95_BITS_5_TO_0_96_ULT_IF_m_robEnqTi_ETC___d900;
|
|
4'd10:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_10_01_BITS_5_TO_0_02_ULT_IF_m_robEnqT_ETC___d906;
|
|
4'd11:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_11_07_BITS_5_TO_0_08_ULT_IF_m_robEnqT_ETC___d912;
|
|
4'd12:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_12_13_BITS_5_TO_0_14_ULT_IF_m_robEnqT_ETC___d918;
|
|
4'd13:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_13_19_BITS_5_TO_0_20_ULT_IF_m_robEnqT_ETC___d924;
|
|
4'd14:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_14_25_BITS_5_TO_0_26_ULT_IF_m_robEnqT_ETC___d930;
|
|
4'd15:
|
|
SEL_ARR_IF_m_tag_0_28_BITS_5_TO_0_29_ULT_IF_m__ETC___d1011 =
|
|
IF_m_tag_15_31_BITS_5_TO_0_32_ULT_IF_m_robEnqT_ETC___d936;
|
|
endcase
|
|
end
|
|
always@(a__h54195 or
|
|
m_valid_0_rl or
|
|
m_ready_wire_0$wget or
|
|
m_valid_1_rl or
|
|
m_ready_wire_1$wget or
|
|
m_valid_2_rl or
|
|
m_ready_wire_2$wget or
|
|
m_valid_3_rl or
|
|
m_ready_wire_3$wget or
|
|
m_valid_4_rl or
|
|
m_ready_wire_4$wget or
|
|
m_valid_5_rl or
|
|
m_ready_wire_5$wget or
|
|
m_valid_6_rl or
|
|
m_ready_wire_6$wget or
|
|
m_valid_7_rl or
|
|
m_ready_wire_7$wget or
|
|
m_valid_8_rl or
|
|
m_ready_wire_8$wget or
|
|
m_valid_9_rl or
|
|
m_ready_wire_9$wget or
|
|
m_valid_10_rl or
|
|
m_ready_wire_10$wget or
|
|
m_valid_11_rl or
|
|
m_ready_wire_11$wget or
|
|
m_valid_12_rl or
|
|
m_ready_wire_12$wget or
|
|
m_valid_13_rl or
|
|
m_ready_wire_13$wget or
|
|
m_valid_14_rl or
|
|
m_ready_wire_14$wget or m_valid_15_rl or m_ready_wire_15$wget)
|
|
begin
|
|
case (a__h54195)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_0_rl || !m_ready_wire_0$wget;
|
|
4'd1:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_1_rl || !m_ready_wire_1$wget;
|
|
4'd2:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_2_rl || !m_ready_wire_2$wget;
|
|
4'd3:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_3_rl || !m_ready_wire_3$wget;
|
|
4'd4:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_4_rl || !m_ready_wire_4$wget;
|
|
4'd5:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_5_rl || !m_ready_wire_5$wget;
|
|
4'd6:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_6_rl || !m_ready_wire_6$wget;
|
|
4'd7:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_7_rl || !m_ready_wire_7$wget;
|
|
4'd8:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_8_rl || !m_ready_wire_8$wget;
|
|
4'd9:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_9_rl || !m_ready_wire_9$wget;
|
|
4'd10:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_10_rl || !m_ready_wire_10$wget;
|
|
4'd11:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_11_rl || !m_ready_wire_11$wget;
|
|
4'd12:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_12_rl || !m_ready_wire_12$wget;
|
|
4'd13:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_13_rl || !m_ready_wire_13$wget;
|
|
4'd14:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_14_rl || !m_ready_wire_14$wget;
|
|
4'd15:
|
|
SEL_ARR_NOT_m_valid_0_rl_41_OR_NOT_m_ready_wir_ETC___d968 =
|
|
!m_valid_15_rl || !m_ready_wire_15$wget;
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0: x__h62947 = m_data_0[12:7];
|
|
4'd1: x__h62947 = m_data_1[12:7];
|
|
4'd2: x__h62947 = m_data_2[12:7];
|
|
4'd3: x__h62947 = m_data_3[12:7];
|
|
4'd4: x__h62947 = m_data_4[12:7];
|
|
4'd5: x__h62947 = m_data_5[12:7];
|
|
4'd6: x__h62947 = m_data_6[12:7];
|
|
4'd7: x__h62947 = m_data_7[12:7];
|
|
4'd8: x__h62947 = m_data_8[12:7];
|
|
4'd9: x__h62947 = m_data_9[12:7];
|
|
4'd10: x__h62947 = m_data_10[12:7];
|
|
4'd11: x__h62947 = m_data_11[12:7];
|
|
4'd12: x__h62947 = m_data_12[12:7];
|
|
4'd13: x__h62947 = m_data_13[12:7];
|
|
4'd14: x__h62947 = m_data_14[12:7];
|
|
4'd15: x__h62947 = m_data_15[12:7];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0: x__h62980 = m_data_0[6:1];
|
|
4'd1: x__h62980 = m_data_1[6:1];
|
|
4'd2: x__h62980 = m_data_2[6:1];
|
|
4'd3: x__h62980 = m_data_3[6:1];
|
|
4'd4: x__h62980 = m_data_4[6:1];
|
|
4'd5: x__h62980 = m_data_5[6:1];
|
|
4'd6: x__h62980 = m_data_6[6:1];
|
|
4'd7: x__h62980 = m_data_7[6:1];
|
|
4'd8: x__h62980 = m_data_8[6:1];
|
|
4'd9: x__h62980 = m_data_9[6:1];
|
|
4'd10: x__h62980 = m_data_10[6:1];
|
|
4'd11: x__h62980 = m_data_11[6:1];
|
|
4'd12: x__h62980 = m_data_12[6:1];
|
|
4'd13: x__h62980 = m_data_13[6:1];
|
|
4'd14: x__h62980 = m_data_14[6:1];
|
|
4'd15: x__h62980 = m_data_15[6:1];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_0[53];
|
|
4'd1:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_1[53];
|
|
4'd2:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_2[53];
|
|
4'd3:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_3[53];
|
|
4'd4:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_4[53];
|
|
4'd5:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_5[53];
|
|
4'd6:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_6[53];
|
|
4'd7:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_7[53];
|
|
4'd8:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_8[53];
|
|
4'd9:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_9[53];
|
|
4'd10:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_10[53];
|
|
4'd11:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_11[53];
|
|
4'd12:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_12[53];
|
|
4'd13:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_13[53];
|
|
4'd14:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_14[53];
|
|
4'd15:
|
|
SEL_ARR_NOT_m_data_0_46_BIT_53_035_036_NOT_m_d_ETC___d1068 =
|
|
!m_data_15[53];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_0[32];
|
|
4'd1:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_1[32];
|
|
4'd2:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_2[32];
|
|
4'd3:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_3[32];
|
|
4'd4:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_4[32];
|
|
4'd5:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_5[32];
|
|
4'd6:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_6[32];
|
|
4'd7:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_7[32];
|
|
4'd8:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_8[32];
|
|
4'd9:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_9[32];
|
|
4'd10:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_10[32];
|
|
4'd11:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_11[32];
|
|
4'd12:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_12[32];
|
|
4'd13:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_13[32];
|
|
4'd14:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_14[32];
|
|
4'd15:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_32_721_722_NOT_m__ETC___d1769 =
|
|
!m_regs_15[32];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_0[24];
|
|
4'd1:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_1[24];
|
|
4'd2:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_2[24];
|
|
4'd3:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_3[24];
|
|
4'd4:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_4[24];
|
|
4'd5:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_5[24];
|
|
4'd6:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_6[24];
|
|
4'd7:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_7[24];
|
|
4'd8:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_8[24];
|
|
4'd9:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_9[24];
|
|
4'd10:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_10[24];
|
|
4'd11:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_11[24];
|
|
4'd12:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_12[24];
|
|
4'd13:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_13[24];
|
|
4'd14:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_14[24];
|
|
4'd15:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_24_790_791_NOT_m__ETC___d1823 =
|
|
!m_regs_15[24];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_0[16];
|
|
4'd1:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_1[16];
|
|
4'd2:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_2[16];
|
|
4'd3:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_3[16];
|
|
4'd4:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_4[16];
|
|
4'd5:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_5[16];
|
|
4'd6:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_6[16];
|
|
4'd7:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_7[16];
|
|
4'd8:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_8[16];
|
|
4'd9:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_9[16];
|
|
4'd10:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_10[16];
|
|
4'd11:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_11[16];
|
|
4'd12:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_12[16];
|
|
4'd13:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_13[16];
|
|
4'd14:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_14[16];
|
|
4'd15:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_16_845_846_NOT_m__ETC___d1878 =
|
|
!m_regs_15[16];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_0[8];
|
|
4'd1:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_1[8];
|
|
4'd2:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_2[8];
|
|
4'd3:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_3[8];
|
|
4'd4:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_4[8];
|
|
4'd5:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_5[8];
|
|
4'd6:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_6[8];
|
|
4'd7:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_7[8];
|
|
4'd8:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_8[8];
|
|
4'd9:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_9[8];
|
|
4'd10:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_10[8];
|
|
4'd11:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_11[8];
|
|
4'd12:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_12[8];
|
|
4'd13:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_13[8];
|
|
4'd14:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_14[8];
|
|
4'd15:
|
|
SEL_ARR_NOT_m_regs_0_720_BIT_8_899_900_NOT_m_r_ETC___d1932 =
|
|
!m_regs_15[8];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_spec_tag_0 or
|
|
m_spec_tag_1 or
|
|
m_spec_tag_2 or
|
|
m_spec_tag_3 or
|
|
m_spec_tag_4 or
|
|
m_spec_tag_5 or
|
|
m_spec_tag_6 or
|
|
m_spec_tag_7 or
|
|
m_spec_tag_8 or
|
|
m_spec_tag_9 or
|
|
m_spec_tag_10 or
|
|
m_spec_tag_11 or
|
|
m_spec_tag_12 or m_spec_tag_13 or m_spec_tag_14 or m_spec_tag_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_0[4];
|
|
4'd1:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_1[4];
|
|
4'd2:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_2[4];
|
|
4'd3:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_3[4];
|
|
4'd4:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_4[4];
|
|
4'd5:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_5[4];
|
|
4'd6:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_6[4];
|
|
4'd7:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_7[4];
|
|
4'd8:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_8[4];
|
|
4'd9:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_9[4];
|
|
4'd10:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_10[4];
|
|
4'd11:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_11[4];
|
|
4'd12:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_12[4];
|
|
4'd13:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_13[4];
|
|
4'd14:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_14[4];
|
|
4'd15:
|
|
SEL_ARR_NOT_m_spec_tag_0_015_BIT_4_016_017_NOT_ETC___d2064 =
|
|
!m_spec_tag_15[4];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_tag_0 or
|
|
m_tag_1 or
|
|
m_tag_2 or
|
|
m_tag_3 or
|
|
m_tag_4 or
|
|
m_tag_5 or
|
|
m_tag_6 or
|
|
m_tag_7 or
|
|
m_tag_8 or
|
|
m_tag_9 or
|
|
m_tag_10 or
|
|
m_tag_11 or m_tag_12 or m_tag_13 or m_tag_14 or m_tag_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_0[11];
|
|
4'd1:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_1[11];
|
|
4'd2:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_2[11];
|
|
4'd3:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_3[11];
|
|
4'd4:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_4[11];
|
|
4'd5:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_5[11];
|
|
4'd6:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_6[11];
|
|
4'd7:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_7[11];
|
|
4'd8:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_8[11];
|
|
4'd9:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_9[11];
|
|
4'd10:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_10[11];
|
|
4'd11:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_11[11];
|
|
4'd12:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_12[11];
|
|
4'd13:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_13[11];
|
|
4'd14:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_14[11];
|
|
4'd15:
|
|
SEL_ARR_m_tag_0_28_BIT_11_974_m_tag_1_37_BIT_1_ETC___d1991 =
|
|
m_tag_15[11];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_0[51:48];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_1[51:48];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_2[51:48];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_3[51:48];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_4[51:48];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_5[51:48];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_6[51:48];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_7[51:48];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_8[51:48];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_9[51:48];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_10[51:48];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_11[51:48];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_12[51:48];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_13[51:48];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_14[51:48];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BITS_51_TO_48_088_m_data_1_ETC___d1105 =
|
|
m_data_15[51:48];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_0[52:48];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_1[52:48];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_2[52:48];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_3[52:48];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_4[52:48];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_5[52:48];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_6[52:48];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_7[52:48];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_8[52:48];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_9[52:48];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_10[52:48];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_11[52:48];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_12[52:48];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_13[52:48];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_14[52:48];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BITS_52_TO_48_070_m_data_1_ETC___d1087 =
|
|
m_data_15[52:48];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_0[23:17];
|
|
4'd1:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_1[23:17];
|
|
4'd2:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_2[23:17];
|
|
4'd3:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_3[23:17];
|
|
4'd4:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_4[23:17];
|
|
4'd5:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_5[23:17];
|
|
4'd6:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_6[23:17];
|
|
4'd7:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_7[23:17];
|
|
4'd8:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_8[23:17];
|
|
4'd9:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_9[23:17];
|
|
4'd10:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_10[23:17];
|
|
4'd11:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_11[23:17];
|
|
4'd12:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_12[23:17];
|
|
4'd13:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_13[23:17];
|
|
4'd14:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_14[23:17];
|
|
4'd15:
|
|
SEL_ARR_m_regs_0_720_BITS_23_TO_17_825_m_regs__ETC___d1842 =
|
|
m_regs_15[23:17];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_0[7:1];
|
|
4'd1:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_1[7:1];
|
|
4'd2:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_2[7:1];
|
|
4'd3:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_3[7:1];
|
|
4'd4:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_4[7:1];
|
|
4'd5:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_5[7:1];
|
|
4'd6:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_6[7:1];
|
|
4'd7:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_7[7:1];
|
|
4'd8:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_8[7:1];
|
|
4'd9:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_9[7:1];
|
|
4'd10:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_10[7:1];
|
|
4'd11:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_11[7:1];
|
|
4'd12:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_12[7:1];
|
|
4'd13:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_13[7:1];
|
|
4'd14:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_14[7:1];
|
|
4'd15:
|
|
SEL_ARR_m_regs_0_720_BITS_7_TO_1_934_m_regs_1__ETC___d1951 =
|
|
m_regs_15[7:1];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_0[0];
|
|
4'd1:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_1[0];
|
|
4'd2:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_2[0];
|
|
4'd3:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_3[0];
|
|
4'd4:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_4[0];
|
|
4'd5:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_5[0];
|
|
4'd6:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_6[0];
|
|
4'd7:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_7[0];
|
|
4'd8:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_8[0];
|
|
4'd9:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_9[0];
|
|
4'd10:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_10[0];
|
|
4'd11:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_11[0];
|
|
4'd12:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_12[0];
|
|
4'd13:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_13[0];
|
|
4'd14:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_14[0];
|
|
4'd15:
|
|
SEL_ARR_m_regs_0_720_BIT_0_952_m_regs_1_723_BI_ETC___d1969 =
|
|
m_regs_15[0];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_spec_tag_0 or
|
|
m_spec_tag_1 or
|
|
m_spec_tag_2 or
|
|
m_spec_tag_3 or
|
|
m_spec_tag_4 or
|
|
m_spec_tag_5 or
|
|
m_spec_tag_6 or
|
|
m_spec_tag_7 or
|
|
m_spec_tag_8 or
|
|
m_spec_tag_9 or
|
|
m_spec_tag_10 or
|
|
m_spec_tag_11 or
|
|
m_spec_tag_12 or m_spec_tag_13 or m_spec_tag_14 or m_spec_tag_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_0[3:0];
|
|
4'd1:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_1[3:0];
|
|
4'd2:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_2[3:0];
|
|
4'd3:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_3[3:0];
|
|
4'd4:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_4[3:0];
|
|
4'd5:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_5[3:0];
|
|
4'd6:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_6[3:0];
|
|
4'd7:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_7[3:0];
|
|
4'd8:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_8[3:0];
|
|
4'd9:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_9[3:0];
|
|
4'd10:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_10[3:0];
|
|
4'd11:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_11[3:0];
|
|
4'd12:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_12[3:0];
|
|
4'd13:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_13[3:0];
|
|
4'd14:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_14[3:0];
|
|
4'd15:
|
|
SEL_ARR_m_spec_tag_0_015_BITS_3_TO_0_066_m_spe_ETC___d2083 =
|
|
m_spec_tag_15[3:0];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_tag_0 or
|
|
m_tag_1 or
|
|
m_tag_2 or
|
|
m_tag_3 or
|
|
m_tag_4 or
|
|
m_tag_5 or
|
|
m_tag_6 or
|
|
m_tag_7 or
|
|
m_tag_8 or
|
|
m_tag_9 or
|
|
m_tag_10 or
|
|
m_tag_11 or m_tag_12 or m_tag_13 or m_tag_14 or m_tag_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_0[10:6];
|
|
4'd1:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_1[10:6];
|
|
4'd2:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_2[10:6];
|
|
4'd3:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_3[10:6];
|
|
4'd4:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_4[10:6];
|
|
4'd5:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_5[10:6];
|
|
4'd6:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_6[10:6];
|
|
4'd7:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_7[10:6];
|
|
4'd8:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_8[10:6];
|
|
4'd9:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_9[10:6];
|
|
4'd10:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_10[10:6];
|
|
4'd11:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_11[10:6];
|
|
4'd12:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_12[10:6];
|
|
4'd13:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_13[10:6];
|
|
4'd14:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_14[10:6];
|
|
4'd15:
|
|
SEL_ARR_m_tag_0_28_BITS_10_TO_6_992_m_tag_1_37_ETC___d2009 =
|
|
m_tag_15[10:6];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_tag_0 or
|
|
m_tag_1 or
|
|
m_tag_2 or
|
|
m_tag_3 or
|
|
m_tag_4 or
|
|
m_tag_5 or
|
|
m_tag_6 or
|
|
m_tag_7 or
|
|
m_tag_8 or
|
|
m_tag_9 or
|
|
m_tag_10 or
|
|
m_tag_11 or m_tag_12 or m_tag_13 or m_tag_14 or m_tag_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_0[5:0];
|
|
4'd1:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_1[5:0];
|
|
4'd2:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_2[5:0];
|
|
4'd3:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_3[5:0];
|
|
4'd4:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_4[5:0];
|
|
4'd5:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_5[5:0];
|
|
4'd6:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_6[5:0];
|
|
4'd7:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_7[5:0];
|
|
4'd8:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_8[5:0];
|
|
4'd9:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_9[5:0];
|
|
4'd10:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_10[5:0];
|
|
4'd11:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_11[5:0];
|
|
4'd12:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_12[5:0];
|
|
4'd13:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_13[5:0];
|
|
4'd14:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_14[5:0];
|
|
4'd15:
|
|
SEL_ARR_m_tag_0_28_BITS_5_TO_0_29_m_tag_1_37_B_ETC___d2011 =
|
|
m_tag_15[5:0];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_0[13];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_1[13];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_2[13];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_3[13];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_4[13];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_5[13];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_6[13];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_7[13];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_8[13];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_9[13];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_10[13];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_11[13];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_12[13];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_13[13];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_14[13];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_13_631_m_data_1_48_BIT_ETC___d1648 =
|
|
m_data_15[13];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_0[15:9];
|
|
4'd1:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_1[15:9];
|
|
4'd2:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_2[15:9];
|
|
4'd3:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_3[15:9];
|
|
4'd4:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_4[15:9];
|
|
4'd5:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_5[15:9];
|
|
4'd6:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_6[15:9];
|
|
4'd7:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_7[15:9];
|
|
4'd8:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_8[15:9];
|
|
4'd9:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_9[15:9];
|
|
4'd10:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_10[15:9];
|
|
4'd11:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_11[15:9];
|
|
4'd12:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_12[15:9];
|
|
4'd13:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_13[15:9];
|
|
4'd14:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_14[15:9];
|
|
4'd15:
|
|
SEL_ARR_m_regs_0_720_BITS_15_TO_9_880_m_regs_1_ETC___d1897 =
|
|
m_regs_15[15:9];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_0[19:17];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_1[19:17];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_2[19:17];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_3[19:17];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_4[19:17];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_5[19:17];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_6[19:17];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_7[19:17];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_8[19:17];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_9[19:17];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_10[19:17];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_11[19:17];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_12[19:17];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_13[19:17];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_14[19:17];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BITS_19_TO_17_595_m_data_1_ETC___d1612 =
|
|
m_data_15[19:17];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_0[16:14];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_1[16:14];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_2[16:14];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_3[16:14];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_4[16:14];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_5[16:14];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_6[16:14];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_7[16:14];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_8[16:14];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_9[16:14];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_10[16:14];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_11[16:14];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_12[16:14];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_13[16:14];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_14[16:14];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BITS_16_TO_14_613_m_data_1_ETC___d1630 =
|
|
m_data_15[16:14];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_0[22];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_1[22];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_2[22];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_3[22];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_4[22];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_5[22];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_6[22];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_7[22];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_8[22];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_9[22];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_10[22];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_11[22];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_12[22];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_13[22];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_14[22];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_22_559_m_data_1_48_BIT_ETC___d1576 =
|
|
m_data_15[22];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_0[21:20];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_1[21:20];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_2[21:20];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_3[21:20];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_4[21:20];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_5[21:20];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_6[21:20];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_7[21:20];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_8[21:20];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_9[21:20];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_10[21:20];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_11[21:20];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_12[21:20];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_13[21:20];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_14[21:20];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BITS_21_TO_20_577_m_data_1_ETC___d1594 =
|
|
m_data_15[21:20];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_0[24];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_1[24];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_2[24];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_3[24];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_4[24];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_5[24];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_6[24];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_7[24];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_8[24];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_9[24];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_10[24];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_11[24];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_12[24];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_13[24];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_14[24];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_24_523_m_data_1_48_BIT_ETC___d1540 =
|
|
m_data_15[24];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_0[26];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_1[26];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_2[26];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_3[26];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_4[26];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_5[26];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_6[26];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_7[26];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_8[26];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_9[26];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_10[26];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_11[26];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_12[26];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_13[26];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_14[26];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_26_487_m_data_1_48_BIT_ETC___d1504 =
|
|
m_data_15[26];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_0[23];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_1[23];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_2[23];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_3[23];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_4[23];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_5[23];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_6[23];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_7[23];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_8[23];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_9[23];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_10[23];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_11[23];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_12[23];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_13[23];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_14[23];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_23_541_m_data_1_48_BIT_ETC___d1558 =
|
|
m_data_15[23];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_0[25];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_1[25];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_2[25];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_3[25];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_4[25];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_5[25];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_6[25];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_7[25];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_8[25];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_9[25];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_10[25];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_11[25];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_12[25];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_13[25];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_14[25];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_25_505_m_data_1_48_BIT_ETC___d1522 =
|
|
m_data_15[25];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_0[28];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_1[28];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_2[28];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_3[28];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_4[28];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_5[28];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_6[28];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_7[28];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_8[28];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_9[28];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_10[28];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_11[28];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_12[28];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_13[28];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_14[28];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_28_451_m_data_1_48_BIT_ETC___d1468 =
|
|
m_data_15[28];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_0[27];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_1[27];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_2[27];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_3[27];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_4[27];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_5[27];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_6[27];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_7[27];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_8[27];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_9[27];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_10[27];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_11[27];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_12[27];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_13[27];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_14[27];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_27_469_m_data_1_48_BIT_ETC___d1486 =
|
|
m_data_15[27];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_0[30];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_1[30];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_2[30];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_3[30];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_4[30];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_5[30];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_6[30];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_7[30];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_8[30];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_9[30];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_10[30];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_11[30];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_12[30];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_13[30];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_14[30];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_30_415_m_data_1_48_BIT_ETC___d1432 =
|
|
m_data_15[30];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_0[29];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_1[29];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_2[29];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_3[29];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_4[29];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_5[29];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_6[29];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_7[29];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_8[29];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_9[29];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_10[29];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_11[29];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_12[29];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_13[29];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_14[29];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_29_433_m_data_1_48_BIT_ETC___d1450 =
|
|
m_data_15[29];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_0[32];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_1[32];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_2[32];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_3[32];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_4[32];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_5[32];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_6[32];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_7[32];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_8[32];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_9[32];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_10[32];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_11[32];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_12[32];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_13[32];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_14[32];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_32_379_m_data_1_48_BIT_ETC___d1396 =
|
|
m_data_15[32];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_0[31];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_1[31];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_2[31];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_3[31];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_4[31];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_5[31];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_6[31];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_7[31];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_8[31];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_9[31];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_10[31];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_11[31];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_12[31];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_13[31];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_14[31];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_31_397_m_data_1_48_BIT_ETC___d1414 =
|
|
m_data_15[31];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_regs_0 or
|
|
m_regs_1 or
|
|
m_regs_2 or
|
|
m_regs_3 or
|
|
m_regs_4 or
|
|
m_regs_5 or
|
|
m_regs_6 or
|
|
m_regs_7 or
|
|
m_regs_8 or
|
|
m_regs_9 or
|
|
m_regs_10 or
|
|
m_regs_11 or m_regs_12 or m_regs_13 or m_regs_14 or m_regs_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_0[31:25];
|
|
4'd1:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_1[31:25];
|
|
4'd2:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_2[31:25];
|
|
4'd3:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_3[31:25];
|
|
4'd4:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_4[31:25];
|
|
4'd5:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_5[31:25];
|
|
4'd6:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_6[31:25];
|
|
4'd7:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_7[31:25];
|
|
4'd8:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_8[31:25];
|
|
4'd9:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_9[31:25];
|
|
4'd10:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_10[31:25];
|
|
4'd11:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_11[31:25];
|
|
4'd12:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_12[31:25];
|
|
4'd13:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_13[31:25];
|
|
4'd14:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_14[31:25];
|
|
4'd15:
|
|
SEL_ARR_m_regs_0_720_BITS_31_TO_25_771_m_regs__ETC___d1788 =
|
|
m_regs_15[31:25];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_0[34];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_1[34];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_2[34];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_3[34];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_4[34];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_5[34];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_6[34];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_7[34];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_8[34];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_9[34];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_10[34];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_11[34];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_12[34];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_13[34];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_14[34];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_34_343_m_data_1_48_BIT_ETC___d1360 =
|
|
m_data_15[34];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_spec_bits_0_rl or
|
|
m_spec_bits_1_rl or
|
|
m_spec_bits_2_rl or
|
|
m_spec_bits_3_rl or
|
|
m_spec_bits_4_rl or
|
|
m_spec_bits_5_rl or
|
|
m_spec_bits_6_rl or
|
|
m_spec_bits_7_rl or
|
|
m_spec_bits_8_rl or
|
|
m_spec_bits_9_rl or
|
|
m_spec_bits_10_rl or
|
|
m_spec_bits_11_rl or
|
|
m_spec_bits_12_rl or
|
|
m_spec_bits_13_rl or m_spec_bits_14_rl or m_spec_bits_15_rl)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_0_rl;
|
|
4'd1:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_1_rl;
|
|
4'd2:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_2_rl;
|
|
4'd3:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_3_rl;
|
|
4'd4:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_4_rl;
|
|
4'd5:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_5_rl;
|
|
4'd6:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_6_rl;
|
|
4'd7:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_7_rl;
|
|
4'd8:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_8_rl;
|
|
4'd9:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_9_rl;
|
|
4'd10:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_10_rl;
|
|
4'd11:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_11_rl;
|
|
4'd12:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_12_rl;
|
|
4'd13:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_13_rl;
|
|
4'd14:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_14_rl;
|
|
4'd15:
|
|
SEL_ARR_m_spec_bits_0_rl_17_m_spec_bits_1_rl_2_ETC___d2014 =
|
|
m_spec_bits_15_rl;
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_0[33];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_1[33];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_2[33];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_3[33];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_4[33];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_5[33];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_6[33];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_7[33];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_8[33];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_9[33];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_10[33];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_11[33];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_12[33];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_13[33];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_14[33];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_33_361_m_data_1_48_BIT_ETC___d1378 =
|
|
m_data_15[33];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_0[36];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_1[36];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_2[36];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_3[36];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_4[36];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_5[36];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_6[36];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_7[36];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_8[36];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_9[36];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_10[36];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_11[36];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_12[36];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_13[36];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_14[36];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_36_307_m_data_1_48_BIT_ETC___d1324 =
|
|
m_data_15[36];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_0[35];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_1[35];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_2[35];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_3[35];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_4[35];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_5[35];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_6[35];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_7[35];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_8[35];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_9[35];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_10[35];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_11[35];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_12[35];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_13[35];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_14[35];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_35_325_m_data_1_48_BIT_ETC___d1342 =
|
|
m_data_15[35];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_0[37];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_1[37];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_2[37];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_3[37];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_4[37];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_5[37];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_6[37];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_7[37];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_8[37];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_9[37];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_10[37];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_11[37];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_12[37];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_13[37];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_14[37];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_37_289_m_data_1_48_BIT_ETC___d1306 =
|
|
m_data_15[37];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_0[38];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_1[38];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_2[38];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_3[38];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_4[38];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_5[38];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_6[38];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_7[38];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_8[38];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_9[38];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_10[38];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_11[38];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_12[38];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_13[38];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_14[38];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_38_271_m_data_1_48_BIT_ETC___d1288 =
|
|
m_data_15[38];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_0[40];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_1[40];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_2[40];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_3[40];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_4[40];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_5[40];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_6[40];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_7[40];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_8[40];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_9[40];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_10[40];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_11[40];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_12[40];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_13[40];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_14[40];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_40_235_m_data_1_48_BIT_ETC___d1252 =
|
|
m_data_15[40];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_0[39];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_1[39];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_2[39];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_3[39];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_4[39];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_5[39];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_6[39];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_7[39];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_8[39];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_9[39];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_10[39];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_11[39];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_12[39];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_13[39];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_14[39];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_39_253_m_data_1_48_BIT_ETC___d1270 =
|
|
m_data_15[39];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_0[42];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_1[42];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_2[42];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_3[42];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_4[42];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_5[42];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_6[42];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_7[42];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_8[42];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_9[42];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_10[42];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_11[42];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_12[42];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_13[42];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_14[42];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_42_199_m_data_1_48_BIT_ETC___d1216 =
|
|
m_data_15[42];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_0[41];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_1[41];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_2[41];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_3[41];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_4[41];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_5[41];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_6[41];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_7[41];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_8[41];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_9[41];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_10[41];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_11[41];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_12[41];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_13[41];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_14[41];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_41_217_m_data_1_48_BIT_ETC___d1234 =
|
|
m_data_15[41];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_0[44];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_1[44];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_2[44];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_3[44];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_4[44];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_5[44];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_6[44];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_7[44];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_8[44];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_9[44];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_10[44];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_11[44];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_12[44];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_13[44];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_14[44];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_44_163_m_data_1_48_BIT_ETC___d1180 =
|
|
m_data_15[44];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_0[43];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_1[43];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_2[43];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_3[43];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_4[43];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_5[43];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_6[43];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_7[43];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_8[43];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_9[43];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_10[43];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_11[43];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_12[43];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_13[43];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_14[43];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_43_181_m_data_1_48_BIT_ETC___d1198 =
|
|
m_data_15[43];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_0[46];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_1[46];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_2[46];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_3[46];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_4[46];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_5[46];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_6[46];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_7[46];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_8[46];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_9[46];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_10[46];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_11[46];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_12[46];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_13[46];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_14[46];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_46_127_m_data_1_48_BIT_ETC___d1144 =
|
|
m_data_15[46];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_0[45];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_1[45];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_2[45];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_3[45];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_4[45];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_5[45];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_6[45];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_7[45];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_8[45];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_9[45];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_10[45];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_11[45];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_12[45];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_13[45];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_14[45];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_45_145_m_data_1_48_BIT_ETC___d1162 =
|
|
m_data_15[45];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_0[47];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_1[47];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_2[47];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_3[47];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_4[47];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_5[47];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_6[47];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_7[47];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_8[47];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_9[47];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_10[47];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_11[47];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_12[47];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_13[47];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_14[47];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_47_109_m_data_1_48_BIT_ETC___d1126 =
|
|
m_data_15[47];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_0[0];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_1[0];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_2[0];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_3[0];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_4[0];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_5[0];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_6[0];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_7[0];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_8[0];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_9[0];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_10[0];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_11[0];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_12[0];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_13[0];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_14[0];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BIT_0_700_m_data_1_48_BIT__ETC___d1717 =
|
|
m_data_15[0];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_0[85:54];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_1[85:54];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_2[85:54];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_3[85:54];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_4[85:54];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_5[85:54];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_6[85:54];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_7[85:54];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_8[85:54];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_9[85:54];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_10[85:54];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_11[85:54];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_12[85:54];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_13[85:54];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_14[85:54];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BITS_85_TO_54_017_m_data_1_ETC___d1034 =
|
|
m_data_15[85:54];
|
|
endcase
|
|
end
|
|
always@(idx__h53445 or
|
|
m_data_0 or
|
|
m_data_1 or
|
|
m_data_2 or
|
|
m_data_3 or
|
|
m_data_4 or
|
|
m_data_5 or
|
|
m_data_6 or
|
|
m_data_7 or
|
|
m_data_8 or
|
|
m_data_9 or
|
|
m_data_10 or
|
|
m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15)
|
|
begin
|
|
case (idx__h53445)
|
|
4'd0:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_0[88:86];
|
|
4'd1:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_1[88:86];
|
|
4'd2:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_2[88:86];
|
|
4'd3:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_3[88:86];
|
|
4'd4:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_4[88:86];
|
|
4'd5:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_5[88:86];
|
|
4'd6:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_6[88:86];
|
|
4'd7:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_7[88:86];
|
|
4'd8:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_8[88:86];
|
|
4'd9:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_9[88:86];
|
|
4'd10:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_10[88:86];
|
|
4'd11:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_11[88:86];
|
|
4'd12:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_12[88:86];
|
|
4'd13:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_13[88:86];
|
|
4'd14:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_14[88:86];
|
|
4'd15:
|
|
SEL_ARR_m_data_0_46_BITS_88_TO_86_47_m_data_1__ETC___d1016 =
|
|
m_data_15[88:86];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_regs_ready_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_10_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_11_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_12_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_13_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_14_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_15_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_8_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_regs_ready_9_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'bxxxx /* unspecified value */ ;
|
|
m_spec_bits_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_10_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_11_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_12_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_13_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_14_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_15_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_8_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_spec_bits_9_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_validEntryCount <= `BSV_ASSIGNMENT_DELAY 5'd0;
|
|
m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_10_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_11_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_12_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_13_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_14_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_15_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_4_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_5_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_6_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_7_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_8_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_9_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_regs_ready_0_rl$EN)
|
|
m_regs_ready_0_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_0_rl$D_IN;
|
|
if (m_regs_ready_10_rl$EN)
|
|
m_regs_ready_10_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_10_rl$D_IN;
|
|
if (m_regs_ready_11_rl$EN)
|
|
m_regs_ready_11_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_11_rl$D_IN;
|
|
if (m_regs_ready_12_rl$EN)
|
|
m_regs_ready_12_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_12_rl$D_IN;
|
|
if (m_regs_ready_13_rl$EN)
|
|
m_regs_ready_13_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_13_rl$D_IN;
|
|
if (m_regs_ready_14_rl$EN)
|
|
m_regs_ready_14_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_14_rl$D_IN;
|
|
if (m_regs_ready_15_rl$EN)
|
|
m_regs_ready_15_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_15_rl$D_IN;
|
|
if (m_regs_ready_1_rl$EN)
|
|
m_regs_ready_1_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_1_rl$D_IN;
|
|
if (m_regs_ready_2_rl$EN)
|
|
m_regs_ready_2_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_2_rl$D_IN;
|
|
if (m_regs_ready_3_rl$EN)
|
|
m_regs_ready_3_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_3_rl$D_IN;
|
|
if (m_regs_ready_4_rl$EN)
|
|
m_regs_ready_4_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_4_rl$D_IN;
|
|
if (m_regs_ready_5_rl$EN)
|
|
m_regs_ready_5_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_5_rl$D_IN;
|
|
if (m_regs_ready_6_rl$EN)
|
|
m_regs_ready_6_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_6_rl$D_IN;
|
|
if (m_regs_ready_7_rl$EN)
|
|
m_regs_ready_7_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_7_rl$D_IN;
|
|
if (m_regs_ready_8_rl$EN)
|
|
m_regs_ready_8_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_8_rl$D_IN;
|
|
if (m_regs_ready_9_rl$EN)
|
|
m_regs_ready_9_rl <= `BSV_ASSIGNMENT_DELAY m_regs_ready_9_rl$D_IN;
|
|
if (m_spec_bits_0_rl$EN)
|
|
m_spec_bits_0_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_0_rl$D_IN;
|
|
if (m_spec_bits_10_rl$EN)
|
|
m_spec_bits_10_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_10_rl$D_IN;
|
|
if (m_spec_bits_11_rl$EN)
|
|
m_spec_bits_11_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_11_rl$D_IN;
|
|
if (m_spec_bits_12_rl$EN)
|
|
m_spec_bits_12_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_12_rl$D_IN;
|
|
if (m_spec_bits_13_rl$EN)
|
|
m_spec_bits_13_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_13_rl$D_IN;
|
|
if (m_spec_bits_14_rl$EN)
|
|
m_spec_bits_14_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_14_rl$D_IN;
|
|
if (m_spec_bits_15_rl$EN)
|
|
m_spec_bits_15_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_15_rl$D_IN;
|
|
if (m_spec_bits_1_rl$EN)
|
|
m_spec_bits_1_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_1_rl$D_IN;
|
|
if (m_spec_bits_2_rl$EN)
|
|
m_spec_bits_2_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_2_rl$D_IN;
|
|
if (m_spec_bits_3_rl$EN)
|
|
m_spec_bits_3_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_3_rl$D_IN;
|
|
if (m_spec_bits_4_rl$EN)
|
|
m_spec_bits_4_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_4_rl$D_IN;
|
|
if (m_spec_bits_5_rl$EN)
|
|
m_spec_bits_5_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_5_rl$D_IN;
|
|
if (m_spec_bits_6_rl$EN)
|
|
m_spec_bits_6_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_6_rl$D_IN;
|
|
if (m_spec_bits_7_rl$EN)
|
|
m_spec_bits_7_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_7_rl$D_IN;
|
|
if (m_spec_bits_8_rl$EN)
|
|
m_spec_bits_8_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_8_rl$D_IN;
|
|
if (m_spec_bits_9_rl$EN)
|
|
m_spec_bits_9_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_9_rl$D_IN;
|
|
if (m_validEntryCount$EN)
|
|
m_validEntryCount <= `BSV_ASSIGNMENT_DELAY m_validEntryCount$D_IN;
|
|
if (m_valid_0_rl$EN)
|
|
m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_valid_0_rl$D_IN;
|
|
if (m_valid_10_rl$EN)
|
|
m_valid_10_rl <= `BSV_ASSIGNMENT_DELAY m_valid_10_rl$D_IN;
|
|
if (m_valid_11_rl$EN)
|
|
m_valid_11_rl <= `BSV_ASSIGNMENT_DELAY m_valid_11_rl$D_IN;
|
|
if (m_valid_12_rl$EN)
|
|
m_valid_12_rl <= `BSV_ASSIGNMENT_DELAY m_valid_12_rl$D_IN;
|
|
if (m_valid_13_rl$EN)
|
|
m_valid_13_rl <= `BSV_ASSIGNMENT_DELAY m_valid_13_rl$D_IN;
|
|
if (m_valid_14_rl$EN)
|
|
m_valid_14_rl <= `BSV_ASSIGNMENT_DELAY m_valid_14_rl$D_IN;
|
|
if (m_valid_15_rl$EN)
|
|
m_valid_15_rl <= `BSV_ASSIGNMENT_DELAY m_valid_15_rl$D_IN;
|
|
if (m_valid_1_rl$EN)
|
|
m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY m_valid_1_rl$D_IN;
|
|
if (m_valid_2_rl$EN)
|
|
m_valid_2_rl <= `BSV_ASSIGNMENT_DELAY m_valid_2_rl$D_IN;
|
|
if (m_valid_3_rl$EN)
|
|
m_valid_3_rl <= `BSV_ASSIGNMENT_DELAY m_valid_3_rl$D_IN;
|
|
if (m_valid_4_rl$EN)
|
|
m_valid_4_rl <= `BSV_ASSIGNMENT_DELAY m_valid_4_rl$D_IN;
|
|
if (m_valid_5_rl$EN)
|
|
m_valid_5_rl <= `BSV_ASSIGNMENT_DELAY m_valid_5_rl$D_IN;
|
|
if (m_valid_6_rl$EN)
|
|
m_valid_6_rl <= `BSV_ASSIGNMENT_DELAY m_valid_6_rl$D_IN;
|
|
if (m_valid_7_rl$EN)
|
|
m_valid_7_rl <= `BSV_ASSIGNMENT_DELAY m_valid_7_rl$D_IN;
|
|
if (m_valid_8_rl$EN)
|
|
m_valid_8_rl <= `BSV_ASSIGNMENT_DELAY m_valid_8_rl$D_IN;
|
|
if (m_valid_9_rl$EN)
|
|
m_valid_9_rl <= `BSV_ASSIGNMENT_DELAY m_valid_9_rl$D_IN;
|
|
end
|
|
if (m_data_0$EN) m_data_0 <= `BSV_ASSIGNMENT_DELAY m_data_0$D_IN;
|
|
if (m_data_1$EN) m_data_1 <= `BSV_ASSIGNMENT_DELAY m_data_1$D_IN;
|
|
if (m_data_10$EN) m_data_10 <= `BSV_ASSIGNMENT_DELAY m_data_10$D_IN;
|
|
if (m_data_11$EN) m_data_11 <= `BSV_ASSIGNMENT_DELAY m_data_11$D_IN;
|
|
if (m_data_12$EN) m_data_12 <= `BSV_ASSIGNMENT_DELAY m_data_12$D_IN;
|
|
if (m_data_13$EN) m_data_13 <= `BSV_ASSIGNMENT_DELAY m_data_13$D_IN;
|
|
if (m_data_14$EN) m_data_14 <= `BSV_ASSIGNMENT_DELAY m_data_14$D_IN;
|
|
if (m_data_15$EN) m_data_15 <= `BSV_ASSIGNMENT_DELAY m_data_15$D_IN;
|
|
if (m_data_2$EN) m_data_2 <= `BSV_ASSIGNMENT_DELAY m_data_2$D_IN;
|
|
if (m_data_3$EN) m_data_3 <= `BSV_ASSIGNMENT_DELAY m_data_3$D_IN;
|
|
if (m_data_4$EN) m_data_4 <= `BSV_ASSIGNMENT_DELAY m_data_4$D_IN;
|
|
if (m_data_5$EN) m_data_5 <= `BSV_ASSIGNMENT_DELAY m_data_5$D_IN;
|
|
if (m_data_6$EN) m_data_6 <= `BSV_ASSIGNMENT_DELAY m_data_6$D_IN;
|
|
if (m_data_7$EN) m_data_7 <= `BSV_ASSIGNMENT_DELAY m_data_7$D_IN;
|
|
if (m_data_8$EN) m_data_8 <= `BSV_ASSIGNMENT_DELAY m_data_8$D_IN;
|
|
if (m_data_9$EN) m_data_9 <= `BSV_ASSIGNMENT_DELAY m_data_9$D_IN;
|
|
if (m_regs_0$EN) m_regs_0 <= `BSV_ASSIGNMENT_DELAY m_regs_0$D_IN;
|
|
if (m_regs_1$EN) m_regs_1 <= `BSV_ASSIGNMENT_DELAY m_regs_1$D_IN;
|
|
if (m_regs_10$EN) m_regs_10 <= `BSV_ASSIGNMENT_DELAY m_regs_10$D_IN;
|
|
if (m_regs_11$EN) m_regs_11 <= `BSV_ASSIGNMENT_DELAY m_regs_11$D_IN;
|
|
if (m_regs_12$EN) m_regs_12 <= `BSV_ASSIGNMENT_DELAY m_regs_12$D_IN;
|
|
if (m_regs_13$EN) m_regs_13 <= `BSV_ASSIGNMENT_DELAY m_regs_13$D_IN;
|
|
if (m_regs_14$EN) m_regs_14 <= `BSV_ASSIGNMENT_DELAY m_regs_14$D_IN;
|
|
if (m_regs_15$EN) m_regs_15 <= `BSV_ASSIGNMENT_DELAY m_regs_15$D_IN;
|
|
if (m_regs_2$EN) m_regs_2 <= `BSV_ASSIGNMENT_DELAY m_regs_2$D_IN;
|
|
if (m_regs_3$EN) m_regs_3 <= `BSV_ASSIGNMENT_DELAY m_regs_3$D_IN;
|
|
if (m_regs_4$EN) m_regs_4 <= `BSV_ASSIGNMENT_DELAY m_regs_4$D_IN;
|
|
if (m_regs_5$EN) m_regs_5 <= `BSV_ASSIGNMENT_DELAY m_regs_5$D_IN;
|
|
if (m_regs_6$EN) m_regs_6 <= `BSV_ASSIGNMENT_DELAY m_regs_6$D_IN;
|
|
if (m_regs_7$EN) m_regs_7 <= `BSV_ASSIGNMENT_DELAY m_regs_7$D_IN;
|
|
if (m_regs_8$EN) m_regs_8 <= `BSV_ASSIGNMENT_DELAY m_regs_8$D_IN;
|
|
if (m_regs_9$EN) m_regs_9 <= `BSV_ASSIGNMENT_DELAY m_regs_9$D_IN;
|
|
if (m_spec_tag_0$EN)
|
|
m_spec_tag_0 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_0$D_IN;
|
|
if (m_spec_tag_1$EN)
|
|
m_spec_tag_1 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_1$D_IN;
|
|
if (m_spec_tag_10$EN)
|
|
m_spec_tag_10 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_10$D_IN;
|
|
if (m_spec_tag_11$EN)
|
|
m_spec_tag_11 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_11$D_IN;
|
|
if (m_spec_tag_12$EN)
|
|
m_spec_tag_12 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_12$D_IN;
|
|
if (m_spec_tag_13$EN)
|
|
m_spec_tag_13 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_13$D_IN;
|
|
if (m_spec_tag_14$EN)
|
|
m_spec_tag_14 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_14$D_IN;
|
|
if (m_spec_tag_15$EN)
|
|
m_spec_tag_15 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_15$D_IN;
|
|
if (m_spec_tag_2$EN)
|
|
m_spec_tag_2 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_2$D_IN;
|
|
if (m_spec_tag_3$EN)
|
|
m_spec_tag_3 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_3$D_IN;
|
|
if (m_spec_tag_4$EN)
|
|
m_spec_tag_4 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_4$D_IN;
|
|
if (m_spec_tag_5$EN)
|
|
m_spec_tag_5 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_5$D_IN;
|
|
if (m_spec_tag_6$EN)
|
|
m_spec_tag_6 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_6$D_IN;
|
|
if (m_spec_tag_7$EN)
|
|
m_spec_tag_7 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_7$D_IN;
|
|
if (m_spec_tag_8$EN)
|
|
m_spec_tag_8 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_8$D_IN;
|
|
if (m_spec_tag_9$EN)
|
|
m_spec_tag_9 <= `BSV_ASSIGNMENT_DELAY m_spec_tag_9$D_IN;
|
|
if (m_tag_0$EN) m_tag_0 <= `BSV_ASSIGNMENT_DELAY m_tag_0$D_IN;
|
|
if (m_tag_1$EN) m_tag_1 <= `BSV_ASSIGNMENT_DELAY m_tag_1$D_IN;
|
|
if (m_tag_10$EN) m_tag_10 <= `BSV_ASSIGNMENT_DELAY m_tag_10$D_IN;
|
|
if (m_tag_11$EN) m_tag_11 <= `BSV_ASSIGNMENT_DELAY m_tag_11$D_IN;
|
|
if (m_tag_12$EN) m_tag_12 <= `BSV_ASSIGNMENT_DELAY m_tag_12$D_IN;
|
|
if (m_tag_13$EN) m_tag_13 <= `BSV_ASSIGNMENT_DELAY m_tag_13$D_IN;
|
|
if (m_tag_14$EN) m_tag_14 <= `BSV_ASSIGNMENT_DELAY m_tag_14$D_IN;
|
|
if (m_tag_15$EN) m_tag_15 <= `BSV_ASSIGNMENT_DELAY m_tag_15$D_IN;
|
|
if (m_tag_2$EN) m_tag_2 <= `BSV_ASSIGNMENT_DELAY m_tag_2$D_IN;
|
|
if (m_tag_3$EN) m_tag_3 <= `BSV_ASSIGNMENT_DELAY m_tag_3$D_IN;
|
|
if (m_tag_4$EN) m_tag_4 <= `BSV_ASSIGNMENT_DELAY m_tag_4$D_IN;
|
|
if (m_tag_5$EN) m_tag_5 <= `BSV_ASSIGNMENT_DELAY m_tag_5$D_IN;
|
|
if (m_tag_6$EN) m_tag_6 <= `BSV_ASSIGNMENT_DELAY m_tag_6$D_IN;
|
|
if (m_tag_7$EN) m_tag_7 <= `BSV_ASSIGNMENT_DELAY m_tag_7$D_IN;
|
|
if (m_tag_8$EN) m_tag_8 <= `BSV_ASSIGNMENT_DELAY m_tag_8$D_IN;
|
|
if (m_tag_9$EN) m_tag_9 <= `BSV_ASSIGNMENT_DELAY m_tag_9$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_data_0 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_1 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_10 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_11 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_12 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_13 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_14 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_15 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_2 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_3 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_4 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_5 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_6 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_7 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_8 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_data_9 = 89'h0AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_regs_0 = 33'h0AAAAAAAA;
|
|
m_regs_1 = 33'h0AAAAAAAA;
|
|
m_regs_10 = 33'h0AAAAAAAA;
|
|
m_regs_11 = 33'h0AAAAAAAA;
|
|
m_regs_12 = 33'h0AAAAAAAA;
|
|
m_regs_13 = 33'h0AAAAAAAA;
|
|
m_regs_14 = 33'h0AAAAAAAA;
|
|
m_regs_15 = 33'h0AAAAAAAA;
|
|
m_regs_2 = 33'h0AAAAAAAA;
|
|
m_regs_3 = 33'h0AAAAAAAA;
|
|
m_regs_4 = 33'h0AAAAAAAA;
|
|
m_regs_5 = 33'h0AAAAAAAA;
|
|
m_regs_6 = 33'h0AAAAAAAA;
|
|
m_regs_7 = 33'h0AAAAAAAA;
|
|
m_regs_8 = 33'h0AAAAAAAA;
|
|
m_regs_9 = 33'h0AAAAAAAA;
|
|
m_regs_ready_0_rl = 4'hA;
|
|
m_regs_ready_10_rl = 4'hA;
|
|
m_regs_ready_11_rl = 4'hA;
|
|
m_regs_ready_12_rl = 4'hA;
|
|
m_regs_ready_13_rl = 4'hA;
|
|
m_regs_ready_14_rl = 4'hA;
|
|
m_regs_ready_15_rl = 4'hA;
|
|
m_regs_ready_1_rl = 4'hA;
|
|
m_regs_ready_2_rl = 4'hA;
|
|
m_regs_ready_3_rl = 4'hA;
|
|
m_regs_ready_4_rl = 4'hA;
|
|
m_regs_ready_5_rl = 4'hA;
|
|
m_regs_ready_6_rl = 4'hA;
|
|
m_regs_ready_7_rl = 4'hA;
|
|
m_regs_ready_8_rl = 4'hA;
|
|
m_regs_ready_9_rl = 4'hA;
|
|
m_spec_bits_0_rl = 12'hAAA;
|
|
m_spec_bits_10_rl = 12'hAAA;
|
|
m_spec_bits_11_rl = 12'hAAA;
|
|
m_spec_bits_12_rl = 12'hAAA;
|
|
m_spec_bits_13_rl = 12'hAAA;
|
|
m_spec_bits_14_rl = 12'hAAA;
|
|
m_spec_bits_15_rl = 12'hAAA;
|
|
m_spec_bits_1_rl = 12'hAAA;
|
|
m_spec_bits_2_rl = 12'hAAA;
|
|
m_spec_bits_3_rl = 12'hAAA;
|
|
m_spec_bits_4_rl = 12'hAAA;
|
|
m_spec_bits_5_rl = 12'hAAA;
|
|
m_spec_bits_6_rl = 12'hAAA;
|
|
m_spec_bits_7_rl = 12'hAAA;
|
|
m_spec_bits_8_rl = 12'hAAA;
|
|
m_spec_bits_9_rl = 12'hAAA;
|
|
m_spec_tag_0 = 5'h0A;
|
|
m_spec_tag_1 = 5'h0A;
|
|
m_spec_tag_10 = 5'h0A;
|
|
m_spec_tag_11 = 5'h0A;
|
|
m_spec_tag_12 = 5'h0A;
|
|
m_spec_tag_13 = 5'h0A;
|
|
m_spec_tag_14 = 5'h0A;
|
|
m_spec_tag_15 = 5'h0A;
|
|
m_spec_tag_2 = 5'h0A;
|
|
m_spec_tag_3 = 5'h0A;
|
|
m_spec_tag_4 = 5'h0A;
|
|
m_spec_tag_5 = 5'h0A;
|
|
m_spec_tag_6 = 5'h0A;
|
|
m_spec_tag_7 = 5'h0A;
|
|
m_spec_tag_8 = 5'h0A;
|
|
m_spec_tag_9 = 5'h0A;
|
|
m_tag_0 = 12'hAAA;
|
|
m_tag_1 = 12'hAAA;
|
|
m_tag_10 = 12'hAAA;
|
|
m_tag_11 = 12'hAAA;
|
|
m_tag_12 = 12'hAAA;
|
|
m_tag_13 = 12'hAAA;
|
|
m_tag_14 = 12'hAAA;
|
|
m_tag_15 = 12'hAAA;
|
|
m_tag_2 = 12'hAAA;
|
|
m_tag_3 = 12'hAAA;
|
|
m_tag_4 = 12'hAAA;
|
|
m_tag_5 = 12'hAAA;
|
|
m_tag_6 = 12'hAAA;
|
|
m_tag_7 = 12'hAAA;
|
|
m_tag_8 = 12'hAAA;
|
|
m_tag_9 = 12'hAAA;
|
|
m_validEntryCount = 5'h0A;
|
|
m_valid_0_rl = 1'h0;
|
|
m_valid_10_rl = 1'h0;
|
|
m_valid_11_rl = 1'h0;
|
|
m_valid_12_rl = 1'h0;
|
|
m_valid_13_rl = 1'h0;
|
|
m_valid_14_rl = 1'h0;
|
|
m_valid_15_rl = 1'h0;
|
|
m_valid_1_rl = 1'h0;
|
|
m_valid_2_rl = 1'h0;
|
|
m_valid_3_rl = 1'h0;
|
|
m_valid_4_rl = 1'h0;
|
|
m_valid_5_rl = 1'h0;
|
|
m_valid_6_rl = 1'h0;
|
|
m_valid_7_rl = 1'h0;
|
|
m_valid_8_rl = 1'h0;
|
|
m_valid_9_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkReservationStationMem
|
|
|