495 lines
15 KiB
Verilog
495 lines
15 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:35:55 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1
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// first O 102
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// RDY_first O 1
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 102
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_deq I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkSimpleRespQ(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first,
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RDY_first,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [101 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first
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output [101 : 0] first;
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output RDY_first;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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reg RDY_deq;
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wire [101 : 0] first;
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wire RDY_enq,
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RDY_first,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation;
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// inlined wires
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wire m_m_deqP_ehr_lat_0$whas,
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m_m_empty_for_enq_wire$wget,
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m_m_valid_0_lat_0$whas,
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m_m_valid_0_lat_1$whas,
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m_m_valid_1_lat_0$whas,
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m_m_valid_1_lat_1$whas;
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// register m_m_deqP_ehr_rl
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reg m_m_deqP_ehr_rl;
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wire m_m_deqP_ehr_rl$D_IN, m_m_deqP_ehr_rl$EN;
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// register m_m_enqP
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reg m_m_enqP;
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wire m_m_enqP$D_IN, m_m_enqP$EN;
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// register m_m_row_0
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reg [89 : 0] m_m_row_0;
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wire [89 : 0] m_m_row_0$D_IN;
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wire m_m_row_0$EN;
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// register m_m_row_1
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reg [89 : 0] m_m_row_1;
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wire [89 : 0] m_m_row_1$D_IN;
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wire m_m_row_1$EN;
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// register m_m_specBits_0_rl
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reg [11 : 0] m_m_specBits_0_rl;
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wire [11 : 0] m_m_specBits_0_rl$D_IN;
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wire m_m_specBits_0_rl$EN;
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// register m_m_specBits_1_rl
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reg [11 : 0] m_m_specBits_1_rl;
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wire [11 : 0] m_m_specBits_1_rl$D_IN;
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wire m_m_specBits_1_rl$EN;
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// register m_m_valid_0_rl
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reg m_m_valid_0_rl;
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wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN;
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// register m_m_valid_1_rl
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reg m_m_valid_1_rl;
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wire m_m_valid_1_rl$D_IN, m_m_valid_1_rl$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_m_canon_deqP,
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CAN_FIRE_RL_m_m_deqP_ehr_canon,
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CAN_FIRE_RL_m_m_setWireForEnq,
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CAN_FIRE_RL_m_m_specBits_0_canon,
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CAN_FIRE_RL_m_m_specBits_1_canon,
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CAN_FIRE_RL_m_m_valid_0_canon,
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CAN_FIRE_RL_m_m_valid_1_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_RL_m_m_canon_deqP,
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WILL_FIRE_RL_m_m_deqP_ehr_canon,
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WILL_FIRE_RL_m_m_setWireForEnq,
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WILL_FIRE_RL_m_m_specBits_0_canon,
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WILL_FIRE_RL_m_m_specBits_1_canon,
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WILL_FIRE_RL_m_m_valid_0_canon,
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WILL_FIRE_RL_m_m_valid_1_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation;
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// inputs to muxes for submodule ports
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wire MUX_m_m_valid_0_lat_0$wset_1__SEL_2,
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MUX_m_m_valid_1_lat_0$wset_1__SEL_2;
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// remaining internal signals
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reg [63 : 0] CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_89_TO_26_ETC__q8;
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reg [11 : 0] CASE_m_m_deqP_ehr_rl_0_m_m_specBits_0_rl_1_m_m_ETC__q10;
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reg [6 : 0] CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_19_TO_13_ETC__q3;
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reg [5 : 0] CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_5_TO_0_1_ETC__q7;
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reg [4 : 0] CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_10_TO_6__ETC__q6,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_25_TO_21_ETC__q9;
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reg CASE_m_m_deqP_ehr_rl_0_NOT_m_m_row_0_BIT_20_1__ETC__q2,
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CASE_m_m_deqP_ehr_rl_0_NOT_m_m_valid_0_rl_1_NO_ETC__q1,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_11_1_m_m__ETC__q5,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_12_1_m_m__ETC__q4;
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wire [20 : 0] NOT_SEL_ARR_NOT_m_m_row_0_2_BIT_20_3_4_NOT_m_m_ETC___d113;
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wire [11 : 0] sb__h5461, sb__h5577, upd__h1621, upd__h1966;
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wire upd__h2497;
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// action method enq
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assign RDY_enq =
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m_m_empty_for_enq_wire$wget || m_m_enqP != m_m_deqP_ehr_rl ;
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assign CAN_FIRE_enq =
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m_m_empty_for_enq_wire$wget || m_m_enqP != m_m_deqP_ehr_rl ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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always@(m_m_deqP_ehr_rl or m_m_valid_0_rl or m_m_valid_1_rl)
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begin
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case (m_m_deqP_ehr_rl)
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1'd0: RDY_deq = m_m_valid_0_rl;
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1'd1: RDY_deq = m_m_valid_1_rl;
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endcase
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end
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assign CAN_FIRE_deq = RDY_deq ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first
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assign first =
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{ CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_89_TO_26_ETC__q8,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_25_TO_21_ETC__q9,
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NOT_SEL_ARR_NOT_m_m_row_0_2_BIT_20_3_4_NOT_m_m_ETC___d113,
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CASE_m_m_deqP_ehr_rl_0_m_m_specBits_0_rl_1_m_m_ETC__q10 } ;
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assign RDY_first = RDY_deq ;
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// action method specUpdate_incorrectSpeculation
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assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_incorrectSpeculation =
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EN_specUpdate_incorrectSpeculation ;
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// action method specUpdate_correctSpeculation
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assign RDY_specUpdate_correctSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_correctSpeculation =
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EN_specUpdate_correctSpeculation ;
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// rule RL_m_m_canon_deqP
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assign CAN_FIRE_RL_m_m_canon_deqP =
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CASE_m_m_deqP_ehr_rl_0_NOT_m_m_valid_0_rl_1_NO_ETC__q1 &&
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(m_m_enqP != m_m_deqP_ehr_rl || m_m_valid_0_rl ||
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m_m_valid_1_rl) ;
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assign WILL_FIRE_RL_m_m_canon_deqP =
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CAN_FIRE_RL_m_m_canon_deqP &&
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!EN_specUpdate_incorrectSpeculation ;
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// rule RL_m_m_setWireForEnq
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assign CAN_FIRE_RL_m_m_setWireForEnq = 1'd1 ;
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assign WILL_FIRE_RL_m_m_setWireForEnq = 1'd1 ;
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// rule RL_m_m_valid_0_canon
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assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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// rule RL_m_m_valid_1_canon
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assign CAN_FIRE_RL_m_m_valid_1_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_1_canon = 1'd1 ;
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// rule RL_m_m_specBits_0_canon
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assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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// rule RL_m_m_specBits_1_canon
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assign CAN_FIRE_RL_m_m_specBits_1_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_1_canon = 1'd1 ;
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// rule RL_m_m_deqP_ehr_canon
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assign CAN_FIRE_RL_m_m_deqP_ehr_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_deqP_ehr_canon = 1'd1 ;
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// inputs to muxes for submodule ports
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assign MUX_m_m_valid_0_lat_0$wset_1__SEL_2 =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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m_m_specBits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
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assign MUX_m_m_valid_1_lat_0$wset_1__SEL_2 =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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m_m_specBits_1_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
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// inlined wires
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assign m_m_valid_0_lat_0$whas =
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EN_deq && m_m_deqP_ehr_rl == 1'd0 ||
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MUX_m_m_valid_0_lat_0$wset_1__SEL_2 ;
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assign m_m_valid_0_lat_1$whas = EN_enq && m_m_enqP == 1'd0 ;
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assign m_m_valid_1_lat_0$whas =
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EN_deq && m_m_deqP_ehr_rl == 1'd1 ||
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MUX_m_m_valid_1_lat_0$wset_1__SEL_2 ;
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assign m_m_valid_1_lat_1$whas = EN_enq && m_m_enqP == 1'd1 ;
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assign m_m_deqP_ehr_lat_0$whas = WILL_FIRE_RL_m_m_canon_deqP || EN_deq ;
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assign m_m_empty_for_enq_wire$wget = !m_m_valid_0_rl && !m_m_valid_1_rl ;
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// register m_m_deqP_ehr_rl
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assign m_m_deqP_ehr_rl$D_IN =
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m_m_deqP_ehr_lat_0$whas ? upd__h2497 : m_m_deqP_ehr_rl ;
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assign m_m_deqP_ehr_rl$EN = 1'd1 ;
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// register m_m_enqP
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assign m_m_enqP$D_IN = m_m_enqP + 1'd1 ;
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assign m_m_enqP$EN = EN_enq ;
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// register m_m_row_0
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assign m_m_row_0$D_IN = enq_x[101:12] ;
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assign m_m_row_0$EN = m_m_valid_0_lat_1$whas ;
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// register m_m_row_1
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assign m_m_row_1$D_IN = enq_x[101:12] ;
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assign m_m_row_1$EN = m_m_valid_1_lat_1$whas ;
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// register m_m_specBits_0_rl
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assign m_m_specBits_0_rl$D_IN =
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EN_specUpdate_correctSpeculation ? upd__h1621 : sb__h5461 ;
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assign m_m_specBits_0_rl$EN = 1'd1 ;
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// register m_m_specBits_1_rl
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assign m_m_specBits_1_rl$D_IN =
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EN_specUpdate_correctSpeculation ? upd__h1966 : sb__h5577 ;
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assign m_m_specBits_1_rl$EN = 1'd1 ;
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// register m_m_valid_0_rl
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assign m_m_valid_0_rl$D_IN =
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m_m_valid_0_lat_1$whas ||
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(m_m_valid_0_lat_0$whas ? 1'd0 : m_m_valid_0_rl) ;
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assign m_m_valid_0_rl$EN = 1'd1 ;
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// register m_m_valid_1_rl
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assign m_m_valid_1_rl$D_IN =
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m_m_valid_1_lat_1$whas ||
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(m_m_valid_1_lat_0$whas ? 1'd0 : m_m_valid_1_rl) ;
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assign m_m_valid_1_rl$EN = 1'd1 ;
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// remaining internal signals
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assign NOT_SEL_ARR_NOT_m_m_row_0_2_BIT_20_3_4_NOT_m_m_ETC___d113 =
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{ !CASE_m_m_deqP_ehr_rl_0_NOT_m_m_row_0_BIT_20_1__ETC__q2,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_19_TO_13_ETC__q3,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_12_1_m_m__ETC__q4,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_11_1_m_m__ETC__q5,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_10_TO_6__ETC__q6,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_5_TO_0_1_ETC__q7 } ;
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assign sb__h5461 =
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m_m_valid_0_lat_1$whas ? enq_x[11:0] : m_m_specBits_0_rl ;
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assign sb__h5577 =
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m_m_valid_1_lat_1$whas ? enq_x[11:0] : m_m_specBits_1_rl ;
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assign upd__h1621 = sb__h5461 & specUpdate_correctSpeculation_mask ;
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assign upd__h1966 = sb__h5577 & specUpdate_correctSpeculation_mask ;
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assign upd__h2497 = m_m_deqP_ehr_rl + 1'd1 ;
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always@(m_m_deqP_ehr_rl or m_m_valid_0_rl or m_m_valid_1_rl)
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begin
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case (m_m_deqP_ehr_rl)
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1'd0:
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CASE_m_m_deqP_ehr_rl_0_NOT_m_m_valid_0_rl_1_NO_ETC__q1 =
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!m_m_valid_0_rl;
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1'd1:
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CASE_m_m_deqP_ehr_rl_0_NOT_m_m_valid_0_rl_1_NO_ETC__q1 =
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!m_m_valid_1_rl;
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endcase
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end
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always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
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begin
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case (m_m_deqP_ehr_rl)
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1'd0:
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CASE_m_m_deqP_ehr_rl_0_NOT_m_m_row_0_BIT_20_1__ETC__q2 =
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!m_m_row_0[20];
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1'd1:
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CASE_m_m_deqP_ehr_rl_0_NOT_m_m_row_0_BIT_20_1__ETC__q2 =
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!m_m_row_1[20];
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endcase
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end
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always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
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begin
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case (m_m_deqP_ehr_rl)
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1'd0:
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_19_TO_13_ETC__q3 =
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m_m_row_0[19:13];
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1'd1:
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_19_TO_13_ETC__q3 =
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m_m_row_1[19:13];
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endcase
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end
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always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
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begin
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case (m_m_deqP_ehr_rl)
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1'd0:
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_12_1_m_m__ETC__q4 =
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m_m_row_0[12];
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1'd1:
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_12_1_m_m__ETC__q4 =
|
|
m_m_row_1[12];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_11_1_m_m__ETC__q5 =
|
|
m_m_row_0[11];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_11_1_m_m__ETC__q5 =
|
|
m_m_row_1[11];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_10_TO_6__ETC__q6 =
|
|
m_m_row_0[10:6];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_10_TO_6__ETC__q6 =
|
|
m_m_row_1[10:6];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_5_TO_0_1_ETC__q7 =
|
|
m_m_row_0[5:0];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_5_TO_0_1_ETC__q7 =
|
|
m_m_row_1[5:0];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_89_TO_26_ETC__q8 =
|
|
m_m_row_0[89:26];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_89_TO_26_ETC__q8 =
|
|
m_m_row_1[89:26];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_25_TO_21_ETC__q9 =
|
|
m_m_row_0[25:21];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_25_TO_21_ETC__q9 =
|
|
m_m_row_1[25:21];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_specBits_0_rl or m_m_specBits_1_rl)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_specBits_0_rl_1_m_m_ETC__q10 =
|
|
m_m_specBits_0_rl;
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_specBits_0_rl_1_m_m_ETC__q10 =
|
|
m_m_specBits_1_rl;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_deqP_ehr_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_deqP_ehr_rl$EN)
|
|
m_m_deqP_ehr_rl <= `BSV_ASSIGNMENT_DELAY m_m_deqP_ehr_rl$D_IN;
|
|
if (m_m_enqP$EN) m_m_enqP <= `BSV_ASSIGNMENT_DELAY m_m_enqP$D_IN;
|
|
if (m_m_specBits_0_rl$EN)
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN;
|
|
if (m_m_specBits_1_rl$EN)
|
|
m_m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_1_rl$D_IN;
|
|
if (m_m_valid_0_rl$EN)
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN;
|
|
if (m_m_valid_1_rl$EN)
|
|
m_m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_1_rl$D_IN;
|
|
end
|
|
if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN;
|
|
if (m_m_row_1$EN) m_m_row_1 <= `BSV_ASSIGNMENT_DELAY m_m_row_1$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_deqP_ehr_rl = 1'h0;
|
|
m_m_enqP = 1'h0;
|
|
m_m_row_0 = 90'h2AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_row_1 = 90'h2AAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_specBits_0_rl = 12'hAAA;
|
|
m_m_specBits_1_rl = 12'hAAA;
|
|
m_m_valid_0_rl = 1'h0;
|
|
m_m_valid_1_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkSimpleRespQ
|
|
|