11821 lines
402 KiB
Verilog
11821 lines
402 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:28:49 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// isEmpty O 1
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// RDY_isEmpty O 1 const
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// getEnqIndex O 3
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// RDY_getEnqIndex O 1 const
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// RDY_enq O 1 reg
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// deq O 638
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// RDY_deq O 1 reg
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// issue O 640
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// RDY_issue O 1 reg
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// search O 133
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// RDY_search O 1 const
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// noMatchLdQ O 1
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// RDY_noMatchLdQ O 1 const
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// noMatchStQ O 1
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// RDY_noMatchStQ O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// getEnqIndex_paddr I 64
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// enq_idx I 2
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// enq_paddr I 64
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// enq_be I 16
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// enq_data I 129
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// deq_idx I 2
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// search_paddr I 64
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// search_be I 16
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// noMatchLdQ_paddr I 64
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// noMatchLdQ_be I 16
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// noMatchStQ_paddr I 64
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// noMatchStQ_be I 16
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// EN_enq I 1
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// EN_deq I 1
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// EN_issue I 1
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//
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// Combinational paths from inputs to outputs:
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// (getEnqIndex_paddr, deq_idx, EN_deq) -> getEnqIndex
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// (search_paddr, search_be) -> search
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// (noMatchLdQ_paddr, noMatchLdQ_be) -> noMatchLdQ
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// (noMatchStQ_paddr, noMatchStQ_be) -> noMatchStQ
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// deq_idx -> deq
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkStoreBufferEhr(CLK,
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RST_N,
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isEmpty,
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RDY_isEmpty,
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getEnqIndex_paddr,
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getEnqIndex,
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RDY_getEnqIndex,
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enq_idx,
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enq_paddr,
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enq_be,
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enq_data,
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EN_enq,
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RDY_enq,
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deq_idx,
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EN_deq,
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deq,
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RDY_deq,
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EN_issue,
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issue,
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RDY_issue,
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search_paddr,
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search_be,
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search,
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RDY_search,
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noMatchLdQ_paddr,
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noMatchLdQ_be,
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noMatchLdQ,
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RDY_noMatchLdQ,
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noMatchStQ_paddr,
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noMatchStQ_be,
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noMatchStQ,
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RDY_noMatchStQ);
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input CLK;
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input RST_N;
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// value method isEmpty
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output isEmpty;
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output RDY_isEmpty;
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// value method getEnqIndex
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input [63 : 0] getEnqIndex_paddr;
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output [2 : 0] getEnqIndex;
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output RDY_getEnqIndex;
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// action method enq
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input [1 : 0] enq_idx;
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input [63 : 0] enq_paddr;
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input [15 : 0] enq_be;
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input [128 : 0] enq_data;
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input EN_enq;
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output RDY_enq;
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// actionvalue method deq
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input [1 : 0] deq_idx;
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input EN_deq;
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output [637 : 0] deq;
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output RDY_deq;
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// actionvalue method issue
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input EN_issue;
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output [639 : 0] issue;
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output RDY_issue;
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// value method search
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input [63 : 0] search_paddr;
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input [15 : 0] search_be;
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output [132 : 0] search;
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output RDY_search;
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// value method noMatchLdQ
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input [63 : 0] noMatchLdQ_paddr;
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input [15 : 0] noMatchLdQ_be;
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output noMatchLdQ;
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output RDY_noMatchLdQ;
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// value method noMatchStQ
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input [63 : 0] noMatchStQ_paddr;
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input [15 : 0] noMatchStQ_be;
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output noMatchStQ;
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output RDY_noMatchStQ;
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// signals for module outputs
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wire [639 : 0] issue;
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wire [637 : 0] deq;
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wire [132 : 0] search;
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wire [2 : 0] getEnqIndex;
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wire RDY_deq,
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RDY_enq,
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RDY_getEnqIndex,
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RDY_isEmpty,
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RDY_issue,
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RDY_noMatchLdQ,
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RDY_noMatchStQ,
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RDY_search,
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isEmpty,
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noMatchLdQ,
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noMatchStQ;
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// inlined wires
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wire [637 : 0] entry_0_lat_1$wget,
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entry_1_lat_1$wget,
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entry_2_lat_1$wget,
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entry_3_lat_1$wget;
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wire entry_0_lat_1$whas,
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entry_1_lat_1$whas,
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entry_2_lat_1$whas,
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entry_3_lat_1$whas,
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valid_0_lat_0$whas,
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valid_0_lat_1$whas,
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valid_1_lat_0$whas,
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valid_1_lat_1$whas,
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valid_2_lat_0$whas,
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valid_2_lat_1$whas,
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valid_3_lat_0$whas,
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valid_3_lat_1$whas;
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// register entry_0_rl
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reg [637 : 0] entry_0_rl;
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wire [637 : 0] entry_0_rl$D_IN;
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wire entry_0_rl$EN;
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// register entry_1_rl
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reg [637 : 0] entry_1_rl;
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wire [637 : 0] entry_1_rl$D_IN;
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wire entry_1_rl$EN;
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// register entry_2_rl
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reg [637 : 0] entry_2_rl;
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wire [637 : 0] entry_2_rl$D_IN;
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wire entry_2_rl$EN;
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// register entry_3_rl
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reg [637 : 0] entry_3_rl;
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wire [637 : 0] entry_3_rl$D_IN;
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wire entry_3_rl$EN;
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// register initIdx
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reg [1 : 0] initIdx;
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wire [1 : 0] initIdx$D_IN;
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wire initIdx$EN;
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// register inited
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reg inited;
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wire inited$D_IN, inited$EN;
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// register valid_0_rl
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reg valid_0_rl;
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wire valid_0_rl$D_IN, valid_0_rl$EN;
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// register valid_1_rl
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reg valid_1_rl;
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wire valid_1_rl$D_IN, valid_1_rl$EN;
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// register valid_2_rl
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reg valid_2_rl;
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wire valid_2_rl$D_IN, valid_2_rl$EN;
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// register valid_3_rl
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reg valid_3_rl;
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wire valid_3_rl$D_IN, valid_3_rl$EN;
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// ports of submodule freeQ
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wire [1 : 0] freeQ$D_IN, freeQ$D_OUT;
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wire freeQ$CLR, freeQ$DEQ, freeQ$EMPTY_N, freeQ$ENQ;
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// ports of submodule issueQ
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wire [1 : 0] issueQ$D_IN, issueQ$D_OUT;
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wire issueQ$CLR, issueQ$DEQ, issueQ$EMPTY_N, issueQ$ENQ;
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// rule scheduling signals
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wire CAN_FIRE_RL_entry_0_canon,
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CAN_FIRE_RL_entry_1_canon,
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CAN_FIRE_RL_entry_2_canon,
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CAN_FIRE_RL_entry_3_canon,
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CAN_FIRE_RL_initFreeQ,
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CAN_FIRE_RL_valid_0_canon,
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CAN_FIRE_RL_valid_1_canon,
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CAN_FIRE_RL_valid_2_canon,
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CAN_FIRE_RL_valid_3_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_issue,
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WILL_FIRE_RL_entry_0_canon,
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WILL_FIRE_RL_entry_1_canon,
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WILL_FIRE_RL_entry_2_canon,
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WILL_FIRE_RL_entry_3_canon,
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WILL_FIRE_RL_initFreeQ,
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WILL_FIRE_RL_valid_0_canon,
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WILL_FIRE_RL_valid_1_canon,
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WILL_FIRE_RL_valid_2_canon,
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WILL_FIRE_RL_valid_3_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_issue;
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// remaining internal signals
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reg [63 : 0] CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_1_ETC__q1,
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CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_6_ETC__q5,
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CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_1_ETC__q2,
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CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_6_ETC__q6,
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CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_1_ETC__q3,
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CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_6_ETC__q7,
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CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_1_ETC__q4,
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CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_6_ETC__q8,
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CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q205,
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CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q209,
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CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q206,
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CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q210,
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CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q207,
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CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q211,
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CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q208,
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CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q212,
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SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1378,
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SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1380,
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SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1384,
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SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1386,
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SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1390,
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SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1392,
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SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1397,
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SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1399,
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SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250,
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SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343,
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SEL_ARR_SEL_ARR_entry_0_rl_BITS_127_TO_64_194__ETC___d2182,
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SEL_ARR_SEL_ARR_entry_0_rl_BITS_63_TO_0_287_en_ETC___d2192,
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SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1719,
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SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1835,
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SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1716,
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SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1833,
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SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1714,
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SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1832,
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SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1711,
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SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1830,
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SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1709,
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SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1829,
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SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1706,
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SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1828,
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SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1704,
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SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1827,
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SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1721,
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SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1836;
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reg [57 : 0] SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1533,
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SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1725;
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reg [3 : 0] IF_enq_be_EQ_65535_112_THEN_IF_enq_paddr_BITS__ETC___d1190;
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reg CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q73,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q74,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q75,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q76,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q77,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q78,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q79,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q80,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q81,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q82,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q83,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q84,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q85,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q86,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q87,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q88,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q100,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q101,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q102,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q103,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q104,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q89,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q90,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q91,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q92,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q93,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q94,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q95,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q96,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q97,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q98,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q99,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q105,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q106,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q107,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q108,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q109,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q110,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q111,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q112,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q113,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q114,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q115,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q116,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q117,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q118,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q119,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q120,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q121,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q122,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q123,
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CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q124,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q125,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q126,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q127,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q128,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q129,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q130,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q131,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q132,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q133,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q134,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q135,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q136,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q137,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q138,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q139,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q140,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q141,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q142,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q143,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q144,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q145,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q146,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q147,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q148,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q149,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q150,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q151,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q152,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q153,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q154,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q155,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q156,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q157,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q158,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q159,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q160,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q161,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q162,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q163,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q164,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q165,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q166,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q167,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q168,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q184,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q185,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q186,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q187,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q188,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q189,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q190,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q191,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q192,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q193,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q194,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q195,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q196,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q197,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q198,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q199,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q169,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q170,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q171,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q172,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q173,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q174,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q175,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q176,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q177,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q178,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q179,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q180,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q181,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q182,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q183,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q200,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q10,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q11,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q12,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q13,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q14,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q15,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q16,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q17,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q18,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q19,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q20,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q201,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q21,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q22,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q23,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q24,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q9,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q202,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q25,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q26,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q27,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q28,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q29,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q30,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q31,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q32,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q33,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q34,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q35,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q36,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q37,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q38,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q39,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q40,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q203,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q41,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q42,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q43,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q44,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q45,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q46,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q47,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q48,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q49,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q50,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q51,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q52,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q53,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q54,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q55,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q56,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q204,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q57,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q58,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q59,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q60,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q61,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q62,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q63,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q64,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q65,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q66,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q67,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q68,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q69,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q70,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q71,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q72,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1004,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1023,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1037,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1051,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1065,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d144,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d158,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d172,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d186,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d202,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d216,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d230,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d244,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d260,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d274,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d288,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d302,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d319,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d333,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d347,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d361,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d377,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d391,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d405,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d419,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d436,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d450,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d464,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d478,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d494,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d508,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d522,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d536,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d553,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d567,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d581,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d595,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d611,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d625,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d639,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d653,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d670,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d684,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d698,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d712,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d728,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d742,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d756,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d770,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d787,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d801,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d815,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d829,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d845,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d859,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d873,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d887,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d904,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d918,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d932,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d946,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d962,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d976,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d990,
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1006,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1067,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d188,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d246,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d304,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d363,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d421,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d480,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d538,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d597,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d655,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d714,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d772,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d831,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d889,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d948,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_512_161_entry_0_ETC___d2172,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_516_011_entry_1_ETC___d2156,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_517_50_entry_1__ETC___d2148,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_518_92_entry_1__ETC___d2142,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_519_33_entry_1__ETC___d2135,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_520_75_entry_1__ETC___d2129,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_521_16_entry_1__ETC___d2122,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_522_58_entry_1__ETC___d2116,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_523_99_entry_1__ETC___d2109,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_524_41_entry_1__ETC___d2103,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_525_82_entry_1__ETC___d2096,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_526_24_entry_1__ETC___d2090,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_527_65_entry_1__ETC___d2083,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_528_07_entry_1__ETC___d2077,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_529_48_entry_1__ETC___d2070,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_530_90_entry_1__ETC___d2064,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2058,
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1702,
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1825,
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1699,
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1824,
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1697,
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1822,
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1695,
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1821,
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1692,
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1820,
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d2151,
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1690,
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1818,
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d2143,
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1687,
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1817,
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d2137,
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1685,
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1815,
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d2130,
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1682,
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1814,
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d2124,
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1680,
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1812,
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d2117,
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1677,
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1811,
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d2111,
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1675,
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1809,
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d2104,
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1672,
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1808,
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d2098,
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1670,
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1806,
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d2091,
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1667,
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1805,
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d2085,
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1665,
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1803,
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d2078,
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1662,
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1802,
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d2072,
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1660,
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1800,
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d2065,
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1657,
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1799,
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d2059,
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1655,
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1797,
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d2053,
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1652,
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1796,
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d2152,
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1650,
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1794,
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d2144,
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1647,
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1793,
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d2138,
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1645,
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1791,
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d2131,
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1642,
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1790,
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d2125,
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1640,
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1788,
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d2118,
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1637,
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1787,
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d2112,
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1635,
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1785,
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d2105,
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1632,
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1784,
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d2099,
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1630,
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1782,
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d2092,
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1627,
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1781,
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d2086,
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1625,
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1779,
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d2079,
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1622,
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1778,
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d2073,
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1620,
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1776,
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d2066,
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1617,
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1775,
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d2060,
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1615,
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1773,
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d2054,
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1612,
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1772,
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d2153,
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1610,
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1770,
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d2145,
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1607,
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1769,
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d2139,
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1605,
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1767,
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d2132,
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1602,
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1766,
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d2126,
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1600,
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1764,
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d2119,
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1597,
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1763,
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d2113,
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1595,
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1761,
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d2106,
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1592,
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1760,
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d2100,
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1590,
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1758,
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d2093,
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1587,
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1757,
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d2087,
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1585,
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1755,
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d2080,
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1582,
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1754,
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d2074,
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1580,
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1752,
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d2067,
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1577,
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1751,
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d2061,
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1575,
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1749,
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d2055,
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1572,
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1748,
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d2154,
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1570,
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1746,
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d2146,
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1567,
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1745,
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d2140,
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1565,
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1743,
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d2133,
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1562,
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1742,
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d2127,
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1560,
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1740,
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d2120,
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1557,
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1739,
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d2114,
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1555,
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1737,
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d2107,
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1552,
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1736,
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d2101,
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1550,
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1734,
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d2094,
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1547,
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1733,
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d2088,
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1545,
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1731,
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d2081,
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1542,
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1730,
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d2075,
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1540,
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1728,
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d2068,
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1537,
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1727,
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d2062,
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1535,
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1726,
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d2056;
|
|
wire [127 : 0] IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1376,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_IF_e_ETC___d1401,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_IF_e_ETC___d1394,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_IF_e_ETC___d1388,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_IF_en_ETC___d1382;
|
|
wire [55 : 0] IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1279,
|
|
IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1372;
|
|
wire [39 : 0] IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1270,
|
|
IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1363;
|
|
wire [23 : 0] IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1261,
|
|
IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1354;
|
|
wire [15 : 0] IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_SEL__ETC___d1110,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_SEL__ETC___d1100,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_SEL__ETC___d1089,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_SEL_A_ETC___d1079,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1070,
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2227,
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2258,
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2289,
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2320,
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2357,
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2388,
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2419,
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2450,
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_0_ETC___d1886,
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_1_ETC___d1933,
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_2_ETC___d1981,
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_3_ETC___d2028;
|
|
wire [14 : 0] SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1009,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2150,
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2223,
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2255,
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2286,
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2317,
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2353,
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2385,
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2416,
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2447,
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_0_ETC___d1881,
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_1_ETC___d1929,
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_2_ETC___d1977,
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_3_ETC___d2024;
|
|
wire [3 : 0] IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_enq_d_ETC___d1175;
|
|
wire [1 : 0] IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d120,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_enq_d_ETC___d1144,
|
|
idx__h325005;
|
|
wire IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d116,
|
|
IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d117,
|
|
IF_IF_valid_2_lat_0_whas__5_THEN_NOT_valid_2_l_ETC___d115,
|
|
IF_entry_0_lat_0_whas_THEN_entry_0_lat_0_wget__ETC___d72,
|
|
IF_entry_1_lat_0_whas__0_THEN_entry_1_lat_0_wg_ETC___d77,
|
|
IF_entry_2_lat_0_whas__7_THEN_entry_2_lat_0_wg_ETC___d83,
|
|
IF_entry_3_lat_0_whas__4_THEN_entry_3_lat_0_wg_ETC___d88,
|
|
IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_lat__ETC___d97,
|
|
IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d34,
|
|
IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d91,
|
|
IF_valid_1_lat_0_whas__8_THEN_NOT_valid_1_lat__ETC___d101,
|
|
IF_valid_1_lat_0_whas__8_THEN_valid_1_lat_0_wg_ETC___d41,
|
|
IF_valid_2_lat_0_whas__5_THEN_NOT_valid_2_lat__ETC___d106,
|
|
IF_valid_2_lat_0_whas__5_THEN_valid_2_lat_0_wg_ETC___d48,
|
|
IF_valid_3_lat_0_whas__2_THEN_valid_3_lat_0_wg_ETC___d55,
|
|
NOT_valid_0_rl_3_2_OR_NOT_search_paddr_BITS_63_ETC___d2040,
|
|
search_paddr_BITS_63_TO_6_839_EQ_entry_0_rl_BI_ETC___d1840,
|
|
search_paddr_BITS_63_TO_6_839_EQ_entry_1_rl_2__ETC___d1890,
|
|
search_paddr_BITS_63_TO_6_839_EQ_entry_2_rl_9__ETC___d1938,
|
|
valid_0_rl_3_AND_search_paddr_BITS_63_TO_6_839_ETC___d1937,
|
|
valid_0_rl_3_AND_search_paddr_BITS_63_TO_6_839_ETC___d2160,
|
|
valid_2_rl_7_AND_search_paddr_BITS_63_TO_6_839_ETC___d2032;
|
|
|
|
// value method isEmpty
|
|
assign isEmpty = !valid_0_rl && !valid_1_rl && !valid_2_rl && !valid_3_rl ;
|
|
assign RDY_isEmpty = 1'd1 ;
|
|
|
|
// value method getEnqIndex
|
|
assign getEnqIndex =
|
|
{ IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d91 ||
|
|
freeQ$EMPTY_N,
|
|
IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d117 ?
|
|
IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d120 :
|
|
freeQ$D_OUT } ;
|
|
assign RDY_getEnqIndex = 1'd1 ;
|
|
|
|
// action method enq
|
|
assign RDY_enq = inited ;
|
|
assign CAN_FIRE_enq = inited ;
|
|
assign WILL_FIRE_enq = EN_enq ;
|
|
|
|
// actionvalue method deq
|
|
assign deq =
|
|
{ SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1533,
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1535,
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1537,
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1540,
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1542,
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1545,
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1547,
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1550,
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1552,
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1555,
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1557,
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1560,
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1562,
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1565,
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1567,
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1570,
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1572,
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1575,
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1577,
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1580,
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1582,
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1585,
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1587,
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1590,
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1592,
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1595,
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1597,
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1600,
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1602,
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1605,
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1607,
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1610,
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1612,
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1615,
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1617,
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1620,
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1622,
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1625,
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1627,
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1630,
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1632,
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1635,
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1637,
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1640,
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1642,
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1645,
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1647,
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1650,
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1652,
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1655,
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1657,
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1660,
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1662,
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1665,
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1667,
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1670,
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1672,
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1675,
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1677,
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1680,
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1682,
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1685,
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1687,
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1690,
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1692,
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1695,
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1697,
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1699,
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1702,
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1704,
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1706,
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1709,
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1711,
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1714,
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1716,
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1719,
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1721 } ;
|
|
assign RDY_deq = inited ;
|
|
assign CAN_FIRE_deq = inited ;
|
|
assign WILL_FIRE_deq = EN_deq ;
|
|
|
|
// actionvalue method issue
|
|
assign issue =
|
|
{ issueQ$D_OUT,
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1725,
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1726,
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1727,
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1728,
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1730,
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1731,
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1733,
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1734,
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1736,
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1737,
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1739,
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1740,
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1742,
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1743,
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1745,
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1746,
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1748,
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1749,
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1751,
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1752,
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1754,
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1755,
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1757,
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1758,
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1760,
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1761,
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1763,
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1764,
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1766,
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1767,
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1769,
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1770,
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1772,
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1773,
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1775,
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1776,
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1778,
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1779,
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1781,
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1782,
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1784,
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1785,
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1787,
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1788,
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1790,
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1791,
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1793,
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1794,
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1796,
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1797,
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1799,
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1800,
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1802,
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1803,
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1805,
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1806,
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1808,
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1809,
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1811,
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1812,
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1814,
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1815,
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1817,
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1818,
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1820,
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1821,
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1822,
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1824,
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1825,
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1827,
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1828,
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1829,
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1830,
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1832,
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1833,
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1835,
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1836 } ;
|
|
assign RDY_issue = issueQ$EMPTY_N ;
|
|
assign CAN_FIRE_issue = issueQ$EMPTY_N ;
|
|
assign WILL_FIRE_issue = EN_issue ;
|
|
|
|
// value method search
|
|
assign search =
|
|
{ valid_0_rl_3_AND_search_paddr_BITS_63_TO_6_839_ETC___d1937 ||
|
|
valid_2_rl_7_AND_search_paddr_BITS_63_TO_6_839_ETC___d2032,
|
|
idx__h325005,
|
|
valid_0_rl_3_AND_search_paddr_BITS_63_TO_6_839_ETC___d2160,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_512_161_entry_0_ETC___d2172,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_127_TO_64_194__ETC___d2182,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_63_TO_0_287_en_ETC___d2192 } ;
|
|
assign RDY_search = 1'd1 ;
|
|
|
|
// value method noMatchLdQ
|
|
assign noMatchLdQ =
|
|
(!valid_0_rl || noMatchLdQ_paddr[63:6] != entry_0_rl[637:580] ||
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2227 ==
|
|
16'd0) &&
|
|
(!valid_1_rl || noMatchLdQ_paddr[63:6] != entry_1_rl[637:580] ||
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2258 ==
|
|
16'd0) &&
|
|
(!valid_2_rl || noMatchLdQ_paddr[63:6] != entry_2_rl[637:580] ||
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2289 ==
|
|
16'd0) &&
|
|
(!valid_3_rl || noMatchLdQ_paddr[63:6] != entry_3_rl[637:580] ||
|
|
noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2320 ==
|
|
16'd0) ;
|
|
assign RDY_noMatchLdQ = 1'd1 ;
|
|
|
|
// value method noMatchStQ
|
|
assign noMatchStQ =
|
|
(!valid_0_rl || noMatchStQ_paddr[63:6] != entry_0_rl[637:580] ||
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2357 ==
|
|
16'd0) &&
|
|
(!valid_1_rl || noMatchStQ_paddr[63:6] != entry_1_rl[637:580] ||
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2388 ==
|
|
16'd0) &&
|
|
(!valid_2_rl || noMatchStQ_paddr[63:6] != entry_2_rl[637:580] ||
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2419 ==
|
|
16'd0) &&
|
|
(!valid_3_rl || noMatchStQ_paddr[63:6] != entry_3_rl[637:580] ||
|
|
noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2450 ==
|
|
16'd0) ;
|
|
assign RDY_noMatchStQ = 1'd1 ;
|
|
|
|
// submodule freeQ
|
|
SizedFIFO #(.p1width(32'd2),
|
|
.p2depth(32'd4),
|
|
.p3cntr_width(32'd2),
|
|
.guarded(32'd0)) freeQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(freeQ$D_IN),
|
|
.ENQ(freeQ$ENQ),
|
|
.DEQ(freeQ$DEQ),
|
|
.CLR(freeQ$CLR),
|
|
.D_OUT(freeQ$D_OUT),
|
|
.FULL_N(),
|
|
.EMPTY_N(freeQ$EMPTY_N));
|
|
|
|
// submodule issueQ
|
|
SizedFIFO #(.p1width(32'd2),
|
|
.p2depth(32'd4),
|
|
.p3cntr_width(32'd2),
|
|
.guarded(32'd0)) issueQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(issueQ$D_IN),
|
|
.ENQ(issueQ$ENQ),
|
|
.DEQ(issueQ$DEQ),
|
|
.CLR(issueQ$CLR),
|
|
.D_OUT(issueQ$D_OUT),
|
|
.FULL_N(),
|
|
.EMPTY_N(issueQ$EMPTY_N));
|
|
|
|
// rule RL_initFreeQ
|
|
assign CAN_FIRE_RL_initFreeQ = !inited ;
|
|
assign WILL_FIRE_RL_initFreeQ = CAN_FIRE_RL_initFreeQ ;
|
|
|
|
// rule RL_entry_0_canon
|
|
assign CAN_FIRE_RL_entry_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_entry_0_canon = 1'd1 ;
|
|
|
|
// rule RL_entry_1_canon
|
|
assign CAN_FIRE_RL_entry_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_entry_1_canon = 1'd1 ;
|
|
|
|
// rule RL_entry_2_canon
|
|
assign CAN_FIRE_RL_entry_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_entry_2_canon = 1'd1 ;
|
|
|
|
// rule RL_entry_3_canon
|
|
assign CAN_FIRE_RL_entry_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_entry_3_canon = 1'd1 ;
|
|
|
|
// rule RL_valid_0_canon
|
|
assign CAN_FIRE_RL_valid_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_valid_0_canon = 1'd1 ;
|
|
|
|
// rule RL_valid_1_canon
|
|
assign CAN_FIRE_RL_valid_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_valid_1_canon = 1'd1 ;
|
|
|
|
// rule RL_valid_2_canon
|
|
assign CAN_FIRE_RL_valid_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_valid_2_canon = 1'd1 ;
|
|
|
|
// rule RL_valid_3_canon
|
|
assign CAN_FIRE_RL_valid_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_valid_3_canon = 1'd1 ;
|
|
|
|
// inlined wires
|
|
assign entry_0_lat_1$wget =
|
|
(enq_idx == 2'd0 &&
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126) ?
|
|
{ enq_paddr[63:6],
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_SEL_A_ETC___d1079,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_SEL__ETC___d1089,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_SEL__ETC___d1100,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_SEL__ETC___d1110,
|
|
IF_enq_be_EQ_65535_112_THEN_IF_enq_paddr_BITS__ETC___d1190,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_IF_en_ETC___d1382,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_IF_e_ETC___d1388,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_IF_e_ETC___d1394,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_IF_e_ETC___d1401 } :
|
|
{ enq_paddr[63:6],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[0],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_data[127:0],
|
|
enq_data[127:0],
|
|
enq_data[127:0],
|
|
enq_data[127:0] } ;
|
|
assign entry_0_lat_1$whas = EN_enq && enq_idx == 2'd0 ;
|
|
assign entry_1_lat_1$wget =
|
|
(enq_idx == 2'd1 &&
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126) ?
|
|
{ enq_paddr[63:6],
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_SEL_A_ETC___d1079,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_SEL__ETC___d1089,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_SEL__ETC___d1100,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_SEL__ETC___d1110,
|
|
IF_enq_be_EQ_65535_112_THEN_IF_enq_paddr_BITS__ETC___d1190,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_IF_en_ETC___d1382,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_IF_e_ETC___d1388,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_IF_e_ETC___d1394,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_IF_e_ETC___d1401 } :
|
|
{ enq_paddr[63:6],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[0],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_data[127:0],
|
|
enq_data[127:0],
|
|
enq_data[127:0],
|
|
enq_data[127:0] } ;
|
|
assign entry_1_lat_1$whas = EN_enq && enq_idx == 2'd1 ;
|
|
assign entry_2_lat_1$wget =
|
|
(enq_idx == 2'd2 &&
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126) ?
|
|
{ enq_paddr[63:6],
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_SEL_A_ETC___d1079,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_SEL__ETC___d1089,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_SEL__ETC___d1100,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_SEL__ETC___d1110,
|
|
IF_enq_be_EQ_65535_112_THEN_IF_enq_paddr_BITS__ETC___d1190,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_IF_en_ETC___d1382,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_IF_e_ETC___d1388,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_IF_e_ETC___d1394,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_IF_e_ETC___d1401 } :
|
|
{ enq_paddr[63:6],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[0],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_data[127:0],
|
|
enq_data[127:0],
|
|
enq_data[127:0],
|
|
enq_data[127:0] } ;
|
|
assign entry_2_lat_1$whas = EN_enq && enq_idx == 2'd2 ;
|
|
assign entry_3_lat_1$wget =
|
|
(enq_idx == 2'd3 &&
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126) ?
|
|
{ enq_paddr[63:6],
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_SEL_A_ETC___d1079,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_SEL__ETC___d1089,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_SEL__ETC___d1100,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_SEL__ETC___d1110,
|
|
IF_enq_be_EQ_65535_112_THEN_IF_enq_paddr_BITS__ETC___d1190,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_IF_en_ETC___d1382,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_IF_e_ETC___d1388,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_IF_e_ETC___d1394,
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_IF_e_ETC___d1401 } :
|
|
{ enq_paddr[63:6],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd3 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd2 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd1 && enq_be[0],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[15],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[14],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[13],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[12],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[11],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[10],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[9],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[8],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[7],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[6],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[5],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[4],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[3],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[2],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[1],
|
|
enq_paddr[5:4] == 2'd0 && enq_be[0],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_be == 16'd65535 && enq_data[128],
|
|
enq_data[127:0],
|
|
enq_data[127:0],
|
|
enq_data[127:0],
|
|
enq_data[127:0] } ;
|
|
assign entry_3_lat_1$whas = EN_enq && enq_idx == 2'd3 ;
|
|
assign valid_0_lat_0$whas = EN_deq && deq_idx == 2'd0 ;
|
|
assign valid_0_lat_1$whas =
|
|
EN_enq && enq_idx == 2'd0 &&
|
|
!SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 ;
|
|
assign valid_1_lat_0$whas = EN_deq && deq_idx == 2'd1 ;
|
|
assign valid_1_lat_1$whas =
|
|
EN_enq && enq_idx == 2'd1 &&
|
|
!SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 ;
|
|
assign valid_2_lat_0$whas = EN_deq && deq_idx == 2'd2 ;
|
|
assign valid_2_lat_1$whas =
|
|
EN_enq && enq_idx == 2'd2 &&
|
|
!SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 ;
|
|
assign valid_3_lat_0$whas = EN_deq && deq_idx == 2'd3 ;
|
|
assign valid_3_lat_1$whas =
|
|
EN_enq && enq_idx == 2'd3 &&
|
|
!SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 ;
|
|
|
|
// register entry_0_rl
|
|
assign entry_0_rl$D_IN =
|
|
entry_0_lat_1$whas ? entry_0_lat_1$wget : entry_0_rl ;
|
|
assign entry_0_rl$EN = 1'd1 ;
|
|
|
|
// register entry_1_rl
|
|
assign entry_1_rl$D_IN =
|
|
entry_1_lat_1$whas ? entry_1_lat_1$wget : entry_1_rl ;
|
|
assign entry_1_rl$EN = 1'd1 ;
|
|
|
|
// register entry_2_rl
|
|
assign entry_2_rl$D_IN =
|
|
entry_2_lat_1$whas ? entry_2_lat_1$wget : entry_2_rl ;
|
|
assign entry_2_rl$EN = 1'd1 ;
|
|
|
|
// register entry_3_rl
|
|
assign entry_3_rl$D_IN =
|
|
entry_3_lat_1$whas ? entry_3_lat_1$wget : entry_3_rl ;
|
|
assign entry_3_rl$EN = 1'd1 ;
|
|
|
|
// register initIdx
|
|
assign initIdx$D_IN = initIdx + 2'd1 ;
|
|
assign initIdx$EN = CAN_FIRE_RL_initFreeQ ;
|
|
|
|
// register inited
|
|
assign inited$D_IN = 1'd1 ;
|
|
assign inited$EN = WILL_FIRE_RL_initFreeQ && initIdx == 2'd3 ;
|
|
|
|
// register valid_0_rl
|
|
assign valid_0_rl$D_IN =
|
|
valid_0_lat_1$whas ||
|
|
IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d34 ;
|
|
assign valid_0_rl$EN = 1'd1 ;
|
|
|
|
// register valid_1_rl
|
|
assign valid_1_rl$D_IN =
|
|
valid_1_lat_1$whas ||
|
|
IF_valid_1_lat_0_whas__8_THEN_valid_1_lat_0_wg_ETC___d41 ;
|
|
assign valid_1_rl$EN = 1'd1 ;
|
|
|
|
// register valid_2_rl
|
|
assign valid_2_rl$D_IN =
|
|
valid_2_lat_1$whas ||
|
|
IF_valid_2_lat_0_whas__5_THEN_valid_2_lat_0_wg_ETC___d48 ;
|
|
assign valid_2_rl$EN = 1'd1 ;
|
|
|
|
// register valid_3_rl
|
|
assign valid_3_rl$D_IN =
|
|
valid_3_lat_1$whas ||
|
|
IF_valid_3_lat_0_whas__2_THEN_valid_3_lat_0_wg_ETC___d55 ;
|
|
assign valid_3_rl$EN = 1'd1 ;
|
|
|
|
// submodule freeQ
|
|
assign freeQ$D_IN = EN_deq ? deq_idx : initIdx ;
|
|
assign freeQ$ENQ = EN_deq || WILL_FIRE_RL_initFreeQ ;
|
|
assign freeQ$DEQ =
|
|
EN_enq &&
|
|
!SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 ;
|
|
assign freeQ$CLR = 1'b0 ;
|
|
|
|
// submodule issueQ
|
|
assign issueQ$D_IN = enq_idx ;
|
|
assign issueQ$ENQ =
|
|
EN_enq &&
|
|
!SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 ;
|
|
assign issueQ$DEQ = EN_issue ;
|
|
assign issueQ$CLR = 1'b0 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d116 =
|
|
IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_lat__ETC___d97 ?
|
|
IF_valid_1_lat_0_whas__8_THEN_valid_1_lat_0_wg_ETC___d41 &&
|
|
IF_entry_1_lat_0_whas__0_THEN_entry_1_lat_0_wg_ETC___d77 :
|
|
IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d34 ;
|
|
assign IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d117 =
|
|
(IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_lat__ETC___d97 &&
|
|
IF_valid_1_lat_0_whas__8_THEN_NOT_valid_1_lat__ETC___d101) ?
|
|
IF_IF_valid_2_lat_0_whas__5_THEN_NOT_valid_2_l_ETC___d115 :
|
|
IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d116 ;
|
|
assign IF_IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_l_ETC___d120 =
|
|
(IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_lat__ETC___d97 &&
|
|
IF_valid_1_lat_0_whas__8_THEN_NOT_valid_1_lat__ETC___d101) ?
|
|
(IF_valid_2_lat_0_whas__5_THEN_NOT_valid_2_lat__ETC___d106 ?
|
|
2'd3 :
|
|
2'd2) :
|
|
(IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_lat__ETC___d97 ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign IF_IF_valid_2_lat_0_whas__5_THEN_NOT_valid_2_l_ETC___d115 =
|
|
IF_valid_2_lat_0_whas__5_THEN_NOT_valid_2_lat__ETC___d106 ?
|
|
IF_valid_3_lat_0_whas__2_THEN_valid_3_lat_0_wg_ETC___d55 &&
|
|
IF_entry_3_lat_0_whas__4_THEN_entry_3_lat_0_wg_ETC___d88 :
|
|
IF_valid_2_lat_0_whas__5_THEN_valid_2_lat_0_wg_ETC___d48 ;
|
|
assign IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1261 =
|
|
{ enq_be[15] ?
|
|
enq_data[127:120] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250[63:56],
|
|
enq_be[14] ?
|
|
enq_data[119:112] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250[55:48],
|
|
enq_be[13] ?
|
|
enq_data[111:104] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250[47:40] } ;
|
|
assign IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1270 =
|
|
{ IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1261,
|
|
enq_be[12] ?
|
|
enq_data[103:96] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250[39:32],
|
|
enq_be[11] ?
|
|
enq_data[95:88] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250[31:24] } ;
|
|
assign IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1279 =
|
|
{ IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1270,
|
|
enq_be[10] ?
|
|
enq_data[87:80] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250[23:16],
|
|
enq_be[9] ?
|
|
enq_data[79:72] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250[15:8] } ;
|
|
assign IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1376 =
|
|
{ IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1279,
|
|
enq_be[8] ?
|
|
enq_data[71:64] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250[7:0],
|
|
IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1372,
|
|
enq_be[0] ?
|
|
enq_data[7:0] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343[7:0] } ;
|
|
assign IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1354 =
|
|
{ enq_be[7] ?
|
|
enq_data[63:56] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343[63:56],
|
|
enq_be[6] ?
|
|
enq_data[55:48] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343[55:48],
|
|
enq_be[5] ?
|
|
enq_data[47:40] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343[47:40] } ;
|
|
assign IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1363 =
|
|
{ IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1354,
|
|
enq_be[4] ?
|
|
enq_data[39:32] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343[39:32],
|
|
enq_be[3] ?
|
|
enq_data[31:24] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343[31:24] } ;
|
|
assign IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1372 =
|
|
{ IF_enq_be_BIT_7_284_THEN_enq_data_BITS_63_TO_5_ETC___d1363,
|
|
enq_be[2] ?
|
|
enq_data[23:16] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343[23:16],
|
|
enq_be[1] ?
|
|
enq_data[15:8] :
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343[15:8] } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_IF_e_ETC___d1401 =
|
|
(enq_paddr[5:4] == 2'd0) ?
|
|
IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1376 :
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1397,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1399 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_0_101_THEN_SEL__ETC___d1110 =
|
|
(enq_paddr[5:4] == 2'd0) ?
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1070 :
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d144,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d202,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d260,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d319,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d377,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d436,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d494,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d553,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d611,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d670,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d728,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d787,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d845,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d904,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d962,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1023 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_IF_e_ETC___d1394 =
|
|
(enq_paddr[5:4] == 2'd1) ?
|
|
IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1376 :
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1390,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1392 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_1_091_THEN_SEL__ETC___d1100 =
|
|
(enq_paddr[5:4] == 2'd1) ?
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1070 :
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d158,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d216,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d274,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d333,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d391,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d450,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d508,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d567,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d625,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d684,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d742,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d801,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d859,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d918,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d976,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1037 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_IF_e_ETC___d1388 =
|
|
(enq_paddr[5:4] == 2'd2) ?
|
|
IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1376 :
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1384,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1386 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_2_080_THEN_SEL__ETC___d1089 =
|
|
(enq_paddr[5:4] == 2'd2) ?
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1070 :
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d172,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d230,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d288,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d347,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d405,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d464,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d522,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d581,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d639,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d698,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d756,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d815,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d873,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d932,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d990,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1051 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_IF_en_ETC___d1382 =
|
|
(enq_paddr[5:4] == 2'd3) ?
|
|
IF_enq_be_BIT_15_191_THEN_enq_data_BITS_127_TO_ETC___d1376 :
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1378,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1380 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_SEL_A_ETC___d1079 =
|
|
(enq_paddr[5:4] == 2'd3) ?
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1070 :
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d186,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d244,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d302,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d361,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d419,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d478,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d536,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d595,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d653,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d712,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d770,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d829,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d887,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d946,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1004,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1065 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_enq_d_ETC___d1144 =
|
|
{ (enq_paddr[5:4] == 2'd3) ?
|
|
enq_data[128] :
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127,
|
|
(enq_paddr[5:4] == 2'd2) ?
|
|
enq_data[128] :
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142 } ;
|
|
assign IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_enq_d_ETC___d1175 =
|
|
{ IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_enq_d_ETC___d1144,
|
|
(enq_paddr[5:4] == 2'd1) ?
|
|
enq_data[128] :
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158,
|
|
(enq_paddr[5:4] == 2'd0) ?
|
|
enq_data[128] :
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173 } ;
|
|
assign IF_entry_0_lat_0_whas_THEN_entry_0_lat_0_wget__ETC___d72 =
|
|
entry_0_rl[637:580] == getEnqIndex_paddr[63:6] ;
|
|
assign IF_entry_1_lat_0_whas__0_THEN_entry_1_lat_0_wg_ETC___d77 =
|
|
entry_1_rl[637:580] == getEnqIndex_paddr[63:6] ;
|
|
assign IF_entry_2_lat_0_whas__7_THEN_entry_2_lat_0_wg_ETC___d83 =
|
|
entry_2_rl[637:580] == getEnqIndex_paddr[63:6] ;
|
|
assign IF_entry_3_lat_0_whas__4_THEN_entry_3_lat_0_wg_ETC___d88 =
|
|
entry_3_rl[637:580] == getEnqIndex_paddr[63:6] ;
|
|
assign IF_valid_0_lat_0_whas__1_THEN_NOT_valid_0_lat__ETC___d97 =
|
|
valid_0_lat_0$whas || !valid_0_rl ||
|
|
!IF_entry_0_lat_0_whas_THEN_entry_0_lat_0_wget__ETC___d72 ;
|
|
assign IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d34 =
|
|
!valid_0_lat_0$whas && valid_0_rl ;
|
|
assign IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d91 =
|
|
IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d34 &&
|
|
IF_entry_0_lat_0_whas_THEN_entry_0_lat_0_wget__ETC___d72 ||
|
|
IF_valid_1_lat_0_whas__8_THEN_valid_1_lat_0_wg_ETC___d41 &&
|
|
IF_entry_1_lat_0_whas__0_THEN_entry_1_lat_0_wg_ETC___d77 ||
|
|
IF_valid_2_lat_0_whas__5_THEN_valid_2_lat_0_wg_ETC___d48 &&
|
|
IF_entry_2_lat_0_whas__7_THEN_entry_2_lat_0_wg_ETC___d83 ||
|
|
IF_valid_3_lat_0_whas__2_THEN_valid_3_lat_0_wg_ETC___d55 &&
|
|
IF_entry_3_lat_0_whas__4_THEN_entry_3_lat_0_wg_ETC___d88 ;
|
|
assign IF_valid_1_lat_0_whas__8_THEN_NOT_valid_1_lat__ETC___d101 =
|
|
valid_1_lat_0$whas || !valid_1_rl ||
|
|
!IF_entry_1_lat_0_whas__0_THEN_entry_1_lat_0_wg_ETC___d77 ;
|
|
assign IF_valid_1_lat_0_whas__8_THEN_valid_1_lat_0_wg_ETC___d41 =
|
|
!valid_1_lat_0$whas && valid_1_rl ;
|
|
assign IF_valid_2_lat_0_whas__5_THEN_NOT_valid_2_lat__ETC___d106 =
|
|
valid_2_lat_0$whas || !valid_2_rl ||
|
|
!IF_entry_2_lat_0_whas__7_THEN_entry_2_lat_0_wg_ETC___d83 ;
|
|
assign IF_valid_2_lat_0_whas__5_THEN_valid_2_lat_0_wg_ETC___d48 =
|
|
!valid_2_lat_0$whas && valid_2_rl ;
|
|
assign IF_valid_3_lat_0_whas__2_THEN_valid_3_lat_0_wg_ETC___d55 =
|
|
!valid_3_lat_0$whas && valid_3_rl ;
|
|
assign NOT_valid_0_rl_3_2_OR_NOT_search_paddr_BITS_63_ETC___d2040 =
|
|
(!valid_0_rl ||
|
|
!search_paddr_BITS_63_TO_6_839_EQ_entry_0_rl_BI_ETC___d1840 ||
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_0_ETC___d1886 ==
|
|
16'd0) &&
|
|
(!valid_1_rl ||
|
|
!search_paddr_BITS_63_TO_6_839_EQ_entry_1_rl_2__ETC___d1890 ||
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_1_ETC___d1933 ==
|
|
16'd0) ;
|
|
assign SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1009 =
|
|
{ SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d188,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d246,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d304,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d363,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d421,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d480,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d538,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d597,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d655,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d714,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d772,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d831,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d889,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d948,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1006 } |
|
|
enq_be[15:1] ;
|
|
assign SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1070 =
|
|
{ SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1009,
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1067 |
|
|
enq_be[0] } ;
|
|
assign SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2150 =
|
|
{ SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2058,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_530_90_entry_1__ETC___d2064,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_529_48_entry_1__ETC___d2070,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_528_07_entry_1__ETC___d2077,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_527_65_entry_1__ETC___d2083,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_526_24_entry_1__ETC___d2090,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_525_82_entry_1__ETC___d2096,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_524_41_entry_1__ETC___d2103,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_523_99_entry_1__ETC___d2109,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_522_58_entry_1__ETC___d2116,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_521_16_entry_1__ETC___d2122,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_520_75_entry_1__ETC___d2129,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_519_33_entry_1__ETC___d2135,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_518_92_entry_1__ETC___d2142,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_517_50_entry_1__ETC___d2148 } &
|
|
search_be[15:1] ;
|
|
assign idx__h325005 =
|
|
NOT_valid_0_rl_3_2_OR_NOT_search_paddr_BITS_63_ETC___d2040 ?
|
|
((!valid_2_rl ||
|
|
!search_paddr_BITS_63_TO_6_839_EQ_entry_2_rl_9__ETC___d1938 ||
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_2_ETC___d1981 ==
|
|
16'd0) ?
|
|
2'd3 :
|
|
2'd2) :
|
|
((!valid_0_rl ||
|
|
!search_paddr_BITS_63_TO_6_839_EQ_entry_0_rl_BI_ETC___d1840 ||
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_0_ETC___d1886 ==
|
|
16'd0) ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2223 =
|
|
noMatchLdQ_be[15:1] &
|
|
{ CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q73,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q74,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q75,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q76,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q77,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q78,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q79,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q80,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q81,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q82,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q83,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q84,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q85,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q86,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q87 } ;
|
|
assign noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2227 =
|
|
{ noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2223,
|
|
noMatchLdQ_be[0] &
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q88 } ;
|
|
assign noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2255 =
|
|
noMatchLdQ_be[15:1] &
|
|
{ CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q89,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q90,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q91,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q92,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q93,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q94,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q95,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q96,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q97,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q98,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q99,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q100,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q101,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q102,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q103 } ;
|
|
assign noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2258 =
|
|
{ noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2255,
|
|
noMatchLdQ_be[0] &
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q104 } ;
|
|
assign noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2286 =
|
|
noMatchLdQ_be[15:1] &
|
|
{ CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q105,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q106,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q107,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q108,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q109,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q110,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q111,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q112,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q113,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q114,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q115,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q116,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q117,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q118,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q119 } ;
|
|
assign noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2289 =
|
|
{ noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2286,
|
|
noMatchLdQ_be[0] &
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q120 } ;
|
|
assign noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2317 =
|
|
noMatchLdQ_be[15:1] &
|
|
{ CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q121,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q122,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q123,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q124,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q125,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q126,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q127,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q128,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q129,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q130,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q131,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q132,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q133,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q134,
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q135 } ;
|
|
assign noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2320 =
|
|
{ noMatchLdQ_be_BITS_15_TO_1_199_AND_SEL_ARR_ent_ETC___d2317,
|
|
noMatchLdQ_be[0] &
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q136 } ;
|
|
assign noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2353 =
|
|
noMatchStQ_be[15:1] &
|
|
{ CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q137,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q138,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q139,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q140,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q141,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q142,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q143,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q144,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q145,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q146,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q147,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q148,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q149,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q150,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q151 } ;
|
|
assign noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2357 =
|
|
{ noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2353,
|
|
noMatchStQ_be[0] &
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q152 } ;
|
|
assign noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2385 =
|
|
noMatchStQ_be[15:1] &
|
|
{ CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q153,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q154,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q155,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q156,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q157,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q158,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q159,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q160,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q161,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q162,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q163,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q164,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q165,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q166,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q167 } ;
|
|
assign noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2388 =
|
|
{ noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2385,
|
|
noMatchStQ_be[0] &
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q168 } ;
|
|
assign noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2416 =
|
|
noMatchStQ_be[15:1] &
|
|
{ CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q184,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q185,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q186,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q187,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q188,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q189,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q190,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q191,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q192,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q193,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q194,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q195,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q196,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q197,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q198 } ;
|
|
assign noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2419 =
|
|
{ noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2416,
|
|
noMatchStQ_be[0] &
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q199 } ;
|
|
assign noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2447 =
|
|
noMatchStQ_be[15:1] &
|
|
{ CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q169,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q170,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q171,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q172,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q173,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q174,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q175,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q176,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q177,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q178,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q179,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q180,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q181,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q182,
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q183 } ;
|
|
assign noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2450 =
|
|
{ noMatchStQ_be_BITS_15_TO_1_329_AND_SEL_ARR_ent_ETC___d2447,
|
|
noMatchStQ_be[0] &
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q200 } ;
|
|
assign search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_0_ETC___d1881 =
|
|
search_be[15:1] &
|
|
{ CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q9,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q10,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q11,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q12,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q13,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q14,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q15,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q16,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q17,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q18,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q19,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q20,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q21,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q22,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q23 } ;
|
|
assign search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_0_ETC___d1886 =
|
|
{ search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_0_ETC___d1881,
|
|
search_be[0] &
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q24 } ;
|
|
assign search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_1_ETC___d1929 =
|
|
search_be[15:1] &
|
|
{ CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q25,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q26,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q27,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q28,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q29,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q30,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q31,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q32,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q33,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q34,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q35,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q36,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q37,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q38,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q39 } ;
|
|
assign search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_1_ETC___d1933 =
|
|
{ search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_1_ETC___d1929,
|
|
search_be[0] &
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q40 } ;
|
|
assign search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_2_ETC___d1977 =
|
|
search_be[15:1] &
|
|
{ CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q41,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q42,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q43,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q44,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q45,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q46,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q47,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q48,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q49,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q50,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q51,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q52,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q53,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q54,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q55 } ;
|
|
assign search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_2_ETC___d1981 =
|
|
{ search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_2_ETC___d1977,
|
|
search_be[0] &
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q56 } ;
|
|
assign search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_3_ETC___d2024 =
|
|
search_be[15:1] &
|
|
{ CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q57,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q58,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q59,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q60,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q61,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q62,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q63,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q64,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q65,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q66,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q67,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q68,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q69,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q70,
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q71 } ;
|
|
assign search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_3_ETC___d2028 =
|
|
{ search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_3_ETC___d2024,
|
|
search_be[0] &
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q72 } ;
|
|
assign search_paddr_BITS_63_TO_6_839_EQ_entry_0_rl_BI_ETC___d1840 =
|
|
search_paddr[63:6] == entry_0_rl[637:580] ;
|
|
assign search_paddr_BITS_63_TO_6_839_EQ_entry_1_rl_2__ETC___d1890 =
|
|
search_paddr[63:6] == entry_1_rl[637:580] ;
|
|
assign search_paddr_BITS_63_TO_6_839_EQ_entry_2_rl_9__ETC___d1938 =
|
|
search_paddr[63:6] == entry_2_rl[637:580] ;
|
|
assign valid_0_rl_3_AND_search_paddr_BITS_63_TO_6_839_ETC___d1937 =
|
|
valid_0_rl &&
|
|
search_paddr_BITS_63_TO_6_839_EQ_entry_0_rl_BI_ETC___d1840 &&
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_0_ETC___d1886 !=
|
|
16'd0 ||
|
|
valid_1_rl &&
|
|
search_paddr_BITS_63_TO_6_839_EQ_entry_1_rl_2__ETC___d1890 &&
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_1_ETC___d1933 !=
|
|
16'd0 ;
|
|
assign valid_0_rl_3_AND_search_paddr_BITS_63_TO_6_839_ETC___d2160 =
|
|
(valid_0_rl_3_AND_search_paddr_BITS_63_TO_6_839_ETC___d1937 ||
|
|
valid_2_rl_7_AND_search_paddr_BITS_63_TO_6_839_ETC___d2032) &&
|
|
{ SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2150,
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_516_011_entry_1_ETC___d2156 &
|
|
search_be[0] } ==
|
|
search_be ;
|
|
assign valid_2_rl_7_AND_search_paddr_BITS_63_TO_6_839_ETC___d2032 =
|
|
valid_2_rl &&
|
|
search_paddr_BITS_63_TO_6_839_EQ_entry_2_rl_9__ETC___d1938 &&
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_2_ETC___d1981 !=
|
|
16'd0 ||
|
|
valid_3_rl && search_paddr[63:6] == entry_3_rl[637:580] &&
|
|
search_be_BITS_15_TO_1_842_AND_SEL_ARR_entry_3_ETC___d2028 !=
|
|
16'd0 ;
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d144 =
|
|
entry_0_rl[531];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d144 =
|
|
entry_1_rl[531];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d144 =
|
|
entry_2_rl[531];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d144 =
|
|
entry_3_rl[531];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d158 =
|
|
entry_0_rl[547];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d158 =
|
|
entry_1_rl[547];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d158 =
|
|
entry_2_rl[547];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d158 =
|
|
entry_3_rl[547];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d172 =
|
|
entry_0_rl[563];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d172 =
|
|
entry_1_rl[563];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d172 =
|
|
entry_2_rl[563];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d172 =
|
|
entry_3_rl[563];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d186 =
|
|
entry_0_rl[579];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d186 =
|
|
entry_1_rl[579];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d186 =
|
|
entry_2_rl[579];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d186 =
|
|
entry_3_rl[579];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d202 =
|
|
entry_0_rl[530];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d202 =
|
|
entry_1_rl[530];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d202 =
|
|
entry_2_rl[530];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d202 =
|
|
entry_3_rl[530];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d216 =
|
|
entry_0_rl[546];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d216 =
|
|
entry_1_rl[546];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d216 =
|
|
entry_2_rl[546];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d216 =
|
|
entry_3_rl[546];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d230 =
|
|
entry_0_rl[562];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d230 =
|
|
entry_1_rl[562];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d230 =
|
|
entry_2_rl[562];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d230 =
|
|
entry_3_rl[562];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d244 =
|
|
entry_0_rl[578];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d244 =
|
|
entry_1_rl[578];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d244 =
|
|
entry_2_rl[578];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d244 =
|
|
entry_3_rl[578];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d260 =
|
|
entry_0_rl[529];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d260 =
|
|
entry_1_rl[529];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d260 =
|
|
entry_2_rl[529];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d260 =
|
|
entry_3_rl[529];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d274 =
|
|
entry_0_rl[545];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d274 =
|
|
entry_1_rl[545];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d274 =
|
|
entry_2_rl[545];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d274 =
|
|
entry_3_rl[545];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d288 =
|
|
entry_0_rl[561];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d288 =
|
|
entry_1_rl[561];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d288 =
|
|
entry_2_rl[561];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d288 =
|
|
entry_3_rl[561];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d302 =
|
|
entry_0_rl[577];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d302 =
|
|
entry_1_rl[577];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d302 =
|
|
entry_2_rl[577];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d302 =
|
|
entry_3_rl[577];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d319 =
|
|
entry_0_rl[528];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d319 =
|
|
entry_1_rl[528];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d319 =
|
|
entry_2_rl[528];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d319 =
|
|
entry_3_rl[528];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d333 =
|
|
entry_0_rl[544];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d333 =
|
|
entry_1_rl[544];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d333 =
|
|
entry_2_rl[544];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d333 =
|
|
entry_3_rl[544];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d347 =
|
|
entry_0_rl[560];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d347 =
|
|
entry_1_rl[560];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d347 =
|
|
entry_2_rl[560];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d347 =
|
|
entry_3_rl[560];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d361 =
|
|
entry_0_rl[576];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d361 =
|
|
entry_1_rl[576];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d361 =
|
|
entry_2_rl[576];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d361 =
|
|
entry_3_rl[576];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d377 =
|
|
entry_0_rl[527];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d377 =
|
|
entry_1_rl[527];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d377 =
|
|
entry_2_rl[527];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d377 =
|
|
entry_3_rl[527];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d391 =
|
|
entry_0_rl[543];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d391 =
|
|
entry_1_rl[543];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d391 =
|
|
entry_2_rl[543];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d391 =
|
|
entry_3_rl[543];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d405 =
|
|
entry_0_rl[559];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d405 =
|
|
entry_1_rl[559];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d405 =
|
|
entry_2_rl[559];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d405 =
|
|
entry_3_rl[559];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d419 =
|
|
entry_0_rl[575];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d419 =
|
|
entry_1_rl[575];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d419 =
|
|
entry_2_rl[575];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d419 =
|
|
entry_3_rl[575];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d436 =
|
|
entry_0_rl[526];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d436 =
|
|
entry_1_rl[526];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d436 =
|
|
entry_2_rl[526];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d436 =
|
|
entry_3_rl[526];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d450 =
|
|
entry_0_rl[542];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d450 =
|
|
entry_1_rl[542];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d450 =
|
|
entry_2_rl[542];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d450 =
|
|
entry_3_rl[542];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d464 =
|
|
entry_0_rl[558];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d464 =
|
|
entry_1_rl[558];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d464 =
|
|
entry_2_rl[558];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d464 =
|
|
entry_3_rl[558];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d478 =
|
|
entry_0_rl[574];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d478 =
|
|
entry_1_rl[574];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d478 =
|
|
entry_2_rl[574];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d478 =
|
|
entry_3_rl[574];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d494 =
|
|
entry_0_rl[525];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d494 =
|
|
entry_1_rl[525];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d494 =
|
|
entry_2_rl[525];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d494 =
|
|
entry_3_rl[525];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d508 =
|
|
entry_0_rl[541];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d508 =
|
|
entry_1_rl[541];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d508 =
|
|
entry_2_rl[541];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d508 =
|
|
entry_3_rl[541];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d522 =
|
|
entry_0_rl[557];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d522 =
|
|
entry_1_rl[557];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d522 =
|
|
entry_2_rl[557];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d522 =
|
|
entry_3_rl[557];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d536 =
|
|
entry_0_rl[573];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d536 =
|
|
entry_1_rl[573];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d536 =
|
|
entry_2_rl[573];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d536 =
|
|
entry_3_rl[573];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d553 =
|
|
entry_0_rl[524];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d553 =
|
|
entry_1_rl[524];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d553 =
|
|
entry_2_rl[524];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d553 =
|
|
entry_3_rl[524];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d567 =
|
|
entry_0_rl[540];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d567 =
|
|
entry_1_rl[540];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d567 =
|
|
entry_2_rl[540];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d567 =
|
|
entry_3_rl[540];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d595 =
|
|
entry_0_rl[572];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d595 =
|
|
entry_1_rl[572];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d595 =
|
|
entry_2_rl[572];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d595 =
|
|
entry_3_rl[572];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d581 =
|
|
entry_0_rl[556];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d581 =
|
|
entry_1_rl[556];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d581 =
|
|
entry_2_rl[556];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d581 =
|
|
entry_3_rl[556];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d611 =
|
|
entry_0_rl[523];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d611 =
|
|
entry_1_rl[523];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d611 =
|
|
entry_2_rl[523];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d611 =
|
|
entry_3_rl[523];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d625 =
|
|
entry_0_rl[539];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d625 =
|
|
entry_1_rl[539];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d625 =
|
|
entry_2_rl[539];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d625 =
|
|
entry_3_rl[539];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d639 =
|
|
entry_0_rl[555];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d639 =
|
|
entry_1_rl[555];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d639 =
|
|
entry_2_rl[555];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d639 =
|
|
entry_3_rl[555];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d653 =
|
|
entry_0_rl[571];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d653 =
|
|
entry_1_rl[571];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d653 =
|
|
entry_2_rl[571];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d653 =
|
|
entry_3_rl[571];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d670 =
|
|
entry_0_rl[522];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d670 =
|
|
entry_1_rl[522];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d670 =
|
|
entry_2_rl[522];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d670 =
|
|
entry_3_rl[522];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d684 =
|
|
entry_0_rl[538];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d684 =
|
|
entry_1_rl[538];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d684 =
|
|
entry_2_rl[538];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d684 =
|
|
entry_3_rl[538];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d698 =
|
|
entry_0_rl[554];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d698 =
|
|
entry_1_rl[554];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d698 =
|
|
entry_2_rl[554];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d698 =
|
|
entry_3_rl[554];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d712 =
|
|
entry_0_rl[570];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d712 =
|
|
entry_1_rl[570];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d712 =
|
|
entry_2_rl[570];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d712 =
|
|
entry_3_rl[570];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d728 =
|
|
entry_0_rl[521];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d728 =
|
|
entry_1_rl[521];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d728 =
|
|
entry_2_rl[521];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d728 =
|
|
entry_3_rl[521];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d742 =
|
|
entry_0_rl[537];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d742 =
|
|
entry_1_rl[537];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d742 =
|
|
entry_2_rl[537];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d742 =
|
|
entry_3_rl[537];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d756 =
|
|
entry_0_rl[553];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d756 =
|
|
entry_1_rl[553];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d756 =
|
|
entry_2_rl[553];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d756 =
|
|
entry_3_rl[553];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d770 =
|
|
entry_0_rl[569];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d770 =
|
|
entry_1_rl[569];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d770 =
|
|
entry_2_rl[569];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d770 =
|
|
entry_3_rl[569];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d787 =
|
|
entry_0_rl[520];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d787 =
|
|
entry_1_rl[520];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d787 =
|
|
entry_2_rl[520];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d787 =
|
|
entry_3_rl[520];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d801 =
|
|
entry_0_rl[536];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d801 =
|
|
entry_1_rl[536];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d801 =
|
|
entry_2_rl[536];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d801 =
|
|
entry_3_rl[536];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d815 =
|
|
entry_0_rl[552];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d815 =
|
|
entry_1_rl[552];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d815 =
|
|
entry_2_rl[552];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d815 =
|
|
entry_3_rl[552];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d829 =
|
|
entry_0_rl[568];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d829 =
|
|
entry_1_rl[568];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d829 =
|
|
entry_2_rl[568];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d829 =
|
|
entry_3_rl[568];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d845 =
|
|
entry_0_rl[519];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d845 =
|
|
entry_1_rl[519];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d845 =
|
|
entry_2_rl[519];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d845 =
|
|
entry_3_rl[519];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d859 =
|
|
entry_0_rl[535];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d859 =
|
|
entry_1_rl[535];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d859 =
|
|
entry_2_rl[535];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d859 =
|
|
entry_3_rl[535];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d873 =
|
|
entry_0_rl[551];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d873 =
|
|
entry_1_rl[551];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d873 =
|
|
entry_2_rl[551];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d873 =
|
|
entry_3_rl[551];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d887 =
|
|
entry_0_rl[567];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d887 =
|
|
entry_1_rl[567];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d887 =
|
|
entry_2_rl[567];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d887 =
|
|
entry_3_rl[567];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d904 =
|
|
entry_0_rl[518];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d904 =
|
|
entry_1_rl[518];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d904 =
|
|
entry_2_rl[518];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d904 =
|
|
entry_3_rl[518];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d918 =
|
|
entry_0_rl[534];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d918 =
|
|
entry_1_rl[534];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d918 =
|
|
entry_2_rl[534];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d918 =
|
|
entry_3_rl[534];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d932 =
|
|
entry_0_rl[550];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d932 =
|
|
entry_1_rl[550];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d932 =
|
|
entry_2_rl[550];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d932 =
|
|
entry_3_rl[550];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d946 =
|
|
entry_0_rl[566];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d946 =
|
|
entry_1_rl[566];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d946 =
|
|
entry_2_rl[566];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d946 =
|
|
entry_3_rl[566];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d962 =
|
|
entry_0_rl[517];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d962 =
|
|
entry_1_rl[517];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d962 =
|
|
entry_2_rl[517];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d962 =
|
|
entry_3_rl[517];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d976 =
|
|
entry_0_rl[533];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d976 =
|
|
entry_1_rl[533];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d976 =
|
|
entry_2_rl[533];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d976 =
|
|
entry_3_rl[533];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d990 =
|
|
entry_0_rl[549];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d990 =
|
|
entry_1_rl[549];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d990 =
|
|
entry_2_rl[549];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d990 =
|
|
entry_3_rl[549];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1004 =
|
|
entry_0_rl[565];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1004 =
|
|
entry_1_rl[565];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1004 =
|
|
entry_2_rl[565];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1004 =
|
|
entry_3_rl[565];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1023 =
|
|
entry_0_rl[516];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1023 =
|
|
entry_1_rl[516];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1023 =
|
|
entry_2_rl[516];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1023 =
|
|
entry_3_rl[516];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1037 =
|
|
entry_0_rl[532];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1037 =
|
|
entry_1_rl[532];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1037 =
|
|
entry_2_rl[532];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1037 =
|
|
entry_3_rl[532];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1051 =
|
|
entry_0_rl[548];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1051 =
|
|
entry_1_rl[548];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1051 =
|
|
entry_2_rl[548];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1051 =
|
|
entry_3_rl[548];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1065 =
|
|
entry_0_rl[564];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1065 =
|
|
entry_1_rl[564];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1065 =
|
|
entry_2_rl[564];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1065 =
|
|
entry_3_rl[564];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127 =
|
|
entry_0_rl[515];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127 =
|
|
entry_1_rl[515];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127 =
|
|
entry_2_rl[515];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127 =
|
|
entry_3_rl[515];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142 =
|
|
entry_0_rl[514];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142 =
|
|
entry_1_rl[514];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142 =
|
|
entry_2_rl[514];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142 =
|
|
entry_3_rl[514];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or entry_0_rl)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_1_ETC__q1 =
|
|
entry_0_rl[127:64];
|
|
2'd1:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_1_ETC__q1 =
|
|
entry_0_rl[255:192];
|
|
2'd2:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_1_ETC__q1 =
|
|
entry_0_rl[383:320];
|
|
2'd3:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_1_ETC__q1 =
|
|
entry_0_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or entry_1_rl)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_1_ETC__q2 =
|
|
entry_1_rl[127:64];
|
|
2'd1:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_1_ETC__q2 =
|
|
entry_1_rl[255:192];
|
|
2'd2:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_1_ETC__q2 =
|
|
entry_1_rl[383:320];
|
|
2'd3:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_1_ETC__q2 =
|
|
entry_1_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or entry_2_rl)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_1_ETC__q3 =
|
|
entry_2_rl[127:64];
|
|
2'd1:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_1_ETC__q3 =
|
|
entry_2_rl[255:192];
|
|
2'd2:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_1_ETC__q3 =
|
|
entry_2_rl[383:320];
|
|
2'd3:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_1_ETC__q3 =
|
|
entry_2_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or entry_3_rl)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_1_ETC__q4 =
|
|
entry_3_rl[127:64];
|
|
2'd1:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_1_ETC__q4 =
|
|
entry_3_rl[255:192];
|
|
2'd2:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_1_ETC__q4 =
|
|
entry_3_rl[383:320];
|
|
2'd3:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_1_ETC__q4 =
|
|
entry_3_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(enq_idx or
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_1_ETC__q1 or
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_1_ETC__q2 or
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_1_ETC__q3 or
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_1_ETC__q4)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250 =
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_1_ETC__q1;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250 =
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_1_ETC__q2;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250 =
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_1_ETC__q3;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1250 =
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_1_ETC__q4;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or entry_0_rl)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_6_ETC__q5 =
|
|
entry_0_rl[63:0];
|
|
2'd1:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_6_ETC__q5 =
|
|
entry_0_rl[191:128];
|
|
2'd2:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_6_ETC__q5 =
|
|
entry_0_rl[319:256];
|
|
2'd3:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_6_ETC__q5 =
|
|
entry_0_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or entry_1_rl)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_6_ETC__q6 =
|
|
entry_1_rl[63:0];
|
|
2'd1:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_6_ETC__q6 =
|
|
entry_1_rl[191:128];
|
|
2'd2:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_6_ETC__q6 =
|
|
entry_1_rl[319:256];
|
|
2'd3:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_6_ETC__q6 =
|
|
entry_1_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or entry_2_rl)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_6_ETC__q7 =
|
|
entry_2_rl[63:0];
|
|
2'd1:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_6_ETC__q7 =
|
|
entry_2_rl[191:128];
|
|
2'd2:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_6_ETC__q7 =
|
|
entry_2_rl[319:256];
|
|
2'd3:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_6_ETC__q7 =
|
|
entry_2_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or entry_3_rl)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_6_ETC__q8 =
|
|
entry_3_rl[63:0];
|
|
2'd1:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_6_ETC__q8 =
|
|
entry_3_rl[191:128];
|
|
2'd2:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_6_ETC__q8 =
|
|
entry_3_rl[319:256];
|
|
2'd3:
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_6_ETC__q8 =
|
|
entry_3_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(enq_idx or
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_6_ETC__q5 or
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_6_ETC__q6 or
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_6_ETC__q7 or
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_6_ETC__q8)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343 =
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_0_rl_BITS_6_ETC__q5;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343 =
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_1_rl_BITS_6_ETC__q6;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343 =
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_2_rl_BITS_6_ETC__q7;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1343 =
|
|
CASE_enq_paddr_BITS_5_TO_4_0_entry_3_rl_BITS_6_ETC__q8;
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1384 =
|
|
entry_0_rl[383:320];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1384 =
|
|
entry_1_rl[383:320];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1384 =
|
|
entry_2_rl[383:320];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1384 =
|
|
entry_3_rl[383:320];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1378 =
|
|
entry_0_rl[511:448];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1378 =
|
|
entry_1_rl[511:448];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1378 =
|
|
entry_2_rl[511:448];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1378 =
|
|
entry_3_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1390 =
|
|
entry_0_rl[255:192];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1390 =
|
|
entry_1_rl[255:192];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1390 =
|
|
entry_2_rl[255:192];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1390 =
|
|
entry_3_rl[255:192];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1397 =
|
|
entry_0_rl[127:64];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1397 =
|
|
entry_1_rl[127:64];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1397 =
|
|
entry_2_rl[127:64];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1397 =
|
|
entry_3_rl[127:64];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d144 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d158 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d172 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d186)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d188 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d144;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d188 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d158;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d188 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d172;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d188 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d186;
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1380 =
|
|
entry_0_rl[447:384];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1380 =
|
|
entry_1_rl[447:384];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1380 =
|
|
entry_2_rl[447:384];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1380 =
|
|
entry_3_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d202 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d216 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d230 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d244)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d246 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d202;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d246 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d216;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d246 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d230;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d246 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d244;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d319 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d333 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d347 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d361)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d363 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d319;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d363 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d333;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d363 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d347;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d363 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d361;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d260 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d274 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d288 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d302)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d304 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d260;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d304 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d274;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d304 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d288;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d304 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d302;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d377 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d391 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d405 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d419)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d421 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d377;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d421 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d391;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d421 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d405;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d421 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d419;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d436 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d450 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d464 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d478)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d480 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d436;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d480 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d450;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d480 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d464;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d480 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d478;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d494 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d508 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d522 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d536)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d538 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d494;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d538 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d508;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d538 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d522;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d538 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d536;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d553 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d567 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d581 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d595)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d597 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d553;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d597 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d567;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d597 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d581;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d597 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d595;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d611 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d625 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d639 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d653)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d655 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d611;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d655 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d625;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d655 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d639;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d655 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d653;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d670 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d684 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d698 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d712)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d714 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d670;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d714 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d684;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d714 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d698;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d714 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d712;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d787 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d801 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d815 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d829)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d831 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d787;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d831 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d801;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d831 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d815;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d831 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d829;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d728 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d742 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d756 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d770)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d772 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d728;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d772 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d742;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d772 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d756;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d772 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d770;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d845 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d859 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d873 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d887)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d889 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d845;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d889 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d859;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d889 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d873;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d889 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d887;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d904 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d918 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d932 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d946)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d948 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d904;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d948 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d918;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d948 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d932;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d948 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d946;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d962 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d976 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d990 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1004)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1006 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d962;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1006 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d976;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1006 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d990;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1006 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1004;
|
|
endcase
|
|
end
|
|
always@(enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1023 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1037 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1051 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1065)
|
|
begin
|
|
case (enq_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1067 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1023;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1067 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1037;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1067 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1051;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_IF_entry_0_lat_0_whas_THEN_ent_ETC___d1067 =
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1065;
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1535 =
|
|
entry_0_rl[579];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1535 =
|
|
entry_1_rl[579];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1535 =
|
|
entry_2_rl[579];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1535 =
|
|
entry_3_rl[579];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1537 =
|
|
entry_0_rl[578];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1537 =
|
|
entry_1_rl[578];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1537 =
|
|
entry_2_rl[578];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1537 =
|
|
entry_3_rl[578];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1540 =
|
|
entry_0_rl[577];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1540 =
|
|
entry_1_rl[577];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1540 =
|
|
entry_2_rl[577];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1540 =
|
|
entry_3_rl[577];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1542 =
|
|
entry_0_rl[576];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1542 =
|
|
entry_1_rl[576];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1542 =
|
|
entry_2_rl[576];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1542 =
|
|
entry_3_rl[576];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1545 =
|
|
entry_0_rl[575];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1545 =
|
|
entry_1_rl[575];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1545 =
|
|
entry_2_rl[575];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1545 =
|
|
entry_3_rl[575];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1547 =
|
|
entry_0_rl[574];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1547 =
|
|
entry_1_rl[574];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1547 =
|
|
entry_2_rl[574];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1547 =
|
|
entry_3_rl[574];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1550 =
|
|
entry_0_rl[573];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1550 =
|
|
entry_1_rl[573];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1550 =
|
|
entry_2_rl[573];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1550 =
|
|
entry_3_rl[573];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1552 =
|
|
entry_0_rl[572];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1552 =
|
|
entry_1_rl[572];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1552 =
|
|
entry_2_rl[572];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1552 =
|
|
entry_3_rl[572];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1555 =
|
|
entry_0_rl[571];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1555 =
|
|
entry_1_rl[571];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1555 =
|
|
entry_2_rl[571];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1555 =
|
|
entry_3_rl[571];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1557 =
|
|
entry_0_rl[570];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1557 =
|
|
entry_1_rl[570];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1557 =
|
|
entry_2_rl[570];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1557 =
|
|
entry_3_rl[570];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1560 =
|
|
entry_0_rl[569];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1560 =
|
|
entry_1_rl[569];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1560 =
|
|
entry_2_rl[569];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1560 =
|
|
entry_3_rl[569];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1562 =
|
|
entry_0_rl[568];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1562 =
|
|
entry_1_rl[568];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1562 =
|
|
entry_2_rl[568];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1562 =
|
|
entry_3_rl[568];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1565 =
|
|
entry_0_rl[567];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1565 =
|
|
entry_1_rl[567];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1565 =
|
|
entry_2_rl[567];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1565 =
|
|
entry_3_rl[567];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1567 =
|
|
entry_0_rl[566];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1567 =
|
|
entry_1_rl[566];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1567 =
|
|
entry_2_rl[566];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1567 =
|
|
entry_3_rl[566];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1570 =
|
|
entry_0_rl[565];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1570 =
|
|
entry_1_rl[565];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1570 =
|
|
entry_2_rl[565];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1570 =
|
|
entry_3_rl[565];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1572 =
|
|
entry_0_rl[564];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1572 =
|
|
entry_1_rl[564];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1572 =
|
|
entry_2_rl[564];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1572 =
|
|
entry_3_rl[564];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1575 =
|
|
entry_0_rl[563];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1575 =
|
|
entry_1_rl[563];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1575 =
|
|
entry_2_rl[563];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1575 =
|
|
entry_3_rl[563];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1577 =
|
|
entry_0_rl[562];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1577 =
|
|
entry_1_rl[562];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1577 =
|
|
entry_2_rl[562];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1577 =
|
|
entry_3_rl[562];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1580 =
|
|
entry_0_rl[561];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1580 =
|
|
entry_1_rl[561];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1580 =
|
|
entry_2_rl[561];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1580 =
|
|
entry_3_rl[561];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1582 =
|
|
entry_0_rl[560];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1582 =
|
|
entry_1_rl[560];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1582 =
|
|
entry_2_rl[560];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1582 =
|
|
entry_3_rl[560];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1585 =
|
|
entry_0_rl[559];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1585 =
|
|
entry_1_rl[559];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1585 =
|
|
entry_2_rl[559];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1585 =
|
|
entry_3_rl[559];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1587 =
|
|
entry_0_rl[558];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1587 =
|
|
entry_1_rl[558];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1587 =
|
|
entry_2_rl[558];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1587 =
|
|
entry_3_rl[558];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1590 =
|
|
entry_0_rl[557];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1590 =
|
|
entry_1_rl[557];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1590 =
|
|
entry_2_rl[557];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1590 =
|
|
entry_3_rl[557];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1592 =
|
|
entry_0_rl[556];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1592 =
|
|
entry_1_rl[556];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1592 =
|
|
entry_2_rl[556];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1592 =
|
|
entry_3_rl[556];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1595 =
|
|
entry_0_rl[555];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1595 =
|
|
entry_1_rl[555];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1595 =
|
|
entry_2_rl[555];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1595 =
|
|
entry_3_rl[555];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1597 =
|
|
entry_0_rl[554];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1597 =
|
|
entry_1_rl[554];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1597 =
|
|
entry_2_rl[554];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1597 =
|
|
entry_3_rl[554];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1600 =
|
|
entry_0_rl[553];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1600 =
|
|
entry_1_rl[553];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1600 =
|
|
entry_2_rl[553];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1600 =
|
|
entry_3_rl[553];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1602 =
|
|
entry_0_rl[552];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1602 =
|
|
entry_1_rl[552];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1602 =
|
|
entry_2_rl[552];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1602 =
|
|
entry_3_rl[552];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1605 =
|
|
entry_0_rl[551];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1605 =
|
|
entry_1_rl[551];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1605 =
|
|
entry_2_rl[551];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1605 =
|
|
entry_3_rl[551];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1607 =
|
|
entry_0_rl[550];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1607 =
|
|
entry_1_rl[550];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1607 =
|
|
entry_2_rl[550];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1607 =
|
|
entry_3_rl[550];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1610 =
|
|
entry_0_rl[549];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1610 =
|
|
entry_1_rl[549];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1610 =
|
|
entry_2_rl[549];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1610 =
|
|
entry_3_rl[549];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1612 =
|
|
entry_0_rl[548];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1612 =
|
|
entry_1_rl[548];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1612 =
|
|
entry_2_rl[548];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1612 =
|
|
entry_3_rl[548];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1615 =
|
|
entry_0_rl[547];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1615 =
|
|
entry_1_rl[547];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1615 =
|
|
entry_2_rl[547];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1615 =
|
|
entry_3_rl[547];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1617 =
|
|
entry_0_rl[546];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1617 =
|
|
entry_1_rl[546];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1617 =
|
|
entry_2_rl[546];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1617 =
|
|
entry_3_rl[546];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1620 =
|
|
entry_0_rl[545];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1620 =
|
|
entry_1_rl[545];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1620 =
|
|
entry_2_rl[545];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1620 =
|
|
entry_3_rl[545];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1622 =
|
|
entry_0_rl[544];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1622 =
|
|
entry_1_rl[544];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1622 =
|
|
entry_2_rl[544];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1622 =
|
|
entry_3_rl[544];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1625 =
|
|
entry_0_rl[543];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1625 =
|
|
entry_1_rl[543];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1625 =
|
|
entry_2_rl[543];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1625 =
|
|
entry_3_rl[543];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1627 =
|
|
entry_0_rl[542];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1627 =
|
|
entry_1_rl[542];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1627 =
|
|
entry_2_rl[542];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1627 =
|
|
entry_3_rl[542];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1630 =
|
|
entry_0_rl[541];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1630 =
|
|
entry_1_rl[541];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1630 =
|
|
entry_2_rl[541];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1630 =
|
|
entry_3_rl[541];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1632 =
|
|
entry_0_rl[540];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1632 =
|
|
entry_1_rl[540];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1632 =
|
|
entry_2_rl[540];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1632 =
|
|
entry_3_rl[540];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1635 =
|
|
entry_0_rl[539];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1635 =
|
|
entry_1_rl[539];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1635 =
|
|
entry_2_rl[539];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1635 =
|
|
entry_3_rl[539];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1637 =
|
|
entry_0_rl[538];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1637 =
|
|
entry_1_rl[538];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1637 =
|
|
entry_2_rl[538];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1637 =
|
|
entry_3_rl[538];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1640 =
|
|
entry_0_rl[537];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1640 =
|
|
entry_1_rl[537];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1640 =
|
|
entry_2_rl[537];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1640 =
|
|
entry_3_rl[537];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1642 =
|
|
entry_0_rl[536];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1642 =
|
|
entry_1_rl[536];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1642 =
|
|
entry_2_rl[536];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1642 =
|
|
entry_3_rl[536];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1645 =
|
|
entry_0_rl[535];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1645 =
|
|
entry_1_rl[535];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1645 =
|
|
entry_2_rl[535];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1645 =
|
|
entry_3_rl[535];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1647 =
|
|
entry_0_rl[534];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1647 =
|
|
entry_1_rl[534];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1647 =
|
|
entry_2_rl[534];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1647 =
|
|
entry_3_rl[534];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1650 =
|
|
entry_0_rl[533];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1650 =
|
|
entry_1_rl[533];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1650 =
|
|
entry_2_rl[533];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1650 =
|
|
entry_3_rl[533];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1652 =
|
|
entry_0_rl[532];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1652 =
|
|
entry_1_rl[532];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1652 =
|
|
entry_2_rl[532];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1652 =
|
|
entry_3_rl[532];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1655 =
|
|
entry_0_rl[531];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1655 =
|
|
entry_1_rl[531];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1655 =
|
|
entry_2_rl[531];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1655 =
|
|
entry_3_rl[531];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1657 =
|
|
entry_0_rl[530];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1657 =
|
|
entry_1_rl[530];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1657 =
|
|
entry_2_rl[530];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1657 =
|
|
entry_3_rl[530];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1660 =
|
|
entry_0_rl[529];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1660 =
|
|
entry_1_rl[529];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1660 =
|
|
entry_2_rl[529];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1660 =
|
|
entry_3_rl[529];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1665 =
|
|
entry_0_rl[527];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1665 =
|
|
entry_1_rl[527];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1665 =
|
|
entry_2_rl[527];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1665 =
|
|
entry_3_rl[527];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1662 =
|
|
entry_0_rl[528];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1662 =
|
|
entry_1_rl[528];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1662 =
|
|
entry_2_rl[528];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1662 =
|
|
entry_3_rl[528];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1667 =
|
|
entry_0_rl[526];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1667 =
|
|
entry_1_rl[526];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1667 =
|
|
entry_2_rl[526];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1667 =
|
|
entry_3_rl[526];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1670 =
|
|
entry_0_rl[525];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1670 =
|
|
entry_1_rl[525];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1670 =
|
|
entry_2_rl[525];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1670 =
|
|
entry_3_rl[525];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1672 =
|
|
entry_0_rl[524];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1672 =
|
|
entry_1_rl[524];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1672 =
|
|
entry_2_rl[524];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1672 =
|
|
entry_3_rl[524];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1675 =
|
|
entry_0_rl[523];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1675 =
|
|
entry_1_rl[523];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1675 =
|
|
entry_2_rl[523];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1675 =
|
|
entry_3_rl[523];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1677 =
|
|
entry_0_rl[522];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1677 =
|
|
entry_1_rl[522];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1677 =
|
|
entry_2_rl[522];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1677 =
|
|
entry_3_rl[522];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1680 =
|
|
entry_0_rl[521];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1680 =
|
|
entry_1_rl[521];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1680 =
|
|
entry_2_rl[521];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1680 =
|
|
entry_3_rl[521];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1682 =
|
|
entry_0_rl[520];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1682 =
|
|
entry_1_rl[520];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1682 =
|
|
entry_2_rl[520];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1682 =
|
|
entry_3_rl[520];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1685 =
|
|
entry_0_rl[519];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1685 =
|
|
entry_1_rl[519];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1685 =
|
|
entry_2_rl[519];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1685 =
|
|
entry_3_rl[519];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1687 =
|
|
entry_0_rl[518];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1687 =
|
|
entry_1_rl[518];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1687 =
|
|
entry_2_rl[518];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1687 =
|
|
entry_3_rl[518];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1695 =
|
|
entry_0_rl[515];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1695 =
|
|
entry_1_rl[515];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1695 =
|
|
entry_2_rl[515];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1695 =
|
|
entry_3_rl[515];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1704 =
|
|
entry_0_rl[511:448];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1704 =
|
|
entry_1_rl[511:448];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1704 =
|
|
entry_2_rl[511:448];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1704 =
|
|
entry_3_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1709 =
|
|
entry_0_rl[383:320];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1709 =
|
|
entry_1_rl[383:320];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1709 =
|
|
entry_2_rl[383:320];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1709 =
|
|
entry_3_rl[383:320];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1706 =
|
|
entry_0_rl[447:384];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1706 =
|
|
entry_1_rl[447:384];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1706 =
|
|
entry_2_rl[447:384];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1706 =
|
|
entry_3_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1719 =
|
|
entry_0_rl[127:64];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1719 =
|
|
entry_1_rl[127:64];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1719 =
|
|
entry_2_rl[127:64];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1719 =
|
|
entry_3_rl[127:64];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1697 =
|
|
entry_0_rl[514];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1697 =
|
|
entry_1_rl[514];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1697 =
|
|
entry_2_rl[514];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1697 =
|
|
entry_3_rl[514];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1699 =
|
|
entry_0_rl[513];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1699 =
|
|
entry_1_rl[513];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1699 =
|
|
entry_2_rl[513];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1699 =
|
|
entry_3_rl[513];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1726 =
|
|
entry_0_rl[579];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1726 =
|
|
entry_1_rl[579];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1726 =
|
|
entry_2_rl[579];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d1726 =
|
|
entry_3_rl[579];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1727 =
|
|
entry_0_rl[578];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1727 =
|
|
entry_1_rl[578];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1727 =
|
|
entry_2_rl[578];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d1727 =
|
|
entry_3_rl[578];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1728 =
|
|
entry_0_rl[577];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1728 =
|
|
entry_1_rl[577];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1728 =
|
|
entry_2_rl[577];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d1728 =
|
|
entry_3_rl[577];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1730 =
|
|
entry_0_rl[576];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1730 =
|
|
entry_1_rl[576];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1730 =
|
|
entry_2_rl[576];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d1730 =
|
|
entry_3_rl[576];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1731 =
|
|
entry_0_rl[575];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1731 =
|
|
entry_1_rl[575];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1731 =
|
|
entry_2_rl[575];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d1731 =
|
|
entry_3_rl[575];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1733 =
|
|
entry_0_rl[574];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1733 =
|
|
entry_1_rl[574];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1733 =
|
|
entry_2_rl[574];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d1733 =
|
|
entry_3_rl[574];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1734 =
|
|
entry_0_rl[573];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1734 =
|
|
entry_1_rl[573];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1734 =
|
|
entry_2_rl[573];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d1734 =
|
|
entry_3_rl[573];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1736 =
|
|
entry_0_rl[572];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1736 =
|
|
entry_1_rl[572];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1736 =
|
|
entry_2_rl[572];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d1736 =
|
|
entry_3_rl[572];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1737 =
|
|
entry_0_rl[571];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1737 =
|
|
entry_1_rl[571];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1737 =
|
|
entry_2_rl[571];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d1737 =
|
|
entry_3_rl[571];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1739 =
|
|
entry_0_rl[570];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1739 =
|
|
entry_1_rl[570];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1739 =
|
|
entry_2_rl[570];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d1739 =
|
|
entry_3_rl[570];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1740 =
|
|
entry_0_rl[569];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1740 =
|
|
entry_1_rl[569];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1740 =
|
|
entry_2_rl[569];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d1740 =
|
|
entry_3_rl[569];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1742 =
|
|
entry_0_rl[568];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1742 =
|
|
entry_1_rl[568];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1742 =
|
|
entry_2_rl[568];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d1742 =
|
|
entry_3_rl[568];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1743 =
|
|
entry_0_rl[567];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1743 =
|
|
entry_1_rl[567];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1743 =
|
|
entry_2_rl[567];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d1743 =
|
|
entry_3_rl[567];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1821 =
|
|
entry_0_rl[515];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1821 =
|
|
entry_1_rl[515];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1821 =
|
|
entry_2_rl[515];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_515_115_entry_1_rl_2_BI_ETC___d1821 =
|
|
entry_3_rl[515];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1822 =
|
|
entry_0_rl[514];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1822 =
|
|
entry_1_rl[514];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1822 =
|
|
entry_2_rl[514];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_514_130_entry_1_rl_2_BI_ETC___d1822 =
|
|
entry_3_rl[514];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1832 =
|
|
entry_0_rl[255:192];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1832 =
|
|
entry_1_rl[255:192];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1832 =
|
|
entry_2_rl[255:192];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1832 =
|
|
entry_3_rl[255:192];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q9 =
|
|
entry_0_rl[531];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q9 =
|
|
entry_0_rl[547];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q9 =
|
|
entry_0_rl[563];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q9 =
|
|
entry_0_rl[579];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q10 =
|
|
entry_0_rl[530];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q10 =
|
|
entry_0_rl[546];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q10 =
|
|
entry_0_rl[562];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q10 =
|
|
entry_0_rl[578];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q11 =
|
|
entry_0_rl[529];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q11 =
|
|
entry_0_rl[545];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q11 =
|
|
entry_0_rl[561];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q11 =
|
|
entry_0_rl[577];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q12 =
|
|
entry_0_rl[528];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q12 =
|
|
entry_0_rl[544];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q12 =
|
|
entry_0_rl[560];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q12 =
|
|
entry_0_rl[576];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q13 =
|
|
entry_0_rl[527];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q13 =
|
|
entry_0_rl[543];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q13 =
|
|
entry_0_rl[559];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q13 =
|
|
entry_0_rl[575];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q14 =
|
|
entry_0_rl[526];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q14 =
|
|
entry_0_rl[542];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q14 =
|
|
entry_0_rl[558];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q14 =
|
|
entry_0_rl[574];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q15 =
|
|
entry_0_rl[525];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q15 =
|
|
entry_0_rl[541];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q15 =
|
|
entry_0_rl[557];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q15 =
|
|
entry_0_rl[573];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q16 =
|
|
entry_0_rl[524];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q16 =
|
|
entry_0_rl[540];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q16 =
|
|
entry_0_rl[556];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q16 =
|
|
entry_0_rl[572];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q17 =
|
|
entry_0_rl[523];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q17 =
|
|
entry_0_rl[539];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q17 =
|
|
entry_0_rl[555];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q17 =
|
|
entry_0_rl[571];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q18 =
|
|
entry_0_rl[522];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q18 =
|
|
entry_0_rl[538];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q18 =
|
|
entry_0_rl[554];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q18 =
|
|
entry_0_rl[570];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q19 =
|
|
entry_0_rl[521];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q19 =
|
|
entry_0_rl[537];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q19 =
|
|
entry_0_rl[553];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q19 =
|
|
entry_0_rl[569];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q20 =
|
|
entry_0_rl[520];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q20 =
|
|
entry_0_rl[536];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q20 =
|
|
entry_0_rl[552];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q20 =
|
|
entry_0_rl[568];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q21 =
|
|
entry_0_rl[519];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q21 =
|
|
entry_0_rl[535];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q21 =
|
|
entry_0_rl[551];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q21 =
|
|
entry_0_rl[567];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q22 =
|
|
entry_0_rl[518];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q22 =
|
|
entry_0_rl[534];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q22 =
|
|
entry_0_rl[550];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q22 =
|
|
entry_0_rl[566];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q23 =
|
|
entry_0_rl[517];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q23 =
|
|
entry_0_rl[533];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q23 =
|
|
entry_0_rl[549];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q23 =
|
|
entry_0_rl[565];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q24 =
|
|
entry_0_rl[516];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q24 =
|
|
entry_0_rl[532];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q24 =
|
|
entry_0_rl[548];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q24 =
|
|
entry_0_rl[564];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q25 =
|
|
entry_1_rl[531];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q25 =
|
|
entry_1_rl[547];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q25 =
|
|
entry_1_rl[563];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q25 =
|
|
entry_1_rl[579];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q26 =
|
|
entry_1_rl[530];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q26 =
|
|
entry_1_rl[546];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q26 =
|
|
entry_1_rl[562];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q26 =
|
|
entry_1_rl[578];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q27 =
|
|
entry_1_rl[529];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q27 =
|
|
entry_1_rl[545];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q27 =
|
|
entry_1_rl[561];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q27 =
|
|
entry_1_rl[577];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q28 =
|
|
entry_1_rl[528];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q28 =
|
|
entry_1_rl[544];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q28 =
|
|
entry_1_rl[560];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q28 =
|
|
entry_1_rl[576];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q29 =
|
|
entry_1_rl[527];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q29 =
|
|
entry_1_rl[543];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q29 =
|
|
entry_1_rl[559];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q29 =
|
|
entry_1_rl[575];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q30 =
|
|
entry_1_rl[526];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q30 =
|
|
entry_1_rl[542];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q30 =
|
|
entry_1_rl[558];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q30 =
|
|
entry_1_rl[574];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q31 =
|
|
entry_1_rl[525];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q31 =
|
|
entry_1_rl[541];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q31 =
|
|
entry_1_rl[557];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q31 =
|
|
entry_1_rl[573];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q32 =
|
|
entry_1_rl[524];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q32 =
|
|
entry_1_rl[540];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q32 =
|
|
entry_1_rl[556];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q32 =
|
|
entry_1_rl[572];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q33 =
|
|
entry_1_rl[523];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q33 =
|
|
entry_1_rl[539];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q33 =
|
|
entry_1_rl[555];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q33 =
|
|
entry_1_rl[571];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q34 =
|
|
entry_1_rl[522];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q34 =
|
|
entry_1_rl[538];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q34 =
|
|
entry_1_rl[554];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q34 =
|
|
entry_1_rl[570];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q35 =
|
|
entry_1_rl[521];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q35 =
|
|
entry_1_rl[537];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q35 =
|
|
entry_1_rl[553];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q35 =
|
|
entry_1_rl[569];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q36 =
|
|
entry_1_rl[520];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q36 =
|
|
entry_1_rl[536];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q36 =
|
|
entry_1_rl[552];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q36 =
|
|
entry_1_rl[568];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q37 =
|
|
entry_1_rl[519];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q37 =
|
|
entry_1_rl[535];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q37 =
|
|
entry_1_rl[551];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q37 =
|
|
entry_1_rl[567];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q38 =
|
|
entry_1_rl[518];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q38 =
|
|
entry_1_rl[534];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q38 =
|
|
entry_1_rl[550];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q38 =
|
|
entry_1_rl[566];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q39 =
|
|
entry_1_rl[517];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q39 =
|
|
entry_1_rl[533];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q39 =
|
|
entry_1_rl[549];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q39 =
|
|
entry_1_rl[565];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q40 =
|
|
entry_1_rl[516];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q40 =
|
|
entry_1_rl[532];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q40 =
|
|
entry_1_rl[548];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q40 =
|
|
entry_1_rl[564];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q41 =
|
|
entry_2_rl[531];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q41 =
|
|
entry_2_rl[547];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q41 =
|
|
entry_2_rl[563];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q41 =
|
|
entry_2_rl[579];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q42 =
|
|
entry_2_rl[530];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q42 =
|
|
entry_2_rl[546];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q42 =
|
|
entry_2_rl[562];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q42 =
|
|
entry_2_rl[578];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q43 =
|
|
entry_2_rl[529];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q43 =
|
|
entry_2_rl[545];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q43 =
|
|
entry_2_rl[561];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q43 =
|
|
entry_2_rl[577];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q44 =
|
|
entry_2_rl[528];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q44 =
|
|
entry_2_rl[544];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q44 =
|
|
entry_2_rl[560];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q44 =
|
|
entry_2_rl[576];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q45 =
|
|
entry_2_rl[527];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q45 =
|
|
entry_2_rl[543];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q45 =
|
|
entry_2_rl[559];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q45 =
|
|
entry_2_rl[575];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q46 =
|
|
entry_2_rl[526];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q46 =
|
|
entry_2_rl[542];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q46 =
|
|
entry_2_rl[558];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q46 =
|
|
entry_2_rl[574];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q47 =
|
|
entry_2_rl[525];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q47 =
|
|
entry_2_rl[541];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q47 =
|
|
entry_2_rl[557];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q47 =
|
|
entry_2_rl[573];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q48 =
|
|
entry_2_rl[524];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q48 =
|
|
entry_2_rl[540];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q48 =
|
|
entry_2_rl[556];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q48 =
|
|
entry_2_rl[572];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q49 =
|
|
entry_2_rl[523];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q49 =
|
|
entry_2_rl[539];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q49 =
|
|
entry_2_rl[555];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q49 =
|
|
entry_2_rl[571];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q50 =
|
|
entry_2_rl[522];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q50 =
|
|
entry_2_rl[538];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q50 =
|
|
entry_2_rl[554];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q50 =
|
|
entry_2_rl[570];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q51 =
|
|
entry_2_rl[521];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q51 =
|
|
entry_2_rl[537];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q51 =
|
|
entry_2_rl[553];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q51 =
|
|
entry_2_rl[569];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q52 =
|
|
entry_2_rl[520];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q52 =
|
|
entry_2_rl[536];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q52 =
|
|
entry_2_rl[552];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q52 =
|
|
entry_2_rl[568];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q53 =
|
|
entry_2_rl[519];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q53 =
|
|
entry_2_rl[535];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q53 =
|
|
entry_2_rl[551];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q53 =
|
|
entry_2_rl[567];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q54 =
|
|
entry_2_rl[518];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q54 =
|
|
entry_2_rl[534];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q54 =
|
|
entry_2_rl[550];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q54 =
|
|
entry_2_rl[566];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q55 =
|
|
entry_2_rl[517];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q55 =
|
|
entry_2_rl[533];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q55 =
|
|
entry_2_rl[549];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q55 =
|
|
entry_2_rl[565];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q56 =
|
|
entry_2_rl[516];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q56 =
|
|
entry_2_rl[532];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q56 =
|
|
entry_2_rl[548];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q56 =
|
|
entry_2_rl[564];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q57 =
|
|
entry_3_rl[531];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q57 =
|
|
entry_3_rl[547];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q57 =
|
|
entry_3_rl[563];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q57 =
|
|
entry_3_rl[579];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q58 =
|
|
entry_3_rl[530];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q58 =
|
|
entry_3_rl[546];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q58 =
|
|
entry_3_rl[562];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q58 =
|
|
entry_3_rl[578];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q59 =
|
|
entry_3_rl[529];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q59 =
|
|
entry_3_rl[545];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q59 =
|
|
entry_3_rl[561];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q59 =
|
|
entry_3_rl[577];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q60 =
|
|
entry_3_rl[528];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q60 =
|
|
entry_3_rl[544];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q60 =
|
|
entry_3_rl[560];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q60 =
|
|
entry_3_rl[576];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q61 =
|
|
entry_3_rl[527];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q61 =
|
|
entry_3_rl[543];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q61 =
|
|
entry_3_rl[559];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q61 =
|
|
entry_3_rl[575];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q62 =
|
|
entry_3_rl[526];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q62 =
|
|
entry_3_rl[542];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q62 =
|
|
entry_3_rl[558];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q62 =
|
|
entry_3_rl[574];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q63 =
|
|
entry_3_rl[525];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q63 =
|
|
entry_3_rl[541];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q63 =
|
|
entry_3_rl[557];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q63 =
|
|
entry_3_rl[573];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q64 =
|
|
entry_3_rl[524];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q64 =
|
|
entry_3_rl[540];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q64 =
|
|
entry_3_rl[556];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q64 =
|
|
entry_3_rl[572];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q65 =
|
|
entry_3_rl[523];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q65 =
|
|
entry_3_rl[539];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q65 =
|
|
entry_3_rl[555];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q65 =
|
|
entry_3_rl[571];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q66 =
|
|
entry_3_rl[522];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q66 =
|
|
entry_3_rl[538];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q66 =
|
|
entry_3_rl[554];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q66 =
|
|
entry_3_rl[570];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q67 =
|
|
entry_3_rl[521];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q67 =
|
|
entry_3_rl[537];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q67 =
|
|
entry_3_rl[553];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q67 =
|
|
entry_3_rl[569];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q68 =
|
|
entry_3_rl[520];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q68 =
|
|
entry_3_rl[536];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q68 =
|
|
entry_3_rl[552];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q68 =
|
|
entry_3_rl[568];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q69 =
|
|
entry_3_rl[519];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q69 =
|
|
entry_3_rl[535];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q69 =
|
|
entry_3_rl[551];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q69 =
|
|
entry_3_rl[567];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q70 =
|
|
entry_3_rl[518];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q70 =
|
|
entry_3_rl[534];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q70 =
|
|
entry_3_rl[550];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q70 =
|
|
entry_3_rl[566];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q71 =
|
|
entry_3_rl[517];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q71 =
|
|
entry_3_rl[533];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q71 =
|
|
entry_3_rl[549];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q71 =
|
|
entry_3_rl[565];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q72 =
|
|
entry_3_rl[516];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q72 =
|
|
entry_3_rl[532];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q72 =
|
|
entry_3_rl[548];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q72 =
|
|
entry_3_rl[564];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d2053 =
|
|
entry_0_rl[531];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d2053 =
|
|
entry_1_rl[531];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d2053 =
|
|
entry_2_rl[531];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d2053 =
|
|
entry_3_rl[531];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d2054 =
|
|
entry_0_rl[547];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d2054 =
|
|
entry_1_rl[547];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d2054 =
|
|
entry_2_rl[547];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d2054 =
|
|
entry_3_rl[547];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d2055 =
|
|
entry_0_rl[563];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d2055 =
|
|
entry_1_rl[563];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d2055 =
|
|
entry_2_rl[563];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d2055 =
|
|
entry_3_rl[563];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d2056 =
|
|
entry_0_rl[579];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d2056 =
|
|
entry_1_rl[579];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d2056 =
|
|
entry_2_rl[579];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d2056 =
|
|
entry_3_rl[579];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d2059 =
|
|
entry_0_rl[530];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d2059 =
|
|
entry_1_rl[530];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d2059 =
|
|
entry_2_rl[530];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d2059 =
|
|
entry_3_rl[530];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d2060 =
|
|
entry_0_rl[546];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d2060 =
|
|
entry_1_rl[546];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d2060 =
|
|
entry_2_rl[546];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d2060 =
|
|
entry_3_rl[546];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d2061 =
|
|
entry_0_rl[562];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d2061 =
|
|
entry_1_rl[562];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d2061 =
|
|
entry_2_rl[562];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d2061 =
|
|
entry_3_rl[562];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d2062 =
|
|
entry_0_rl[578];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d2062 =
|
|
entry_1_rl[578];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d2062 =
|
|
entry_2_rl[578];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d2062 =
|
|
entry_3_rl[578];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d2065 =
|
|
entry_0_rl[529];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d2065 =
|
|
entry_1_rl[529];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d2065 =
|
|
entry_2_rl[529];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d2065 =
|
|
entry_3_rl[529];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d2066 =
|
|
entry_0_rl[545];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d2066 =
|
|
entry_1_rl[545];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d2066 =
|
|
entry_2_rl[545];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d2066 =
|
|
entry_3_rl[545];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d2067 =
|
|
entry_0_rl[561];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d2067 =
|
|
entry_1_rl[561];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d2067 =
|
|
entry_2_rl[561];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d2067 =
|
|
entry_3_rl[561];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d2068 =
|
|
entry_0_rl[577];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d2068 =
|
|
entry_1_rl[577];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d2068 =
|
|
entry_2_rl[577];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d2068 =
|
|
entry_3_rl[577];
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d2053 or
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d2054 or
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d2055 or
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d2056)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2058 =
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d2053;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2058 =
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d2054;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2058 =
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d2055;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_531_32_entry_1__ETC___d2058 =
|
|
SEL_ARR_entry_0_rl_BIT_579_74_entry_1_rl_2_BIT_ETC___d2056;
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d2072 =
|
|
entry_0_rl[528];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d2072 =
|
|
entry_1_rl[528];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d2072 =
|
|
entry_2_rl[528];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d2072 =
|
|
entry_3_rl[528];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d2073 =
|
|
entry_0_rl[544];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d2073 =
|
|
entry_1_rl[544];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d2073 =
|
|
entry_2_rl[544];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d2073 =
|
|
entry_3_rl[544];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d2074 =
|
|
entry_0_rl[560];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d2074 =
|
|
entry_1_rl[560];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d2074 =
|
|
entry_2_rl[560];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d2074 =
|
|
entry_3_rl[560];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d2078 =
|
|
entry_0_rl[527];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d2078 =
|
|
entry_1_rl[527];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d2078 =
|
|
entry_2_rl[527];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d2078 =
|
|
entry_3_rl[527];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d2075 =
|
|
entry_0_rl[576];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d2075 =
|
|
entry_1_rl[576];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d2075 =
|
|
entry_2_rl[576];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d2075 =
|
|
entry_3_rl[576];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d2079 =
|
|
entry_0_rl[543];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d2079 =
|
|
entry_1_rl[543];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d2079 =
|
|
entry_2_rl[543];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d2079 =
|
|
entry_3_rl[543];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d2080 =
|
|
entry_0_rl[559];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d2080 =
|
|
entry_1_rl[559];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d2080 =
|
|
entry_2_rl[559];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d2080 =
|
|
entry_3_rl[559];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d2081 =
|
|
entry_0_rl[575];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d2081 =
|
|
entry_1_rl[575];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d2081 =
|
|
entry_2_rl[575];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d2081 =
|
|
entry_3_rl[575];
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d2059 or
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d2060 or
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d2061 or
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d2062)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_530_90_entry_1__ETC___d2064 =
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d2059;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_530_90_entry_1__ETC___d2064 =
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d2060;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_530_90_entry_1__ETC___d2064 =
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d2061;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_530_90_entry_1__ETC___d2064 =
|
|
SEL_ARR_entry_0_rl_BIT_578_32_entry_1_rl_2_BIT_ETC___d2062;
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d2065 or
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d2066 or
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d2067 or
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d2068)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_529_48_entry_1__ETC___d2070 =
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d2065;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_529_48_entry_1__ETC___d2070 =
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d2066;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_529_48_entry_1__ETC___d2070 =
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d2067;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_529_48_entry_1__ETC___d2070 =
|
|
SEL_ARR_entry_0_rl_BIT_577_90_entry_1_rl_2_BIT_ETC___d2068;
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d2085 =
|
|
entry_0_rl[526];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d2085 =
|
|
entry_1_rl[526];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d2085 =
|
|
entry_2_rl[526];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d2085 =
|
|
entry_3_rl[526];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d2086 =
|
|
entry_0_rl[542];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d2086 =
|
|
entry_1_rl[542];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d2086 =
|
|
entry_2_rl[542];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d2086 =
|
|
entry_3_rl[542];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d2087 =
|
|
entry_0_rl[558];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d2087 =
|
|
entry_1_rl[558];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d2087 =
|
|
entry_2_rl[558];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d2087 =
|
|
entry_3_rl[558];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d2088 =
|
|
entry_0_rl[574];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d2088 =
|
|
entry_1_rl[574];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d2088 =
|
|
entry_2_rl[574];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d2088 =
|
|
entry_3_rl[574];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d2091 =
|
|
entry_0_rl[525];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d2091 =
|
|
entry_1_rl[525];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d2091 =
|
|
entry_2_rl[525];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d2091 =
|
|
entry_3_rl[525];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d2092 =
|
|
entry_0_rl[541];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d2092 =
|
|
entry_1_rl[541];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d2092 =
|
|
entry_2_rl[541];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d2092 =
|
|
entry_3_rl[541];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d2093 =
|
|
entry_0_rl[557];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d2093 =
|
|
entry_1_rl[557];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d2093 =
|
|
entry_2_rl[557];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d2093 =
|
|
entry_3_rl[557];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d2094 =
|
|
entry_0_rl[573];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d2094 =
|
|
entry_1_rl[573];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d2094 =
|
|
entry_2_rl[573];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d2094 =
|
|
entry_3_rl[573];
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d2072 or
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d2073 or
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d2074 or
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d2075)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_528_07_entry_1__ETC___d2077 =
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d2072;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_528_07_entry_1__ETC___d2077 =
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d2073;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_528_07_entry_1__ETC___d2077 =
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d2074;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_528_07_entry_1__ETC___d2077 =
|
|
SEL_ARR_entry_0_rl_BIT_576_49_entry_1_rl_2_BIT_ETC___d2075;
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d2078 or
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d2079 or
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d2080 or
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d2081)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_527_65_entry_1__ETC___d2083 =
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d2078;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_527_65_entry_1__ETC___d2083 =
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d2079;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_527_65_entry_1__ETC___d2083 =
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d2080;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_527_65_entry_1__ETC___d2083 =
|
|
SEL_ARR_entry_0_rl_BIT_575_07_entry_1_rl_2_BIT_ETC___d2081;
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d2098 =
|
|
entry_0_rl[524];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d2098 =
|
|
entry_1_rl[524];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d2098 =
|
|
entry_2_rl[524];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d2098 =
|
|
entry_3_rl[524];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d2099 =
|
|
entry_0_rl[540];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d2099 =
|
|
entry_1_rl[540];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d2099 =
|
|
entry_2_rl[540];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d2099 =
|
|
entry_3_rl[540];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d2100 =
|
|
entry_0_rl[556];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d2100 =
|
|
entry_1_rl[556];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d2100 =
|
|
entry_2_rl[556];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d2100 =
|
|
entry_3_rl[556];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d2101 =
|
|
entry_0_rl[572];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d2101 =
|
|
entry_1_rl[572];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d2101 =
|
|
entry_2_rl[572];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d2101 =
|
|
entry_3_rl[572];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d2104 =
|
|
entry_0_rl[523];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d2104 =
|
|
entry_1_rl[523];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d2104 =
|
|
entry_2_rl[523];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d2104 =
|
|
entry_3_rl[523];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d2105 =
|
|
entry_0_rl[539];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d2105 =
|
|
entry_1_rl[539];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d2105 =
|
|
entry_2_rl[539];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d2105 =
|
|
entry_3_rl[539];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d2106 =
|
|
entry_0_rl[555];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d2106 =
|
|
entry_1_rl[555];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d2106 =
|
|
entry_2_rl[555];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d2106 =
|
|
entry_3_rl[555];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d2107 =
|
|
entry_0_rl[571];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d2107 =
|
|
entry_1_rl[571];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d2107 =
|
|
entry_2_rl[571];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d2107 =
|
|
entry_3_rl[571];
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d2085 or
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d2086 or
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d2087 or
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d2088)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_526_24_entry_1__ETC___d2090 =
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d2085;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_526_24_entry_1__ETC___d2090 =
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d2086;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_526_24_entry_1__ETC___d2090 =
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d2087;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_526_24_entry_1__ETC___d2090 =
|
|
SEL_ARR_entry_0_rl_BIT_574_66_entry_1_rl_2_BIT_ETC___d2088;
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d2091 or
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d2092 or
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d2093 or
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d2094)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_525_82_entry_1__ETC___d2096 =
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d2091;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_525_82_entry_1__ETC___d2096 =
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d2092;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_525_82_entry_1__ETC___d2096 =
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d2093;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_525_82_entry_1__ETC___d2096 =
|
|
SEL_ARR_entry_0_rl_BIT_573_24_entry_1_rl_2_BIT_ETC___d2094;
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d2111 =
|
|
entry_0_rl[522];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d2111 =
|
|
entry_1_rl[522];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d2111 =
|
|
entry_2_rl[522];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d2111 =
|
|
entry_3_rl[522];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d2112 =
|
|
entry_0_rl[538];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d2112 =
|
|
entry_1_rl[538];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d2112 =
|
|
entry_2_rl[538];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d2112 =
|
|
entry_3_rl[538];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d2113 =
|
|
entry_0_rl[554];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d2113 =
|
|
entry_1_rl[554];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d2113 =
|
|
entry_2_rl[554];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d2113 =
|
|
entry_3_rl[554];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d2114 =
|
|
entry_0_rl[570];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d2114 =
|
|
entry_1_rl[570];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d2114 =
|
|
entry_2_rl[570];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d2114 =
|
|
entry_3_rl[570];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d2117 =
|
|
entry_0_rl[521];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d2117 =
|
|
entry_1_rl[521];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d2117 =
|
|
entry_2_rl[521];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d2117 =
|
|
entry_3_rl[521];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d2118 =
|
|
entry_0_rl[537];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d2118 =
|
|
entry_1_rl[537];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d2118 =
|
|
entry_2_rl[537];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d2118 =
|
|
entry_3_rl[537];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d2119 =
|
|
entry_0_rl[553];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d2119 =
|
|
entry_1_rl[553];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d2119 =
|
|
entry_2_rl[553];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d2119 =
|
|
entry_3_rl[553];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d2120 =
|
|
entry_0_rl[569];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d2120 =
|
|
entry_1_rl[569];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d2120 =
|
|
entry_2_rl[569];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d2120 =
|
|
entry_3_rl[569];
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d2098 or
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d2099 or
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d2100 or
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d2101)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_524_41_entry_1__ETC___d2103 =
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d2098;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_524_41_entry_1__ETC___d2103 =
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d2099;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_524_41_entry_1__ETC___d2103 =
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d2100;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_524_41_entry_1__ETC___d2103 =
|
|
SEL_ARR_entry_0_rl_BIT_572_83_entry_1_rl_2_BIT_ETC___d2101;
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d2104 or
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d2105 or
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d2106 or
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d2107)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_523_99_entry_1__ETC___d2109 =
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d2104;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_523_99_entry_1__ETC___d2109 =
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d2105;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_523_99_entry_1__ETC___d2109 =
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d2106;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_523_99_entry_1__ETC___d2109 =
|
|
SEL_ARR_entry_0_rl_BIT_571_41_entry_1_rl_2_BIT_ETC___d2107;
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d2124 =
|
|
entry_0_rl[520];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d2124 =
|
|
entry_1_rl[520];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d2124 =
|
|
entry_2_rl[520];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d2124 =
|
|
entry_3_rl[520];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d2125 =
|
|
entry_0_rl[536];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d2125 =
|
|
entry_1_rl[536];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d2125 =
|
|
entry_2_rl[536];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d2125 =
|
|
entry_3_rl[536];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d2126 =
|
|
entry_0_rl[552];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d2126 =
|
|
entry_1_rl[552];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d2126 =
|
|
entry_2_rl[552];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d2126 =
|
|
entry_3_rl[552];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d2127 =
|
|
entry_0_rl[568];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d2127 =
|
|
entry_1_rl[568];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d2127 =
|
|
entry_2_rl[568];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d2127 =
|
|
entry_3_rl[568];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d2130 =
|
|
entry_0_rl[519];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d2130 =
|
|
entry_1_rl[519];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d2130 =
|
|
entry_2_rl[519];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d2130 =
|
|
entry_3_rl[519];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d2131 =
|
|
entry_0_rl[535];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d2131 =
|
|
entry_1_rl[535];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d2131 =
|
|
entry_2_rl[535];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d2131 =
|
|
entry_3_rl[535];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d2132 =
|
|
entry_0_rl[551];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d2132 =
|
|
entry_1_rl[551];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d2132 =
|
|
entry_2_rl[551];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d2132 =
|
|
entry_3_rl[551];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d2133 =
|
|
entry_0_rl[567];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d2133 =
|
|
entry_1_rl[567];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d2133 =
|
|
entry_2_rl[567];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d2133 =
|
|
entry_3_rl[567];
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d2111 or
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d2112 or
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d2113 or
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d2114)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_522_58_entry_1__ETC___d2116 =
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d2111;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_522_58_entry_1__ETC___d2116 =
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d2112;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_522_58_entry_1__ETC___d2116 =
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d2113;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_522_58_entry_1__ETC___d2116 =
|
|
SEL_ARR_entry_0_rl_BIT_570_00_entry_1_rl_2_BIT_ETC___d2114;
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d2117 or
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d2118 or
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d2119 or
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d2120)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_521_16_entry_1__ETC___d2122 =
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d2117;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_521_16_entry_1__ETC___d2122 =
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d2118;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_521_16_entry_1__ETC___d2122 =
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d2119;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_521_16_entry_1__ETC___d2122 =
|
|
SEL_ARR_entry_0_rl_BIT_569_58_entry_1_rl_2_BIT_ETC___d2120;
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d2137 =
|
|
entry_0_rl[518];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d2137 =
|
|
entry_1_rl[518];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d2137 =
|
|
entry_2_rl[518];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d2137 =
|
|
entry_3_rl[518];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d2138 =
|
|
entry_0_rl[534];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d2138 =
|
|
entry_1_rl[534];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d2138 =
|
|
entry_2_rl[534];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d2138 =
|
|
entry_3_rl[534];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d2139 =
|
|
entry_0_rl[550];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d2139 =
|
|
entry_1_rl[550];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d2139 =
|
|
entry_2_rl[550];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d2139 =
|
|
entry_3_rl[550];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d2140 =
|
|
entry_0_rl[566];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d2140 =
|
|
entry_1_rl[566];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d2140 =
|
|
entry_2_rl[566];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d2140 =
|
|
entry_3_rl[566];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d2143 =
|
|
entry_0_rl[517];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d2143 =
|
|
entry_1_rl[517];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d2143 =
|
|
entry_2_rl[517];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d2143 =
|
|
entry_3_rl[517];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d2144 =
|
|
entry_0_rl[533];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d2144 =
|
|
entry_1_rl[533];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d2144 =
|
|
entry_2_rl[533];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d2144 =
|
|
entry_3_rl[533];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d2145 =
|
|
entry_0_rl[549];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d2145 =
|
|
entry_1_rl[549];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d2145 =
|
|
entry_2_rl[549];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d2145 =
|
|
entry_3_rl[549];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d2146 =
|
|
entry_0_rl[565];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d2146 =
|
|
entry_1_rl[565];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d2146 =
|
|
entry_2_rl[565];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d2146 =
|
|
entry_3_rl[565];
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d2124 or
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d2125 or
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d2126 or
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d2127)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_520_75_entry_1__ETC___d2129 =
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d2124;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_520_75_entry_1__ETC___d2129 =
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d2125;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_520_75_entry_1__ETC___d2129 =
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d2126;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_520_75_entry_1__ETC___d2129 =
|
|
SEL_ARR_entry_0_rl_BIT_568_17_entry_1_rl_2_BIT_ETC___d2127;
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d2130 or
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d2131 or
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d2132 or
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d2133)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_519_33_entry_1__ETC___d2135 =
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d2130;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_519_33_entry_1__ETC___d2135 =
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d2131;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_519_33_entry_1__ETC___d2135 =
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d2132;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_519_33_entry_1__ETC___d2135 =
|
|
SEL_ARR_entry_0_rl_BIT_567_75_entry_1_rl_2_BIT_ETC___d2133;
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d2137 or
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d2138 or
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d2139 or
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d2140)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_518_92_entry_1__ETC___d2142 =
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d2137;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_518_92_entry_1__ETC___d2142 =
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d2138;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_518_92_entry_1__ETC___d2142 =
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d2139;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_518_92_entry_1__ETC___d2142 =
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d2140;
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d2143 or
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d2144 or
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d2145 or
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d2146)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_517_50_entry_1__ETC___d2148 =
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d2143;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_517_50_entry_1__ETC___d2148 =
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d2144;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_517_50_entry_1__ETC___d2148 =
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d2145;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_517_50_entry_1__ETC___d2148 =
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d2146;
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d2151 =
|
|
entry_0_rl[516];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d2151 =
|
|
entry_1_rl[516];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d2151 =
|
|
entry_2_rl[516];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d2151 =
|
|
entry_3_rl[516];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d2152 =
|
|
entry_0_rl[532];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d2152 =
|
|
entry_1_rl[532];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d2152 =
|
|
entry_2_rl[532];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d2152 =
|
|
entry_3_rl[532];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d2153 =
|
|
entry_0_rl[548];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d2153 =
|
|
entry_1_rl[548];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d2153 =
|
|
entry_2_rl[548];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d2153 =
|
|
entry_3_rl[548];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d2154 =
|
|
entry_0_rl[564];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d2154 =
|
|
entry_1_rl[564];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d2154 =
|
|
entry_2_rl[564];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d2154 =
|
|
entry_3_rl[564];
|
|
endcase
|
|
end
|
|
always@(search_paddr or
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d2151 or
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d2152 or
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d2153 or
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d2154)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_516_011_entry_1_ETC___d2156 =
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d2151;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_516_011_entry_1_ETC___d2156 =
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d2152;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_516_011_entry_1_ETC___d2156 =
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d2153;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_516_011_entry_1_ETC___d2156 =
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d2154;
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q73 =
|
|
entry_0_rl[531];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q73 =
|
|
entry_0_rl[547];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q73 =
|
|
entry_0_rl[563];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q73 =
|
|
entry_0_rl[579];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q74 =
|
|
entry_0_rl[530];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q74 =
|
|
entry_0_rl[546];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q74 =
|
|
entry_0_rl[562];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q74 =
|
|
entry_0_rl[578];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q75 =
|
|
entry_0_rl[529];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q75 =
|
|
entry_0_rl[545];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q75 =
|
|
entry_0_rl[561];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q75 =
|
|
entry_0_rl[577];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q76 =
|
|
entry_0_rl[528];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q76 =
|
|
entry_0_rl[544];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q76 =
|
|
entry_0_rl[560];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q76 =
|
|
entry_0_rl[576];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q77 =
|
|
entry_0_rl[527];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q77 =
|
|
entry_0_rl[543];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q77 =
|
|
entry_0_rl[559];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q77 =
|
|
entry_0_rl[575];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q78 =
|
|
entry_0_rl[526];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q78 =
|
|
entry_0_rl[542];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q78 =
|
|
entry_0_rl[558];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q78 =
|
|
entry_0_rl[574];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q79 =
|
|
entry_0_rl[525];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q79 =
|
|
entry_0_rl[541];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q79 =
|
|
entry_0_rl[557];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q79 =
|
|
entry_0_rl[573];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q80 =
|
|
entry_0_rl[524];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q80 =
|
|
entry_0_rl[540];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q80 =
|
|
entry_0_rl[556];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q80 =
|
|
entry_0_rl[572];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q81 =
|
|
entry_0_rl[523];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q81 =
|
|
entry_0_rl[539];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q81 =
|
|
entry_0_rl[555];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q81 =
|
|
entry_0_rl[571];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q82 =
|
|
entry_0_rl[522];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q82 =
|
|
entry_0_rl[538];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q82 =
|
|
entry_0_rl[554];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q82 =
|
|
entry_0_rl[570];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q83 =
|
|
entry_0_rl[521];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q83 =
|
|
entry_0_rl[537];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q83 =
|
|
entry_0_rl[553];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q83 =
|
|
entry_0_rl[569];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q84 =
|
|
entry_0_rl[520];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q84 =
|
|
entry_0_rl[536];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q84 =
|
|
entry_0_rl[552];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q84 =
|
|
entry_0_rl[568];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q85 =
|
|
entry_0_rl[519];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q85 =
|
|
entry_0_rl[535];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q85 =
|
|
entry_0_rl[551];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q85 =
|
|
entry_0_rl[567];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q86 =
|
|
entry_0_rl[518];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q86 =
|
|
entry_0_rl[534];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q86 =
|
|
entry_0_rl[550];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q86 =
|
|
entry_0_rl[566];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q87 =
|
|
entry_0_rl[517];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q87 =
|
|
entry_0_rl[533];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q87 =
|
|
entry_0_rl[549];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q87 =
|
|
entry_0_rl[565];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q88 =
|
|
entry_0_rl[516];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q88 =
|
|
entry_0_rl[532];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q88 =
|
|
entry_0_rl[548];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q88 =
|
|
entry_0_rl[564];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q89 =
|
|
entry_1_rl[531];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q89 =
|
|
entry_1_rl[547];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q89 =
|
|
entry_1_rl[563];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q89 =
|
|
entry_1_rl[579];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q90 =
|
|
entry_1_rl[530];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q90 =
|
|
entry_1_rl[546];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q90 =
|
|
entry_1_rl[562];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q90 =
|
|
entry_1_rl[578];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q91 =
|
|
entry_1_rl[529];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q91 =
|
|
entry_1_rl[545];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q91 =
|
|
entry_1_rl[561];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q91 =
|
|
entry_1_rl[577];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q92 =
|
|
entry_1_rl[528];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q92 =
|
|
entry_1_rl[544];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q92 =
|
|
entry_1_rl[560];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q92 =
|
|
entry_1_rl[576];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q93 =
|
|
entry_1_rl[527];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q93 =
|
|
entry_1_rl[543];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q93 =
|
|
entry_1_rl[559];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q93 =
|
|
entry_1_rl[575];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q94 =
|
|
entry_1_rl[526];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q94 =
|
|
entry_1_rl[542];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q94 =
|
|
entry_1_rl[558];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q94 =
|
|
entry_1_rl[574];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q95 =
|
|
entry_1_rl[525];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q95 =
|
|
entry_1_rl[541];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q95 =
|
|
entry_1_rl[557];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q95 =
|
|
entry_1_rl[573];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q96 =
|
|
entry_1_rl[524];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q96 =
|
|
entry_1_rl[540];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q96 =
|
|
entry_1_rl[556];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q96 =
|
|
entry_1_rl[572];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q97 =
|
|
entry_1_rl[523];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q97 =
|
|
entry_1_rl[539];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q97 =
|
|
entry_1_rl[555];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q97 =
|
|
entry_1_rl[571];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q98 =
|
|
entry_1_rl[522];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q98 =
|
|
entry_1_rl[538];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q98 =
|
|
entry_1_rl[554];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q98 =
|
|
entry_1_rl[570];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q99 =
|
|
entry_1_rl[521];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q99 =
|
|
entry_1_rl[537];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q99 =
|
|
entry_1_rl[553];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q99 =
|
|
entry_1_rl[569];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q100 =
|
|
entry_1_rl[520];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q100 =
|
|
entry_1_rl[536];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q100 =
|
|
entry_1_rl[552];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q100 =
|
|
entry_1_rl[568];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q101 =
|
|
entry_1_rl[519];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q101 =
|
|
entry_1_rl[535];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q101 =
|
|
entry_1_rl[551];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q101 =
|
|
entry_1_rl[567];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q102 =
|
|
entry_1_rl[518];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q102 =
|
|
entry_1_rl[534];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q102 =
|
|
entry_1_rl[550];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q102 =
|
|
entry_1_rl[566];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q103 =
|
|
entry_1_rl[517];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q103 =
|
|
entry_1_rl[533];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q103 =
|
|
entry_1_rl[549];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q103 =
|
|
entry_1_rl[565];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q104 =
|
|
entry_1_rl[516];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q104 =
|
|
entry_1_rl[532];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q104 =
|
|
entry_1_rl[548];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q104 =
|
|
entry_1_rl[564];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q105 =
|
|
entry_2_rl[531];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q105 =
|
|
entry_2_rl[547];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q105 =
|
|
entry_2_rl[563];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q105 =
|
|
entry_2_rl[579];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q106 =
|
|
entry_2_rl[530];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q106 =
|
|
entry_2_rl[546];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q106 =
|
|
entry_2_rl[562];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q106 =
|
|
entry_2_rl[578];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q107 =
|
|
entry_2_rl[529];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q107 =
|
|
entry_2_rl[545];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q107 =
|
|
entry_2_rl[561];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q107 =
|
|
entry_2_rl[577];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q108 =
|
|
entry_2_rl[528];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q108 =
|
|
entry_2_rl[544];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q108 =
|
|
entry_2_rl[560];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q108 =
|
|
entry_2_rl[576];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q109 =
|
|
entry_2_rl[527];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q109 =
|
|
entry_2_rl[543];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q109 =
|
|
entry_2_rl[559];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q109 =
|
|
entry_2_rl[575];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q110 =
|
|
entry_2_rl[526];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q110 =
|
|
entry_2_rl[542];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q110 =
|
|
entry_2_rl[558];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q110 =
|
|
entry_2_rl[574];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q111 =
|
|
entry_2_rl[525];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q111 =
|
|
entry_2_rl[541];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q111 =
|
|
entry_2_rl[557];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q111 =
|
|
entry_2_rl[573];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q112 =
|
|
entry_2_rl[524];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q112 =
|
|
entry_2_rl[540];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q112 =
|
|
entry_2_rl[556];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q112 =
|
|
entry_2_rl[572];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q113 =
|
|
entry_2_rl[523];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q113 =
|
|
entry_2_rl[539];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q113 =
|
|
entry_2_rl[555];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q113 =
|
|
entry_2_rl[571];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q114 =
|
|
entry_2_rl[522];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q114 =
|
|
entry_2_rl[538];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q114 =
|
|
entry_2_rl[554];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q114 =
|
|
entry_2_rl[570];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q115 =
|
|
entry_2_rl[521];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q115 =
|
|
entry_2_rl[537];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q115 =
|
|
entry_2_rl[553];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q115 =
|
|
entry_2_rl[569];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q116 =
|
|
entry_2_rl[520];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q116 =
|
|
entry_2_rl[536];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q116 =
|
|
entry_2_rl[552];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q116 =
|
|
entry_2_rl[568];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q117 =
|
|
entry_2_rl[519];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q117 =
|
|
entry_2_rl[535];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q117 =
|
|
entry_2_rl[551];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q117 =
|
|
entry_2_rl[567];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q118 =
|
|
entry_2_rl[518];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q118 =
|
|
entry_2_rl[534];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q118 =
|
|
entry_2_rl[550];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q118 =
|
|
entry_2_rl[566];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q119 =
|
|
entry_2_rl[517];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q119 =
|
|
entry_2_rl[533];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q119 =
|
|
entry_2_rl[549];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q119 =
|
|
entry_2_rl[565];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q120 =
|
|
entry_2_rl[516];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q120 =
|
|
entry_2_rl[532];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q120 =
|
|
entry_2_rl[548];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q120 =
|
|
entry_2_rl[564];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q121 =
|
|
entry_3_rl[531];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q121 =
|
|
entry_3_rl[547];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q121 =
|
|
entry_3_rl[563];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q121 =
|
|
entry_3_rl[579];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q122 =
|
|
entry_3_rl[530];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q122 =
|
|
entry_3_rl[546];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q122 =
|
|
entry_3_rl[562];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q122 =
|
|
entry_3_rl[578];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q123 =
|
|
entry_3_rl[529];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q123 =
|
|
entry_3_rl[545];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q123 =
|
|
entry_3_rl[561];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q123 =
|
|
entry_3_rl[577];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q124 =
|
|
entry_3_rl[528];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q124 =
|
|
entry_3_rl[544];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q124 =
|
|
entry_3_rl[560];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q124 =
|
|
entry_3_rl[576];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q125 =
|
|
entry_3_rl[527];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q125 =
|
|
entry_3_rl[543];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q125 =
|
|
entry_3_rl[559];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q125 =
|
|
entry_3_rl[575];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q126 =
|
|
entry_3_rl[526];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q126 =
|
|
entry_3_rl[542];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q126 =
|
|
entry_3_rl[558];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q126 =
|
|
entry_3_rl[574];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q127 =
|
|
entry_3_rl[525];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q127 =
|
|
entry_3_rl[541];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q127 =
|
|
entry_3_rl[557];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q127 =
|
|
entry_3_rl[573];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q128 =
|
|
entry_3_rl[524];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q128 =
|
|
entry_3_rl[540];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q128 =
|
|
entry_3_rl[556];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q128 =
|
|
entry_3_rl[572];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q129 =
|
|
entry_3_rl[523];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q129 =
|
|
entry_3_rl[539];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q129 =
|
|
entry_3_rl[555];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q129 =
|
|
entry_3_rl[571];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q130 =
|
|
entry_3_rl[522];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q130 =
|
|
entry_3_rl[538];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q130 =
|
|
entry_3_rl[554];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q130 =
|
|
entry_3_rl[570];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q131 =
|
|
entry_3_rl[521];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q131 =
|
|
entry_3_rl[537];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q131 =
|
|
entry_3_rl[553];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q131 =
|
|
entry_3_rl[569];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q132 =
|
|
entry_3_rl[520];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q132 =
|
|
entry_3_rl[536];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q132 =
|
|
entry_3_rl[552];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q132 =
|
|
entry_3_rl[568];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q133 =
|
|
entry_3_rl[519];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q133 =
|
|
entry_3_rl[535];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q133 =
|
|
entry_3_rl[551];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q133 =
|
|
entry_3_rl[567];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q134 =
|
|
entry_3_rl[518];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q134 =
|
|
entry_3_rl[534];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q134 =
|
|
entry_3_rl[550];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q134 =
|
|
entry_3_rl[566];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q135 =
|
|
entry_3_rl[517];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q135 =
|
|
entry_3_rl[533];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q135 =
|
|
entry_3_rl[549];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q135 =
|
|
entry_3_rl[565];
|
|
endcase
|
|
end
|
|
always@(noMatchLdQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchLdQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q136 =
|
|
entry_3_rl[516];
|
|
2'd1:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q136 =
|
|
entry_3_rl[532];
|
|
2'd2:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q136 =
|
|
entry_3_rl[548];
|
|
2'd3:
|
|
CASE_noMatchLdQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q136 =
|
|
entry_3_rl[564];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q137 =
|
|
entry_0_rl[531];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q137 =
|
|
entry_0_rl[547];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q137 =
|
|
entry_0_rl[563];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q137 =
|
|
entry_0_rl[579];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q138 =
|
|
entry_0_rl[530];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q138 =
|
|
entry_0_rl[546];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q138 =
|
|
entry_0_rl[562];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q138 =
|
|
entry_0_rl[578];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q139 =
|
|
entry_0_rl[529];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q139 =
|
|
entry_0_rl[545];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q139 =
|
|
entry_0_rl[561];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q139 =
|
|
entry_0_rl[577];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q140 =
|
|
entry_0_rl[528];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q140 =
|
|
entry_0_rl[544];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q140 =
|
|
entry_0_rl[560];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q140 =
|
|
entry_0_rl[576];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q141 =
|
|
entry_0_rl[527];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q141 =
|
|
entry_0_rl[543];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q141 =
|
|
entry_0_rl[559];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q141 =
|
|
entry_0_rl[575];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q142 =
|
|
entry_0_rl[526];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q142 =
|
|
entry_0_rl[542];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q142 =
|
|
entry_0_rl[558];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q142 =
|
|
entry_0_rl[574];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q143 =
|
|
entry_0_rl[525];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q143 =
|
|
entry_0_rl[541];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q143 =
|
|
entry_0_rl[557];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q143 =
|
|
entry_0_rl[573];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q144 =
|
|
entry_0_rl[524];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q144 =
|
|
entry_0_rl[540];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q144 =
|
|
entry_0_rl[556];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q144 =
|
|
entry_0_rl[572];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q145 =
|
|
entry_0_rl[523];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q145 =
|
|
entry_0_rl[539];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q145 =
|
|
entry_0_rl[555];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q145 =
|
|
entry_0_rl[571];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q146 =
|
|
entry_0_rl[522];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q146 =
|
|
entry_0_rl[538];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q146 =
|
|
entry_0_rl[554];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q146 =
|
|
entry_0_rl[570];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q147 =
|
|
entry_0_rl[521];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q147 =
|
|
entry_0_rl[537];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q147 =
|
|
entry_0_rl[553];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q147 =
|
|
entry_0_rl[569];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q148 =
|
|
entry_0_rl[520];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q148 =
|
|
entry_0_rl[536];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q148 =
|
|
entry_0_rl[552];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q148 =
|
|
entry_0_rl[568];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q149 =
|
|
entry_0_rl[519];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q149 =
|
|
entry_0_rl[535];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q149 =
|
|
entry_0_rl[551];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q149 =
|
|
entry_0_rl[567];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q150 =
|
|
entry_0_rl[518];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q150 =
|
|
entry_0_rl[534];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q150 =
|
|
entry_0_rl[550];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q150 =
|
|
entry_0_rl[566];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q151 =
|
|
entry_0_rl[517];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q151 =
|
|
entry_0_rl[533];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q151 =
|
|
entry_0_rl[549];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q151 =
|
|
entry_0_rl[565];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_0_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q152 =
|
|
entry_0_rl[516];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q152 =
|
|
entry_0_rl[532];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q152 =
|
|
entry_0_rl[548];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_0_rl_ETC__q152 =
|
|
entry_0_rl[564];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q153 =
|
|
entry_1_rl[531];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q153 =
|
|
entry_1_rl[547];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q153 =
|
|
entry_1_rl[563];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q153 =
|
|
entry_1_rl[579];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q154 =
|
|
entry_1_rl[530];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q154 =
|
|
entry_1_rl[546];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q154 =
|
|
entry_1_rl[562];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q154 =
|
|
entry_1_rl[578];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q155 =
|
|
entry_1_rl[529];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q155 =
|
|
entry_1_rl[545];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q155 =
|
|
entry_1_rl[561];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q155 =
|
|
entry_1_rl[577];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q156 =
|
|
entry_1_rl[528];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q156 =
|
|
entry_1_rl[544];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q156 =
|
|
entry_1_rl[560];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q156 =
|
|
entry_1_rl[576];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q157 =
|
|
entry_1_rl[527];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q157 =
|
|
entry_1_rl[543];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q157 =
|
|
entry_1_rl[559];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q157 =
|
|
entry_1_rl[575];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q158 =
|
|
entry_1_rl[526];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q158 =
|
|
entry_1_rl[542];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q158 =
|
|
entry_1_rl[558];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q158 =
|
|
entry_1_rl[574];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q159 =
|
|
entry_1_rl[525];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q159 =
|
|
entry_1_rl[541];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q159 =
|
|
entry_1_rl[557];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q159 =
|
|
entry_1_rl[573];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q160 =
|
|
entry_1_rl[524];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q160 =
|
|
entry_1_rl[540];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q160 =
|
|
entry_1_rl[556];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q160 =
|
|
entry_1_rl[572];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q161 =
|
|
entry_1_rl[523];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q161 =
|
|
entry_1_rl[539];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q161 =
|
|
entry_1_rl[555];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q161 =
|
|
entry_1_rl[571];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q162 =
|
|
entry_1_rl[522];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q162 =
|
|
entry_1_rl[538];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q162 =
|
|
entry_1_rl[554];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q162 =
|
|
entry_1_rl[570];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q163 =
|
|
entry_1_rl[521];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q163 =
|
|
entry_1_rl[537];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q163 =
|
|
entry_1_rl[553];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q163 =
|
|
entry_1_rl[569];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q164 =
|
|
entry_1_rl[520];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q164 =
|
|
entry_1_rl[536];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q164 =
|
|
entry_1_rl[552];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q164 =
|
|
entry_1_rl[568];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q165 =
|
|
entry_1_rl[519];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q165 =
|
|
entry_1_rl[535];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q165 =
|
|
entry_1_rl[551];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q165 =
|
|
entry_1_rl[567];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q166 =
|
|
entry_1_rl[518];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q166 =
|
|
entry_1_rl[534];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q166 =
|
|
entry_1_rl[550];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q166 =
|
|
entry_1_rl[566];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q167 =
|
|
entry_1_rl[517];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q167 =
|
|
entry_1_rl[533];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q167 =
|
|
entry_1_rl[549];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q167 =
|
|
entry_1_rl[565];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_1_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q168 =
|
|
entry_1_rl[516];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q168 =
|
|
entry_1_rl[532];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q168 =
|
|
entry_1_rl[548];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_1_rl_ETC__q168 =
|
|
entry_1_rl[564];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q169 =
|
|
entry_3_rl[531];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q169 =
|
|
entry_3_rl[547];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q169 =
|
|
entry_3_rl[563];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q169 =
|
|
entry_3_rl[579];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q170 =
|
|
entry_3_rl[530];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q170 =
|
|
entry_3_rl[546];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q170 =
|
|
entry_3_rl[562];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q170 =
|
|
entry_3_rl[578];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q171 =
|
|
entry_3_rl[529];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q171 =
|
|
entry_3_rl[545];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q171 =
|
|
entry_3_rl[561];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q171 =
|
|
entry_3_rl[577];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q172 =
|
|
entry_3_rl[528];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q172 =
|
|
entry_3_rl[544];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q172 =
|
|
entry_3_rl[560];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q172 =
|
|
entry_3_rl[576];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q173 =
|
|
entry_3_rl[527];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q173 =
|
|
entry_3_rl[543];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q173 =
|
|
entry_3_rl[559];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q173 =
|
|
entry_3_rl[575];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q174 =
|
|
entry_3_rl[526];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q174 =
|
|
entry_3_rl[542];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q174 =
|
|
entry_3_rl[558];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q174 =
|
|
entry_3_rl[574];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q175 =
|
|
entry_3_rl[525];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q175 =
|
|
entry_3_rl[541];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q175 =
|
|
entry_3_rl[557];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q175 =
|
|
entry_3_rl[573];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q176 =
|
|
entry_3_rl[524];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q176 =
|
|
entry_3_rl[540];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q176 =
|
|
entry_3_rl[556];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q176 =
|
|
entry_3_rl[572];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q177 =
|
|
entry_3_rl[523];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q177 =
|
|
entry_3_rl[539];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q177 =
|
|
entry_3_rl[555];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q177 =
|
|
entry_3_rl[571];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q178 =
|
|
entry_3_rl[522];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q178 =
|
|
entry_3_rl[538];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q178 =
|
|
entry_3_rl[554];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q178 =
|
|
entry_3_rl[570];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q179 =
|
|
entry_3_rl[521];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q179 =
|
|
entry_3_rl[537];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q179 =
|
|
entry_3_rl[553];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q179 =
|
|
entry_3_rl[569];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q180 =
|
|
entry_3_rl[520];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q180 =
|
|
entry_3_rl[536];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q180 =
|
|
entry_3_rl[552];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q180 =
|
|
entry_3_rl[568];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q181 =
|
|
entry_3_rl[519];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q181 =
|
|
entry_3_rl[535];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q181 =
|
|
entry_3_rl[551];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q181 =
|
|
entry_3_rl[567];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q182 =
|
|
entry_3_rl[518];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q182 =
|
|
entry_3_rl[534];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q182 =
|
|
entry_3_rl[550];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q182 =
|
|
entry_3_rl[566];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q183 =
|
|
entry_3_rl[517];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q183 =
|
|
entry_3_rl[533];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q183 =
|
|
entry_3_rl[549];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q183 =
|
|
entry_3_rl[565];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q184 =
|
|
entry_2_rl[531];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q184 =
|
|
entry_2_rl[547];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q184 =
|
|
entry_2_rl[563];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q184 =
|
|
entry_2_rl[579];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q185 =
|
|
entry_2_rl[530];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q185 =
|
|
entry_2_rl[546];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q185 =
|
|
entry_2_rl[562];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q185 =
|
|
entry_2_rl[578];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q186 =
|
|
entry_2_rl[529];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q186 =
|
|
entry_2_rl[545];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q186 =
|
|
entry_2_rl[561];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q186 =
|
|
entry_2_rl[577];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q187 =
|
|
entry_2_rl[528];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q187 =
|
|
entry_2_rl[544];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q187 =
|
|
entry_2_rl[560];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q187 =
|
|
entry_2_rl[576];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q188 =
|
|
entry_2_rl[527];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q188 =
|
|
entry_2_rl[543];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q188 =
|
|
entry_2_rl[559];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q188 =
|
|
entry_2_rl[575];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q189 =
|
|
entry_2_rl[526];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q189 =
|
|
entry_2_rl[542];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q189 =
|
|
entry_2_rl[558];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q189 =
|
|
entry_2_rl[574];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q190 =
|
|
entry_2_rl[525];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q190 =
|
|
entry_2_rl[541];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q190 =
|
|
entry_2_rl[557];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q190 =
|
|
entry_2_rl[573];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q191 =
|
|
entry_2_rl[524];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q191 =
|
|
entry_2_rl[540];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q191 =
|
|
entry_2_rl[556];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q191 =
|
|
entry_2_rl[572];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q192 =
|
|
entry_2_rl[523];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q192 =
|
|
entry_2_rl[539];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q192 =
|
|
entry_2_rl[555];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q192 =
|
|
entry_2_rl[571];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q193 =
|
|
entry_2_rl[522];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q193 =
|
|
entry_2_rl[538];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q193 =
|
|
entry_2_rl[554];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q193 =
|
|
entry_2_rl[570];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q194 =
|
|
entry_2_rl[521];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q194 =
|
|
entry_2_rl[537];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q194 =
|
|
entry_2_rl[553];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q194 =
|
|
entry_2_rl[569];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q195 =
|
|
entry_2_rl[520];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q195 =
|
|
entry_2_rl[536];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q195 =
|
|
entry_2_rl[552];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q195 =
|
|
entry_2_rl[568];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q196 =
|
|
entry_2_rl[519];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q196 =
|
|
entry_2_rl[535];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q196 =
|
|
entry_2_rl[551];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q196 =
|
|
entry_2_rl[567];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q197 =
|
|
entry_2_rl[518];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q197 =
|
|
entry_2_rl[534];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q197 =
|
|
entry_2_rl[550];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q197 =
|
|
entry_2_rl[566];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q198 =
|
|
entry_2_rl[517];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q198 =
|
|
entry_2_rl[533];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q198 =
|
|
entry_2_rl[549];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q198 =
|
|
entry_2_rl[565];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_2_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q199 =
|
|
entry_2_rl[516];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q199 =
|
|
entry_2_rl[532];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q199 =
|
|
entry_2_rl[548];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_2_rl_ETC__q199 =
|
|
entry_2_rl[564];
|
|
endcase
|
|
end
|
|
always@(noMatchStQ_paddr or entry_3_rl)
|
|
begin
|
|
case (noMatchStQ_paddr[5:4])
|
|
2'd0:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q200 =
|
|
entry_3_rl[516];
|
|
2'd1:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q200 =
|
|
entry_3_rl[532];
|
|
2'd2:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q200 =
|
|
entry_3_rl[548];
|
|
2'd3:
|
|
CASE_noMatchStQ_paddr_BITS_5_TO_4_0_entry_3_rl_ETC__q200 =
|
|
entry_3_rl[564];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158 =
|
|
entry_0_rl[513];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158 =
|
|
entry_1_rl[513];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158 =
|
|
entry_2_rl[513];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158 =
|
|
entry_3_rl[513];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173 =
|
|
entry_0_rl[512];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173 =
|
|
entry_1_rl[512];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173 =
|
|
entry_2_rl[512];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173 =
|
|
entry_3_rl[512];
|
|
endcase
|
|
end
|
|
always@(enq_be or
|
|
enq_paddr or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158 or
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173 or
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_enq_d_ETC___d1175)
|
|
begin
|
|
case (enq_be)
|
|
16'd0:
|
|
IF_enq_be_EQ_65535_112_THEN_IF_enq_paddr_BITS__ETC___d1190 =
|
|
{ SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158,
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173 };
|
|
16'd65535:
|
|
IF_enq_be_EQ_65535_112_THEN_IF_enq_paddr_BITS__ETC___d1190 =
|
|
IF_enq_paddr_BITS_5_TO_4_29_EQ_3_30_THEN_enq_d_ETC___d1175;
|
|
default: IF_enq_be_EQ_65535_112_THEN_IF_enq_paddr_BITS__ETC___d1190 =
|
|
{ enq_paddr[5:4] != 2'd3 &&
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1127,
|
|
enq_paddr[5:4] != 2'd2 &&
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1142,
|
|
enq_paddr[5:4] != 2'd1 &&
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1158,
|
|
enq_paddr[5:4] != 2'd0 &&
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1173 };
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1386 =
|
|
entry_0_rl[319:256];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1386 =
|
|
entry_1_rl[319:256];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1386 =
|
|
entry_2_rl[319:256];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1386 =
|
|
entry_3_rl[319:256];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1392 =
|
|
entry_0_rl[191:128];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1392 =
|
|
entry_1_rl[191:128];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1392 =
|
|
entry_2_rl[191:128];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1392 =
|
|
entry_3_rl[191:128];
|
|
endcase
|
|
end
|
|
always@(enq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1399 =
|
|
entry_0_rl[63:0];
|
|
2'd1:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1399 =
|
|
entry_1_rl[63:0];
|
|
2'd2:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1399 =
|
|
entry_2_rl[63:0];
|
|
2'd3:
|
|
SEL_ARR_IF_entry_0_lat_0_whas_THEN_entry_0_lat_ETC___d1399 =
|
|
entry_3_rl[63:0];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1824 =
|
|
entry_0_rl[513];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1824 =
|
|
entry_1_rl[513];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1824 =
|
|
entry_2_rl[513];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_513_146_entry_1_rl_2_BI_ETC___d1824 =
|
|
entry_3_rl[513];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1825 =
|
|
entry_0_rl[512];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1825 =
|
|
entry_1_rl[512];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1825 =
|
|
entry_2_rl[512];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1825 =
|
|
entry_3_rl[512];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1745 =
|
|
entry_0_rl[566];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1745 =
|
|
entry_1_rl[566];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1745 =
|
|
entry_2_rl[566];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_566_34_entry_1_rl_2_BIT_ETC___d1745 =
|
|
entry_3_rl[566];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1746 =
|
|
entry_0_rl[565];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1746 =
|
|
entry_1_rl[565];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1746 =
|
|
entry_2_rl[565];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_565_92_entry_1_rl_2_BIT_ETC___d1746 =
|
|
entry_3_rl[565];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1748 =
|
|
entry_0_rl[564];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1748 =
|
|
entry_1_rl[564];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1748 =
|
|
entry_2_rl[564];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_564_053_entry_1_rl_2_BI_ETC___d1748 =
|
|
entry_3_rl[564];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1749 =
|
|
entry_0_rl[563];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1749 =
|
|
entry_1_rl[563];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1749 =
|
|
entry_2_rl[563];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_563_60_entry_1_rl_2_BIT_ETC___d1749 =
|
|
entry_3_rl[563];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1751 =
|
|
entry_0_rl[562];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1751 =
|
|
entry_1_rl[562];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1751 =
|
|
entry_2_rl[562];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_562_18_entry_1_rl_2_BIT_ETC___d1751 =
|
|
entry_3_rl[562];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1752 =
|
|
entry_0_rl[561];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1752 =
|
|
entry_1_rl[561];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1752 =
|
|
entry_2_rl[561];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_561_76_entry_1_rl_2_BIT_ETC___d1752 =
|
|
entry_3_rl[561];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1754 =
|
|
entry_0_rl[560];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1754 =
|
|
entry_1_rl[560];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1754 =
|
|
entry_2_rl[560];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_560_35_entry_1_rl_2_BIT_ETC___d1754 =
|
|
entry_3_rl[560];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1755 =
|
|
entry_0_rl[559];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1755 =
|
|
entry_1_rl[559];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1755 =
|
|
entry_2_rl[559];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_559_93_entry_1_rl_2_BIT_ETC___d1755 =
|
|
entry_3_rl[559];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1757 =
|
|
entry_0_rl[558];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1757 =
|
|
entry_1_rl[558];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1757 =
|
|
entry_2_rl[558];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_558_52_entry_1_rl_2_BIT_ETC___d1757 =
|
|
entry_3_rl[558];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1758 =
|
|
entry_0_rl[557];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1758 =
|
|
entry_1_rl[557];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1758 =
|
|
entry_2_rl[557];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_557_10_entry_1_rl_2_BIT_ETC___d1758 =
|
|
entry_3_rl[557];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1760 =
|
|
entry_0_rl[556];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1760 =
|
|
entry_1_rl[556];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1760 =
|
|
entry_2_rl[556];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_556_69_entry_1_rl_2_BIT_ETC___d1760 =
|
|
entry_3_rl[556];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1761 =
|
|
entry_0_rl[555];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1761 =
|
|
entry_1_rl[555];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1761 =
|
|
entry_2_rl[555];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_555_27_entry_1_rl_2_BIT_ETC___d1761 =
|
|
entry_3_rl[555];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1763 =
|
|
entry_0_rl[554];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1763 =
|
|
entry_1_rl[554];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1763 =
|
|
entry_2_rl[554];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_554_86_entry_1_rl_2_BIT_ETC___d1763 =
|
|
entry_3_rl[554];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1764 =
|
|
entry_0_rl[553];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1764 =
|
|
entry_1_rl[553];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1764 =
|
|
entry_2_rl[553];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_553_44_entry_1_rl_2_BIT_ETC___d1764 =
|
|
entry_3_rl[553];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1766 =
|
|
entry_0_rl[552];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1766 =
|
|
entry_1_rl[552];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1766 =
|
|
entry_2_rl[552];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_552_03_entry_1_rl_2_BIT_ETC___d1766 =
|
|
entry_3_rl[552];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1767 =
|
|
entry_0_rl[551];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1767 =
|
|
entry_1_rl[551];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1767 =
|
|
entry_2_rl[551];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_551_61_entry_1_rl_2_BIT_ETC___d1767 =
|
|
entry_3_rl[551];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1769 =
|
|
entry_0_rl[550];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1769 =
|
|
entry_1_rl[550];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1769 =
|
|
entry_2_rl[550];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_550_20_entry_1_rl_2_BIT_ETC___d1769 =
|
|
entry_3_rl[550];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1770 =
|
|
entry_0_rl[549];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1770 =
|
|
entry_1_rl[549];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1770 =
|
|
entry_2_rl[549];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_549_78_entry_1_rl_2_BIT_ETC___d1770 =
|
|
entry_3_rl[549];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1772 =
|
|
entry_0_rl[548];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1772 =
|
|
entry_1_rl[548];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1772 =
|
|
entry_2_rl[548];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_548_039_entry_1_rl_2_BI_ETC___d1772 =
|
|
entry_3_rl[548];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1773 =
|
|
entry_0_rl[547];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1773 =
|
|
entry_1_rl[547];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1773 =
|
|
entry_2_rl[547];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_547_46_entry_1_rl_2_BIT_ETC___d1773 =
|
|
entry_3_rl[547];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1775 =
|
|
entry_0_rl[546];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1775 =
|
|
entry_1_rl[546];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1775 =
|
|
entry_2_rl[546];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_546_04_entry_1_rl_2_BIT_ETC___d1775 =
|
|
entry_3_rl[546];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1776 =
|
|
entry_0_rl[545];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1776 =
|
|
entry_1_rl[545];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1776 =
|
|
entry_2_rl[545];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_545_62_entry_1_rl_2_BIT_ETC___d1776 =
|
|
entry_3_rl[545];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1778 =
|
|
entry_0_rl[544];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1778 =
|
|
entry_1_rl[544];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1778 =
|
|
entry_2_rl[544];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_544_21_entry_1_rl_2_BIT_ETC___d1778 =
|
|
entry_3_rl[544];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1779 =
|
|
entry_0_rl[543];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1779 =
|
|
entry_1_rl[543];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1779 =
|
|
entry_2_rl[543];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_543_79_entry_1_rl_2_BIT_ETC___d1779 =
|
|
entry_3_rl[543];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1781 =
|
|
entry_0_rl[542];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1781 =
|
|
entry_1_rl[542];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1781 =
|
|
entry_2_rl[542];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_542_38_entry_1_rl_2_BIT_ETC___d1781 =
|
|
entry_3_rl[542];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1782 =
|
|
entry_0_rl[541];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1782 =
|
|
entry_1_rl[541];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1782 =
|
|
entry_2_rl[541];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_541_96_entry_1_rl_2_BIT_ETC___d1782 =
|
|
entry_3_rl[541];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1784 =
|
|
entry_0_rl[540];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1784 =
|
|
entry_1_rl[540];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1784 =
|
|
entry_2_rl[540];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_540_55_entry_1_rl_2_BIT_ETC___d1784 =
|
|
entry_3_rl[540];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1785 =
|
|
entry_0_rl[539];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1785 =
|
|
entry_1_rl[539];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1785 =
|
|
entry_2_rl[539];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_539_13_entry_1_rl_2_BIT_ETC___d1785 =
|
|
entry_3_rl[539];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1787 =
|
|
entry_0_rl[538];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1787 =
|
|
entry_1_rl[538];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1787 =
|
|
entry_2_rl[538];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_538_72_entry_1_rl_2_BIT_ETC___d1787 =
|
|
entry_3_rl[538];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1788 =
|
|
entry_0_rl[537];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1788 =
|
|
entry_1_rl[537];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1788 =
|
|
entry_2_rl[537];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_537_30_entry_1_rl_2_BIT_ETC___d1788 =
|
|
entry_3_rl[537];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1790 =
|
|
entry_0_rl[536];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1790 =
|
|
entry_1_rl[536];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1790 =
|
|
entry_2_rl[536];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_536_89_entry_1_rl_2_BIT_ETC___d1790 =
|
|
entry_3_rl[536];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1791 =
|
|
entry_0_rl[535];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1791 =
|
|
entry_1_rl[535];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1791 =
|
|
entry_2_rl[535];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_535_47_entry_1_rl_2_BIT_ETC___d1791 =
|
|
entry_3_rl[535];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1794 =
|
|
entry_0_rl[533];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1794 =
|
|
entry_1_rl[533];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1794 =
|
|
entry_2_rl[533];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_533_64_entry_1_rl_2_BIT_ETC___d1794 =
|
|
entry_3_rl[533];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1793 =
|
|
entry_0_rl[534];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1793 =
|
|
entry_1_rl[534];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1793 =
|
|
entry_2_rl[534];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_534_06_entry_1_rl_2_BIT_ETC___d1793 =
|
|
entry_3_rl[534];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1796 =
|
|
entry_0_rl[532];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1796 =
|
|
entry_1_rl[532];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1796 =
|
|
entry_2_rl[532];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_532_025_entry_1_rl_2_BI_ETC___d1796 =
|
|
entry_3_rl[532];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1797 =
|
|
entry_0_rl[531];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1797 =
|
|
entry_1_rl[531];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1797 =
|
|
entry_2_rl[531];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_531_32_entry_1_rl_2_BIT_ETC___d1797 =
|
|
entry_3_rl[531];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1799 =
|
|
entry_0_rl[530];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1799 =
|
|
entry_1_rl[530];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1799 =
|
|
entry_2_rl[530];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_530_90_entry_1_rl_2_BIT_ETC___d1799 =
|
|
entry_3_rl[530];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1800 =
|
|
entry_0_rl[529];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1800 =
|
|
entry_1_rl[529];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1800 =
|
|
entry_2_rl[529];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_529_48_entry_1_rl_2_BIT_ETC___d1800 =
|
|
entry_3_rl[529];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1802 =
|
|
entry_0_rl[528];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1802 =
|
|
entry_1_rl[528];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1802 =
|
|
entry_2_rl[528];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_528_07_entry_1_rl_2_BIT_ETC___d1802 =
|
|
entry_3_rl[528];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1803 =
|
|
entry_0_rl[527];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1803 =
|
|
entry_1_rl[527];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1803 =
|
|
entry_2_rl[527];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_527_65_entry_1_rl_2_BIT_ETC___d1803 =
|
|
entry_3_rl[527];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1805 =
|
|
entry_0_rl[526];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1805 =
|
|
entry_1_rl[526];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1805 =
|
|
entry_2_rl[526];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_526_24_entry_1_rl_2_BIT_ETC___d1805 =
|
|
entry_3_rl[526];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1806 =
|
|
entry_0_rl[525];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1806 =
|
|
entry_1_rl[525];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1806 =
|
|
entry_2_rl[525];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_525_82_entry_1_rl_2_BIT_ETC___d1806 =
|
|
entry_3_rl[525];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1690 =
|
|
entry_0_rl[517];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1690 =
|
|
entry_1_rl[517];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1690 =
|
|
entry_2_rl[517];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1690 =
|
|
entry_3_rl[517];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1808 =
|
|
entry_0_rl[524];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1808 =
|
|
entry_1_rl[524];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1808 =
|
|
entry_2_rl[524];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_524_41_entry_1_rl_2_BIT_ETC___d1808 =
|
|
entry_3_rl[524];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1809 =
|
|
entry_0_rl[523];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1809 =
|
|
entry_1_rl[523];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1809 =
|
|
entry_2_rl[523];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_523_99_entry_1_rl_2_BIT_ETC___d1809 =
|
|
entry_3_rl[523];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1811 =
|
|
entry_0_rl[522];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1811 =
|
|
entry_1_rl[522];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1811 =
|
|
entry_2_rl[522];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_522_58_entry_1_rl_2_BIT_ETC___d1811 =
|
|
entry_3_rl[522];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1812 =
|
|
entry_0_rl[521];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1812 =
|
|
entry_1_rl[521];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1812 =
|
|
entry_2_rl[521];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_521_16_entry_1_rl_2_BIT_ETC___d1812 =
|
|
entry_3_rl[521];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1814 =
|
|
entry_0_rl[520];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1814 =
|
|
entry_1_rl[520];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1814 =
|
|
entry_2_rl[520];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_520_75_entry_1_rl_2_BIT_ETC___d1814 =
|
|
entry_3_rl[520];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1815 =
|
|
entry_0_rl[519];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1815 =
|
|
entry_1_rl[519];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1815 =
|
|
entry_2_rl[519];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_519_33_entry_1_rl_2_BIT_ETC___d1815 =
|
|
entry_3_rl[519];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1817 =
|
|
entry_0_rl[518];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1817 =
|
|
entry_1_rl[518];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1817 =
|
|
entry_2_rl[518];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_518_92_entry_1_rl_2_BIT_ETC___d1817 =
|
|
entry_3_rl[518];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1818 =
|
|
entry_0_rl[517];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1818 =
|
|
entry_1_rl[517];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1818 =
|
|
entry_2_rl[517];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_517_50_entry_1_rl_2_BIT_ETC___d1818 =
|
|
entry_3_rl[517];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1692 =
|
|
entry_0_rl[516];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1692 =
|
|
entry_1_rl[516];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1692 =
|
|
entry_2_rl[516];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1692 =
|
|
entry_3_rl[516];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1711 =
|
|
entry_0_rl[319:256];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1711 =
|
|
entry_1_rl[319:256];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1711 =
|
|
entry_2_rl[319:256];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1711 =
|
|
entry_3_rl[319:256];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1721 =
|
|
entry_0_rl[63:0];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1721 =
|
|
entry_1_rl[63:0];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1721 =
|
|
entry_2_rl[63:0];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1721 =
|
|
entry_3_rl[63:0];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1833 =
|
|
entry_0_rl[191:128];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1833 =
|
|
entry_1_rl[191:128];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1833 =
|
|
entry_2_rl[191:128];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1833 =
|
|
entry_3_rl[191:128];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q201 =
|
|
entry_0_rl[512];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q201 =
|
|
entry_0_rl[513];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q201 =
|
|
entry_0_rl[514];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q201 =
|
|
entry_0_rl[515];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q202 =
|
|
entry_1_rl[512];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q202 =
|
|
entry_1_rl[513];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q202 =
|
|
entry_1_rl[514];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q202 =
|
|
entry_1_rl[515];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q203 =
|
|
entry_2_rl[512];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q203 =
|
|
entry_2_rl[513];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q203 =
|
|
entry_2_rl[514];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q203 =
|
|
entry_2_rl[515];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q204 =
|
|
entry_3_rl[512];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q204 =
|
|
entry_3_rl[513];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q204 =
|
|
entry_3_rl[514];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q204 =
|
|
entry_3_rl[515];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q201 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q202 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q203 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q204)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_512_161_entry_0_ETC___d2172 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q201;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_512_161_entry_0_ETC___d2172 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q202;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_512_161_entry_0_ETC___d2172 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q203;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BIT_512_161_entry_0_ETC___d2172 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q204;
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q205 =
|
|
entry_0_rl[127:64];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q205 =
|
|
entry_0_rl[255:192];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q205 =
|
|
entry_0_rl[383:320];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q205 =
|
|
entry_0_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q206 =
|
|
entry_1_rl[127:64];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q206 =
|
|
entry_1_rl[255:192];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q206 =
|
|
entry_1_rl[383:320];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q206 =
|
|
entry_1_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q207 =
|
|
entry_2_rl[127:64];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q207 =
|
|
entry_2_rl[255:192];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q207 =
|
|
entry_2_rl[383:320];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q207 =
|
|
entry_2_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q208 =
|
|
entry_3_rl[127:64];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q208 =
|
|
entry_3_rl[255:192];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q208 =
|
|
entry_3_rl[383:320];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q208 =
|
|
entry_3_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q205 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q206 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q207 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q208)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_127_TO_64_194__ETC___d2182 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q205;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_127_TO_64_194__ETC___d2182 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q206;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_127_TO_64_194__ETC___d2182 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q207;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_127_TO_64_194__ETC___d2182 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q208;
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_0_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q209 =
|
|
entry_0_rl[63:0];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q209 =
|
|
entry_0_rl[191:128];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q209 =
|
|
entry_0_rl[319:256];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q209 =
|
|
entry_0_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_1_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q210 =
|
|
entry_1_rl[63:0];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q210 =
|
|
entry_1_rl[191:128];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q210 =
|
|
entry_1_rl[319:256];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q210 =
|
|
entry_1_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_2_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q211 =
|
|
entry_2_rl[63:0];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q211 =
|
|
entry_2_rl[191:128];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q211 =
|
|
entry_2_rl[319:256];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q211 =
|
|
entry_2_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(search_paddr or entry_3_rl)
|
|
begin
|
|
case (search_paddr[5:4])
|
|
2'd0:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q212 =
|
|
entry_3_rl[63:0];
|
|
2'd1:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q212 =
|
|
entry_3_rl[191:128];
|
|
2'd2:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q212 =
|
|
entry_3_rl[319:256];
|
|
2'd3:
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q212 =
|
|
entry_3_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(idx__h325005 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q209 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q210 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q211 or
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q212)
|
|
begin
|
|
case (idx__h325005)
|
|
2'd0:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_63_TO_0_287_en_ETC___d2192 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_0_rl_BIT_ETC__q209;
|
|
2'd1:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_63_TO_0_287_en_ETC___d2192 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_1_rl_BIT_ETC__q210;
|
|
2'd2:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_63_TO_0_287_en_ETC___d2192 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_2_rl_BIT_ETC__q211;
|
|
2'd3:
|
|
SEL_ARR_SEL_ARR_entry_0_rl_BITS_63_TO_0_287_en_ETC___d2192 =
|
|
CASE_search_paddr_BITS_5_TO_4_0_entry_3_rl_BIT_ETC__q212;
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1827 =
|
|
entry_0_rl[511:448];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1827 =
|
|
entry_1_rl[511:448];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1827 =
|
|
entry_2_rl[511:448];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_511_TO_448_203_entry_1_ETC___d1827 =
|
|
entry_3_rl[511:448];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1828 =
|
|
entry_0_rl[447:384];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1828 =
|
|
entry_1_rl[447:384];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1828 =
|
|
entry_2_rl[447:384];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_447_TO_384_296_entry_1_ETC___d1828 =
|
|
entry_3_rl[447:384];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1829 =
|
|
entry_0_rl[383:320];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1829 =
|
|
entry_1_rl[383:320];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1829 =
|
|
entry_2_rl[383:320];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_383_TO_320_200_entry_1_ETC___d1829 =
|
|
entry_3_rl[383:320];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1830 =
|
|
entry_0_rl[319:256];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1830 =
|
|
entry_1_rl[319:256];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1830 =
|
|
entry_2_rl[319:256];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_319_TO_256_293_entry_1_ETC___d1830 =
|
|
entry_3_rl[319:256];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1714 =
|
|
entry_0_rl[255:192];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1714 =
|
|
entry_1_rl[255:192];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1714 =
|
|
entry_2_rl[255:192];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_255_TO_192_197_entry_1_ETC___d1714 =
|
|
entry_3_rl[255:192];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1716 =
|
|
entry_0_rl[191:128];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1716 =
|
|
entry_1_rl[191:128];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1716 =
|
|
entry_2_rl[191:128];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_191_TO_128_290_entry_1_ETC___d1716 =
|
|
entry_3_rl[191:128];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1835 =
|
|
entry_0_rl[127:64];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1835 =
|
|
entry_1_rl[127:64];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1835 =
|
|
entry_2_rl[127:64];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_127_TO_64_194_entry_1__ETC___d1835 =
|
|
entry_3_rl[127:64];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1836 =
|
|
entry_0_rl[63:0];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1836 =
|
|
entry_1_rl[63:0];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1836 =
|
|
entry_2_rl[63:0];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_63_TO_0_287_entry_1_rl_ETC___d1836 =
|
|
entry_3_rl[63:0];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1702 =
|
|
entry_0_rl[512];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1702 =
|
|
entry_1_rl[512];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1702 =
|
|
entry_2_rl[512];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_512_161_entry_1_rl_2_BI_ETC___d1702 =
|
|
entry_3_rl[512];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1820 =
|
|
entry_0_rl[516];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1820 =
|
|
entry_1_rl[516];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1820 =
|
|
entry_2_rl[516];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BIT_516_011_entry_1_rl_2_BI_ETC___d1820 =
|
|
entry_3_rl[516];
|
|
endcase
|
|
end
|
|
always@(deq_idx or entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (deq_idx)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1533 =
|
|
entry_0_rl[637:580];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1533 =
|
|
entry_1_rl[637:580];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1533 =
|
|
entry_2_rl[637:580];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1533 =
|
|
entry_3_rl[637:580];
|
|
endcase
|
|
end
|
|
always@(issueQ$D_OUT or
|
|
entry_0_rl or entry_1_rl or entry_2_rl or entry_3_rl)
|
|
begin
|
|
case (issueQ$D_OUT)
|
|
2'd0:
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1725 =
|
|
entry_0_rl[637:580];
|
|
2'd1:
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1725 =
|
|
entry_1_rl[637:580];
|
|
2'd2:
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1725 =
|
|
entry_2_rl[637:580];
|
|
2'd3:
|
|
SEL_ARR_entry_0_rl_BITS_637_TO_580_9_entry_1_r_ETC___d1725 =
|
|
entry_3_rl[637:580];
|
|
endcase
|
|
end
|
|
always@(enq_idx or
|
|
IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d34 or
|
|
IF_valid_1_lat_0_whas__8_THEN_valid_1_lat_0_wg_ETC___d41 or
|
|
IF_valid_2_lat_0_whas__5_THEN_valid_2_lat_0_wg_ETC___d48 or
|
|
IF_valid_3_lat_0_whas__2_THEN_valid_3_lat_0_wg_ETC___d55)
|
|
begin
|
|
case (enq_idx)
|
|
2'd0:
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 =
|
|
IF_valid_0_lat_0_whas__1_THEN_valid_0_lat_0_wg_ETC___d34;
|
|
2'd1:
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 =
|
|
IF_valid_1_lat_0_whas__8_THEN_valid_1_lat_0_wg_ETC___d41;
|
|
2'd2:
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 =
|
|
IF_valid_2_lat_0_whas__5_THEN_valid_2_lat_0_wg_ETC___d48;
|
|
2'd3:
|
|
SEL_ARR_IF_valid_0_lat_0_whas__1_THEN_valid_0__ETC___d126 =
|
|
IF_valid_3_lat_0_whas__2_THEN_valid_3_lat_0_wg_ETC___d55;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
entry_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
638'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
entry_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
638'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
entry_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
638'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
entry_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
638'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
initIdx <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
inited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
valid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
valid_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
valid_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (entry_0_rl$EN)
|
|
entry_0_rl <= `BSV_ASSIGNMENT_DELAY entry_0_rl$D_IN;
|
|
if (entry_1_rl$EN)
|
|
entry_1_rl <= `BSV_ASSIGNMENT_DELAY entry_1_rl$D_IN;
|
|
if (entry_2_rl$EN)
|
|
entry_2_rl <= `BSV_ASSIGNMENT_DELAY entry_2_rl$D_IN;
|
|
if (entry_3_rl$EN)
|
|
entry_3_rl <= `BSV_ASSIGNMENT_DELAY entry_3_rl$D_IN;
|
|
if (initIdx$EN) initIdx <= `BSV_ASSIGNMENT_DELAY initIdx$D_IN;
|
|
if (inited$EN) inited <= `BSV_ASSIGNMENT_DELAY inited$D_IN;
|
|
if (valid_0_rl$EN)
|
|
valid_0_rl <= `BSV_ASSIGNMENT_DELAY valid_0_rl$D_IN;
|
|
if (valid_1_rl$EN)
|
|
valid_1_rl <= `BSV_ASSIGNMENT_DELAY valid_1_rl$D_IN;
|
|
if (valid_2_rl$EN)
|
|
valid_2_rl <= `BSV_ASSIGNMENT_DELAY valid_2_rl$D_IN;
|
|
if (valid_3_rl$EN)
|
|
valid_3_rl <= `BSV_ASSIGNMENT_DELAY valid_3_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
entry_0_rl =
|
|
638'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
entry_1_rl =
|
|
638'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
entry_2_rl =
|
|
638'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
entry_3_rl =
|
|
638'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
initIdx = 2'h2;
|
|
inited = 1'h0;
|
|
valid_0_rl = 1'h0;
|
|
valid_1_rl = 1'h0;
|
|
valid_2_rl = 1'h0;
|
|
valid_3_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkStoreBufferEhr
|
|
|