507 lines
14 KiB
Verilog
507 lines
14 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:37:05 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// pred_0_pred O 25
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// RDY_pred_0_pred O 1 const
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// pred_1_pred O 25
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// RDY_pred_1_pred O 1 const
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// RDY_update O 1 const
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// RDY_flush O 1 const
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// flush_done O 1 const
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// RDY_flush_done O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// pred_0_pred_pc I 129
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// pred_1_pred_pc I 129
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// update_pc I 129
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// update_taken I 1
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// update_train I 24
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// update_mispred I 1
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// EN_update I 1
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// EN_flush I 1 unused
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// EN_pred_0_pred I 1
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// EN_pred_1_pred I 1
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//
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// Combinational paths from inputs to outputs:
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// EN_pred_0_pred -> pred_1_pred
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkTourPred(CLK,
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RST_N,
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pred_0_pred_pc,
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EN_pred_0_pred,
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pred_0_pred,
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RDY_pred_0_pred,
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pred_1_pred_pc,
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EN_pred_1_pred,
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pred_1_pred,
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RDY_pred_1_pred,
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update_pc,
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update_taken,
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update_train,
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update_mispred,
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EN_update,
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RDY_update,
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EN_flush,
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RDY_flush,
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flush_done,
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RDY_flush_done);
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input CLK;
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input RST_N;
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// actionvalue method pred_0_pred
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input [128 : 0] pred_0_pred_pc;
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input EN_pred_0_pred;
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output [24 : 0] pred_0_pred;
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output RDY_pred_0_pred;
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// actionvalue method pred_1_pred
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input [128 : 0] pred_1_pred_pc;
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input EN_pred_1_pred;
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output [24 : 0] pred_1_pred;
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output RDY_pred_1_pred;
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// action method update
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input [128 : 0] update_pc;
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input update_taken;
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input [23 : 0] update_train;
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input update_mispred;
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input EN_update;
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output RDY_update;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// signals for module outputs
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wire [24 : 0] pred_0_pred, pred_1_pred;
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wire RDY_flush,
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RDY_flush_done,
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RDY_pred_0_pred,
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RDY_pred_1_pred,
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RDY_update,
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flush_done;
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// inlined wires
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wire [1 : 0] predCnt_lat_0$wget,
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predCnt_lat_1$wget,
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predRes_lat_0$wget,
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predRes_lat_1$wget;
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// register predCnt_rl
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reg [1 : 0] predCnt_rl;
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wire [1 : 0] predCnt_rl$D_IN;
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wire predCnt_rl$EN;
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// register predRes_rl
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reg [1 : 0] predRes_rl;
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wire [1 : 0] predRes_rl$D_IN;
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wire predRes_rl$EN;
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// ports of submodule choiceBht
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wire [11 : 0] choiceBht$ADDR_1,
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choiceBht$ADDR_2,
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choiceBht$ADDR_3,
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choiceBht$ADDR_4,
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choiceBht$ADDR_5,
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choiceBht$ADDR_IN;
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wire [1 : 0] choiceBht$D_IN,
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choiceBht$D_OUT_1,
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choiceBht$D_OUT_2,
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choiceBht$D_OUT_3;
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wire choiceBht$WE;
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// ports of submodule gHistReg
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wire [11 : 0] gHistReg$history, gHistReg$redirect_newHist;
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wire [1 : 0] gHistReg$addHistory_num, gHistReg$addHistory_taken;
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wire gHistReg$EN_addHistory, gHistReg$EN_redirect;
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// ports of submodule globalBht
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wire [11 : 0] globalBht$ADDR_1,
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globalBht$ADDR_2,
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globalBht$ADDR_3,
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globalBht$ADDR_4,
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globalBht$ADDR_5,
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globalBht$ADDR_IN;
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wire [1 : 0] globalBht$D_IN,
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globalBht$D_OUT_1,
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globalBht$D_OUT_2,
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globalBht$D_OUT_3;
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wire globalBht$WE;
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// ports of submodule localBht
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wire [9 : 0] localBht$ADDR_1,
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localBht$ADDR_2,
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localBht$ADDR_3,
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localBht$ADDR_4,
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localBht$ADDR_5,
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localBht$ADDR_IN;
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wire [2 : 0] localBht$D_IN,
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localBht$D_OUT_1,
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localBht$D_OUT_2,
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localBht$D_OUT_3;
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wire localBht$WE;
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// ports of submodule localHistTab
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wire [9 : 0] localHistTab$ADDR_1,
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localHistTab$ADDR_2,
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localHistTab$ADDR_3,
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localHistTab$ADDR_4,
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localHistTab$ADDR_5,
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localHistTab$ADDR_IN,
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localHistTab$D_IN,
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localHistTab$D_OUT_1,
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localHistTab$D_OUT_2;
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wire localHistTab$WE;
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// rule scheduling signals
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wire CAN_FIRE_RL_canonGlobalHist,
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CAN_FIRE_RL_predCnt_canon,
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CAN_FIRE_RL_predRes_canon,
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CAN_FIRE_flush,
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CAN_FIRE_pred_0_pred,
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CAN_FIRE_pred_1_pred,
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CAN_FIRE_update,
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WILL_FIRE_RL_canonGlobalHist,
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WILL_FIRE_RL_predCnt_canon,
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WILL_FIRE_RL_predRes_canon,
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WILL_FIRE_flush,
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WILL_FIRE_pred_0_pred,
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WILL_FIRE_pred_1_pred,
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WILL_FIRE_update;
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// remaining internal signals
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wire [11 : 0] globalHist__h2457, globalHist__h2811;
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wire [1 : 0] IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8,
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IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18,
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upd__h2081,
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upd__h2201,
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upd__h2893,
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upd__h3108,
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x__h2572,
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x__h2954,
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y__h2774,
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y__h3141;
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wire IF_choiceBht_sub_gHistReg_history__2_SRL_IF_pr_ETC___d49,
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IF_choiceBht_sub_gHistReg_history__2_SRL_predC_ETC___d32;
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// actionvalue method pred_0_pred
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assign pred_0_pred =
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{ IF_choiceBht_sub_gHistReg_history__2_SRL_predC_ETC___d32,
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globalHist__h2457,
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localHistTab$D_OUT_2,
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globalBht$D_OUT_2[1],
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localBht$D_OUT_3[2] } ;
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assign RDY_pred_0_pred = 1'd1 ;
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assign CAN_FIRE_pred_0_pred = 1'd1 ;
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assign WILL_FIRE_pred_0_pred = EN_pred_0_pred ;
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// actionvalue method pred_1_pred
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assign pred_1_pred =
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{ IF_choiceBht_sub_gHistReg_history__2_SRL_IF_pr_ETC___d49,
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globalHist__h2811,
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localHistTab$D_OUT_1,
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globalBht$D_OUT_1[1],
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localBht$D_OUT_2[2] } ;
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assign RDY_pred_1_pred = 1'd1 ;
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assign CAN_FIRE_pred_1_pred = 1'd1 ;
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assign WILL_FIRE_pred_1_pred = EN_pred_1_pred ;
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// action method update
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assign RDY_update = 1'd1 ;
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assign CAN_FIRE_update = 1'd1 ;
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assign WILL_FIRE_update = EN_update ;
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// action method flush
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assign RDY_flush = 1'd1 ;
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assign CAN_FIRE_flush = 1'd1 ;
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assign WILL_FIRE_flush = EN_flush ;
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// value method flush_done
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assign flush_done = 1'd1 ;
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assign RDY_flush_done = 1'd1 ;
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// submodule choiceBht
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RegFile #(.addr_width(32'd12),
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.data_width(32'd2),
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.lo(12'd0),
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.hi(12'd4095)) choiceBht(.CLK(CLK),
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.ADDR_1(choiceBht$ADDR_1),
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.ADDR_2(choiceBht$ADDR_2),
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.ADDR_3(choiceBht$ADDR_3),
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.ADDR_4(choiceBht$ADDR_4),
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.ADDR_5(choiceBht$ADDR_5),
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.ADDR_IN(choiceBht$ADDR_IN),
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.D_IN(choiceBht$D_IN),
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.WE(choiceBht$WE),
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.D_OUT_1(choiceBht$D_OUT_1),
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.D_OUT_2(choiceBht$D_OUT_2),
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.D_OUT_3(choiceBht$D_OUT_3),
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.D_OUT_4(),
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.D_OUT_5());
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// submodule gHistReg
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mkTourGHistReg gHistReg(.CLK(CLK),
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.RST_N(RST_N),
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.addHistory_num(gHistReg$addHistory_num),
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.addHistory_taken(gHistReg$addHistory_taken),
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.redirect_newHist(gHistReg$redirect_newHist),
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.EN_addHistory(gHistReg$EN_addHistory),
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.EN_redirect(gHistReg$EN_redirect),
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.history(gHistReg$history),
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.RDY_history(),
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.RDY_addHistory(),
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.RDY_redirect());
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// submodule globalBht
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RegFile #(.addr_width(32'd12),
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.data_width(32'd2),
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.lo(12'd0),
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.hi(12'd4095)) globalBht(.CLK(CLK),
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.ADDR_1(globalBht$ADDR_1),
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.ADDR_2(globalBht$ADDR_2),
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.ADDR_3(globalBht$ADDR_3),
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.ADDR_4(globalBht$ADDR_4),
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.ADDR_5(globalBht$ADDR_5),
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.ADDR_IN(globalBht$ADDR_IN),
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.D_IN(globalBht$D_IN),
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.WE(globalBht$WE),
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.D_OUT_1(globalBht$D_OUT_1),
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.D_OUT_2(globalBht$D_OUT_2),
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.D_OUT_3(globalBht$D_OUT_3),
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.D_OUT_4(),
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.D_OUT_5());
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// submodule localBht
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RegFile #(.addr_width(32'd10),
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.data_width(32'd3),
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.lo(10'd0),
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.hi(10'd1023)) localBht(.CLK(CLK),
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.ADDR_1(localBht$ADDR_1),
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.ADDR_2(localBht$ADDR_2),
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.ADDR_3(localBht$ADDR_3),
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.ADDR_4(localBht$ADDR_4),
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.ADDR_5(localBht$ADDR_5),
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.ADDR_IN(localBht$ADDR_IN),
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.D_IN(localBht$D_IN),
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.WE(localBht$WE),
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.D_OUT_1(localBht$D_OUT_1),
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.D_OUT_2(localBht$D_OUT_2),
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.D_OUT_3(localBht$D_OUT_3),
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.D_OUT_4(),
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.D_OUT_5());
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// submodule localHistTab
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RegFile #(.addr_width(32'd10),
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.data_width(32'd10),
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.lo(10'd0),
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.hi(10'd1023)) localHistTab(.CLK(CLK),
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.ADDR_1(localHistTab$ADDR_1),
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.ADDR_2(localHistTab$ADDR_2),
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.ADDR_3(localHistTab$ADDR_3),
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.ADDR_4(localHistTab$ADDR_4),
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.ADDR_5(localHistTab$ADDR_5),
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.ADDR_IN(localHistTab$ADDR_IN),
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.D_IN(localHistTab$D_IN),
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.WE(localHistTab$WE),
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.D_OUT_1(localHistTab$D_OUT_1),
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.D_OUT_2(localHistTab$D_OUT_2),
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.D_OUT_3(),
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.D_OUT_4(),
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.D_OUT_5());
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// rule RL_canonGlobalHist
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assign CAN_FIRE_RL_canonGlobalHist = 1'd1 ;
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assign WILL_FIRE_RL_canonGlobalHist = 1'd1 ;
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// rule RL_predCnt_canon
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assign CAN_FIRE_RL_predCnt_canon = 1'd1 ;
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assign WILL_FIRE_RL_predCnt_canon = 1'd1 ;
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// rule RL_predRes_canon
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assign CAN_FIRE_RL_predRes_canon = 1'd1 ;
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assign WILL_FIRE_RL_predRes_canon = 1'd1 ;
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// inlined wires
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assign predCnt_lat_0$wget = predCnt_rl + 2'd1 ;
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assign predCnt_lat_1$wget =
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IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8 + 2'd1 ;
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assign predRes_lat_0$wget =
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IF_choiceBht_sub_gHistReg_history__2_SRL_predC_ETC___d32 ?
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predRes_rl | x__h2572 :
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predRes_rl & y__h2774 ;
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assign predRes_lat_1$wget =
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IF_choiceBht_sub_gHistReg_history__2_SRL_IF_pr_ETC___d49 ?
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IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18 |
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x__h2954 :
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IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18 &
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y__h3141 ;
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// register predCnt_rl
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assign predCnt_rl$D_IN = 2'd0 ;
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assign predCnt_rl$EN = 1'd1 ;
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// register predRes_rl
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assign predRes_rl$D_IN = 2'd0 ;
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assign predRes_rl$EN = 1'd1 ;
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// submodule choiceBht
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assign choiceBht$ADDR_1 = globalHist__h2811 ;
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assign choiceBht$ADDR_2 = globalHist__h2457 ;
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assign choiceBht$ADDR_3 = update_train[23:12] ;
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assign choiceBht$ADDR_4 = 12'h0 ;
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assign choiceBht$ADDR_5 = 12'h0 ;
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assign choiceBht$ADDR_IN = update_train[23:12] ;
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assign choiceBht$D_IN =
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(update_train[0] == update_taken) ?
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((choiceBht$D_OUT_3 == 2'd3) ?
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choiceBht$D_OUT_3 :
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choiceBht$D_OUT_3 + 2'd1) :
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((choiceBht$D_OUT_3 == 2'd0) ?
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choiceBht$D_OUT_3 :
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choiceBht$D_OUT_3 - 2'd1) ;
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assign choiceBht$WE = EN_update && update_train[1] != update_train[0] ;
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// submodule gHistReg
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assign gHistReg$addHistory_num =
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EN_pred_1_pred ?
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upd__h2201 :
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IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8 ;
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assign gHistReg$addHistory_taken =
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EN_pred_1_pred ?
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upd__h2081 :
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IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18 ;
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assign gHistReg$redirect_newHist = { update_taken, update_train[23:13] } ;
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assign gHistReg$EN_addHistory = 1'd1 ;
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assign gHistReg$EN_redirect = EN_update && update_mispred ;
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// submodule globalBht
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assign globalBht$ADDR_1 = globalHist__h2811 ;
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assign globalBht$ADDR_2 = globalHist__h2457 ;
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assign globalBht$ADDR_3 = update_train[23:12] ;
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assign globalBht$ADDR_4 = 12'h0 ;
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assign globalBht$ADDR_5 = 12'h0 ;
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assign globalBht$ADDR_IN = update_train[23:12] ;
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assign globalBht$D_IN =
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update_taken ?
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((globalBht$D_OUT_3 == 2'd3) ?
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globalBht$D_OUT_3 :
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globalBht$D_OUT_3 + 2'd1) :
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((globalBht$D_OUT_3 == 2'd0) ?
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globalBht$D_OUT_3 :
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globalBht$D_OUT_3 - 2'd1) ;
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assign globalBht$WE = EN_update ;
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// submodule localBht
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assign localBht$ADDR_1 = update_train[11:2] ;
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assign localBht$ADDR_2 = localHistTab$D_OUT_1 ;
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assign localBht$ADDR_3 = localHistTab$D_OUT_2 ;
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assign localBht$ADDR_4 = 10'h0 ;
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assign localBht$ADDR_5 = 10'h0 ;
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assign localBht$ADDR_IN = update_train[11:2] ;
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assign localBht$D_IN =
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update_taken ?
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((localBht$D_OUT_1 == 3'd7) ?
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localBht$D_OUT_1 :
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localBht$D_OUT_1 + 3'd1) :
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((localBht$D_OUT_1 == 3'd0) ?
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localBht$D_OUT_1 :
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localBht$D_OUT_1 - 3'd1) ;
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assign localBht$WE = EN_update ;
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// submodule localHistTab
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assign localHistTab$ADDR_1 = pred_1_pred_pc[11:2] ;
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assign localHistTab$ADDR_2 = pred_0_pred_pc[11:2] ;
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assign localHistTab$ADDR_3 = 10'h0 ;
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assign localHistTab$ADDR_4 = 10'h0 ;
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assign localHistTab$ADDR_5 = 10'h0 ;
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assign localHistTab$ADDR_IN = update_pc[11:2] ;
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assign localHistTab$D_IN = { update_taken, update_train[11:3] } ;
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assign localHistTab$WE = EN_update ;
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// remaining internal signals
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assign IF_choiceBht_sub_gHistReg_history__2_SRL_IF_pr_ETC___d49 =
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choiceBht$D_OUT_1[1] ?
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localBht$D_OUT_2[2] :
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globalBht$D_OUT_1[1] ;
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assign IF_choiceBht_sub_gHistReg_history__2_SRL_predC_ETC___d32 =
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choiceBht$D_OUT_2[1] ?
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localBht$D_OUT_3[2] :
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globalBht$D_OUT_2[1] ;
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assign IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8 =
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EN_pred_0_pred ? upd__h2893 : predCnt_rl ;
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assign IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18 =
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EN_pred_0_pred ? upd__h3108 : predRes_rl ;
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assign globalHist__h2457 = gHistReg$history >> predCnt_rl ;
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assign globalHist__h2811 =
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|
gHistReg$history >>
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IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8 ;
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|
assign upd__h2081 = predRes_lat_1$wget ;
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|
assign upd__h2201 = predCnt_lat_1$wget ;
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|
assign upd__h2893 = predCnt_lat_0$wget ;
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assign upd__h3108 = predRes_lat_0$wget ;
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assign x__h2572 = 2'd1 << predCnt_rl ;
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|
assign x__h2954 =
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|
2'd1 << IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8 ;
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|
assign y__h2774 = ~x__h2572 ;
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|
assign y__h3141 = ~x__h2954 ;
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|
|
|
// handling of inlined registers
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|
|
|
always@(posedge CLK)
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|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
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|
predCnt_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
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|
predRes_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
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|
end
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|
else
|
|
begin
|
|
if (predCnt_rl$EN)
|
|
predCnt_rl <= `BSV_ASSIGNMENT_DELAY predCnt_rl$D_IN;
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|
if (predRes_rl$EN)
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|
predRes_rl <= `BSV_ASSIGNMENT_DELAY predRes_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
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|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
predCnt_rl = 2'h2;
|
|
predRes_rl = 2'h2;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
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|
// synopsys translate_on
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|
endmodule // mkTourPred
|
|
|