74 lines
1.8 KiB
Verilog
74 lines
1.8 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:28:07 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// aluBr O 1
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// aluBr_a I 64
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// aluBr_b I 64
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// aluBr_brFunc I 3
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//
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// Combinational paths from inputs to outputs:
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// (aluBr_a, aluBr_b, aluBr_brFunc) -> aluBr
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_aluBr(aluBr_a,
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aluBr_b,
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aluBr_brFunc,
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aluBr);
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// value method aluBr
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input [63 : 0] aluBr_a;
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input [63 : 0] aluBr_b;
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input [2 : 0] aluBr_brFunc;
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output aluBr;
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// signals for module outputs
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reg aluBr;
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// remaining internal signals
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wire aluBr_a_EQ_aluBr_b___d2,
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aluBr_a_SLT_aluBr_b___d6,
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aluBr_a_ULT_aluBr_b___d8;
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// value method aluBr
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always@(aluBr_brFunc or
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aluBr_a_EQ_aluBr_b___d2 or
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aluBr_a_SLT_aluBr_b___d6 or aluBr_a_ULT_aluBr_b___d8)
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begin
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case (aluBr_brFunc)
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3'd0: aluBr = aluBr_a_EQ_aluBr_b___d2;
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3'd1: aluBr = !aluBr_a_EQ_aluBr_b___d2;
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3'd2: aluBr = aluBr_a_SLT_aluBr_b___d6;
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3'd3: aluBr = aluBr_a_ULT_aluBr_b___d8;
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3'd4: aluBr = !aluBr_a_SLT_aluBr_b___d6;
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3'd5: aluBr = !aluBr_a_ULT_aluBr_b___d8;
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default: aluBr = aluBr_brFunc == 3'd6;
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endcase
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end
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// remaining internal signals
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assign aluBr_a_EQ_aluBr_b___d2 = aluBr_a == aluBr_b ;
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assign aluBr_a_SLT_aluBr_b___d6 =
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(aluBr_a ^ 64'h8000000000000000) <
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(aluBr_b ^ 64'h8000000000000000) ;
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assign aluBr_a_ULT_aluBr_b___d8 = aluBr_a < aluBr_b ;
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endmodule // module_aluBr
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