389 lines
16 KiB
Verilog
389 lines
16 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:28:08 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// checkForException O 14
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// checkForException_dInst I 145
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// checkForException_regs I 27
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// checkForException_csrState I 15
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// checkForException_pcc I 129
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// checkForException_fourByteInst I 1
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//
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// Combinational paths from inputs to outputs:
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// (checkForException_dInst,
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// checkForException_regs,
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// checkForException_csrState,
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// checkForException_pcc,
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// checkForException_fourByteInst) -> checkForException
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_checkForException(checkForException_dInst,
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checkForException_regs,
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checkForException_csrState,
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checkForException_pcc,
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checkForException_fourByteInst,
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checkForException);
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// value method checkForException
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input [144 : 0] checkForException_dInst;
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input [26 : 0] checkForException_regs;
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input [14 : 0] checkForException_csrState;
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input [128 : 0] checkForException_pcc;
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input checkForException_fourByteInst;
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output [13 : 0] checkForException;
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// signals for module outputs
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wire [13 : 0] checkForException;
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// remaining internal signals
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reg [4 : 0] CASE_checkForException_dInst_BITS_144_TO_140_2_ETC__q2,
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code__h2344;
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reg IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d197,
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IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d268;
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wire [63 : 0] memCap_address__h637, x__h443, x__h997;
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wire [31 : 0] imm__h1512;
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wire [18 : 0] INV_checkForException_pcc_BITS_108_TO_90__q1;
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wire [13 : 0] b_base__h929,
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cr_addrBits__h111,
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cr_addrBits__h561,
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x__h960,
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y__h1054;
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wire [12 : 0] IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d284;
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wire [11 : 0] IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18,
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b_top__h928,
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csr__h1509,
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inc__h652;
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wire [5 : 0] x__h1035;
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wire [4 : 0] IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d275,
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d276,
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rs1__h1511;
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wire [2 : 0] repBound__h535,
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rm_mode__h2169,
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tb__h532,
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tmp_expBotHalf__h991,
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tmp_expTopHalf__h989;
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wire [1 : 0] carry_out__h594,
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impliedTopBits__h596,
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len_correction__h595,
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x__h617;
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wire IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d200,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d271,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d45,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d50,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d64,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d68,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d79,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d46,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60,
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IF_checkForException_dInst_BIT_38_60_THEN_chec_ETC___d193,
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NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d148,
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NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d152,
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NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d153,
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NOT_checkForException_dInst_BITS_139_TO_137_02_ETC___d225,
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NOT_checkForException_dInst_BITS_139_TO_137_02_ETC___d263,
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d129,
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d162,
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checkForException_dInst_BITS_139_TO_137_02_EQ__ETC___d127,
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checkForException_dInst_BITS_139_TO_137_02_EQ__ETC___d159;
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// value method checkForException
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assign checkForException =
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{ IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d200,
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d284 } ;
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// remaining internal signals
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assign IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d275 =
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(IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d45 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d50 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d64 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d68) ?
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5'd1 :
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(checkForException_pcc[113] ?
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((INV_checkForException_pcc_BITS_108_TO_90__q1[18:1] ==
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18'd262143) ?
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5'd2 :
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5'd3) :
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5'd17) ;
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assign IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d276 =
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(IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d45 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d50 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d79) ?
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d275 :
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5'd24 ;
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assign IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d284 =
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d271 ?
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{ 8'd32,
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d276 } :
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{ 2'd1,
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6'bxxxxxx /* unspecified value */ ,
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CASE_checkForException_dInst_BITS_144_TO_140_2_ETC__q2 } ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d200 =
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d45 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d50 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d79 ||
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checkForException_dInst[144:140] == 5'd22 ||
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checkForException_dInst[144:140] == 5'd23 ||
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IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d197 ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d271 =
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d45 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d50 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d79 ||
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checkForException_dInst[144:140] != 5'd22 &&
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checkForException_dInst[144:140] != 5'd23 &&
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IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d268 ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d45 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29 ==
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39) ?
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cr_addrBits__h111 > y__h1054 :
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29 ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d50 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d46 ==
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39) ?
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cr_addrBits__h111 < x__h960 :
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39 ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d64 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29 ==
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60) ?
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cr_addrBits__h561 > y__h1054 :
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29 ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d68 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d46 ==
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60) ?
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cr_addrBits__h561 < x__h960 :
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60 ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d79 =
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d64 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d68 ||
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!checkForException_pcc[113] ||
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INV_checkForException_pcc_BITS_108_TO_90__q1[18:1] !=
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18'd262143 ||
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!checkForException_pcc[128] ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18 =
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INV_checkForException_pcc_BITS_108_TO_90__q1[0] ?
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{ checkForException_pcc[89:81], 3'd0 } :
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b_top__h928 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29 =
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tb__h532 < repBound__h535 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39 =
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cr_addrBits__h111[13:11] < repBound__h535 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d46 =
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x__h960[13:11] < repBound__h535 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60 =
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cr_addrBits__h561[13:11] < repBound__h535 ;
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assign IF_checkForException_dInst_BIT_38_60_THEN_chec_ETC___d193 =
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checkForException_dInst[38] ?
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d162 ||
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checkForException_dInst[37:33] == 5'd10 ||
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!checkForException_pcc[122] &&
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checkForException_dInst[37:33] != 5'd1 :
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checkForException_dInst[144:140] == 5'd16 &&
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(checkForException_dInst[139:137] != 3'd4 ||
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rm_mode__h2169 != 3'b0 && rm_mode__h2169 != 3'b001 &&
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rm_mode__h2169 != 3'b010 &&
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rm_mode__h2169 != 3'b011 &&
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rm_mode__h2169 != 3'b100) ;
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assign INV_checkForException_pcc_BITS_108_TO_90__q1 =
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~checkForException_pcc[108:90] ;
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assign NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d148 =
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csr__h1509 != 12'hC00 ||
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(checkForException_dInst[139:137] != 3'd0 ||
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checkForException_dInst[114:110] != 5'd15) &&
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rs1__h1511 == 5'd0 &&
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imm__h1512 == 32'd0 ;
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assign NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d152 =
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csr__h1509 != 12'hC02 ||
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(checkForException_dInst[139:137] != 3'd0 ||
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checkForException_dInst[114:110] != 5'd15) &&
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rs1__h1511 == 5'd0 &&
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imm__h1512 == 32'd0 ;
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assign NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d153 =
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csr__h1509 != 12'h001 && csr__h1509 != 12'h002 &&
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csr__h1509 != 12'h003 &&
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NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d148 &&
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NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d152 ;
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assign NOT_checkForException_dInst_BITS_139_TO_137_02_ETC___d225 =
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(checkForException_dInst[139:137] != 3'd0 ||
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checkForException_dInst[114:110] != 5'd15) &&
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rs1__h1511 == 5'd0 &&
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imm__h1512 == 32'd0 ||
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csr__h1509[11:10] != 2'b11 ;
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assign NOT_checkForException_dInst_BITS_139_TO_137_02_ETC___d263 =
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NOT_checkForException_dInst_BITS_139_TO_137_02_ETC___d225 &&
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!checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d129 &&
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csr__h1509 != 12'h8FF &&
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!checkForException_pcc[122] &&
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NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d153 ;
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assign b_base__h929 =
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{ checkForException_pcc[77:67],
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~checkForException_pcc[66],
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checkForException_pcc[65:64] } ;
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assign b_top__h928 =
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{ checkForException_pcc[89:81],
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~checkForException_pcc[80:79],
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checkForException_pcc[78] } ;
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assign carry_out__h594 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18 <
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x__h960[11:0]) ?
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2'b01 :
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2'b0 ;
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assign checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d129 =
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checkForException_csrState[10:9] < csr__h1509[9:8] ;
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assign checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d162 =
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checkForException_csrState[10:9] <
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checkForException_dInst[37:36] ;
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assign checkForException_dInst_BITS_139_TO_137_02_EQ__ETC___d127 =
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(checkForException_dInst[139:137] == 3'd0 &&
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checkForException_dInst[114:110] == 5'd15 ||
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rs1__h1511 != 5'd0 ||
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imm__h1512 != 32'd0) &&
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csr__h1509[11:10] == 2'b11 ;
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assign checkForException_dInst_BITS_139_TO_137_02_EQ__ETC___d159 =
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checkForException_dInst_BITS_139_TO_137_02_EQ__ETC___d127 ||
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d129 ||
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csr__h1509 == 12'h8FF ||
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!checkForException_pcc[122] &&
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NOT_IF_checkForException_dInst_BIT_51_22_THEN__ETC___d153 ||
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checkForException_csrState[10:9] == 2'd1 &&
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checkForException_csrState[8] &&
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checkForException_dInst[50:39] == 12'h180 ;
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assign cr_addrBits__h111 =
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INV_checkForException_pcc_BITS_108_TO_90__q1[0] ?
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x__h443[13:0] :
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checkForException_pcc[13:0] ;
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assign cr_addrBits__h561 =
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INV_checkForException_pcc_BITS_108_TO_90__q1[0] ?
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x__h997[13:0] :
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memCap_address__h637[13:0] ;
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assign csr__h1509 =
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checkForException_dInst[51] ?
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checkForException_dInst[50:39] :
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12'h8FF ;
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assign imm__h1512 =
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checkForException_dInst[32] ?
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checkForException_dInst[31:0] :
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32'd0 ;
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assign impliedTopBits__h596 = x__h617 + len_correction__h595 ;
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assign inc__h652 = checkForException_fourByteInst ? 12'd4 : 12'd2 ;
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assign len_correction__h595 =
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INV_checkForException_pcc_BITS_108_TO_90__q1[0] ? 2'b01 : 2'b0 ;
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assign memCap_address__h637 =
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checkForException_pcc[63:0] +
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{ {52{inc__h652[11]}}, inc__h652 } ;
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assign repBound__h535 = x__h960[13:11] - 3'b001 ;
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assign rm_mode__h2169 =
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(checkForException_dInst[113:111] == 3'b111) ?
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checkForException_csrState[14:12] :
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checkForException_dInst[113:111] ;
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assign rs1__h1511 =
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(checkForException_regs[19] && !checkForException_regs[18]) ?
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checkForException_regs[17:13] :
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5'd0 ;
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assign tb__h532 =
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{ impliedTopBits__h596,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18[11] } ;
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assign tmp_expBotHalf__h991 =
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{ ~checkForException_pcc[66], checkForException_pcc[65:64] } ;
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assign tmp_expTopHalf__h989 =
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{ ~checkForException_pcc[80:79], checkForException_pcc[78] } ;
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assign x__h1035 = { tmp_expTopHalf__h989, tmp_expBotHalf__h991 } ;
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assign x__h443 = checkForException_pcc[63:0] >> x__h1035 ;
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assign x__h617 = x__h960[13:12] + carry_out__h594 ;
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assign x__h960 =
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INV_checkForException_pcc_BITS_108_TO_90__q1[0] ?
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{ checkForException_pcc[77:67], 3'd0 } :
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b_base__h929 ;
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assign x__h997 = memCap_address__h637 >> x__h1035 ;
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assign y__h1054 =
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{ impliedTopBits__h596,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18 } ;
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always@(checkForException_csrState)
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begin
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case (checkForException_csrState[10:9])
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2'd0: code__h2344 = 5'd8;
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2'd1: code__h2344 = 5'd9;
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2'd2: code__h2344 = 5'd2;
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2'd3: code__h2344 = 5'd11;
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endcase
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end
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always@(checkForException_dInst or
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NOT_checkForException_dInst_BITS_139_TO_137_02_ETC___d263 or
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d162 or
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checkForException_csrState)
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begin
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case (checkForException_dInst[144:140])
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5'd24:
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IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d268 =
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checkForException_csrState[10:9] != 2'd0 &&
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(checkForException_csrState[10:9] != 2'd1 ||
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!checkForException_csrState[6]);
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5'd25:
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IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d268 =
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checkForException_csrState[10:9] == 2'd3;
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default: IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d268 =
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checkForException_dInst[144:140] != 5'd21 &&
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((checkForException_dInst[144:140] == 5'd17) ?
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NOT_checkForException_dInst_BITS_139_TO_137_02_ETC___d263 :
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checkForException_dInst[38] &&
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!checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d162 &&
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checkForException_dInst[37:33] != 5'd10);
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endcase
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end
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always@(checkForException_dInst or
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IF_checkForException_dInst_BIT_38_60_THEN_chec_ETC___d193 or
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checkForException_dInst_BITS_139_TO_137_02_EQ__ETC___d159 or
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checkForException_csrState or checkForException_pcc)
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begin
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case (checkForException_dInst[144:140])
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5'd17:
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IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d197 =
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checkForException_dInst_BITS_139_TO_137_02_EQ__ETC___d159;
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5'd21:
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IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d197 =
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checkForException_csrState[10:9] == 2'd1 &&
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checkForException_csrState[8];
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|
5'd24:
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IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d197 =
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checkForException_csrState[10:9] == 2'd0 ||
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checkForException_csrState[10:9] == 2'd1 &&
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|
checkForException_csrState[6] ||
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|
!checkForException_pcc[122];
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|
5'd25:
|
|
IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d197 =
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checkForException_csrState[10:9] != 2'd3 ||
|
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!checkForException_pcc[122];
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default: IF_checkForException_dInst_BITS_144_TO_140_1_E_ETC___d197 =
|
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IF_checkForException_dInst_BIT_38_60_THEN_chec_ETC___d193;
|
|
endcase
|
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end
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always@(checkForException_dInst or code__h2344)
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begin
|
|
case (checkForException_dInst[144:140])
|
|
5'd22:
|
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CASE_checkForException_dInst_BITS_144_TO_140_2_ETC__q2 =
|
|
code__h2344;
|
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5'd23: CASE_checkForException_dInst_BITS_144_TO_140_2_ETC__q2 = 5'd3;
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default: CASE_checkForException_dInst_BITS_144_TO_140_2_ETC__q2 = 5'd2;
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endcase
|
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end
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endmodule // module_checkForException
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