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Toooba/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v
Jessica Clarke 72f49a1109 Regenerate verilog
2020-07-16 19:35:51 +01:00

10894 lines
455 KiB
Verilog
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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Thu Jul 16 18:36:00 BST 2020
//
//
// Ports:
// Name I/O size props
// execFpuSimple O 69
// execFpuSimple_fpu_inst I 9
// execFpuSimple_rVal1 I 64
// execFpuSimple_rVal2 I 64
//
// Combinational paths from inputs to outputs:
// (execFpuSimple_fpu_inst,
// execFpuSimple_rVal1,
// execFpuSimple_rVal2) -> execFpuSimple
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_rVal1,
execFpuSimple_rVal2,
execFpuSimple);
// value method execFpuSimple
input [8 : 0] execFpuSimple_fpu_inst;
input [63 : 0] execFpuSimple_rVal1;
input [63 : 0] execFpuSimple_rVal2;
output [68 : 0] execFpuSimple;
// signals for module outputs
wire [68 : 0] execFpuSimple;
// remaining internal signals
reg [63 : 0] IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838;
reg [51 : 0] CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_45_ETC__q5,
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q25,
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q26,
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q23,
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q24,
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q27,
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q28,
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q35,
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q36,
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q37,
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q38,
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q65,
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q66,
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q67,
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q68,
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q47,
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q48,
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q49,
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q50,
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q81,
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q82,
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q83,
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q84,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1130,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1148,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1553,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1571,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1774,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1789,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2083,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2098,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d844,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d871,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d890,
_theResult___snd_fst_sfd__h176702;
reg [30 : 0] IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600;
reg [22 : 0] CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_83_ETC__q3,
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q148,
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q149,
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q113,
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q114,
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q150,
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q151,
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q131,
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q132,
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q154,
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q155,
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q133,
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q134,
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q111,
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q112,
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q156,
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q157,
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q109,
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q110,
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q107,
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q108,
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q121,
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q122,
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q123,
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q124,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3739,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3758,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3785,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3804,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4068,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4086,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4229,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4247,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4433,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4448,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4567,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4582;
reg [10 : 0] CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q62,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q78,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_20_ETC__q4,
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q17,
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q18,
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q19,
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q20,
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q21,
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q22,
CASE_guard43753_0b0_0_0b1_0_0b10_out_exp44372__ETC__q32,
CASE_guard43753_0b0_0_0b1_theResult___exp44369_ETC__q31,
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_th_ETC__q33,
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_x4_ETC__q34,
CASE_guard53144_0b0_0_0b1_0_0b10_out_exp53763__ETC__q60,
CASE_guard53144_0b0_0_0b1_theResult___exp53760_ETC__q61,
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_th_ETC__q63,
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_x5_ETC__q64,
CASE_guard64377_0b0_0_0b1_0_0b10_out_exp64996__ETC__q44,
CASE_guard64377_0b0_0_0b1_theResult___exp64993_ETC__q43,
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_th_ETC__q45,
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_x6_ETC__q46,
CASE_guard75083_0b0_0_0b1_0_0b10_out_exp75702__ETC__q76,
CASE_guard75083_0b0_0_0b1_theResult___exp75699_ETC__q77,
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_th_ETC__q79,
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_x7_ETC__q80,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1056,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1103,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1478,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1525,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1751,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2059,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d413,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d743,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d812,
_theResult___snd_fst_exp__h176701;
reg [7 : 0] CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q145,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q75,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_25_ETC__q2,
CASE_guard2670_0b0_0_0b1_0_0b10_out_exp3086_0b_ETC__q143,
CASE_guard2670_0b0_0_0b1_theResult___exp3083_0_ETC__q144,
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q105,
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q106,
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_theRe_ETC__q146,
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_x3211_ETC__q147,
CASE_guard3497_0b0_0_0b1_0_0b10_out_exp3913_0b_ETC__q128,
CASE_guard3497_0b0_0_0b1_theResult___exp3910_0_ETC__q127,
CASE_guard3797_0b0_0_0b1_0_0b10_out_exp4213_0b_ETC__q73,
CASE_guard3797_0b0_0_0b1_theResult___exp4210_0_ETC__q74,
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_theRe_ETC__q129,
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_x4039_ETC__q130,
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q103,
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q104,
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_theRe_ETC__q152,
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_x4338_ETC__q153,
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q101,
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q102,
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q100,
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q99,
CASE_guard6815_0b0_0_0b1_0_0b10_out_exp7231_0b_ETC__q118,
CASE_guard6815_0b0_0_0b1_theResult___exp7228_0_ETC__q117,
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_theRe_ETC__q119,
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_x7357_ETC__q120,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3198,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3315,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3639,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3708,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3993,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4040,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4154,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4201,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4409,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4543;
reg CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q6,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q86,
CASE_guard08320_0b0_execFpuSimple_rVal1_BIT_31_ETC__q51,
CASE_guard17628_0b0_execFpuSimple_rVal1_BIT_31_ETC__q52,
CASE_guard26695_0b0_execFpuSimple_rVal1_BIT_31_ETC__q53,
CASE_guard2928_0b0_execFpuSimple_rVal1_BIT_63__ETC__q140,
CASE_guard3497_0b0_execFpuSimple_rVal1_BIT_63__ETC__q135,
CASE_guard4024_0b0_execFpuSimple_rVal1_BIT_63__ETC__q136,
CASE_guard4064_0b0_execFpuSimple_rVal1_BIT_63__ETC__q139,
CASE_guard43753_0b0_execFpuSimple_rVal1_BIT_31_ETC__q54,
CASE_guard44483_0b0_execFpuSimple_rVal1_BIT_31_ETC__q55,
CASE_guard5075_0b0_execFpuSimple_rVal1_BIT_63__ETC__q138,
CASE_guard6338_0b0_execFpuSimple_rVal1_BIT_63__ETC__q137,
CASE_guard64377_0b0_execFpuSimple_rVal1_BIT_63_ETC__q56,
CASE_guard65107_0b0_execFpuSimple_rVal1_BIT_63_ETC__q57,
CASE_guard6815_0b0_execFpuSimple_rVal1_BIT_31__ETC__q125,
CASE_guard7342_0b0_execFpuSimple_rVal1_BIT_31__ETC__q126,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1161,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1168,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1586,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1593,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3820,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3828,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3838,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3846,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4098,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4105,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4259,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4266,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d912,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d920,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d928,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690;
wire [117 : 0] int_val__h94407,
int_val__h94408,
shifted__h94440,
shifted_out_mask__h96300,
x__h94673,
x__h96545,
x__h96568,
y__h94627,
y__h94722;
wire [115 : 0] int_val_rnd__h94412;
wire [88 : 0] int_val__h5743,
int_val__h5744,
shifted__h5776,
shifted_out_mask__h5777,
x__h5981,
x__h5994,
x__h6017,
y__h5935,
y__h6030;
wire [86 : 0] int_val_rnd__h5748;
wire [63 : 0] IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2693,
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2711,
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2714,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2186,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4603,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d67,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d78,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178,
_theResult_____1_fst__h6884,
_theResult_____1_fst__h8071,
_theResult_____1_fst__h95556,
_theResult_____1_fst__h96799,
_theResult___fst__h5722,
_theResult___fst__h5738,
_theResult___fst__h5753,
_theResult___fst__h6366,
_theResult___fst__h6381,
_theResult___fst__h6963,
_theResult___fst__h6979,
_theResult___fst__h6994,
_theResult___fst__h7553,
_theResult___fst__h7568,
_theResult___fst__h94386,
_theResult___fst__h94402,
_theResult___fst__h94417,
_theResult___fst__h95010,
_theResult___fst__h95025,
_theResult___fst__h95635,
_theResult___fst__h95651,
_theResult___fst__h95666,
_theResult___fst__h96253,
_theResult___fst__h96268,
dst_bits__h251,
dst_bits__h256,
dst_bits__h261,
dst_bits__h266,
dst_bits__h85486,
dst_bits__h85491,
dst_bits__h85496,
dst_bits__h85501,
max_val__h7005,
max_val__h95677,
out__h5724,
out__h6306,
out__h6311,
out__h6368,
out__h6900,
out__h6965,
out__h7498,
out__h94388,
out__h94950,
out__h94955,
out__h95012,
out__h95572,
out__h95637,
out__h96198,
sfd___3__h164367,
sfd___3__h175073,
x__h219,
x__h224,
x__h4245,
x__h4413,
x__h4568,
x__h85464,
x__h85469;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_ETC__q88,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimpl_ETC__q12,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimpl_ETC__q94,
IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q15,
IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q8,
IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q90,
IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q97,
_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_30_TO__ETC___d436,
_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_62_TO__ETC___d3334,
_theResult____h117618,
_theResult____h16328,
_theResult____h34054,
_theResult___snd__h116232,
_theResult___snd__h116234,
_theResult___snd__h116241,
_theResult___snd__h116247,
_theResult___snd__h116270,
_theResult___snd__h125865,
_theResult___snd__h125876,
_theResult___snd__h125878,
_theResult___snd__h125888,
_theResult___snd__h125894,
_theResult___snd__h125917,
_theResult___snd__h134631,
_theResult___snd__h134645,
_theResult___snd__h134651,
_theResult___snd__h134669,
_theResult___snd__h24448,
_theResult___snd__h24459,
_theResult___snd__h24461,
_theResult___snd__h24471,
_theResult___snd__h24477,
_theResult___snd__h24500,
_theResult___snd__h33074,
_theResult___snd__h33076,
_theResult___snd__h33083,
_theResult___snd__h33089,
_theResult___snd__h33112,
_theResult___snd__h42301,
_theResult___snd__h42312,
_theResult___snd__h42314,
_theResult___snd__h42324,
_theResult___snd__h42330,
_theResult___snd__h42353,
_theResult___snd__h50951,
_theResult___snd__h50965,
_theResult___snd__h50971,
_theResult___snd__h50989,
result__h118231,
result__h34667,
sfd__h8697,
sfd__h97423,
sfdin__h125848,
sfdin__h24431,
sfdin__h42284,
x__h118326,
x__h34762;
wire [54 : 0] sfd___3__h143743,
sfd___3__h153134,
sfd__h135742,
sfd__h145382;
wire [53 : 0] sfd__h116299,
sfd__h125946,
sfd__h134704,
sfd__h143770,
sfd__h144513,
sfd__h153161,
sfd__h153903,
sfd__h164394,
sfd__h165137,
sfd__h175100,
sfd__h175842,
value__h16950;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d865,
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d867,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d838,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d840,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d884,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d886,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1124,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1126,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1142,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1144,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1547,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1549,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1565,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1567,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102,
_theResult___fst_sfd__h101209,
_theResult___fst_sfd__h117035,
_theResult___fst_sfd__h117038,
_theResult___fst_sfd__h126682,
_theResult___fst_sfd__h126685,
_theResult___fst_sfd__h135464,
_theResult___fst_sfd__h135467,
_theResult___fst_sfd__h135476,
_theResult___fst_sfd__h135482,
_theResult___fst_sfd__h144467,
_theResult___fst_sfd__h145223,
_theResult___fst_sfd__h145226,
_theResult___fst_sfd__h153857,
_theResult___fst_sfd__h154612,
_theResult___fst_sfd__h154615,
_theResult___fst_sfd__h165091,
_theResult___fst_sfd__h165847,
_theResult___fst_sfd__h165850,
_theResult___fst_sfd__h175796,
_theResult___fst_sfd__h176551,
_theResult___fst_sfd__h176554,
_theResult___sfd__h116937,
_theResult___sfd__h126584,
_theResult___sfd__h135366,
_theResult___sfd__h144370,
_theResult___sfd__h145126,
_theResult___sfd__h153761,
_theResult___sfd__h154516,
_theResult___sfd__h164994,
_theResult___sfd__h165750,
_theResult___sfd__h175700,
_theResult___sfd__h176455,
_theResult___snd_fst_sfd__h117041,
_theResult___snd_fst_sfd__h135470,
_theResult___snd_fst_sfd__h145229,
_theResult___snd_fst_sfd__h154618,
_theResult___snd_fst_sfd__h165853,
_theResult___snd_fst_sfd__h176557,
_theResult___snd_fst_sfd__h97377,
_theResult___snd_sfd__h135723,
_theResult___snd_sfd__h145369,
_theResult___snd_sfd__h154746,
_theResult___snd_sfd__h165993,
_theResult___snd_sfd__h176685,
_theResult___snd_sfd__h96909,
_theResult___snd_sfd__h96969,
_theResult___snd_sfd__h97029,
dst_sfd__h96906,
dst_sfd__h96966,
dst_sfd__h97026,
out___1_sfd__h97126,
out_sfd__h116940,
out_sfd__h126587,
out_sfd__h135369,
out_sfd__h144373,
out_sfd__h145129,
out_sfd__h153764,
out_sfd__h154519,
out_sfd__h164997,
out_sfd__h165753,
out_sfd__h175703,
out_sfd__h176458;
wire [31 : 0] IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2643,
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2656,
IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2644,
IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2657,
execFpuSimple_rVal1_BITS_31_TO_0__q158,
int_val_rnd4412_BITS_31_TO_0__q7,
int_val_rnd748_BITS_31_TO_0__q87,
max_val__h5764,
max_val__h94428,
sfd___3__h56805,
sfd___3__h62660,
val__h6305,
val__h94949,
value__h136325,
x__h4067,
x__h4081,
x__h8101;
wire [30 : 0] IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625,
IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630;
wire [24 : 0] sfd__h24529,
sfd__h33141,
sfd__h42382,
sfd__h51024,
sfd__h56832,
sfd__h57372,
sfd__h62687,
sfd__h63226,
sfd__h73514,
sfd__h74054,
sfd__h83814,
sfd__h84353,
value__h101838;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3733,
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3735,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3779,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3781,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3752,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3754,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3798,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3800,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4062,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4064,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4080,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4082,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4223,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4225,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4241,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4243,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586,
_theResult___fst_sfd__h16311,
_theResult___fst_sfd__h25062,
_theResult___fst_sfd__h25065,
_theResult___fst_sfd__h33674,
_theResult___fst_sfd__h33677,
_theResult___fst_sfd__h42915,
_theResult___fst_sfd__h42918,
_theResult___fst_sfd__h51581,
_theResult___fst_sfd__h51584,
_theResult___fst_sfd__h51593,
_theResult___fst_sfd__h51599,
_theResult___fst_sfd__h57326,
_theResult___fst_sfd__h57879,
_theResult___fst_sfd__h57882,
_theResult___fst_sfd__h63180,
_theResult___fst_sfd__h63732,
_theResult___fst_sfd__h63735,
_theResult___fst_sfd__h74008,
_theResult___fst_sfd__h74561,
_theResult___fst_sfd__h74564,
_theResult___fst_sfd__h84307,
_theResult___fst_sfd__h84859,
_theResult___fst_sfd__h84862,
_theResult___sfd__h24964,
_theResult___sfd__h33576,
_theResult___sfd__h42817,
_theResult___sfd__h51483,
_theResult___sfd__h57229,
_theResult___sfd__h57782,
_theResult___sfd__h63084,
_theResult___sfd__h63636,
_theResult___sfd__h73911,
_theResult___sfd__h74464,
_theResult___sfd__h84211,
_theResult___sfd__h84763,
_theResult___snd_fst_sfd__h33680,
_theResult___snd_fst_sfd__h51587,
_theResult___snd_fst_sfd__h57885,
_theResult___snd_fst_sfd__h63738,
_theResult___snd_fst_sfd__h74567,
_theResult___snd_fst_sfd__h84865,
_theResult___snd_fst_sfd__h8651,
_theResult___snd_sfd__h51882,
in1_sfd__h4124,
in2_sfd__h4199,
out_sfd__h24967,
out_sfd__h33579,
out_sfd__h42820,
out_sfd__h51486,
out_sfd__h57232,
out_sfd__h57785,
out_sfd__h63087,
out_sfd__h63639,
out_sfd__h73914,
out_sfd__h74467,
out_sfd__h84214,
out_sfd__h84766;
wire [16 : 0] _1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115,
amt_abs__h96298;
wire [12 : 0] _150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746,
amt_abs__h5775;
wire [11 : 0] IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d752,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q11,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2898,
_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669,
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d276,
_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979,
x__h118359,
x__h144498,
x__h153888,
x__h165122,
x__h175827,
x__h34795;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d737,
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d739,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d407,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d409,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d806,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d808,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1053,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1097,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1099,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1475,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1519,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1521,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q14,
_theResult___exp__h116936,
_theResult___exp__h126583,
_theResult___exp__h135365,
_theResult___exp__h144369,
_theResult___exp__h145125,
_theResult___exp__h153760,
_theResult___exp__h154515,
_theResult___exp__h164993,
_theResult___exp__h165749,
_theResult___exp__h175699,
_theResult___exp__h176454,
_theResult___fst_exp__h101208,
_theResult___fst_exp__h116272,
_theResult___fst_exp__h116278,
_theResult___fst_exp__h116281,
_theResult___fst_exp__h117034,
_theResult___fst_exp__h117037,
_theResult___fst_exp__h125854,
_theResult___fst_exp__h125919,
_theResult___fst_exp__h125925,
_theResult___fst_exp__h125928,
_theResult___fst_exp__h126681,
_theResult___fst_exp__h126684,
_theResult___fst_exp__h134637,
_theResult___fst_exp__h134676,
_theResult___fst_exp__h134682,
_theResult___fst_exp__h134685,
_theResult___fst_exp__h135463,
_theResult___fst_exp__h135466,
_theResult___fst_exp__h135475,
_theResult___fst_exp__h135478,
_theResult___fst_exp__h144466,
_theResult___fst_exp__h145222,
_theResult___fst_exp__h145225,
_theResult___fst_exp__h153856,
_theResult___fst_exp__h154611,
_theResult___fst_exp__h154614,
_theResult___fst_exp__h165090,
_theResult___fst_exp__h165846,
_theResult___fst_exp__h165849,
_theResult___fst_exp__h175795,
_theResult___fst_exp__h176550,
_theResult___fst_exp__h176553,
_theResult___snd_exp__h135722,
_theResult___snd_exp__h145368,
_theResult___snd_exp__h154745,
_theResult___snd_exp__h165992,
_theResult___snd_exp__h176684,
_theResult___snd_fst_exp__h117040,
_theResult___snd_fst_exp__h135469,
_theResult___snd_fst_exp__h145228,
_theResult___snd_fst_exp__h145231,
_theResult___snd_fst_exp__h145234,
_theResult___snd_fst_exp__h154617,
_theResult___snd_fst_exp__h154620,
_theResult___snd_fst_exp__h154623,
_theResult___snd_fst_exp__h165852,
_theResult___snd_fst_exp__h165855,
_theResult___snd_fst_exp__h165858,
_theResult___snd_fst_exp__h176556,
_theResult___snd_fst_exp__h176559,
_theResult___snd_fst_exp__h176562,
din_inc___2_exp__h135501,
din_inc___2_exp__h135531,
din_inc___2_exp__h135555,
din_inc___2_exp__h145267,
din_inc___2_exp__h154653,
din_inc___2_exp__h165891,
din_inc___2_exp__h176592,
execFpuSimple_rVal1_BITS_62_TO_52_MINUS_1023__q92,
out_exp__h116939,
out_exp__h126586,
out_exp__h135368,
out_exp__h144372,
out_exp__h145128,
out_exp__h153763,
out_exp__h154518,
out_exp__h164996,
out_exp__h165752,
out_exp__h175702,
out_exp__h176457;
wire [9 : 0] IF_execFpuSimple_rVal1_BITS_63_TO_32_EQ_0xFFFF_ETC__q85,
IF_execFpuSimple_rVal1_BIT_63_AND_execFpuSimpl_ETC__q1,
x__h4812,
x__h93102;
wire [8 : 0] IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3648,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464,
x__h57357,
x__h63211,
x__h74039,
x__h84338;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3192,
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3194,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3309,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3311,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d3990,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4034,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4036,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4151,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4195,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4197,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q96,
_theResult___exp__h24963,
_theResult___exp__h33575,
_theResult___exp__h42816,
_theResult___exp__h51482,
_theResult___exp__h57228,
_theResult___exp__h57781,
_theResult___exp__h63083,
_theResult___exp__h63635,
_theResult___exp__h73910,
_theResult___exp__h74463,
_theResult___exp__h84210,
_theResult___exp__h84762,
_theResult___fst_exp__h16310,
_theResult___fst_exp__h24437,
_theResult___fst_exp__h24502,
_theResult___fst_exp__h24508,
_theResult___fst_exp__h24511,
_theResult___fst_exp__h25061,
_theResult___fst_exp__h25064,
_theResult___fst_exp__h33114,
_theResult___fst_exp__h33120,
_theResult___fst_exp__h33123,
_theResult___fst_exp__h33673,
_theResult___fst_exp__h33676,
_theResult___fst_exp__h42290,
_theResult___fst_exp__h42355,
_theResult___fst_exp__h42361,
_theResult___fst_exp__h42364,
_theResult___fst_exp__h42914,
_theResult___fst_exp__h42917,
_theResult___fst_exp__h50957,
_theResult___fst_exp__h50996,
_theResult___fst_exp__h51002,
_theResult___fst_exp__h51005,
_theResult___fst_exp__h51580,
_theResult___fst_exp__h51583,
_theResult___fst_exp__h51592,
_theResult___fst_exp__h51595,
_theResult___fst_exp__h57325,
_theResult___fst_exp__h57878,
_theResult___fst_exp__h57881,
_theResult___fst_exp__h63179,
_theResult___fst_exp__h63731,
_theResult___fst_exp__h63734,
_theResult___fst_exp__h74007,
_theResult___fst_exp__h74560,
_theResult___fst_exp__h74563,
_theResult___fst_exp__h84306,
_theResult___fst_exp__h84858,
_theResult___fst_exp__h84861,
_theResult___snd_exp__h51881,
_theResult___snd_fst_exp__h33679,
_theResult___snd_fst_exp__h51586,
_theResult___snd_fst_exp__h57884,
_theResult___snd_fst_exp__h57887,
_theResult___snd_fst_exp__h57890,
_theResult___snd_fst_exp__h63737,
_theResult___snd_fst_exp__h63740,
_theResult___snd_fst_exp__h63743,
_theResult___snd_fst_exp__h74566,
_theResult___snd_fst_exp__h74569,
_theResult___snd_fst_exp__h74572,
_theResult___snd_fst_exp__h84864,
_theResult___snd_fst_exp__h84867,
_theResult___snd_fst_exp__h84870,
din_inc___2_exp__h51614,
din_inc___2_exp__h51638,
din_inc___2_exp__h51668,
din_inc___2_exp__h51692,
din_inc___2_exp__h57923,
din_inc___2_exp__h63773,
din_inc___2_exp__h74605,
din_inc___2_exp__h84900,
execFpuSimple_rVal1_BITS_30_TO_23_MINUS_127__q10,
in1_exp__h4123,
in2_exp__h4198,
out_exp__h24966,
out_exp__h33578,
out_exp__h42819,
out_exp__h51485,
out_exp__h57231,
out_exp__h57784,
out_exp__h63086,
out_exp__h63638,
out_exp__h73913,
out_exp__h74466,
out_exp__h84213,
out_exp__h84765;
wire [6 : 0] IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133,
IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678,
IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574,
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d1011,
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d3949,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d1666,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d4326;
wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638;
wire [1 : 0] IF_sfd___32660_BIT_7_THEN_2_ELSE_0__q142,
IF_sfd___32660_BIT_8_THEN_2_ELSE_0__q141,
IF_sfd___343743_BIT_1_THEN_2_ELSE_0__q30,
IF_sfd___343743_BIT_2_THEN_2_ELSE_0__q29,
IF_sfd___353134_BIT_1_THEN_2_ELSE_0__q59,
IF_sfd___353134_BIT_2_THEN_2_ELSE_0__q58,
IF_sfd___364367_BIT_10_THEN_2_ELSE_0__q42,
IF_sfd___364367_BIT_11_THEN_2_ELSE_0__q41,
IF_sfd___364367_BIT_39_THEN_2_ELSE_0__q40,
IF_sfd___364367_BIT_40_THEN_2_ELSE_0__q39,
IF_sfd___36805_BIT_7_THEN_2_ELSE_0__q116,
IF_sfd___36805_BIT_8_THEN_2_ELSE_0__q115,
IF_sfd___375073_BIT_10_THEN_2_ELSE_0__q72,
IF_sfd___375073_BIT_11_THEN_2_ELSE_0__q71,
IF_sfd___375073_BIT_39_THEN_2_ELSE_0__q70,
IF_sfd___375073_BIT_40_THEN_2_ELSE_0__q69,
IF_sfdin2284_BIT_33_THEN_2_ELSE_0__q95,
IF_sfdin25848_BIT_4_THEN_2_ELSE_0__q13,
IF_sfdin4431_BIT_33_THEN_2_ELSE_0__q89,
IF_theResult___snd0951_BIT_33_THEN_2_ELSE_0__q98,
IF_theResult___snd16232_BIT_4_THEN_2_ELSE_0__q9,
IF_theResult___snd3074_BIT_33_THEN_2_ELSE_0__q91,
IF_theResult___snd34631_BIT_4_THEN_2_ELSE_0__q16,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2735,
guard__h108320,
guard__h117628,
guard__h126695,
guard__h143753,
guard__h144483,
guard__h153144,
guard__h153873,
guard__h16338,
guard__h164377,
guard__h165107,
guard__h175083,
guard__h175812,
guard__h25075,
guard__h34064,
guard__h42928,
guard__h56815,
guard__h57342,
guard__h62670,
guard__h63196,
guard__h73497,
guard__h74024,
guard__h83797,
guard__h84323;
wire IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175,
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198,
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792,
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815,
IF_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1__ETC___d3831,
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1171,
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2551,
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4108,
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4883,
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2559,
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4892,
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1596,
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2567,
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4269,
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4901,
IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2576,
IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4910,
IF_NOT_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_r_ETC___d1172,
IF_NOT_3970_MINUS_0_CONCAT_IF_execFpuSimple_rV_ETC___d914,
IF_NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_N_ETC___d4109,
IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2705,
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2292,
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2483,
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2520,
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d931,
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3849,
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4713,
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4812,
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4852,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1162,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1169,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1587,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1594,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d164,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2781,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3821,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3829,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3839,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3847,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4099,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4106,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4260,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4267,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d913,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d921,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d929,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2470,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2507,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4798,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4838,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d1601,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4274,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2277,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2294,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2485,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d933,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d1621,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3851,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4659,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4698,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4715,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4814,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4854,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d4286,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2686,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2690,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2804,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4607,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4612,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4667,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4677,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4886,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2387,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2494,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2570,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4778,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4825,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4904,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NOT_execF_ETC___d2157,
NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4707,
NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4848,
NOT_IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_ETC___d935,
NOT_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ__ETC___d3853,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2685,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2708,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4670,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4680,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4863,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4869,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4873,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4878,
NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915,
NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d1536,
NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d4212,
NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d1599,
NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d4272,
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4759,
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4769,
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4820,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9_ETC___d2160,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2541,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2546,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_ex_ETC___d2139,
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322,
NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878,
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899,
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d2069,
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d4553,
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_execFpu_ETC___d76,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d3135,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d680,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d3576,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d351,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d753,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3257,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3649,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4641,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4694,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4808,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332,
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277,
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683,
execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_OR_ETC___d4052,
execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129,
execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134,
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2192,
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2198,
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127,
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126,
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2138,
execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2636,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2640,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2653,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2688,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2707,
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418,
execFpuSimple_rVal1_BIT_31_05_OR_execFpuSimple_ETC___d4895,
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439,
execFpuSimple_rVal1_BIT_63_4_AND_NOT_execFpuSi_ETC___d65,
execFpuSimple_rVal1_BIT_63_4_EQ_execFpuSimple__ETC___d58,
execFpuSimple_rVal1_BIT_63_4_OR_NOT_execFpuSim_ETC___d2141,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2460,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2497,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4788,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4828,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4913,
guard__h118226,
guard__h34662,
saturated_bit__h5778,
saturated_bit__h94442,
x__h176711,
x__h176838,
x__h176960,
x__h4248,
x__h4416,
x__h4571;
// value method execFpuSimple
assign execFpuSimple =
execFpuSimple_fpu_inst[0] ?
{ IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2186,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270,
execFpuSimple_fpu_inst[8:4] == 5'd10 &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2277,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2470,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2507,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 } :
{ IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4603,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690,
execFpuSimple_fpu_inst[8:4] == 5'd10 &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4698,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4798,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4838,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 } ;
// remaining internal signals
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_ETC__q88 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d3135 ?
_theResult___snd__h24500 :
_theResult____h16328 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimpl_ETC__q12 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d680 ?
_theResult___snd__h125917 :
_theResult____h117618 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimpl_ETC__q94 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d3576 ?
_theResult___snd__h42353 :
_theResult____h34054 ;
assign IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q15 =
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d753 ?
_theResult___snd__h116270 :
_theResult___snd__h134669 ;
assign IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q8 =
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d351 ?
_theResult___snd__h116270 :
57'd0 ;
assign IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q90 =
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3257 ?
_theResult___snd__h33112 :
57'd0 ;
assign IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q97 =
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3649 ?
_theResult___snd__h33112 :
_theResult___snd__h50989 ;
assign IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175 =
int_val_rnd__h94412[31:0] <= max_val__h94428 ;
assign IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198 =
int_val_rnd__h94412[63:0] <= max_val__h95677 ;
assign IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792 =
int_val_rnd__h5748[31:0] <= max_val__h5764 ;
assign IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815 =
int_val_rnd__h5748[63:0] <= max_val__h7005 ;
assign IF_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1__ETC___d3831 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
((_theResult___fst_exp__h24437 == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3821) :
((_theResult___fst_exp__h33123 == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3829) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1171 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 ?
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1162 :
((x__h144498[10:0] == 11'd2047) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1169) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2551 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 ?
guard__h143753 != 2'b0 :
x__h144498[10:0] != 11'd2047 && guard__h144483 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4108 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 ?
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4099 :
((x__h57357[7:0] == 8'd255) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4106) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4883 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 ?
guard__h56815 != 2'b0 :
x__h57357[7:0] != 8'd255 && guard__h57342 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2559 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 ?
guard__h153144 != 2'b0 :
x__h153888[10:0] != 11'd2047 && guard__h153873 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4892 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 ?
guard__h62670 != 2'b0 :
x__h63211[7:0] != 8'd255 && guard__h63196 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1596 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 ?
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1587 :
((x__h165122[10:0] == 11'd2047) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1594) ;
assign IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2567 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 ?
guard__h164377 != 2'b0 :
x__h165122[10:0] != 11'd2047 && guard__h165107 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4269 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 ?
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4260 :
((x__h74039[7:0] == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4267) ;
assign IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4901 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 ?
guard__h73497 != 2'b0 :
x__h74039[7:0] != 8'd255 && guard__h74024 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2576 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 ?
guard__h175083 != 2'b0 :
x__h175827[10:0] != 11'd2047 && guard__h175812 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4910 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 ?
guard__h83797 != 2'b0 :
x__h84338[7:0] != 8'd255 && guard__h84323 != 2'b0 ;
assign IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133 =
(_theResult____h16328[56] ?
6'd0 :
(_theResult____h16328[55] ?
6'd1 :
(_theResult____h16328[54] ?
6'd2 :
(_theResult____h16328[53] ?
6'd3 :
(_theResult____h16328[52] ?
6'd4 :
(_theResult____h16328[51] ?
6'd5 :
(_theResult____h16328[50] ?
6'd6 :
(_theResult____h16328[49] ?
6'd7 :
(_theResult____h16328[48] ?
6'd8 :
(_theResult____h16328[47] ?
6'd9 :
(_theResult____h16328[46] ?
6'd10 :
(_theResult____h16328[45] ?
6'd11 :
(_theResult____h16328[44] ?
6'd12 :
(_theResult____h16328[43] ?
6'd13 :
(_theResult____h16328[42] ?
6'd14 :
(_theResult____h16328[41] ?
6'd15 :
(_theResult____h16328[40] ?
6'd16 :
(_theResult____h16328[39] ?
6'd17 :
(_theResult____h16328[38] ?
6'd18 :
(_theResult____h16328[37] ?
6'd19 :
(_theResult____h16328[36] ?
6'd20 :
(_theResult____h16328[35] ?
6'd21 :
(_theResult____h16328[34] ?
6'd22 :
(_theResult____h16328[33] ?
6'd23 :
(_theResult____h16328[32] ?
6'd24 :
(_theResult____h16328[31] ?
6'd25 :
(_theResult____h16328[30] ?
6'd26 :
(_theResult____h16328[29] ?
6'd27 :
(_theResult____h16328[28] ?
6'd28 :
(_theResult____h16328[27] ?
6'd29 :
(_theResult____h16328[26] ?
6'd30 :
(_theResult____h16328[25] ?
6'd31 :
(_theResult____h16328[24] ?
6'd32 :
(_theResult____h16328[23] ?
6'd33 :
(_theResult____h16328[22] ?
6'd34 :
(_theResult____h16328[21] ?
6'd35 :
(_theResult____h16328[20] ?
6'd36 :
(_theResult____h16328[19] ?
6'd37 :
(_theResult____h16328[18] ?
6'd38 :
(_theResult____h16328[17] ?
6'd39 :
(_theResult____h16328[16] ?
6'd40 :
(_theResult____h16328[15] ?
6'd41 :
(_theResult____h16328[14] ?
6'd42 :
(_theResult____h16328[13] ?
6'd43 :
(_theResult____h16328[12] ?
6'd44 :
(_theResult____h16328[11] ?
6'd45 :
(_theResult____h16328[10] ?
6'd46 :
(_theResult____h16328[9] ?
6'd47 :
(_theResult____h16328[8] ?
6'd48 :
(_theResult____h16328[7] ?
6'd49 :
(_theResult____h16328[6] ?
6'd50 :
(_theResult____h16328[5] ?
6'd51 :
(_theResult____h16328[4] ?
6'd52 :
(_theResult____h16328[3] ?
6'd53 :
(_theResult____h16328[2] ?
6'd54 :
(_theResult____h16328[1] ?
6'd55 :
(_theResult____h16328[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678 =
(_theResult____h117618[56] ?
6'd0 :
(_theResult____h117618[55] ?
6'd1 :
(_theResult____h117618[54] ?
6'd2 :
(_theResult____h117618[53] ?
6'd3 :
(_theResult____h117618[52] ?
6'd4 :
(_theResult____h117618[51] ?
6'd5 :
(_theResult____h117618[50] ?
6'd6 :
(_theResult____h117618[49] ?
6'd7 :
(_theResult____h117618[48] ?
6'd8 :
(_theResult____h117618[47] ?
6'd9 :
(_theResult____h117618[46] ?
6'd10 :
(_theResult____h117618[45] ?
6'd11 :
(_theResult____h117618[44] ?
6'd12 :
(_theResult____h117618[43] ?
6'd13 :
(_theResult____h117618[42] ?
6'd14 :
(_theResult____h117618[41] ?
6'd15 :
(_theResult____h117618[40] ?
6'd16 :
(_theResult____h117618[39] ?
6'd17 :
(_theResult____h117618[38] ?
6'd18 :
(_theResult____h117618[37] ?
6'd19 :
(_theResult____h117618[36] ?
6'd20 :
(_theResult____h117618[35] ?
6'd21 :
(_theResult____h117618[34] ?
6'd22 :
(_theResult____h117618[33] ?
6'd23 :
(_theResult____h117618[32] ?
6'd24 :
(_theResult____h117618[31] ?
6'd25 :
(_theResult____h117618[30] ?
6'd26 :
(_theResult____h117618[29] ?
6'd27 :
(_theResult____h117618[28] ?
6'd28 :
(_theResult____h117618[27] ?
6'd29 :
(_theResult____h117618[26] ?
6'd30 :
(_theResult____h117618[25] ?
6'd31 :
(_theResult____h117618[24] ?
6'd32 :
(_theResult____h117618[23] ?
6'd33 :
(_theResult____h117618[22] ?
6'd34 :
(_theResult____h117618[21] ?
6'd35 :
(_theResult____h117618[20] ?
6'd36 :
(_theResult____h117618[19] ?
6'd37 :
(_theResult____h117618[18] ?
6'd38 :
(_theResult____h117618[17] ?
6'd39 :
(_theResult____h117618[16] ?
6'd40 :
(_theResult____h117618[15] ?
6'd41 :
(_theResult____h117618[14] ?
6'd42 :
(_theResult____h117618[13] ?
6'd43 :
(_theResult____h117618[12] ?
6'd44 :
(_theResult____h117618[11] ?
6'd45 :
(_theResult____h117618[10] ?
6'd46 :
(_theResult____h117618[9] ?
6'd47 :
(_theResult____h117618[8] ?
6'd48 :
(_theResult____h117618[7] ?
6'd49 :
(_theResult____h117618[6] ?
6'd50 :
(_theResult____h117618[5] ?
6'd51 :
(_theResult____h117618[4] ?
6'd52 :
(_theResult____h117618[3] ?
6'd53 :
(_theResult____h117618[2] ?
6'd54 :
(_theResult____h117618[1] ?
6'd55 :
(_theResult____h117618[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574 =
(_theResult____h34054[56] ?
6'd0 :
(_theResult____h34054[55] ?
6'd1 :
(_theResult____h34054[54] ?
6'd2 :
(_theResult____h34054[53] ?
6'd3 :
(_theResult____h34054[52] ?
6'd4 :
(_theResult____h34054[51] ?
6'd5 :
(_theResult____h34054[50] ?
6'd6 :
(_theResult____h34054[49] ?
6'd7 :
(_theResult____h34054[48] ?
6'd8 :
(_theResult____h34054[47] ?
6'd9 :
(_theResult____h34054[46] ?
6'd10 :
(_theResult____h34054[45] ?
6'd11 :
(_theResult____h34054[44] ?
6'd12 :
(_theResult____h34054[43] ?
6'd13 :
(_theResult____h34054[42] ?
6'd14 :
(_theResult____h34054[41] ?
6'd15 :
(_theResult____h34054[40] ?
6'd16 :
(_theResult____h34054[39] ?
6'd17 :
(_theResult____h34054[38] ?
6'd18 :
(_theResult____h34054[37] ?
6'd19 :
(_theResult____h34054[36] ?
6'd20 :
(_theResult____h34054[35] ?
6'd21 :
(_theResult____h34054[34] ?
6'd22 :
(_theResult____h34054[33] ?
6'd23 :
(_theResult____h34054[32] ?
6'd24 :
(_theResult____h34054[31] ?
6'd25 :
(_theResult____h34054[30] ?
6'd26 :
(_theResult____h34054[29] ?
6'd27 :
(_theResult____h34054[28] ?
6'd28 :
(_theResult____h34054[27] ?
6'd29 :
(_theResult____h34054[26] ?
6'd30 :
(_theResult____h34054[25] ?
6'd31 :
(_theResult____h34054[24] ?
6'd32 :
(_theResult____h34054[23] ?
6'd33 :
(_theResult____h34054[22] ?
6'd34 :
(_theResult____h34054[21] ?
6'd35 :
(_theResult____h34054[20] ?
6'd36 :
(_theResult____h34054[19] ?
6'd37 :
(_theResult____h34054[18] ?
6'd38 :
(_theResult____h34054[17] ?
6'd39 :
(_theResult____h34054[16] ?
6'd40 :
(_theResult____h34054[15] ?
6'd41 :
(_theResult____h34054[14] ?
6'd42 :
(_theResult____h34054[13] ?
6'd43 :
(_theResult____h34054[12] ?
6'd44 :
(_theResult____h34054[11] ?
6'd45 :
(_theResult____h34054[10] ?
6'd46 :
(_theResult____h34054[9] ?
6'd47 :
(_theResult____h34054[8] ?
6'd48 :
(_theResult____h34054[7] ?
6'd49 :
(_theResult____h34054[6] ?
6'd50 :
(_theResult____h34054[5] ?
6'd51 :
(_theResult____h34054[4] ?
6'd52 :
(_theResult____h34054[3] ?
6'd53 :
(_theResult____h34054[2] ?
6'd54 :
(_theResult____h34054[1] ?
6'd55 :
(_theResult____h34054[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3192 =
(guard__h16338 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___fst_exp__h24437 :
_theResult___exp__h24963 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3194 =
(guard__h16338 == 2'b0) ?
_theResult___fst_exp__h24437 :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h24963 :
_theResult___fst_exp__h24437) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3733 =
(guard__h16338 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfdin__h24431[56:34] :
_theResult___sfd__h24964 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3735 =
(guard__h16338 == 2'b0) ?
sfdin__h24431[56:34] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h24964 :
sfdin__h24431[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d737 =
(guard__h117628 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___fst_exp__h125854 :
_theResult___exp__h126583 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d739 =
(guard__h117628 == 2'b0) ?
_theResult___fst_exp__h125854 :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h126583 :
_theResult___fst_exp__h125854) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d865 =
(guard__h117628 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfdin__h125848[56:5] :
_theResult___sfd__h126584 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d867 =
(guard__h117628 == 2'b0) ?
sfdin__h125848[56:5] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h126584 :
sfdin__h125848[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633 =
(guard__h34064 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___fst_exp__h42290 :
_theResult___exp__h42816 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635 =
(guard__h34064 == 2'b0) ?
_theResult___fst_exp__h42290 :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h42816 :
_theResult___fst_exp__h42290) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3779 =
(guard__h34064 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfdin__h42284[56:34] :
_theResult___sfd__h42817 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3781 =
(guard__h34064 == 2'b0) ?
sfdin__h42284[56:34] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h42817 :
sfdin__h42284[56:34]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d407 =
(guard__h108320 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___fst_exp__h116281 :
_theResult___exp__h116936 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d409 =
(guard__h108320 == 2'b0) ?
_theResult___fst_exp__h116281 :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h116936 :
_theResult___fst_exp__h116281) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d806 =
(guard__h126695 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___fst_exp__h134685 :
_theResult___exp__h135365 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d808 =
(guard__h126695 == 2'b0) ?
_theResult___fst_exp__h134685 :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h135365 :
_theResult___fst_exp__h134685) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d838 =
(guard__h108320 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___snd__h116232[56:5] :
_theResult___sfd__h116937 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d840 =
(guard__h108320 == 2'b0) ?
_theResult___snd__h116232[56:5] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h116937 :
_theResult___snd__h116232[56:5]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d884 =
(guard__h126695 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___snd__h134631[56:5] :
_theResult___sfd__h135366 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d886 =
(guard__h126695 == 2'b0) ?
_theResult___snd__h134631[56:5] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h135366 :
_theResult___snd__h134631[56:5]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3309 =
(guard__h25075 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___fst_exp__h33123 :
_theResult___exp__h33575 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3311 =
(guard__h25075 == 2'b0) ?
_theResult___fst_exp__h33123 :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h33575 :
_theResult___fst_exp__h33123) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702 =
(guard__h42928 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___fst_exp__h51005 :
_theResult___exp__h51482 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704 =
(guard__h42928 == 2'b0) ?
_theResult___fst_exp__h51005 :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h51482 :
_theResult___fst_exp__h51005) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3752 =
(guard__h25075 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___snd__h33074[56:34] :
_theResult___sfd__h33576 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3754 =
(guard__h25075 == 2'b0) ?
_theResult___snd__h33074[56:34] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h33576 :
_theResult___snd__h33074[56:34]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3798 =
(guard__h42928 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___snd__h50951[56:34] :
_theResult___sfd__h51483 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3800 =
(guard__h42928 == 2'b0) ?
_theResult___snd__h50951[56:34] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h51483 :
_theResult___snd__h50951[56:34]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1053 =
(guard__h143753 == 2'b0) ?
11'd0 :
(execFpuSimple_rVal1[31] ? _theResult___exp__h144369 : 11'd0) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1097 =
(guard__h144483 == 2'b0 || execFpuSimple_rVal1[31]) ?
x__h144498[10:0] :
_theResult___exp__h145125 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1099 =
(guard__h144483 == 2'b0) ?
x__h144498[10:0] :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h145125 :
x__h144498[10:0]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1124 =
(guard__h143753 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfd___3__h143743[54:3] :
_theResult___sfd__h144370 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1126 =
(guard__h143753 == 2'b0) ?
sfd___3__h143743[54:3] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h144370 :
sfd___3__h143743[54:3]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1142 =
(guard__h144483 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfd___3__h143743[53:2] :
_theResult___sfd__h145126 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1144 =
(guard__h144483 == 2'b0) ?
sfd___3__h143743[53:2] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h145126 :
sfd___3__h143743[53:2]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d3990 =
(guard__h56815 == 2'b0) ?
8'd0 :
(execFpuSimple_rVal1[31] ? _theResult___exp__h57228 : 8'd0) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4034 =
(guard__h57342 == 2'b0 || execFpuSimple_rVal1[31]) ?
x__h57357[7:0] :
_theResult___exp__h57781 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4036 =
(guard__h57342 == 2'b0) ?
x__h57357[7:0] :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h57781 :
x__h57357[7:0]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4062 =
(guard__h56815 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfd___3__h56805[31:9] :
_theResult___sfd__h57229 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4064 =
(guard__h56815 == 2'b0) ?
sfd___3__h56805[31:9] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h57229 :
sfd___3__h56805[31:9]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4080 =
(guard__h57342 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfd___3__h56805[30:8] :
_theResult___sfd__h57782 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4082 =
(guard__h57342 == 2'b0) ?
sfd___3__h56805[30:8] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h57782 :
sfd___3__h56805[30:8]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1475 =
(guard__h164377 == 2'b0) ?
11'd0 :
(execFpuSimple_rVal1[63] ? _theResult___exp__h164993 : 11'd0) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1519 =
(guard__h165107 == 2'b0 || execFpuSimple_rVal1[63]) ?
x__h165122[10:0] :
_theResult___exp__h165749 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1521 =
(guard__h165107 == 2'b0) ?
x__h165122[10:0] :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h165749 :
x__h165122[10:0]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1547 =
(guard__h164377 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfd___3__h164367[63:12] :
_theResult___sfd__h164994 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1549 =
(guard__h164377 == 2'b0) ?
sfd___3__h164367[63:12] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h164994 :
sfd___3__h164367[63:12]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1565 =
(guard__h165107 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfd___3__h164367[62:11] :
_theResult___sfd__h165750 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1567 =
(guard__h165107 == 2'b0) ?
sfd___3__h164367[62:11] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h165750 :
sfd___3__h164367[62:11]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4151 =
(guard__h73497 == 2'b0) ?
8'd0 :
(execFpuSimple_rVal1[63] ? _theResult___exp__h73910 : 8'd0) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4195 =
(guard__h74024 == 2'b0 || execFpuSimple_rVal1[63]) ?
x__h74039[7:0] :
_theResult___exp__h74463 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4197 =
(guard__h74024 == 2'b0) ?
x__h74039[7:0] :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h74463 :
x__h74039[7:0]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4223 =
(guard__h73497 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfd___3__h164367[63:41] :
_theResult___sfd__h73911 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4225 =
(guard__h73497 == 2'b0) ?
sfd___3__h164367[63:41] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h73911 :
sfd___3__h164367[63:41]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4241 =
(guard__h74024 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfd___3__h164367[62:40] :
_theResult___sfd__h74464 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4243 =
(guard__h74024 == 2'b0) ?
sfd___3__h164367[62:40] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h74464 :
sfd___3__h164367[62:40]) ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2643 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
x__h4081 :
((execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
(execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31]) ||
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2640) ?
x__h4067 :
x__h4081) ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2656 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
x__h4081 :
(((execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31] ||
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2653) ?
x__h4067 :
x__h4081) ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2693 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
64'd0 :
x__h4245 ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2711 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
64'd0 :
x__h4413 ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2714 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
64'd0 :
x__h4568 ;
assign IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d1011 =
value__h136325[31] ?
6'd0 :
(value__h136325[30] ?
6'd1 :
(value__h136325[29] ?
6'd2 :
(value__h136325[28] ?
6'd3 :
(value__h136325[27] ?
6'd4 :
(value__h136325[26] ?
6'd5 :
(value__h136325[25] ?
6'd6 :
(value__h136325[24] ?
6'd7 :
(value__h136325[23] ?
6'd8 :
(value__h136325[22] ?
6'd9 :
(value__h136325[21] ?
6'd10 :
(value__h136325[20] ?
6'd11 :
(value__h136325[19] ?
6'd12 :
(value__h136325[18] ?
6'd13 :
(value__h136325[17] ?
6'd14 :
(value__h136325[16] ?
6'd15 :
(value__h136325[15] ?
6'd16 :
(value__h136325[14] ?
6'd17 :
(value__h136325[13] ?
6'd18 :
(value__h136325[12] ?
6'd19 :
(value__h136325[11] ?
6'd20 :
(value__h136325[10] ?
6'd21 :
(value__h136325[9] ?
6'd22 :
(value__h136325[8] ?
6'd23 :
(value__h136325[7] ?
6'd24 :
(value__h136325[6] ?
6'd25 :
(value__h136325[5] ?
6'd26 :
(value__h136325[4] ?
6'd27 :
(value__h136325[3] ?
6'd28 :
(value__h136325[2] ?
6'd29 :
(value__h136325[1] ?
6'd30 :
(value__h136325[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d3949 =
value__h136325[31] ?
6'd0 :
(value__h136325[30] ?
6'd1 :
(value__h136325[29] ?
6'd2 :
(value__h136325[28] ?
6'd3 :
(value__h136325[27] ?
6'd4 :
(value__h136325[26] ?
6'd5 :
(value__h136325[25] ?
6'd6 :
(value__h136325[24] ?
6'd7 :
(value__h136325[23] ?
6'd8 :
(value__h136325[22] ?
6'd9 :
(value__h136325[21] ?
6'd10 :
(value__h136325[20] ?
6'd11 :
(value__h136325[19] ?
6'd12 :
(value__h136325[18] ?
6'd13 :
(value__h136325[17] ?
6'd14 :
(value__h136325[16] ?
6'd15 :
(value__h136325[15] ?
6'd16 :
(value__h136325[14] ?
6'd17 :
(value__h136325[13] ?
6'd18 :
(value__h136325[12] ?
6'd19 :
(value__h136325[11] ?
6'd20 :
(value__h136325[10] ?
6'd21 :
(value__h136325[9] ?
6'd22 :
(value__h136325[8] ?
6'd23 :
(value__h136325[7] ?
6'd24 :
(value__h136325[6] ?
6'd25 :
(value__h136325[5] ?
6'd26 :
(value__h136325[4] ?
6'd27 :
(value__h136325[3] ?
6'd28 :
(value__h136325[2] ?
6'd29 :
(value__h136325[1] ?
6'd30 :
(value__h136325[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434 =
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ?
7'd0 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ?
7'd1 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ?
7'd2 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ?
7'd3 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ?
7'd4 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ?
7'd5 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ?
7'd6 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ?
7'd7 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ?
7'd8 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ?
7'd9 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ?
7'd10 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ?
7'd11 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ?
7'd12 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ?
7'd13 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ?
7'd14 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ?
7'd15 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ?
7'd16 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ?
7'd17 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ?
7'd18 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ?
7'd19 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ?
7'd20 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ?
7'd21 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ?
7'd22 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ?
7'd23 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ?
7'd24 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ?
7'd25 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ?
7'd26 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ?
7'd27 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ?
7'd28 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ?
7'd29 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ?
7'd30 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ?
7'd31 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ?
7'd32 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ?
7'd33 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ?
7'd34 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ?
7'd35 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ?
7'd36 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ?
7'd37 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ?
7'd38 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ?
7'd39 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ?
7'd40 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ?
7'd41 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ?
7'd42 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ?
7'd43 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ?
7'd44 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ?
7'd45 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ?
7'd46 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ?
7'd47 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ?
7'd48 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ?
7'd49 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ?
7'd50 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ?
7'd51 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ?
7'd52 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ?
7'd53 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ?
7'd54 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ?
7'd55 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ?
7'd56 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ?
7'd57 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ?
7'd58 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ?
7'd59 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ?
7'd60 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ?
7'd61 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ?
7'd62 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0] ?
7'd63 :
7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ;
assign IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2644 =
(in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
x__h4067 :
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2643 ;
assign IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2657 =
(in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
x__h4067 :
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2656 ;
assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_r_ETC___d1172 =
(!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 ||
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016) ?
execFpuSimple_rVal1[31] :
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1171 ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_execFpuSimple_rV_ETC___d914 =
(!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ||
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 ||
_theResult___fst_exp__h116281 == 11'd2047) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d913 ;
assign IF_NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_N_ETC___d4109 =
(!value__h136325[31] &&
NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 ||
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954) ?
execFpuSimple_rVal1[31] :
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4108 ;
assign IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2705 =
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) ?
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 &&
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677 :
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 &&
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2292 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[2] :
_theResult___fst_exp__h135466 == 11'd2047 &&
_theResult___fst_sfd__h135467 == 52'd0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2483 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[1] :
_theResult___fst_exp__h134685 == 11'd0 &&
guard__h126695 != 2'b0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2520 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[0] :
_theResult___fst_exp__h134685 != 11'd2047 &&
guard__h126695 != 2'b0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d752 =
((SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q11[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q14[10],
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q14 }) -
12'd3074 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d931 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
((_theResult___fst_exp__h125854 == 11'd2047) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d921) :
((_theResult___fst_exp__h134685 == 11'd2047) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d929) ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3648 =
((SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q96[7],
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q96 }) -
9'd386 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3849 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
((_theResult___fst_exp__h42290 == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3839) :
((_theResult___fst_exp__h51005 == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3847) ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4713 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[2] :
_theResult___fst_exp__h51583 == 8'd255 &&
_theResult___fst_sfd__h51584 == 23'd0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4812 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[1] :
_theResult___fst_exp__h51005 == 8'd0 && guard__h42928 != 2'b0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4852 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[0] :
_theResult___fst_exp__h51005 != 8'd255 &&
guard__h42928 != 2'b0 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1162 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard43753_0b0_execFpuSimple_rVal1_BIT_31_ETC__q54 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1161 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1169 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard44483_0b0_execFpuSimple_rVal1_BIT_31_ETC__q55 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1168 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1587 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard64377_0b0_execFpuSimple_rVal1_BIT_63_ETC__q56 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1586 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1594 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard65107_0b0_execFpuSimple_rVal1_BIT_63_ETC__q57 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1593 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d164 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
int_val__h94408[1:0] == 2'b11 ||
int_val__h94408[1:0] == 2'b10 && int_val__h94408[2] :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q6 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2781 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
int_val__h5744[1:0] == 2'b11 ||
int_val__h5744[1:0] == 2'b10 && int_val__h5744[2] :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q86 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3821 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard6338_0b0_execFpuSimple_rVal1_BIT_63__ETC__q137 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3820 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3829 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard5075_0b0_execFpuSimple_rVal1_BIT_63__ETC__q138 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3828 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3839 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard4064_0b0_execFpuSimple_rVal1_BIT_63__ETC__q139 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3838 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3847 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard2928_0b0_execFpuSimple_rVal1_BIT_63__ETC__q140 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3846 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4099 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard6815_0b0_execFpuSimple_rVal1_BIT_31__ETC__q125 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4098 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4106 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard7342_0b0_execFpuSimple_rVal1_BIT_31__ETC__q126 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4105 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4260 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard3497_0b0_execFpuSimple_rVal1_BIT_63__ETC__q135 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4259 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4267 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard4024_0b0_execFpuSimple_rVal1_BIT_63__ETC__q136 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4266 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d913 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard08320_0b0_execFpuSimple_rVal1_BIT_31_ETC__q51 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d912 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d921 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard17628_0b0_execFpuSimple_rVal1_BIT_31_ETC__q52 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d920 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d929 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard26695_0b0_execFpuSimple_rVal1_BIT_31_ETC__q53 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d928 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2470 =
(execFpuSimple_fpu_inst[8:4] == 5'd10) ?
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2294 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2507 =
(execFpuSimple_fpu_inst[8:4] == 5'd10) ?
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2485 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4798 =
(execFpuSimple_fpu_inst[8:4] == 5'd10) ?
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4715 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4838 =
(execFpuSimple_fpu_inst[8:4] == 5'd10) ?
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4814 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d1601 =
(execFpuSimple_fpu_inst[8:4] == 5'd15) ?
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 !=
11'd2047 ||
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 ==
52'd0) &&
execFpuSimple_rVal1[31:0] != 32'd0 &&
IF_NOT_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_r_ETC___d1172 :
execFpuSimple_fpu_inst[8:4] == 5'd17 &&
NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d1599 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4274 =
(execFpuSimple_fpu_inst[8:4] == 5'd15) ?
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046 !=
8'd255 ||
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 ==
23'd0) &&
execFpuSimple_rVal1[31:0] != 32'd0 &&
IF_NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_N_ETC___d4109 :
execFpuSimple_fpu_inst[8:4] == 5'd17 &&
NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d4272 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2186 =
(execFpuSimple_fpu_inst[8:4] == 5'd8 ||
execFpuSimple_fpu_inst[8:4] == 5'd9 ||
execFpuSimple_fpu_inst[8:4] == 5'd22 ||
execFpuSimple_fpu_inst[8:4] == 5'd23 ||
execFpuSimple_fpu_inst[8:4] == 5'd24 ||
execFpuSimple_fpu_inst[8:4] == 5'd11 ||
execFpuSimple_fpu_inst[8:4] == 5'd12 ||
execFpuSimple_fpu_inst[8:4] == 5'd13 ||
execFpuSimple_fpu_inst[8:4] == 5'd14) ?
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 :
{ execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607,
_theResult___snd_fst_exp__h176701,
_theResult___snd_fst_sfd__h176702 } ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4603 =
(execFpuSimple_fpu_inst[8:4] == 5'd8 ||
execFpuSimple_fpu_inst[8:4] == 5'd9 ||
execFpuSimple_fpu_inst[8:4] == 5'd19 ||
execFpuSimple_fpu_inst[8:4] == 5'd20 ||
execFpuSimple_fpu_inst[8:4] == 5'd21 ||
execFpuSimple_fpu_inst[8:4] == 5'd22 ||
execFpuSimple_fpu_inst[8:4] == 5'd23 ||
execFpuSimple_fpu_inst[8:4] == 5'd24 ||
execFpuSimple_fpu_inst[8:4] == 5'd11 ||
execFpuSimple_fpu_inst[8:4] == 5'd12 ||
execFpuSimple_fpu_inst[8:4] == 5'd13 ||
execFpuSimple_fpu_inst[8:4] == 5'd14) ?
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 :
{ 32'hFFFFFFFF, x__h8101 } ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 &&
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 &&
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[4] :
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 &&
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[4] ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2277 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 &&
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 &&
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[3] :
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 &&
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[3] ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2294 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ||
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 &&
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[2] :
!SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ||
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2292 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2485 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 &&
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 ||
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[1]) :
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 &&
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2483 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ||
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 &&
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[0] :
!SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ||
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2520 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 =
((execFpuSimple_rVal1[30:23] == 8'd0) ?
(execFpuSimple_rVal1[22] ?
6'd2 :
(execFpuSimple_rVal1[21] ?
6'd3 :
(execFpuSimple_rVal1[20] ?
6'd4 :
(execFpuSimple_rVal1[19] ?
6'd5 :
(execFpuSimple_rVal1[18] ?
6'd6 :
(execFpuSimple_rVal1[17] ?
6'd7 :
(execFpuSimple_rVal1[16] ?
6'd8 :
(execFpuSimple_rVal1[15] ?
6'd9 :
(execFpuSimple_rVal1[14] ?
6'd10 :
(execFpuSimple_rVal1[13] ?
6'd11 :
(execFpuSimple_rVal1[12] ?
6'd12 :
(execFpuSimple_rVal1[11] ?
6'd13 :
(execFpuSimple_rVal1[10] ?
6'd14 :
(execFpuSimple_rVal1[9] ?
6'd15 :
(execFpuSimple_rVal1[8] ?
6'd16 :
(execFpuSimple_rVal1[7] ?
6'd17 :
(execFpuSimple_rVal1[6] ?
6'd18 :
(execFpuSimple_rVal1[5] ?
6'd19 :
(execFpuSimple_rVal1[4] ?
6'd20 :
(execFpuSimple_rVal1[3] ?
6'd21 :
(execFpuSimple_rVal1[2] ?
6'd22 :
(execFpuSimple_rVal1[1] ?
6'd23 :
(execFpuSimple_rVal1[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d933 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_execFpuSimple_rV_ETC___d914 :
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ?
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d931 :
execFpuSimple_rVal1[31]) ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d1621 =
((execFpuSimple_rVal1[30:23] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h135478) ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 !=
52'd0 ||
execFpuSimple_rVal1[30:23] == 8'd255 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 =
(execFpuSimple_rVal1[30:23] == 8'd255 &&
execFpuSimple_rVal1[22:0] != 23'd0) ?
_theResult___snd_fst_sfd__h97377 :
_theResult___fst_sfd__h135482 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 =
(execFpuSimple_rVal1[31:0] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h145234 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 ||
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016) ?
52'd0 :
_theResult___snd_fst_sfd__h145229 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757 =
(execFpuSimple_rVal1[31:0] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h154623 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 ||
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671) ?
52'd0 :
_theResult___snd_fst_sfd__h154618 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!value__h136325[31] &&
NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915) ?
8'd0 :
_theResult___snd_fst_exp__h57890 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 =
execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_OR_ETC___d4052 ?
23'd0 :
_theResult___snd_fst_sfd__h57885 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!execFpuSimple_rVal1[31] &&
NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878) ?
8'd0 :
_theResult___snd_fst_exp__h63743 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!execFpuSimple_rVal1[31] &&
NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878 ||
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 ||
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331) ?
23'd0 :
_theResult___snd_fst_sfd__h63738 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 =
((execFpuSimple_rVal1[62:52] == 11'd0) ?
(execFpuSimple_rVal1[51] ?
6'd2 :
(execFpuSimple_rVal1[50] ?
6'd3 :
(execFpuSimple_rVal1[49] ?
6'd4 :
(execFpuSimple_rVal1[48] ?
6'd5 :
(execFpuSimple_rVal1[47] ?
6'd6 :
(execFpuSimple_rVal1[46] ?
6'd7 :
(execFpuSimple_rVal1[45] ?
6'd8 :
(execFpuSimple_rVal1[44] ?
6'd9 :
(execFpuSimple_rVal1[43] ?
6'd10 :
(execFpuSimple_rVal1[42] ?
6'd11 :
(execFpuSimple_rVal1[41] ?
6'd12 :
(execFpuSimple_rVal1[40] ?
6'd13 :
(execFpuSimple_rVal1[39] ?
6'd14 :
(execFpuSimple_rVal1[38] ?
6'd15 :
(execFpuSimple_rVal1[37] ?
6'd16 :
(execFpuSimple_rVal1[36] ?
6'd17 :
(execFpuSimple_rVal1[35] ?
6'd18 :
(execFpuSimple_rVal1[34] ?
6'd19 :
(execFpuSimple_rVal1[33] ?
6'd20 :
(execFpuSimple_rVal1[32] ?
6'd21 :
(execFpuSimple_rVal1[31] ?
6'd22 :
(execFpuSimple_rVal1[30] ?
6'd23 :
(execFpuSimple_rVal1[29] ?
6'd24 :
(execFpuSimple_rVal1[28] ?
6'd25 :
(execFpuSimple_rVal1[27] ?
6'd26 :
(execFpuSimple_rVal1[26] ?
6'd27 :
(execFpuSimple_rVal1[25] ?
6'd28 :
(execFpuSimple_rVal1[24] ?
6'd29 :
(execFpuSimple_rVal1[23] ?
6'd30 :
(execFpuSimple_rVal1[22] ?
6'd31 :
(execFpuSimple_rVal1[21] ?
6'd32 :
(execFpuSimple_rVal1[20] ?
6'd33 :
(execFpuSimple_rVal1[19] ?
6'd34 :
(execFpuSimple_rVal1[18] ?
6'd35 :
(execFpuSimple_rVal1[17] ?
6'd36 :
(execFpuSimple_rVal1[16] ?
6'd37 :
(execFpuSimple_rVal1[15] ?
6'd38 :
(execFpuSimple_rVal1[14] ?
6'd39 :
(execFpuSimple_rVal1[13] ?
6'd40 :
(execFpuSimple_rVal1[12] ?
6'd41 :
(execFpuSimple_rVal1[11] ?
6'd42 :
(execFpuSimple_rVal1[10] ?
6'd43 :
(execFpuSimple_rVal1[9] ?
6'd44 :
(execFpuSimple_rVal1[8] ?
6'd45 :
(execFpuSimple_rVal1[7] ?
6'd46 :
(execFpuSimple_rVal1[6] ?
6'd47 :
(execFpuSimple_rVal1[5] ?
6'd48 :
(execFpuSimple_rVal1[4] ?
6'd49 :
(execFpuSimple_rVal1[3] ?
6'd50 :
(execFpuSimple_rVal1[2] ?
6'd51 :
(execFpuSimple_rVal1[1] ?
6'd52 :
(execFpuSimple_rVal1[0] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3851 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ?
IF_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1__ETC___d3831 :
execFpuSimple_rVal1[63]) :
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ?
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3849 :
execFpuSimple_rVal1[63]) ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4659 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4641 :
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 &&
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[4] ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4698 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4694 :
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 &&
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[3] ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4715 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4707 :
!SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ||
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4713 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4814 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4808 :
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 &&
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4812 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4854 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4848 :
!SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ||
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4852 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
_theResult___snd_fst_sfd__h8651 :
_theResult___fst_sfd__h51599 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d4286 =
((execFpuSimple_rVal1[62:52] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h51595) ==
8'd255 &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 !=
23'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d67 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
execFpuSimple_rVal2 :
(execFpuSimple_rVal1_BIT_63_4_AND_NOT_execFpuSi_ETC___d65 ?
execFpuSimple_rVal1 :
execFpuSimple_rVal2) ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d78 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
execFpuSimple_rVal2 :
(NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_execFpu_ETC___d76 ?
execFpuSimple_rVal1 :
execFpuSimple_rVal2) ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal1[30:0] :
31'h7FC00000 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673 =
in1_exp__h4123 < in2_exp__h4198 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 =
in1_exp__h4123 == in2_exp__h4198 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677 =
in1_sfd__h4124 < in2_sfd__h4199 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681 =
in1_exp__h4123 <= in2_exp__h4198 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682 =
in1_sfd__h4124 <= in2_sfd__h4199 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2686 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681 &&
(!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682) &&
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673 &&
(!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 ||
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677) ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2690 =
in1_exp__h4123 == 8'd0 && in1_sfd__h4124 == 23'd0 &&
in2_exp__h4198 == 8'd0 &&
in2_sfd__h4199 == 23'd0 ||
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31] ||
execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31]) &&
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2688 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2804 =
in1_exp__h4123 == 8'd0 && in1_sfd__h4124 == 23'd0 ||
int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4607 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 &&
!in1_sfd__h4124[22] ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0 &&
!in2_sfd__h4199[22] ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4612 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4667 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0 ||
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748[86:32] != 55'd0 ||
!IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792) ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4677 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0 ||
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748[86:64] != 23'd0 ||
!IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815) ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_EQ_0xFFFF_ETC__q85 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
in1_exp__h4123 == 8'd255 &&
in1_sfd__h4124 == 23'd0) ?
10'd1 :
10'd0 ;
assign IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d1666 =
execFpuSimple_rVal1[31] ?
6'd0 :
(execFpuSimple_rVal1[30] ?
6'd1 :
(execFpuSimple_rVal1[29] ?
6'd2 :
(execFpuSimple_rVal1[28] ?
6'd3 :
(execFpuSimple_rVal1[27] ?
6'd4 :
(execFpuSimple_rVal1[26] ?
6'd5 :
(execFpuSimple_rVal1[25] ?
6'd6 :
(execFpuSimple_rVal1[24] ?
6'd7 :
(execFpuSimple_rVal1[23] ?
6'd8 :
(execFpuSimple_rVal1[22] ?
6'd9 :
(execFpuSimple_rVal1[21] ?
6'd10 :
(execFpuSimple_rVal1[20] ?
6'd11 :
(execFpuSimple_rVal1[19] ?
6'd12 :
(execFpuSimple_rVal1[18] ?
6'd13 :
(execFpuSimple_rVal1[17] ?
6'd14 :
(execFpuSimple_rVal1[16] ?
6'd15 :
(execFpuSimple_rVal1[15] ?
6'd16 :
(execFpuSimple_rVal1[14] ?
6'd17 :
(execFpuSimple_rVal1[13] ?
6'd18 :
(execFpuSimple_rVal1[12] ?
6'd19 :
(execFpuSimple_rVal1[11] ?
6'd20 :
(execFpuSimple_rVal1[10] ?
6'd21 :
(execFpuSimple_rVal1[9] ?
6'd22 :
(execFpuSimple_rVal1[8] ?
6'd23 :
(execFpuSimple_rVal1[7] ?
6'd24 :
(execFpuSimple_rVal1[6] ?
6'd25 :
(execFpuSimple_rVal1[5] ?
6'd26 :
(execFpuSimple_rVal1[4] ?
6'd27 :
(execFpuSimple_rVal1[3] ?
6'd28 :
(execFpuSimple_rVal1[2] ?
6'd29 :
(execFpuSimple_rVal1[1] ?
6'd30 :
(execFpuSimple_rVal1[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d4326 =
execFpuSimple_rVal1[31] ?
6'd0 :
(execFpuSimple_rVal1[30] ?
6'd1 :
(execFpuSimple_rVal1[29] ?
6'd2 :
(execFpuSimple_rVal1[28] ?
6'd3 :
(execFpuSimple_rVal1[27] ?
6'd4 :
(execFpuSimple_rVal1[26] ?
6'd5 :
(execFpuSimple_rVal1[25] ?
6'd6 :
(execFpuSimple_rVal1[24] ?
6'd7 :
(execFpuSimple_rVal1[23] ?
6'd8 :
(execFpuSimple_rVal1[22] ?
6'd9 :
(execFpuSimple_rVal1[21] ?
6'd10 :
(execFpuSimple_rVal1[20] ?
6'd11 :
(execFpuSimple_rVal1[19] ?
6'd12 :
(execFpuSimple_rVal1[18] ?
6'd13 :
(execFpuSimple_rVal1[17] ?
6'd14 :
(execFpuSimple_rVal1[16] ?
6'd15 :
(execFpuSimple_rVal1[15] ?
6'd16 :
(execFpuSimple_rVal1[14] ?
6'd17 :
(execFpuSimple_rVal1[13] ?
6'd18 :
(execFpuSimple_rVal1[12] ?
6'd19 :
(execFpuSimple_rVal1[11] ?
6'd20 :
(execFpuSimple_rVal1[10] ?
6'd21 :
(execFpuSimple_rVal1[9] ?
6'd22 :
(execFpuSimple_rVal1[8] ?
6'd23 :
(execFpuSimple_rVal1[7] ?
6'd24 :
(execFpuSimple_rVal1[6] ?
6'd25 :
(execFpuSimple_rVal1[5] ?
6'd26 :
(execFpuSimple_rVal1[4] ?
6'd27 :
(execFpuSimple_rVal1[3] ?
6'd28 :
(execFpuSimple_rVal1[2] ?
6'd29 :
(execFpuSimple_rVal1[1] ?
6'd30 :
(execFpuSimple_rVal1[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748 =
value__h136325[30] || value__h136325[29] || value__h136325[28] ||
value__h136325[27] ||
value__h136325[26] ||
value__h136325[25] ||
value__h136325[24] ||
value__h136325[23] ||
value__h136325[22] ||
value__h136325[21] ||
value__h136325[20] ||
value__h136325[19] ||
value__h136325[18] ||
value__h136325[17] ||
value__h136325[16] ||
value__h136325[15] ||
value__h136325[14] ||
value__h136325[13] ||
value__h136325[12] ||
value__h136325[11] ||
value__h136325[10] ||
value__h136325[9] ||
value__h136325[8] ||
value__h136325[7] ||
value__h136325[6] ||
value__h136325[5] ||
value__h136325[4] ||
value__h136325[3] ||
value__h136325[2] ||
value__h136325[1] ||
value__h136325[0] ;
assign IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4886 =
(value__h136325[31] ||
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748) &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 &&
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 &&
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4883 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976 =
execFpuSimple_rVal1[63] ?
7'd0 :
(execFpuSimple_rVal1[62] ?
7'd1 :
(execFpuSimple_rVal1[61] ?
7'd2 :
(execFpuSimple_rVal1[60] ?
7'd3 :
(execFpuSimple_rVal1[59] ?
7'd4 :
(execFpuSimple_rVal1[58] ?
7'd5 :
(execFpuSimple_rVal1[57] ?
7'd6 :
(execFpuSimple_rVal1[56] ?
7'd7 :
(execFpuSimple_rVal1[55] ?
7'd8 :
(execFpuSimple_rVal1[54] ?
7'd9 :
(execFpuSimple_rVal1[53] ?
7'd10 :
(execFpuSimple_rVal1[52] ?
7'd11 :
(execFpuSimple_rVal1[51] ?
7'd12 :
(execFpuSimple_rVal1[50] ?
7'd13 :
(execFpuSimple_rVal1[49] ?
7'd14 :
(execFpuSimple_rVal1[48] ?
7'd15 :
(execFpuSimple_rVal1[47] ?
7'd16 :
(execFpuSimple_rVal1[46] ?
7'd17 :
(execFpuSimple_rVal1[45] ?
7'd18 :
(execFpuSimple_rVal1[44] ?
7'd19 :
(execFpuSimple_rVal1[43] ?
7'd20 :
(execFpuSimple_rVal1[42] ?
7'd21 :
(execFpuSimple_rVal1[41] ?
7'd22 :
(execFpuSimple_rVal1[40] ?
7'd23 :
(execFpuSimple_rVal1[39] ?
7'd24 :
(execFpuSimple_rVal1[38] ?
7'd25 :
(execFpuSimple_rVal1[37] ?
7'd26 :
(execFpuSimple_rVal1[36] ?
7'd27 :
(execFpuSimple_rVal1[35] ?
7'd28 :
(execFpuSimple_rVal1[34] ?
7'd29 :
(execFpuSimple_rVal1[33] ?
7'd30 :
(execFpuSimple_rVal1[32] ?
7'd31 :
(execFpuSimple_rVal1[31] ?
7'd32 :
(execFpuSimple_rVal1[30] ?
7'd33 :
(execFpuSimple_rVal1[29] ?
7'd34 :
(execFpuSimple_rVal1[28] ?
7'd35 :
(execFpuSimple_rVal1[27] ?
7'd36 :
(execFpuSimple_rVal1[26] ?
7'd37 :
(execFpuSimple_rVal1[25] ?
7'd38 :
(execFpuSimple_rVal1[24] ?
7'd39 :
(execFpuSimple_rVal1[23] ?
7'd40 :
(execFpuSimple_rVal1[22] ?
7'd41 :
(execFpuSimple_rVal1[21] ?
7'd42 :
(execFpuSimple_rVal1[20] ?
7'd43 :
(execFpuSimple_rVal1[19] ?
7'd44 :
(execFpuSimple_rVal1[18] ?
7'd45 :
(execFpuSimple_rVal1[17] ?
7'd46 :
(execFpuSimple_rVal1[16] ?
7'd47 :
(execFpuSimple_rVal1[15] ?
7'd48 :
(execFpuSimple_rVal1[14] ?
7'd49 :
(execFpuSimple_rVal1[13] ?
7'd50 :
(execFpuSimple_rVal1[12] ?
7'd51 :
(execFpuSimple_rVal1[11] ?
7'd52 :
(execFpuSimple_rVal1[10] ?
7'd53 :
(execFpuSimple_rVal1[9] ?
7'd54 :
(execFpuSimple_rVal1[8] ?
7'd55 :
(execFpuSimple_rVal1[7] ?
7'd56 :
(execFpuSimple_rVal1[6] ?
7'd57 :
(execFpuSimple_rVal1[5] ?
7'd58 :
(execFpuSimple_rVal1[4] ?
7'd59 :
(execFpuSimple_rVal1[3] ?
7'd60 :
(execFpuSimple_rVal1[2] ?
7'd61 :
(execFpuSimple_rVal1[1] ?
7'd62 :
(execFpuSimple_rVal1[0] ?
7'd63 :
7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178 =
execFpuSimple_rVal1[63] ?
-execFpuSimple_rVal1 :
execFpuSimple_rVal1 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2387 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 ||
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 &&
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 &&
_theResult___fst_exp__h165849 == 11'd2047 &&
_theResult___fst_sfd__h165850 == 52'd0) ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2494 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2570 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 &&
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 &&
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2567 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4778 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 ||
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 &&
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 &&
_theResult___fst_exp__h74563 == 8'd255 &&
_theResult___fst_sfd__h74564 == 23'd0) ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4825 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4904 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 &&
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 &&
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4901 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NOT_execF_ETC___d2157 =
execFpuSimple_rVal1[63] ?
!execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126 ||
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 &&
!execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129 :
execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132 ||
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 &&
execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134 ;
assign IF_execFpuSimple_rVal1_BIT_63_AND_execFpuSimpl_ETC__q1 =
(execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
10'd1 :
10'd0 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 =
(execFpuSimple_rVal1 == 64'd0 ||
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) ?
11'd0 :
_theResult___snd_fst_exp__h165858 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 =
(execFpuSimple_rVal1 == 64'd0 ||
NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d1536) ?
52'd0 :
_theResult___snd_fst_sfd__h165853 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207 =
(execFpuSimple_rVal1 == 64'd0 ||
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) ?
8'd0 :
_theResult___snd_fst_exp__h74572 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 =
(execFpuSimple_rVal1 == 64'd0 ||
NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d4212) ?
23'd0 :
_theResult___snd_fst_sfd__h74567 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065 =
(execFpuSimple_rVal1 == 64'd0 ||
!execFpuSimple_rVal1[63] && !execFpuSimple_rVal1[62] &&
!execFpuSimple_rVal1[61] &&
!execFpuSimple_rVal1[60] &&
!execFpuSimple_rVal1[59] &&
!execFpuSimple_rVal1[58] &&
!execFpuSimple_rVal1[57] &&
!execFpuSimple_rVal1[56] &&
!execFpuSimple_rVal1[55] &&
!execFpuSimple_rVal1[54] &&
!execFpuSimple_rVal1[53] &&
!execFpuSimple_rVal1[52] &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899) ?
11'd0 :
_theResult___snd_fst_exp__h176562 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102 =
(execFpuSimple_rVal1 == 64'd0 ||
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d2069) ?
52'd0 :
_theResult___snd_fst_sfd__h176557 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549 =
(execFpuSimple_rVal1 == 64'd0 ||
!execFpuSimple_rVal1[63] && !execFpuSimple_rVal1[62] &&
!execFpuSimple_rVal1[61] &&
!execFpuSimple_rVal1[60] &&
!execFpuSimple_rVal1[59] &&
!execFpuSimple_rVal1[58] &&
!execFpuSimple_rVal1[57] &&
!execFpuSimple_rVal1[56] &&
!execFpuSimple_rVal1[55] &&
!execFpuSimple_rVal1[54] &&
!execFpuSimple_rVal1[53] &&
!execFpuSimple_rVal1[52] &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899) ?
8'd0 :
_theResult___snd_fst_exp__h84870 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586 =
(execFpuSimple_rVal1 == 64'd0 ||
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d4553) ?
23'd0 :
_theResult___snd_fst_sfd__h84865 ;
assign IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630 =
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal2[30:0] :
31'h7FC00000 ;
assign IF_sfd___32660_BIT_7_THEN_2_ELSE_0__q142 =
sfd___3__h62660[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___32660_BIT_8_THEN_2_ELSE_0__q141 =
sfd___3__h62660[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___343743_BIT_1_THEN_2_ELSE_0__q30 =
sfd___3__h143743[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___343743_BIT_2_THEN_2_ELSE_0__q29 =
sfd___3__h143743[2] ? 2'd2 : 2'd0 ;
assign IF_sfd___353134_BIT_1_THEN_2_ELSE_0__q59 =
sfd___3__h153134[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___353134_BIT_2_THEN_2_ELSE_0__q58 =
sfd___3__h153134[2] ? 2'd2 : 2'd0 ;
assign IF_sfd___364367_BIT_10_THEN_2_ELSE_0__q42 =
sfd___3__h164367[10] ? 2'd2 : 2'd0 ;
assign IF_sfd___364367_BIT_11_THEN_2_ELSE_0__q41 =
sfd___3__h164367[11] ? 2'd2 : 2'd0 ;
assign IF_sfd___364367_BIT_39_THEN_2_ELSE_0__q40 =
sfd___3__h164367[39] ? 2'd2 : 2'd0 ;
assign IF_sfd___364367_BIT_40_THEN_2_ELSE_0__q39 =
sfd___3__h164367[40] ? 2'd2 : 2'd0 ;
assign IF_sfd___36805_BIT_7_THEN_2_ELSE_0__q116 =
sfd___3__h56805[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___36805_BIT_8_THEN_2_ELSE_0__q115 =
sfd___3__h56805[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___375073_BIT_10_THEN_2_ELSE_0__q72 =
sfd___3__h175073[10] ? 2'd2 : 2'd0 ;
assign IF_sfd___375073_BIT_11_THEN_2_ELSE_0__q71 =
sfd___3__h175073[11] ? 2'd2 : 2'd0 ;
assign IF_sfd___375073_BIT_39_THEN_2_ELSE_0__q70 =
sfd___3__h175073[39] ? 2'd2 : 2'd0 ;
assign IF_sfd___375073_BIT_40_THEN_2_ELSE_0__q69 =
sfd___3__h175073[40] ? 2'd2 : 2'd0 ;
assign IF_sfdin2284_BIT_33_THEN_2_ELSE_0__q95 =
sfdin__h42284[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin25848_BIT_4_THEN_2_ELSE_0__q13 =
sfdin__h125848[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin4431_BIT_33_THEN_2_ELSE_0__q89 =
sfdin__h24431[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd0951_BIT_33_THEN_2_ELSE_0__q98 =
_theResult___snd__h50951[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd16232_BIT_4_THEN_2_ELSE_0__q9 =
_theResult___snd__h116232[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd3074_BIT_33_THEN_2_ELSE_0__q91 =
_theResult___snd__h33074[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd34631_BIT_4_THEN_2_ELSE_0__q16 =
_theResult___snd__h134631[4] ? 2'd2 : 2'd0 ;
assign NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4707 =
!_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ||
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[2] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4848 =
!_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ||
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[0] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[0]) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_ETC___d935 =
(((execFpuSimple_rVal1[30:23] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h135478) !=
11'd2047 ||
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 ==
52'd0) &&
((execFpuSimple_rVal1[30:23] == 8'd255 &&
execFpuSimple_rVal1[22:0] != 23'd0 ||
(execFpuSimple_rVal1[30:23] == 8'd255 ||
execFpuSimple_rVal1[30:23] == 8'd0) &&
execFpuSimple_rVal1[22:0] == 23'd0) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d933) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ__ETC___d3853 =
(((execFpuSimple_rVal1[62:52] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h51595) !=
8'd255 ||
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 ==
23'd0) &&
((execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
(execFpuSimple_rVal1[62:52] == 11'd2047 ||
execFpuSimple_rVal1[62:52] == 11'd0) &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3851) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2685 =
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673 &&
(!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 ||
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677) &&
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681 &&
(!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2708 =
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 != 8'd0 ||
in2_sfd__h4199 != 23'd0) &&
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2707 ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4670 =
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ||
int_val_rnd__h5748[86:32] != 55'd0) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4680 =
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ||
int_val_rnd__h5748[86:64] != 23'd0) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4863 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 != 23'd0) &&
int_val_rnd__h5748[86:32] == 55'd0 &&
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792 &&
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
int_val__h5744[1:0] != 2'd0 ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4869 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748 == 87'd0 ||
execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
int_val_rnd__h5748[86:32] == 55'd0 &&
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
int_val__h5744[1:0] != 2'd0 ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4873 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 != 23'd0) &&
int_val_rnd__h5748[86:64] == 23'd0 &&
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815 &&
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
int_val__h5744[1:0] != 2'd0 ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4878 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748 == 87'd0 ||
execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
int_val_rnd__h5748[86:64] == 23'd0 &&
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
int_val__h5744[1:0] != 2'd0 ;
assign NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915 =
!value__h136325[30] && !value__h136325[29] &&
!value__h136325[28] &&
!value__h136325[27] &&
!value__h136325[26] &&
!value__h136325[25] &&
!value__h136325[24] &&
!value__h136325[23] &&
!value__h136325[22] &&
!value__h136325[21] &&
!value__h136325[20] &&
!value__h136325[19] &&
!value__h136325[18] &&
!value__h136325[17] &&
!value__h136325[16] &&
!value__h136325[15] &&
!value__h136325[14] &&
!value__h136325[13] &&
!value__h136325[12] &&
!value__h136325[11] &&
!value__h136325[10] &&
!value__h136325[9] &&
!value__h136325[8] &&
!value__h136325[7] &&
!value__h136325[6] &&
!value__h136325[5] &&
!value__h136325[4] &&
!value__h136325[3] &&
!value__h136325[2] &&
!value__h136325[1] &&
!value__h136325[0] ;
assign NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d1536 =
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0] ||
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 ||
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 ;
assign NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d4212 =
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0] ||
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 ||
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 ;
assign NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d1599 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 !=
11'd2047 ||
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 ==
52'd0) &&
execFpuSimple_rVal1 != 64'd0 &&
(NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d1536 ?
execFpuSimple_rVal1[63] :
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1596) ;
assign NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d4272 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207 !=
8'd255 ||
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 ==
23'd0) &&
execFpuSimple_rVal1 != 64'd0 &&
(NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d4212 ?
execFpuSimple_rVal1[63] :
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4269) ;
assign NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4759 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(value__h136325[31] ||
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748) &&
(!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 &&
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 &&
_theResult___fst_exp__h57881 == 8'd255 &&
_theResult___fst_sfd__h57882 == 23'd0) ;
assign NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4769 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(execFpuSimple_rVal1[31] ||
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418) &&
(!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 ||
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 &&
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 &&
_theResult___fst_exp__h63734 == 8'd255 &&
_theResult___fst_sfd__h63735 == 23'd0) ;
assign NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4820 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(value__h136325[31] ||
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748) &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9_ETC___d2160 =
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] != 11'd0 ||
execFpuSimple_rVal2[51:0] != 52'd0) &&
(execFpuSimple_rVal1[63] && !execFpuSimple_rVal2[63] ||
(execFpuSimple_rVal1[63] || !execFpuSimple_rVal2[63]) &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NOT_execF_ETC___d2157) ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val_rnd__h94412[115:32] == 84'd0 &&
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175 &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val__h94408[1:0] != 2'd0 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94412 == 116'd0 || !execFpuSimple_rVal1[63]) &&
int_val_rnd__h94412[115:32] == 84'd0 &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val__h94408[1:0] != 2'd0 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2541 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val_rnd__h94412[115:64] == 52'd0 &&
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198 &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val__h94408[1:0] != 2'd0 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2546 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94412 == 116'd0 || !execFpuSimple_rVal1[63]) &&
int_val_rnd__h94412[115:64] == 52'd0 &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val__h94408[1:0] != 2'd0 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_ex_ETC___d2139 =
!execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132 &&
(!execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 ||
!execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134) &&
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126 &&
(!execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 ||
execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129) ;
assign NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322 =
!execFpuSimple_rVal1[21] && !execFpuSimple_rVal1[20] &&
!execFpuSimple_rVal1[19] &&
!execFpuSimple_rVal1[18] &&
!execFpuSimple_rVal1[17] &&
!execFpuSimple_rVal1[16] &&
!execFpuSimple_rVal1[15] &&
!execFpuSimple_rVal1[14] &&
!execFpuSimple_rVal1[13] &&
!execFpuSimple_rVal1[12] &&
!execFpuSimple_rVal1[11] &&
!execFpuSimple_rVal1[10] &&
!execFpuSimple_rVal1[9] &&
!execFpuSimple_rVal1[8] &&
!execFpuSimple_rVal1[7] &&
!execFpuSimple_rVal1[6] &&
!execFpuSimple_rVal1[5] &&
!execFpuSimple_rVal1[4] &&
!execFpuSimple_rVal1[3] &&
!execFpuSimple_rVal1[2] &&
!execFpuSimple_rVal1[1] &&
!execFpuSimple_rVal1[0] ;
assign NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878 =
!execFpuSimple_rVal1[30] && !execFpuSimple_rVal1[29] &&
!execFpuSimple_rVal1[28] &&
!execFpuSimple_rVal1[27] &&
!execFpuSimple_rVal1[26] &&
!execFpuSimple_rVal1[25] &&
!execFpuSimple_rVal1[24] &&
!execFpuSimple_rVal1[23] &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322 ;
assign NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 =
!execFpuSimple_rVal1[51] && !execFpuSimple_rVal1[50] &&
!execFpuSimple_rVal1[49] &&
!execFpuSimple_rVal1[48] &&
!execFpuSimple_rVal1[47] &&
!execFpuSimple_rVal1[46] &&
!execFpuSimple_rVal1[45] &&
!execFpuSimple_rVal1[44] &&
!execFpuSimple_rVal1[43] &&
!execFpuSimple_rVal1[42] &&
!execFpuSimple_rVal1[41] &&
!execFpuSimple_rVal1[40] &&
!execFpuSimple_rVal1[39] &&
!execFpuSimple_rVal1[38] &&
!execFpuSimple_rVal1[37] &&
!execFpuSimple_rVal1[36] &&
!execFpuSimple_rVal1[35] &&
!execFpuSimple_rVal1[34] &&
!execFpuSimple_rVal1[33] &&
!execFpuSimple_rVal1[32] &&
!execFpuSimple_rVal1[31] &&
NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878 ;
assign NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d2069 =
!execFpuSimple_rVal1[63] && !execFpuSimple_rVal1[62] &&
!execFpuSimple_rVal1[61] &&
!execFpuSimple_rVal1[60] &&
!execFpuSimple_rVal1[59] &&
!execFpuSimple_rVal1[58] &&
!execFpuSimple_rVal1[57] &&
!execFpuSimple_rVal1[56] &&
!execFpuSimple_rVal1[55] &&
!execFpuSimple_rVal1[54] &&
!execFpuSimple_rVal1[53] &&
!execFpuSimple_rVal1[52] &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 ||
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 ||
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 ;
assign NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d4553 =
!execFpuSimple_rVal1[63] && !execFpuSimple_rVal1[62] &&
!execFpuSimple_rVal1[61] &&
!execFpuSimple_rVal1[60] &&
!execFpuSimple_rVal1[59] &&
!execFpuSimple_rVal1[58] &&
!execFpuSimple_rVal1[57] &&
!execFpuSimple_rVal1[56] &&
!execFpuSimple_rVal1[55] &&
!execFpuSimple_rVal1[54] &&
!execFpuSimple_rVal1[53] &&
!execFpuSimple_rVal1[52] &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 ||
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 ||
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 ;
assign NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_execFpu_ETC___d76 =
!execFpuSimple_rVal1[63] && execFpuSimple_rVal2[63] ||
execFpuSimple_rVal1_BIT_63_4_EQ_execFpuSimple__ETC___d58 &&
!(execFpuSimple_rVal1[63] ^
execFpuSimple_rVal1[62:0] <= execFpuSimple_rVal2[62:0]) ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 =
{ {4{execFpuSimple_rVal1_BITS_30_TO_23_MINUS_127__q10[7]}},
execFpuSimple_rVal1_BITS_30_TO_23_MINUS_127__q10 } ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 =
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 ^
12'h800) <=
12'd3071 ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 =
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 ^
12'h800) <
12'd1026 ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q11 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 +
12'd1023 ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q14 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q11[10:0] -
11'd1023 ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 =
{ execFpuSimple_rVal1_BITS_62_TO_52_MINUS_1023__q92[10],
execFpuSimple_rVal1_BITS_62_TO_52_MINUS_1023__q92 } ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 =
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 ^
12'h800) <=
12'd2175 ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 =
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 ^
12'h800) <
12'd1922 ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 +
12'd127 ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q96 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d3135 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626 =
{ 3'd0,
_theResult___fst_exp__h24437 == 8'd0 &&
(sfdin__h24431[56:34] == 23'd0 || guard__h16338 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h25064 == 8'd255 &&
_theResult___fst_sfd__h25065 == 23'd0,
1'd0,
_theResult___fst_exp__h24437 != 8'd255 &&
guard__h16338 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235 =
{ 3'd0,
_theResult___fst_exp__h125854 == 11'd0 &&
(sfdin__h125848[56:5] == 52'd0 || guard__h117628 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h126684 == 11'd2047 &&
_theResult___fst_sfd__h126685 == 52'd0,
1'd0,
_theResult___fst_exp__h125854 != 11'd2047 &&
guard__h117628 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d680 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d3576 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655 =
{ 3'd0,
_theResult___fst_exp__h42290 == 8'd0 &&
(sfdin__h42284[56:34] == 23'd0 || guard__h34064 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h42917 == 8'd255 &&
_theResult___fst_sfd__h42918 == 23'd0,
1'd0,
_theResult___fst_exp__h42290 != 8'd255 &&
guard__h34064 != 2'b0 } ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218 =
{ 3'd0,
_theResult___fst_exp__h116281 == 11'd0 &&
guard__h108320 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h117037 == 11'd2047 &&
_theResult___fst_sfd__h117038 == 52'd0,
1'd0,
_theResult___fst_exp__h116281 != 11'd2047 &&
guard__h108320 != 2'b0 } ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d351 =
({ 6'd0,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d753 =
({ 6'd0,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 } ^
12'h800) <=
(IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d752 ^
12'h800) ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3257 =
({ 3'd0,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3649 =
({ 3'd0,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 } ^
9'h100) <=
(IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3648 ^
9'h100) ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638 =
{ 3'd0,
_theResult___fst_exp__h33123 == 8'd0 && guard__h25075 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h33676 == 8'd255 &&
_theResult___fst_sfd__h33677 == 23'd0,
1'd0,
_theResult___fst_exp__h33123 != 8'd255 &&
guard__h25075 != 2'b0 } ;
assign _0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_30_TO__ETC___d436 =
sfd__h97423 >>
_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432 ;
assign _0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_62_TO__ETC___d3334 =
sfd__h8697 >>
_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330 ;
assign _1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115 =
17'd1075 - { 6'd0, execFpuSimple_rVal1[62:52] } ;
assign _150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746 =
13'd150 - { 5'd0, in1_exp__h4123 } ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2898 =
12'd3074 -
{ 6'd0,
execFpuSimple_rVal1[51] ?
6'd0 :
(execFpuSimple_rVal1[50] ?
6'd1 :
(execFpuSimple_rVal1[49] ?
6'd2 :
(execFpuSimple_rVal1[48] ?
6'd3 :
(execFpuSimple_rVal1[47] ?
6'd4 :
(execFpuSimple_rVal1[46] ?
6'd5 :
(execFpuSimple_rVal1[45] ?
6'd6 :
(execFpuSimple_rVal1[44] ?
6'd7 :
(execFpuSimple_rVal1[43] ?
6'd8 :
(execFpuSimple_rVal1[42] ?
6'd9 :
(execFpuSimple_rVal1[41] ?
6'd10 :
(execFpuSimple_rVal1[40] ?
6'd11 :
(execFpuSimple_rVal1[39] ?
6'd12 :
(execFpuSimple_rVal1[38] ?
6'd13 :
(execFpuSimple_rVal1[37] ?
6'd14 :
(execFpuSimple_rVal1[36] ?
6'd15 :
(execFpuSimple_rVal1[35] ?
6'd16 :
(execFpuSimple_rVal1[34] ?
6'd17 :
(execFpuSimple_rVal1[33] ?
6'd18 :
(execFpuSimple_rVal1[32] ?
6'd19 :
(execFpuSimple_rVal1[31] ?
6'd20 :
(execFpuSimple_rVal1[30] ?
6'd21 :
(execFpuSimple_rVal1[29] ?
6'd22 :
(execFpuSimple_rVal1[28] ?
6'd23 :
(execFpuSimple_rVal1[27] ?
6'd24 :
(execFpuSimple_rVal1[26] ?
6'd25 :
(execFpuSimple_rVal1[25] ?
6'd26 :
(execFpuSimple_rVal1[24] ?
6'd27 :
(execFpuSimple_rVal1[23] ?
6'd28 :
(execFpuSimple_rVal1[22] ?
6'd29 :
(execFpuSimple_rVal1[21] ?
6'd30 :
(execFpuSimple_rVal1[20] ?
6'd31 :
(execFpuSimple_rVal1[19] ?
6'd32 :
(execFpuSimple_rVal1[18] ?
6'd33 :
(execFpuSimple_rVal1[17] ?
6'd34 :
(execFpuSimple_rVal1[16] ?
6'd35 :
(execFpuSimple_rVal1[15] ?
6'd36 :
(execFpuSimple_rVal1[14] ?
6'd37 :
(execFpuSimple_rVal1[13] ?
6'd38 :
(execFpuSimple_rVal1[12] ?
6'd39 :
(execFpuSimple_rVal1[11] ?
6'd40 :
(execFpuSimple_rVal1[10] ?
6'd41 :
(execFpuSimple_rVal1[9] ?
6'd42 :
(execFpuSimple_rVal1[8] ?
6'd43 :
(execFpuSimple_rVal1[7] ?
6'd44 :
(execFpuSimple_rVal1[6] ?
6'd45 :
(execFpuSimple_rVal1[5] ?
6'd46 :
(execFpuSimple_rVal1[4] ?
6'd47 :
(execFpuSimple_rVal1[3] ?
6'd48 :
(execFpuSimple_rVal1[2] ?
6'd49 :
(execFpuSimple_rVal1[1] ?
6'd50 :
(execFpuSimple_rVal1[0] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 =
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2898 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 =
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2898 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4641 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 &&
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[4] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[4]) ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4694 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 &&
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[3] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[3]) ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4808 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 &&
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[1] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[1]) ;
assign _3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432 =
12'd3074 -
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 =
(12'd32 -
{ 6'd0,
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d1011 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 =
(9'd32 -
{ 3'd0,
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d3949 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 ^
9'h100) <
9'd130 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 =
(12'd32 -
{ 6'd0,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d1666 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 =
(9'd32 -
{ 3'd0,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d4326 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 ^
9'h100) <
9'd130 ;
assign _3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d276 =
12'd3970 -
{ 7'd0,
execFpuSimple_rVal1[22] ?
5'd0 :
(execFpuSimple_rVal1[21] ?
5'd1 :
(execFpuSimple_rVal1[20] ?
5'd2 :
(execFpuSimple_rVal1[19] ?
5'd3 :
(execFpuSimple_rVal1[18] ?
5'd4 :
(execFpuSimple_rVal1[17] ?
5'd5 :
(execFpuSimple_rVal1[16] ?
5'd6 :
(execFpuSimple_rVal1[15] ?
5'd7 :
(execFpuSimple_rVal1[14] ?
5'd8 :
(execFpuSimple_rVal1[13] ?
5'd9 :
(execFpuSimple_rVal1[12] ?
5'd10 :
(execFpuSimple_rVal1[11] ?
5'd11 :
(execFpuSimple_rVal1[10] ?
5'd12 :
(execFpuSimple_rVal1[9] ?
5'd13 :
(execFpuSimple_rVal1[8] ?
5'd14 :
(execFpuSimple_rVal1[7] ?
5'd15 :
(execFpuSimple_rVal1[6] ?
5'd16 :
(execFpuSimple_rVal1[5] ?
5'd17 :
(execFpuSimple_rVal1[4] ?
5'd18 :
(execFpuSimple_rVal1[3] ?
5'd19 :
(execFpuSimple_rVal1[2] ?
5'd20 :
(execFpuSimple_rVal1[1] ?
5'd21 :
(execFpuSimple_rVal1[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 =
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d276 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 =
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d276 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330 =
12'd3970 -
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 =
(12'd64 -
{ 5'd0,
IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434 }) -
12'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 ^
12'h800) <=
12'd3071 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 ^
12'h800) <
12'd974 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 ^
12'h800) <
12'd1026 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 =
(9'd64 -
{ 2'd0,
IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434 }) -
9'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 ^
9'h100) <=
9'd383 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 ^
9'h100) <
9'd107 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 ^
9'h100) <
9'd130 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 =
(12'd64 -
{ 5'd0,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976 }) -
12'd1 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 ^
12'h800) <=
12'd3071 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 ^
12'h800) <
12'd974 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 ^
12'h800) <
12'd1026 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 =
(9'd64 -
{ 2'd0,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976 }) -
9'd1 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 ^
9'h100) <=
9'd383 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 ^
9'h100) <
9'd107 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 ^
9'h100) <
9'd130 ;
assign _theResult_____1_fst__h6884 =
(int_val_rnd__h5748[86:32] == 55'd0) ?
out__h6900 :
64'hFFFFFFFFFFFFFFFF ;
assign _theResult_____1_fst__h8071 =
(int_val_rnd__h5748[86:64] == 23'd0) ?
int_val_rnd__h5748[63:0] :
64'hFFFFFFFFFFFFFFFF ;
assign _theResult_____1_fst__h95556 =
(int_val_rnd__h94412[115:32] == 84'd0) ?
out__h95572 :
64'hFFFFFFFFFFFFFFFF ;
assign _theResult_____1_fst__h96799 =
(int_val_rnd__h94412[115:64] == 52'd0) ?
int_val_rnd__h94412[63:0] :
64'hFFFFFFFFFFFFFFFF ;
assign _theResult____h117618 =
((_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432 ^
12'h800) <
12'd2105) ?
result__h118231 :
((value__h101838 == 25'd0) ? sfd__h97423 : 57'd1) ;
assign _theResult____h16328 =
(value__h16950 == 54'd0) ? sfd__h8697 : 57'd1 ;
assign _theResult____h34054 =
((_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330 ^
12'h800) <
12'd2105) ?
result__h34667 :
_theResult____h16328 ;
assign _theResult___exp__h116936 =
sfd__h116299[53] ?
((_theResult___fst_exp__h116281 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h135501) :
((_theResult___fst_exp__h116281 == 11'd0 &&
sfd__h116299[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h116281) ;
assign _theResult___exp__h126583 =
sfd__h125946[53] ?
((_theResult___fst_exp__h125854 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h135531) :
((_theResult___fst_exp__h125854 == 11'd0 &&
sfd__h125946[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h125854) ;
assign _theResult___exp__h135365 =
sfd__h134704[53] ?
((_theResult___fst_exp__h134685 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h135555) :
((_theResult___fst_exp__h134685 == 11'd0 &&
sfd__h134704[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h134685) ;
assign _theResult___exp__h144369 =
(sfd__h143770[53] || sfd__h143770[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h145125 =
sfd__h144513[53] ?
((x__h144498[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h145267) :
((x__h144498[10:0] == 11'd0 && sfd__h144513[53:52] == 2'b01) ?
11'd1 :
x__h144498[10:0]) ;
assign _theResult___exp__h153760 =
(sfd__h153161[53] || sfd__h153161[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h154515 =
sfd__h153903[53] ?
((x__h153888[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h154653) :
((x__h153888[10:0] == 11'd0 && sfd__h153903[53:52] == 2'b01) ?
11'd1 :
x__h153888[10:0]) ;
assign _theResult___exp__h164993 =
(sfd__h164394[53] || sfd__h164394[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h165749 =
sfd__h165137[53] ?
((x__h165122[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h165891) :
((x__h165122[10:0] == 11'd0 && sfd__h165137[53:52] == 2'b01) ?
11'd1 :
x__h165122[10:0]) ;
assign _theResult___exp__h175699 =
(sfd__h175100[53] || sfd__h175100[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h176454 =
sfd__h175842[53] ?
((x__h175827[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h176592) :
((x__h175827[10:0] == 11'd0 && sfd__h175842[53:52] == 2'b01) ?
11'd1 :
x__h175827[10:0]) ;
assign _theResult___exp__h24963 =
sfd__h24529[24] ?
((_theResult___fst_exp__h24437 == 8'd254) ?
8'd255 :
din_inc___2_exp__h51614) :
((_theResult___fst_exp__h24437 == 8'd0 &&
sfd__h24529[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h24437) ;
assign _theResult___exp__h33575 =
sfd__h33141[24] ?
((_theResult___fst_exp__h33123 == 8'd254) ?
8'd255 :
din_inc___2_exp__h51638) :
((_theResult___fst_exp__h33123 == 8'd0 &&
sfd__h33141[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h33123) ;
assign _theResult___exp__h42816 =
sfd__h42382[24] ?
((_theResult___fst_exp__h42290 == 8'd254) ?
8'd255 :
din_inc___2_exp__h51668) :
((_theResult___fst_exp__h42290 == 8'd0 &&
sfd__h42382[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h42290) ;
assign _theResult___exp__h51482 =
sfd__h51024[24] ?
((_theResult___fst_exp__h51005 == 8'd254) ?
8'd255 :
din_inc___2_exp__h51692) :
((_theResult___fst_exp__h51005 == 8'd0 &&
sfd__h51024[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h51005) ;
assign _theResult___exp__h57228 =
(sfd__h56832[24] || sfd__h56832[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h57781 =
sfd__h57372[24] ?
((x__h57357[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h57923) :
((x__h57357[7:0] == 8'd0 && sfd__h57372[24:23] == 2'b01) ?
8'd1 :
x__h57357[7:0]) ;
assign _theResult___exp__h63083 =
(sfd__h62687[24] || sfd__h62687[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h63635 =
sfd__h63226[24] ?
((x__h63211[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h63773) :
((x__h63211[7:0] == 8'd0 && sfd__h63226[24:23] == 2'b01) ?
8'd1 :
x__h63211[7:0]) ;
assign _theResult___exp__h73910 =
(sfd__h73514[24] || sfd__h73514[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h74463 =
sfd__h74054[24] ?
((x__h74039[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h74605) :
((x__h74039[7:0] == 8'd0 && sfd__h74054[24:23] == 2'b01) ?
8'd1 :
x__h74039[7:0]) ;
assign _theResult___exp__h84210 =
(sfd__h83814[24] || sfd__h83814[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h84762 =
sfd__h84353[24] ?
((x__h84338[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h84900) :
((x__h84338[7:0] == 8'd0 && sfd__h84353[24:23] == 2'b01) ?
8'd1 :
x__h84338[7:0]) ;
assign _theResult___fst__h5722 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0) ?
out__h5724 :
_theResult___fst__h5738 ;
assign _theResult___fst__h5738 =
(in1_exp__h4123 == 8'd0 && in1_sfd__h4124 == 23'd0) ?
64'd0 :
_theResult___fst__h5753 ;
assign _theResult___fst__h5753 =
(int_val_rnd__h5748[86:32] == 55'd0 &&
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792) ?
out__h6306 :
out__h6311 ;
assign _theResult___fst__h6366 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0) ?
out__h6368 :
_theResult___fst__h6381 ;
assign _theResult___fst__h6381 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2804 ?
64'd0 :
_theResult_____1_fst__h6884 ;
assign _theResult___fst__h6963 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0) ?
out__h6965 :
_theResult___fst__h6979 ;
assign _theResult___fst__h6979 =
(in1_exp__h4123 == 8'd0 && in1_sfd__h4124 == 23'd0) ?
64'd0 :
_theResult___fst__h6994 ;
assign _theResult___fst__h6994 =
(int_val_rnd__h5748[86:64] == 23'd0 &&
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815) ?
out__h7498 :
max_val__h7005 ;
assign _theResult___fst__h7553 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0) ?
out__h6368 :
_theResult___fst__h7568 ;
assign _theResult___fst__h7568 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2804 ?
64'd0 :
_theResult_____1_fst__h8071 ;
assign _theResult___fst__h94386 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
out__h94388 :
_theResult___fst__h94402 ;
assign _theResult___fst__h94402 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
64'd0 :
_theResult___fst__h94417 ;
assign _theResult___fst__h94417 =
(int_val_rnd__h94412[115:32] == 84'd0 &&
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175) ?
out__h94950 :
out__h94955 ;
assign _theResult___fst__h95010 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
out__h95012 :
_theResult___fst__h95025 ;
assign _theResult___fst__h95025 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
int_val_rnd__h94412 != 116'd0 && execFpuSimple_rVal1[63]) ?
64'd0 :
_theResult_____1_fst__h95556 ;
assign _theResult___fst__h95635 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
out__h95637 :
_theResult___fst__h95651 ;
assign _theResult___fst__h95651 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
64'd0 :
_theResult___fst__h95666 ;
assign _theResult___fst__h95666 =
(int_val_rnd__h94412[115:64] == 52'd0 &&
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198) ?
out__h96198 :
max_val__h95677 ;
assign _theResult___fst__h96253 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
out__h95012 :
_theResult___fst__h96268 ;
assign _theResult___fst__h96268 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
int_val_rnd__h94412 != 116'd0 && execFpuSimple_rVal1[63]) ?
64'd0 :
_theResult_____1_fst__h96799 ;
assign _theResult___fst_exp__h101208 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011) ?
11'd2047 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_20_ETC__q4 ;
assign _theResult___fst_exp__h116272 =
11'd897 -
{ 5'd0,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 } ;
assign _theResult___fst_exp__h116278 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322 ||
!_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d351) ?
11'd0 :
_theResult___fst_exp__h116272 ;
assign _theResult___fst_exp__h116281 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_theResult___fst_exp__h116278 :
11'd897 ;
assign _theResult___fst_exp__h117034 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q18 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d413 ;
assign _theResult___fst_exp__h117037 =
(_theResult___fst_exp__h116281 == 11'd2047) ?
_theResult___fst_exp__h116281 :
_theResult___fst_exp__h117034 ;
assign _theResult___fst_exp__h125854 =
_theResult____h117618[56] ?
11'd2 :
_theResult___fst_exp__h125928 ;
assign _theResult___fst_exp__h125919 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678 } ;
assign _theResult___fst_exp__h125925 =
(!_theResult____h117618[56] && !_theResult____h117618[55] &&
!_theResult____h117618[54] &&
!_theResult____h117618[53] &&
!_theResult____h117618[52] &&
!_theResult____h117618[51] &&
!_theResult____h117618[50] &&
!_theResult____h117618[49] &&
!_theResult____h117618[48] &&
!_theResult____h117618[47] &&
!_theResult____h117618[46] &&
!_theResult____h117618[45] &&
!_theResult____h117618[44] &&
!_theResult____h117618[43] &&
!_theResult____h117618[42] &&
!_theResult____h117618[41] &&
!_theResult____h117618[40] &&
!_theResult____h117618[39] &&
!_theResult____h117618[38] &&
!_theResult____h117618[37] &&
!_theResult____h117618[36] &&
!_theResult____h117618[35] &&
!_theResult____h117618[34] &&
!_theResult____h117618[33] &&
!_theResult____h117618[32] &&
!_theResult____h117618[31] &&
!_theResult____h117618[30] &&
!_theResult____h117618[29] &&
!_theResult____h117618[28] &&
!_theResult____h117618[27] &&
!_theResult____h117618[26] &&
!_theResult____h117618[25] &&
!_theResult____h117618[24] &&
!_theResult____h117618[23] &&
!_theResult____h117618[22] &&
!_theResult____h117618[21] &&
!_theResult____h117618[20] &&
!_theResult____h117618[19] &&
!_theResult____h117618[18] &&
!_theResult____h117618[17] &&
!_theResult____h117618[16] &&
!_theResult____h117618[15] &&
!_theResult____h117618[14] &&
!_theResult____h117618[13] &&
!_theResult____h117618[12] &&
!_theResult____h117618[11] &&
!_theResult____h117618[10] &&
!_theResult____h117618[9] &&
!_theResult____h117618[8] &&
!_theResult____h117618[7] &&
!_theResult____h117618[6] &&
!_theResult____h117618[5] &&
!_theResult____h117618[4] &&
!_theResult____h117618[3] &&
!_theResult____h117618[2] &&
!_theResult____h117618[1] &&
!_theResult____h117618[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d680) ?
11'd0 :
_theResult___fst_exp__h125919 ;
assign _theResult___fst_exp__h125928 =
(!_theResult____h117618[56] && _theResult____h117618[55]) ?
11'd1 :
_theResult___fst_exp__h125925 ;
assign _theResult___fst_exp__h126681 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q20 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d743 ;
assign _theResult___fst_exp__h126684 =
(_theResult___fst_exp__h125854 == 11'd2047) ?
_theResult___fst_exp__h125854 :
_theResult___fst_exp__h126681 ;
assign _theResult___fst_exp__h134637 =
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q11[10:0] ==
11'd0) ?
11'd1 :
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q11[10:0] ;
assign _theResult___fst_exp__h134676 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q11[10:0] -
{ 5'd0,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 } ;
assign _theResult___fst_exp__h134682 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322 ||
!_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d753) ?
11'd0 :
_theResult___fst_exp__h134676 ;
assign _theResult___fst_exp__h134685 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_theResult___fst_exp__h134682 :
_theResult___fst_exp__h134637 ;
assign _theResult___fst_exp__h135463 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q22 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d812 ;
assign _theResult___fst_exp__h135466 =
(_theResult___fst_exp__h134685 == 11'd2047) ?
_theResult___fst_exp__h134685 :
_theResult___fst_exp__h135463 ;
assign _theResult___fst_exp__h135475 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ?
_theResult___snd_fst_exp__h117040 :
_theResult___fst_exp__h101208) :
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ?
_theResult___snd_fst_exp__h135469 :
_theResult___fst_exp__h101208) ;
assign _theResult___fst_exp__h135478 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
execFpuSimple_rVal1[22:0] == 23'd0) ?
11'd0 :
_theResult___fst_exp__h135475 ;
assign _theResult___fst_exp__h144466 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard43753_0b0_0_0b1_0_0b10_out_exp44372__ETC__q32 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1056 ;
assign _theResult___fst_exp__h145222 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_x4_ETC__q34 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1103 ;
assign _theResult___fst_exp__h145225 =
(x__h144498[10:0] == 11'd2047) ?
x__h144498[10:0] :
_theResult___fst_exp__h145222 ;
assign _theResult___fst_exp__h153856 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard53144_0b0_0_0b1_0_0b10_out_exp53763__ETC__q60 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q62 ;
assign _theResult___fst_exp__h154611 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_x5_ETC__q64 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1751 ;
assign _theResult___fst_exp__h154614 =
(x__h153888[10:0] == 11'd2047) ?
x__h153888[10:0] :
_theResult___fst_exp__h154611 ;
assign _theResult___fst_exp__h16310 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011) ?
8'd255 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_25_ETC__q2 ;
assign _theResult___fst_exp__h165090 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard64377_0b0_0_0b1_0_0b10_out_exp64996__ETC__q44 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1478 ;
assign _theResult___fst_exp__h165846 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_x6_ETC__q46 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1525 ;
assign _theResult___fst_exp__h165849 =
(x__h165122[10:0] == 11'd2047) ?
x__h165122[10:0] :
_theResult___fst_exp__h165846 ;
assign _theResult___fst_exp__h175795 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard75083_0b0_0_0b1_0_0b10_out_exp75702__ETC__q76 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q78 ;
assign _theResult___fst_exp__h176550 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_x7_ETC__q80 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2059 ;
assign _theResult___fst_exp__h176553 =
(x__h175827[10:0] == 11'd2047) ?
x__h175827[10:0] :
_theResult___fst_exp__h176550 ;
assign _theResult___fst_exp__h24437 =
_theResult____h16328[56] ? 8'd2 : _theResult___fst_exp__h24511 ;
assign _theResult___fst_exp__h24502 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133 } ;
assign _theResult___fst_exp__h24508 =
(!_theResult____h16328[56] && !_theResult____h16328[55] &&
!_theResult____h16328[54] &&
!_theResult____h16328[53] &&
!_theResult____h16328[52] &&
!_theResult____h16328[51] &&
!_theResult____h16328[50] &&
!_theResult____h16328[49] &&
!_theResult____h16328[48] &&
!_theResult____h16328[47] &&
!_theResult____h16328[46] &&
!_theResult____h16328[45] &&
!_theResult____h16328[44] &&
!_theResult____h16328[43] &&
!_theResult____h16328[42] &&
!_theResult____h16328[41] &&
!_theResult____h16328[40] &&
!_theResult____h16328[39] &&
!_theResult____h16328[38] &&
!_theResult____h16328[37] &&
!_theResult____h16328[36] &&
!_theResult____h16328[35] &&
!_theResult____h16328[34] &&
!_theResult____h16328[33] &&
!_theResult____h16328[32] &&
!_theResult____h16328[31] &&
!_theResult____h16328[30] &&
!_theResult____h16328[29] &&
!_theResult____h16328[28] &&
!_theResult____h16328[27] &&
!_theResult____h16328[26] &&
!_theResult____h16328[25] &&
!_theResult____h16328[24] &&
!_theResult____h16328[23] &&
!_theResult____h16328[22] &&
!_theResult____h16328[21] &&
!_theResult____h16328[20] &&
!_theResult____h16328[19] &&
!_theResult____h16328[18] &&
!_theResult____h16328[17] &&
!_theResult____h16328[16] &&
!_theResult____h16328[15] &&
!_theResult____h16328[14] &&
!_theResult____h16328[13] &&
!_theResult____h16328[12] &&
!_theResult____h16328[11] &&
!_theResult____h16328[10] &&
!_theResult____h16328[9] &&
!_theResult____h16328[8] &&
!_theResult____h16328[7] &&
!_theResult____h16328[6] &&
!_theResult____h16328[5] &&
!_theResult____h16328[4] &&
!_theResult____h16328[3] &&
!_theResult____h16328[2] &&
!_theResult____h16328[1] &&
!_theResult____h16328[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d3135) ?
8'd0 :
_theResult___fst_exp__h24502 ;
assign _theResult___fst_exp__h24511 =
(!_theResult____h16328[56] && _theResult____h16328[55]) ?
8'd1 :
_theResult___fst_exp__h24508 ;
assign _theResult___fst_exp__h25061 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q100 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3198 ;
assign _theResult___fst_exp__h25064 =
(_theResult___fst_exp__h24437 == 8'd255) ?
_theResult___fst_exp__h24437 :
_theResult___fst_exp__h25061 ;
assign _theResult___fst_exp__h33114 =
8'd129 -
{ 2'd0,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 } ;
assign _theResult___fst_exp__h33120 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 ||
!_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3257) ?
8'd0 :
_theResult___fst_exp__h33114 ;
assign _theResult___fst_exp__h33123 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_theResult___fst_exp__h33120 :
8'd129 ;
assign _theResult___fst_exp__h33673 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q102 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3315 ;
assign _theResult___fst_exp__h33676 =
(_theResult___fst_exp__h33123 == 8'd255) ?
_theResult___fst_exp__h33123 :
_theResult___fst_exp__h33673 ;
assign _theResult___fst_exp__h42290 =
_theResult____h34054[56] ? 8'd2 : _theResult___fst_exp__h42364 ;
assign _theResult___fst_exp__h42355 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574 } ;
assign _theResult___fst_exp__h42361 =
(!_theResult____h34054[56] && !_theResult____h34054[55] &&
!_theResult____h34054[54] &&
!_theResult____h34054[53] &&
!_theResult____h34054[52] &&
!_theResult____h34054[51] &&
!_theResult____h34054[50] &&
!_theResult____h34054[49] &&
!_theResult____h34054[48] &&
!_theResult____h34054[47] &&
!_theResult____h34054[46] &&
!_theResult____h34054[45] &&
!_theResult____h34054[44] &&
!_theResult____h34054[43] &&
!_theResult____h34054[42] &&
!_theResult____h34054[41] &&
!_theResult____h34054[40] &&
!_theResult____h34054[39] &&
!_theResult____h34054[38] &&
!_theResult____h34054[37] &&
!_theResult____h34054[36] &&
!_theResult____h34054[35] &&
!_theResult____h34054[34] &&
!_theResult____h34054[33] &&
!_theResult____h34054[32] &&
!_theResult____h34054[31] &&
!_theResult____h34054[30] &&
!_theResult____h34054[29] &&
!_theResult____h34054[28] &&
!_theResult____h34054[27] &&
!_theResult____h34054[26] &&
!_theResult____h34054[25] &&
!_theResult____h34054[24] &&
!_theResult____h34054[23] &&
!_theResult____h34054[22] &&
!_theResult____h34054[21] &&
!_theResult____h34054[20] &&
!_theResult____h34054[19] &&
!_theResult____h34054[18] &&
!_theResult____h34054[17] &&
!_theResult____h34054[16] &&
!_theResult____h34054[15] &&
!_theResult____h34054[14] &&
!_theResult____h34054[13] &&
!_theResult____h34054[12] &&
!_theResult____h34054[11] &&
!_theResult____h34054[10] &&
!_theResult____h34054[9] &&
!_theResult____h34054[8] &&
!_theResult____h34054[7] &&
!_theResult____h34054[6] &&
!_theResult____h34054[5] &&
!_theResult____h34054[4] &&
!_theResult____h34054[3] &&
!_theResult____h34054[2] &&
!_theResult____h34054[1] &&
!_theResult____h34054[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d3576) ?
8'd0 :
_theResult___fst_exp__h42355 ;
assign _theResult___fst_exp__h42364 =
(!_theResult____h34054[56] && _theResult____h34054[55]) ?
8'd1 :
_theResult___fst_exp__h42361 ;
assign _theResult___fst_exp__h42914 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q104 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3639 ;
assign _theResult___fst_exp__h42917 =
(_theResult___fst_exp__h42290 == 8'd255) ?
_theResult___fst_exp__h42290 :
_theResult___fst_exp__h42914 ;
assign _theResult___fst_exp__h50957 =
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] ==
8'd0) ?
8'd1 :
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] ;
assign _theResult___fst_exp__h50996 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] -
{ 2'd0,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 } ;
assign _theResult___fst_exp__h51002 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 ||
!_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3649) ?
8'd0 :
_theResult___fst_exp__h50996 ;
assign _theResult___fst_exp__h51005 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_theResult___fst_exp__h51002 :
_theResult___fst_exp__h50957 ;
assign _theResult___fst_exp__h51580 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q106 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3708 ;
assign _theResult___fst_exp__h51583 =
(_theResult___fst_exp__h51005 == 8'd255) ?
_theResult___fst_exp__h51005 :
_theResult___fst_exp__h51580 ;
assign _theResult___fst_exp__h51592 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ?
_theResult___snd_fst_exp__h33679 :
_theResult___fst_exp__h16310) :
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ?
_theResult___snd_fst_exp__h51586 :
_theResult___fst_exp__h16310) ;
assign _theResult___fst_exp__h51595 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
8'd0 :
_theResult___fst_exp__h51592 ;
assign _theResult___fst_exp__h57325 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard6815_0b0_0_0b1_0_0b10_out_exp7231_0b_ETC__q118 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3993 ;
assign _theResult___fst_exp__h57878 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_x7357_ETC__q120 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4040 ;
assign _theResult___fst_exp__h57881 =
(x__h57357[7:0] == 8'd255) ?
x__h57357[7:0] :
_theResult___fst_exp__h57878 ;
assign _theResult___fst_exp__h63179 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard2670_0b0_0_0b1_0_0b10_out_exp3086_0b_ETC__q143 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q145 ;
assign _theResult___fst_exp__h63731 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_x3211_ETC__q147 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4409 ;
assign _theResult___fst_exp__h63734 =
(x__h63211[7:0] == 8'd255) ?
x__h63211[7:0] :
_theResult___fst_exp__h63731 ;
assign _theResult___fst_exp__h74007 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard3497_0b0_0_0b1_0_0b10_out_exp3913_0b_ETC__q128 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4154 ;
assign _theResult___fst_exp__h74560 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_x4039_ETC__q130 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4201 ;
assign _theResult___fst_exp__h74563 =
(x__h74039[7:0] == 8'd255) ?
x__h74039[7:0] :
_theResult___fst_exp__h74560 ;
assign _theResult___fst_exp__h84306 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard3797_0b0_0_0b1_0_0b10_out_exp4213_0b_ETC__q73 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q75 ;
assign _theResult___fst_exp__h84858 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_x4338_ETC__q153 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4543 ;
assign _theResult___fst_exp__h84861 =
(x__h84338[7:0] == 8'd255) ?
x__h84338[7:0] :
_theResult___fst_exp__h84858 ;
assign _theResult___fst_sfd__h101209 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011) ?
52'd0 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_45_ETC__q5 ;
assign _theResult___fst_sfd__h117035 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q26 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d844 ;
assign _theResult___fst_sfd__h117038 =
(_theResult___fst_exp__h116281 == 11'd2047) ?
_theResult___snd__h116232[56:5] :
_theResult___fst_sfd__h117035 ;
assign _theResult___fst_sfd__h126682 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q24 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d871 ;
assign _theResult___fst_sfd__h126685 =
(_theResult___fst_exp__h125854 == 11'd2047) ?
sfdin__h125848[56:5] :
_theResult___fst_sfd__h126682 ;
assign _theResult___fst_sfd__h135464 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q28 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d890 ;
assign _theResult___fst_sfd__h135467 =
(_theResult___fst_exp__h134685 == 11'd2047) ?
_theResult___snd__h134631[56:5] :
_theResult___fst_sfd__h135464 ;
assign _theResult___fst_sfd__h135476 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ?
_theResult___snd_fst_sfd__h117041 :
_theResult___fst_sfd__h101209) :
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ?
_theResult___snd_fst_sfd__h135470 :
_theResult___fst_sfd__h101209) ;
assign _theResult___fst_sfd__h135482 =
((execFpuSimple_rVal1[30:23] == 8'd255 ||
execFpuSimple_rVal1[30:23] == 8'd0) &&
execFpuSimple_rVal1[22:0] == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h135476 ;
assign _theResult___fst_sfd__h144467 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q36 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1130 ;
assign _theResult___fst_sfd__h145223 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q38 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1148 ;
assign _theResult___fst_sfd__h145226 =
(x__h144498[10:0] == 11'd2047) ?
sfd___3__h143743[53:2] :
_theResult___fst_sfd__h145223 ;
assign _theResult___fst_sfd__h153857 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q66 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1774 ;
assign _theResult___fst_sfd__h154612 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q68 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1789 ;
assign _theResult___fst_sfd__h154615 =
(x__h153888[10:0] == 11'd2047) ?
sfd___3__h153134[53:2] :
_theResult___fst_sfd__h154612 ;
assign _theResult___fst_sfd__h16311 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011) ?
23'd0 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_83_ETC__q3 ;
assign _theResult___fst_sfd__h165091 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q48 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1553 ;
assign _theResult___fst_sfd__h165847 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q50 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1571 ;
assign _theResult___fst_sfd__h165850 =
(x__h165122[10:0] == 11'd2047) ?
sfd___3__h164367[62:11] :
_theResult___fst_sfd__h165847 ;
assign _theResult___fst_sfd__h175796 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q82 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2083 ;
assign _theResult___fst_sfd__h176551 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q84 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2098 ;
assign _theResult___fst_sfd__h176554 =
(x__h175827[10:0] == 11'd2047) ?
sfd___3__h175073[62:11] :
_theResult___fst_sfd__h176551 ;
assign _theResult___fst_sfd__h25062 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q108 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3739 ;
assign _theResult___fst_sfd__h25065 =
(_theResult___fst_exp__h24437 == 8'd255) ?
sfdin__h24431[56:34] :
_theResult___fst_sfd__h25062 ;
assign _theResult___fst_sfd__h33674 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q110 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3758 ;
assign _theResult___fst_sfd__h33677 =
(_theResult___fst_exp__h33123 == 8'd255) ?
_theResult___snd__h33074[56:34] :
_theResult___fst_sfd__h33674 ;
assign _theResult___fst_sfd__h42915 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q112 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3785 ;
assign _theResult___fst_sfd__h42918 =
(_theResult___fst_exp__h42290 == 8'd255) ?
sfdin__h42284[56:34] :
_theResult___fst_sfd__h42915 ;
assign _theResult___fst_sfd__h51581 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q114 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3804 ;
assign _theResult___fst_sfd__h51584 =
(_theResult___fst_exp__h51005 == 8'd255) ?
_theResult___snd__h50951[56:34] :
_theResult___fst_sfd__h51581 ;
assign _theResult___fst_sfd__h51593 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ?
_theResult___snd_fst_sfd__h33680 :
_theResult___fst_sfd__h16311) :
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ?
_theResult___snd_fst_sfd__h51587 :
_theResult___fst_sfd__h16311) ;
assign _theResult___fst_sfd__h51599 =
((execFpuSimple_rVal1[62:52] == 11'd2047 ||
execFpuSimple_rVal1[62:52] == 11'd0) &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
23'd0 :
_theResult___fst_sfd__h51593 ;
assign _theResult___fst_sfd__h57326 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q122 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4068 ;
assign _theResult___fst_sfd__h57879 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q124 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4086 ;
assign _theResult___fst_sfd__h57882 =
(x__h57357[7:0] == 8'd255) ?
sfd___3__h56805[30:8] :
_theResult___fst_sfd__h57879 ;
assign _theResult___fst_sfd__h63180 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q149 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4433 ;
assign _theResult___fst_sfd__h63732 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q151 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4448 ;
assign _theResult___fst_sfd__h63735 =
(x__h63211[7:0] == 8'd255) ?
sfd___3__h62660[30:8] :
_theResult___fst_sfd__h63732 ;
assign _theResult___fst_sfd__h74008 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q132 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4229 ;
assign _theResult___fst_sfd__h74561 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q134 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4247 ;
assign _theResult___fst_sfd__h74564 =
(x__h74039[7:0] == 8'd255) ?
sfd___3__h164367[62:40] :
_theResult___fst_sfd__h74561 ;
assign _theResult___fst_sfd__h84307 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q155 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4567 ;
assign _theResult___fst_sfd__h84859 =
(execFpuSimple_fpu_inst[3:1] != 3'b001 &&
execFpuSimple_fpu_inst[3:1] != 3'b010 &&
execFpuSimple_fpu_inst[3:1] != 3'b011 &&
execFpuSimple_fpu_inst[3:1] != 3'b100) ?
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q157 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4582 ;
assign _theResult___fst_sfd__h84862 =
(x__h84338[7:0] == 8'd255) ?
sfd___3__h175073[62:40] :
_theResult___fst_sfd__h84859 ;
assign _theResult___sfd__h116937 =
sfd__h116299[53] ?
((_theResult___fst_exp__h116281 == 11'd2046) ?
52'd0 :
sfd__h116299[52:1]) :
sfd__h116299[51:0] ;
assign _theResult___sfd__h126584 =
sfd__h125946[53] ?
((_theResult___fst_exp__h125854 == 11'd2046) ?
52'd0 :
sfd__h125946[52:1]) :
sfd__h125946[51:0] ;
assign _theResult___sfd__h135366 =
sfd__h134704[53] ?
((_theResult___fst_exp__h134685 == 11'd2046) ?
52'd0 :
sfd__h134704[52:1]) :
sfd__h134704[51:0] ;
assign _theResult___sfd__h144370 =
sfd__h143770[53] ? sfd__h143770[52:1] : sfd__h143770[51:0] ;
assign _theResult___sfd__h145126 =
sfd__h144513[53] ?
((x__h144498[10:0] == 11'd2046) ? 52'd0 : sfd__h144513[52:1]) :
sfd__h144513[51:0] ;
assign _theResult___sfd__h153761 =
sfd__h153161[53] ? sfd__h153161[52:1] : sfd__h153161[51:0] ;
assign _theResult___sfd__h154516 =
sfd__h153903[53] ?
((x__h153888[10:0] == 11'd2046) ? 52'd0 : sfd__h153903[52:1]) :
sfd__h153903[51:0] ;
assign _theResult___sfd__h164994 =
sfd__h164394[53] ? sfd__h164394[52:1] : sfd__h164394[51:0] ;
assign _theResult___sfd__h165750 =
sfd__h165137[53] ?
((x__h165122[10:0] == 11'd2046) ? 52'd0 : sfd__h165137[52:1]) :
sfd__h165137[51:0] ;
assign _theResult___sfd__h175700 =
sfd__h175100[53] ? sfd__h175100[52:1] : sfd__h175100[51:0] ;
assign _theResult___sfd__h176455 =
sfd__h175842[53] ?
((x__h175827[10:0] == 11'd2046) ? 52'd0 : sfd__h175842[52:1]) :
sfd__h175842[51:0] ;
assign _theResult___sfd__h24964 =
sfd__h24529[24] ?
((_theResult___fst_exp__h24437 == 8'd254) ?
23'd0 :
sfd__h24529[23:1]) :
sfd__h24529[22:0] ;
assign _theResult___sfd__h33576 =
sfd__h33141[24] ?
((_theResult___fst_exp__h33123 == 8'd254) ?
23'd0 :
sfd__h33141[23:1]) :
sfd__h33141[22:0] ;
assign _theResult___sfd__h42817 =
sfd__h42382[24] ?
((_theResult___fst_exp__h42290 == 8'd254) ?
23'd0 :
sfd__h42382[23:1]) :
sfd__h42382[22:0] ;
assign _theResult___sfd__h51483 =
sfd__h51024[24] ?
((_theResult___fst_exp__h51005 == 8'd254) ?
23'd0 :
sfd__h51024[23:1]) :
sfd__h51024[22:0] ;
assign _theResult___sfd__h57229 =
sfd__h56832[24] ? sfd__h56832[23:1] : sfd__h56832[22:0] ;
assign _theResult___sfd__h57782 =
sfd__h57372[24] ?
((x__h57357[7:0] == 8'd254) ? 23'd0 : sfd__h57372[23:1]) :
sfd__h57372[22:0] ;
assign _theResult___sfd__h63084 =
sfd__h62687[24] ? sfd__h62687[23:1] : sfd__h62687[22:0] ;
assign _theResult___sfd__h63636 =
sfd__h63226[24] ?
((x__h63211[7:0] == 8'd254) ? 23'd0 : sfd__h63226[23:1]) :
sfd__h63226[22:0] ;
assign _theResult___sfd__h73911 =
sfd__h73514[24] ? sfd__h73514[23:1] : sfd__h73514[22:0] ;
assign _theResult___sfd__h74464 =
sfd__h74054[24] ?
((x__h74039[7:0] == 8'd254) ? 23'd0 : sfd__h74054[23:1]) :
sfd__h74054[22:0] ;
assign _theResult___sfd__h84211 =
sfd__h83814[24] ? sfd__h83814[23:1] : sfd__h83814[22:0] ;
assign _theResult___sfd__h84763 =
sfd__h84353[24] ?
((x__h84338[7:0] == 8'd254) ? 23'd0 : sfd__h84353[23:1]) :
sfd__h84353[22:0] ;
assign _theResult___snd__h116232 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_theResult___snd__h116241 :
_theResult___snd__h116234 ;
assign _theResult___snd__h116234 = { execFpuSimple_rVal1[22:0], 34'd0 } ;
assign _theResult___snd__h116241 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322) ?
sfd__h97423 :
_theResult___snd__h116247 ;
assign _theResult___snd__h116247 =
{ IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q8[54:0],
2'd0 } ;
assign _theResult___snd__h116270 =
sfd__h97423 <<
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 ;
assign _theResult___snd__h125865 = { _theResult____h117618[55:0], 1'd0 } ;
assign _theResult___snd__h125876 =
(!_theResult____h117618[56] && _theResult____h117618[55]) ?
_theResult___snd__h125878 :
_theResult___snd__h125888 ;
assign _theResult___snd__h125878 = { _theResult____h117618[54:0], 2'd0 } ;
assign _theResult___snd__h125888 =
(!_theResult____h117618[56] && !_theResult____h117618[55] &&
!_theResult____h117618[54] &&
!_theResult____h117618[53] &&
!_theResult____h117618[52] &&
!_theResult____h117618[51] &&
!_theResult____h117618[50] &&
!_theResult____h117618[49] &&
!_theResult____h117618[48] &&
!_theResult____h117618[47] &&
!_theResult____h117618[46] &&
!_theResult____h117618[45] &&
!_theResult____h117618[44] &&
!_theResult____h117618[43] &&
!_theResult____h117618[42] &&
!_theResult____h117618[41] &&
!_theResult____h117618[40] &&
!_theResult____h117618[39] &&
!_theResult____h117618[38] &&
!_theResult____h117618[37] &&
!_theResult____h117618[36] &&
!_theResult____h117618[35] &&
!_theResult____h117618[34] &&
!_theResult____h117618[33] &&
!_theResult____h117618[32] &&
!_theResult____h117618[31] &&
!_theResult____h117618[30] &&
!_theResult____h117618[29] &&
!_theResult____h117618[28] &&
!_theResult____h117618[27] &&
!_theResult____h117618[26] &&
!_theResult____h117618[25] &&
!_theResult____h117618[24] &&
!_theResult____h117618[23] &&
!_theResult____h117618[22] &&
!_theResult____h117618[21] &&
!_theResult____h117618[20] &&
!_theResult____h117618[19] &&
!_theResult____h117618[18] &&
!_theResult____h117618[17] &&
!_theResult____h117618[16] &&
!_theResult____h117618[15] &&
!_theResult____h117618[14] &&
!_theResult____h117618[13] &&
!_theResult____h117618[12] &&
!_theResult____h117618[11] &&
!_theResult____h117618[10] &&
!_theResult____h117618[9] &&
!_theResult____h117618[8] &&
!_theResult____h117618[7] &&
!_theResult____h117618[6] &&
!_theResult____h117618[5] &&
!_theResult____h117618[4] &&
!_theResult____h117618[3] &&
!_theResult____h117618[2] &&
!_theResult____h117618[1] &&
!_theResult____h117618[0]) ?
_theResult____h117618 :
_theResult___snd__h125894 ;
assign _theResult___snd__h125894 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimpl_ETC__q12[54:0],
2'd0 } ;
assign _theResult___snd__h125917 =
_theResult____h117618 <<
IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678 ;
assign _theResult___snd__h134631 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_theResult___snd__h134645 :
_theResult___snd__h116234 ;
assign _theResult___snd__h134645 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322) ?
sfd__h97423 :
_theResult___snd__h134651 ;
assign _theResult___snd__h134651 =
{ IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q15[54:0],
2'd0 } ;
assign _theResult___snd__h134669 =
sfd__h97423 <<
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d752 ;
assign _theResult___snd__h24448 = { _theResult____h16328[55:0], 1'd0 } ;
assign _theResult___snd__h24459 =
(!_theResult____h16328[56] && _theResult____h16328[55]) ?
_theResult___snd__h24461 :
_theResult___snd__h24471 ;
assign _theResult___snd__h24461 = { _theResult____h16328[54:0], 2'd0 } ;
assign _theResult___snd__h24471 =
(!_theResult____h16328[56] && !_theResult____h16328[55] &&
!_theResult____h16328[54] &&
!_theResult____h16328[53] &&
!_theResult____h16328[52] &&
!_theResult____h16328[51] &&
!_theResult____h16328[50] &&
!_theResult____h16328[49] &&
!_theResult____h16328[48] &&
!_theResult____h16328[47] &&
!_theResult____h16328[46] &&
!_theResult____h16328[45] &&
!_theResult____h16328[44] &&
!_theResult____h16328[43] &&
!_theResult____h16328[42] &&
!_theResult____h16328[41] &&
!_theResult____h16328[40] &&
!_theResult____h16328[39] &&
!_theResult____h16328[38] &&
!_theResult____h16328[37] &&
!_theResult____h16328[36] &&
!_theResult____h16328[35] &&
!_theResult____h16328[34] &&
!_theResult____h16328[33] &&
!_theResult____h16328[32] &&
!_theResult____h16328[31] &&
!_theResult____h16328[30] &&
!_theResult____h16328[29] &&
!_theResult____h16328[28] &&
!_theResult____h16328[27] &&
!_theResult____h16328[26] &&
!_theResult____h16328[25] &&
!_theResult____h16328[24] &&
!_theResult____h16328[23] &&
!_theResult____h16328[22] &&
!_theResult____h16328[21] &&
!_theResult____h16328[20] &&
!_theResult____h16328[19] &&
!_theResult____h16328[18] &&
!_theResult____h16328[17] &&
!_theResult____h16328[16] &&
!_theResult____h16328[15] &&
!_theResult____h16328[14] &&
!_theResult____h16328[13] &&
!_theResult____h16328[12] &&
!_theResult____h16328[11] &&
!_theResult____h16328[10] &&
!_theResult____h16328[9] &&
!_theResult____h16328[8] &&
!_theResult____h16328[7] &&
!_theResult____h16328[6] &&
!_theResult____h16328[5] &&
!_theResult____h16328[4] &&
!_theResult____h16328[3] &&
!_theResult____h16328[2] &&
!_theResult____h16328[1] &&
!_theResult____h16328[0]) ?
_theResult____h16328 :
_theResult___snd__h24477 ;
assign _theResult___snd__h24477 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_ETC__q88[54:0],
2'd0 } ;
assign _theResult___snd__h24500 =
_theResult____h16328 <<
IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133 ;
assign _theResult___snd__h33074 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_theResult___snd__h33083 :
_theResult___snd__h33076 ;
assign _theResult___snd__h33076 = { execFpuSimple_rVal1[51:0], 5'd0 } ;
assign _theResult___snd__h33083 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899) ?
sfd__h8697 :
_theResult___snd__h33089 ;
assign _theResult___snd__h33089 =
{ IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q90[54:0],
2'd0 } ;
assign _theResult___snd__h33112 =
sfd__h8697 <<
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 ;
assign _theResult___snd__h42301 = { _theResult____h34054[55:0], 1'd0 } ;
assign _theResult___snd__h42312 =
(!_theResult____h34054[56] && _theResult____h34054[55]) ?
_theResult___snd__h42314 :
_theResult___snd__h42324 ;
assign _theResult___snd__h42314 = { _theResult____h34054[54:0], 2'd0 } ;
assign _theResult___snd__h42324 =
(!_theResult____h34054[56] && !_theResult____h34054[55] &&
!_theResult____h34054[54] &&
!_theResult____h34054[53] &&
!_theResult____h34054[52] &&
!_theResult____h34054[51] &&
!_theResult____h34054[50] &&
!_theResult____h34054[49] &&
!_theResult____h34054[48] &&
!_theResult____h34054[47] &&
!_theResult____h34054[46] &&
!_theResult____h34054[45] &&
!_theResult____h34054[44] &&
!_theResult____h34054[43] &&
!_theResult____h34054[42] &&
!_theResult____h34054[41] &&
!_theResult____h34054[40] &&
!_theResult____h34054[39] &&
!_theResult____h34054[38] &&
!_theResult____h34054[37] &&
!_theResult____h34054[36] &&
!_theResult____h34054[35] &&
!_theResult____h34054[34] &&
!_theResult____h34054[33] &&
!_theResult____h34054[32] &&
!_theResult____h34054[31] &&
!_theResult____h34054[30] &&
!_theResult____h34054[29] &&
!_theResult____h34054[28] &&
!_theResult____h34054[27] &&
!_theResult____h34054[26] &&
!_theResult____h34054[25] &&
!_theResult____h34054[24] &&
!_theResult____h34054[23] &&
!_theResult____h34054[22] &&
!_theResult____h34054[21] &&
!_theResult____h34054[20] &&
!_theResult____h34054[19] &&
!_theResult____h34054[18] &&
!_theResult____h34054[17] &&
!_theResult____h34054[16] &&
!_theResult____h34054[15] &&
!_theResult____h34054[14] &&
!_theResult____h34054[13] &&
!_theResult____h34054[12] &&
!_theResult____h34054[11] &&
!_theResult____h34054[10] &&
!_theResult____h34054[9] &&
!_theResult____h34054[8] &&
!_theResult____h34054[7] &&
!_theResult____h34054[6] &&
!_theResult____h34054[5] &&
!_theResult____h34054[4] &&
!_theResult____h34054[3] &&
!_theResult____h34054[2] &&
!_theResult____h34054[1] &&
!_theResult____h34054[0]) ?
_theResult____h34054 :
_theResult___snd__h42330 ;
assign _theResult___snd__h42330 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimpl_ETC__q94[54:0],
2'd0 } ;
assign _theResult___snd__h42353 =
_theResult____h34054 <<
IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574 ;
assign _theResult___snd__h50951 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_theResult___snd__h50965 :
_theResult___snd__h33076 ;
assign _theResult___snd__h50965 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899) ?
sfd__h8697 :
_theResult___snd__h50971 ;
assign _theResult___snd__h50971 =
{ IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q97[54:0],
2'd0 } ;
assign _theResult___snd__h50989 =
sfd__h8697 <<
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3648 ;
assign _theResult___snd_exp__h135722 =
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d1621 ?
11'd2047 :
_theResult___fst_exp__h135478 ;
assign _theResult___snd_exp__h145368 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 !=
52'd0) ?
11'd2047 :
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 ;
assign _theResult___snd_exp__h154745 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757 ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793 !=
52'd0) ?
11'd2047 :
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757 ;
assign _theResult___snd_exp__h165992 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 ==
11'd2047 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 !=
52'd0) ?
11'd2047 :
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 ;
assign _theResult___snd_exp__h176684 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065 ==
11'd2047 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102 !=
52'd0) ?
11'd2047 :
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065 ;
assign _theResult___snd_exp__h51881 =
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d4286 ?
8'd255 :
_theResult___fst_exp__h51595 ;
assign _theResult___snd_fst_exp__h117040 =
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 ?
11'd0 :
_theResult___fst_exp__h117037 ;
assign _theResult___snd_fst_exp__h135469 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_theResult___fst_exp__h126684 :
_theResult___fst_exp__h135466 ;
assign _theResult___snd_fst_exp__h145228 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 ?
_theResult___fst_exp__h144466 :
_theResult___fst_exp__h145225 ;
assign _theResult___snd_fst_exp__h145231 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 ?
11'd0 :
_theResult___snd_fst_exp__h145228 ;
assign _theResult___snd_fst_exp__h145234 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 ?
_theResult___snd_fst_exp__h145231 :
11'd2047 ;
assign _theResult___snd_fst_exp__h154617 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 ?
_theResult___fst_exp__h153856 :
_theResult___fst_exp__h154614 ;
assign _theResult___snd_fst_exp__h154620 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 ?
11'd0 :
_theResult___snd_fst_exp__h154617 ;
assign _theResult___snd_fst_exp__h154623 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 ?
_theResult___snd_fst_exp__h154620 :
11'd2047 ;
assign _theResult___snd_fst_exp__h165852 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 ?
_theResult___fst_exp__h165090 :
_theResult___fst_exp__h165849 ;
assign _theResult___snd_fst_exp__h165855 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 ?
11'd0 :
_theResult___snd_fst_exp__h165852 ;
assign _theResult___snd_fst_exp__h165858 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 ?
_theResult___snd_fst_exp__h165855 :
11'd2047 ;
assign _theResult___snd_fst_exp__h176556 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 ?
_theResult___fst_exp__h175795 :
_theResult___fst_exp__h176553 ;
assign _theResult___snd_fst_exp__h176559 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 ?
11'd0 :
_theResult___snd_fst_exp__h176556 ;
assign _theResult___snd_fst_exp__h176562 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 ?
_theResult___snd_fst_exp__h176559 :
11'd2047 ;
assign _theResult___snd_fst_exp__h33679 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_theResult___fst_exp__h25064 :
_theResult___fst_exp__h33676 ;
assign _theResult___snd_fst_exp__h51586 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_theResult___fst_exp__h42917 :
_theResult___fst_exp__h51583 ;
assign _theResult___snd_fst_exp__h57884 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 ?
_theResult___fst_exp__h57325 :
_theResult___fst_exp__h57881 ;
assign _theResult___snd_fst_exp__h57887 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 ?
8'd0 :
_theResult___snd_fst_exp__h57884 ;
assign _theResult___snd_fst_exp__h57890 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 ?
_theResult___snd_fst_exp__h57887 :
8'd255 ;
assign _theResult___snd_fst_exp__h63737 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 ?
_theResult___fst_exp__h63179 :
_theResult___fst_exp__h63734 ;
assign _theResult___snd_fst_exp__h63740 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 ?
8'd0 :
_theResult___snd_fst_exp__h63737 ;
assign _theResult___snd_fst_exp__h63743 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 ?
_theResult___snd_fst_exp__h63740 :
8'd255 ;
assign _theResult___snd_fst_exp__h74566 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 ?
_theResult___fst_exp__h74007 :
_theResult___fst_exp__h74563 ;
assign _theResult___snd_fst_exp__h74569 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 ?
8'd0 :
_theResult___snd_fst_exp__h74566 ;
assign _theResult___snd_fst_exp__h74572 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 ?
_theResult___snd_fst_exp__h74569 :
8'd255 ;
assign _theResult___snd_fst_exp__h84864 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 ?
_theResult___fst_exp__h84306 :
_theResult___fst_exp__h84861 ;
assign _theResult___snd_fst_exp__h84867 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 ?
8'd0 :
_theResult___snd_fst_exp__h84864 ;
assign _theResult___snd_fst_exp__h84870 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 ?
_theResult___snd_fst_exp__h84867 :
8'd255 ;
assign _theResult___snd_fst_sfd__h117041 =
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 ?
52'd0 :
_theResult___fst_sfd__h117038 ;
assign _theResult___snd_fst_sfd__h135470 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_theResult___fst_sfd__h126685 :
_theResult___fst_sfd__h135467 ;
assign _theResult___snd_fst_sfd__h145229 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 ?
_theResult___fst_sfd__h144467 :
_theResult___fst_sfd__h145226 ;
assign _theResult___snd_fst_sfd__h154618 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 ?
_theResult___fst_sfd__h153857 :
_theResult___fst_sfd__h154615 ;
assign _theResult___snd_fst_sfd__h165853 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 ?
_theResult___fst_sfd__h165091 :
_theResult___fst_sfd__h165850 ;
assign _theResult___snd_fst_sfd__h176557 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 ?
_theResult___fst_sfd__h175796 :
_theResult___fst_sfd__h176554 ;
assign _theResult___snd_fst_sfd__h33680 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_theResult___fst_sfd__h25065 :
_theResult___fst_sfd__h33677 ;
assign _theResult___snd_fst_sfd__h51587 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_theResult___fst_sfd__h42918 :
_theResult___fst_sfd__h51584 ;
assign _theResult___snd_fst_sfd__h57885 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 ?
_theResult___fst_sfd__h57326 :
_theResult___fst_sfd__h57882 ;
assign _theResult___snd_fst_sfd__h63738 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 ?
_theResult___fst_sfd__h63180 :
_theResult___fst_sfd__h63735 ;
assign _theResult___snd_fst_sfd__h74567 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 ?
_theResult___fst_sfd__h74008 :
_theResult___fst_sfd__h74564 ;
assign _theResult___snd_fst_sfd__h84865 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 ?
_theResult___fst_sfd__h84307 :
_theResult___fst_sfd__h84862 ;
assign _theResult___snd_fst_sfd__h8651 =
(execFpuSimple_rVal1[51:29] == 23'd0) ?
23'd2097152 :
execFpuSimple_rVal1[51:29] ;
assign _theResult___snd_fst_sfd__h97377 =
(execFpuSimple_rVal1[22:0] == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h97126 ;
assign _theResult___snd_sfd__h135723 =
(((execFpuSimple_rVal1[30:23] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h135478) ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 ;
assign _theResult___snd_sfd__h145369 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 ;
assign _theResult___snd_sfd__h154746 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757 ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793 ;
assign _theResult___snd_sfd__h165993 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 ==
11'd2047 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 ;
assign _theResult___snd_sfd__h176685 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065 ==
11'd2047 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102 ;
assign _theResult___snd_sfd__h51882 =
(((execFpuSimple_rVal1[62:52] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h51595) ==
8'd255 &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 !=
23'd0) ?
23'd4194304 :
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 ;
assign _theResult___snd_sfd__h96909 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
52'd0 :
dst_sfd__h96906 ;
assign _theResult___snd_sfd__h96969 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
52'd0 :
dst_sfd__h96966 ;
assign _theResult___snd_sfd__h97029 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
52'd0 :
dst_sfd__h97026 ;
assign amt_abs__h5775 =
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746[12] ?
~_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746 +
13'd1 :
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746 ;
assign amt_abs__h96298 =
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115[16] ?
~_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115 +
17'd1 :
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115 ;
assign din_inc___2_exp__h135501 = _theResult___fst_exp__h116281 + 11'd1 ;
assign din_inc___2_exp__h135531 = _theResult___fst_exp__h125854 + 11'd1 ;
assign din_inc___2_exp__h135555 = _theResult___fst_exp__h134685 + 11'd1 ;
assign din_inc___2_exp__h145267 = x__h144498[10:0] + 11'd1 ;
assign din_inc___2_exp__h154653 = x__h153888[10:0] + 11'd1 ;
assign din_inc___2_exp__h165891 = x__h165122[10:0] + 11'd1 ;
assign din_inc___2_exp__h176592 = x__h175827[10:0] + 11'd1 ;
assign din_inc___2_exp__h51614 = _theResult___fst_exp__h24437 + 8'd1 ;
assign din_inc___2_exp__h51638 = _theResult___fst_exp__h33123 + 8'd1 ;
assign din_inc___2_exp__h51668 = _theResult___fst_exp__h42290 + 8'd1 ;
assign din_inc___2_exp__h51692 = _theResult___fst_exp__h51005 + 8'd1 ;
assign din_inc___2_exp__h57923 = x__h57357[7:0] + 8'd1 ;
assign din_inc___2_exp__h63773 = x__h63211[7:0] + 8'd1 ;
assign din_inc___2_exp__h74605 = x__h74039[7:0] + 8'd1 ;
assign din_inc___2_exp__h84900 = x__h84338[7:0] + 8'd1 ;
assign dst_bits__h251 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
64'h000000007FFFFFFF :
_theResult___fst__h5722 ;
assign dst_bits__h256 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
64'hFFFFFFFFFFFFFFFF :
_theResult___fst__h6366 ;
assign dst_bits__h261 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
64'h7FFFFFFFFFFFFFFF :
_theResult___fst__h6963 ;
assign dst_bits__h266 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
64'hFFFFFFFFFFFFFFFF :
_theResult___fst__h7553 ;
assign dst_bits__h85486 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
64'h000000007FFFFFFF :
_theResult___fst__h94386 ;
assign dst_bits__h85491 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
64'hFFFFFFFFFFFFFFFF :
_theResult___fst__h95010 ;
assign dst_bits__h85496 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
64'h7FFFFFFFFFFFFFFF :
_theResult___fst__h95635 ;
assign dst_bits__h85501 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
64'hFFFFFFFFFFFFFFFF :
_theResult___fst__h96253 ;
assign dst_sfd__h96906 = { 51'd0, x__h176711 } ;
assign dst_sfd__h96966 = { 51'd0, x__h176838 } ;
assign dst_sfd__h97026 = { 51'd0, x__h176960 } ;
assign execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263 =
execFpuSimple_fpu_inst[8:4] == 5'd14 &&
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94412 != 116'd0 && execFpuSimple_rVal1[63] ||
int_val_rnd__h94412[115:64] != 52'd0)) ;
assign execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683 =
execFpuSimple_fpu_inst[8:4] == 5'd14 &&
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0 ||
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4680) ;
assign execFpuSimple_rVal1_BITS_30_TO_23_MINUS_127__q10 =
execFpuSimple_rVal1[30:23] - 8'd127 ;
assign execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_OR_ETC___d4052 =
execFpuSimple_rVal1[31:0] == 32'd0 ||
!value__h136325[31] &&
NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 ||
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 ;
assign execFpuSimple_rVal1_BITS_31_TO_0__q158 = execFpuSimple_rVal1[31:0] ;
assign execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129 =
execFpuSimple_rVal1[51:0] <= execFpuSimple_rVal2[51:0] ;
assign execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134 =
execFpuSimple_rVal1[51:0] < execFpuSimple_rVal2[51:0] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2192 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 &&
!execFpuSimple_rVal1[51] ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0 &&
!execFpuSimple_rVal2[51] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2198 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0 ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 =
execFpuSimple_rVal1[62:52] == execFpuSimple_rVal2[62:52] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126 =
execFpuSimple_rVal1[62:52] <= execFpuSimple_rVal2[62:52] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2138 =
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126 &&
(!execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 ||
execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129) &&
!execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132 &&
(!execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 ||
!execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134) ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132 =
execFpuSimple_rVal1[62:52] < execFpuSimple_rVal2[62:52] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_MINUS_1023__q92 =
execFpuSimple_rVal1[62:52] - 11'd1023 ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2636 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ==
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31]) ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2640 =
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2636 &&
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ^
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 <
IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630 ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2653 =
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2636 &&
!((execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ^
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 <=
IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630) ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2688 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ||
execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31]) &&
((execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) ?
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2685 :
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2686) ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2707 =
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
(execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31]) ||
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ||
execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31]) &&
IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2705 ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2735 =
{ execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
in1_exp__h4123 != 8'd255 &&
in1_exp__h4123 != 8'd0,
IF_execFpuSimple_rVal1_BITS_63_TO_32_EQ_0xFFFF_ETC__q85[0] } ;
assign execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418 =
execFpuSimple_rVal1[30] || execFpuSimple_rVal1[29] ||
execFpuSimple_rVal1[28] ||
execFpuSimple_rVal1[27] ||
execFpuSimple_rVal1[26] ||
execFpuSimple_rVal1[25] ||
execFpuSimple_rVal1[24] ||
execFpuSimple_rVal1[23] ||
execFpuSimple_rVal1[22] ||
execFpuSimple_rVal1[21] ||
execFpuSimple_rVal1[20] ||
execFpuSimple_rVal1[19] ||
execFpuSimple_rVal1[18] ||
execFpuSimple_rVal1[17] ||
execFpuSimple_rVal1[16] ||
execFpuSimple_rVal1[15] ||
execFpuSimple_rVal1[14] ||
execFpuSimple_rVal1[13] ||
execFpuSimple_rVal1[12] ||
execFpuSimple_rVal1[11] ||
execFpuSimple_rVal1[10] ||
execFpuSimple_rVal1[9] ||
execFpuSimple_rVal1[8] ||
execFpuSimple_rVal1[7] ||
execFpuSimple_rVal1[6] ||
execFpuSimple_rVal1[5] ||
execFpuSimple_rVal1[4] ||
execFpuSimple_rVal1[3] ||
execFpuSimple_rVal1[2] ||
execFpuSimple_rVal1[1] ||
execFpuSimple_rVal1[0] ;
assign execFpuSimple_rVal1_BIT_31_05_OR_execFpuSimple_ETC___d4895 =
(execFpuSimple_rVal1[31] ||
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418) &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 &&
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 &&
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4892 ;
assign execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439 =
execFpuSimple_rVal1[51] || execFpuSimple_rVal1[50] ||
execFpuSimple_rVal1[49] ||
execFpuSimple_rVal1[48] ||
execFpuSimple_rVal1[47] ||
execFpuSimple_rVal1[46] ||
execFpuSimple_rVal1[45] ||
execFpuSimple_rVal1[44] ||
execFpuSimple_rVal1[43] ||
execFpuSimple_rVal1[42] ||
execFpuSimple_rVal1[41] ||
execFpuSimple_rVal1[40] ||
execFpuSimple_rVal1[39] ||
execFpuSimple_rVal1[38] ||
execFpuSimple_rVal1[37] ||
execFpuSimple_rVal1[36] ||
execFpuSimple_rVal1[35] ||
execFpuSimple_rVal1[34] ||
execFpuSimple_rVal1[33] ||
execFpuSimple_rVal1[32] ||
execFpuSimple_rVal1[31] ||
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418 ;
assign execFpuSimple_rVal1_BIT_63_4_AND_NOT_execFpuSi_ETC___d65 =
execFpuSimple_rVal1[63] && !execFpuSimple_rVal2[63] ||
execFpuSimple_rVal1_BIT_63_4_EQ_execFpuSimple__ETC___d58 &&
execFpuSimple_rVal1[63] ^
execFpuSimple_rVal1[62:0] < execFpuSimple_rVal2[62:0] ;
assign execFpuSimple_rVal1_BIT_63_4_EQ_execFpuSimple__ETC___d58 =
execFpuSimple_rVal1[63] == execFpuSimple_rVal2[63] ;
assign execFpuSimple_rVal1_BIT_63_4_OR_NOT_execFpuSim_ETC___d2141 =
(execFpuSimple_rVal1[63] || !execFpuSimple_rVal2[63]) &&
(execFpuSimple_rVal1[63] ?
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2138 :
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_ex_ETC___d2139) ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2460 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
(!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 ||
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 &&
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 &&
_theResult___fst_exp__h176553 == 11'd2047 &&
_theResult___fst_sfd__h176554 == 52'd0) ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2497 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 &&
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 &&
IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2576 ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4788 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
(!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 ||
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 &&
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 &&
_theResult___fst_exp__h84861 == 8'd255 &&
_theResult___fst_sfd__h84862 == 23'd0) ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4828 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4913 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 &&
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 &&
IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4910 ;
assign guard__h108320 =
{ IF_theResult___snd16232_BIT_4_THEN_2_ELSE_0__q9[1],
{ _theResult___snd__h116232[3:0], 52'd0 } != 56'd0 } ;
assign guard__h117628 =
{ IF_sfdin25848_BIT_4_THEN_2_ELSE_0__q13[1],
{ sfdin__h125848[3:0], 52'd0 } != 56'd0 } ;
assign guard__h118226 = x__h118326 != 57'd0 ;
assign guard__h126695 =
{ IF_theResult___snd34631_BIT_4_THEN_2_ELSE_0__q16[1],
{ _theResult___snd__h134631[3:0], 52'd0 } != 56'd0 } ;
assign guard__h143753 =
{ IF_sfd___343743_BIT_2_THEN_2_ELSE_0__q29[1],
{ sfd___3__h143743[1:0], 52'd0 } != 54'd0 } ;
assign guard__h144483 =
{ IF_sfd___343743_BIT_1_THEN_2_ELSE_0__q30[1],
{ sfd___3__h143743[0], 53'd0 } != 54'd0 } ;
assign guard__h153144 =
{ IF_sfd___353134_BIT_2_THEN_2_ELSE_0__q58[1],
{ sfd___3__h153134[1:0], 52'd0 } != 54'd0 } ;
assign guard__h153873 =
{ IF_sfd___353134_BIT_1_THEN_2_ELSE_0__q59[1],
{ sfd___3__h153134[0], 53'd0 } != 54'd0 } ;
assign guard__h16338 =
{ IF_sfdin4431_BIT_33_THEN_2_ELSE_0__q89[1],
{ sfdin__h24431[32:0], 23'd0 } != 56'd0 } ;
assign guard__h164377 =
{ IF_sfd___364367_BIT_11_THEN_2_ELSE_0__q41[1],
{ sfd___3__h164367[10:0], 52'd0 } != 63'd0 } ;
assign guard__h165107 =
{ IF_sfd___364367_BIT_10_THEN_2_ELSE_0__q42[1],
{ sfd___3__h164367[9:0], 53'd0 } != 63'd0 } ;
assign guard__h175083 =
{ IF_sfd___375073_BIT_11_THEN_2_ELSE_0__q71[1],
{ sfd___3__h175073[10:0], 52'd0 } != 63'd0 } ;
assign guard__h175812 =
{ IF_sfd___375073_BIT_10_THEN_2_ELSE_0__q72[1],
{ sfd___3__h175073[9:0], 53'd0 } != 63'd0 } ;
assign guard__h25075 =
{ IF_theResult___snd3074_BIT_33_THEN_2_ELSE_0__q91[1],
{ _theResult___snd__h33074[32:0], 23'd0 } != 56'd0 } ;
assign guard__h34064 =
{ IF_sfdin2284_BIT_33_THEN_2_ELSE_0__q95[1],
{ sfdin__h42284[32:0], 23'd0 } != 56'd0 } ;
assign guard__h34662 = x__h34762 != 57'd0 ;
assign guard__h42928 =
{ IF_theResult___snd0951_BIT_33_THEN_2_ELSE_0__q98[1],
{ _theResult___snd__h50951[32:0], 23'd0 } != 56'd0 } ;
assign guard__h56815 =
{ IF_sfd___36805_BIT_8_THEN_2_ELSE_0__q115[1],
{ sfd___3__h56805[7:0], 23'd0 } != 31'd0 } ;
assign guard__h57342 =
{ IF_sfd___36805_BIT_7_THEN_2_ELSE_0__q116[1],
{ sfd___3__h56805[6:0], 24'd0 } != 31'd0 } ;
assign guard__h62670 =
{ IF_sfd___32660_BIT_8_THEN_2_ELSE_0__q141[1],
{ sfd___3__h62660[7:0], 23'd0 } != 31'd0 } ;
assign guard__h63196 =
{ IF_sfd___32660_BIT_7_THEN_2_ELSE_0__q142[1],
{ sfd___3__h62660[6:0], 24'd0 } != 31'd0 } ;
assign guard__h73497 =
{ IF_sfd___364367_BIT_40_THEN_2_ELSE_0__q39[1],
{ sfd___3__h164367[39:0], 23'd0 } != 63'd0 } ;
assign guard__h74024 =
{ IF_sfd___364367_BIT_39_THEN_2_ELSE_0__q40[1],
{ sfd___3__h164367[38:0], 24'd0 } != 63'd0 } ;
assign guard__h83797 =
{ IF_sfd___375073_BIT_40_THEN_2_ELSE_0__q69[1],
{ sfd___3__h175073[39:0], 23'd0 } != 63'd0 } ;
assign guard__h84323 =
{ IF_sfd___375073_BIT_39_THEN_2_ELSE_0__q70[1],
{ sfd___3__h175073[38:0], 24'd0 } != 63'd0 } ;
assign in1_exp__h4123 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal1[30:23] :
8'd255 ;
assign in1_sfd__h4124 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal1[22:0] :
23'd4194304 ;
assign in2_exp__h4198 =
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal2[30:23] :
8'd255 ;
assign in2_sfd__h4199 =
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal2[22:0] :
23'd4194304 ;
assign int_val__h5743 =
{ 64'b0000000000000000000000000000000000000000000000000000000000000001,
in1_sfd__h4124,
2'b0 } ;
assign int_val__h5744 =
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746[12] ?
shifted__h5776 | y__h5935 :
shifted__h5776 | y__h6030 ;
assign int_val__h94407 =
{ 64'b0000000000000000000000000000000000000000000000000000000000000001,
execFpuSimple_rVal1[51:0],
2'b0 } ;
assign int_val__h94408 =
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115[16] ?
shifted__h94440 | y__h94627 :
shifted__h94440 | y__h94722 ;
assign int_val_rnd4412_BITS_31_TO_0__q7 = int_val_rnd__h94412[31:0] ;
assign int_val_rnd748_BITS_31_TO_0__q87 = int_val_rnd__h5748[31:0] ;
assign int_val_rnd__h5748 =
int_val__h5744[88:2] +
((int_val__h5744[1:0] != 2'd0 &&
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2781) ?
87'd1 :
87'd0) ;
assign int_val_rnd__h94412 =
int_val__h94408[117:2] +
((int_val__h94408[1:0] != 2'd0 &&
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d164) ?
116'd1 :
116'd0) ;
assign max_val__h5764 =
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
32'h80000000 :
32'h7FFFFFFF ;
assign max_val__h7005 =
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign max_val__h94428 =
(int_val_rnd__h94412 != 116'd0 && execFpuSimple_rVal1[63]) ?
32'h80000000 :
32'h7FFFFFFF ;
assign max_val__h95677 =
(int_val_rnd__h94412 != 116'd0 && execFpuSimple_rVal1[63]) ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign out___1_sfd__h97126 = { execFpuSimple_rVal1[22:0], 29'd0 } ;
assign out__h5724 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
64'hFFFFFFFF80000000 :
64'h000000007FFFFFFF ;
assign out__h6306 = { {32{val__h6305[31]}}, val__h6305 } ;
assign out__h6311 = { {32{max_val__h5764[31]}}, max_val__h5764 } ;
assign out__h6368 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
64'd0 :
64'hFFFFFFFFFFFFFFFF ;
assign out__h6900 =
{ {32{int_val_rnd748_BITS_31_TO_0__q87[31]}},
int_val_rnd748_BITS_31_TO_0__q87 } ;
assign out__h6965 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign out__h7498 =
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
~int_val_rnd__h5748[63:0] + 64'd1 :
int_val_rnd__h5748[63:0] ;
assign out__h94388 =
execFpuSimple_rVal1[63] ?
64'hFFFFFFFF80000000 :
64'h000000007FFFFFFF ;
assign out__h94950 = { {32{val__h94949[31]}}, val__h94949 } ;
assign out__h94955 = { {32{max_val__h94428[31]}}, max_val__h94428 } ;
assign out__h95012 =
execFpuSimple_rVal1[63] ? 64'd0 : 64'hFFFFFFFFFFFFFFFF ;
assign out__h95572 =
{ {32{int_val_rnd4412_BITS_31_TO_0__q7[31]}},
int_val_rnd4412_BITS_31_TO_0__q7 } ;
assign out__h95637 =
execFpuSimple_rVal1[63] ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign out__h96198 =
(int_val_rnd__h94412 != 116'd0 && execFpuSimple_rVal1[63]) ?
~int_val_rnd__h94412[63:0] + 64'd1 :
int_val_rnd__h94412[63:0] ;
assign out_exp__h116939 =
_theResult___snd__h116232[5] ?
_theResult___exp__h116936 :
_theResult___fst_exp__h116281 ;
assign out_exp__h126586 =
sfdin__h125848[5] ?
_theResult___exp__h126583 :
_theResult___fst_exp__h125854 ;
assign out_exp__h135368 =
_theResult___snd__h134631[5] ?
_theResult___exp__h135365 :
_theResult___fst_exp__h134685 ;
assign out_exp__h144372 =
sfd___3__h143743[3] ? _theResult___exp__h144369 : 11'd0 ;
assign out_exp__h145128 =
sfd___3__h143743[2] ?
_theResult___exp__h145125 :
x__h144498[10:0] ;
assign out_exp__h153763 =
sfd___3__h153134[3] ? _theResult___exp__h153760 : 11'd0 ;
assign out_exp__h154518 =
sfd___3__h153134[2] ?
_theResult___exp__h154515 :
x__h153888[10:0] ;
assign out_exp__h164996 =
sfd___3__h164367[12] ? _theResult___exp__h164993 : 11'd0 ;
assign out_exp__h165752 =
sfd___3__h164367[11] ?
_theResult___exp__h165749 :
x__h165122[10:0] ;
assign out_exp__h175702 =
sfd___3__h175073[12] ? _theResult___exp__h175699 : 11'd0 ;
assign out_exp__h176457 =
sfd___3__h175073[11] ?
_theResult___exp__h176454 :
x__h175827[10:0] ;
assign out_exp__h24966 =
sfdin__h24431[34] ?
_theResult___exp__h24963 :
_theResult___fst_exp__h24437 ;
assign out_exp__h33578 =
_theResult___snd__h33074[34] ?
_theResult___exp__h33575 :
_theResult___fst_exp__h33123 ;
assign out_exp__h42819 =
sfdin__h42284[34] ?
_theResult___exp__h42816 :
_theResult___fst_exp__h42290 ;
assign out_exp__h51485 =
_theResult___snd__h50951[34] ?
_theResult___exp__h51482 :
_theResult___fst_exp__h51005 ;
assign out_exp__h57231 =
sfd___3__h56805[9] ? _theResult___exp__h57228 : 8'd0 ;
assign out_exp__h57784 =
sfd___3__h56805[8] ? _theResult___exp__h57781 : x__h57357[7:0] ;
assign out_exp__h63086 =
sfd___3__h62660[9] ? _theResult___exp__h63083 : 8'd0 ;
assign out_exp__h63638 =
sfd___3__h62660[8] ? _theResult___exp__h63635 : x__h63211[7:0] ;
assign out_exp__h73913 =
sfd___3__h164367[41] ? _theResult___exp__h73910 : 8'd0 ;
assign out_exp__h74466 =
sfd___3__h164367[40] ?
_theResult___exp__h74463 :
x__h74039[7:0] ;
assign out_exp__h84213 =
sfd___3__h175073[41] ? _theResult___exp__h84210 : 8'd0 ;
assign out_exp__h84765 =
sfd___3__h175073[40] ?
_theResult___exp__h84762 :
x__h84338[7:0] ;
assign out_sfd__h116940 =
_theResult___snd__h116232[5] ?
_theResult___sfd__h116937 :
_theResult___snd__h116232[56:5] ;
assign out_sfd__h126587 =
sfdin__h125848[5] ?
_theResult___sfd__h126584 :
sfdin__h125848[56:5] ;
assign out_sfd__h135369 =
_theResult___snd__h134631[5] ?
_theResult___sfd__h135366 :
_theResult___snd__h134631[56:5] ;
assign out_sfd__h144373 =
sfd___3__h143743[3] ?
_theResult___sfd__h144370 :
sfd___3__h143743[54:3] ;
assign out_sfd__h145129 =
sfd___3__h143743[2] ?
_theResult___sfd__h145126 :
sfd___3__h143743[53:2] ;
assign out_sfd__h153764 =
sfd___3__h153134[3] ?
_theResult___sfd__h153761 :
sfd___3__h153134[54:3] ;
assign out_sfd__h154519 =
sfd___3__h153134[2] ?
_theResult___sfd__h154516 :
sfd___3__h153134[53:2] ;
assign out_sfd__h164997 =
sfd___3__h164367[12] ?
_theResult___sfd__h164994 :
sfd___3__h164367[63:12] ;
assign out_sfd__h165753 =
sfd___3__h164367[11] ?
_theResult___sfd__h165750 :
sfd___3__h164367[62:11] ;
assign out_sfd__h175703 =
sfd___3__h175073[12] ?
_theResult___sfd__h175700 :
sfd___3__h175073[63:12] ;
assign out_sfd__h176458 =
sfd___3__h175073[11] ?
_theResult___sfd__h176455 :
sfd___3__h175073[62:11] ;
assign out_sfd__h24967 =
sfdin__h24431[34] ?
_theResult___sfd__h24964 :
sfdin__h24431[56:34] ;
assign out_sfd__h33579 =
_theResult___snd__h33074[34] ?
_theResult___sfd__h33576 :
_theResult___snd__h33074[56:34] ;
assign out_sfd__h42820 =
sfdin__h42284[34] ?
_theResult___sfd__h42817 :
sfdin__h42284[56:34] ;
assign out_sfd__h51486 =
_theResult___snd__h50951[34] ?
_theResult___sfd__h51483 :
_theResult___snd__h50951[56:34] ;
assign out_sfd__h57232 =
sfd___3__h56805[9] ?
_theResult___sfd__h57229 :
sfd___3__h56805[31:9] ;
assign out_sfd__h57785 =
sfd___3__h56805[8] ?
_theResult___sfd__h57782 :
sfd___3__h56805[30:8] ;
assign out_sfd__h63087 =
sfd___3__h62660[9] ?
_theResult___sfd__h63084 :
sfd___3__h62660[31:9] ;
assign out_sfd__h63639 =
sfd___3__h62660[8] ?
_theResult___sfd__h63636 :
sfd___3__h62660[30:8] ;
assign out_sfd__h73914 =
sfd___3__h164367[41] ?
_theResult___sfd__h73911 :
sfd___3__h164367[63:41] ;
assign out_sfd__h74467 =
sfd___3__h164367[40] ?
_theResult___sfd__h74464 :
sfd___3__h164367[62:40] ;
assign out_sfd__h84214 =
sfd___3__h175073[41] ?
_theResult___sfd__h84211 :
sfd___3__h175073[63:41] ;
assign out_sfd__h84766 =
sfd___3__h175073[40] ?
_theResult___sfd__h84763 :
sfd___3__h175073[62:40] ;
assign result__h118231 =
{ _0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_30_TO__ETC___d436[56:1],
_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_30_TO__ETC___d436[0] |
guard__h118226 } ;
assign result__h34667 =
{ _0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_62_TO__ETC___d3334[56:1],
_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_62_TO__ETC___d3334[0] |
guard__h34662 } ;
assign saturated_bit__h5778 = x__h5981 != 89'd0 ;
assign saturated_bit__h94442 = x__h94673 != 118'd0 ;
assign sfd___3__h143743 =
sfd__h135742 <<
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d1011 ;
assign sfd___3__h153134 =
sfd__h145382 <<
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d1666 ;
assign sfd___3__h164367 =
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178 <<
IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434 ;
assign sfd___3__h175073 =
execFpuSimple_rVal1 <<
IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976 ;
assign sfd___3__h56805 =
value__h136325 <<
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d3949 ;
assign sfd___3__h62660 =
execFpuSimple_rVal1[31:0] <<
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d4326 ;
assign sfd__h116299 =
{ 1'b0,
_theResult___fst_exp__h116281 != 11'd0,
_theResult___snd__h116232[56:5] } +
54'd1 ;
assign sfd__h125946 =
{ 1'b0,
_theResult___fst_exp__h125854 != 11'd0,
sfdin__h125848[56:5] } +
54'd1 ;
assign sfd__h134704 =
{ 1'b0,
_theResult___fst_exp__h134685 != 11'd0,
_theResult___snd__h134631[56:5] } +
54'd1 ;
assign sfd__h135742 = { value__h136325, 23'd0 } ;
assign sfd__h143770 = { 2'd0, sfd___3__h143743[54:3] } + 54'd1 ;
assign sfd__h144513 =
{ 1'b0, x__h144498[10:0] != 11'd0, sfd___3__h143743[53:2] } +
54'd1 ;
assign sfd__h145382 = { execFpuSimple_rVal1[31:0], 23'd0 } ;
assign sfd__h153161 = { 2'd0, sfd___3__h153134[54:3] } + 54'd1 ;
assign sfd__h153903 =
{ 1'b0, x__h153888[10:0] != 11'd0, sfd___3__h153134[53:2] } +
54'd1 ;
assign sfd__h164394 = { 2'd0, sfd___3__h164367[63:12] } + 54'd1 ;
assign sfd__h165137 =
{ 1'b0, x__h165122[10:0] != 11'd0, sfd___3__h164367[62:11] } +
54'd1 ;
assign sfd__h175100 = { 2'd0, sfd___3__h175073[63:12] } + 54'd1 ;
assign sfd__h175842 =
{ 1'b0, x__h175827[10:0] != 11'd0, sfd___3__h175073[62:11] } +
54'd1 ;
assign sfd__h24529 =
{ 1'b0,
_theResult___fst_exp__h24437 != 8'd0,
sfdin__h24431[56:34] } +
25'd1 ;
assign sfd__h33141 =
{ 1'b0,
_theResult___fst_exp__h33123 != 8'd0,
_theResult___snd__h33074[56:34] } +
25'd1 ;
assign sfd__h42382 =
{ 1'b0,
_theResult___fst_exp__h42290 != 8'd0,
sfdin__h42284[56:34] } +
25'd1 ;
assign sfd__h51024 =
{ 1'b0,
_theResult___fst_exp__h51005 != 8'd0,
_theResult___snd__h50951[56:34] } +
25'd1 ;
assign sfd__h56832 = { 2'd0, sfd___3__h56805[31:9] } + 25'd1 ;
assign sfd__h57372 =
{ 1'b0, x__h57357[7:0] != 8'd0, sfd___3__h56805[30:8] } + 25'd1 ;
assign sfd__h62687 = { 2'd0, sfd___3__h62660[31:9] } + 25'd1 ;
assign sfd__h63226 =
{ 1'b0, x__h63211[7:0] != 8'd0, sfd___3__h62660[30:8] } + 25'd1 ;
assign sfd__h73514 = { 2'd0, sfd___3__h164367[63:41] } + 25'd1 ;
assign sfd__h74054 =
{ 1'b0, x__h74039[7:0] != 8'd0, sfd___3__h164367[62:40] } +
25'd1 ;
assign sfd__h83814 = { 2'd0, sfd___3__h175073[63:41] } + 25'd1 ;
assign sfd__h84353 =
{ 1'b0, x__h84338[7:0] != 8'd0, sfd___3__h175073[62:40] } +
25'd1 ;
assign sfd__h8697 = { value__h16950, 3'd0 } ;
assign sfd__h97423 = { value__h101838, 32'd0 } ;
assign sfdin__h125848 =
_theResult____h117618[56] ?
_theResult___snd__h125865 :
_theResult___snd__h125876 ;
assign sfdin__h24431 =
_theResult____h16328[56] ?
_theResult___snd__h24448 :
_theResult___snd__h24459 ;
assign sfdin__h42284 =
_theResult____h34054[56] ?
_theResult___snd__h42301 :
_theResult___snd__h42312 ;
assign shifted__h5776 =
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746[12] ?
int_val__h5743 << amt_abs__h5775 :
int_val__h5743 >> amt_abs__h5775 ;
assign shifted__h94440 =
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115[16] ?
int_val__h94407 << amt_abs__h96298 :
int_val__h94407 >> amt_abs__h96298 ;
assign shifted_out_mask__h5777 =
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746[12] ?
~x__h5994 :
~x__h6017 ;
assign shifted_out_mask__h96300 =
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115[16] ?
~x__h96545 :
~x__h96568 ;
assign val__h6305 =
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
~int_val_rnd__h5748[31:0] + 32'd1 :
int_val_rnd__h5748[31:0] ;
assign val__h94949 =
(int_val_rnd__h94412 != 116'd0 && execFpuSimple_rVal1[63]) ?
~int_val_rnd__h94412[31:0] + 32'd1 :
int_val_rnd__h94412[31:0] ;
assign value__h101838 =
{ 1'b0,
execFpuSimple_rVal1[30:23] != 8'd0,
execFpuSimple_rVal1[22:0] } ;
assign value__h136325 =
execFpuSimple_rVal1[31] ?
-execFpuSimple_rVal1[31:0] :
execFpuSimple_rVal1[31:0] ;
assign value__h16950 =
{ 1'b0,
execFpuSimple_rVal1[62:52] != 11'd0,
execFpuSimple_rVal1[51:0] } ;
assign x__h118326 = sfd__h97423 << x__h118359 ;
assign x__h118359 =
12'd57 -
_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432 ;
assign x__h144498 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 +
12'd1023 ;
assign x__h153888 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 +
12'd1023 ;
assign x__h165122 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 +
12'd1023 ;
assign x__h175827 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 +
12'd1023 ;
assign x__h176711 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal2[62:52] != 11'd2047 ||
execFpuSimple_rVal2[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0 &&
execFpuSimple_rVal2[62:52] == 11'd0 &&
execFpuSimple_rVal2[51:0] == 52'd0 ||
(!execFpuSimple_rVal1[63] || execFpuSimple_rVal2[63]) &&
execFpuSimple_rVal1_BIT_63_4_OR_NOT_execFpuSim_ETC___d2141) ;
assign x__h176838 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal2[62:52] != 11'd2047 ||
execFpuSimple_rVal2[51:0] == 52'd0) &&
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9_ETC___d2160 ;
assign x__h176960 = x__h176838 || x__h176711 ;
assign x__h219 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 &&
in2_exp__h4198 == 8'd255 &&
in2_sfd__h4199 != 23'd0) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2644 } ;
assign x__h224 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 &&
in2_exp__h4198 == 8'd255 &&
in2_sfd__h4199 != 23'd0) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2657 } ;
assign x__h34762 = sfd__h8697 << x__h34795 ;
assign x__h34795 =
12'd57 -
_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330 ;
assign x__h4067 =
{ execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31],
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 } ;
assign x__h4081 =
{ execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31],
IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630 } ;
assign x__h4245 = { 63'd0, x__h4248 } ;
assign x__h4248 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in2_exp__h4198 != 8'd255 || in2_sfd__h4199 == 23'd0) &&
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2690 ;
assign x__h4413 = { 63'd0, x__h4416 } ;
assign x__h4416 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in2_exp__h4198 != 8'd255 || in2_sfd__h4199 == 23'd0) &&
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2708 ;
assign x__h4568 = { 63'd0, x__h4571 } ;
assign x__h4571 = x__h4416 || x__h4248 ;
assign x__h4812 =
{ in1_exp__h4123 == 8'd255 && in1_sfd__h4124[22],
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 &&
!in1_sfd__h4124[22],
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
in1_exp__h4123 == 8'd255 &&
in1_sfd__h4124 == 23'd0,
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
in1_exp__h4123 != 8'd255 &&
in1_exp__h4123 != 8'd0,
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
in1_exp__h4123 == 8'd0 &&
in1_sfd__h4124 != 23'd0,
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
in1_exp__h4123 == 8'd0 &&
in1_sfd__h4124 == 23'd0,
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
in1_exp__h4123 == 8'd0 &&
in1_sfd__h4124 == 23'd0,
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
in1_exp__h4123 == 8'd0 &&
in1_sfd__h4124 != 23'd0,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2735 } ;
assign x__h57357 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 +
9'd127 ;
assign x__h5981 = int_val__h5743 & shifted_out_mask__h5777 ;
assign x__h5994 = 89'h1FFFFFFFFFFFFFFFFFFFFFF >> amt_abs__h5775 ;
assign x__h6017 = 89'h1FFFFFFFFFFFFFFFFFFFFFF << amt_abs__h5775 ;
assign x__h63211 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 +
9'd127 ;
assign x__h74039 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 +
9'd127 ;
assign x__h8101 =
{ execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 } ;
assign x__h84338 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 +
9'd127 ;
assign x__h85464 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 &&
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
64'h7FF8000000000000 :
((execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
execFpuSimple_rVal1 :
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d67) ;
assign x__h85469 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 &&
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
64'h7FF8000000000000 :
((execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
execFpuSimple_rVal1 :
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d78) ;
assign x__h93102 =
{ execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51],
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 &&
!execFpuSimple_rVal1[51],
!execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0,
!execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] != 11'd2047 &&
execFpuSimple_rVal1[62:52] != 11'd0,
!execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] != 52'd0,
!execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0,
execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0,
execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] != 52'd0,
execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] != 11'd2047 &&
execFpuSimple_rVal1[62:52] != 11'd0,
IF_execFpuSimple_rVal1_BIT_63_AND_execFpuSimpl_ETC__q1[0] } ;
assign x__h94673 = int_val__h94407 & shifted_out_mask__h96300 ;
assign x__h96545 = 118'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFF >> amt_abs__h96298 ;
assign x__h96568 = 118'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFF << amt_abs__h96298 ;
assign y__h5935 = { saturated_bit__h5778, 88'd0 } ;
assign y__h6030 = { 88'd0, saturated_bit__h5778 } ;
assign y__h94627 = { saturated_bit__h94442, 117'd0 } ;
assign y__h94722 = { 117'd0, saturated_bit__h94442 } ;
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_25_ETC__q2 = 8'd254;
3'b010:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_25_ETC__q2 =
execFpuSimple_rVal1[63] ? 8'd255 : 8'd254;
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_25_ETC__q2 =
execFpuSimple_rVal1[63] ? 8'd254 : 8'd255;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_25_ETC__q2 = 8'd0;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_83_ETC__q3 =
23'd8388607;
3'b010:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_83_ETC__q3 =
execFpuSimple_rVal1[63] ? 23'd0 : 23'd8388607;
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_83_ETC__q3 =
execFpuSimple_rVal1[63] ? 23'd8388607 : 23'd0;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_83_ETC__q3 = 23'd0;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_20_ETC__q4 = 11'd2046;
3'b010:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_20_ETC__q4 =
execFpuSimple_rVal1[31] ? 11'd2047 : 11'd2046;
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_20_ETC__q4 =
execFpuSimple_rVal1[31] ? 11'd2046 : 11'd2047;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_20_ETC__q4 = 11'd0;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_45_ETC__q5 =
52'hFFFFFFFFFFFFF;
3'b010:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_45_ETC__q5 =
execFpuSimple_rVal1[31] ? 52'd0 : 52'hFFFFFFFFFFFFF;
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_45_ETC__q5 =
execFpuSimple_rVal1[31] ? 52'hFFFFFFFFFFFFF : 52'd0;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b1_45_ETC__q5 = 52'd0;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or int_val__h94408)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q6 =
!execFpuSimple_rVal1[63];
3'b100:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q6 =
int_val__h94408[1];
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q6 =
execFpuSimple_fpu_inst[3:1] == 3'b010 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h108320 or
_theResult___fst_exp__h116281 or _theResult___exp__h116936)
begin
case (guard__h108320)
2'b0:
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q17 =
_theResult___fst_exp__h116281;
2'b01, 2'b10, 2'b11:
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q17 =
_theResult___exp__h116936;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h116281 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d409 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d407 or
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q17)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d413 =
_theResult___fst_exp__h116281;
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d413 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d409;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d413 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d407;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d413 =
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q17;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d413 =
11'd0;
endcase
end
always@(guard__h108320 or
_theResult___fst_exp__h116281 or
out_exp__h116939 or _theResult___exp__h116936)
begin
case (guard__h108320)
2'b0, 2'b01:
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q18 =
_theResult___fst_exp__h116281;
2'b10:
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q18 =
out_exp__h116939;
2'b11:
CASE_guard08320_0b0_theResult___fst_exp16281_0_ETC__q18 =
_theResult___exp__h116936;
endcase
end
always@(guard__h117628 or
_theResult___fst_exp__h125854 or _theResult___exp__h126583)
begin
case (guard__h117628)
2'b0:
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q19 =
_theResult___fst_exp__h125854;
2'b01, 2'b10, 2'b11:
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q19 =
_theResult___exp__h126583;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h125854 or
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d739 or
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d737 or
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q19)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d743 =
_theResult___fst_exp__h125854;
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d743 =
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d739;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d743 =
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d737;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d743 =
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q19;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d743 =
11'd0;
endcase
end
always@(guard__h117628 or
_theResult___fst_exp__h125854 or
out_exp__h126586 or _theResult___exp__h126583)
begin
case (guard__h117628)
2'b0, 2'b01:
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q20 =
_theResult___fst_exp__h125854;
2'b10:
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q20 =
out_exp__h126586;
2'b11:
CASE_guard17628_0b0_theResult___fst_exp25854_0_ETC__q20 =
_theResult___exp__h126583;
endcase
end
always@(guard__h126695 or
_theResult___fst_exp__h134685 or _theResult___exp__h135365)
begin
case (guard__h126695)
2'b0:
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q21 =
_theResult___fst_exp__h134685;
2'b01, 2'b10, 2'b11:
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q21 =
_theResult___exp__h135365;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h134685 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d808 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d806 or
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q21)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d812 =
_theResult___fst_exp__h134685;
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d812 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d808;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d812 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d806;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d812 =
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q21;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d812 =
11'd0;
endcase
end
always@(guard__h126695 or
_theResult___fst_exp__h134685 or
out_exp__h135368 or _theResult___exp__h135365)
begin
case (guard__h126695)
2'b0, 2'b01:
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q22 =
_theResult___fst_exp__h134685;
2'b10:
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q22 =
out_exp__h135368;
2'b11:
CASE_guard26695_0b0_theResult___fst_exp34685_0_ETC__q22 =
_theResult___exp__h135365;
endcase
end
always@(guard__h117628 or sfdin__h125848 or _theResult___sfd__h126584)
begin
case (guard__h117628)
2'b0:
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q23 =
sfdin__h125848[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q23 =
_theResult___sfd__h126584;
endcase
end
always@(execFpuSimple_fpu_inst or
sfdin__h125848 or
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d867 or
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d865 or
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q23)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d871 =
sfdin__h125848[56:5];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d871 =
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d867;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d871 =
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d865;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d871 =
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q23;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d871 =
52'd0;
endcase
end
always@(guard__h117628 or
sfdin__h125848 or out_sfd__h126587 or _theResult___sfd__h126584)
begin
case (guard__h117628)
2'b0, 2'b01:
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q24 =
sfdin__h125848[56:5];
2'b10:
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q24 =
out_sfd__h126587;
2'b11:
CASE_guard17628_0b0_sfdin25848_BITS_56_TO_5_0b_ETC__q24 =
_theResult___sfd__h126584;
endcase
end
always@(guard__h108320 or
_theResult___snd__h116232 or _theResult___sfd__h116937)
begin
case (guard__h108320)
2'b0:
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q25 =
_theResult___snd__h116232[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q25 =
_theResult___sfd__h116937;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___snd__h116232 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d840 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d838 or
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q25)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d844 =
_theResult___snd__h116232[56:5];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d844 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d840;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d844 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d838;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d844 =
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q25;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d844 =
52'd0;
endcase
end
always@(guard__h108320 or
_theResult___snd__h116232 or
out_sfd__h116940 or _theResult___sfd__h116937)
begin
case (guard__h108320)
2'b0, 2'b01:
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q26 =
_theResult___snd__h116232[56:5];
2'b10:
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q26 =
out_sfd__h116940;
2'b11:
CASE_guard08320_0b0_theResult___snd16232_BITS__ETC__q26 =
_theResult___sfd__h116937;
endcase
end
always@(guard__h126695 or
_theResult___snd__h134631 or _theResult___sfd__h135366)
begin
case (guard__h126695)
2'b0:
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q27 =
_theResult___snd__h134631[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q27 =
_theResult___sfd__h135366;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___snd__h134631 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d886 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d884 or
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q27)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d890 =
_theResult___snd__h134631[56:5];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d890 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d886;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d890 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d884;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d890 =
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q27;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d890 =
52'd0;
endcase
end
always@(guard__h126695 or
_theResult___snd__h134631 or
out_sfd__h135369 or _theResult___sfd__h135366)
begin
case (guard__h126695)
2'b0, 2'b01:
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q28 =
_theResult___snd__h134631[56:5];
2'b10:
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q28 =
out_sfd__h135369;
2'b11:
CASE_guard26695_0b0_theResult___snd34631_BITS__ETC__q28 =
_theResult___sfd__h135366;
endcase
end
always@(guard__h143753 or _theResult___exp__h144369)
begin
case (guard__h143753)
2'b0: CASE_guard43753_0b0_0_0b1_theResult___exp44369_ETC__q31 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard43753_0b0_0_0b1_theResult___exp44369_ETC__q31 =
_theResult___exp__h144369;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1053 or
guard__h143753 or
execFpuSimple_rVal1 or
_theResult___exp__h144369 or
CASE_guard43753_0b0_0_0b1_theResult___exp44369_ETC__q31)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1056 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1053;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1056 =
(guard__h143753 == 2'b0 || execFpuSimple_rVal1[31]) ?
11'd0 :
_theResult___exp__h144369;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1056 =
CASE_guard43753_0b0_0_0b1_theResult___exp44369_ETC__q31;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1056 =
11'd0;
endcase
end
always@(guard__h143753 or out_exp__h144372 or _theResult___exp__h144369)
begin
case (guard__h143753)
2'b0, 2'b01:
CASE_guard43753_0b0_0_0b1_0_0b10_out_exp44372__ETC__q32 = 11'd0;
2'b10:
CASE_guard43753_0b0_0_0b1_0_0b10_out_exp44372__ETC__q32 =
out_exp__h144372;
2'b11:
CASE_guard43753_0b0_0_0b1_0_0b10_out_exp44372__ETC__q32 =
_theResult___exp__h144369;
endcase
end
always@(guard__h144483 or x__h144498 or _theResult___exp__h145125)
begin
case (guard__h144483)
2'b0:
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_th_ETC__q33 =
x__h144498[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_th_ETC__q33 =
_theResult___exp__h145125;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h144498 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1099 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1097 or
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_th_ETC__q33)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1103 =
x__h144498[10:0];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1103 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1099;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1103 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1097;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1103 =
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_th_ETC__q33;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1103 =
11'd0;
endcase
end
always@(guard__h144483 or
x__h144498 or out_exp__h145128 or _theResult___exp__h145125)
begin
case (guard__h144483)
2'b0, 2'b01:
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_x4_ETC__q34 =
x__h144498[10:0];
2'b10:
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_x4_ETC__q34 =
out_exp__h145128;
2'b11:
CASE_guard44483_0b0_x44498_BITS_10_TO_0_0b1_x4_ETC__q34 =
_theResult___exp__h145125;
endcase
end
always@(guard__h143753 or sfd___3__h143743 or _theResult___sfd__h144370)
begin
case (guard__h143753)
2'b0:
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q35 =
sfd___3__h143743[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q35 =
_theResult___sfd__h144370;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h143743 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1126 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1124 or
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q35)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1130 =
sfd___3__h143743[54:3];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1130 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1126;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1130 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1124;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1130 =
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q35;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1130 =
52'd0;
endcase
end
always@(guard__h143753 or
sfd___3__h143743 or out_sfd__h144373 or _theResult___sfd__h144370)
begin
case (guard__h143753)
2'b0, 2'b01:
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q36 =
sfd___3__h143743[54:3];
2'b10:
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q36 =
out_sfd__h144373;
2'b11:
CASE_guard43753_0b0_sfd___343743_BITS_54_TO_3__ETC__q36 =
_theResult___sfd__h144370;
endcase
end
always@(guard__h144483 or sfd___3__h143743 or _theResult___sfd__h145126)
begin
case (guard__h144483)
2'b0:
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q37 =
sfd___3__h143743[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q37 =
_theResult___sfd__h145126;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h143743 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1144 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1142 or
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q37)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1148 =
sfd___3__h143743[53:2];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1148 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1144;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1148 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1142;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1148 =
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q37;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1148 =
52'd0;
endcase
end
always@(guard__h144483 or
sfd___3__h143743 or out_sfd__h145129 or _theResult___sfd__h145126)
begin
case (guard__h144483)
2'b0, 2'b01:
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q38 =
sfd___3__h143743[53:2];
2'b10:
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q38 =
out_sfd__h145129;
2'b11:
CASE_guard44483_0b0_sfd___343743_BITS_53_TO_2__ETC__q38 =
_theResult___sfd__h145126;
endcase
end
always@(guard__h164377 or _theResult___exp__h164993)
begin
case (guard__h164377)
2'b0: CASE_guard64377_0b0_0_0b1_theResult___exp64993_ETC__q43 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard64377_0b0_0_0b1_theResult___exp64993_ETC__q43 =
_theResult___exp__h164993;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1475 or
guard__h164377 or
execFpuSimple_rVal1 or
_theResult___exp__h164993 or
CASE_guard64377_0b0_0_0b1_theResult___exp64993_ETC__q43)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1478 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1475;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1478 =
(guard__h164377 == 2'b0 || execFpuSimple_rVal1[63]) ?
11'd0 :
_theResult___exp__h164993;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1478 =
CASE_guard64377_0b0_0_0b1_theResult___exp64993_ETC__q43;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1478 =
11'd0;
endcase
end
always@(guard__h164377 or out_exp__h164996 or _theResult___exp__h164993)
begin
case (guard__h164377)
2'b0, 2'b01:
CASE_guard64377_0b0_0_0b1_0_0b10_out_exp64996__ETC__q44 = 11'd0;
2'b10:
CASE_guard64377_0b0_0_0b1_0_0b10_out_exp64996__ETC__q44 =
out_exp__h164996;
2'b11:
CASE_guard64377_0b0_0_0b1_0_0b10_out_exp64996__ETC__q44 =
_theResult___exp__h164993;
endcase
end
always@(guard__h165107 or x__h165122 or _theResult___exp__h165749)
begin
case (guard__h165107)
2'b0:
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_th_ETC__q45 =
x__h165122[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_th_ETC__q45 =
_theResult___exp__h165749;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h165122 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1521 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1519 or
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_th_ETC__q45)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1525 =
x__h165122[10:0];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1525 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1521;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1525 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1519;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1525 =
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_th_ETC__q45;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1525 =
11'd0;
endcase
end
always@(guard__h165107 or
x__h165122 or out_exp__h165752 or _theResult___exp__h165749)
begin
case (guard__h165107)
2'b0, 2'b01:
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_x6_ETC__q46 =
x__h165122[10:0];
2'b10:
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_x6_ETC__q46 =
out_exp__h165752;
2'b11:
CASE_guard65107_0b0_x65122_BITS_10_TO_0_0b1_x6_ETC__q46 =
_theResult___exp__h165749;
endcase
end
always@(guard__h164377 or sfd___3__h164367 or _theResult___sfd__h164994)
begin
case (guard__h164377)
2'b0:
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q47 =
sfd___3__h164367[63:12];
2'b01, 2'b10, 2'b11:
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q47 =
_theResult___sfd__h164994;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h164367 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1549 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1547 or
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q47)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1553 =
sfd___3__h164367[63:12];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1553 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1549;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1553 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1547;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1553 =
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q47;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1553 =
52'd0;
endcase
end
always@(guard__h164377 or
sfd___3__h164367 or out_sfd__h164997 or _theResult___sfd__h164994)
begin
case (guard__h164377)
2'b0, 2'b01:
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q48 =
sfd___3__h164367[63:12];
2'b10:
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q48 =
out_sfd__h164997;
2'b11:
CASE_guard64377_0b0_sfd___364367_BITS_63_TO_12_ETC__q48 =
_theResult___sfd__h164994;
endcase
end
always@(guard__h165107 or sfd___3__h164367 or _theResult___sfd__h165750)
begin
case (guard__h165107)
2'b0:
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q49 =
sfd___3__h164367[62:11];
2'b01, 2'b10, 2'b11:
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q49 =
_theResult___sfd__h165750;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h164367 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1567 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1565 or
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q49)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1571 =
sfd___3__h164367[62:11];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1571 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1567;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1571 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1565;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1571 =
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q49;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1571 =
52'd0;
endcase
end
always@(guard__h165107 or
sfd___3__h164367 or out_sfd__h165753 or _theResult___sfd__h165750)
begin
case (guard__h165107)
2'b0, 2'b01:
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q50 =
sfd___3__h164367[62:11];
2'b10:
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q50 =
out_sfd__h165753;
2'b11:
CASE_guard65107_0b0_sfd___364367_BITS_62_TO_11_ETC__q50 =
_theResult___sfd__h165750;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h108320)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d912 =
execFpuSimple_rVal1[31];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d912 =
(guard__h108320 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h108320 == 2'b01 || guard__h108320 == 2'b10 ||
guard__h108320 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d912 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h108320 or execFpuSimple_rVal1)
begin
case (guard__h108320)
2'b0, 2'b01, 2'b10:
CASE_guard08320_0b0_execFpuSimple_rVal1_BIT_31_ETC__q51 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard08320_0b0_execFpuSimple_rVal1_BIT_31_ETC__q51 =
guard__h108320 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h117628)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d920 =
execFpuSimple_rVal1[31];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d920 =
(guard__h117628 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h117628 == 2'b01 || guard__h117628 == 2'b10 ||
guard__h117628 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d920 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h117628 or execFpuSimple_rVal1)
begin
case (guard__h117628)
2'b0, 2'b01, 2'b10:
CASE_guard17628_0b0_execFpuSimple_rVal1_BIT_31_ETC__q52 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard17628_0b0_execFpuSimple_rVal1_BIT_31_ETC__q52 =
guard__h117628 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h126695)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d928 =
execFpuSimple_rVal1[31];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d928 =
(guard__h126695 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h126695 == 2'b01 || guard__h126695 == 2'b10 ||
guard__h126695 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d928 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h126695 or execFpuSimple_rVal1)
begin
case (guard__h126695)
2'b0, 2'b01, 2'b10:
CASE_guard26695_0b0_execFpuSimple_rVal1_BIT_31_ETC__q53 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard26695_0b0_execFpuSimple_rVal1_BIT_31_ETC__q53 =
guard__h126695 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h143753)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1161 =
execFpuSimple_rVal1[31];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1161 =
(guard__h143753 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h143753 == 2'b01 || guard__h143753 == 2'b10 ||
guard__h143753 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1161 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h143753 or execFpuSimple_rVal1)
begin
case (guard__h143753)
2'b0, 2'b01, 2'b10:
CASE_guard43753_0b0_execFpuSimple_rVal1_BIT_31_ETC__q54 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard43753_0b0_execFpuSimple_rVal1_BIT_31_ETC__q54 =
guard__h143753 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h144483)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1168 =
execFpuSimple_rVal1[31];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1168 =
(guard__h144483 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h144483 == 2'b01 || guard__h144483 == 2'b10 ||
guard__h144483 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1168 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h144483 or execFpuSimple_rVal1)
begin
case (guard__h144483)
2'b0, 2'b01, 2'b10:
CASE_guard44483_0b0_execFpuSimple_rVal1_BIT_31_ETC__q55 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard44483_0b0_execFpuSimple_rVal1_BIT_31_ETC__q55 =
guard__h144483 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h164377)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1586 =
execFpuSimple_rVal1[63];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1586 =
(guard__h164377 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h164377 == 2'b01 || guard__h164377 == 2'b10 ||
guard__h164377 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1586 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h164377 or execFpuSimple_rVal1)
begin
case (guard__h164377)
2'b0, 2'b01, 2'b10:
CASE_guard64377_0b0_execFpuSimple_rVal1_BIT_63_ETC__q56 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard64377_0b0_execFpuSimple_rVal1_BIT_63_ETC__q56 =
guard__h164377 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h165107)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1593 =
execFpuSimple_rVal1[63];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1593 =
(guard__h165107 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h165107 == 2'b01 || guard__h165107 == 2'b10 ||
guard__h165107 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1593 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h165107 or execFpuSimple_rVal1)
begin
case (guard__h165107)
2'b0, 2'b01, 2'b10:
CASE_guard65107_0b0_execFpuSimple_rVal1_BIT_63_ETC__q57 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard65107_0b0_execFpuSimple_rVal1_BIT_63_ETC__q57 =
guard__h165107 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or
NOT_IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_ETC___d935 or
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d1601 or
execFpuSimple_rVal2 or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607 =
execFpuSimple_rVal2[63];
5'd6:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607 =
!execFpuSimple_rVal2[63];
5'd7:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607 =
execFpuSimple_rVal1[63] ^ execFpuSimple_rVal2[63];
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607 =
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
((execFpuSimple_fpu_inst[8:4] == 5'd10) ?
NOT_IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_ETC___d935 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d1601);
endcase
end
always@(guard__h153144 or out_exp__h153763 or _theResult___exp__h153760)
begin
case (guard__h153144)
2'b0, 2'b01:
CASE_guard53144_0b0_0_0b1_0_0b10_out_exp53763__ETC__q60 = 11'd0;
2'b10:
CASE_guard53144_0b0_0_0b1_0_0b10_out_exp53763__ETC__q60 =
out_exp__h153763;
2'b11:
CASE_guard53144_0b0_0_0b1_0_0b10_out_exp53763__ETC__q60 =
_theResult___exp__h153760;
endcase
end
always@(guard__h153144 or _theResult___exp__h153760)
begin
case (guard__h153144)
2'b0: CASE_guard53144_0b0_0_0b1_theResult___exp53760_ETC__q61 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard53144_0b0_0_0b1_theResult___exp53760_ETC__q61 =
_theResult___exp__h153760;
endcase
end
always@(execFpuSimple_fpu_inst or
guard__h153144 or
_theResult___exp__h153760 or
CASE_guard53144_0b0_0_0b1_theResult___exp53760_ETC__q61)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q62 =
(guard__h153144 == 2'b0) ? 11'd0 : _theResult___exp__h153760;
3'b100:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q62 =
CASE_guard53144_0b0_0_0b1_theResult___exp53760_ETC__q61;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q62 =
11'd0;
endcase
end
always@(guard__h153873 or x__h153888 or _theResult___exp__h154515)
begin
case (guard__h153873)
2'b0:
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_th_ETC__q63 =
x__h153888[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_th_ETC__q63 =
_theResult___exp__h154515;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h153888 or
guard__h153873 or
_theResult___exp__h154515 or
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_th_ETC__q63)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1751 =
x__h153888[10:0];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1751 =
(guard__h153873 == 2'b0) ?
x__h153888[10:0] :
_theResult___exp__h154515;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1751 =
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_th_ETC__q63;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1751 =
11'd0;
endcase
end
always@(guard__h153873 or
x__h153888 or out_exp__h154518 or _theResult___exp__h154515)
begin
case (guard__h153873)
2'b0, 2'b01:
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_x5_ETC__q64 =
x__h153888[10:0];
2'b10:
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_x5_ETC__q64 =
out_exp__h154518;
2'b11:
CASE_guard53873_0b0_x53888_BITS_10_TO_0_0b1_x5_ETC__q64 =
_theResult___exp__h154515;
endcase
end
always@(guard__h153144 or sfd___3__h153134 or _theResult___sfd__h153761)
begin
case (guard__h153144)
2'b0:
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q65 =
sfd___3__h153134[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q65 =
_theResult___sfd__h153761;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h153134 or
guard__h153144 or
_theResult___sfd__h153761 or
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q65)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1774 =
sfd___3__h153134[54:3];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1774 =
(guard__h153144 == 2'b0) ?
sfd___3__h153134[54:3] :
_theResult___sfd__h153761;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1774 =
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q65;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1774 =
52'd0;
endcase
end
always@(guard__h153144 or
sfd___3__h153134 or out_sfd__h153764 or _theResult___sfd__h153761)
begin
case (guard__h153144)
2'b0, 2'b01:
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q66 =
sfd___3__h153134[54:3];
2'b10:
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q66 =
out_sfd__h153764;
2'b11:
CASE_guard53144_0b0_sfd___353134_BITS_54_TO_3__ETC__q66 =
_theResult___sfd__h153761;
endcase
end
always@(guard__h153873 or sfd___3__h153134 or _theResult___sfd__h154516)
begin
case (guard__h153873)
2'b0:
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q67 =
sfd___3__h153134[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q67 =
_theResult___sfd__h154516;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h153134 or
guard__h153873 or
_theResult___sfd__h154516 or
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q67)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1789 =
sfd___3__h153134[53:2];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1789 =
(guard__h153873 == 2'b0) ?
sfd___3__h153134[53:2] :
_theResult___sfd__h154516;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1789 =
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q67;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d1789 =
52'd0;
endcase
end
always@(guard__h153873 or
sfd___3__h153134 or out_sfd__h154519 or _theResult___sfd__h154516)
begin
case (guard__h153873)
2'b0, 2'b01:
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q68 =
sfd___3__h153134[53:2];
2'b10:
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q68 =
out_sfd__h154519;
2'b11:
CASE_guard53873_0b0_sfd___353134_BITS_53_TO_2__ETC__q68 =
_theResult___sfd__h154516;
endcase
end
always@(guard__h83797 or out_exp__h84213 or _theResult___exp__h84210)
begin
case (guard__h83797)
2'b0, 2'b01:
CASE_guard3797_0b0_0_0b1_0_0b10_out_exp4213_0b_ETC__q73 = 8'd0;
2'b10:
CASE_guard3797_0b0_0_0b1_0_0b10_out_exp4213_0b_ETC__q73 =
out_exp__h84213;
2'b11:
CASE_guard3797_0b0_0_0b1_0_0b10_out_exp4213_0b_ETC__q73 =
_theResult___exp__h84210;
endcase
end
always@(guard__h83797 or _theResult___exp__h84210)
begin
case (guard__h83797)
2'b0: CASE_guard3797_0b0_0_0b1_theResult___exp4210_0_ETC__q74 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard3797_0b0_0_0b1_theResult___exp4210_0_ETC__q74 =
_theResult___exp__h84210;
endcase
end
always@(execFpuSimple_fpu_inst or
guard__h83797 or
_theResult___exp__h84210 or
CASE_guard3797_0b0_0_0b1_theResult___exp4210_0_ETC__q74)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q75 =
(guard__h83797 == 2'b0) ? 8'd0 : _theResult___exp__h84210;
3'b100:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q75 =
CASE_guard3797_0b0_0_0b1_theResult___exp4210_0_ETC__q74;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q75 = 8'd0;
endcase
end
always@(guard__h175083 or out_exp__h175702 or _theResult___exp__h175699)
begin
case (guard__h175083)
2'b0, 2'b01:
CASE_guard75083_0b0_0_0b1_0_0b10_out_exp75702__ETC__q76 = 11'd0;
2'b10:
CASE_guard75083_0b0_0_0b1_0_0b10_out_exp75702__ETC__q76 =
out_exp__h175702;
2'b11:
CASE_guard75083_0b0_0_0b1_0_0b10_out_exp75702__ETC__q76 =
_theResult___exp__h175699;
endcase
end
always@(guard__h175083 or _theResult___exp__h175699)
begin
case (guard__h175083)
2'b0: CASE_guard75083_0b0_0_0b1_theResult___exp75699_ETC__q77 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard75083_0b0_0_0b1_theResult___exp75699_ETC__q77 =
_theResult___exp__h175699;
endcase
end
always@(execFpuSimple_fpu_inst or
guard__h175083 or
_theResult___exp__h175699 or
CASE_guard75083_0b0_0_0b1_theResult___exp75699_ETC__q77)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q78 =
(guard__h175083 == 2'b0) ? 11'd0 : _theResult___exp__h175699;
3'b100:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q78 =
CASE_guard75083_0b0_0_0b1_theResult___exp75699_ETC__q77;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q78 =
11'd0;
endcase
end
always@(guard__h175812 or x__h175827 or _theResult___exp__h176454)
begin
case (guard__h175812)
2'b0:
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_th_ETC__q79 =
x__h175827[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_th_ETC__q79 =
_theResult___exp__h176454;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h175827 or
guard__h175812 or
_theResult___exp__h176454 or
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_th_ETC__q79)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2059 =
x__h175827[10:0];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2059 =
(guard__h175812 == 2'b0) ?
x__h175827[10:0] :
_theResult___exp__h176454;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2059 =
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_th_ETC__q79;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2059 =
11'd0;
endcase
end
always@(guard__h175812 or
x__h175827 or out_exp__h176457 or _theResult___exp__h176454)
begin
case (guard__h175812)
2'b0, 2'b01:
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_x7_ETC__q80 =
x__h175827[10:0];
2'b10:
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_x7_ETC__q80 =
out_exp__h176457;
2'b11:
CASE_guard75812_0b0_x75827_BITS_10_TO_0_0b1_x7_ETC__q80 =
_theResult___exp__h176454;
endcase
end
always@(guard__h175083 or sfd___3__h175073 or _theResult___sfd__h175700)
begin
case (guard__h175083)
2'b0:
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q81 =
sfd___3__h175073[63:12];
2'b01, 2'b10, 2'b11:
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q81 =
_theResult___sfd__h175700;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h175073 or
guard__h175083 or
_theResult___sfd__h175700 or
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q81)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2083 =
sfd___3__h175073[63:12];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2083 =
(guard__h175083 == 2'b0) ?
sfd___3__h175073[63:12] :
_theResult___sfd__h175700;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2083 =
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q81;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2083 =
52'd0;
endcase
end
always@(guard__h175083 or
sfd___3__h175073 or out_sfd__h175703 or _theResult___sfd__h175700)
begin
case (guard__h175083)
2'b0, 2'b01:
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q82 =
sfd___3__h175073[63:12];
2'b10:
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q82 =
out_sfd__h175703;
2'b11:
CASE_guard75083_0b0_sfd___375073_BITS_63_TO_12_ETC__q82 =
_theResult___sfd__h175700;
endcase
end
always@(guard__h175812 or sfd___3__h175073 or _theResult___sfd__h176455)
begin
case (guard__h175812)
2'b0:
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q83 =
sfd___3__h175073[62:11];
2'b01, 2'b10, 2'b11:
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q83 =
_theResult___sfd__h176455;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h175073 or
guard__h175812 or
_theResult___sfd__h176455 or
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q83)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2098 =
sfd___3__h175073[62:11];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2098 =
(guard__h175812 == 2'b0) ?
sfd___3__h175073[62:11] :
_theResult___sfd__h176455;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2098 =
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q83;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d2098 =
52'd0;
endcase
end
always@(guard__h175812 or
sfd___3__h175073 or out_sfd__h176458 or _theResult___sfd__h176455)
begin
case (guard__h175812)
2'b0, 2'b01:
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q84 =
sfd___3__h175073[62:11];
2'b10:
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q84 =
out_sfd__h176458;
2'b11:
CASE_guard75812_0b0_sfd___375073_BITS_62_TO_11_ETC__q84 =
_theResult___sfd__h176455;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
_theResult___snd_exp__h135722 or
_theResult___snd_exp__h145368 or
_theResult___snd_exp__h154745 or
_theResult___snd_exp__h165992 or _theResult___snd_exp__h176684)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5, 5'd6, 5'd7:
_theResult___snd_fst_exp__h176701 = execFpuSimple_rVal1[62:52];
5'd8,
5'd9,
5'd11,
5'd12,
5'd13,
5'd14,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24:
_theResult___snd_fst_exp__h176701 = 11'd0;
5'd10:
_theResult___snd_fst_exp__h176701 = _theResult___snd_exp__h135722;
5'd15:
_theResult___snd_fst_exp__h176701 = _theResult___snd_exp__h145368;
5'd16:
_theResult___snd_fst_exp__h176701 = _theResult___snd_exp__h154745;
5'd17:
_theResult___snd_fst_exp__h176701 = _theResult___snd_exp__h165992;
5'd18:
_theResult___snd_fst_exp__h176701 = _theResult___snd_exp__h176684;
default: _theResult___snd_fst_exp__h176701 = 11'd0;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
_theResult___snd_sfd__h135723 or
_theResult___snd_sfd__h145369 or
_theResult___snd_sfd__h154746 or
_theResult___snd_sfd__h165993 or
_theResult___snd_sfd__h176685 or
_theResult___snd_sfd__h96909 or
_theResult___snd_sfd__h96969 or _theResult___snd_sfd__h97029)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5, 5'd6, 5'd7:
_theResult___snd_fst_sfd__h176702 = execFpuSimple_rVal1[51:0];
5'd8, 5'd9, 5'd11, 5'd12, 5'd13, 5'd14, 5'd22, 5'd23, 5'd24:
_theResult___snd_fst_sfd__h176702 = 52'd0;
5'd10:
_theResult___snd_fst_sfd__h176702 = _theResult___snd_sfd__h135723;
5'd15:
_theResult___snd_fst_sfd__h176702 = _theResult___snd_sfd__h145369;
5'd16:
_theResult___snd_fst_sfd__h176702 = _theResult___snd_sfd__h154746;
5'd17:
_theResult___snd_fst_sfd__h176702 = _theResult___snd_sfd__h165993;
5'd18:
_theResult___snd_fst_sfd__h176702 = _theResult___snd_sfd__h176685;
5'd19: _theResult___snd_fst_sfd__h176702 = _theResult___snd_sfd__h96909;
5'd20: _theResult___snd_fst_sfd__h176702 = _theResult___snd_sfd__h96969;
5'd21: _theResult___snd_fst_sfd__h176702 = _theResult___snd_sfd__h97029;
default: _theResult___snd_fst_sfd__h176702 = 52'd0;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2460 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 or
_theResult___fst_exp__h145225 or
_theResult___fst_sfd__h145226 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 or
_theResult___fst_exp__h154614 or
_theResult___fst_sfd__h154615 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2387)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 &&
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 &&
_theResult___fst_exp__h145225 == 11'd2047 &&
_theResult___fst_sfd__h145226 == 52'd0);
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 ||
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 &&
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 &&
_theResult___fst_exp__h154614 == 11'd2047 &&
_theResult___fst_sfd__h154615 == 52'd0);
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2387;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2460;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263 or
execFpuSimple_rVal1 or
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239 or
int_val_rnd__h94412 or
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175 or
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94412[115:32] != 84'd0 ||
!IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175);
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94412 != 116'd0 && execFpuSimple_rVal1[63] ||
int_val_rnd__h94412[115:32] != 84'd0);
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94412[115:64] != 52'd0 ||
!IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198);
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2497 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2494)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2494;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2497;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579 or
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2541 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2546 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 or
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2551 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 or
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2559 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2570)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd0 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2541;
5'd14:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2546;
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 &&
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 &&
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2551;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 &&
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 &&
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2559;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2570;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or int_val__h5744)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q86 =
execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31];
3'b100:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q86 =
int_val__h5744[1];
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_N_ETC__q86 =
execFpuSimple_fpu_inst[3:1] == 3'b010 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h16338 or
_theResult___fst_exp__h24437 or _theResult___exp__h24963)
begin
case (guard__h16338)
2'b0:
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q99 =
_theResult___fst_exp__h24437;
2'b01, 2'b10, 2'b11:
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q99 =
_theResult___exp__h24963;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h24437 or
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3194 or
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3192 or
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q99)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3198 =
_theResult___fst_exp__h24437;
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3198 =
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3194;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3198 =
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3192;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3198 =
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q99;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3198 =
8'd0;
endcase
end
always@(guard__h16338 or
_theResult___fst_exp__h24437 or
out_exp__h24966 or _theResult___exp__h24963)
begin
case (guard__h16338)
2'b0, 2'b01:
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q100 =
_theResult___fst_exp__h24437;
2'b10:
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q100 =
out_exp__h24966;
2'b11:
CASE_guard6338_0b0_theResult___fst_exp4437_0b1_ETC__q100 =
_theResult___exp__h24963;
endcase
end
always@(guard__h25075 or
_theResult___fst_exp__h33123 or _theResult___exp__h33575)
begin
case (guard__h25075)
2'b0:
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q101 =
_theResult___fst_exp__h33123;
2'b01, 2'b10, 2'b11:
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q101 =
_theResult___exp__h33575;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h33123 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3311 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3309 or
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q101)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3315 =
_theResult___fst_exp__h33123;
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3315 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3311;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3315 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3309;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3315 =
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q101;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3315 =
8'd0;
endcase
end
always@(guard__h25075 or
_theResult___fst_exp__h33123 or
out_exp__h33578 or _theResult___exp__h33575)
begin
case (guard__h25075)
2'b0, 2'b01:
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q102 =
_theResult___fst_exp__h33123;
2'b10:
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q102 =
out_exp__h33578;
2'b11:
CASE_guard5075_0b0_theResult___fst_exp3123_0b1_ETC__q102 =
_theResult___exp__h33575;
endcase
end
always@(guard__h34064 or
_theResult___fst_exp__h42290 or _theResult___exp__h42816)
begin
case (guard__h34064)
2'b0:
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q103 =
_theResult___fst_exp__h42290;
2'b01, 2'b10, 2'b11:
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q103 =
_theResult___exp__h42816;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h42290 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633 or
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q103)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3639 =
_theResult___fst_exp__h42290;
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3639 =
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3639 =
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3639 =
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q103;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3639 =
8'd0;
endcase
end
always@(guard__h34064 or
_theResult___fst_exp__h42290 or
out_exp__h42819 or _theResult___exp__h42816)
begin
case (guard__h34064)
2'b0, 2'b01:
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q104 =
_theResult___fst_exp__h42290;
2'b10:
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q104 =
out_exp__h42819;
2'b11:
CASE_guard4064_0b0_theResult___fst_exp2290_0b1_ETC__q104 =
_theResult___exp__h42816;
endcase
end
always@(guard__h42928 or
_theResult___fst_exp__h51005 or _theResult___exp__h51482)
begin
case (guard__h42928)
2'b0:
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q105 =
_theResult___fst_exp__h51005;
2'b01, 2'b10, 2'b11:
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q105 =
_theResult___exp__h51482;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h51005 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702 or
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q105)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3708 =
_theResult___fst_exp__h51005;
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3708 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3708 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3708 =
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q105;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3708 =
8'd0;
endcase
end
always@(guard__h42928 or
_theResult___fst_exp__h51005 or
out_exp__h51485 or _theResult___exp__h51482)
begin
case (guard__h42928)
2'b0, 2'b01:
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q106 =
_theResult___fst_exp__h51005;
2'b10:
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q106 =
out_exp__h51485;
2'b11:
CASE_guard2928_0b0_theResult___fst_exp1005_0b1_ETC__q106 =
_theResult___exp__h51482;
endcase
end
always@(guard__h16338 or sfdin__h24431 or _theResult___sfd__h24964)
begin
case (guard__h16338)
2'b0:
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q107 =
sfdin__h24431[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q107 =
_theResult___sfd__h24964;
endcase
end
always@(execFpuSimple_fpu_inst or
sfdin__h24431 or
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3735 or
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3733 or
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q107)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3739 =
sfdin__h24431[56:34];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3739 =
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3735;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3739 =
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3733;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3739 =
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q107;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3739 =
23'd0;
endcase
end
always@(guard__h16338 or
sfdin__h24431 or out_sfd__h24967 or _theResult___sfd__h24964)
begin
case (guard__h16338)
2'b0, 2'b01:
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q108 =
sfdin__h24431[56:34];
2'b10:
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q108 =
out_sfd__h24967;
2'b11:
CASE_guard6338_0b0_sfdin4431_BITS_56_TO_34_0b1_ETC__q108 =
_theResult___sfd__h24964;
endcase
end
always@(guard__h25075 or
_theResult___snd__h33074 or _theResult___sfd__h33576)
begin
case (guard__h25075)
2'b0:
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q109 =
_theResult___snd__h33074[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q109 =
_theResult___sfd__h33576;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___snd__h33074 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3754 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3752 or
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q109)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3758 =
_theResult___snd__h33074[56:34];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3758 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3754;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3758 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3752;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3758 =
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q109;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3758 =
23'd0;
endcase
end
always@(guard__h25075 or
_theResult___snd__h33074 or
out_sfd__h33579 or _theResult___sfd__h33576)
begin
case (guard__h25075)
2'b0, 2'b01:
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q110 =
_theResult___snd__h33074[56:34];
2'b10:
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q110 =
out_sfd__h33579;
2'b11:
CASE_guard5075_0b0_theResult___snd3074_BITS_56_ETC__q110 =
_theResult___sfd__h33576;
endcase
end
always@(guard__h34064 or sfdin__h42284 or _theResult___sfd__h42817)
begin
case (guard__h34064)
2'b0:
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q111 =
sfdin__h42284[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q111 =
_theResult___sfd__h42817;
endcase
end
always@(execFpuSimple_fpu_inst or
sfdin__h42284 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3781 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3779 or
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q111)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3785 =
sfdin__h42284[56:34];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3785 =
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3781;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3785 =
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3779;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3785 =
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q111;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3785 =
23'd0;
endcase
end
always@(guard__h34064 or
sfdin__h42284 or out_sfd__h42820 or _theResult___sfd__h42817)
begin
case (guard__h34064)
2'b0, 2'b01:
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q112 =
sfdin__h42284[56:34];
2'b10:
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q112 =
out_sfd__h42820;
2'b11:
CASE_guard4064_0b0_sfdin2284_BITS_56_TO_34_0b1_ETC__q112 =
_theResult___sfd__h42817;
endcase
end
always@(guard__h42928 or
_theResult___snd__h50951 or _theResult___sfd__h51483)
begin
case (guard__h42928)
2'b0:
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q113 =
_theResult___snd__h50951[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q113 =
_theResult___sfd__h51483;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___snd__h50951 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3800 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3798 or
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q113)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3804 =
_theResult___snd__h50951[56:34];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3804 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3800;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3804 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3798;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3804 =
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q113;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3804 =
23'd0;
endcase
end
always@(guard__h42928 or
_theResult___snd__h50951 or
out_sfd__h51486 or _theResult___sfd__h51483)
begin
case (guard__h42928)
2'b0, 2'b01:
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q114 =
_theResult___snd__h50951[56:34];
2'b10:
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q114 =
out_sfd__h51486;
2'b11:
CASE_guard2928_0b0_theResult___snd0951_BITS_56_ETC__q114 =
_theResult___sfd__h51483;
endcase
end
always@(guard__h56815 or _theResult___exp__h57228)
begin
case (guard__h56815)
2'b0: CASE_guard6815_0b0_0_0b1_theResult___exp7228_0_ETC__q117 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard6815_0b0_0_0b1_theResult___exp7228_0_ETC__q117 =
_theResult___exp__h57228;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d3990 or
guard__h56815 or
execFpuSimple_rVal1 or
_theResult___exp__h57228 or
CASE_guard6815_0b0_0_0b1_theResult___exp7228_0_ETC__q117)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3993 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d3990;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3993 =
(guard__h56815 == 2'b0 || execFpuSimple_rVal1[31]) ?
8'd0 :
_theResult___exp__h57228;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3993 =
CASE_guard6815_0b0_0_0b1_theResult___exp7228_0_ETC__q117;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3993 =
8'd0;
endcase
end
always@(guard__h56815 or out_exp__h57231 or _theResult___exp__h57228)
begin
case (guard__h56815)
2'b0, 2'b01:
CASE_guard6815_0b0_0_0b1_0_0b10_out_exp7231_0b_ETC__q118 = 8'd0;
2'b10:
CASE_guard6815_0b0_0_0b1_0_0b10_out_exp7231_0b_ETC__q118 =
out_exp__h57231;
2'b11:
CASE_guard6815_0b0_0_0b1_0_0b10_out_exp7231_0b_ETC__q118 =
_theResult___exp__h57228;
endcase
end
always@(guard__h57342 or x__h57357 or _theResult___exp__h57781)
begin
case (guard__h57342)
2'b0:
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_theRe_ETC__q119 =
x__h57357[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_theRe_ETC__q119 =
_theResult___exp__h57781;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h57357 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4036 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4034 or
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_theRe_ETC__q119)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4040 =
x__h57357[7:0];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4040 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4036;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4040 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4034;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4040 =
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_theRe_ETC__q119;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4040 =
8'd0;
endcase
end
always@(guard__h57342 or
x__h57357 or out_exp__h57784 or _theResult___exp__h57781)
begin
case (guard__h57342)
2'b0, 2'b01:
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_x7357_ETC__q120 =
x__h57357[7:0];
2'b10:
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_x7357_ETC__q120 =
out_exp__h57784;
2'b11:
CASE_guard7342_0b0_x7357_BITS_7_TO_0_0b1_x7357_ETC__q120 =
_theResult___exp__h57781;
endcase
end
always@(guard__h56815 or sfd___3__h56805 or _theResult___sfd__h57229)
begin
case (guard__h56815)
2'b0:
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q121 =
sfd___3__h56805[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q121 =
_theResult___sfd__h57229;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h56805 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4064 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4062 or
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q121)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4068 =
sfd___3__h56805[31:9];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4068 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4064;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4068 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4062;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4068 =
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q121;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4068 =
23'd0;
endcase
end
always@(guard__h56815 or
sfd___3__h56805 or out_sfd__h57232 or _theResult___sfd__h57229)
begin
case (guard__h56815)
2'b0, 2'b01:
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q122 =
sfd___3__h56805[31:9];
2'b10:
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q122 =
out_sfd__h57232;
2'b11:
CASE_guard6815_0b0_sfd___36805_BITS_31_TO_9_0b_ETC__q122 =
_theResult___sfd__h57229;
endcase
end
always@(guard__h57342 or sfd___3__h56805 or _theResult___sfd__h57782)
begin
case (guard__h57342)
2'b0:
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q123 =
sfd___3__h56805[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q123 =
_theResult___sfd__h57782;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h56805 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4082 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4080 or
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q123)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4086 =
sfd___3__h56805[30:8];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4086 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4082;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4086 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4080;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4086 =
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q123;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4086 =
23'd0;
endcase
end
always@(guard__h57342 or
sfd___3__h56805 or out_sfd__h57785 or _theResult___sfd__h57782)
begin
case (guard__h57342)
2'b0, 2'b01:
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q124 =
sfd___3__h56805[30:8];
2'b10:
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q124 =
out_sfd__h57785;
2'b11:
CASE_guard7342_0b0_sfd___36805_BITS_30_TO_8_0b_ETC__q124 =
_theResult___sfd__h57782;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h56815)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4098 =
execFpuSimple_rVal1[31];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4098 =
(guard__h56815 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h56815 == 2'b01 || guard__h56815 == 2'b10 ||
guard__h56815 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4098 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h56815 or execFpuSimple_rVal1)
begin
case (guard__h56815)
2'b0, 2'b01, 2'b10:
CASE_guard6815_0b0_execFpuSimple_rVal1_BIT_31__ETC__q125 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard6815_0b0_execFpuSimple_rVal1_BIT_31__ETC__q125 =
guard__h56815 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h57342)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4105 =
execFpuSimple_rVal1[31];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4105 =
(guard__h57342 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h57342 == 2'b01 || guard__h57342 == 2'b10 ||
guard__h57342 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4105 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h57342 or execFpuSimple_rVal1)
begin
case (guard__h57342)
2'b0, 2'b01, 2'b10:
CASE_guard7342_0b0_execFpuSimple_rVal1_BIT_31__ETC__q126 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard7342_0b0_execFpuSimple_rVal1_BIT_31__ETC__q126 =
guard__h57342 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(guard__h73497 or _theResult___exp__h73910)
begin
case (guard__h73497)
2'b0: CASE_guard3497_0b0_0_0b1_theResult___exp3910_0_ETC__q127 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard3497_0b0_0_0b1_theResult___exp3910_0_ETC__q127 =
_theResult___exp__h73910;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4151 or
guard__h73497 or
execFpuSimple_rVal1 or
_theResult___exp__h73910 or
CASE_guard3497_0b0_0_0b1_theResult___exp3910_0_ETC__q127)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4154 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4151;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4154 =
(guard__h73497 == 2'b0 || execFpuSimple_rVal1[63]) ?
8'd0 :
_theResult___exp__h73910;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4154 =
CASE_guard3497_0b0_0_0b1_theResult___exp3910_0_ETC__q127;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4154 =
8'd0;
endcase
end
always@(guard__h73497 or out_exp__h73913 or _theResult___exp__h73910)
begin
case (guard__h73497)
2'b0, 2'b01:
CASE_guard3497_0b0_0_0b1_0_0b10_out_exp3913_0b_ETC__q128 = 8'd0;
2'b10:
CASE_guard3497_0b0_0_0b1_0_0b10_out_exp3913_0b_ETC__q128 =
out_exp__h73913;
2'b11:
CASE_guard3497_0b0_0_0b1_0_0b10_out_exp3913_0b_ETC__q128 =
_theResult___exp__h73910;
endcase
end
always@(guard__h74024 or x__h74039 or _theResult___exp__h74463)
begin
case (guard__h74024)
2'b0:
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_theRe_ETC__q129 =
x__h74039[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_theRe_ETC__q129 =
_theResult___exp__h74463;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h74039 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4197 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4195 or
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_theRe_ETC__q129)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4201 =
x__h74039[7:0];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4201 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4197;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4201 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4195;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4201 =
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_theRe_ETC__q129;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4201 =
8'd0;
endcase
end
always@(guard__h74024 or
x__h74039 or out_exp__h74466 or _theResult___exp__h74463)
begin
case (guard__h74024)
2'b0, 2'b01:
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_x4039_ETC__q130 =
x__h74039[7:0];
2'b10:
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_x4039_ETC__q130 =
out_exp__h74466;
2'b11:
CASE_guard4024_0b0_x4039_BITS_7_TO_0_0b1_x4039_ETC__q130 =
_theResult___exp__h74463;
endcase
end
always@(guard__h73497 or sfd___3__h164367 or _theResult___sfd__h73911)
begin
case (guard__h73497)
2'b0:
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q131 =
sfd___3__h164367[63:41];
2'b01, 2'b10, 2'b11:
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q131 =
_theResult___sfd__h73911;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h164367 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4225 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4223 or
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q131)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4229 =
sfd___3__h164367[63:41];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4229 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4225;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4229 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4223;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4229 =
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q131;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4229 =
23'd0;
endcase
end
always@(guard__h73497 or
sfd___3__h164367 or out_sfd__h73914 or _theResult___sfd__h73911)
begin
case (guard__h73497)
2'b0, 2'b01:
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q132 =
sfd___3__h164367[63:41];
2'b10:
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q132 =
out_sfd__h73914;
2'b11:
CASE_guard3497_0b0_sfd___364367_BITS_63_TO_41__ETC__q132 =
_theResult___sfd__h73911;
endcase
end
always@(guard__h74024 or sfd___3__h164367 or _theResult___sfd__h74464)
begin
case (guard__h74024)
2'b0:
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q133 =
sfd___3__h164367[62:40];
2'b01, 2'b10, 2'b11:
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q133 =
_theResult___sfd__h74464;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h164367 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4243 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4241 or
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q133)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4247 =
sfd___3__h164367[62:40];
3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4247 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4243;
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4247 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4241;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4247 =
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q133;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4247 =
23'd0;
endcase
end
always@(guard__h74024 or
sfd___3__h164367 or out_sfd__h74467 or _theResult___sfd__h74464)
begin
case (guard__h74024)
2'b0, 2'b01:
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q134 =
sfd___3__h164367[62:40];
2'b10:
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q134 =
out_sfd__h74467;
2'b11:
CASE_guard4024_0b0_sfd___364367_BITS_62_TO_40__ETC__q134 =
_theResult___sfd__h74464;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h73497)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4259 =
execFpuSimple_rVal1[63];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4259 =
(guard__h73497 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h73497 == 2'b01 || guard__h73497 == 2'b10 ||
guard__h73497 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4259 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h73497 or execFpuSimple_rVal1)
begin
case (guard__h73497)
2'b0, 2'b01, 2'b10:
CASE_guard3497_0b0_execFpuSimple_rVal1_BIT_63__ETC__q135 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard3497_0b0_execFpuSimple_rVal1_BIT_63__ETC__q135 =
guard__h73497 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h74024)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4266 =
execFpuSimple_rVal1[63];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4266 =
(guard__h74024 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h74024 == 2'b01 || guard__h74024 == 2'b10 ||
guard__h74024 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4266 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h74024 or execFpuSimple_rVal1)
begin
case (guard__h74024)
2'b0, 2'b01, 2'b10:
CASE_guard4024_0b0_execFpuSimple_rVal1_BIT_63__ETC__q136 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard4024_0b0_execFpuSimple_rVal1_BIT_63__ETC__q136 =
guard__h74024 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h16338)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3820 =
execFpuSimple_rVal1[63];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3820 =
(guard__h16338 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h16338 == 2'b01 || guard__h16338 == 2'b10 ||
guard__h16338 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3820 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h16338 or execFpuSimple_rVal1)
begin
case (guard__h16338)
2'b0, 2'b01, 2'b10:
CASE_guard6338_0b0_execFpuSimple_rVal1_BIT_63__ETC__q137 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard6338_0b0_execFpuSimple_rVal1_BIT_63__ETC__q137 =
guard__h16338 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h25075)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3828 =
execFpuSimple_rVal1[63];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3828 =
(guard__h25075 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h25075 == 2'b01 || guard__h25075 == 2'b10 ||
guard__h25075 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3828 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h25075 or execFpuSimple_rVal1)
begin
case (guard__h25075)
2'b0, 2'b01, 2'b10:
CASE_guard5075_0b0_execFpuSimple_rVal1_BIT_63__ETC__q138 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard5075_0b0_execFpuSimple_rVal1_BIT_63__ETC__q138 =
guard__h25075 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h34064)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3838 =
execFpuSimple_rVal1[63];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3838 =
(guard__h34064 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h34064 == 2'b01 || guard__h34064 == 2'b10 ||
guard__h34064 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3838 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h34064 or execFpuSimple_rVal1)
begin
case (guard__h34064)
2'b0, 2'b01, 2'b10:
CASE_guard4064_0b0_execFpuSimple_rVal1_BIT_63__ETC__q139 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard4064_0b0_execFpuSimple_rVal1_BIT_63__ETC__q139 =
guard__h34064 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h42928)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b010, 3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3846 =
execFpuSimple_rVal1[63];
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3846 =
(guard__h42928 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h42928 == 2'b01 || guard__h42928 == 2'b10 ||
guard__h42928 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d3846 =
execFpuSimple_fpu_inst[3:1] == 3'b001 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h42928 or execFpuSimple_rVal1)
begin
case (guard__h42928)
2'b0, 2'b01, 2'b10:
CASE_guard2928_0b0_execFpuSimple_rVal1_BIT_63__ETC__q140 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard2928_0b0_execFpuSimple_rVal1_BIT_63__ETC__q140 =
guard__h42928 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(guard__h62670 or out_exp__h63086 or _theResult___exp__h63083)
begin
case (guard__h62670)
2'b0, 2'b01:
CASE_guard2670_0b0_0_0b1_0_0b10_out_exp3086_0b_ETC__q143 = 8'd0;
2'b10:
CASE_guard2670_0b0_0_0b1_0_0b10_out_exp3086_0b_ETC__q143 =
out_exp__h63086;
2'b11:
CASE_guard2670_0b0_0_0b1_0_0b10_out_exp3086_0b_ETC__q143 =
_theResult___exp__h63083;
endcase
end
always@(guard__h62670 or _theResult___exp__h63083)
begin
case (guard__h62670)
2'b0: CASE_guard2670_0b0_0_0b1_theResult___exp3083_0_ETC__q144 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard2670_0b0_0_0b1_theResult___exp3083_0_ETC__q144 =
_theResult___exp__h63083;
endcase
end
always@(execFpuSimple_fpu_inst or
guard__h62670 or
_theResult___exp__h63083 or
CASE_guard2670_0b0_0_0b1_theResult___exp3083_0_ETC__q144)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b011:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q145 =
(guard__h62670 == 2'b0) ? 8'd0 : _theResult___exp__h63083;
3'b100:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q145 =
CASE_guard2670_0b0_0_0b1_theResult___exp3083_0_ETC__q144;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_0b11_I_ETC__q145 =
8'd0;
endcase
end
always@(guard__h63196 or x__h63211 or _theResult___exp__h63635)
begin
case (guard__h63196)
2'b0:
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_theRe_ETC__q146 =
x__h63211[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_theRe_ETC__q146 =
_theResult___exp__h63635;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h63211 or
guard__h63196 or
_theResult___exp__h63635 or
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_theRe_ETC__q146)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4409 =
x__h63211[7:0];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4409 =
(guard__h63196 == 2'b0) ?
x__h63211[7:0] :
_theResult___exp__h63635;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4409 =
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_theRe_ETC__q146;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4409 =
8'd0;
endcase
end
always@(guard__h63196 or
x__h63211 or out_exp__h63638 or _theResult___exp__h63635)
begin
case (guard__h63196)
2'b0, 2'b01:
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_x3211_ETC__q147 =
x__h63211[7:0];
2'b10:
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_x3211_ETC__q147 =
out_exp__h63638;
2'b11:
CASE_guard3196_0b0_x3211_BITS_7_TO_0_0b1_x3211_ETC__q147 =
_theResult___exp__h63635;
endcase
end
always@(guard__h62670 or sfd___3__h62660 or _theResult___sfd__h63084)
begin
case (guard__h62670)
2'b0:
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q148 =
sfd___3__h62660[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q148 =
_theResult___sfd__h63084;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h62660 or
guard__h62670 or
_theResult___sfd__h63084 or
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q148)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4433 =
sfd___3__h62660[31:9];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4433 =
(guard__h62670 == 2'b0) ?
sfd___3__h62660[31:9] :
_theResult___sfd__h63084;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4433 =
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q148;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4433 =
23'd0;
endcase
end
always@(guard__h62670 or
sfd___3__h62660 or out_sfd__h63087 or _theResult___sfd__h63084)
begin
case (guard__h62670)
2'b0, 2'b01:
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q149 =
sfd___3__h62660[31:9];
2'b10:
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q149 =
out_sfd__h63087;
2'b11:
CASE_guard2670_0b0_sfd___32660_BITS_31_TO_9_0b_ETC__q149 =
_theResult___sfd__h63084;
endcase
end
always@(guard__h63196 or sfd___3__h62660 or _theResult___sfd__h63636)
begin
case (guard__h63196)
2'b0:
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q150 =
sfd___3__h62660[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q150 =
_theResult___sfd__h63636;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h62660 or
guard__h63196 or
_theResult___sfd__h63636 or
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q150)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4448 =
sfd___3__h62660[30:8];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4448 =
(guard__h63196 == 2'b0) ?
sfd___3__h62660[30:8] :
_theResult___sfd__h63636;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4448 =
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q150;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4448 =
23'd0;
endcase
end
always@(guard__h63196 or
sfd___3__h62660 or out_sfd__h63639 or _theResult___sfd__h63636)
begin
case (guard__h63196)
2'b0, 2'b01:
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q151 =
sfd___3__h62660[30:8];
2'b10:
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q151 =
out_sfd__h63639;
2'b11:
CASE_guard3196_0b0_sfd___32660_BITS_30_TO_8_0b_ETC__q151 =
_theResult___sfd__h63636;
endcase
end
always@(guard__h84323 or x__h84338 or _theResult___exp__h84762)
begin
case (guard__h84323)
2'b0:
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_theRe_ETC__q152 =
x__h84338[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_theRe_ETC__q152 =
_theResult___exp__h84762;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h84338 or
guard__h84323 or
_theResult___exp__h84762 or
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_theRe_ETC__q152)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4543 =
x__h84338[7:0];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4543 =
(guard__h84323 == 2'b0) ?
x__h84338[7:0] :
_theResult___exp__h84762;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4543 =
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_theRe_ETC__q152;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4543 =
8'd0;
endcase
end
always@(guard__h84323 or
x__h84338 or out_exp__h84765 or _theResult___exp__h84762)
begin
case (guard__h84323)
2'b0, 2'b01:
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_x4338_ETC__q153 =
x__h84338[7:0];
2'b10:
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_x4338_ETC__q153 =
out_exp__h84765;
2'b11:
CASE_guard4323_0b0_x4338_BITS_7_TO_0_0b1_x4338_ETC__q153 =
_theResult___exp__h84762;
endcase
end
always@(guard__h83797 or sfd___3__h175073 or _theResult___sfd__h84211)
begin
case (guard__h83797)
2'b0:
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q154 =
sfd___3__h175073[63:41];
2'b01, 2'b10, 2'b11:
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q154 =
_theResult___sfd__h84211;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h175073 or
guard__h83797 or
_theResult___sfd__h84211 or
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q154)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4567 =
sfd___3__h175073[63:41];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4567 =
(guard__h83797 == 2'b0) ?
sfd___3__h175073[63:41] :
_theResult___sfd__h84211;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4567 =
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q154;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4567 =
23'd0;
endcase
end
always@(guard__h83797 or
sfd___3__h175073 or out_sfd__h84214 or _theResult___sfd__h84211)
begin
case (guard__h83797)
2'b0, 2'b01:
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q155 =
sfd___3__h175073[63:41];
2'b10:
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q155 =
out_sfd__h84214;
2'b11:
CASE_guard3797_0b0_sfd___375073_BITS_63_TO_41__ETC__q155 =
_theResult___sfd__h84211;
endcase
end
always@(guard__h84323 or sfd___3__h175073 or _theResult___sfd__h84763)
begin
case (guard__h84323)
2'b0:
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q156 =
sfd___3__h175073[62:40];
2'b01, 2'b10, 2'b11:
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q156 =
_theResult___sfd__h84763;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h175073 or
guard__h84323 or
_theResult___sfd__h84763 or
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q156)
begin
case (execFpuSimple_fpu_inst[3:1])
3'b001, 3'b010:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4582 =
sfd___3__h175073[62:40];
3'b011:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4582 =
(guard__h84323 == 2'b0) ?
sfd___3__h175073[62:40] :
_theResult___sfd__h84763;
3'b100:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4582 =
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q156;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0b_ETC___d4582 =
23'd0;
endcase
end
always@(guard__h84323 or
sfd___3__h175073 or out_sfd__h84766 or _theResult___sfd__h84763)
begin
case (guard__h84323)
2'b0, 2'b01:
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q157 =
sfd___3__h175073[62:40];
2'b10:
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q157 =
out_sfd__h84766;
2'b11:
CASE_guard4323_0b0_sfd___375073_BITS_62_TO_40__ETC__q157 =
_theResult___sfd__h84763;
endcase
end
always@(execFpuSimple_fpu_inst or
NOT_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ__ETC___d3853 or
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4274 or
execFpuSimple_rVal2 or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280 =
execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31];
5'd6:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280 =
execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31];
5'd7:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ^
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31]);
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280 =
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
((execFpuSimple_fpu_inst[8:4] == 5'd10) ?
NOT_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ__ETC___d3853 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4274);
endcase
end
always@(execFpuSimple_fpu_inst or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 or
_theResult___snd_exp__h51881 or
_theResult___snd_sfd__h51882 or
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046 or
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 or
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415 or
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452 or
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207 or
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 or
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549 or
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5, 5'd6, 5'd7:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625;
5'd8,
5'd9,
5'd11,
5'd12,
5'd13,
5'd14,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 = 31'd0;
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
{ _theResult___snd_exp__h51881, _theResult___snd_sfd__h51882 };
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046 ==
8'd255 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 !=
23'd0) ?
31'h7FC00000 :
{ IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 };
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415 ==
8'd255 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452 !=
23'd0) ?
31'h7FC00000 :
{ IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452 };
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207 ==
8'd255 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 !=
23'd0) ?
31'h7FC00000 :
{ IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 };
5'd18:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549 ==
8'd255 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586 !=
23'd0) ?
31'h7FC00000 :
{ IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586 };
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
31'd0;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683 or
execFpuSimple_rVal1 or
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4659 or
in1_exp__h4123 or
in1_sfd__h4124 or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4667 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4670 or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4677)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4659;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4667;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0 ||
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4670;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4677;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4788 or
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4759 or
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4769 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4778)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 =
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4759;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 =
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4769;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4778;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4788;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4828 or
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4820 or
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4825)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 =
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4820;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(execFpuSimple_rVal1[31] ||
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418) &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4825;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4828;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4913 or
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4854 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4863 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4869 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4873 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4878 or
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4886 or
execFpuSimple_rVal1_BIT_31_05_OR_execFpuSimple_ETC___d4895 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4904)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4854;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4863;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4869;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4873;
5'd14:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4878;
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4886;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
execFpuSimple_rVal1_BIT_31_05_OR_execFpuSimple_ETC___d4895;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4904;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4913;
endcase
end
always@(execFpuSimple_fpu_inst or
dst_bits__h266 or
x__h219 or
x__h224 or
dst_bits__h251 or
dst_bits__h256 or
dst_bits__h261 or
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2693 or
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2711 or
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2714 or
x__h4812 or
execFpuSimple_rVal1_BITS_31_TO_0__q158 or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd8:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
x__h219;
5'd9:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
x__h224;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
dst_bits__h251;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
dst_bits__h256;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
dst_bits__h261;
5'd19:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2693;
5'd20:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2711;
5'd21:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2714;
5'd22:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
{ 54'd0, x__h4812 };
5'd23:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
{ {32{execFpuSimple_rVal1_BITS_31_TO_0__q158[31]}},
execFpuSimple_rVal1_BITS_31_TO_0__q158 };
5'd24:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
{ 32'hFFFFFFFF, execFpuSimple_rVal1[31:0] };
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
dst_bits__h266;
endcase
end
always@(execFpuSimple_fpu_inst or
dst_bits__h85501 or
x__h85464 or
x__h85469 or
dst_bits__h85486 or
dst_bits__h85491 or
dst_bits__h85496 or x__h93102 or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd8:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
x__h85464;
5'd9:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
x__h85469;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
dst_bits__h85486;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
dst_bits__h85491;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
dst_bits__h85496;
5'd22:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
{ 54'd0, x__h93102 };
5'd23, 5'd24:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
execFpuSimple_rVal1;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
dst_bits__h85501;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4607 or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4612)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd8, 5'd9, 5'd19:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4607;
5'd20, 5'd21:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4612;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690 =
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 or
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2192 or
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2198)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd8, 5'd9, 5'd19:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270 =
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2192;
5'd20, 5'd21:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270 =
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2198;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270 =
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267;
endcase
end
endmodule // module_execFpuSimple
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