533 lines
18 KiB
Verilog
533 lines
18 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:24:48 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1 reg
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// first O 231
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// RDY_first O 1 reg
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 231
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_deq I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// Combinational paths from inputs to outputs:
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// (specUpdate_incorrectSpeculation_kill_all,
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// specUpdate_incorrectSpeculation_kill_tag,
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// EN_deq,
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// EN_specUpdate_incorrectSpeculation) -> RDY_enq
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkAluDispToRegFifo(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first,
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RDY_first,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [230 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first
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output [230 : 0] first;
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output RDY_first;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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wire [230 : 0] first;
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wire RDY_deq,
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RDY_enq,
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RDY_first,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation;
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// inlined wires
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wire [11 : 0] m_m_specBits_0_lat_1$wget;
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wire m_m_valid_0_lat_0$whas;
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// register m_m_row_0
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reg [218 : 0] m_m_row_0;
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wire [218 : 0] m_m_row_0$D_IN;
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wire m_m_row_0$EN;
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// register m_m_specBits_0_rl
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reg [11 : 0] m_m_specBits_0_rl;
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wire [11 : 0] m_m_specBits_0_rl$D_IN;
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wire m_m_specBits_0_rl$EN;
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// register m_m_valid_0_rl
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reg m_m_valid_0_rl;
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wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_m_specBits_0_canon,
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CAN_FIRE_RL_m_m_valid_0_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_RL_m_m_specBits_0_canon,
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WILL_FIRE_RL_m_m_valid_0_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation;
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// inputs to muxes for submodule ports
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wire MUX_m_m_valid_0_lat_0$wset_1__SEL_1;
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// remaining internal signals
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reg [29 : 0] CASE_enq_x_BITS_225_TO_223_0_enq_x_BITS_225_TO_ETC__q3,
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CASE_m_m_row_0_BITS_213_TO_211_0_m_m_row_0_BIT_ETC__q7;
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reg [10 : 0] CASE_enq_x_BITS_195_TO_194_0_enq_x_BITS_195_TO_ETC__q4,
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CASE_m_m_row_0_BITS_183_TO_182_0_m_m_row_0_BIT_ETC__q8;
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reg [3 : 0] CASE_IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq__ETC__q2,
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CASE_IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_1_ETC__q6,
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IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56,
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224;
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reg [2 : 0] CASE_IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq__ETC__q1,
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CASE_IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_5_ETC__q5,
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IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq_x_BIT_ETC___d88,
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IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_53_OR__ETC___d256;
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wire [11 : 0] sb__h10895, upd__h1154;
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wire [8 : 0] IF_enq_x_BITS_193_TO_190_3_EQ_0_4_OR_NOT_enq_x_ETC___d140,
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IF_enq_x_BITS_193_TO_190_3_EQ_1_5_OR_NOT_enq_x_ETC___d139,
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IF_enq_x_BITS_193_TO_190_3_EQ_2_7_OR_NOT_enq_x_ETC___d138,
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_0_02_OR__ETC___d306,
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_1_03_OR__ETC___d305,
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_2_05_OR__ETC___d304;
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wire IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6;
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// action method enq
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assign RDY_enq = m_m_valid_0_lat_0$whas ? !1'd0 : !m_m_valid_0_rl ;
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assign CAN_FIRE_enq = m_m_valid_0_lat_0$whas ? !1'd0 : !m_m_valid_0_rl ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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assign RDY_deq = m_m_valid_0_rl ;
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assign CAN_FIRE_deq = m_m_valid_0_rl ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first
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assign first =
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{ m_m_row_0[218:214],
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CASE_m_m_row_0_BITS_213_TO_211_0_m_m_row_0_BIT_ETC__q7,
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CASE_m_m_row_0_BITS_183_TO_182_0_m_m_row_0_BIT_ETC__q8,
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m_m_row_0[172:0],
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m_m_specBits_0_rl } ;
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assign RDY_first = m_m_valid_0_rl ;
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// action method specUpdate_incorrectSpeculation
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assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_incorrectSpeculation =
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EN_specUpdate_incorrectSpeculation ;
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// action method specUpdate_correctSpeculation
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assign RDY_specUpdate_correctSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_correctSpeculation =
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EN_specUpdate_correctSpeculation ;
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// rule RL_m_m_valid_0_canon
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assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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// rule RL_m_m_specBits_0_canon
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assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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// inputs to muxes for submodule ports
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assign MUX_m_m_valid_0_lat_0$wset_1__SEL_1 =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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m_m_specBits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
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// inlined wires
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assign m_m_valid_0_lat_0$whas =
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MUX_m_m_valid_0_lat_0$wset_1__SEL_1 || EN_deq ;
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assign m_m_specBits_0_lat_1$wget =
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sb__h10895 & specUpdate_correctSpeculation_mask ;
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// register m_m_row_0
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assign m_m_row_0$D_IN =
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{ enq_x[230:226],
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CASE_enq_x_BITS_225_TO_223_0_enq_x_BITS_225_TO_ETC__q3,
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CASE_enq_x_BITS_195_TO_194_0_enq_x_BITS_195_TO_ETC__q4,
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enq_x[184:12] } ;
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assign m_m_row_0$EN = EN_enq ;
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// register m_m_specBits_0_rl
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assign m_m_specBits_0_rl$D_IN =
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EN_specUpdate_correctSpeculation ? upd__h1154 : sb__h10895 ;
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assign m_m_specBits_0_rl$EN = 1'd1 ;
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// register m_m_valid_0_rl
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assign m_m_valid_0_rl$D_IN =
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EN_enq ||
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IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 ;
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assign m_m_valid_0_rl$EN = 1'd1 ;
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// remaining internal signals
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assign IF_enq_x_BITS_193_TO_190_3_EQ_0_4_OR_NOT_enq_x_ETC___d140 =
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(enq_x[193:190] == 4'd0 ||
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enq_x[193:190] != 4'd1 && enq_x[193:190] != 4'd2 &&
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enq_x[193:190] != 4'd3 &&
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enq_x[193:190] != 4'd4 &&
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enq_x[193:190] != 4'd5 &&
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enq_x[193:190] != 4'd6 &&
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IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 ==
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4'd0) ?
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{ 4'd0, enq_x[189:185] } :
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IF_enq_x_BITS_193_TO_190_3_EQ_1_5_OR_NOT_enq_x_ETC___d139 ;
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assign IF_enq_x_BITS_193_TO_190_3_EQ_1_5_OR_NOT_enq_x_ETC___d139 =
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(enq_x[193:190] == 4'd1 ||
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enq_x[193:190] != 4'd2 && enq_x[193:190] != 4'd3 &&
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enq_x[193:190] != 4'd4 &&
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enq_x[193:190] != 4'd5 &&
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enq_x[193:190] != 4'd6 &&
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IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 ==
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4'd1) ?
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{ 4'd1, enq_x[189:185] } :
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IF_enq_x_BITS_193_TO_190_3_EQ_2_7_OR_NOT_enq_x_ETC___d138 ;
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assign IF_enq_x_BITS_193_TO_190_3_EQ_2_7_OR_NOT_enq_x_ETC___d138 =
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(enq_x[193:190] == 4'd2 ||
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enq_x[193:190] != 4'd3 && enq_x[193:190] != 4'd4 &&
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enq_x[193:190] != 4'd5 &&
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enq_x[193:190] != 4'd6 &&
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IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 ==
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4'd2) ?
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{ 4'd2,
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(enq_x[189:187] == 3'd0 ||
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enq_x[189:187] != 3'd1 &&
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IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq_x_BIT_ETC___d88 ==
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3'd0) ?
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{ 3'd0, enq_x[186:185] } :
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((enq_x[189:187] == 3'd1 ||
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IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq_x_BIT_ETC___d88 ==
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3'd1) ?
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{ 3'd1, enq_x[186:185] } :
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{ CASE_IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq__ETC__q1,
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2'bxx /* unspecified value */ }) } :
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((enq_x[193:190] == 4'd3 ||
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enq_x[193:190] != 4'd4 && enq_x[193:190] != 4'd5 &&
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enq_x[193:190] != 4'd6 &&
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IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 ==
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4'd3) ?
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{ 4'd3, enq_x[189:185] } :
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((enq_x[193:190] == 4'd4 ||
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enq_x[193:190] != 4'd5 && enq_x[193:190] != 4'd6 &&
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IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 ==
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4'd4) ?
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{ 4'd4, 5'bxxxxx /* unspecified value */ } :
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((enq_x[193:190] == 4'd5 ||
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enq_x[193:190] != 4'd6 &&
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IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 ==
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4'd5) ?
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{ 4'd5, 5'bxxxxx /* unspecified value */ } :
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((enq_x[193:190] == 4'd6 ||
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IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 ==
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4'd6) ?
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{ 4'd6, enq_x[189:185] } :
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{ CASE_IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq__ETC__q2,
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5'bxxxxx /* unspecified value */ })))) ;
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assign IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_0_02_OR__ETC___d306 =
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(m_m_row_0[181:178] == 4'd0 ||
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m_m_row_0[181:178] != 4'd1 && m_m_row_0[181:178] != 4'd2 &&
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m_m_row_0[181:178] != 4'd3 &&
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m_m_row_0[181:178] != 4'd4 &&
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m_m_row_0[181:178] != 4'd5 &&
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m_m_row_0[181:178] != 4'd6 &&
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 ==
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4'd0) ?
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{ 4'd0, m_m_row_0[177:173] } :
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_1_03_OR__ETC___d305 ;
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assign IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_1_03_OR__ETC___d305 =
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(m_m_row_0[181:178] == 4'd1 ||
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m_m_row_0[181:178] != 4'd2 && m_m_row_0[181:178] != 4'd3 &&
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m_m_row_0[181:178] != 4'd4 &&
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m_m_row_0[181:178] != 4'd5 &&
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m_m_row_0[181:178] != 4'd6 &&
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 ==
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4'd1) ?
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{ 4'd1, m_m_row_0[177:173] } :
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_2_05_OR__ETC___d304 ;
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assign IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_2_05_OR__ETC___d304 =
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(m_m_row_0[181:178] == 4'd2 ||
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m_m_row_0[181:178] != 4'd3 && m_m_row_0[181:178] != 4'd4 &&
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m_m_row_0[181:178] != 4'd5 &&
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m_m_row_0[181:178] != 4'd6 &&
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 ==
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4'd2) ?
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{ 4'd2,
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(m_m_row_0[177:175] == 3'd0 ||
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m_m_row_0[177:175] != 3'd1 &&
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IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_53_OR__ETC___d256 ==
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3'd0) ?
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{ 3'd0, m_m_row_0[174:173] } :
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((m_m_row_0[177:175] == 3'd1 ||
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IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_53_OR__ETC___d256 ==
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3'd1) ?
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{ 3'd1, m_m_row_0[174:173] } :
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{ CASE_IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_5_ETC__q5,
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2'bxx /* unspecified value */ }) } :
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((m_m_row_0[181:178] == 4'd3 ||
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m_m_row_0[181:178] != 4'd4 && m_m_row_0[181:178] != 4'd5 &&
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m_m_row_0[181:178] != 4'd6 &&
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 ==
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4'd3) ?
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{ 4'd3, m_m_row_0[177:173] } :
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((m_m_row_0[181:178] == 4'd4 ||
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m_m_row_0[181:178] != 4'd5 &&
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m_m_row_0[181:178] != 4'd6 &&
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 ==
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4'd4) ?
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{ 4'd4, 5'bxxxxx /* unspecified value */ } :
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((m_m_row_0[181:178] == 4'd5 ||
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m_m_row_0[181:178] != 4'd6 &&
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 ==
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4'd5) ?
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{ 4'd5, 5'bxxxxx /* unspecified value */ } :
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((m_m_row_0[181:178] == 4'd6 ||
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IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 ==
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4'd6) ?
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{ 4'd6, m_m_row_0[177:173] } :
|
|
{ CASE_IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_1_ETC__q6,
|
|
5'bxxxxx /* unspecified value */ })))) ;
|
|
assign IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 =
|
|
m_m_valid_0_lat_0$whas ? 1'd0 : m_m_valid_0_rl ;
|
|
assign sb__h10895 = EN_enq ? enq_x[11:0] : m_m_specBits_0_rl ;
|
|
assign upd__h1154 = m_m_specBits_0_lat_1$wget ;
|
|
always@(enq_x)
|
|
begin
|
|
case (enq_x[193:190])
|
|
4'd7, 4'd8, 4'd9, 4'd10, 4'd11:
|
|
IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 =
|
|
enq_x[193:190];
|
|
default: IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56 =
|
|
4'd12;
|
|
endcase
|
|
end
|
|
always@(enq_x)
|
|
begin
|
|
case (enq_x[189:187])
|
|
3'd2, 3'd3:
|
|
IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq_x_BIT_ETC___d88 =
|
|
enq_x[189:187];
|
|
default: IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq_x_BIT_ETC___d88 =
|
|
3'd4;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[181:178])
|
|
4'd7, 4'd8, 4'd9, 4'd10, 4'd11:
|
|
IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 =
|
|
m_m_row_0[181:178];
|
|
default: IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224 =
|
|
4'd12;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[177:175])
|
|
3'd2, 3'd3:
|
|
IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_53_OR__ETC___d256 =
|
|
m_m_row_0[177:175];
|
|
default: IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_53_OR__ETC___d256 =
|
|
3'd4;
|
|
endcase
|
|
end
|
|
always@(IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq_x_BIT_ETC___d88)
|
|
begin
|
|
case (IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq_x_BIT_ETC___d88)
|
|
3'd2, 3'd3:
|
|
CASE_IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq__ETC__q1 =
|
|
IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq_x_BIT_ETC___d88;
|
|
default: CASE_IF_enq_x_BITS_189_TO_187_1_EQ_2_5_OR_enq__ETC__q1 = 3'd4;
|
|
endcase
|
|
end
|
|
always@(IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56)
|
|
begin
|
|
case (IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56)
|
|
4'd7, 4'd8, 4'd9, 4'd10, 4'd11:
|
|
CASE_IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq__ETC__q2 =
|
|
IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq_x_BIT_ETC___d56;
|
|
default: CASE_IF_enq_x_BITS_193_TO_190_3_EQ_7_7_OR_enq__ETC__q2 = 4'd12;
|
|
endcase
|
|
end
|
|
always@(enq_x)
|
|
begin
|
|
case (enq_x[225:223])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_enq_x_BITS_225_TO_223_0_enq_x_BITS_225_TO_ETC__q3 =
|
|
enq_x[225:196];
|
|
default: CASE_enq_x_BITS_225_TO_223_0_enq_x_BITS_225_TO_ETC__q3 =
|
|
{ 3'd5,
|
|
27'bxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
endcase
|
|
end
|
|
always@(enq_x or IF_enq_x_BITS_193_TO_190_3_EQ_0_4_OR_NOT_enq_x_ETC___d140)
|
|
begin
|
|
case (enq_x[195:194])
|
|
2'd0:
|
|
CASE_enq_x_BITS_195_TO_194_0_enq_x_BITS_195_TO_ETC__q4 =
|
|
enq_x[195:185];
|
|
2'd1:
|
|
CASE_enq_x_BITS_195_TO_194_0_enq_x_BITS_195_TO_ETC__q4 =
|
|
{ enq_x[195:194],
|
|
IF_enq_x_BITS_193_TO_190_3_EQ_0_4_OR_NOT_enq_x_ETC___d140 };
|
|
default: CASE_enq_x_BITS_195_TO_194_0_enq_x_BITS_195_TO_ETC__q4 =
|
|
{ 2'd2, 9'bxxxxxxxxx /* unspecified value */ };
|
|
endcase
|
|
end
|
|
always@(IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_53_OR__ETC___d256)
|
|
begin
|
|
case (IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_53_OR__ETC___d256)
|
|
3'd2, 3'd3:
|
|
CASE_IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_5_ETC__q5 =
|
|
IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_53_OR__ETC___d256;
|
|
default: CASE_IF_m_m_row_0_83_BITS_177_TO_175_49_EQ_2_5_ETC__q5 = 3'd4;
|
|
endcase
|
|
end
|
|
always@(IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224)
|
|
begin
|
|
case (IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224)
|
|
4'd7, 4'd8, 4'd9, 4'd10, 4'd11:
|
|
CASE_IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_1_ETC__q6 =
|
|
IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_15_OR__ETC___d224;
|
|
default: CASE_IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_7_1_ETC__q6 = 4'd12;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[213:211])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_m_m_row_0_BITS_213_TO_211_0_m_m_row_0_BIT_ETC__q7 =
|
|
m_m_row_0[213:184];
|
|
default: CASE_m_m_row_0_BITS_213_TO_211_0_m_m_row_0_BIT_ETC__q7 =
|
|
{ 3'd5,
|
|
27'bxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
endcase
|
|
end
|
|
always@(m_m_row_0 or
|
|
IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_0_02_OR__ETC___d306)
|
|
begin
|
|
case (m_m_row_0[183:182])
|
|
2'd0:
|
|
CASE_m_m_row_0_BITS_183_TO_182_0_m_m_row_0_BIT_ETC__q8 =
|
|
m_m_row_0[183:173];
|
|
2'd1:
|
|
CASE_m_m_row_0_BITS_183_TO_182_0_m_m_row_0_BIT_ETC__q8 =
|
|
{ m_m_row_0[183:182],
|
|
IF_m_m_row_0_83_BITS_181_TO_178_01_EQ_0_02_OR__ETC___d306 };
|
|
default: CASE_m_m_row_0_BITS_183_TO_182_0_m_m_row_0_BIT_ETC__q8 =
|
|
{ 2'd2, 9'bxxxxxxxxx /* unspecified value */ };
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_specBits_0_rl$EN)
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN;
|
|
if (m_m_valid_0_rl$EN)
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN;
|
|
end
|
|
if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_row_0 = 219'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_specBits_0_rl = 12'hAAA;
|
|
m_m_valid_0_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_enq && IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkAluDispToRegFifo
|
|
|