6731 lines
231 KiB
Verilog
6731 lines
231 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:21:11 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// cRqTransfer_getRq O 227
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// RDY_cRqTransfer_getRq O 1 const
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// cRqTransfer_getEmptyEntryInit O 3 reg
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// RDY_cRqTransfer_getEmptyEntryInit O 1
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// sendRsToP_cRq_getState O 3
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// RDY_sendRsToP_cRq_getState O 1 const
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// sendRsToP_cRq_getRq O 227
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// RDY_sendRsToP_cRq_getRq O 1 const
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// sendRsToP_cRq_getSlot O 58
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// RDY_sendRsToP_cRq_getSlot O 1 const
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// sendRsToP_cRq_getData O 517
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// RDY_sendRsToP_cRq_getData O 1 const
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// RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData O 1 const
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// sendRqToP_getRq O 227
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// RDY_sendRqToP_getRq O 1 const
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// sendRqToP_getSlot O 58
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// RDY_sendRqToP_getSlot O 1 const
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// RDY_pipelineResp_releaseEntry O 1
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// pipelineResp_getState O 3
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// RDY_pipelineResp_getState O 1 const
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// pipelineResp_getRq O 227
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// RDY_pipelineResp_getRq O 1 const
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// pipelineResp_getSlot O 58
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// RDY_pipelineResp_getSlot O 1 const
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// RDY_pipelineResp_setData O 1 const
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// RDY_pipelineResp_setStateSlot O 1 const
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// pipelineResp_getSucc O 4
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// RDY_pipelineResp_getSucc O 1 const
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// RDY_pipelineResp_setSucc O 1 const
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// pipelineResp_searchEndOfChain O 4
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// RDY_pipelineResp_searchEndOfChain O 1 const
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// emptyForFlush O 1
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// RDY_emptyForFlush O 1 const
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// stuck_get O 233
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// RDY_stuck_get O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// cRqTransfer_getRq_n I 3
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// cRqTransfer_getEmptyEntryInit_r I 227
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// sendRsToP_cRq_getState_n I 3
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// sendRsToP_cRq_getRq_n I 3
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// sendRsToP_cRq_getSlot_n I 3
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// sendRsToP_cRq_getData_n I 3
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_n I 3
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_slot I 58
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// sendRqToP_getRq_n I 3
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// sendRqToP_getSlot_n I 3
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// pipelineResp_releaseEntry_n I 3
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// pipelineResp_getState_n I 3
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// pipelineResp_getRq_n I 3
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// pipelineResp_getSlot_n I 3
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// pipelineResp_setData_n I 3
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// pipelineResp_setData_d I 517
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// pipelineResp_setStateSlot_n I 3
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// pipelineResp_setStateSlot_state I 3
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// pipelineResp_setStateSlot_slot I 58
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// pipelineResp_getSucc_n I 3
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// pipelineResp_setSucc_n I 3
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// pipelineResp_setSucc_succ I 4
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// pipelineResp_searchEndOfChain_addr I 64
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// EN_sendRsToP_cRq_setWaitSt_setSlot_clearData I 1
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// EN_pipelineResp_releaseEntry I 1
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// EN_pipelineResp_setData I 1
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// EN_pipelineResp_setStateSlot I 1
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// EN_pipelineResp_setSucc I 1
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// EN_cRqTransfer_getEmptyEntryInit I 1
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// EN_stuck_get I 1 unused
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//
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// Combinational paths from inputs to outputs:
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// cRqTransfer_getRq_n -> cRqTransfer_getRq
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// sendRsToP_cRq_getState_n -> sendRsToP_cRq_getState
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// sendRsToP_cRq_getRq_n -> sendRsToP_cRq_getRq
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// sendRsToP_cRq_getSlot_n -> sendRsToP_cRq_getSlot
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// sendRsToP_cRq_getData_n -> sendRsToP_cRq_getData
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// sendRqToP_getRq_n -> sendRqToP_getRq
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// sendRqToP_getSlot_n -> sendRqToP_getSlot
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// (pipelineResp_getState_n,
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_n,
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// EN_sendRsToP_cRq_setWaitSt_setSlot_clearData) -> pipelineResp_getState
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// pipelineResp_getRq_n -> pipelineResp_getRq
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// (pipelineResp_getSlot_n,
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_n,
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_slot,
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// EN_sendRsToP_cRq_setWaitSt_setSlot_clearData) -> pipelineResp_getSlot
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// pipelineResp_getSucc_n -> pipelineResp_getSucc
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// (pipelineResp_searchEndOfChain_addr,
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_n,
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// EN_sendRsToP_cRq_setWaitSt_setSlot_clearData) -> pipelineResp_searchEndOfChain
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDCRqMshrWrapper(CLK,
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RST_N,
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cRqTransfer_getRq_n,
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cRqTransfer_getRq,
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RDY_cRqTransfer_getRq,
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cRqTransfer_getEmptyEntryInit_r,
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EN_cRqTransfer_getEmptyEntryInit,
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cRqTransfer_getEmptyEntryInit,
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RDY_cRqTransfer_getEmptyEntryInit,
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sendRsToP_cRq_getState_n,
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sendRsToP_cRq_getState,
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RDY_sendRsToP_cRq_getState,
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sendRsToP_cRq_getRq_n,
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sendRsToP_cRq_getRq,
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RDY_sendRsToP_cRq_getRq,
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sendRsToP_cRq_getSlot_n,
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sendRsToP_cRq_getSlot,
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RDY_sendRsToP_cRq_getSlot,
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sendRsToP_cRq_getData_n,
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sendRsToP_cRq_getData,
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RDY_sendRsToP_cRq_getData,
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sendRsToP_cRq_setWaitSt_setSlot_clearData_n,
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sendRsToP_cRq_setWaitSt_setSlot_clearData_slot,
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EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
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RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData,
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sendRqToP_getRq_n,
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sendRqToP_getRq,
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RDY_sendRqToP_getRq,
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sendRqToP_getSlot_n,
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sendRqToP_getSlot,
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RDY_sendRqToP_getSlot,
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pipelineResp_releaseEntry_n,
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EN_pipelineResp_releaseEntry,
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RDY_pipelineResp_releaseEntry,
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pipelineResp_getState_n,
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pipelineResp_getState,
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RDY_pipelineResp_getState,
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pipelineResp_getRq_n,
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pipelineResp_getRq,
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RDY_pipelineResp_getRq,
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pipelineResp_getSlot_n,
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pipelineResp_getSlot,
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RDY_pipelineResp_getSlot,
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pipelineResp_setData_n,
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pipelineResp_setData_d,
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EN_pipelineResp_setData,
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RDY_pipelineResp_setData,
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pipelineResp_setStateSlot_n,
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pipelineResp_setStateSlot_state,
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pipelineResp_setStateSlot_slot,
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EN_pipelineResp_setStateSlot,
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RDY_pipelineResp_setStateSlot,
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pipelineResp_getSucc_n,
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pipelineResp_getSucc,
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RDY_pipelineResp_getSucc,
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pipelineResp_setSucc_n,
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pipelineResp_setSucc_succ,
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EN_pipelineResp_setSucc,
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RDY_pipelineResp_setSucc,
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pipelineResp_searchEndOfChain_addr,
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pipelineResp_searchEndOfChain,
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RDY_pipelineResp_searchEndOfChain,
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emptyForFlush,
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RDY_emptyForFlush,
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EN_stuck_get,
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stuck_get,
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RDY_stuck_get);
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input CLK;
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input RST_N;
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// value method cRqTransfer_getRq
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input [2 : 0] cRqTransfer_getRq_n;
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output [226 : 0] cRqTransfer_getRq;
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output RDY_cRqTransfer_getRq;
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// actionvalue method cRqTransfer_getEmptyEntryInit
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input [226 : 0] cRqTransfer_getEmptyEntryInit_r;
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input EN_cRqTransfer_getEmptyEntryInit;
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output [2 : 0] cRqTransfer_getEmptyEntryInit;
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output RDY_cRqTransfer_getEmptyEntryInit;
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// value method sendRsToP_cRq_getState
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input [2 : 0] sendRsToP_cRq_getState_n;
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output [2 : 0] sendRsToP_cRq_getState;
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output RDY_sendRsToP_cRq_getState;
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// value method sendRsToP_cRq_getRq
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input [2 : 0] sendRsToP_cRq_getRq_n;
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output [226 : 0] sendRsToP_cRq_getRq;
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output RDY_sendRsToP_cRq_getRq;
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// value method sendRsToP_cRq_getSlot
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input [2 : 0] sendRsToP_cRq_getSlot_n;
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output [57 : 0] sendRsToP_cRq_getSlot;
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output RDY_sendRsToP_cRq_getSlot;
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// value method sendRsToP_cRq_getData
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input [2 : 0] sendRsToP_cRq_getData_n;
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output [516 : 0] sendRsToP_cRq_getData;
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output RDY_sendRsToP_cRq_getData;
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// action method sendRsToP_cRq_setWaitSt_setSlot_clearData
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input [2 : 0] sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
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input [57 : 0] sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
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input EN_sendRsToP_cRq_setWaitSt_setSlot_clearData;
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output RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData;
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// value method sendRqToP_getRq
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input [2 : 0] sendRqToP_getRq_n;
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output [226 : 0] sendRqToP_getRq;
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output RDY_sendRqToP_getRq;
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// value method sendRqToP_getSlot
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input [2 : 0] sendRqToP_getSlot_n;
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output [57 : 0] sendRqToP_getSlot;
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output RDY_sendRqToP_getSlot;
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// action method pipelineResp_releaseEntry
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input [2 : 0] pipelineResp_releaseEntry_n;
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input EN_pipelineResp_releaseEntry;
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output RDY_pipelineResp_releaseEntry;
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// value method pipelineResp_getState
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input [2 : 0] pipelineResp_getState_n;
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output [2 : 0] pipelineResp_getState;
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output RDY_pipelineResp_getState;
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// value method pipelineResp_getRq
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input [2 : 0] pipelineResp_getRq_n;
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output [226 : 0] pipelineResp_getRq;
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output RDY_pipelineResp_getRq;
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// value method pipelineResp_getSlot
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input [2 : 0] pipelineResp_getSlot_n;
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output [57 : 0] pipelineResp_getSlot;
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output RDY_pipelineResp_getSlot;
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// action method pipelineResp_setData
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input [2 : 0] pipelineResp_setData_n;
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input [516 : 0] pipelineResp_setData_d;
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input EN_pipelineResp_setData;
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output RDY_pipelineResp_setData;
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// action method pipelineResp_setStateSlot
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input [2 : 0] pipelineResp_setStateSlot_n;
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input [2 : 0] pipelineResp_setStateSlot_state;
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input [57 : 0] pipelineResp_setStateSlot_slot;
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input EN_pipelineResp_setStateSlot;
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output RDY_pipelineResp_setStateSlot;
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// value method pipelineResp_getSucc
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input [2 : 0] pipelineResp_getSucc_n;
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output [3 : 0] pipelineResp_getSucc;
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output RDY_pipelineResp_getSucc;
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// action method pipelineResp_setSucc
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input [2 : 0] pipelineResp_setSucc_n;
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input [3 : 0] pipelineResp_setSucc_succ;
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input EN_pipelineResp_setSucc;
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output RDY_pipelineResp_setSucc;
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// value method pipelineResp_searchEndOfChain
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input [63 : 0] pipelineResp_searchEndOfChain_addr;
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output [3 : 0] pipelineResp_searchEndOfChain;
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output RDY_pipelineResp_searchEndOfChain;
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// value method emptyForFlush
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output emptyForFlush;
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output RDY_emptyForFlush;
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// actionvalue method stuck_get
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input EN_stuck_get;
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output [232 : 0] stuck_get;
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output RDY_stuck_get;
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// signals for module outputs
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reg [2 : 0] pipelineResp_getState, sendRsToP_cRq_getState;
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wire [516 : 0] sendRsToP_cRq_getData;
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wire [232 : 0] stuck_get;
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wire [226 : 0] cRqTransfer_getRq,
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pipelineResp_getRq,
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sendRqToP_getRq,
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sendRsToP_cRq_getRq;
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wire [57 : 0] pipelineResp_getSlot,
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sendRqToP_getSlot,
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sendRsToP_cRq_getSlot;
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wire [3 : 0] pipelineResp_getSucc, pipelineResp_searchEndOfChain;
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wire [2 : 0] cRqTransfer_getEmptyEntryInit;
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wire RDY_cRqTransfer_getEmptyEntryInit,
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RDY_cRqTransfer_getRq,
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RDY_emptyForFlush,
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RDY_pipelineResp_getRq,
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RDY_pipelineResp_getSlot,
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RDY_pipelineResp_getState,
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RDY_pipelineResp_getSucc,
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RDY_pipelineResp_releaseEntry,
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RDY_pipelineResp_searchEndOfChain,
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RDY_pipelineResp_setData,
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RDY_pipelineResp_setStateSlot,
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RDY_pipelineResp_setSucc,
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RDY_sendRqToP_getRq,
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RDY_sendRqToP_getSlot,
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RDY_sendRsToP_cRq_getData,
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RDY_sendRsToP_cRq_getRq,
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RDY_sendRsToP_cRq_getSlot,
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RDY_sendRsToP_cRq_getState,
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RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData,
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RDY_stuck_get,
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emptyForFlush;
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// inlined wires
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wire [57 : 0] m_m_slotVec_0_lat_2$wget;
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wire [2 : 0] m_m_stateVec_0_lat_1$wget,
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m_m_stateVec_1_lat_1$wget,
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m_m_stateVec_2_lat_1$wget,
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m_m_stateVec_3_lat_1$wget,
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m_m_stateVec_4_lat_1$wget,
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m_m_stateVec_5_lat_1$wget,
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m_m_stateVec_6_lat_1$wget,
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m_m_stateVec_7_lat_1$wget;
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wire m_m_dataValidVec_0_lat_1$whas,
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m_m_dataValidVec_1_lat_1$whas,
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m_m_dataValidVec_2_lat_1$whas,
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m_m_dataValidVec_3_lat_1$whas,
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m_m_dataValidVec_4_lat_1$whas,
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m_m_dataValidVec_5_lat_1$whas,
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m_m_dataValidVec_6_lat_1$whas,
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m_m_dataValidVec_7_lat_1$whas,
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m_m_stateVec_0_lat_0$whas,
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m_m_stateVec_0_lat_1$whas,
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m_m_stateVec_0_lat_2$whas,
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m_m_stateVec_1_lat_0$whas,
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m_m_stateVec_1_lat_1$whas,
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m_m_stateVec_1_lat_2$whas,
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m_m_stateVec_2_lat_0$whas,
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m_m_stateVec_2_lat_1$whas,
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m_m_stateVec_2_lat_2$whas,
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m_m_stateVec_3_lat_0$whas,
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m_m_stateVec_3_lat_1$whas,
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m_m_stateVec_3_lat_2$whas,
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m_m_stateVec_4_lat_0$whas,
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m_m_stateVec_4_lat_1$whas,
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m_m_stateVec_4_lat_2$whas,
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m_m_stateVec_5_lat_0$whas,
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m_m_stateVec_5_lat_1$whas,
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m_m_stateVec_5_lat_2$whas,
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m_m_stateVec_6_lat_0$whas,
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m_m_stateVec_6_lat_1$whas,
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m_m_stateVec_6_lat_2$whas,
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m_m_stateVec_7_lat_0$whas,
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m_m_stateVec_7_lat_1$whas,
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m_m_stateVec_7_lat_2$whas,
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m_m_succValidVec_0_lat_1$whas,
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m_m_succValidVec_1_lat_1$whas,
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m_m_succValidVec_2_lat_1$whas,
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m_m_succValidVec_3_lat_1$whas,
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m_m_succValidVec_4_lat_1$whas,
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m_m_succValidVec_5_lat_1$whas,
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m_m_succValidVec_6_lat_1$whas,
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m_m_succValidVec_7_lat_1$whas;
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// register m_m_dataValidVec_0_rl
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reg m_m_dataValidVec_0_rl;
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wire m_m_dataValidVec_0_rl$D_IN, m_m_dataValidVec_0_rl$EN;
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// register m_m_dataValidVec_1_rl
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reg m_m_dataValidVec_1_rl;
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wire m_m_dataValidVec_1_rl$D_IN, m_m_dataValidVec_1_rl$EN;
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// register m_m_dataValidVec_2_rl
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reg m_m_dataValidVec_2_rl;
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wire m_m_dataValidVec_2_rl$D_IN, m_m_dataValidVec_2_rl$EN;
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// register m_m_dataValidVec_3_rl
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reg m_m_dataValidVec_3_rl;
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wire m_m_dataValidVec_3_rl$D_IN, m_m_dataValidVec_3_rl$EN;
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// register m_m_dataValidVec_4_rl
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reg m_m_dataValidVec_4_rl;
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wire m_m_dataValidVec_4_rl$D_IN, m_m_dataValidVec_4_rl$EN;
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// register m_m_dataValidVec_5_rl
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reg m_m_dataValidVec_5_rl;
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wire m_m_dataValidVec_5_rl$D_IN, m_m_dataValidVec_5_rl$EN;
|
|
|
|
// register m_m_dataValidVec_6_rl
|
|
reg m_m_dataValidVec_6_rl;
|
|
wire m_m_dataValidVec_6_rl$D_IN, m_m_dataValidVec_6_rl$EN;
|
|
|
|
// register m_m_dataValidVec_7_rl
|
|
reg m_m_dataValidVec_7_rl;
|
|
wire m_m_dataValidVec_7_rl$D_IN, m_m_dataValidVec_7_rl$EN;
|
|
|
|
// register m_m_initIdx
|
|
reg [2 : 0] m_m_initIdx;
|
|
wire [2 : 0] m_m_initIdx$D_IN;
|
|
wire m_m_initIdx$EN;
|
|
|
|
// register m_m_inited
|
|
reg m_m_inited;
|
|
wire m_m_inited$D_IN, m_m_inited$EN;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
reg [226 : 0] m_m_reqVec_0_rl;
|
|
wire [226 : 0] m_m_reqVec_0_rl$D_IN;
|
|
wire m_m_reqVec_0_rl$EN;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
reg [226 : 0] m_m_reqVec_1_rl;
|
|
wire [226 : 0] m_m_reqVec_1_rl$D_IN;
|
|
wire m_m_reqVec_1_rl$EN;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
reg [226 : 0] m_m_reqVec_2_rl;
|
|
wire [226 : 0] m_m_reqVec_2_rl$D_IN;
|
|
wire m_m_reqVec_2_rl$EN;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
reg [226 : 0] m_m_reqVec_3_rl;
|
|
wire [226 : 0] m_m_reqVec_3_rl$D_IN;
|
|
wire m_m_reqVec_3_rl$EN;
|
|
|
|
// register m_m_reqVec_4_rl
|
|
reg [226 : 0] m_m_reqVec_4_rl;
|
|
wire [226 : 0] m_m_reqVec_4_rl$D_IN;
|
|
wire m_m_reqVec_4_rl$EN;
|
|
|
|
// register m_m_reqVec_5_rl
|
|
reg [226 : 0] m_m_reqVec_5_rl;
|
|
wire [226 : 0] m_m_reqVec_5_rl$D_IN;
|
|
wire m_m_reqVec_5_rl$EN;
|
|
|
|
// register m_m_reqVec_6_rl
|
|
reg [226 : 0] m_m_reqVec_6_rl;
|
|
wire [226 : 0] m_m_reqVec_6_rl$D_IN;
|
|
wire m_m_reqVec_6_rl$EN;
|
|
|
|
// register m_m_reqVec_7_rl
|
|
reg [226 : 0] m_m_reqVec_7_rl;
|
|
wire [226 : 0] m_m_reqVec_7_rl$D_IN;
|
|
wire m_m_reqVec_7_rl$EN;
|
|
|
|
// register m_m_slotVec_0_rl
|
|
reg [57 : 0] m_m_slotVec_0_rl;
|
|
wire [57 : 0] m_m_slotVec_0_rl$D_IN;
|
|
wire m_m_slotVec_0_rl$EN;
|
|
|
|
// register m_m_slotVec_1_rl
|
|
reg [57 : 0] m_m_slotVec_1_rl;
|
|
wire [57 : 0] m_m_slotVec_1_rl$D_IN;
|
|
wire m_m_slotVec_1_rl$EN;
|
|
|
|
// register m_m_slotVec_2_rl
|
|
reg [57 : 0] m_m_slotVec_2_rl;
|
|
wire [57 : 0] m_m_slotVec_2_rl$D_IN;
|
|
wire m_m_slotVec_2_rl$EN;
|
|
|
|
// register m_m_slotVec_3_rl
|
|
reg [57 : 0] m_m_slotVec_3_rl;
|
|
wire [57 : 0] m_m_slotVec_3_rl$D_IN;
|
|
wire m_m_slotVec_3_rl$EN;
|
|
|
|
// register m_m_slotVec_4_rl
|
|
reg [57 : 0] m_m_slotVec_4_rl;
|
|
wire [57 : 0] m_m_slotVec_4_rl$D_IN;
|
|
wire m_m_slotVec_4_rl$EN;
|
|
|
|
// register m_m_slotVec_5_rl
|
|
reg [57 : 0] m_m_slotVec_5_rl;
|
|
wire [57 : 0] m_m_slotVec_5_rl$D_IN;
|
|
wire m_m_slotVec_5_rl$EN;
|
|
|
|
// register m_m_slotVec_6_rl
|
|
reg [57 : 0] m_m_slotVec_6_rl;
|
|
wire [57 : 0] m_m_slotVec_6_rl$D_IN;
|
|
wire m_m_slotVec_6_rl$EN;
|
|
|
|
// register m_m_slotVec_7_rl
|
|
reg [57 : 0] m_m_slotVec_7_rl;
|
|
wire [57 : 0] m_m_slotVec_7_rl$D_IN;
|
|
wire m_m_slotVec_7_rl$EN;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
reg [2 : 0] m_m_stateVec_0_rl;
|
|
wire [2 : 0] m_m_stateVec_0_rl$D_IN;
|
|
wire m_m_stateVec_0_rl$EN;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
reg [2 : 0] m_m_stateVec_1_rl;
|
|
wire [2 : 0] m_m_stateVec_1_rl$D_IN;
|
|
wire m_m_stateVec_1_rl$EN;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
reg [2 : 0] m_m_stateVec_2_rl;
|
|
wire [2 : 0] m_m_stateVec_2_rl$D_IN;
|
|
wire m_m_stateVec_2_rl$EN;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
reg [2 : 0] m_m_stateVec_3_rl;
|
|
wire [2 : 0] m_m_stateVec_3_rl$D_IN;
|
|
wire m_m_stateVec_3_rl$EN;
|
|
|
|
// register m_m_stateVec_4_rl
|
|
reg [2 : 0] m_m_stateVec_4_rl;
|
|
wire [2 : 0] m_m_stateVec_4_rl$D_IN;
|
|
wire m_m_stateVec_4_rl$EN;
|
|
|
|
// register m_m_stateVec_5_rl
|
|
reg [2 : 0] m_m_stateVec_5_rl;
|
|
wire [2 : 0] m_m_stateVec_5_rl$D_IN;
|
|
wire m_m_stateVec_5_rl$EN;
|
|
|
|
// register m_m_stateVec_6_rl
|
|
reg [2 : 0] m_m_stateVec_6_rl;
|
|
wire [2 : 0] m_m_stateVec_6_rl$D_IN;
|
|
wire m_m_stateVec_6_rl$EN;
|
|
|
|
// register m_m_stateVec_7_rl
|
|
reg [2 : 0] m_m_stateVec_7_rl;
|
|
wire [2 : 0] m_m_stateVec_7_rl$D_IN;
|
|
wire m_m_stateVec_7_rl$EN;
|
|
|
|
// register m_m_succValidVec_0_rl
|
|
reg m_m_succValidVec_0_rl;
|
|
wire m_m_succValidVec_0_rl$D_IN, m_m_succValidVec_0_rl$EN;
|
|
|
|
// register m_m_succValidVec_1_rl
|
|
reg m_m_succValidVec_1_rl;
|
|
wire m_m_succValidVec_1_rl$D_IN, m_m_succValidVec_1_rl$EN;
|
|
|
|
// register m_m_succValidVec_2_rl
|
|
reg m_m_succValidVec_2_rl;
|
|
wire m_m_succValidVec_2_rl$D_IN, m_m_succValidVec_2_rl$EN;
|
|
|
|
// register m_m_succValidVec_3_rl
|
|
reg m_m_succValidVec_3_rl;
|
|
wire m_m_succValidVec_3_rl$D_IN, m_m_succValidVec_3_rl$EN;
|
|
|
|
// register m_m_succValidVec_4_rl
|
|
reg m_m_succValidVec_4_rl;
|
|
wire m_m_succValidVec_4_rl$D_IN, m_m_succValidVec_4_rl$EN;
|
|
|
|
// register m_m_succValidVec_5_rl
|
|
reg m_m_succValidVec_5_rl;
|
|
wire m_m_succValidVec_5_rl$D_IN, m_m_succValidVec_5_rl$EN;
|
|
|
|
// register m_m_succValidVec_6_rl
|
|
reg m_m_succValidVec_6_rl;
|
|
wire m_m_succValidVec_6_rl$D_IN, m_m_succValidVec_6_rl$EN;
|
|
|
|
// register m_m_succValidVec_7_rl
|
|
reg m_m_succValidVec_7_rl;
|
|
wire m_m_succValidVec_7_rl$D_IN, m_m_succValidVec_7_rl$EN;
|
|
|
|
// ports of submodule m_m_dataFile
|
|
wire [515 : 0] m_m_dataFile$D_IN, m_m_dataFile$D_OUT_1;
|
|
wire [2 : 0] m_m_dataFile$ADDR_1,
|
|
m_m_dataFile$ADDR_2,
|
|
m_m_dataFile$ADDR_3,
|
|
m_m_dataFile$ADDR_4,
|
|
m_m_dataFile$ADDR_5,
|
|
m_m_dataFile$ADDR_IN;
|
|
wire m_m_dataFile$WE;
|
|
|
|
// ports of submodule m_m_emptyEntryQ
|
|
wire [2 : 0] m_m_emptyEntryQ$D_IN, m_m_emptyEntryQ$D_OUT;
|
|
wire m_m_emptyEntryQ$CLR,
|
|
m_m_emptyEntryQ$DEQ,
|
|
m_m_emptyEntryQ$EMPTY_N,
|
|
m_m_emptyEntryQ$ENQ,
|
|
m_m_emptyEntryQ$FULL_N;
|
|
|
|
// ports of submodule m_m_succFile
|
|
wire [2 : 0] m_m_succFile$ADDR_1,
|
|
m_m_succFile$ADDR_2,
|
|
m_m_succFile$ADDR_3,
|
|
m_m_succFile$ADDR_4,
|
|
m_m_succFile$ADDR_5,
|
|
m_m_succFile$ADDR_IN,
|
|
m_m_succFile$D_IN,
|
|
m_m_succFile$D_OUT_1;
|
|
wire m_m_succFile$WE;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_m_dataValidVec_0_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_1_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_2_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_3_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_4_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_5_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_6_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_7_canon,
|
|
CAN_FIRE_RL_m_m_initEmptyEntry,
|
|
CAN_FIRE_RL_m_m_reqVec_0_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_1_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_2_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_3_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_4_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_5_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_6_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_7_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_0_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_1_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_2_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_3_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_4_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_5_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_6_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_7_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_0_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_1_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_2_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_3_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_4_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_5_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_6_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_7_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_0_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_1_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_2_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_3_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_4_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_5_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_6_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_7_canon,
|
|
CAN_FIRE_cRqTransfer_getEmptyEntryInit,
|
|
CAN_FIRE_pipelineResp_releaseEntry,
|
|
CAN_FIRE_pipelineResp_setData,
|
|
CAN_FIRE_pipelineResp_setStateSlot,
|
|
CAN_FIRE_pipelineResp_setSucc,
|
|
CAN_FIRE_sendRsToP_cRq_setWaitSt_setSlot_clearData,
|
|
CAN_FIRE_stuck_get,
|
|
WILL_FIRE_RL_m_m_dataValidVec_0_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_1_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_2_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_3_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_4_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_5_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_6_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_7_canon,
|
|
WILL_FIRE_RL_m_m_initEmptyEntry,
|
|
WILL_FIRE_RL_m_m_reqVec_0_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_1_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_2_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_3_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_4_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_5_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_6_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_7_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_0_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_1_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_2_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_3_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_4_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_5_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_6_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_7_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_0_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_1_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_2_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_3_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_4_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_5_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_6_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_7_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_0_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_1_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_2_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_3_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_4_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_5_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_6_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_7_canon,
|
|
WILL_FIRE_cRqTransfer_getEmptyEntryInit,
|
|
WILL_FIRE_pipelineResp_releaseEntry,
|
|
WILL_FIRE_pipelineResp_setData,
|
|
WILL_FIRE_pipelineResp_setStateSlot,
|
|
WILL_FIRE_pipelineResp_setSucc,
|
|
WILL_FIRE_sendRsToP_cRq_setWaitSt_setSlot_clearData,
|
|
WILL_FIRE_stuck_get;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire MUX_m_m_stateVec_0_lat_1$wset_1__SEL_1,
|
|
MUX_m_m_stateVec_0_lat_1$wset_1__SEL_2,
|
|
MUX_m_m_stateVec_1_lat_1$wset_1__SEL_1,
|
|
MUX_m_m_stateVec_1_lat_1$wset_1__SEL_2,
|
|
MUX_m_m_stateVec_2_lat_1$wset_1__SEL_1,
|
|
MUX_m_m_stateVec_2_lat_1$wset_1__SEL_2,
|
|
MUX_m_m_stateVec_3_lat_1$wset_1__SEL_1,
|
|
MUX_m_m_stateVec_3_lat_1$wset_1__SEL_2,
|
|
MUX_m_m_stateVec_4_lat_1$wset_1__SEL_1,
|
|
MUX_m_m_stateVec_4_lat_1$wset_1__SEL_2,
|
|
MUX_m_m_stateVec_5_lat_1$wset_1__SEL_1,
|
|
MUX_m_m_stateVec_5_lat_1$wset_1__SEL_2,
|
|
MUX_m_m_stateVec_6_lat_1$wset_1__SEL_1,
|
|
MUX_m_m_stateVec_6_lat_1$wset_1__SEL_2,
|
|
MUX_m_m_stateVec_7_lat_1$wset_1__SEL_1,
|
|
MUX_m_m_stateVec_7_lat_1$wset_1__SEL_2;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715;
|
|
reg [51 : 0] x__h101896, x__h105130, x__h97371;
|
|
reg [4 : 0] x__h100316, x__h102456, x__h75626, x__h95633;
|
|
reg [3 : 0] SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717;
|
|
reg [2 : 0] SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689,
|
|
x__h101857,
|
|
x__h104747,
|
|
x__h97252;
|
|
reg [1 : 0] SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533,
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726;
|
|
reg SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999,
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876,
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899,
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728;
|
|
wire [63 : 0] m_m_reqVec_0_rl_BITS_221_TO_158__q1,
|
|
m_m_reqVec_1_rl_BITS_221_TO_158__q2,
|
|
m_m_reqVec_2_rl_BITS_221_TO_158__q3,
|
|
m_m_reqVec_3_rl_BITS_221_TO_158__q5,
|
|
m_m_reqVec_4_rl_BITS_221_TO_158__q4,
|
|
m_m_reqVec_5_rl_BITS_221_TO_158__q6,
|
|
m_m_reqVec_6_rl_BITS_221_TO_158__q7,
|
|
m_m_reqVec_7_rl_BITS_221_TO_158__q8;
|
|
wire [57 : 0] IF_m_m_slotVec_0_lat_1_whas__63_THEN_m_m_slotV_ETC___d169,
|
|
IF_m_m_slotVec_1_lat_1_whas__73_THEN_m_m_slotV_ETC___d179,
|
|
IF_m_m_slotVec_2_lat_1_whas__83_THEN_m_m_slotV_ETC___d189,
|
|
IF_m_m_slotVec_3_lat_1_whas__93_THEN_m_m_slotV_ETC___d199,
|
|
IF_m_m_slotVec_4_lat_1_whas__03_THEN_m_m_slotV_ETC___d209,
|
|
IF_m_m_slotVec_5_lat_1_whas__13_THEN_m_m_slotV_ETC___d219,
|
|
IF_m_m_slotVec_6_lat_1_whas__23_THEN_m_m_slotV_ETC___d229,
|
|
IF_m_m_slotVec_7_lat_1_whas__33_THEN_m_m_slotV_ETC___d239;
|
|
wire [2 : 0] IF_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_state_ETC___d2093,
|
|
IF_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_state_ETC___d2094,
|
|
IF_IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_st_ETC___d2090,
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8,
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18,
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28,
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38,
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48,
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58,
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68,
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78;
|
|
wire IF_m_m_dataValidVec_0_lat_1_whas__43_THEN_m_m__ETC___d249,
|
|
IF_m_m_dataValidVec_1_lat_1_whas__53_THEN_m_m__ETC___d259,
|
|
IF_m_m_dataValidVec_2_lat_1_whas__63_THEN_m_m__ETC___d269,
|
|
IF_m_m_dataValidVec_3_lat_1_whas__73_THEN_m_m__ETC___d279,
|
|
IF_m_m_dataValidVec_4_lat_1_whas__83_THEN_m_m__ETC___d289,
|
|
IF_m_m_dataValidVec_5_lat_1_whas__93_THEN_m_m__ETC___d299,
|
|
IF_m_m_dataValidVec_6_lat_1_whas__03_THEN_m_m__ETC___d309,
|
|
IF_m_m_dataValidVec_7_lat_1_whas__13_THEN_m_m__ETC___d319,
|
|
IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_reqVec__ETC___d1923,
|
|
IF_m_m_reqVec_1_lat_0_whas__5_THEN_m_m_reqVec__ETC___d1938,
|
|
IF_m_m_reqVec_2_lat_0_whas__05_THEN_m_m_reqVec_ETC___d1954,
|
|
IF_m_m_reqVec_3_lat_0_whas__15_THEN_m_m_reqVec_ETC___d1969,
|
|
IF_m_m_reqVec_4_lat_0_whas__25_THEN_m_m_reqVec_ETC___d1986,
|
|
IF_m_m_reqVec_5_lat_0_whas__35_THEN_m_m_reqVec_ETC___d2001,
|
|
IF_m_m_reqVec_6_lat_0_whas__45_THEN_m_m_reqVec_ETC___d2017,
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d2045,
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d2050,
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d2056,
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d2068,
|
|
NOT_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stat_ETC___d2040,
|
|
m_m_stateVec_1_rl_7_EQ_0_097_AND_m_m_stateVec__ETC___d2109;
|
|
|
|
// value method cRqTransfer_getRq
|
|
assign cRqTransfer_getRq =
|
|
{ x__h75626,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 } ;
|
|
assign RDY_cRqTransfer_getRq = 1'd1 ;
|
|
|
|
// actionvalue method cRqTransfer_getEmptyEntryInit
|
|
assign cRqTransfer_getEmptyEntryInit = m_m_emptyEntryQ$D_OUT ;
|
|
assign RDY_cRqTransfer_getEmptyEntryInit =
|
|
m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign CAN_FIRE_cRqTransfer_getEmptyEntryInit =
|
|
m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign WILL_FIRE_cRqTransfer_getEmptyEntryInit =
|
|
EN_cRqTransfer_getEmptyEntryInit ;
|
|
|
|
// value method sendRsToP_cRq_getState
|
|
always@(sendRsToP_cRq_getState_n or
|
|
m_m_stateVec_0_rl or
|
|
m_m_stateVec_1_rl or
|
|
m_m_stateVec_2_rl or
|
|
m_m_stateVec_3_rl or
|
|
m_m_stateVec_4_rl or
|
|
m_m_stateVec_5_rl or m_m_stateVec_6_rl or m_m_stateVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getState_n)
|
|
3'd0: sendRsToP_cRq_getState = m_m_stateVec_0_rl;
|
|
3'd1: sendRsToP_cRq_getState = m_m_stateVec_1_rl;
|
|
3'd2: sendRsToP_cRq_getState = m_m_stateVec_2_rl;
|
|
3'd3: sendRsToP_cRq_getState = m_m_stateVec_3_rl;
|
|
3'd4: sendRsToP_cRq_getState = m_m_stateVec_4_rl;
|
|
3'd5: sendRsToP_cRq_getState = m_m_stateVec_5_rl;
|
|
3'd6: sendRsToP_cRq_getState = m_m_stateVec_6_rl;
|
|
3'd7: sendRsToP_cRq_getState = m_m_stateVec_7_rl;
|
|
endcase
|
|
end
|
|
assign RDY_sendRsToP_cRq_getState = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getRq
|
|
assign sendRsToP_cRq_getRq =
|
|
{ x__h95633,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 } ;
|
|
assign RDY_sendRsToP_cRq_getRq = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getSlot
|
|
assign sendRsToP_cRq_getSlot =
|
|
{ x__h97252,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652,
|
|
x__h97371,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 } ;
|
|
assign RDY_sendRsToP_cRq_getSlot = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getData
|
|
assign sendRsToP_cRq_getData =
|
|
{ SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675,
|
|
m_m_dataFile$D_OUT_1 } ;
|
|
assign RDY_sendRsToP_cRq_getData = 1'd1 ;
|
|
|
|
// action method sendRsToP_cRq_setWaitSt_setSlot_clearData
|
|
assign RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData = 1'd1 ;
|
|
assign CAN_FIRE_sendRsToP_cRq_setWaitSt_setSlot_clearData = 1'd1 ;
|
|
assign WILL_FIRE_sendRsToP_cRq_setWaitSt_setSlot_clearData =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData ;
|
|
|
|
// value method sendRqToP_getRq
|
|
assign sendRqToP_getRq =
|
|
{ x__h100316,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719,
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 } ;
|
|
assign RDY_sendRqToP_getRq = 1'd1 ;
|
|
|
|
// value method sendRqToP_getSlot
|
|
assign sendRqToP_getSlot =
|
|
{ x__h101857,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726,
|
|
x__h101896,
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 } ;
|
|
assign RDY_sendRqToP_getSlot = 1'd1 ;
|
|
|
|
// action method pipelineResp_releaseEntry
|
|
assign RDY_pipelineResp_releaseEntry =
|
|
m_m_inited && m_m_emptyEntryQ$FULL_N ;
|
|
assign CAN_FIRE_pipelineResp_releaseEntry =
|
|
m_m_inited && m_m_emptyEntryQ$FULL_N ;
|
|
assign WILL_FIRE_pipelineResp_releaseEntry = EN_pipelineResp_releaseEntry ;
|
|
|
|
// value method pipelineResp_getState
|
|
always@(pipelineResp_getState_n or
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 or
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 or
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 or
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 or
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 or
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 or
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 or
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78)
|
|
begin
|
|
case (pipelineResp_getState_n)
|
|
3'd0:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8;
|
|
3'd1:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18;
|
|
3'd2:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28;
|
|
3'd3:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38;
|
|
3'd4:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48;
|
|
3'd5:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58;
|
|
3'd6:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68;
|
|
3'd7:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78;
|
|
endcase
|
|
end
|
|
assign RDY_pipelineResp_getState = 1'd1 ;
|
|
|
|
// value method pipelineResp_getRq
|
|
assign pipelineResp_getRq =
|
|
{ x__h102456,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798,
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 } ;
|
|
assign RDY_pipelineResp_getRq = 1'd1 ;
|
|
|
|
// value method pipelineResp_getSlot
|
|
assign pipelineResp_getSlot =
|
|
{ x__h104747,
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840,
|
|
x__h105130,
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 } ;
|
|
assign RDY_pipelineResp_getSlot = 1'd1 ;
|
|
|
|
// action method pipelineResp_setData
|
|
assign RDY_pipelineResp_setData = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setData = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setData = EN_pipelineResp_setData ;
|
|
|
|
// action method pipelineResp_setStateSlot
|
|
assign RDY_pipelineResp_setStateSlot = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setStateSlot = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setStateSlot = EN_pipelineResp_setStateSlot ;
|
|
|
|
// value method pipelineResp_getSucc
|
|
assign pipelineResp_getSucc =
|
|
{ SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899,
|
|
m_m_succFile$D_OUT_1 } ;
|
|
assign RDY_pipelineResp_getSucc = 1'd1 ;
|
|
|
|
// action method pipelineResp_setSucc
|
|
assign RDY_pipelineResp_setSucc = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setSucc = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setSucc = EN_pipelineResp_setSucc ;
|
|
|
|
// value method pipelineResp_searchEndOfChain
|
|
assign pipelineResp_searchEndOfChain =
|
|
{ NOT_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stat_ETC___d2040,
|
|
IF_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_state_ETC___d2094 } ;
|
|
assign RDY_pipelineResp_searchEndOfChain = 1'd1 ;
|
|
|
|
// value method emptyForFlush
|
|
assign emptyForFlush =
|
|
m_m_stateVec_0_rl == 3'd0 &&
|
|
m_m_stateVec_1_rl_7_EQ_0_097_AND_m_m_stateVec__ETC___d2109 ;
|
|
assign RDY_emptyForFlush = 1'd1 ;
|
|
|
|
// actionvalue method stuck_get
|
|
assign stuck_get =
|
|
233'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
assign RDY_stuck_get = 1'd0 ;
|
|
assign CAN_FIRE_stuck_get = 1'd0 ;
|
|
assign WILL_FIRE_stuck_get = EN_stuck_get ;
|
|
|
|
// submodule m_m_dataFile
|
|
RegFile #(.addr_width(32'd3),
|
|
.data_width(32'd516),
|
|
.lo(3'd0),
|
|
.hi(3'd7)) m_m_dataFile(.CLK(CLK),
|
|
.ADDR_1(m_m_dataFile$ADDR_1),
|
|
.ADDR_2(m_m_dataFile$ADDR_2),
|
|
.ADDR_3(m_m_dataFile$ADDR_3),
|
|
.ADDR_4(m_m_dataFile$ADDR_4),
|
|
.ADDR_5(m_m_dataFile$ADDR_5),
|
|
.ADDR_IN(m_m_dataFile$ADDR_IN),
|
|
.D_IN(m_m_dataFile$D_IN),
|
|
.WE(m_m_dataFile$WE),
|
|
.D_OUT_1(m_m_dataFile$D_OUT_1),
|
|
.D_OUT_2(),
|
|
.D_OUT_3(),
|
|
.D_OUT_4(),
|
|
.D_OUT_5());
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
SizedFIFO #(.p1width(32'd3),
|
|
.p2depth(32'd8),
|
|
.p3cntr_width(32'd3),
|
|
.guarded(32'd1)) m_m_emptyEntryQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_m_emptyEntryQ$D_IN),
|
|
.ENQ(m_m_emptyEntryQ$ENQ),
|
|
.DEQ(m_m_emptyEntryQ$DEQ),
|
|
.CLR(m_m_emptyEntryQ$CLR),
|
|
.D_OUT(m_m_emptyEntryQ$D_OUT),
|
|
.FULL_N(m_m_emptyEntryQ$FULL_N),
|
|
.EMPTY_N(m_m_emptyEntryQ$EMPTY_N));
|
|
|
|
// submodule m_m_succFile
|
|
RegFile #(.addr_width(32'd3),
|
|
.data_width(32'd3),
|
|
.lo(3'd0),
|
|
.hi(3'd7)) m_m_succFile(.CLK(CLK),
|
|
.ADDR_1(m_m_succFile$ADDR_1),
|
|
.ADDR_2(m_m_succFile$ADDR_2),
|
|
.ADDR_3(m_m_succFile$ADDR_3),
|
|
.ADDR_4(m_m_succFile$ADDR_4),
|
|
.ADDR_5(m_m_succFile$ADDR_5),
|
|
.ADDR_IN(m_m_succFile$ADDR_IN),
|
|
.D_IN(m_m_succFile$D_IN),
|
|
.WE(m_m_succFile$WE),
|
|
.D_OUT_1(m_m_succFile$D_OUT_1),
|
|
.D_OUT_2(),
|
|
.D_OUT_3(),
|
|
.D_OUT_4(),
|
|
.D_OUT_5());
|
|
|
|
// rule RL_m_m_initEmptyEntry
|
|
assign CAN_FIRE_RL_m_m_initEmptyEntry =
|
|
m_m_emptyEntryQ$FULL_N && !m_m_inited ;
|
|
assign WILL_FIRE_RL_m_m_initEmptyEntry = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// rule RL_m_m_stateVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_m_stateVec_0_lat_1$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd0 ;
|
|
assign MUX_m_m_stateVec_0_lat_1$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd0 ;
|
|
assign MUX_m_m_stateVec_1_lat_1$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd1 ;
|
|
assign MUX_m_m_stateVec_1_lat_1$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd1 ;
|
|
assign MUX_m_m_stateVec_2_lat_1$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd2 ;
|
|
assign MUX_m_m_stateVec_2_lat_1$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd2 ;
|
|
assign MUX_m_m_stateVec_3_lat_1$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd3 ;
|
|
assign MUX_m_m_stateVec_3_lat_1$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd3 ;
|
|
assign MUX_m_m_stateVec_4_lat_1$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd4 ;
|
|
assign MUX_m_m_stateVec_4_lat_1$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd4 ;
|
|
assign MUX_m_m_stateVec_5_lat_1$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd5 ;
|
|
assign MUX_m_m_stateVec_5_lat_1$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd5 ;
|
|
assign MUX_m_m_stateVec_6_lat_1$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd6 ;
|
|
assign MUX_m_m_stateVec_6_lat_1$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd6 ;
|
|
assign MUX_m_m_stateVec_7_lat_1$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd7 ;
|
|
assign MUX_m_m_stateVec_7_lat_1$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd7 ;
|
|
|
|
// inlined wires
|
|
assign m_m_stateVec_0_lat_0$whas =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd0 ;
|
|
assign m_m_stateVec_0_lat_1$wget =
|
|
MUX_m_m_stateVec_0_lat_1$wset_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_0_lat_1$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd0 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd0 ;
|
|
assign m_m_stateVec_0_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd0 ;
|
|
assign m_m_stateVec_1_lat_0$whas =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd1 ;
|
|
assign m_m_stateVec_1_lat_1$wget =
|
|
MUX_m_m_stateVec_1_lat_1$wset_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_1_lat_1$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd1 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd1 ;
|
|
assign m_m_stateVec_1_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd1 ;
|
|
assign m_m_stateVec_2_lat_0$whas =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd2 ;
|
|
assign m_m_stateVec_2_lat_1$wget =
|
|
MUX_m_m_stateVec_2_lat_1$wset_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_2_lat_1$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd2 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd2 ;
|
|
assign m_m_stateVec_2_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd2 ;
|
|
assign m_m_stateVec_3_lat_0$whas =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd3 ;
|
|
assign m_m_stateVec_3_lat_1$wget =
|
|
MUX_m_m_stateVec_3_lat_1$wset_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_3_lat_1$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd3 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd3 ;
|
|
assign m_m_stateVec_3_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd3 ;
|
|
assign m_m_stateVec_4_lat_0$whas =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd4 ;
|
|
assign m_m_stateVec_4_lat_1$wget =
|
|
MUX_m_m_stateVec_4_lat_1$wset_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_4_lat_1$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd4 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd4 ;
|
|
assign m_m_stateVec_4_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd4 ;
|
|
assign m_m_stateVec_5_lat_0$whas =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd5 ;
|
|
assign m_m_stateVec_5_lat_1$wget =
|
|
MUX_m_m_stateVec_5_lat_1$wset_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_5_lat_1$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd5 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd5 ;
|
|
assign m_m_stateVec_5_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd5 ;
|
|
assign m_m_stateVec_6_lat_0$whas =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd6 ;
|
|
assign m_m_stateVec_6_lat_1$wget =
|
|
MUX_m_m_stateVec_6_lat_1$wset_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_6_lat_1$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd6 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd6 ;
|
|
assign m_m_stateVec_6_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd6 ;
|
|
assign m_m_stateVec_7_lat_0$whas =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd7 ;
|
|
assign m_m_stateVec_7_lat_1$wget =
|
|
MUX_m_m_stateVec_7_lat_1$wset_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_7_lat_1$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd7 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd7 ;
|
|
assign m_m_stateVec_7_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd7 ;
|
|
assign m_m_slotVec_0_lat_2$wget =
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 } ;
|
|
assign m_m_dataValidVec_0_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd0 ;
|
|
assign m_m_dataValidVec_1_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd1 ;
|
|
assign m_m_dataValidVec_2_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd2 ;
|
|
assign m_m_dataValidVec_3_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd3 ;
|
|
assign m_m_dataValidVec_4_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd4 ;
|
|
assign m_m_dataValidVec_5_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd5 ;
|
|
assign m_m_dataValidVec_6_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd6 ;
|
|
assign m_m_dataValidVec_7_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd7 ;
|
|
assign m_m_succValidVec_0_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd0 ;
|
|
assign m_m_succValidVec_1_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd1 ;
|
|
assign m_m_succValidVec_2_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd2 ;
|
|
assign m_m_succValidVec_3_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd3 ;
|
|
assign m_m_succValidVec_4_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd4 ;
|
|
assign m_m_succValidVec_5_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd5 ;
|
|
assign m_m_succValidVec_6_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd6 ;
|
|
assign m_m_succValidVec_7_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd7 ;
|
|
|
|
// register m_m_dataValidVec_0_rl
|
|
assign m_m_dataValidVec_0_rl$D_IN =
|
|
!m_m_stateVec_0_lat_2$whas &&
|
|
IF_m_m_dataValidVec_0_lat_1_whas__43_THEN_m_m__ETC___d249 ;
|
|
assign m_m_dataValidVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_1_rl
|
|
assign m_m_dataValidVec_1_rl$D_IN =
|
|
!m_m_stateVec_1_lat_2$whas &&
|
|
IF_m_m_dataValidVec_1_lat_1_whas__53_THEN_m_m__ETC___d259 ;
|
|
assign m_m_dataValidVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_2_rl
|
|
assign m_m_dataValidVec_2_rl$D_IN =
|
|
!m_m_stateVec_2_lat_2$whas &&
|
|
IF_m_m_dataValidVec_2_lat_1_whas__63_THEN_m_m__ETC___d269 ;
|
|
assign m_m_dataValidVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_3_rl
|
|
assign m_m_dataValidVec_3_rl$D_IN =
|
|
!m_m_stateVec_3_lat_2$whas &&
|
|
IF_m_m_dataValidVec_3_lat_1_whas__73_THEN_m_m__ETC___d279 ;
|
|
assign m_m_dataValidVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_4_rl
|
|
assign m_m_dataValidVec_4_rl$D_IN =
|
|
!m_m_stateVec_4_lat_2$whas &&
|
|
IF_m_m_dataValidVec_4_lat_1_whas__83_THEN_m_m__ETC___d289 ;
|
|
assign m_m_dataValidVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_5_rl
|
|
assign m_m_dataValidVec_5_rl$D_IN =
|
|
!m_m_stateVec_5_lat_2$whas &&
|
|
IF_m_m_dataValidVec_5_lat_1_whas__93_THEN_m_m__ETC___d299 ;
|
|
assign m_m_dataValidVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_6_rl
|
|
assign m_m_dataValidVec_6_rl$D_IN =
|
|
!m_m_stateVec_6_lat_2$whas &&
|
|
IF_m_m_dataValidVec_6_lat_1_whas__03_THEN_m_m__ETC___d309 ;
|
|
assign m_m_dataValidVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_7_rl
|
|
assign m_m_dataValidVec_7_rl$D_IN =
|
|
!m_m_stateVec_7_lat_2$whas &&
|
|
IF_m_m_dataValidVec_7_lat_1_whas__13_THEN_m_m__ETC___d319 ;
|
|
assign m_m_dataValidVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_initIdx
|
|
assign m_m_initIdx$D_IN = m_m_initIdx + 3'd1 ;
|
|
assign m_m_initIdx$EN = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// register m_m_inited
|
|
assign m_m_inited$D_IN = 1'd1 ;
|
|
assign m_m_inited$EN =
|
|
WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 3'd7 ;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
assign m_m_reqVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_0_rl ;
|
|
assign m_m_reqVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
assign m_m_reqVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_1_rl ;
|
|
assign m_m_reqVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
assign m_m_reqVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_2_rl ;
|
|
assign m_m_reqVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
assign m_m_reqVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_3_rl ;
|
|
assign m_m_reqVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_4_rl
|
|
assign m_m_reqVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_4_rl ;
|
|
assign m_m_reqVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_5_rl
|
|
assign m_m_reqVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_5_rl ;
|
|
assign m_m_reqVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_6_rl
|
|
assign m_m_reqVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_6_rl ;
|
|
assign m_m_reqVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_7_rl
|
|
assign m_m_reqVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_7_rl ;
|
|
assign m_m_reqVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_0_rl
|
|
assign m_m_slotVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
IF_m_m_slotVec_0_lat_1_whas__63_THEN_m_m_slotV_ETC___d169 ;
|
|
assign m_m_slotVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_1_rl
|
|
assign m_m_slotVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
IF_m_m_slotVec_1_lat_1_whas__73_THEN_m_m_slotV_ETC___d179 ;
|
|
assign m_m_slotVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_2_rl
|
|
assign m_m_slotVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
IF_m_m_slotVec_2_lat_1_whas__83_THEN_m_m_slotV_ETC___d189 ;
|
|
assign m_m_slotVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_3_rl
|
|
assign m_m_slotVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
IF_m_m_slotVec_3_lat_1_whas__93_THEN_m_m_slotV_ETC___d199 ;
|
|
assign m_m_slotVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_4_rl
|
|
assign m_m_slotVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
IF_m_m_slotVec_4_lat_1_whas__03_THEN_m_m_slotV_ETC___d209 ;
|
|
assign m_m_slotVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_5_rl
|
|
assign m_m_slotVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
IF_m_m_slotVec_5_lat_1_whas__13_THEN_m_m_slotV_ETC___d219 ;
|
|
assign m_m_slotVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_6_rl
|
|
assign m_m_slotVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
IF_m_m_slotVec_6_lat_1_whas__23_THEN_m_m_slotV_ETC___d229 ;
|
|
assign m_m_slotVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_7_rl
|
|
assign m_m_slotVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
m_m_slotVec_0_lat_2$wget :
|
|
IF_m_m_slotVec_7_lat_1_whas__33_THEN_m_m_slotV_ETC___d239 ;
|
|
assign m_m_slotVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
assign m_m_stateVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_0_lat_1$whas ?
|
|
m_m_stateVec_0_lat_1$wget :
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8) ;
|
|
assign m_m_stateVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
assign m_m_stateVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_1_lat_1$whas ?
|
|
m_m_stateVec_1_lat_1$wget :
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18) ;
|
|
assign m_m_stateVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
assign m_m_stateVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_2_lat_1$whas ?
|
|
m_m_stateVec_2_lat_1$wget :
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28) ;
|
|
assign m_m_stateVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
assign m_m_stateVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_3_lat_1$whas ?
|
|
m_m_stateVec_3_lat_1$wget :
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38) ;
|
|
assign m_m_stateVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_4_rl
|
|
assign m_m_stateVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_4_lat_1$whas ?
|
|
m_m_stateVec_4_lat_1$wget :
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48) ;
|
|
assign m_m_stateVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_5_rl
|
|
assign m_m_stateVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_5_lat_1$whas ?
|
|
m_m_stateVec_5_lat_1$wget :
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58) ;
|
|
assign m_m_stateVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_6_rl
|
|
assign m_m_stateVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_6_lat_1$whas ?
|
|
m_m_stateVec_6_lat_1$wget :
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68) ;
|
|
assign m_m_stateVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_7_rl
|
|
assign m_m_stateVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_7_lat_1$whas ?
|
|
m_m_stateVec_7_lat_1$wget :
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78) ;
|
|
assign m_m_stateVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_0_rl
|
|
assign m_m_succValidVec_0_rl$D_IN =
|
|
!m_m_stateVec_0_lat_2$whas &&
|
|
(m_m_succValidVec_0_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_0_rl) ;
|
|
assign m_m_succValidVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_1_rl
|
|
assign m_m_succValidVec_1_rl$D_IN =
|
|
!m_m_stateVec_1_lat_2$whas &&
|
|
(m_m_succValidVec_1_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_1_rl) ;
|
|
assign m_m_succValidVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_2_rl
|
|
assign m_m_succValidVec_2_rl$D_IN =
|
|
!m_m_stateVec_2_lat_2$whas &&
|
|
(m_m_succValidVec_2_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_2_rl) ;
|
|
assign m_m_succValidVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_3_rl
|
|
assign m_m_succValidVec_3_rl$D_IN =
|
|
!m_m_stateVec_3_lat_2$whas &&
|
|
(m_m_succValidVec_3_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_3_rl) ;
|
|
assign m_m_succValidVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_4_rl
|
|
assign m_m_succValidVec_4_rl$D_IN =
|
|
!m_m_stateVec_4_lat_2$whas &&
|
|
(m_m_succValidVec_4_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_4_rl) ;
|
|
assign m_m_succValidVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_5_rl
|
|
assign m_m_succValidVec_5_rl$D_IN =
|
|
!m_m_stateVec_5_lat_2$whas &&
|
|
(m_m_succValidVec_5_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_5_rl) ;
|
|
assign m_m_succValidVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_6_rl
|
|
assign m_m_succValidVec_6_rl$D_IN =
|
|
!m_m_stateVec_6_lat_2$whas &&
|
|
(m_m_succValidVec_6_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_6_rl) ;
|
|
assign m_m_succValidVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_7_rl
|
|
assign m_m_succValidVec_7_rl$D_IN =
|
|
!m_m_stateVec_7_lat_2$whas &&
|
|
(m_m_succValidVec_7_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_7_rl) ;
|
|
assign m_m_succValidVec_7_rl$EN = 1'd1 ;
|
|
|
|
// submodule m_m_dataFile
|
|
assign m_m_dataFile$ADDR_1 = sendRsToP_cRq_getData_n ;
|
|
assign m_m_dataFile$ADDR_2 = 3'h0 ;
|
|
assign m_m_dataFile$ADDR_3 = 3'h0 ;
|
|
assign m_m_dataFile$ADDR_4 = 3'h0 ;
|
|
assign m_m_dataFile$ADDR_5 = 3'h0 ;
|
|
assign m_m_dataFile$ADDR_IN = pipelineResp_setData_n ;
|
|
assign m_m_dataFile$D_IN = pipelineResp_setData_d[515:0] ;
|
|
assign m_m_dataFile$WE = EN_pipelineResp_setData ;
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
assign m_m_emptyEntryQ$D_IN =
|
|
EN_pipelineResp_releaseEntry ?
|
|
pipelineResp_releaseEntry_n :
|
|
m_m_initIdx ;
|
|
assign m_m_emptyEntryQ$ENQ =
|
|
EN_pipelineResp_releaseEntry || WILL_FIRE_RL_m_m_initEmptyEntry ;
|
|
assign m_m_emptyEntryQ$DEQ = EN_cRqTransfer_getEmptyEntryInit ;
|
|
assign m_m_emptyEntryQ$CLR = 1'b0 ;
|
|
|
|
// submodule m_m_succFile
|
|
assign m_m_succFile$ADDR_1 = pipelineResp_getSucc_n ;
|
|
assign m_m_succFile$ADDR_2 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_3 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_4 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_5 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_IN = pipelineResp_setSucc_n ;
|
|
assign m_m_succFile$D_IN = pipelineResp_setSucc_succ[2:0] ;
|
|
assign m_m_succFile$WE = EN_pipelineResp_setSucc ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_state_ETC___d2093 =
|
|
(IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d2045 &&
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d2050) ?
|
|
(IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d2056 ?
|
|
3'd3 :
|
|
3'd2) :
|
|
(IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d2045 ?
|
|
3'd1 :
|
|
3'd0) ;
|
|
assign IF_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_state_ETC___d2094 =
|
|
(IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d2045 &&
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d2050 &&
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d2056 &&
|
|
(IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_3_lat_0_whas__15_THEN_m_m_reqVec_ETC___d1969 ||
|
|
m_m_succValidVec_3_rl)) ?
|
|
IF_IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_st_ETC___d2090 :
|
|
IF_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_state_ETC___d2093 ;
|
|
assign IF_IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_st_ETC___d2090 =
|
|
(IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d2068 &&
|
|
(IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_5_lat_0_whas__35_THEN_m_m_reqVec_ETC___d2001 ||
|
|
m_m_succValidVec_5_rl)) ?
|
|
((IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_6_lat_0_whas__45_THEN_m_m_reqVec_ETC___d2017 ||
|
|
m_m_succValidVec_6_rl) ?
|
|
3'd7 :
|
|
3'd6) :
|
|
(IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d2068 ?
|
|
3'd5 :
|
|
3'd4) ;
|
|
assign IF_m_m_dataValidVec_0_lat_1_whas__43_THEN_m_m__ETC___d249 =
|
|
m_m_dataValidVec_0_lat_1$whas ?
|
|
pipelineResp_setData_d[516] :
|
|
!m_m_stateVec_0_lat_0$whas && m_m_dataValidVec_0_rl ;
|
|
assign IF_m_m_dataValidVec_1_lat_1_whas__53_THEN_m_m__ETC___d259 =
|
|
m_m_dataValidVec_1_lat_1$whas ?
|
|
pipelineResp_setData_d[516] :
|
|
!m_m_stateVec_1_lat_0$whas && m_m_dataValidVec_1_rl ;
|
|
assign IF_m_m_dataValidVec_2_lat_1_whas__63_THEN_m_m__ETC___d269 =
|
|
m_m_dataValidVec_2_lat_1$whas ?
|
|
pipelineResp_setData_d[516] :
|
|
!m_m_stateVec_2_lat_0$whas && m_m_dataValidVec_2_rl ;
|
|
assign IF_m_m_dataValidVec_3_lat_1_whas__73_THEN_m_m__ETC___d279 =
|
|
m_m_dataValidVec_3_lat_1$whas ?
|
|
pipelineResp_setData_d[516] :
|
|
!m_m_stateVec_3_lat_0$whas && m_m_dataValidVec_3_rl ;
|
|
assign IF_m_m_dataValidVec_4_lat_1_whas__83_THEN_m_m__ETC___d289 =
|
|
m_m_dataValidVec_4_lat_1$whas ?
|
|
pipelineResp_setData_d[516] :
|
|
!m_m_stateVec_4_lat_0$whas && m_m_dataValidVec_4_rl ;
|
|
assign IF_m_m_dataValidVec_5_lat_1_whas__93_THEN_m_m__ETC___d299 =
|
|
m_m_dataValidVec_5_lat_1$whas ?
|
|
pipelineResp_setData_d[516] :
|
|
!m_m_stateVec_5_lat_0$whas && m_m_dataValidVec_5_rl ;
|
|
assign IF_m_m_dataValidVec_6_lat_1_whas__03_THEN_m_m__ETC___d309 =
|
|
m_m_dataValidVec_6_lat_1$whas ?
|
|
pipelineResp_setData_d[516] :
|
|
!m_m_stateVec_6_lat_0$whas && m_m_dataValidVec_6_rl ;
|
|
assign IF_m_m_dataValidVec_7_lat_1_whas__13_THEN_m_m__ETC___d319 =
|
|
m_m_dataValidVec_7_lat_1$whas ?
|
|
pipelineResp_setData_d[516] :
|
|
!m_m_stateVec_7_lat_0$whas && m_m_dataValidVec_7_rl ;
|
|
assign IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_reqVec__ETC___d1923 =
|
|
m_m_reqVec_0_rl_BITS_221_TO_158__q1[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_1_lat_0_whas__5_THEN_m_m_reqVec__ETC___d1938 =
|
|
m_m_reqVec_1_rl_BITS_221_TO_158__q2[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_2_lat_0_whas__05_THEN_m_m_reqVec_ETC___d1954 =
|
|
m_m_reqVec_2_rl_BITS_221_TO_158__q3[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_3_lat_0_whas__15_THEN_m_m_reqVec_ETC___d1969 =
|
|
m_m_reqVec_3_rl_BITS_221_TO_158__q5[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_4_lat_0_whas__25_THEN_m_m_reqVec_ETC___d1986 =
|
|
m_m_reqVec_4_rl_BITS_221_TO_158__q4[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_5_lat_0_whas__35_THEN_m_m_reqVec_ETC___d2001 =
|
|
m_m_reqVec_5_rl_BITS_221_TO_158__q6[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_6_lat_0_whas__45_THEN_m_m_reqVec_ETC___d2017 =
|
|
m_m_reqVec_6_rl_BITS_221_TO_158__q7[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_slotVec_0_lat_1_whas__63_THEN_m_m_slotV_ETC___d169 =
|
|
MUX_m_m_stateVec_0_lat_1$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(m_m_stateVec_0_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_0_rl) ;
|
|
assign IF_m_m_slotVec_1_lat_1_whas__73_THEN_m_m_slotV_ETC___d179 =
|
|
MUX_m_m_stateVec_1_lat_1$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(m_m_stateVec_1_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_1_rl) ;
|
|
assign IF_m_m_slotVec_2_lat_1_whas__83_THEN_m_m_slotV_ETC___d189 =
|
|
MUX_m_m_stateVec_2_lat_1$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(m_m_stateVec_2_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_2_rl) ;
|
|
assign IF_m_m_slotVec_3_lat_1_whas__93_THEN_m_m_slotV_ETC___d199 =
|
|
MUX_m_m_stateVec_3_lat_1$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(m_m_stateVec_3_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_3_rl) ;
|
|
assign IF_m_m_slotVec_4_lat_1_whas__03_THEN_m_m_slotV_ETC___d209 =
|
|
MUX_m_m_stateVec_4_lat_1$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(m_m_stateVec_4_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_4_rl) ;
|
|
assign IF_m_m_slotVec_5_lat_1_whas__13_THEN_m_m_slotV_ETC___d219 =
|
|
MUX_m_m_stateVec_5_lat_1$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(m_m_stateVec_5_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_5_rl) ;
|
|
assign IF_m_m_slotVec_6_lat_1_whas__23_THEN_m_m_slotV_ETC___d229 =
|
|
MUX_m_m_stateVec_6_lat_1$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(m_m_stateVec_6_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_6_rl) ;
|
|
assign IF_m_m_slotVec_7_lat_1_whas__33_THEN_m_m_slotV_ETC___d239 =
|
|
MUX_m_m_stateVec_7_lat_1$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(m_m_stateVec_7_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_7_rl) ;
|
|
assign IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d2045 =
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_reqVec__ETC___d1923 ||
|
|
m_m_succValidVec_0_rl ;
|
|
assign IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 =
|
|
m_m_stateVec_0_lat_0$whas ? 3'd3 : m_m_stateVec_0_rl ;
|
|
assign IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 =
|
|
m_m_stateVec_1_lat_0$whas ? 3'd3 : m_m_stateVec_1_rl ;
|
|
assign IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d2050 =
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_1_lat_0_whas__5_THEN_m_m_reqVec__ETC___d1938 ||
|
|
m_m_succValidVec_1_rl ;
|
|
assign IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d2056 =
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_2_lat_0_whas__05_THEN_m_m_reqVec_ETC___d1954 ||
|
|
m_m_succValidVec_2_rl ;
|
|
assign IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 =
|
|
m_m_stateVec_2_lat_0$whas ? 3'd3 : m_m_stateVec_2_rl ;
|
|
assign IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 =
|
|
m_m_stateVec_3_lat_0$whas ? 3'd3 : m_m_stateVec_3_rl ;
|
|
assign IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d2068 =
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_4_lat_0_whas__25_THEN_m_m_reqVec_ETC___d1986 ||
|
|
m_m_succValidVec_4_rl ;
|
|
assign IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 =
|
|
m_m_stateVec_4_lat_0$whas ? 3'd3 : m_m_stateVec_4_rl ;
|
|
assign IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 =
|
|
m_m_stateVec_5_lat_0$whas ? 3'd3 : m_m_stateVec_5_rl ;
|
|
assign IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 =
|
|
m_m_stateVec_6_lat_0$whas ? 3'd3 : m_m_stateVec_6_rl ;
|
|
assign IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78 =
|
|
m_m_stateVec_7_lat_0$whas ? 3'd3 : m_m_stateVec_7_rl ;
|
|
assign NOT_IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stat_ETC___d2040 =
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_reqVec__ETC___d1923 &&
|
|
!m_m_succValidVec_0_rl ||
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_1_lat_0_whas__5_THEN_m_m_reqVec__ETC___d1938 &&
|
|
!m_m_succValidVec_1_rl ||
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_2_lat_0_whas__05_THEN_m_m_reqVec_ETC___d1954 &&
|
|
!m_m_succValidVec_2_rl ||
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_3_lat_0_whas__15_THEN_m_m_reqVec_ETC___d1969 &&
|
|
!m_m_succValidVec_3_rl ||
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_4_lat_0_whas__25_THEN_m_m_reqVec_ETC___d1986 &&
|
|
!m_m_succValidVec_4_rl ||
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_5_lat_0_whas__35_THEN_m_m_reqVec_ETC___d2001 &&
|
|
!m_m_succValidVec_5_rl ||
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_6_lat_0_whas__45_THEN_m_m_reqVec_ETC___d2017 &&
|
|
!m_m_succValidVec_6_rl ||
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78 !=
|
|
3'd1 &&
|
|
m_m_reqVec_7_rl_BITS_221_TO_158__q8[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] &&
|
|
!m_m_succValidVec_7_rl ;
|
|
assign m_m_reqVec_0_rl_BITS_221_TO_158__q1 = m_m_reqVec_0_rl[221:158] ;
|
|
assign m_m_reqVec_1_rl_BITS_221_TO_158__q2 = m_m_reqVec_1_rl[221:158] ;
|
|
assign m_m_reqVec_2_rl_BITS_221_TO_158__q3 = m_m_reqVec_2_rl[221:158] ;
|
|
assign m_m_reqVec_3_rl_BITS_221_TO_158__q5 = m_m_reqVec_3_rl[221:158] ;
|
|
assign m_m_reqVec_4_rl_BITS_221_TO_158__q4 = m_m_reqVec_4_rl[221:158] ;
|
|
assign m_m_reqVec_5_rl_BITS_221_TO_158__q6 = m_m_reqVec_5_rl[221:158] ;
|
|
assign m_m_reqVec_6_rl_BITS_221_TO_158__q7 = m_m_reqVec_6_rl[221:158] ;
|
|
assign m_m_reqVec_7_rl_BITS_221_TO_158__q8 = m_m_reqVec_7_rl[221:158] ;
|
|
assign m_m_stateVec_1_rl_7_EQ_0_097_AND_m_m_stateVec__ETC___d2109 =
|
|
m_m_stateVec_1_rl == 3'd0 && m_m_stateVec_2_rl == 3'd0 &&
|
|
m_m_stateVec_3_rl == 3'd0 &&
|
|
m_m_stateVec_4_rl == 3'd0 &&
|
|
m_m_stateVec_5_rl == 3'd0 &&
|
|
m_m_stateVec_6_rl == 3'd0 &&
|
|
m_m_stateVec_7_rl == 3'd0 ;
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0: x__h97371 = m_m_slotVec_0_rl[52:1];
|
|
3'd1: x__h97371 = m_m_slotVec_1_rl[52:1];
|
|
3'd2: x__h97371 = m_m_slotVec_2_rl[52:1];
|
|
3'd3: x__h97371 = m_m_slotVec_3_rl[52:1];
|
|
3'd4: x__h97371 = m_m_slotVec_4_rl[52:1];
|
|
3'd5: x__h97371 = m_m_slotVec_5_rl[52:1];
|
|
3'd6: x__h97371 = m_m_slotVec_6_rl[52:1];
|
|
3'd7: x__h97371 = m_m_slotVec_7_rl[52:1];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0: x__h101896 = m_m_slotVec_0_rl[52:1];
|
|
3'd1: x__h101896 = m_m_slotVec_1_rl[52:1];
|
|
3'd2: x__h101896 = m_m_slotVec_2_rl[52:1];
|
|
3'd3: x__h101896 = m_m_slotVec_3_rl[52:1];
|
|
3'd4: x__h101896 = m_m_slotVec_4_rl[52:1];
|
|
3'd5: x__h101896 = m_m_slotVec_5_rl[52:1];
|
|
3'd6: x__h101896 = m_m_slotVec_6_rl[52:1];
|
|
3'd7: x__h101896 = m_m_slotVec_7_rl[52:1];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0: x__h75626 = m_m_reqVec_0_rl[226:222];
|
|
3'd1: x__h75626 = m_m_reqVec_1_rl[226:222];
|
|
3'd2: x__h75626 = m_m_reqVec_2_rl[226:222];
|
|
3'd3: x__h75626 = m_m_reqVec_3_rl[226:222];
|
|
3'd4: x__h75626 = m_m_reqVec_4_rl[226:222];
|
|
3'd5: x__h75626 = m_m_reqVec_5_rl[226:222];
|
|
3'd6: x__h75626 = m_m_reqVec_6_rl[226:222];
|
|
3'd7: x__h75626 = m_m_reqVec_7_rl[226:222];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0: x__h95633 = m_m_reqVec_0_rl[226:222];
|
|
3'd1: x__h95633 = m_m_reqVec_1_rl[226:222];
|
|
3'd2: x__h95633 = m_m_reqVec_2_rl[226:222];
|
|
3'd3: x__h95633 = m_m_reqVec_3_rl[226:222];
|
|
3'd4: x__h95633 = m_m_reqVec_4_rl[226:222];
|
|
3'd5: x__h95633 = m_m_reqVec_5_rl[226:222];
|
|
3'd6: x__h95633 = m_m_reqVec_6_rl[226:222];
|
|
3'd7: x__h95633 = m_m_reqVec_7_rl[226:222];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0: x__h97252 = m_m_slotVec_0_rl[57:55];
|
|
3'd1: x__h97252 = m_m_slotVec_1_rl[57:55];
|
|
3'd2: x__h97252 = m_m_slotVec_2_rl[57:55];
|
|
3'd3: x__h97252 = m_m_slotVec_3_rl[57:55];
|
|
3'd4: x__h97252 = m_m_slotVec_4_rl[57:55];
|
|
3'd5: x__h97252 = m_m_slotVec_5_rl[57:55];
|
|
3'd6: x__h97252 = m_m_slotVec_6_rl[57:55];
|
|
3'd7: x__h97252 = m_m_slotVec_7_rl[57:55];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0: x__h100316 = m_m_reqVec_0_rl[226:222];
|
|
3'd1: x__h100316 = m_m_reqVec_1_rl[226:222];
|
|
3'd2: x__h100316 = m_m_reqVec_2_rl[226:222];
|
|
3'd3: x__h100316 = m_m_reqVec_3_rl[226:222];
|
|
3'd4: x__h100316 = m_m_reqVec_4_rl[226:222];
|
|
3'd5: x__h100316 = m_m_reqVec_5_rl[226:222];
|
|
3'd6: x__h100316 = m_m_reqVec_6_rl[226:222];
|
|
3'd7: x__h100316 = m_m_reqVec_7_rl[226:222];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0: x__h102456 = m_m_reqVec_0_rl[226:222];
|
|
3'd1: x__h102456 = m_m_reqVec_1_rl[226:222];
|
|
3'd2: x__h102456 = m_m_reqVec_2_rl[226:222];
|
|
3'd3: x__h102456 = m_m_reqVec_3_rl[226:222];
|
|
3'd4: x__h102456 = m_m_reqVec_4_rl[226:222];
|
|
3'd5: x__h102456 = m_m_reqVec_5_rl[226:222];
|
|
3'd6: x__h102456 = m_m_reqVec_6_rl[226:222];
|
|
3'd7: x__h102456 = m_m_reqVec_7_rl[226:222];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0: x__h101857 = m_m_slotVec_0_rl[57:55];
|
|
3'd1: x__h101857 = m_m_slotVec_1_rl[57:55];
|
|
3'd2: x__h101857 = m_m_slotVec_2_rl[57:55];
|
|
3'd3: x__h101857 = m_m_slotVec_3_rl[57:55];
|
|
3'd4: x__h101857 = m_m_slotVec_4_rl[57:55];
|
|
3'd5: x__h101857 = m_m_slotVec_5_rl[57:55];
|
|
3'd6: x__h101857 = m_m_slotVec_6_rl[57:55];
|
|
3'd7: x__h101857 = m_m_slotVec_7_rl[57:55];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576 =
|
|
m_m_reqVec_0_rl[152];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576 =
|
|
m_m_reqVec_1_rl[152];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576 =
|
|
m_m_reqVec_2_rl[152];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576 =
|
|
m_m_reqVec_3_rl[152];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576 =
|
|
m_m_reqVec_4_rl[152];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576 =
|
|
m_m_reqVec_5_rl[152];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576 =
|
|
m_m_reqVec_6_rl[152];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1576 =
|
|
m_m_reqVec_7_rl[152];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617 =
|
|
m_m_reqVec_0_rl[152];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617 =
|
|
m_m_reqVec_1_rl[152];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617 =
|
|
m_m_reqVec_2_rl[152];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617 =
|
|
m_m_reqVec_3_rl[152];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617 =
|
|
m_m_reqVec_4_rl[152];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617 =
|
|
m_m_reqVec_5_rl[152];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617 =
|
|
m_m_reqVec_6_rl[152];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d617 =
|
|
m_m_reqVec_7_rl[152];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578 =
|
|
m_m_reqVec_0_rl[151];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578 =
|
|
m_m_reqVec_1_rl[151];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578 =
|
|
m_m_reqVec_2_rl[151];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578 =
|
|
m_m_reqVec_3_rl[151];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578 =
|
|
m_m_reqVec_4_rl[151];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578 =
|
|
m_m_reqVec_5_rl[151];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578 =
|
|
m_m_reqVec_6_rl[151];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1578 =
|
|
m_m_reqVec_7_rl[151];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580 =
|
|
m_m_reqVec_0_rl[150];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580 =
|
|
m_m_reqVec_1_rl[150];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580 =
|
|
m_m_reqVec_2_rl[150];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580 =
|
|
m_m_reqVec_3_rl[150];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580 =
|
|
m_m_reqVec_4_rl[150];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580 =
|
|
m_m_reqVec_5_rl[150];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580 =
|
|
m_m_reqVec_6_rl[150];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1580 =
|
|
m_m_reqVec_7_rl[150];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701 =
|
|
m_m_reqVec_0_rl[150];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701 =
|
|
m_m_reqVec_1_rl[150];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701 =
|
|
m_m_reqVec_2_rl[150];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701 =
|
|
m_m_reqVec_3_rl[150];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701 =
|
|
m_m_reqVec_4_rl[150];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701 =
|
|
m_m_reqVec_5_rl[150];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701 =
|
|
m_m_reqVec_6_rl[150];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d701 =
|
|
m_m_reqVec_7_rl[150];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659 =
|
|
m_m_reqVec_0_rl[151];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659 =
|
|
m_m_reqVec_1_rl[151];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659 =
|
|
m_m_reqVec_2_rl[151];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659 =
|
|
m_m_reqVec_3_rl[151];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659 =
|
|
m_m_reqVec_4_rl[151];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659 =
|
|
m_m_reqVec_5_rl[151];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659 =
|
|
m_m_reqVec_6_rl[151];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d659 =
|
|
m_m_reqVec_7_rl[151];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583 =
|
|
m_m_reqVec_0_rl[149];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583 =
|
|
m_m_reqVec_1_rl[149];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583 =
|
|
m_m_reqVec_2_rl[149];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583 =
|
|
m_m_reqVec_3_rl[149];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583 =
|
|
m_m_reqVec_4_rl[149];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583 =
|
|
m_m_reqVec_5_rl[149];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583 =
|
|
m_m_reqVec_6_rl[149];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1583 =
|
|
m_m_reqVec_7_rl[149];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585 =
|
|
m_m_reqVec_0_rl[148];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585 =
|
|
m_m_reqVec_1_rl[148];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585 =
|
|
m_m_reqVec_2_rl[148];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585 =
|
|
m_m_reqVec_3_rl[148];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585 =
|
|
m_m_reqVec_4_rl[148];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585 =
|
|
m_m_reqVec_5_rl[148];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585 =
|
|
m_m_reqVec_6_rl[148];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1585 =
|
|
m_m_reqVec_7_rl[148];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744 =
|
|
m_m_reqVec_0_rl[149];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744 =
|
|
m_m_reqVec_1_rl[149];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744 =
|
|
m_m_reqVec_2_rl[149];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744 =
|
|
m_m_reqVec_3_rl[149];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744 =
|
|
m_m_reqVec_4_rl[149];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744 =
|
|
m_m_reqVec_5_rl[149];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744 =
|
|
m_m_reqVec_6_rl[149];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d744 =
|
|
m_m_reqVec_7_rl[149];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786 =
|
|
m_m_reqVec_0_rl[148];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786 =
|
|
m_m_reqVec_1_rl[148];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786 =
|
|
m_m_reqVec_2_rl[148];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786 =
|
|
m_m_reqVec_3_rl[148];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786 =
|
|
m_m_reqVec_4_rl[148];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786 =
|
|
m_m_reqVec_5_rl[148];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786 =
|
|
m_m_reqVec_6_rl[148];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d786 =
|
|
m_m_reqVec_7_rl[148];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588 =
|
|
m_m_reqVec_0_rl[147];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588 =
|
|
m_m_reqVec_1_rl[147];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588 =
|
|
m_m_reqVec_2_rl[147];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588 =
|
|
m_m_reqVec_3_rl[147];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588 =
|
|
m_m_reqVec_4_rl[147];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588 =
|
|
m_m_reqVec_5_rl[147];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588 =
|
|
m_m_reqVec_6_rl[147];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1588 =
|
|
m_m_reqVec_7_rl[147];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590 =
|
|
m_m_reqVec_0_rl[146];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590 =
|
|
m_m_reqVec_1_rl[146];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590 =
|
|
m_m_reqVec_2_rl[146];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590 =
|
|
m_m_reqVec_3_rl[146];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590 =
|
|
m_m_reqVec_4_rl[146];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590 =
|
|
m_m_reqVec_5_rl[146];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590 =
|
|
m_m_reqVec_6_rl[146];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1590 =
|
|
m_m_reqVec_7_rl[146];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829 =
|
|
m_m_reqVec_0_rl[147];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829 =
|
|
m_m_reqVec_1_rl[147];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829 =
|
|
m_m_reqVec_2_rl[147];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829 =
|
|
m_m_reqVec_3_rl[147];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829 =
|
|
m_m_reqVec_4_rl[147];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829 =
|
|
m_m_reqVec_5_rl[147];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829 =
|
|
m_m_reqVec_6_rl[147];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d829 =
|
|
m_m_reqVec_7_rl[147];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871 =
|
|
m_m_reqVec_0_rl[146];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871 =
|
|
m_m_reqVec_1_rl[146];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871 =
|
|
m_m_reqVec_2_rl[146];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871 =
|
|
m_m_reqVec_3_rl[146];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871 =
|
|
m_m_reqVec_4_rl[146];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871 =
|
|
m_m_reqVec_5_rl[146];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871 =
|
|
m_m_reqVec_6_rl[146];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d871 =
|
|
m_m_reqVec_7_rl[146];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593 =
|
|
m_m_reqVec_0_rl[145];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593 =
|
|
m_m_reqVec_1_rl[145];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593 =
|
|
m_m_reqVec_2_rl[145];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593 =
|
|
m_m_reqVec_3_rl[145];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593 =
|
|
m_m_reqVec_4_rl[145];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593 =
|
|
m_m_reqVec_5_rl[145];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593 =
|
|
m_m_reqVec_6_rl[145];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1593 =
|
|
m_m_reqVec_7_rl[145];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914 =
|
|
m_m_reqVec_0_rl[145];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914 =
|
|
m_m_reqVec_1_rl[145];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914 =
|
|
m_m_reqVec_2_rl[145];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914 =
|
|
m_m_reqVec_3_rl[145];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914 =
|
|
m_m_reqVec_4_rl[145];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914 =
|
|
m_m_reqVec_5_rl[145];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914 =
|
|
m_m_reqVec_6_rl[145];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d914 =
|
|
m_m_reqVec_7_rl[145];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595 =
|
|
m_m_reqVec_0_rl[144];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595 =
|
|
m_m_reqVec_1_rl[144];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595 =
|
|
m_m_reqVec_2_rl[144];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595 =
|
|
m_m_reqVec_3_rl[144];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595 =
|
|
m_m_reqVec_4_rl[144];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595 =
|
|
m_m_reqVec_5_rl[144];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595 =
|
|
m_m_reqVec_6_rl[144];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1595 =
|
|
m_m_reqVec_7_rl[144];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956 =
|
|
m_m_reqVec_0_rl[144];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956 =
|
|
m_m_reqVec_1_rl[144];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956 =
|
|
m_m_reqVec_2_rl[144];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956 =
|
|
m_m_reqVec_3_rl[144];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956 =
|
|
m_m_reqVec_4_rl[144];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956 =
|
|
m_m_reqVec_5_rl[144];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956 =
|
|
m_m_reqVec_6_rl[144];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d956 =
|
|
m_m_reqVec_7_rl[144];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598 =
|
|
m_m_reqVec_0_rl[143];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598 =
|
|
m_m_reqVec_1_rl[143];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598 =
|
|
m_m_reqVec_2_rl[143];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598 =
|
|
m_m_reqVec_3_rl[143];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598 =
|
|
m_m_reqVec_4_rl[143];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598 =
|
|
m_m_reqVec_5_rl[143];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598 =
|
|
m_m_reqVec_6_rl[143];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1598 =
|
|
m_m_reqVec_7_rl[143];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600 =
|
|
m_m_reqVec_0_rl[142];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600 =
|
|
m_m_reqVec_1_rl[142];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600 =
|
|
m_m_reqVec_2_rl[142];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600 =
|
|
m_m_reqVec_3_rl[142];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600 =
|
|
m_m_reqVec_4_rl[142];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600 =
|
|
m_m_reqVec_5_rl[142];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600 =
|
|
m_m_reqVec_6_rl[142];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1600 =
|
|
m_m_reqVec_7_rl[142];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999 =
|
|
m_m_reqVec_0_rl[143];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999 =
|
|
m_m_reqVec_1_rl[143];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999 =
|
|
m_m_reqVec_2_rl[143];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999 =
|
|
m_m_reqVec_3_rl[143];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999 =
|
|
m_m_reqVec_4_rl[143];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999 =
|
|
m_m_reqVec_5_rl[143];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999 =
|
|
m_m_reqVec_6_rl[143];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d999 =
|
|
m_m_reqVec_7_rl[143];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041 =
|
|
m_m_reqVec_0_rl[142];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041 =
|
|
m_m_reqVec_1_rl[142];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041 =
|
|
m_m_reqVec_2_rl[142];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041 =
|
|
m_m_reqVec_3_rl[142];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041 =
|
|
m_m_reqVec_4_rl[142];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041 =
|
|
m_m_reqVec_5_rl[142];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041 =
|
|
m_m_reqVec_6_rl[142];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1041 =
|
|
m_m_reqVec_7_rl[142];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603 =
|
|
m_m_reqVec_0_rl[141];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603 =
|
|
m_m_reqVec_1_rl[141];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603 =
|
|
m_m_reqVec_2_rl[141];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603 =
|
|
m_m_reqVec_3_rl[141];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603 =
|
|
m_m_reqVec_4_rl[141];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603 =
|
|
m_m_reqVec_5_rl[141];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603 =
|
|
m_m_reqVec_6_rl[141];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1603 =
|
|
m_m_reqVec_7_rl[141];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605 =
|
|
m_m_reqVec_0_rl[140];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605 =
|
|
m_m_reqVec_1_rl[140];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605 =
|
|
m_m_reqVec_2_rl[140];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605 =
|
|
m_m_reqVec_3_rl[140];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605 =
|
|
m_m_reqVec_4_rl[140];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605 =
|
|
m_m_reqVec_5_rl[140];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605 =
|
|
m_m_reqVec_6_rl[140];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1605 =
|
|
m_m_reqVec_7_rl[140];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084 =
|
|
m_m_reqVec_0_rl[141];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084 =
|
|
m_m_reqVec_1_rl[141];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084 =
|
|
m_m_reqVec_2_rl[141];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084 =
|
|
m_m_reqVec_3_rl[141];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084 =
|
|
m_m_reqVec_4_rl[141];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084 =
|
|
m_m_reqVec_5_rl[141];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084 =
|
|
m_m_reqVec_6_rl[141];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1084 =
|
|
m_m_reqVec_7_rl[141];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126 =
|
|
m_m_reqVec_0_rl[140];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126 =
|
|
m_m_reqVec_1_rl[140];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126 =
|
|
m_m_reqVec_2_rl[140];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126 =
|
|
m_m_reqVec_3_rl[140];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126 =
|
|
m_m_reqVec_4_rl[140];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126 =
|
|
m_m_reqVec_5_rl[140];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126 =
|
|
m_m_reqVec_6_rl[140];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1126 =
|
|
m_m_reqVec_7_rl[140];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296 =
|
|
m_m_reqVec_0_rl[136];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296 =
|
|
m_m_reqVec_1_rl[136];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296 =
|
|
m_m_reqVec_2_rl[136];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296 =
|
|
m_m_reqVec_3_rl[136];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296 =
|
|
m_m_reqVec_4_rl[136];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296 =
|
|
m_m_reqVec_5_rl[136];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296 =
|
|
m_m_reqVec_6_rl[136];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1296 =
|
|
m_m_reqVec_7_rl[136];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615 =
|
|
m_m_reqVec_0_rl[136];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615 =
|
|
m_m_reqVec_1_rl[136];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615 =
|
|
m_m_reqVec_2_rl[136];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615 =
|
|
m_m_reqVec_3_rl[136];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615 =
|
|
m_m_reqVec_4_rl[136];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615 =
|
|
m_m_reqVec_5_rl[136];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615 =
|
|
m_m_reqVec_6_rl[136];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1615 =
|
|
m_m_reqVec_7_rl[136];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626 =
|
|
m_m_reqVec_0_rl[1];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626 =
|
|
m_m_reqVec_1_rl[1];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626 =
|
|
m_m_reqVec_2_rl[1];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626 =
|
|
m_m_reqVec_3_rl[1];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626 =
|
|
m_m_reqVec_4_rl[1];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626 =
|
|
m_m_reqVec_5_rl[1];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626 =
|
|
m_m_reqVec_6_rl[1];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1626 =
|
|
m_m_reqVec_7_rl[1];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507 =
|
|
m_m_reqVec_0_rl[1];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507 =
|
|
m_m_reqVec_1_rl[1];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507 =
|
|
m_m_reqVec_2_rl[1];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507 =
|
|
m_m_reqVec_3_rl[1];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507 =
|
|
m_m_reqVec_4_rl[1];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507 =
|
|
m_m_reqVec_5_rl[1];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507 =
|
|
m_m_reqVec_6_rl[1];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1507 =
|
|
m_m_reqVec_7_rl[1];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622 =
|
|
m_m_reqVec_0_rl[7:4];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622 =
|
|
m_m_reqVec_1_rl[7:4];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622 =
|
|
m_m_reqVec_2_rl[7:4];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622 =
|
|
m_m_reqVec_3_rl[7:4];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622 =
|
|
m_m_reqVec_4_rl[7:4];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622 =
|
|
m_m_reqVec_5_rl[7:4];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622 =
|
|
m_m_reqVec_6_rl[7:4];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1622 =
|
|
m_m_reqVec_7_rl[7:4];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423 =
|
|
m_m_reqVec_0_rl[7:4];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423 =
|
|
m_m_reqVec_1_rl[7:4];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423 =
|
|
m_m_reqVec_2_rl[7:4];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423 =
|
|
m_m_reqVec_3_rl[7:4];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423 =
|
|
m_m_reqVec_4_rl[7:4];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423 =
|
|
m_m_reqVec_5_rl[7:4];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423 =
|
|
m_m_reqVec_6_rl[7:4];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1423 =
|
|
m_m_reqVec_7_rl[7:4];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608 =
|
|
m_m_reqVec_0_rl[139];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608 =
|
|
m_m_reqVec_1_rl[139];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608 =
|
|
m_m_reqVec_2_rl[139];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608 =
|
|
m_m_reqVec_3_rl[139];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608 =
|
|
m_m_reqVec_4_rl[139];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608 =
|
|
m_m_reqVec_5_rl[139];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608 =
|
|
m_m_reqVec_6_rl[139];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1608 =
|
|
m_m_reqVec_7_rl[139];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610 =
|
|
m_m_reqVec_0_rl[138];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610 =
|
|
m_m_reqVec_1_rl[138];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610 =
|
|
m_m_reqVec_2_rl[138];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610 =
|
|
m_m_reqVec_3_rl[138];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610 =
|
|
m_m_reqVec_4_rl[138];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610 =
|
|
m_m_reqVec_5_rl[138];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610 =
|
|
m_m_reqVec_6_rl[138];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1610 =
|
|
m_m_reqVec_7_rl[138];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169 =
|
|
m_m_reqVec_0_rl[139];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169 =
|
|
m_m_reqVec_1_rl[139];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169 =
|
|
m_m_reqVec_2_rl[139];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169 =
|
|
m_m_reqVec_3_rl[139];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169 =
|
|
m_m_reqVec_4_rl[139];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169 =
|
|
m_m_reqVec_5_rl[139];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169 =
|
|
m_m_reqVec_6_rl[139];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1169 =
|
|
m_m_reqVec_7_rl[139];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211 =
|
|
m_m_reqVec_0_rl[138];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211 =
|
|
m_m_reqVec_1_rl[138];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211 =
|
|
m_m_reqVec_2_rl[138];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211 =
|
|
m_m_reqVec_3_rl[138];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211 =
|
|
m_m_reqVec_4_rl[138];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211 =
|
|
m_m_reqVec_5_rl[138];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211 =
|
|
m_m_reqVec_6_rl[138];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1211 =
|
|
m_m_reqVec_7_rl[138];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572 =
|
|
m_m_reqVec_0_rl[157:156];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572 =
|
|
m_m_reqVec_1_rl[157:156];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572 =
|
|
m_m_reqVec_2_rl[157:156];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572 =
|
|
m_m_reqVec_3_rl[157:156];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572 =
|
|
m_m_reqVec_4_rl[157:156];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572 =
|
|
m_m_reqVec_5_rl[157:156];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572 =
|
|
m_m_reqVec_6_rl[157:156];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1572 =
|
|
m_m_reqVec_7_rl[157:156];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690 =
|
|
m_m_reqVec_0_rl[152];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690 =
|
|
m_m_reqVec_1_rl[152];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690 =
|
|
m_m_reqVec_2_rl[152];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690 =
|
|
m_m_reqVec_3_rl[152];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690 =
|
|
m_m_reqVec_4_rl[152];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690 =
|
|
m_m_reqVec_5_rl[152];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690 =
|
|
m_m_reqVec_6_rl[152];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_152_78_m_m_reqVe_ETC___d1690 =
|
|
m_m_reqVec_7_rl[152];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533 =
|
|
m_m_reqVec_0_rl[157:156];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533 =
|
|
m_m_reqVec_1_rl[157:156];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533 =
|
|
m_m_reqVec_2_rl[157:156];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533 =
|
|
m_m_reqVec_3_rl[157:156];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533 =
|
|
m_m_reqVec_4_rl[157:156];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533 =
|
|
m_m_reqVec_5_rl[157:156];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533 =
|
|
m_m_reqVec_6_rl[157:156];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d533 =
|
|
m_m_reqVec_7_rl[157:156];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691 =
|
|
m_m_reqVec_0_rl[151];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691 =
|
|
m_m_reqVec_1_rl[151];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691 =
|
|
m_m_reqVec_2_rl[151];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691 =
|
|
m_m_reqVec_3_rl[151];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691 =
|
|
m_m_reqVec_4_rl[151];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691 =
|
|
m_m_reqVec_5_rl[151];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691 =
|
|
m_m_reqVec_6_rl[151];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_151_20_m_m_reqVe_ETC___d1691 =
|
|
m_m_reqVec_7_rl[151];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692 =
|
|
m_m_reqVec_0_rl[150];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692 =
|
|
m_m_reqVec_1_rl[150];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692 =
|
|
m_m_reqVec_2_rl[150];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692 =
|
|
m_m_reqVec_3_rl[150];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692 =
|
|
m_m_reqVec_4_rl[150];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692 =
|
|
m_m_reqVec_5_rl[150];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692 =
|
|
m_m_reqVec_6_rl[150];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_150_62_m_m_reqVe_ETC___d1692 =
|
|
m_m_reqVec_7_rl[150];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694 =
|
|
m_m_reqVec_0_rl[149];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694 =
|
|
m_m_reqVec_1_rl[149];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694 =
|
|
m_m_reqVec_2_rl[149];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694 =
|
|
m_m_reqVec_3_rl[149];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694 =
|
|
m_m_reqVec_4_rl[149];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694 =
|
|
m_m_reqVec_5_rl[149];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694 =
|
|
m_m_reqVec_6_rl[149];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_149_05_m_m_reqVe_ETC___d1694 =
|
|
m_m_reqVec_7_rl[149];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695 =
|
|
m_m_reqVec_0_rl[148];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695 =
|
|
m_m_reqVec_1_rl[148];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695 =
|
|
m_m_reqVec_2_rl[148];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695 =
|
|
m_m_reqVec_3_rl[148];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695 =
|
|
m_m_reqVec_4_rl[148];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695 =
|
|
m_m_reqVec_5_rl[148];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695 =
|
|
m_m_reqVec_6_rl[148];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_148_47_m_m_reqVe_ETC___d1695 =
|
|
m_m_reqVec_7_rl[148];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697 =
|
|
m_m_reqVec_0_rl[147];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697 =
|
|
m_m_reqVec_1_rl[147];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697 =
|
|
m_m_reqVec_2_rl[147];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697 =
|
|
m_m_reqVec_3_rl[147];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697 =
|
|
m_m_reqVec_4_rl[147];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697 =
|
|
m_m_reqVec_5_rl[147];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697 =
|
|
m_m_reqVec_6_rl[147];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_147_90_m_m_reqVe_ETC___d1697 =
|
|
m_m_reqVec_7_rl[147];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698 =
|
|
m_m_reqVec_0_rl[146];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698 =
|
|
m_m_reqVec_1_rl[146];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698 =
|
|
m_m_reqVec_2_rl[146];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698 =
|
|
m_m_reqVec_3_rl[146];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698 =
|
|
m_m_reqVec_4_rl[146];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698 =
|
|
m_m_reqVec_5_rl[146];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698 =
|
|
m_m_reqVec_6_rl[146];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_146_32_m_m_reqVe_ETC___d1698 =
|
|
m_m_reqVec_7_rl[146];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700 =
|
|
m_m_reqVec_0_rl[145];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700 =
|
|
m_m_reqVec_1_rl[145];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700 =
|
|
m_m_reqVec_2_rl[145];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700 =
|
|
m_m_reqVec_3_rl[145];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700 =
|
|
m_m_reqVec_4_rl[145];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700 =
|
|
m_m_reqVec_5_rl[145];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700 =
|
|
m_m_reqVec_6_rl[145];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_145_75_m_m_reqVe_ETC___d1700 =
|
|
m_m_reqVec_7_rl[145];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701 =
|
|
m_m_reqVec_0_rl[144];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701 =
|
|
m_m_reqVec_1_rl[144];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701 =
|
|
m_m_reqVec_2_rl[144];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701 =
|
|
m_m_reqVec_3_rl[144];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701 =
|
|
m_m_reqVec_4_rl[144];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701 =
|
|
m_m_reqVec_5_rl[144];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701 =
|
|
m_m_reqVec_6_rl[144];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_144_17_m_m_reqVe_ETC___d1701 =
|
|
m_m_reqVec_7_rl[144];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703 =
|
|
m_m_reqVec_0_rl[143];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703 =
|
|
m_m_reqVec_1_rl[143];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703 =
|
|
m_m_reqVec_2_rl[143];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703 =
|
|
m_m_reqVec_3_rl[143];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703 =
|
|
m_m_reqVec_4_rl[143];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703 =
|
|
m_m_reqVec_5_rl[143];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703 =
|
|
m_m_reqVec_6_rl[143];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_143_60_m_m_reqVe_ETC___d1703 =
|
|
m_m_reqVec_7_rl[143];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706 =
|
|
m_m_reqVec_0_rl[141];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706 =
|
|
m_m_reqVec_1_rl[141];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706 =
|
|
m_m_reqVec_2_rl[141];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706 =
|
|
m_m_reqVec_3_rl[141];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706 =
|
|
m_m_reqVec_4_rl[141];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706 =
|
|
m_m_reqVec_5_rl[141];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706 =
|
|
m_m_reqVec_6_rl[141];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_141_045_m_m_reqV_ETC___d1706 =
|
|
m_m_reqVec_7_rl[141];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704 =
|
|
m_m_reqVec_0_rl[142];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704 =
|
|
m_m_reqVec_1_rl[142];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704 =
|
|
m_m_reqVec_2_rl[142];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704 =
|
|
m_m_reqVec_3_rl[142];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704 =
|
|
m_m_reqVec_4_rl[142];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704 =
|
|
m_m_reqVec_5_rl[142];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704 =
|
|
m_m_reqVec_6_rl[142];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_142_002_m_m_reqV_ETC___d1704 =
|
|
m_m_reqVec_7_rl[142];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707 =
|
|
m_m_reqVec_0_rl[140];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707 =
|
|
m_m_reqVec_1_rl[140];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707 =
|
|
m_m_reqVec_2_rl[140];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707 =
|
|
m_m_reqVec_3_rl[140];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707 =
|
|
m_m_reqVec_4_rl[140];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707 =
|
|
m_m_reqVec_5_rl[140];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707 =
|
|
m_m_reqVec_6_rl[140];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_140_087_m_m_reqV_ETC___d1707 =
|
|
m_m_reqVec_7_rl[140];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713 =
|
|
m_m_reqVec_0_rl[136];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713 =
|
|
m_m_reqVec_1_rl[136];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713 =
|
|
m_m_reqVec_2_rl[136];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713 =
|
|
m_m_reqVec_3_rl[136];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713 =
|
|
m_m_reqVec_4_rl[136];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713 =
|
|
m_m_reqVec_5_rl[136];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713 =
|
|
m_m_reqVec_6_rl[136];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_136_257_m_m_reqV_ETC___d1713 =
|
|
m_m_reqVec_7_rl[136];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719 =
|
|
m_m_reqVec_0_rl[1];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719 =
|
|
m_m_reqVec_1_rl[1];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719 =
|
|
m_m_reqVec_2_rl[1];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719 =
|
|
m_m_reqVec_3_rl[1];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719 =
|
|
m_m_reqVec_4_rl[1];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719 =
|
|
m_m_reqVec_5_rl[1];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719 =
|
|
m_m_reqVec_6_rl[1];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_1_468_m_m_reqVec_ETC___d1719 =
|
|
m_m_reqVec_7_rl[1];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717 =
|
|
m_m_reqVec_0_rl[7:4];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717 =
|
|
m_m_reqVec_1_rl[7:4];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717 =
|
|
m_m_reqVec_2_rl[7:4];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717 =
|
|
m_m_reqVec_3_rl[7:4];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717 =
|
|
m_m_reqVec_4_rl[7:4];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717 =
|
|
m_m_reqVec_5_rl[7:4];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717 =
|
|
m_m_reqVec_6_rl[7:4];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_7_TO_4_384_m_m__ETC___d1717 =
|
|
m_m_reqVec_7_rl[7:4];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709 =
|
|
m_m_reqVec_0_rl[139];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709 =
|
|
m_m_reqVec_1_rl[139];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709 =
|
|
m_m_reqVec_2_rl[139];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709 =
|
|
m_m_reqVec_3_rl[139];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709 =
|
|
m_m_reqVec_4_rl[139];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709 =
|
|
m_m_reqVec_5_rl[139];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709 =
|
|
m_m_reqVec_6_rl[139];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_139_130_m_m_reqV_ETC___d1709 =
|
|
m_m_reqVec_7_rl[139];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710 =
|
|
m_m_reqVec_0_rl[138];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710 =
|
|
m_m_reqVec_1_rl[138];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710 =
|
|
m_m_reqVec_2_rl[138];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710 =
|
|
m_m_reqVec_3_rl[138];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710 =
|
|
m_m_reqVec_4_rl[138];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710 =
|
|
m_m_reqVec_5_rl[138];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710 =
|
|
m_m_reqVec_6_rl[138];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_138_172_m_m_reqV_ETC___d1710 =
|
|
m_m_reqVec_7_rl[138];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688 =
|
|
m_m_reqVec_0_rl[157:156];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688 =
|
|
m_m_reqVec_1_rl[157:156];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688 =
|
|
m_m_reqVec_2_rl[157:156];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688 =
|
|
m_m_reqVec_3_rl[157:156];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688 =
|
|
m_m_reqVec_4_rl[157:156];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688 =
|
|
m_m_reqVec_5_rl[157:156];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688 =
|
|
m_m_reqVec_6_rl[157:156];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_157_TO_156_94_m_ETC___d1688 =
|
|
m_m_reqVec_7_rl[157:156];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748 =
|
|
m_m_reqVec_0_rl[152];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748 =
|
|
m_m_reqVec_1_rl[152];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748 =
|
|
m_m_reqVec_2_rl[152];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748 =
|
|
m_m_reqVec_3_rl[152];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748 =
|
|
m_m_reqVec_4_rl[152];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748 =
|
|
m_m_reqVec_5_rl[152];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748 =
|
|
m_m_reqVec_6_rl[152];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1748 =
|
|
m_m_reqVec_7_rl[152];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752 =
|
|
m_m_reqVec_0_rl[150];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752 =
|
|
m_m_reqVec_1_rl[150];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752 =
|
|
m_m_reqVec_2_rl[150];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752 =
|
|
m_m_reqVec_3_rl[150];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752 =
|
|
m_m_reqVec_4_rl[150];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752 =
|
|
m_m_reqVec_5_rl[150];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752 =
|
|
m_m_reqVec_6_rl[150];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1752 =
|
|
m_m_reqVec_7_rl[150];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750 =
|
|
m_m_reqVec_0_rl[151];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750 =
|
|
m_m_reqVec_1_rl[151];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750 =
|
|
m_m_reqVec_2_rl[151];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750 =
|
|
m_m_reqVec_3_rl[151];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750 =
|
|
m_m_reqVec_4_rl[151];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750 =
|
|
m_m_reqVec_5_rl[151];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750 =
|
|
m_m_reqVec_6_rl[151];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1750 =
|
|
m_m_reqVec_7_rl[151];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755 =
|
|
m_m_reqVec_0_rl[149];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755 =
|
|
m_m_reqVec_1_rl[149];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755 =
|
|
m_m_reqVec_2_rl[149];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755 =
|
|
m_m_reqVec_3_rl[149];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755 =
|
|
m_m_reqVec_4_rl[149];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755 =
|
|
m_m_reqVec_5_rl[149];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755 =
|
|
m_m_reqVec_6_rl[149];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1755 =
|
|
m_m_reqVec_7_rl[149];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757 =
|
|
m_m_reqVec_0_rl[148];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757 =
|
|
m_m_reqVec_1_rl[148];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757 =
|
|
m_m_reqVec_2_rl[148];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757 =
|
|
m_m_reqVec_3_rl[148];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757 =
|
|
m_m_reqVec_4_rl[148];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757 =
|
|
m_m_reqVec_5_rl[148];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757 =
|
|
m_m_reqVec_6_rl[148];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1757 =
|
|
m_m_reqVec_7_rl[148];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762 =
|
|
m_m_reqVec_0_rl[146];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762 =
|
|
m_m_reqVec_1_rl[146];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762 =
|
|
m_m_reqVec_2_rl[146];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762 =
|
|
m_m_reqVec_3_rl[146];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762 =
|
|
m_m_reqVec_4_rl[146];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762 =
|
|
m_m_reqVec_5_rl[146];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762 =
|
|
m_m_reqVec_6_rl[146];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1762 =
|
|
m_m_reqVec_7_rl[146];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760 =
|
|
m_m_reqVec_0_rl[147];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760 =
|
|
m_m_reqVec_1_rl[147];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760 =
|
|
m_m_reqVec_2_rl[147];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760 =
|
|
m_m_reqVec_3_rl[147];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760 =
|
|
m_m_reqVec_4_rl[147];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760 =
|
|
m_m_reqVec_5_rl[147];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760 =
|
|
m_m_reqVec_6_rl[147];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1760 =
|
|
m_m_reqVec_7_rl[147];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765 =
|
|
m_m_reqVec_0_rl[145];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765 =
|
|
m_m_reqVec_1_rl[145];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765 =
|
|
m_m_reqVec_2_rl[145];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765 =
|
|
m_m_reqVec_3_rl[145];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765 =
|
|
m_m_reqVec_4_rl[145];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765 =
|
|
m_m_reqVec_5_rl[145];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765 =
|
|
m_m_reqVec_6_rl[145];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1765 =
|
|
m_m_reqVec_7_rl[145];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767 =
|
|
m_m_reqVec_0_rl[144];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767 =
|
|
m_m_reqVec_1_rl[144];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767 =
|
|
m_m_reqVec_2_rl[144];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767 =
|
|
m_m_reqVec_3_rl[144];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767 =
|
|
m_m_reqVec_4_rl[144];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767 =
|
|
m_m_reqVec_5_rl[144];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767 =
|
|
m_m_reqVec_6_rl[144];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1767 =
|
|
m_m_reqVec_7_rl[144];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770 =
|
|
m_m_reqVec_0_rl[143];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770 =
|
|
m_m_reqVec_1_rl[143];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770 =
|
|
m_m_reqVec_2_rl[143];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770 =
|
|
m_m_reqVec_3_rl[143];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770 =
|
|
m_m_reqVec_4_rl[143];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770 =
|
|
m_m_reqVec_5_rl[143];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770 =
|
|
m_m_reqVec_6_rl[143];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1770 =
|
|
m_m_reqVec_7_rl[143];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772 =
|
|
m_m_reqVec_0_rl[142];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772 =
|
|
m_m_reqVec_1_rl[142];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772 =
|
|
m_m_reqVec_2_rl[142];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772 =
|
|
m_m_reqVec_3_rl[142];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772 =
|
|
m_m_reqVec_4_rl[142];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772 =
|
|
m_m_reqVec_5_rl[142];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772 =
|
|
m_m_reqVec_6_rl[142];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1772 =
|
|
m_m_reqVec_7_rl[142];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775 =
|
|
m_m_reqVec_0_rl[141];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775 =
|
|
m_m_reqVec_1_rl[141];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775 =
|
|
m_m_reqVec_2_rl[141];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775 =
|
|
m_m_reqVec_3_rl[141];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775 =
|
|
m_m_reqVec_4_rl[141];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775 =
|
|
m_m_reqVec_5_rl[141];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775 =
|
|
m_m_reqVec_6_rl[141];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1775 =
|
|
m_m_reqVec_7_rl[141];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787 =
|
|
m_m_reqVec_0_rl[136];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787 =
|
|
m_m_reqVec_1_rl[136];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787 =
|
|
m_m_reqVec_2_rl[136];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787 =
|
|
m_m_reqVec_3_rl[136];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787 =
|
|
m_m_reqVec_4_rl[136];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787 =
|
|
m_m_reqVec_5_rl[136];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787 =
|
|
m_m_reqVec_6_rl[136];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1787 =
|
|
m_m_reqVec_7_rl[136];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777 =
|
|
m_m_reqVec_0_rl[140];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777 =
|
|
m_m_reqVec_1_rl[140];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777 =
|
|
m_m_reqVec_2_rl[140];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777 =
|
|
m_m_reqVec_3_rl[140];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777 =
|
|
m_m_reqVec_4_rl[140];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777 =
|
|
m_m_reqVec_5_rl[140];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777 =
|
|
m_m_reqVec_6_rl[140];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1777 =
|
|
m_m_reqVec_7_rl[140];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798 =
|
|
m_m_reqVec_0_rl[1];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798 =
|
|
m_m_reqVec_1_rl[1];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798 =
|
|
m_m_reqVec_2_rl[1];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798 =
|
|
m_m_reqVec_3_rl[1];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798 =
|
|
m_m_reqVec_4_rl[1];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798 =
|
|
m_m_reqVec_5_rl[1];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798 =
|
|
m_m_reqVec_6_rl[1];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1798 =
|
|
m_m_reqVec_7_rl[1];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794 =
|
|
m_m_reqVec_0_rl[7:4];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794 =
|
|
m_m_reqVec_1_rl[7:4];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794 =
|
|
m_m_reqVec_2_rl[7:4];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794 =
|
|
m_m_reqVec_3_rl[7:4];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794 =
|
|
m_m_reqVec_4_rl[7:4];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794 =
|
|
m_m_reqVec_5_rl[7:4];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794 =
|
|
m_m_reqVec_6_rl[7:4];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1794 =
|
|
m_m_reqVec_7_rl[7:4];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780 =
|
|
m_m_reqVec_0_rl[139];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780 =
|
|
m_m_reqVec_1_rl[139];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780 =
|
|
m_m_reqVec_2_rl[139];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780 =
|
|
m_m_reqVec_3_rl[139];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780 =
|
|
m_m_reqVec_4_rl[139];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780 =
|
|
m_m_reqVec_5_rl[139];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780 =
|
|
m_m_reqVec_6_rl[139];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1780 =
|
|
m_m_reqVec_7_rl[139];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782 =
|
|
m_m_reqVec_0_rl[138];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782 =
|
|
m_m_reqVec_1_rl[138];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782 =
|
|
m_m_reqVec_2_rl[138];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782 =
|
|
m_m_reqVec_3_rl[138];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782 =
|
|
m_m_reqVec_4_rl[138];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782 =
|
|
m_m_reqVec_5_rl[138];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782 =
|
|
m_m_reqVec_6_rl[138];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1782 =
|
|
m_m_reqVec_7_rl[138];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744 =
|
|
m_m_reqVec_0_rl[157:156];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744 =
|
|
m_m_reqVec_1_rl[157:156];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744 =
|
|
m_m_reqVec_2_rl[157:156];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744 =
|
|
m_m_reqVec_3_rl[157:156];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744 =
|
|
m_m_reqVec_4_rl[157:156];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744 =
|
|
m_m_reqVec_5_rl[157:156];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744 =
|
|
m_m_reqVec_6_rl[157:156];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1744 =
|
|
m_m_reqVec_7_rl[157:156];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getData_n or
|
|
m_m_dataValidVec_0_rl or
|
|
m_m_dataValidVec_1_rl or
|
|
m_m_dataValidVec_2_rl or
|
|
m_m_dataValidVec_3_rl or
|
|
m_m_dataValidVec_4_rl or
|
|
m_m_dataValidVec_5_rl or
|
|
m_m_dataValidVec_6_rl or m_m_dataValidVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getData_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675 =
|
|
m_m_dataValidVec_0_rl;
|
|
3'd1:
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675 =
|
|
m_m_dataValidVec_1_rl;
|
|
3'd2:
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675 =
|
|
m_m_dataValidVec_2_rl;
|
|
3'd3:
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675 =
|
|
m_m_dataValidVec_3_rl;
|
|
3'd4:
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675 =
|
|
m_m_dataValidVec_4_rl;
|
|
3'd5:
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675 =
|
|
m_m_dataValidVec_5_rl;
|
|
3'd6:
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675 =
|
|
m_m_dataValidVec_6_rl;
|
|
3'd7:
|
|
SEL_ARR_m_m_dataValidVec_0_rl_47_m_m_dataValid_ETC___d1675 =
|
|
m_m_dataValidVec_7_rl;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSucc_n or
|
|
m_m_succValidVec_0_rl or
|
|
m_m_succValidVec_1_rl or
|
|
m_m_succValidVec_2_rl or
|
|
m_m_succValidVec_3_rl or
|
|
m_m_succValidVec_4_rl or
|
|
m_m_succValidVec_5_rl or
|
|
m_m_succValidVec_6_rl or m_m_succValidVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSucc_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899 =
|
|
m_m_succValidVec_0_rl;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899 =
|
|
m_m_succValidVec_1_rl;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899 =
|
|
m_m_succValidVec_2_rl;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899 =
|
|
m_m_succValidVec_3_rl;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899 =
|
|
m_m_succValidVec_4_rl;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899 =
|
|
m_m_succValidVec_5_rl;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899 =
|
|
m_m_succValidVec_6_rl;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_succValidVec_0_lat_0_whas__25_T_ETC___d1899 =
|
|
m_m_succValidVec_7_rl;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 =
|
|
m_m_reqVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 =
|
|
m_m_reqVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 =
|
|
m_m_reqVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 =
|
|
m_m_reqVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 =
|
|
m_m_reqVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 =
|
|
m_m_reqVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 =
|
|
m_m_reqVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1628 =
|
|
m_m_reqVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 =
|
|
m_m_reqVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 =
|
|
m_m_reqVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 =
|
|
m_m_reqVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 =
|
|
m_m_reqVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 =
|
|
m_m_reqVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 =
|
|
m_m_reqVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 =
|
|
m_m_reqVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1549 =
|
|
m_m_reqVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 =
|
|
m_m_reqVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 =
|
|
m_m_reqVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 =
|
|
m_m_reqVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 =
|
|
m_m_reqVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 =
|
|
m_m_reqVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 =
|
|
m_m_reqVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 =
|
|
m_m_reqVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_0_510_m_m_reqVec_ETC___d1720 =
|
|
m_m_reqVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 =
|
|
m_m_reqVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 =
|
|
m_m_reqVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 =
|
|
m_m_reqVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 =
|
|
m_m_reqVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 =
|
|
m_m_reqVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 =
|
|
m_m_reqVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 =
|
|
m_m_reqVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1800 =
|
|
m_m_reqVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624 =
|
|
m_m_reqVec_0_rl[3:2];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624 =
|
|
m_m_reqVec_1_rl[3:2];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624 =
|
|
m_m_reqVec_2_rl[3:2];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624 =
|
|
m_m_reqVec_3_rl[3:2];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624 =
|
|
m_m_reqVec_4_rl[3:2];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624 =
|
|
m_m_reqVec_5_rl[3:2];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624 =
|
|
m_m_reqVec_6_rl[3:2];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1624 =
|
|
m_m_reqVec_7_rl[3:2];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465 =
|
|
m_m_reqVec_0_rl[3:2];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465 =
|
|
m_m_reqVec_1_rl[3:2];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465 =
|
|
m_m_reqVec_2_rl[3:2];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465 =
|
|
m_m_reqVec_3_rl[3:2];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465 =
|
|
m_m_reqVec_4_rl[3:2];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465 =
|
|
m_m_reqVec_5_rl[3:2];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465 =
|
|
m_m_reqVec_6_rl[3:2];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1465 =
|
|
m_m_reqVec_7_rl[3:2];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796 =
|
|
m_m_reqVec_0_rl[3:2];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796 =
|
|
m_m_reqVec_1_rl[3:2];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796 =
|
|
m_m_reqVec_2_rl[3:2];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796 =
|
|
m_m_reqVec_3_rl[3:2];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796 =
|
|
m_m_reqVec_4_rl[3:2];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796 =
|
|
m_m_reqVec_5_rl[3:2];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796 =
|
|
m_m_reqVec_6_rl[3:2];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1796 =
|
|
m_m_reqVec_7_rl[3:2];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718 =
|
|
m_m_reqVec_0_rl[3:2];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718 =
|
|
m_m_reqVec_1_rl[3:2];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718 =
|
|
m_m_reqVec_2_rl[3:2];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718 =
|
|
m_m_reqVec_3_rl[3:2];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718 =
|
|
m_m_reqVec_4_rl[3:2];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718 =
|
|
m_m_reqVec_5_rl[3:2];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718 =
|
|
m_m_reqVec_6_rl[3:2];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_3_TO_2_426_m_m__ETC___d1718 =
|
|
m_m_reqVec_7_rl[3:2];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 =
|
|
m_m_slotVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 =
|
|
m_m_slotVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 =
|
|
m_m_slotVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 =
|
|
m_m_slotVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 =
|
|
m_m_slotVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 =
|
|
m_m_slotVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 =
|
|
m_m_slotVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1728 =
|
|
m_m_slotVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 =
|
|
m_m_slotVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 =
|
|
m_m_slotVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 =
|
|
m_m_slotVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 =
|
|
m_m_slotVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 =
|
|
m_m_slotVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 =
|
|
m_m_slotVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 =
|
|
m_m_slotVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BIT_0_663_m_m_slot_ETC___d1672 =
|
|
m_m_slotVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617 =
|
|
m_m_reqVec_0_rl[135:72];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617 =
|
|
m_m_reqVec_1_rl[135:72];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617 =
|
|
m_m_reqVec_2_rl[135:72];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617 =
|
|
m_m_reqVec_3_rl[135:72];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617 =
|
|
m_m_reqVec_4_rl[135:72];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617 =
|
|
m_m_reqVec_5_rl[135:72];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617 =
|
|
m_m_reqVec_6_rl[135:72];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1617 =
|
|
m_m_reqVec_7_rl[135:72];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619 =
|
|
m_m_reqVec_0_rl[71:8];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619 =
|
|
m_m_reqVec_1_rl[71:8];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619 =
|
|
m_m_reqVec_2_rl[71:8];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619 =
|
|
m_m_reqVec_3_rl[71:8];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619 =
|
|
m_m_reqVec_4_rl[71:8];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619 =
|
|
m_m_reqVec_5_rl[71:8];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619 =
|
|
m_m_reqVec_6_rl[71:8];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1619 =
|
|
m_m_reqVec_7_rl[71:8];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338 =
|
|
m_m_reqVec_0_rl[135:72];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338 =
|
|
m_m_reqVec_1_rl[135:72];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338 =
|
|
m_m_reqVec_2_rl[135:72];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338 =
|
|
m_m_reqVec_3_rl[135:72];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338 =
|
|
m_m_reqVec_4_rl[135:72];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338 =
|
|
m_m_reqVec_5_rl[135:72];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338 =
|
|
m_m_reqVec_6_rl[135:72];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1338 =
|
|
m_m_reqVec_7_rl[135:72];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380 =
|
|
m_m_reqVec_0_rl[71:8];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380 =
|
|
m_m_reqVec_1_rl[71:8];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380 =
|
|
m_m_reqVec_2_rl[71:8];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380 =
|
|
m_m_reqVec_3_rl[71:8];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380 =
|
|
m_m_reqVec_4_rl[71:8];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380 =
|
|
m_m_reqVec_5_rl[71:8];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380 =
|
|
m_m_reqVec_6_rl[71:8];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1380 =
|
|
m_m_reqVec_7_rl[71:8];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714 =
|
|
m_m_reqVec_0_rl[135:72];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714 =
|
|
m_m_reqVec_1_rl[135:72];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714 =
|
|
m_m_reqVec_2_rl[135:72];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714 =
|
|
m_m_reqVec_3_rl[135:72];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714 =
|
|
m_m_reqVec_4_rl[135:72];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714 =
|
|
m_m_reqVec_5_rl[135:72];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714 =
|
|
m_m_reqVec_6_rl[135:72];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_135_TO_72_299_m_ETC___d1714 =
|
|
m_m_reqVec_7_rl[135:72];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715 =
|
|
m_m_reqVec_0_rl[71:8];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715 =
|
|
m_m_reqVec_1_rl[71:8];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715 =
|
|
m_m_reqVec_2_rl[71:8];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715 =
|
|
m_m_reqVec_3_rl[71:8];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715 =
|
|
m_m_reqVec_4_rl[71:8];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715 =
|
|
m_m_reqVec_5_rl[71:8];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715 =
|
|
m_m_reqVec_6_rl[71:8];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_71_TO_8_341_m_m_ETC___d1715 =
|
|
m_m_reqVec_7_rl[71:8];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791 =
|
|
m_m_reqVec_0_rl[71:8];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791 =
|
|
m_m_reqVec_1_rl[71:8];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791 =
|
|
m_m_reqVec_2_rl[71:8];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791 =
|
|
m_m_reqVec_3_rl[71:8];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791 =
|
|
m_m_reqVec_4_rl[71:8];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791 =
|
|
m_m_reqVec_5_rl[71:8];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791 =
|
|
m_m_reqVec_6_rl[71:8];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1791 =
|
|
m_m_reqVec_7_rl[71:8];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789 =
|
|
m_m_reqVec_0_rl[135:72];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789 =
|
|
m_m_reqVec_1_rl[135:72];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789 =
|
|
m_m_reqVec_2_rl[135:72];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789 =
|
|
m_m_reqVec_3_rl[135:72];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789 =
|
|
m_m_reqVec_4_rl[135:72];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789 =
|
|
m_m_reqVec_5_rl[135:72];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789 =
|
|
m_m_reqVec_6_rl[135:72];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1789 =
|
|
m_m_reqVec_7_rl[135:72];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613 =
|
|
m_m_reqVec_0_rl[137];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613 =
|
|
m_m_reqVec_1_rl[137];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613 =
|
|
m_m_reqVec_2_rl[137];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613 =
|
|
m_m_reqVec_3_rl[137];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613 =
|
|
m_m_reqVec_4_rl[137];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613 =
|
|
m_m_reqVec_5_rl[137];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613 =
|
|
m_m_reqVec_6_rl[137];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1613 =
|
|
m_m_reqVec_7_rl[137];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254 =
|
|
m_m_reqVec_0_rl[137];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254 =
|
|
m_m_reqVec_1_rl[137];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254 =
|
|
m_m_reqVec_2_rl[137];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254 =
|
|
m_m_reqVec_3_rl[137];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254 =
|
|
m_m_reqVec_4_rl[137];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254 =
|
|
m_m_reqVec_5_rl[137];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254 =
|
|
m_m_reqVec_6_rl[137];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d1254 =
|
|
m_m_reqVec_7_rl[137];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712 =
|
|
m_m_reqVec_0_rl[137];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712 =
|
|
m_m_reqVec_1_rl[137];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712 =
|
|
m_m_reqVec_2_rl[137];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712 =
|
|
m_m_reqVec_3_rl[137];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712 =
|
|
m_m_reqVec_4_rl[137];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712 =
|
|
m_m_reqVec_5_rl[137];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712 =
|
|
m_m_reqVec_6_rl[137];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BIT_137_215_m_m_reqV_ETC___d1712 =
|
|
m_m_reqVec_7_rl[137];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785 =
|
|
m_m_reqVec_0_rl[137];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785 =
|
|
m_m_reqVec_1_rl[137];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785 =
|
|
m_m_reqVec_2_rl[137];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785 =
|
|
m_m_reqVec_3_rl[137];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785 =
|
|
m_m_reqVec_4_rl[137];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785 =
|
|
m_m_reqVec_5_rl[137];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785 =
|
|
m_m_reqVec_6_rl[137];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1785 =
|
|
m_m_reqVec_7_rl[137];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574 =
|
|
m_m_reqVec_0_rl[155:153];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574 =
|
|
m_m_reqVec_1_rl[155:153];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574 =
|
|
m_m_reqVec_2_rl[155:153];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574 =
|
|
m_m_reqVec_3_rl[155:153];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574 =
|
|
m_m_reqVec_4_rl[155:153];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574 =
|
|
m_m_reqVec_5_rl[155:153];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574 =
|
|
m_m_reqVec_6_rl[155:153];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1574 =
|
|
m_m_reqVec_7_rl[155:153];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575 =
|
|
m_m_reqVec_0_rl[155:153];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575 =
|
|
m_m_reqVec_1_rl[155:153];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575 =
|
|
m_m_reqVec_2_rl[155:153];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575 =
|
|
m_m_reqVec_3_rl[155:153];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575 =
|
|
m_m_reqVec_4_rl[155:153];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575 =
|
|
m_m_reqVec_5_rl[155:153];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575 =
|
|
m_m_reqVec_6_rl[155:153];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d575 =
|
|
m_m_reqVec_7_rl[155:153];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689 =
|
|
m_m_reqVec_0_rl[155:153];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689 =
|
|
m_m_reqVec_1_rl[155:153];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689 =
|
|
m_m_reqVec_2_rl[155:153];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689 =
|
|
m_m_reqVec_3_rl[155:153];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689 =
|
|
m_m_reqVec_4_rl[155:153];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689 =
|
|
m_m_reqVec_5_rl[155:153];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689 =
|
|
m_m_reqVec_6_rl[155:153];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_155_TO_153_36_m_ETC___d1689 =
|
|
m_m_reqVec_7_rl[155:153];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746 =
|
|
m_m_reqVec_0_rl[155:153];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746 =
|
|
m_m_reqVec_1_rl[155:153];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746 =
|
|
m_m_reqVec_2_rl[155:153];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746 =
|
|
m_m_reqVec_3_rl[155:153];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746 =
|
|
m_m_reqVec_4_rl[155:153];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746 =
|
|
m_m_reqVec_5_rl[155:153];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746 =
|
|
m_m_reqVec_6_rl[155:153];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1746 =
|
|
m_m_reqVec_7_rl[155:153];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491 =
|
|
m_m_reqVec_0_rl[221:158];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491 =
|
|
m_m_reqVec_1_rl[221:158];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491 =
|
|
m_m_reqVec_2_rl[221:158];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491 =
|
|
m_m_reqVec_3_rl[221:158];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491 =
|
|
m_m_reqVec_4_rl[221:158];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491 =
|
|
m_m_reqVec_5_rl[221:158];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491 =
|
|
m_m_reqVec_6_rl[221:158];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_1_whas__3_THEN_m_m_ETC___d491 =
|
|
m_m_reqVec_7_rl[221:158];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570 =
|
|
m_m_reqVec_0_rl[221:158];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570 =
|
|
m_m_reqVec_1_rl[221:158];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570 =
|
|
m_m_reqVec_2_rl[221:158];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570 =
|
|
m_m_reqVec_3_rl[221:158];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570 =
|
|
m_m_reqVec_4_rl[221:158];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570 =
|
|
m_m_reqVec_5_rl[221:158];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570 =
|
|
m_m_reqVec_6_rl[221:158];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1570 =
|
|
m_m_reqVec_7_rl[221:158];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652 =
|
|
m_m_slotVec_0_rl[54:53];
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652 =
|
|
m_m_slotVec_1_rl[54:53];
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652 =
|
|
m_m_slotVec_2_rl[54:53];
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652 =
|
|
m_m_slotVec_3_rl[54:53];
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652 =
|
|
m_m_slotVec_4_rl[54:53];
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652 =
|
|
m_m_slotVec_5_rl[54:53];
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652 =
|
|
m_m_slotVec_6_rl[54:53];
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1652 =
|
|
m_m_slotVec_7_rl[54:53];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687 =
|
|
m_m_reqVec_0_rl[221:158];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687 =
|
|
m_m_reqVec_1_rl[221:158];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687 =
|
|
m_m_reqVec_2_rl[221:158];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687 =
|
|
m_m_reqVec_3_rl[221:158];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687 =
|
|
m_m_reqVec_4_rl[221:158];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687 =
|
|
m_m_reqVec_5_rl[221:158];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687 =
|
|
m_m_reqVec_6_rl[221:158];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_221_TO_158_52_m_ETC___d1687 =
|
|
m_m_reqVec_7_rl[221:158];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_rl or m_m_reqVec_6_rl or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742 =
|
|
m_m_reqVec_0_rl[221:158];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742 =
|
|
m_m_reqVec_1_rl[221:158];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742 =
|
|
m_m_reqVec_2_rl[221:158];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742 =
|
|
m_m_reqVec_3_rl[221:158];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742 =
|
|
m_m_reqVec_4_rl[221:158];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742 =
|
|
m_m_reqVec_5_rl[221:158];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742 =
|
|
m_m_reqVec_6_rl[221:158];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d1742 =
|
|
m_m_reqVec_7_rl[221:158];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_rl or
|
|
m_m_slotVec_1_rl or
|
|
m_m_slotVec_2_rl or
|
|
m_m_slotVec_3_rl or
|
|
m_m_slotVec_4_rl or
|
|
m_m_slotVec_5_rl or m_m_slotVec_6_rl or m_m_slotVec_7_rl)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726 =
|
|
m_m_slotVec_0_rl[54:53];
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726 =
|
|
m_m_slotVec_1_rl[54:53];
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726 =
|
|
m_m_slotVec_2_rl[54:53];
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726 =
|
|
m_m_slotVec_3_rl[54:53];
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726 =
|
|
m_m_slotVec_4_rl[54:53];
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726 =
|
|
m_m_slotVec_5_rl[54:53];
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726 =
|
|
m_m_slotVec_6_rl[54:53];
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_rl_67_BITS_54_TO_53_643__ETC___d1726 =
|
|
m_m_slotVec_7_rl[54:53];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_stateVec_0_lat_0$whas or
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot or
|
|
m_m_slotVec_0_rl or
|
|
m_m_stateVec_1_lat_0$whas or
|
|
m_m_slotVec_1_rl or
|
|
m_m_stateVec_2_lat_0$whas or
|
|
m_m_slotVec_2_rl or
|
|
m_m_stateVec_3_lat_0$whas or
|
|
m_m_slotVec_3_rl or
|
|
m_m_stateVec_4_lat_0$whas or
|
|
m_m_slotVec_4_rl or
|
|
m_m_stateVec_5_lat_0$whas or
|
|
m_m_slotVec_5_rl or
|
|
m_m_stateVec_6_lat_0$whas or
|
|
m_m_slotVec_6_rl or m_m_stateVec_7_lat_0$whas or m_m_slotVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0:
|
|
x__h105130 =
|
|
m_m_stateVec_0_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_0_rl[52:1];
|
|
3'd1:
|
|
x__h105130 =
|
|
m_m_stateVec_1_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_1_rl[52:1];
|
|
3'd2:
|
|
x__h105130 =
|
|
m_m_stateVec_2_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_2_rl[52:1];
|
|
3'd3:
|
|
x__h105130 =
|
|
m_m_stateVec_3_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_3_rl[52:1];
|
|
3'd4:
|
|
x__h105130 =
|
|
m_m_stateVec_4_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_4_rl[52:1];
|
|
3'd5:
|
|
x__h105130 =
|
|
m_m_stateVec_5_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_5_rl[52:1];
|
|
3'd6:
|
|
x__h105130 =
|
|
m_m_stateVec_6_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_6_rl[52:1];
|
|
3'd7:
|
|
x__h105130 =
|
|
m_m_stateVec_7_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_7_rl[52:1];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_stateVec_0_lat_0$whas or
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot or
|
|
m_m_slotVec_0_rl or
|
|
m_m_stateVec_1_lat_0$whas or
|
|
m_m_slotVec_1_rl or
|
|
m_m_stateVec_2_lat_0$whas or
|
|
m_m_slotVec_2_rl or
|
|
m_m_stateVec_3_lat_0$whas or
|
|
m_m_slotVec_3_rl or
|
|
m_m_stateVec_4_lat_0$whas or
|
|
m_m_slotVec_4_rl or
|
|
m_m_stateVec_5_lat_0$whas or
|
|
m_m_slotVec_5_rl or
|
|
m_m_stateVec_6_lat_0$whas or
|
|
m_m_slotVec_6_rl or m_m_stateVec_7_lat_0$whas or m_m_slotVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0:
|
|
x__h104747 =
|
|
m_m_stateVec_0_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_0_rl[57:55];
|
|
3'd1:
|
|
x__h104747 =
|
|
m_m_stateVec_1_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_1_rl[57:55];
|
|
3'd2:
|
|
x__h104747 =
|
|
m_m_stateVec_2_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_2_rl[57:55];
|
|
3'd3:
|
|
x__h104747 =
|
|
m_m_stateVec_3_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_3_rl[57:55];
|
|
3'd4:
|
|
x__h104747 =
|
|
m_m_stateVec_4_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_4_rl[57:55];
|
|
3'd5:
|
|
x__h104747 =
|
|
m_m_stateVec_5_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_5_rl[57:55];
|
|
3'd6:
|
|
x__h104747 =
|
|
m_m_stateVec_6_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_6_rl[57:55];
|
|
3'd7:
|
|
x__h104747 =
|
|
m_m_stateVec_7_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_7_rl[57:55];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_stateVec_0_lat_0$whas or
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot or
|
|
m_m_slotVec_0_rl or
|
|
m_m_stateVec_1_lat_0$whas or
|
|
m_m_slotVec_1_rl or
|
|
m_m_stateVec_2_lat_0$whas or
|
|
m_m_slotVec_2_rl or
|
|
m_m_stateVec_3_lat_0$whas or
|
|
m_m_slotVec_3_rl or
|
|
m_m_stateVec_4_lat_0$whas or
|
|
m_m_slotVec_4_rl or
|
|
m_m_stateVec_5_lat_0$whas or
|
|
m_m_slotVec_5_rl or
|
|
m_m_stateVec_6_lat_0$whas or
|
|
m_m_slotVec_6_rl or m_m_stateVec_7_lat_0$whas or m_m_slotVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 =
|
|
m_m_stateVec_0_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 =
|
|
m_m_stateVec_1_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 =
|
|
m_m_stateVec_2_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 =
|
|
m_m_stateVec_3_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 =
|
|
m_m_stateVec_4_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 =
|
|
m_m_stateVec_5_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 =
|
|
m_m_stateVec_6_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1876 =
|
|
m_m_stateVec_7_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_stateVec_0_lat_0$whas or
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot or
|
|
m_m_slotVec_0_rl or
|
|
m_m_stateVec_1_lat_0$whas or
|
|
m_m_slotVec_1_rl or
|
|
m_m_stateVec_2_lat_0$whas or
|
|
m_m_slotVec_2_rl or
|
|
m_m_stateVec_3_lat_0$whas or
|
|
m_m_slotVec_3_rl or
|
|
m_m_stateVec_4_lat_0$whas or
|
|
m_m_slotVec_4_rl or
|
|
m_m_stateVec_5_lat_0$whas or
|
|
m_m_slotVec_5_rl or
|
|
m_m_stateVec_6_lat_0$whas or
|
|
m_m_slotVec_6_rl or m_m_stateVec_7_lat_0$whas or m_m_slotVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840 =
|
|
m_m_stateVec_0_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_0_rl[54:53];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840 =
|
|
m_m_stateVec_1_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_1_rl[54:53];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840 =
|
|
m_m_stateVec_2_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_2_rl[54:53];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840 =
|
|
m_m_stateVec_3_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_3_rl[54:53];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840 =
|
|
m_m_stateVec_4_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_4_rl[54:53];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840 =
|
|
m_m_stateVec_5_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_5_rl[54:53];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840 =
|
|
m_m_stateVec_6_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_6_rl[54:53];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_slotVec_0_lat_0_whas__65_THEN_m_ETC___d1840 =
|
|
m_m_stateVec_7_lat_0$whas ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_7_rl[54:53];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_dataValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
227'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
227'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
227'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
227'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
227'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
227'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
227'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
227'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 3'bxxx /* unspecified value */ ,
|
|
2'bxx /* unspecified value */ ,
|
|
52'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
1'd0 };
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_dataValidVec_0_rl$EN)
|
|
m_m_dataValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_0_rl$D_IN;
|
|
if (m_m_dataValidVec_1_rl$EN)
|
|
m_m_dataValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_1_rl$D_IN;
|
|
if (m_m_dataValidVec_2_rl$EN)
|
|
m_m_dataValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_2_rl$D_IN;
|
|
if (m_m_dataValidVec_3_rl$EN)
|
|
m_m_dataValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_3_rl$D_IN;
|
|
if (m_m_dataValidVec_4_rl$EN)
|
|
m_m_dataValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_4_rl$D_IN;
|
|
if (m_m_dataValidVec_5_rl$EN)
|
|
m_m_dataValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_5_rl$D_IN;
|
|
if (m_m_dataValidVec_6_rl$EN)
|
|
m_m_dataValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_6_rl$D_IN;
|
|
if (m_m_dataValidVec_7_rl$EN)
|
|
m_m_dataValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_7_rl$D_IN;
|
|
if (m_m_initIdx$EN)
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY m_m_initIdx$D_IN;
|
|
if (m_m_inited$EN)
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY m_m_inited$D_IN;
|
|
if (m_m_reqVec_0_rl$EN)
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_0_rl$D_IN;
|
|
if (m_m_reqVec_1_rl$EN)
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_1_rl$D_IN;
|
|
if (m_m_reqVec_2_rl$EN)
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_2_rl$D_IN;
|
|
if (m_m_reqVec_3_rl$EN)
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_3_rl$D_IN;
|
|
if (m_m_reqVec_4_rl$EN)
|
|
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_4_rl$D_IN;
|
|
if (m_m_reqVec_5_rl$EN)
|
|
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_5_rl$D_IN;
|
|
if (m_m_reqVec_6_rl$EN)
|
|
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_6_rl$D_IN;
|
|
if (m_m_reqVec_7_rl$EN)
|
|
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_7_rl$D_IN;
|
|
if (m_m_slotVec_0_rl$EN)
|
|
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_0_rl$D_IN;
|
|
if (m_m_slotVec_1_rl$EN)
|
|
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_1_rl$D_IN;
|
|
if (m_m_slotVec_2_rl$EN)
|
|
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_2_rl$D_IN;
|
|
if (m_m_slotVec_3_rl$EN)
|
|
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_3_rl$D_IN;
|
|
if (m_m_slotVec_4_rl$EN)
|
|
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_4_rl$D_IN;
|
|
if (m_m_slotVec_5_rl$EN)
|
|
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_5_rl$D_IN;
|
|
if (m_m_slotVec_6_rl$EN)
|
|
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_6_rl$D_IN;
|
|
if (m_m_slotVec_7_rl$EN)
|
|
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_7_rl$D_IN;
|
|
if (m_m_stateVec_0_rl$EN)
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_0_rl$D_IN;
|
|
if (m_m_stateVec_1_rl$EN)
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_1_rl$D_IN;
|
|
if (m_m_stateVec_2_rl$EN)
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_2_rl$D_IN;
|
|
if (m_m_stateVec_3_rl$EN)
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_3_rl$D_IN;
|
|
if (m_m_stateVec_4_rl$EN)
|
|
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_4_rl$D_IN;
|
|
if (m_m_stateVec_5_rl$EN)
|
|
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_5_rl$D_IN;
|
|
if (m_m_stateVec_6_rl$EN)
|
|
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_6_rl$D_IN;
|
|
if (m_m_stateVec_7_rl$EN)
|
|
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_7_rl$D_IN;
|
|
if (m_m_succValidVec_0_rl$EN)
|
|
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_0_rl$D_IN;
|
|
if (m_m_succValidVec_1_rl$EN)
|
|
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_1_rl$D_IN;
|
|
if (m_m_succValidVec_2_rl$EN)
|
|
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_2_rl$D_IN;
|
|
if (m_m_succValidVec_3_rl$EN)
|
|
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_3_rl$D_IN;
|
|
if (m_m_succValidVec_4_rl$EN)
|
|
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_4_rl$D_IN;
|
|
if (m_m_succValidVec_5_rl$EN)
|
|
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_5_rl$D_IN;
|
|
if (m_m_succValidVec_6_rl$EN)
|
|
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_6_rl$D_IN;
|
|
if (m_m_succValidVec_7_rl$EN)
|
|
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_7_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_dataValidVec_0_rl = 1'h0;
|
|
m_m_dataValidVec_1_rl = 1'h0;
|
|
m_m_dataValidVec_2_rl = 1'h0;
|
|
m_m_dataValidVec_3_rl = 1'h0;
|
|
m_m_dataValidVec_4_rl = 1'h0;
|
|
m_m_dataValidVec_5_rl = 1'h0;
|
|
m_m_dataValidVec_6_rl = 1'h0;
|
|
m_m_dataValidVec_7_rl = 1'h0;
|
|
m_m_initIdx = 3'h2;
|
|
m_m_inited = 1'h0;
|
|
m_m_reqVec_0_rl =
|
|
227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl =
|
|
227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl =
|
|
227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl =
|
|
227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_4_rl =
|
|
227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_5_rl =
|
|
227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_6_rl =
|
|
227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_7_rl =
|
|
227'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_slotVec_0_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_1_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_2_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_3_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_4_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_5_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_6_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_7_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_stateVec_0_rl = 3'h2;
|
|
m_m_stateVec_1_rl = 3'h2;
|
|
m_m_stateVec_2_rl = 3'h2;
|
|
m_m_stateVec_3_rl = 3'h2;
|
|
m_m_stateVec_4_rl = 3'h2;
|
|
m_m_stateVec_5_rl = 3'h2;
|
|
m_m_stateVec_6_rl = 3'h2;
|
|
m_m_stateVec_7_rl = 3'h2;
|
|
m_m_succValidVec_0_rl = 1'h0;
|
|
m_m_succValidVec_1_rl = 1'h0;
|
|
m_m_succValidVec_2_rl = 1'h0;
|
|
m_m_succValidVec_3_rl = 1'h0;
|
|
m_m_succValidVec_4_rl = 1'h0;
|
|
m_m_succValidVec_5_rl = 1'h0;
|
|
m_m_succValidVec_6_rl = 1'h0;
|
|
m_m_succValidVec_7_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_state == 3'd0)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkDCRqMshrWrapper
|
|
|