196 lines
5.1 KiB
Verilog
196 lines
5.1 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:24:13 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// pred_0_pred O 25
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// RDY_pred_0_pred O 1 const
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// pred_1_pred O 25
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// RDY_pred_1_pred O 1 const
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// RDY_update O 1 const
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// RDY_flush O 1 const
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// flush_done O 1 const
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// RDY_flush_done O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// pred_0_pred_pc I 129
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// pred_1_pred_pc I 129
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// update_pc I 129
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// update_taken I 1
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// update_train I 24
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// update_mispred I 1
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// EN_update I 1
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// EN_flush I 1 unused
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// EN_pred_0_pred I 1
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// EN_pred_1_pred I 1
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//
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// Combinational paths from inputs to outputs:
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// EN_pred_0_pred -> pred_1_pred
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDirPredictor(CLK,
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RST_N,
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pred_0_pred_pc,
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EN_pred_0_pred,
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pred_0_pred,
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RDY_pred_0_pred,
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pred_1_pred_pc,
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EN_pred_1_pred,
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pred_1_pred,
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RDY_pred_1_pred,
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update_pc,
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update_taken,
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update_train,
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update_mispred,
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EN_update,
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RDY_update,
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EN_flush,
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RDY_flush,
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flush_done,
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RDY_flush_done);
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input CLK;
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input RST_N;
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// actionvalue method pred_0_pred
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input [128 : 0] pred_0_pred_pc;
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input EN_pred_0_pred;
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output [24 : 0] pred_0_pred;
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output RDY_pred_0_pred;
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// actionvalue method pred_1_pred
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input [128 : 0] pred_1_pred_pc;
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input EN_pred_1_pred;
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output [24 : 0] pred_1_pred;
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output RDY_pred_1_pred;
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// action method update
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input [128 : 0] update_pc;
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input update_taken;
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input [23 : 0] update_train;
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input update_mispred;
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input EN_update;
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output RDY_update;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// signals for module outputs
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wire [24 : 0] pred_0_pred, pred_1_pred;
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wire RDY_flush,
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RDY_flush_done,
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RDY_pred_0_pred,
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RDY_pred_1_pred,
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RDY_update,
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flush_done;
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// ports of submodule m
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wire [128 : 0] m$pred_0_pred_pc, m$pred_1_pred_pc, m$update_pc;
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wire [24 : 0] m$pred_0_pred, m$pred_1_pred;
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wire [23 : 0] m$update_train;
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wire m$EN_flush,
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m$EN_pred_0_pred,
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m$EN_pred_1_pred,
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m$EN_update,
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m$flush_done,
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m$update_mispred,
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m$update_taken;
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// rule scheduling signals
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wire CAN_FIRE_flush,
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CAN_FIRE_pred_0_pred,
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CAN_FIRE_pred_1_pred,
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CAN_FIRE_update,
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WILL_FIRE_flush,
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WILL_FIRE_pred_0_pred,
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WILL_FIRE_pred_1_pred,
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WILL_FIRE_update;
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// actionvalue method pred_0_pred
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assign pred_0_pred = m$pred_0_pred ;
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assign RDY_pred_0_pred = 1'd1 ;
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assign CAN_FIRE_pred_0_pred = 1'd1 ;
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assign WILL_FIRE_pred_0_pred = EN_pred_0_pred ;
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// actionvalue method pred_1_pred
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assign pred_1_pred = m$pred_1_pred ;
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assign RDY_pred_1_pred = 1'd1 ;
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assign CAN_FIRE_pred_1_pred = 1'd1 ;
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assign WILL_FIRE_pred_1_pred = EN_pred_1_pred ;
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// action method update
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assign RDY_update = 1'd1 ;
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assign CAN_FIRE_update = 1'd1 ;
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assign WILL_FIRE_update = EN_update ;
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// action method flush
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assign RDY_flush = 1'd1 ;
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assign CAN_FIRE_flush = 1'd1 ;
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assign WILL_FIRE_flush = EN_flush ;
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// value method flush_done
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assign flush_done = m$flush_done ;
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assign RDY_flush_done = 1'd1 ;
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// submodule m
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mkTourPred m(.CLK(CLK),
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.RST_N(RST_N),
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.pred_0_pred_pc(m$pred_0_pred_pc),
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.pred_1_pred_pc(m$pred_1_pred_pc),
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.update_mispred(m$update_mispred),
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.update_pc(m$update_pc),
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.update_taken(m$update_taken),
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.update_train(m$update_train),
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.EN_pred_0_pred(m$EN_pred_0_pred),
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.EN_pred_1_pred(m$EN_pred_1_pred),
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.EN_update(m$EN_update),
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.EN_flush(m$EN_flush),
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.pred_0_pred(m$pred_0_pred),
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.RDY_pred_0_pred(),
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.pred_1_pred(m$pred_1_pred),
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.RDY_pred_1_pred(),
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.RDY_update(),
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.RDY_flush(),
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.flush_done(m$flush_done),
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.RDY_flush_done());
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// submodule m
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assign m$pred_0_pred_pc = pred_0_pred_pc ;
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assign m$pred_1_pred_pc = pred_1_pred_pc ;
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assign m$update_mispred = update_mispred ;
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assign m$update_pc = update_pc ;
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assign m$update_taken = update_taken ;
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assign m$update_train = update_train ;
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assign m$EN_pred_0_pred = EN_pred_0_pred ;
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assign m$EN_pred_1_pred = EN_pred_1_pred ;
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assign m$EN_update = EN_update ;
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assign m$EN_flush = EN_flush ;
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endmodule // mkDirPredictor
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