5645 lines
216 KiB
Verilog
5645 lines
216 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:22:54 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_request_put O 1
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// response_get O 69 reg
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// RDY_response_get O 1 reg
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// CLK I 1 clock
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// RST_N I 1 reset
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// request_put I 67 reg
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// EN_request_put I 1
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// EN_response_get I 1
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//
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// Combinational paths from inputs to outputs:
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// EN_response_get -> RDY_request_put
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDoubleSqrt(CLK,
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RST_N,
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request_put,
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EN_request_put,
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RDY_request_put,
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EN_response_get,
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response_get,
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RDY_response_get);
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input CLK;
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input RST_N;
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// action method request_put
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input [66 : 0] request_put;
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input EN_request_put;
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output RDY_request_put;
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// actionvalue method response_get
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input EN_response_get;
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output [68 : 0] response_get;
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output RDY_response_get;
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// signals for module outputs
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wire [68 : 0] response_get;
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wire RDY_request_put, RDY_response_get;
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// ports of submodule fpu_fOperand_S0
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wire [66 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT;
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wire fpu_fOperand_S0$CLR,
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fpu_fOperand_S0$DEQ,
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fpu_fOperand_S0$EMPTY_N,
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fpu_fOperand_S0$ENQ,
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fpu_fOperand_S0$FULL_N;
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// ports of submodule fpu_fResult_S5
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wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT;
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wire fpu_fResult_S5$CLR,
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fpu_fResult_S5$DEQ,
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fpu_fResult_S5$EMPTY_N,
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fpu_fResult_S5$ENQ,
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fpu_fResult_S5$FULL_N;
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// ports of submodule fpu_fState_S1
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wire [194 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT;
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wire fpu_fState_S1$CLR,
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fpu_fState_S1$DEQ,
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fpu_fState_S1$EMPTY_N,
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fpu_fState_S1$ENQ,
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fpu_fState_S1$FULL_N;
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// ports of submodule fpu_fState_S2
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wire [136 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT;
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wire fpu_fState_S2$CLR,
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fpu_fState_S2$DEQ,
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fpu_fState_S2$EMPTY_N,
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fpu_fState_S2$ENQ,
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fpu_fState_S2$FULL_N;
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// ports of submodule fpu_fState_S3
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wire [195 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT;
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wire fpu_fState_S3$CLR,
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fpu_fState_S3$DEQ,
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fpu_fState_S3$EMPTY_N,
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fpu_fState_S3$ENQ,
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fpu_fState_S3$FULL_N;
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// ports of submodule fpu_fState_S4
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wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT;
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wire fpu_fState_S4$CLR,
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fpu_fState_S4$DEQ,
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fpu_fState_S4$EMPTY_N,
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fpu_fState_S4$ENQ,
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fpu_fState_S4$FULL_N;
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// ports of submodule int_sqrt_fFirst
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wire [464 : 0] int_sqrt_fFirst$D_IN, int_sqrt_fFirst$D_OUT;
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wire int_sqrt_fFirst$CLR,
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int_sqrt_fFirst$DEQ,
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int_sqrt_fFirst$EMPTY_N,
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int_sqrt_fFirst$ENQ,
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int_sqrt_fFirst$FULL_N;
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// ports of submodule int_sqrt_fNext_0
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wire [464 : 0] int_sqrt_fNext_0$D_IN, int_sqrt_fNext_0$D_OUT;
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wire int_sqrt_fNext_0$CLR,
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int_sqrt_fNext_0$DEQ,
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int_sqrt_fNext_0$EMPTY_N,
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int_sqrt_fNext_0$ENQ,
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int_sqrt_fNext_0$FULL_N;
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// ports of submodule int_sqrt_fNext_1
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wire [464 : 0] int_sqrt_fNext_1$D_IN, int_sqrt_fNext_1$D_OUT;
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wire int_sqrt_fNext_1$CLR,
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int_sqrt_fNext_1$DEQ,
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int_sqrt_fNext_1$EMPTY_N,
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int_sqrt_fNext_1$ENQ,
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int_sqrt_fNext_1$FULL_N;
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// ports of submodule int_sqrt_fNext_10
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wire [464 : 0] int_sqrt_fNext_10$D_IN, int_sqrt_fNext_10$D_OUT;
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wire int_sqrt_fNext_10$CLR,
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int_sqrt_fNext_10$DEQ,
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int_sqrt_fNext_10$EMPTY_N,
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int_sqrt_fNext_10$ENQ,
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int_sqrt_fNext_10$FULL_N;
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// ports of submodule int_sqrt_fNext_11
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wire [464 : 0] int_sqrt_fNext_11$D_IN, int_sqrt_fNext_11$D_OUT;
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wire int_sqrt_fNext_11$CLR,
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int_sqrt_fNext_11$DEQ,
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int_sqrt_fNext_11$EMPTY_N,
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int_sqrt_fNext_11$ENQ,
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int_sqrt_fNext_11$FULL_N;
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// ports of submodule int_sqrt_fNext_12
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wire [464 : 0] int_sqrt_fNext_12$D_IN, int_sqrt_fNext_12$D_OUT;
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wire int_sqrt_fNext_12$CLR,
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int_sqrt_fNext_12$DEQ,
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int_sqrt_fNext_12$EMPTY_N,
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int_sqrt_fNext_12$ENQ,
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int_sqrt_fNext_12$FULL_N;
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// ports of submodule int_sqrt_fNext_13
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wire [464 : 0] int_sqrt_fNext_13$D_IN, int_sqrt_fNext_13$D_OUT;
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wire int_sqrt_fNext_13$CLR,
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int_sqrt_fNext_13$DEQ,
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int_sqrt_fNext_13$EMPTY_N,
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int_sqrt_fNext_13$ENQ,
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int_sqrt_fNext_13$FULL_N;
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// ports of submodule int_sqrt_fNext_14
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wire [464 : 0] int_sqrt_fNext_14$D_IN, int_sqrt_fNext_14$D_OUT;
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wire int_sqrt_fNext_14$CLR,
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int_sqrt_fNext_14$DEQ,
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int_sqrt_fNext_14$EMPTY_N,
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int_sqrt_fNext_14$ENQ,
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int_sqrt_fNext_14$FULL_N;
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// ports of submodule int_sqrt_fNext_15
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wire [464 : 0] int_sqrt_fNext_15$D_IN, int_sqrt_fNext_15$D_OUT;
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wire int_sqrt_fNext_15$CLR,
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int_sqrt_fNext_15$DEQ,
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int_sqrt_fNext_15$EMPTY_N,
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int_sqrt_fNext_15$ENQ,
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int_sqrt_fNext_15$FULL_N;
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// ports of submodule int_sqrt_fNext_16
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wire [464 : 0] int_sqrt_fNext_16$D_IN, int_sqrt_fNext_16$D_OUT;
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wire int_sqrt_fNext_16$CLR,
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int_sqrt_fNext_16$DEQ,
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int_sqrt_fNext_16$EMPTY_N,
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int_sqrt_fNext_16$ENQ,
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int_sqrt_fNext_16$FULL_N;
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// ports of submodule int_sqrt_fNext_17
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wire [464 : 0] int_sqrt_fNext_17$D_IN, int_sqrt_fNext_17$D_OUT;
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wire int_sqrt_fNext_17$CLR,
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int_sqrt_fNext_17$DEQ,
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int_sqrt_fNext_17$EMPTY_N,
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int_sqrt_fNext_17$ENQ,
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int_sqrt_fNext_17$FULL_N;
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// ports of submodule int_sqrt_fNext_18
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wire [464 : 0] int_sqrt_fNext_18$D_IN, int_sqrt_fNext_18$D_OUT;
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wire int_sqrt_fNext_18$CLR,
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int_sqrt_fNext_18$DEQ,
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int_sqrt_fNext_18$EMPTY_N,
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int_sqrt_fNext_18$ENQ,
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int_sqrt_fNext_18$FULL_N;
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// ports of submodule int_sqrt_fNext_19
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wire [464 : 0] int_sqrt_fNext_19$D_IN, int_sqrt_fNext_19$D_OUT;
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wire int_sqrt_fNext_19$CLR,
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int_sqrt_fNext_19$DEQ,
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int_sqrt_fNext_19$EMPTY_N,
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int_sqrt_fNext_19$ENQ,
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int_sqrt_fNext_19$FULL_N;
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// ports of submodule int_sqrt_fNext_2
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wire [464 : 0] int_sqrt_fNext_2$D_IN, int_sqrt_fNext_2$D_OUT;
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wire int_sqrt_fNext_2$CLR,
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int_sqrt_fNext_2$DEQ,
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int_sqrt_fNext_2$EMPTY_N,
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int_sqrt_fNext_2$ENQ,
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int_sqrt_fNext_2$FULL_N;
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// ports of submodule int_sqrt_fNext_20
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wire [464 : 0] int_sqrt_fNext_20$D_IN, int_sqrt_fNext_20$D_OUT;
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wire int_sqrt_fNext_20$CLR,
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int_sqrt_fNext_20$DEQ,
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int_sqrt_fNext_20$EMPTY_N,
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int_sqrt_fNext_20$ENQ,
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int_sqrt_fNext_20$FULL_N;
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// ports of submodule int_sqrt_fNext_21
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wire [464 : 0] int_sqrt_fNext_21$D_IN, int_sqrt_fNext_21$D_OUT;
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wire int_sqrt_fNext_21$CLR,
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int_sqrt_fNext_21$DEQ,
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int_sqrt_fNext_21$EMPTY_N,
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int_sqrt_fNext_21$ENQ,
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int_sqrt_fNext_21$FULL_N;
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// ports of submodule int_sqrt_fNext_22
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wire [464 : 0] int_sqrt_fNext_22$D_IN, int_sqrt_fNext_22$D_OUT;
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wire int_sqrt_fNext_22$CLR,
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int_sqrt_fNext_22$DEQ,
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int_sqrt_fNext_22$EMPTY_N,
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int_sqrt_fNext_22$ENQ,
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int_sqrt_fNext_22$FULL_N;
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// ports of submodule int_sqrt_fNext_23
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wire [464 : 0] int_sqrt_fNext_23$D_IN, int_sqrt_fNext_23$D_OUT;
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wire int_sqrt_fNext_23$CLR,
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int_sqrt_fNext_23$DEQ,
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int_sqrt_fNext_23$EMPTY_N,
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int_sqrt_fNext_23$ENQ,
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int_sqrt_fNext_23$FULL_N;
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// ports of submodule int_sqrt_fNext_24
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wire [464 : 0] int_sqrt_fNext_24$D_IN, int_sqrt_fNext_24$D_OUT;
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wire int_sqrt_fNext_24$CLR,
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int_sqrt_fNext_24$DEQ,
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int_sqrt_fNext_24$EMPTY_N,
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int_sqrt_fNext_24$ENQ,
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int_sqrt_fNext_24$FULL_N;
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// ports of submodule int_sqrt_fNext_25
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wire [464 : 0] int_sqrt_fNext_25$D_IN, int_sqrt_fNext_25$D_OUT;
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wire int_sqrt_fNext_25$CLR,
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int_sqrt_fNext_25$DEQ,
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int_sqrt_fNext_25$EMPTY_N,
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int_sqrt_fNext_25$ENQ,
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int_sqrt_fNext_25$FULL_N;
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// ports of submodule int_sqrt_fNext_26
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wire [464 : 0] int_sqrt_fNext_26$D_IN, int_sqrt_fNext_26$D_OUT;
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wire int_sqrt_fNext_26$CLR,
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int_sqrt_fNext_26$DEQ,
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int_sqrt_fNext_26$EMPTY_N,
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int_sqrt_fNext_26$ENQ,
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int_sqrt_fNext_26$FULL_N;
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// ports of submodule int_sqrt_fNext_27
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wire [464 : 0] int_sqrt_fNext_27$D_IN, int_sqrt_fNext_27$D_OUT;
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wire int_sqrt_fNext_27$CLR,
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int_sqrt_fNext_27$DEQ,
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int_sqrt_fNext_27$EMPTY_N,
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int_sqrt_fNext_27$ENQ,
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int_sqrt_fNext_27$FULL_N;
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// ports of submodule int_sqrt_fNext_28
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wire [464 : 0] int_sqrt_fNext_28$D_IN, int_sqrt_fNext_28$D_OUT;
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wire int_sqrt_fNext_28$CLR,
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int_sqrt_fNext_28$DEQ,
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int_sqrt_fNext_28$EMPTY_N,
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int_sqrt_fNext_28$ENQ,
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int_sqrt_fNext_28$FULL_N;
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// ports of submodule int_sqrt_fNext_29
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wire [464 : 0] int_sqrt_fNext_29$D_IN, int_sqrt_fNext_29$D_OUT;
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wire int_sqrt_fNext_29$CLR,
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int_sqrt_fNext_29$DEQ,
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int_sqrt_fNext_29$EMPTY_N,
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int_sqrt_fNext_29$ENQ,
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int_sqrt_fNext_29$FULL_N;
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// ports of submodule int_sqrt_fNext_3
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wire [464 : 0] int_sqrt_fNext_3$D_IN, int_sqrt_fNext_3$D_OUT;
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wire int_sqrt_fNext_3$CLR,
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int_sqrt_fNext_3$DEQ,
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int_sqrt_fNext_3$EMPTY_N,
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int_sqrt_fNext_3$ENQ,
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int_sqrt_fNext_3$FULL_N;
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// ports of submodule int_sqrt_fNext_30
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wire [464 : 0] int_sqrt_fNext_30$D_IN, int_sqrt_fNext_30$D_OUT;
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wire int_sqrt_fNext_30$CLR,
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int_sqrt_fNext_30$DEQ,
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int_sqrt_fNext_30$EMPTY_N,
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int_sqrt_fNext_30$ENQ,
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int_sqrt_fNext_30$FULL_N;
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// ports of submodule int_sqrt_fNext_31
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wire [464 : 0] int_sqrt_fNext_31$D_IN, int_sqrt_fNext_31$D_OUT;
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wire int_sqrt_fNext_31$CLR,
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int_sqrt_fNext_31$DEQ,
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int_sqrt_fNext_31$EMPTY_N,
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int_sqrt_fNext_31$ENQ,
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int_sqrt_fNext_31$FULL_N;
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// ports of submodule int_sqrt_fNext_32
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wire [464 : 0] int_sqrt_fNext_32$D_IN, int_sqrt_fNext_32$D_OUT;
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wire int_sqrt_fNext_32$CLR,
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int_sqrt_fNext_32$DEQ,
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int_sqrt_fNext_32$EMPTY_N,
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int_sqrt_fNext_32$ENQ,
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int_sqrt_fNext_32$FULL_N;
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// ports of submodule int_sqrt_fNext_33
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wire [464 : 0] int_sqrt_fNext_33$D_IN, int_sqrt_fNext_33$D_OUT;
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wire int_sqrt_fNext_33$CLR,
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int_sqrt_fNext_33$DEQ,
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int_sqrt_fNext_33$EMPTY_N,
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int_sqrt_fNext_33$ENQ,
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int_sqrt_fNext_33$FULL_N;
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// ports of submodule int_sqrt_fNext_34
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wire [464 : 0] int_sqrt_fNext_34$D_IN, int_sqrt_fNext_34$D_OUT;
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wire int_sqrt_fNext_34$CLR,
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int_sqrt_fNext_34$DEQ,
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int_sqrt_fNext_34$EMPTY_N,
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int_sqrt_fNext_34$ENQ,
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int_sqrt_fNext_34$FULL_N;
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// ports of submodule int_sqrt_fNext_35
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wire [464 : 0] int_sqrt_fNext_35$D_IN, int_sqrt_fNext_35$D_OUT;
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wire int_sqrt_fNext_35$CLR,
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int_sqrt_fNext_35$DEQ,
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int_sqrt_fNext_35$EMPTY_N,
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int_sqrt_fNext_35$ENQ,
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int_sqrt_fNext_35$FULL_N;
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// ports of submodule int_sqrt_fNext_36
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wire [464 : 0] int_sqrt_fNext_36$D_IN, int_sqrt_fNext_36$D_OUT;
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wire int_sqrt_fNext_36$CLR,
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int_sqrt_fNext_36$DEQ,
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int_sqrt_fNext_36$EMPTY_N,
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int_sqrt_fNext_36$ENQ,
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int_sqrt_fNext_36$FULL_N;
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// ports of submodule int_sqrt_fNext_37
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wire [464 : 0] int_sqrt_fNext_37$D_IN, int_sqrt_fNext_37$D_OUT;
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wire int_sqrt_fNext_37$CLR,
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int_sqrt_fNext_37$DEQ,
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int_sqrt_fNext_37$EMPTY_N,
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int_sqrt_fNext_37$ENQ,
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int_sqrt_fNext_37$FULL_N;
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// ports of submodule int_sqrt_fNext_38
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wire [464 : 0] int_sqrt_fNext_38$D_IN, int_sqrt_fNext_38$D_OUT;
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wire int_sqrt_fNext_38$CLR,
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int_sqrt_fNext_38$DEQ,
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int_sqrt_fNext_38$EMPTY_N,
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int_sqrt_fNext_38$ENQ,
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int_sqrt_fNext_38$FULL_N;
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// ports of submodule int_sqrt_fNext_39
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wire [464 : 0] int_sqrt_fNext_39$D_IN, int_sqrt_fNext_39$D_OUT;
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wire int_sqrt_fNext_39$CLR,
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int_sqrt_fNext_39$DEQ,
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int_sqrt_fNext_39$EMPTY_N,
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int_sqrt_fNext_39$ENQ,
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int_sqrt_fNext_39$FULL_N;
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// ports of submodule int_sqrt_fNext_4
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wire [464 : 0] int_sqrt_fNext_4$D_IN, int_sqrt_fNext_4$D_OUT;
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wire int_sqrt_fNext_4$CLR,
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int_sqrt_fNext_4$DEQ,
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int_sqrt_fNext_4$EMPTY_N,
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int_sqrt_fNext_4$ENQ,
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int_sqrt_fNext_4$FULL_N;
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// ports of submodule int_sqrt_fNext_40
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wire [464 : 0] int_sqrt_fNext_40$D_IN, int_sqrt_fNext_40$D_OUT;
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wire int_sqrt_fNext_40$CLR,
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int_sqrt_fNext_40$DEQ,
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int_sqrt_fNext_40$EMPTY_N,
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int_sqrt_fNext_40$ENQ,
|
|
int_sqrt_fNext_40$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_41
|
|
wire [464 : 0] int_sqrt_fNext_41$D_IN, int_sqrt_fNext_41$D_OUT;
|
|
wire int_sqrt_fNext_41$CLR,
|
|
int_sqrt_fNext_41$DEQ,
|
|
int_sqrt_fNext_41$EMPTY_N,
|
|
int_sqrt_fNext_41$ENQ,
|
|
int_sqrt_fNext_41$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_42
|
|
wire [464 : 0] int_sqrt_fNext_42$D_IN, int_sqrt_fNext_42$D_OUT;
|
|
wire int_sqrt_fNext_42$CLR,
|
|
int_sqrt_fNext_42$DEQ,
|
|
int_sqrt_fNext_42$EMPTY_N,
|
|
int_sqrt_fNext_42$ENQ,
|
|
int_sqrt_fNext_42$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_43
|
|
wire [464 : 0] int_sqrt_fNext_43$D_IN, int_sqrt_fNext_43$D_OUT;
|
|
wire int_sqrt_fNext_43$CLR,
|
|
int_sqrt_fNext_43$DEQ,
|
|
int_sqrt_fNext_43$EMPTY_N,
|
|
int_sqrt_fNext_43$ENQ,
|
|
int_sqrt_fNext_43$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_44
|
|
wire [464 : 0] int_sqrt_fNext_44$D_IN, int_sqrt_fNext_44$D_OUT;
|
|
wire int_sqrt_fNext_44$CLR,
|
|
int_sqrt_fNext_44$DEQ,
|
|
int_sqrt_fNext_44$EMPTY_N,
|
|
int_sqrt_fNext_44$ENQ,
|
|
int_sqrt_fNext_44$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_45
|
|
wire [464 : 0] int_sqrt_fNext_45$D_IN, int_sqrt_fNext_45$D_OUT;
|
|
wire int_sqrt_fNext_45$CLR,
|
|
int_sqrt_fNext_45$DEQ,
|
|
int_sqrt_fNext_45$EMPTY_N,
|
|
int_sqrt_fNext_45$ENQ,
|
|
int_sqrt_fNext_45$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_46
|
|
wire [464 : 0] int_sqrt_fNext_46$D_IN, int_sqrt_fNext_46$D_OUT;
|
|
wire int_sqrt_fNext_46$CLR,
|
|
int_sqrt_fNext_46$DEQ,
|
|
int_sqrt_fNext_46$EMPTY_N,
|
|
int_sqrt_fNext_46$ENQ,
|
|
int_sqrt_fNext_46$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_47
|
|
wire [464 : 0] int_sqrt_fNext_47$D_IN, int_sqrt_fNext_47$D_OUT;
|
|
wire int_sqrt_fNext_47$CLR,
|
|
int_sqrt_fNext_47$DEQ,
|
|
int_sqrt_fNext_47$EMPTY_N,
|
|
int_sqrt_fNext_47$ENQ,
|
|
int_sqrt_fNext_47$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_48
|
|
wire [464 : 0] int_sqrt_fNext_48$D_IN, int_sqrt_fNext_48$D_OUT;
|
|
wire int_sqrt_fNext_48$CLR,
|
|
int_sqrt_fNext_48$DEQ,
|
|
int_sqrt_fNext_48$EMPTY_N,
|
|
int_sqrt_fNext_48$ENQ,
|
|
int_sqrt_fNext_48$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_49
|
|
wire [464 : 0] int_sqrt_fNext_49$D_IN, int_sqrt_fNext_49$D_OUT;
|
|
wire int_sqrt_fNext_49$CLR,
|
|
int_sqrt_fNext_49$DEQ,
|
|
int_sqrt_fNext_49$EMPTY_N,
|
|
int_sqrt_fNext_49$ENQ,
|
|
int_sqrt_fNext_49$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_5
|
|
wire [464 : 0] int_sqrt_fNext_5$D_IN, int_sqrt_fNext_5$D_OUT;
|
|
wire int_sqrt_fNext_5$CLR,
|
|
int_sqrt_fNext_5$DEQ,
|
|
int_sqrt_fNext_5$EMPTY_N,
|
|
int_sqrt_fNext_5$ENQ,
|
|
int_sqrt_fNext_5$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_50
|
|
wire [464 : 0] int_sqrt_fNext_50$D_IN, int_sqrt_fNext_50$D_OUT;
|
|
wire int_sqrt_fNext_50$CLR,
|
|
int_sqrt_fNext_50$DEQ,
|
|
int_sqrt_fNext_50$EMPTY_N,
|
|
int_sqrt_fNext_50$ENQ,
|
|
int_sqrt_fNext_50$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_51
|
|
wire [464 : 0] int_sqrt_fNext_51$D_IN, int_sqrt_fNext_51$D_OUT;
|
|
wire int_sqrt_fNext_51$CLR,
|
|
int_sqrt_fNext_51$DEQ,
|
|
int_sqrt_fNext_51$EMPTY_N,
|
|
int_sqrt_fNext_51$ENQ,
|
|
int_sqrt_fNext_51$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_52
|
|
wire [464 : 0] int_sqrt_fNext_52$D_IN, int_sqrt_fNext_52$D_OUT;
|
|
wire int_sqrt_fNext_52$CLR,
|
|
int_sqrt_fNext_52$DEQ,
|
|
int_sqrt_fNext_52$EMPTY_N,
|
|
int_sqrt_fNext_52$ENQ,
|
|
int_sqrt_fNext_52$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_53
|
|
wire [464 : 0] int_sqrt_fNext_53$D_IN, int_sqrt_fNext_53$D_OUT;
|
|
wire int_sqrt_fNext_53$CLR,
|
|
int_sqrt_fNext_53$DEQ,
|
|
int_sqrt_fNext_53$EMPTY_N,
|
|
int_sqrt_fNext_53$ENQ,
|
|
int_sqrt_fNext_53$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_54
|
|
wire [464 : 0] int_sqrt_fNext_54$D_IN, int_sqrt_fNext_54$D_OUT;
|
|
wire int_sqrt_fNext_54$CLR,
|
|
int_sqrt_fNext_54$DEQ,
|
|
int_sqrt_fNext_54$EMPTY_N,
|
|
int_sqrt_fNext_54$ENQ,
|
|
int_sqrt_fNext_54$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_55
|
|
wire [464 : 0] int_sqrt_fNext_55$D_IN, int_sqrt_fNext_55$D_OUT;
|
|
wire int_sqrt_fNext_55$CLR,
|
|
int_sqrt_fNext_55$DEQ,
|
|
int_sqrt_fNext_55$EMPTY_N,
|
|
int_sqrt_fNext_55$ENQ,
|
|
int_sqrt_fNext_55$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_56
|
|
wire [464 : 0] int_sqrt_fNext_56$D_IN, int_sqrt_fNext_56$D_OUT;
|
|
wire int_sqrt_fNext_56$CLR,
|
|
int_sqrt_fNext_56$DEQ,
|
|
int_sqrt_fNext_56$EMPTY_N,
|
|
int_sqrt_fNext_56$ENQ,
|
|
int_sqrt_fNext_56$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_57
|
|
wire [464 : 0] int_sqrt_fNext_57$D_IN, int_sqrt_fNext_57$D_OUT;
|
|
wire int_sqrt_fNext_57$CLR,
|
|
int_sqrt_fNext_57$DEQ,
|
|
int_sqrt_fNext_57$EMPTY_N,
|
|
int_sqrt_fNext_57$ENQ,
|
|
int_sqrt_fNext_57$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_58
|
|
wire [464 : 0] int_sqrt_fNext_58$D_IN, int_sqrt_fNext_58$D_OUT;
|
|
wire int_sqrt_fNext_58$CLR,
|
|
int_sqrt_fNext_58$DEQ,
|
|
int_sqrt_fNext_58$EMPTY_N,
|
|
int_sqrt_fNext_58$ENQ,
|
|
int_sqrt_fNext_58$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_6
|
|
wire [464 : 0] int_sqrt_fNext_6$D_IN, int_sqrt_fNext_6$D_OUT;
|
|
wire int_sqrt_fNext_6$CLR,
|
|
int_sqrt_fNext_6$DEQ,
|
|
int_sqrt_fNext_6$EMPTY_N,
|
|
int_sqrt_fNext_6$ENQ,
|
|
int_sqrt_fNext_6$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_7
|
|
wire [464 : 0] int_sqrt_fNext_7$D_IN, int_sqrt_fNext_7$D_OUT;
|
|
wire int_sqrt_fNext_7$CLR,
|
|
int_sqrt_fNext_7$DEQ,
|
|
int_sqrt_fNext_7$EMPTY_N,
|
|
int_sqrt_fNext_7$ENQ,
|
|
int_sqrt_fNext_7$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_8
|
|
wire [464 : 0] int_sqrt_fNext_8$D_IN, int_sqrt_fNext_8$D_OUT;
|
|
wire int_sqrt_fNext_8$CLR,
|
|
int_sqrt_fNext_8$DEQ,
|
|
int_sqrt_fNext_8$EMPTY_N,
|
|
int_sqrt_fNext_8$ENQ,
|
|
int_sqrt_fNext_8$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fNext_9
|
|
wire [464 : 0] int_sqrt_fNext_9$D_IN, int_sqrt_fNext_9$D_OUT;
|
|
wire int_sqrt_fNext_9$CLR,
|
|
int_sqrt_fNext_9$DEQ,
|
|
int_sqrt_fNext_9$EMPTY_N,
|
|
int_sqrt_fNext_9$ENQ,
|
|
int_sqrt_fNext_9$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fRequest
|
|
wire [115 : 0] int_sqrt_fRequest$D_IN, int_sqrt_fRequest$D_OUT;
|
|
wire int_sqrt_fRequest$CLR,
|
|
int_sqrt_fRequest$DEQ,
|
|
int_sqrt_fRequest$EMPTY_N,
|
|
int_sqrt_fRequest$ENQ,
|
|
int_sqrt_fRequest$FULL_N;
|
|
|
|
// ports of submodule int_sqrt_fResponse
|
|
wire [116 : 0] int_sqrt_fResponse$D_IN, int_sqrt_fResponse$D_OUT;
|
|
wire int_sqrt_fResponse$CLR,
|
|
int_sqrt_fResponse$DEQ,
|
|
int_sqrt_fResponse$EMPTY_N,
|
|
int_sqrt_fResponse$ENQ,
|
|
int_sqrt_fResponse$FULL_N;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_fpu_s1_stage,
|
|
CAN_FIRE_RL_fpu_s2_stage,
|
|
CAN_FIRE_RL_fpu_s3_stage,
|
|
CAN_FIRE_RL_fpu_s4_stage,
|
|
CAN_FIRE_RL_fpu_s5_stage,
|
|
CAN_FIRE_RL_int_sqrt_finish,
|
|
CAN_FIRE_RL_int_sqrt_start,
|
|
CAN_FIRE_RL_int_sqrt_work,
|
|
CAN_FIRE_RL_int_sqrt_work_1,
|
|
CAN_FIRE_RL_int_sqrt_work_10,
|
|
CAN_FIRE_RL_int_sqrt_work_11,
|
|
CAN_FIRE_RL_int_sqrt_work_12,
|
|
CAN_FIRE_RL_int_sqrt_work_13,
|
|
CAN_FIRE_RL_int_sqrt_work_14,
|
|
CAN_FIRE_RL_int_sqrt_work_15,
|
|
CAN_FIRE_RL_int_sqrt_work_16,
|
|
CAN_FIRE_RL_int_sqrt_work_17,
|
|
CAN_FIRE_RL_int_sqrt_work_18,
|
|
CAN_FIRE_RL_int_sqrt_work_19,
|
|
CAN_FIRE_RL_int_sqrt_work_2,
|
|
CAN_FIRE_RL_int_sqrt_work_20,
|
|
CAN_FIRE_RL_int_sqrt_work_21,
|
|
CAN_FIRE_RL_int_sqrt_work_22,
|
|
CAN_FIRE_RL_int_sqrt_work_23,
|
|
CAN_FIRE_RL_int_sqrt_work_24,
|
|
CAN_FIRE_RL_int_sqrt_work_25,
|
|
CAN_FIRE_RL_int_sqrt_work_26,
|
|
CAN_FIRE_RL_int_sqrt_work_27,
|
|
CAN_FIRE_RL_int_sqrt_work_28,
|
|
CAN_FIRE_RL_int_sqrt_work_29,
|
|
CAN_FIRE_RL_int_sqrt_work_3,
|
|
CAN_FIRE_RL_int_sqrt_work_30,
|
|
CAN_FIRE_RL_int_sqrt_work_31,
|
|
CAN_FIRE_RL_int_sqrt_work_32,
|
|
CAN_FIRE_RL_int_sqrt_work_33,
|
|
CAN_FIRE_RL_int_sqrt_work_34,
|
|
CAN_FIRE_RL_int_sqrt_work_35,
|
|
CAN_FIRE_RL_int_sqrt_work_36,
|
|
CAN_FIRE_RL_int_sqrt_work_37,
|
|
CAN_FIRE_RL_int_sqrt_work_38,
|
|
CAN_FIRE_RL_int_sqrt_work_39,
|
|
CAN_FIRE_RL_int_sqrt_work_4,
|
|
CAN_FIRE_RL_int_sqrt_work_40,
|
|
CAN_FIRE_RL_int_sqrt_work_41,
|
|
CAN_FIRE_RL_int_sqrt_work_42,
|
|
CAN_FIRE_RL_int_sqrt_work_43,
|
|
CAN_FIRE_RL_int_sqrt_work_44,
|
|
CAN_FIRE_RL_int_sqrt_work_45,
|
|
CAN_FIRE_RL_int_sqrt_work_46,
|
|
CAN_FIRE_RL_int_sqrt_work_47,
|
|
CAN_FIRE_RL_int_sqrt_work_48,
|
|
CAN_FIRE_RL_int_sqrt_work_49,
|
|
CAN_FIRE_RL_int_sqrt_work_5,
|
|
CAN_FIRE_RL_int_sqrt_work_50,
|
|
CAN_FIRE_RL_int_sqrt_work_51,
|
|
CAN_FIRE_RL_int_sqrt_work_52,
|
|
CAN_FIRE_RL_int_sqrt_work_53,
|
|
CAN_FIRE_RL_int_sqrt_work_54,
|
|
CAN_FIRE_RL_int_sqrt_work_55,
|
|
CAN_FIRE_RL_int_sqrt_work_56,
|
|
CAN_FIRE_RL_int_sqrt_work_57,
|
|
CAN_FIRE_RL_int_sqrt_work_58,
|
|
CAN_FIRE_RL_int_sqrt_work_6,
|
|
CAN_FIRE_RL_int_sqrt_work_7,
|
|
CAN_FIRE_RL_int_sqrt_work_8,
|
|
CAN_FIRE_RL_int_sqrt_work_9,
|
|
CAN_FIRE_request_put,
|
|
CAN_FIRE_response_get,
|
|
WILL_FIRE_RL_fpu_s1_stage,
|
|
WILL_FIRE_RL_fpu_s2_stage,
|
|
WILL_FIRE_RL_fpu_s3_stage,
|
|
WILL_FIRE_RL_fpu_s4_stage,
|
|
WILL_FIRE_RL_fpu_s5_stage,
|
|
WILL_FIRE_RL_int_sqrt_finish,
|
|
WILL_FIRE_RL_int_sqrt_start,
|
|
WILL_FIRE_RL_int_sqrt_work,
|
|
WILL_FIRE_RL_int_sqrt_work_1,
|
|
WILL_FIRE_RL_int_sqrt_work_10,
|
|
WILL_FIRE_RL_int_sqrt_work_11,
|
|
WILL_FIRE_RL_int_sqrt_work_12,
|
|
WILL_FIRE_RL_int_sqrt_work_13,
|
|
WILL_FIRE_RL_int_sqrt_work_14,
|
|
WILL_FIRE_RL_int_sqrt_work_15,
|
|
WILL_FIRE_RL_int_sqrt_work_16,
|
|
WILL_FIRE_RL_int_sqrt_work_17,
|
|
WILL_FIRE_RL_int_sqrt_work_18,
|
|
WILL_FIRE_RL_int_sqrt_work_19,
|
|
WILL_FIRE_RL_int_sqrt_work_2,
|
|
WILL_FIRE_RL_int_sqrt_work_20,
|
|
WILL_FIRE_RL_int_sqrt_work_21,
|
|
WILL_FIRE_RL_int_sqrt_work_22,
|
|
WILL_FIRE_RL_int_sqrt_work_23,
|
|
WILL_FIRE_RL_int_sqrt_work_24,
|
|
WILL_FIRE_RL_int_sqrt_work_25,
|
|
WILL_FIRE_RL_int_sqrt_work_26,
|
|
WILL_FIRE_RL_int_sqrt_work_27,
|
|
WILL_FIRE_RL_int_sqrt_work_28,
|
|
WILL_FIRE_RL_int_sqrt_work_29,
|
|
WILL_FIRE_RL_int_sqrt_work_3,
|
|
WILL_FIRE_RL_int_sqrt_work_30,
|
|
WILL_FIRE_RL_int_sqrt_work_31,
|
|
WILL_FIRE_RL_int_sqrt_work_32,
|
|
WILL_FIRE_RL_int_sqrt_work_33,
|
|
WILL_FIRE_RL_int_sqrt_work_34,
|
|
WILL_FIRE_RL_int_sqrt_work_35,
|
|
WILL_FIRE_RL_int_sqrt_work_36,
|
|
WILL_FIRE_RL_int_sqrt_work_37,
|
|
WILL_FIRE_RL_int_sqrt_work_38,
|
|
WILL_FIRE_RL_int_sqrt_work_39,
|
|
WILL_FIRE_RL_int_sqrt_work_4,
|
|
WILL_FIRE_RL_int_sqrt_work_40,
|
|
WILL_FIRE_RL_int_sqrt_work_41,
|
|
WILL_FIRE_RL_int_sqrt_work_42,
|
|
WILL_FIRE_RL_int_sqrt_work_43,
|
|
WILL_FIRE_RL_int_sqrt_work_44,
|
|
WILL_FIRE_RL_int_sqrt_work_45,
|
|
WILL_FIRE_RL_int_sqrt_work_46,
|
|
WILL_FIRE_RL_int_sqrt_work_47,
|
|
WILL_FIRE_RL_int_sqrt_work_48,
|
|
WILL_FIRE_RL_int_sqrt_work_49,
|
|
WILL_FIRE_RL_int_sqrt_work_5,
|
|
WILL_FIRE_RL_int_sqrt_work_50,
|
|
WILL_FIRE_RL_int_sqrt_work_51,
|
|
WILL_FIRE_RL_int_sqrt_work_52,
|
|
WILL_FIRE_RL_int_sqrt_work_53,
|
|
WILL_FIRE_RL_int_sqrt_work_54,
|
|
WILL_FIRE_RL_int_sqrt_work_55,
|
|
WILL_FIRE_RL_int_sqrt_work_56,
|
|
WILL_FIRE_RL_int_sqrt_work_57,
|
|
WILL_FIRE_RL_int_sqrt_work_58,
|
|
WILL_FIRE_RL_int_sqrt_work_6,
|
|
WILL_FIRE_RL_int_sqrt_work_7,
|
|
WILL_FIRE_RL_int_sqrt_work_8,
|
|
WILL_FIRE_RL_int_sqrt_work_9,
|
|
WILL_FIRE_request_put,
|
|
WILL_FIRE_response_get;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15;
|
|
reg [62 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13,
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11;
|
|
reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2,
|
|
_theResult___fst_sfd__h76507;
|
|
reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4,
|
|
_theResult___fst_exp__h76506;
|
|
reg CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12,
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10;
|
|
wire [194 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477;
|
|
wire [115 : 0] _theResult___snd_fst__h25299,
|
|
_theResult___snd_fst__h25701,
|
|
_theResult___snd_fst__h26101,
|
|
_theResult___snd_fst__h26501,
|
|
_theResult___snd_fst__h26901,
|
|
_theResult___snd_fst__h27301,
|
|
_theResult___snd_fst__h27701,
|
|
_theResult___snd_fst__h28101,
|
|
_theResult___snd_fst__h28501,
|
|
_theResult___snd_fst__h28901,
|
|
_theResult___snd_fst__h29301,
|
|
_theResult___snd_fst__h29701,
|
|
_theResult___snd_fst__h30101,
|
|
_theResult___snd_fst__h30501,
|
|
_theResult___snd_fst__h30901,
|
|
_theResult___snd_fst__h31301,
|
|
_theResult___snd_fst__h31701,
|
|
_theResult___snd_fst__h32101,
|
|
_theResult___snd_fst__h32501,
|
|
_theResult___snd_fst__h32901,
|
|
_theResult___snd_fst__h33301,
|
|
_theResult___snd_fst__h33701,
|
|
_theResult___snd_fst__h34101,
|
|
_theResult___snd_fst__h34501,
|
|
_theResult___snd_fst__h34901,
|
|
_theResult___snd_fst__h35301,
|
|
_theResult___snd_fst__h35701,
|
|
_theResult___snd_fst__h36101,
|
|
_theResult___snd_fst__h36501,
|
|
_theResult___snd_fst__h36901,
|
|
_theResult___snd_fst__h37301,
|
|
_theResult___snd_fst__h37701,
|
|
_theResult___snd_fst__h38101,
|
|
_theResult___snd_fst__h38501,
|
|
_theResult___snd_fst__h38901,
|
|
_theResult___snd_fst__h39301,
|
|
_theResult___snd_fst__h39701,
|
|
_theResult___snd_fst__h40101,
|
|
_theResult___snd_fst__h40501,
|
|
_theResult___snd_fst__h40901,
|
|
_theResult___snd_fst__h41301,
|
|
_theResult___snd_fst__h41701,
|
|
_theResult___snd_fst__h42101,
|
|
_theResult___snd_fst__h42501,
|
|
_theResult___snd_fst__h42901,
|
|
_theResult___snd_fst__h43301,
|
|
_theResult___snd_fst__h43701,
|
|
_theResult___snd_fst__h44101,
|
|
_theResult___snd_fst__h44501,
|
|
_theResult___snd_fst__h44901,
|
|
_theResult___snd_fst__h45301,
|
|
_theResult___snd_fst__h45701,
|
|
_theResult___snd_fst__h46101,
|
|
_theResult___snd_fst__h46501,
|
|
_theResult___snd_fst__h46901,
|
|
_theResult___snd_fst__h47301,
|
|
_theResult___snd_fst__h47701,
|
|
_theResult___snd_fst__h48101,
|
|
_theResult___snd_fst__h48501,
|
|
_theResult___snd_snd__h25377,
|
|
_theResult___snd_snd__h25777,
|
|
_theResult___snd_snd__h26177,
|
|
_theResult___snd_snd__h26577,
|
|
_theResult___snd_snd__h26977,
|
|
_theResult___snd_snd__h27377,
|
|
_theResult___snd_snd__h27777,
|
|
_theResult___snd_snd__h28177,
|
|
_theResult___snd_snd__h28577,
|
|
_theResult___snd_snd__h28977,
|
|
_theResult___snd_snd__h29377,
|
|
_theResult___snd_snd__h29777,
|
|
_theResult___snd_snd__h30177,
|
|
_theResult___snd_snd__h30577,
|
|
_theResult___snd_snd__h30977,
|
|
_theResult___snd_snd__h31377,
|
|
_theResult___snd_snd__h31777,
|
|
_theResult___snd_snd__h32177,
|
|
_theResult___snd_snd__h32577,
|
|
_theResult___snd_snd__h32977,
|
|
_theResult___snd_snd__h33377,
|
|
_theResult___snd_snd__h33777,
|
|
_theResult___snd_snd__h34177,
|
|
_theResult___snd_snd__h34577,
|
|
_theResult___snd_snd__h34977,
|
|
_theResult___snd_snd__h35377,
|
|
_theResult___snd_snd__h35777,
|
|
_theResult___snd_snd__h36177,
|
|
_theResult___snd_snd__h36577,
|
|
_theResult___snd_snd__h36977,
|
|
_theResult___snd_snd__h37377,
|
|
_theResult___snd_snd__h37777,
|
|
_theResult___snd_snd__h38177,
|
|
_theResult___snd_snd__h38577,
|
|
_theResult___snd_snd__h38977,
|
|
_theResult___snd_snd__h39377,
|
|
_theResult___snd_snd__h39777,
|
|
_theResult___snd_snd__h40177,
|
|
_theResult___snd_snd__h40577,
|
|
_theResult___snd_snd__h40977,
|
|
_theResult___snd_snd__h41377,
|
|
_theResult___snd_snd__h41777,
|
|
_theResult___snd_snd__h42177,
|
|
_theResult___snd_snd__h42577,
|
|
_theResult___snd_snd__h42977,
|
|
_theResult___snd_snd__h43377,
|
|
_theResult___snd_snd__h43777,
|
|
_theResult___snd_snd__h44177,
|
|
_theResult___snd_snd__h44577,
|
|
_theResult___snd_snd__h44977,
|
|
_theResult___snd_snd__h45377,
|
|
_theResult___snd_snd__h45777,
|
|
_theResult___snd_snd__h46177,
|
|
_theResult___snd_snd__h46577,
|
|
_theResult___snd_snd__h46977,
|
|
_theResult___snd_snd__h47377,
|
|
_theResult___snd_snd__h47777,
|
|
_theResult___snd_snd__h48177,
|
|
_theResult___snd_snd__h48577,
|
|
b___1__h16687,
|
|
b__h25374,
|
|
b__h25774,
|
|
b__h26174,
|
|
b__h26574,
|
|
b__h26974,
|
|
b__h27374,
|
|
b__h27774,
|
|
b__h28174,
|
|
b__h28574,
|
|
b__h28974,
|
|
b__h29374,
|
|
b__h29774,
|
|
b__h30174,
|
|
b__h30574,
|
|
b__h30974,
|
|
b__h31374,
|
|
b__h31774,
|
|
b__h32174,
|
|
b__h32574,
|
|
b__h32974,
|
|
b__h33374,
|
|
b__h33774,
|
|
b__h34174,
|
|
b__h34574,
|
|
b__h34974,
|
|
b__h35374,
|
|
b__h35774,
|
|
b__h36174,
|
|
b__h36574,
|
|
b__h36974,
|
|
b__h37374,
|
|
b__h37774,
|
|
b__h38174,
|
|
b__h38574,
|
|
b__h38974,
|
|
b__h39374,
|
|
b__h39774,
|
|
b__h40174,
|
|
b__h40574,
|
|
b__h40974,
|
|
b__h41374,
|
|
b__h41774,
|
|
b__h42174,
|
|
b__h42574,
|
|
b__h42974,
|
|
b__h43374,
|
|
b__h43774,
|
|
b__h44174,
|
|
b__h44574,
|
|
b__h44974,
|
|
b__h45374,
|
|
b__h45774,
|
|
b__h46174,
|
|
b__h46574,
|
|
b__h46974,
|
|
b__h47374,
|
|
b__h47774,
|
|
b__h48174,
|
|
b__h48574,
|
|
b__h48712,
|
|
r__h25386,
|
|
r__h25394,
|
|
r__h25786,
|
|
r__h25794,
|
|
r__h26186,
|
|
r__h26194,
|
|
r__h26586,
|
|
r__h26594,
|
|
r__h26986,
|
|
r__h26994,
|
|
r__h27386,
|
|
r__h27394,
|
|
r__h27786,
|
|
r__h27794,
|
|
r__h28186,
|
|
r__h28194,
|
|
r__h28586,
|
|
r__h28594,
|
|
r__h28986,
|
|
r__h28994,
|
|
r__h29386,
|
|
r__h29394,
|
|
r__h29786,
|
|
r__h29794,
|
|
r__h30186,
|
|
r__h30194,
|
|
r__h30586,
|
|
r__h30594,
|
|
r__h30986,
|
|
r__h30994,
|
|
r__h31386,
|
|
r__h31394,
|
|
r__h31786,
|
|
r__h31794,
|
|
r__h32186,
|
|
r__h32194,
|
|
r__h32586,
|
|
r__h32594,
|
|
r__h32986,
|
|
r__h32994,
|
|
r__h33386,
|
|
r__h33394,
|
|
r__h33786,
|
|
r__h33794,
|
|
r__h34186,
|
|
r__h34194,
|
|
r__h34586,
|
|
r__h34594,
|
|
r__h34986,
|
|
r__h34994,
|
|
r__h35386,
|
|
r__h35394,
|
|
r__h35786,
|
|
r__h35794,
|
|
r__h36186,
|
|
r__h36194,
|
|
r__h36586,
|
|
r__h36594,
|
|
r__h36986,
|
|
r__h36994,
|
|
r__h37386,
|
|
r__h37394,
|
|
r__h37786,
|
|
r__h37794,
|
|
r__h38186,
|
|
r__h38194,
|
|
r__h38586,
|
|
r__h38594,
|
|
r__h38986,
|
|
r__h38994,
|
|
r__h39386,
|
|
r__h39394,
|
|
r__h39786,
|
|
r__h39794,
|
|
r__h40186,
|
|
r__h40194,
|
|
r__h40586,
|
|
r__h40594,
|
|
r__h40986,
|
|
r__h40994,
|
|
r__h41386,
|
|
r__h41394,
|
|
r__h41786,
|
|
r__h41794,
|
|
r__h42186,
|
|
r__h42194,
|
|
r__h42586,
|
|
r__h42594,
|
|
r__h42986,
|
|
r__h42994,
|
|
r__h43386,
|
|
r__h43394,
|
|
r__h43786,
|
|
r__h43794,
|
|
r__h44186,
|
|
r__h44194,
|
|
r__h44586,
|
|
r__h44594,
|
|
r__h44986,
|
|
r__h44994,
|
|
r__h45386,
|
|
r__h45394,
|
|
r__h45786,
|
|
r__h45794,
|
|
r__h46186,
|
|
r__h46194,
|
|
r__h46586,
|
|
r__h46594,
|
|
r__h46986,
|
|
r__h46994,
|
|
r__h47386,
|
|
r__h47394,
|
|
r__h47786,
|
|
r__h47794,
|
|
r__h48186,
|
|
r__h48194,
|
|
r__h48586,
|
|
r__h48594,
|
|
s__h25385,
|
|
s__h25785,
|
|
s__h26185,
|
|
s__h26585,
|
|
s__h26985,
|
|
s__h27385,
|
|
s__h27785,
|
|
s__h28185,
|
|
s__h28585,
|
|
s__h28985,
|
|
s__h29385,
|
|
s__h29785,
|
|
s__h30185,
|
|
s__h30585,
|
|
s__h30985,
|
|
s__h31385,
|
|
s__h31785,
|
|
s__h32185,
|
|
s__h32585,
|
|
s__h32985,
|
|
s__h33385,
|
|
s__h33785,
|
|
s__h34185,
|
|
s__h34585,
|
|
s__h34985,
|
|
s__h35385,
|
|
s__h35785,
|
|
s__h36185,
|
|
s__h36585,
|
|
s__h36985,
|
|
s__h37385,
|
|
s__h37785,
|
|
s__h38185,
|
|
s__h38585,
|
|
s__h38985,
|
|
s__h39385,
|
|
s__h39785,
|
|
s__h40185,
|
|
s__h40585,
|
|
s__h40985,
|
|
s__h41385,
|
|
s__h41785,
|
|
s__h42185,
|
|
s__h42585,
|
|
s__h42985,
|
|
s__h43385,
|
|
s__h43785,
|
|
s__h44185,
|
|
s__h44585,
|
|
s__h44985,
|
|
s__h45385,
|
|
s__h45785,
|
|
s__h46185,
|
|
s__h46585,
|
|
s__h46985,
|
|
s__h47385,
|
|
s__h47785,
|
|
s__h48185,
|
|
s__h48585,
|
|
sum__h25372,
|
|
sum__h25772,
|
|
sum__h26172,
|
|
sum__h26572,
|
|
sum__h26972,
|
|
sum__h27372,
|
|
sum__h27772,
|
|
sum__h28172,
|
|
sum__h28572,
|
|
sum__h28972,
|
|
sum__h29372,
|
|
sum__h29772,
|
|
sum__h30172,
|
|
sum__h30572,
|
|
sum__h30972,
|
|
sum__h31372,
|
|
sum__h31772,
|
|
sum__h32172,
|
|
sum__h32572,
|
|
sum__h32972,
|
|
sum__h33372,
|
|
sum__h33772,
|
|
sum__h34172,
|
|
sum__h34572,
|
|
sum__h34972,
|
|
sum__h35372,
|
|
sum__h35772,
|
|
sum__h36172,
|
|
sum__h36572,
|
|
sum__h36972,
|
|
sum__h37372,
|
|
sum__h37772,
|
|
sum__h38172,
|
|
sum__h38572,
|
|
sum__h38972,
|
|
sum__h39372,
|
|
sum__h39772,
|
|
sum__h40172,
|
|
sum__h40572,
|
|
sum__h40972,
|
|
sum__h41372,
|
|
sum__h41772,
|
|
sum__h42172,
|
|
sum__h42572,
|
|
sum__h42972,
|
|
sum__h43372,
|
|
sum__h43772,
|
|
sum__h44172,
|
|
sum__h44572,
|
|
sum__h44972,
|
|
sum__h45372,
|
|
sum__h45772,
|
|
sum__h46172,
|
|
sum__h46572,
|
|
sum__h46972,
|
|
sum__h47372,
|
|
sum__h47772,
|
|
sum__h48172,
|
|
sum__h48572,
|
|
x__h402;
|
|
wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866,
|
|
IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820;
|
|
wire [58 : 0] IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6,
|
|
_theResult___snd__h75283,
|
|
_theResult___snd__h75298,
|
|
_theResult___snd__h75300,
|
|
_theResult___snd__h75313,
|
|
_theResult___snd__h75319,
|
|
_theResult___snd__h75337,
|
|
_theResult___snd__h75342,
|
|
result__h66451,
|
|
sfdin__h75260,
|
|
x__h66665;
|
|
wire [57 : 0] sfd___1__h65692, sfd__h49936, sfd__h49938, x__h65683;
|
|
wire [53 : 0] sfd__h75932, value__h58164;
|
|
wire [51 : 0] _theResult___fst_sfd__h76510,
|
|
_theResult___sfd__h76429,
|
|
out_sfd__h76432,
|
|
sfd__h49989;
|
|
wire [12 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460,
|
|
x__h57541,
|
|
x__h57559;
|
|
wire [11 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9,
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531,
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774;
|
|
wire [10 : 0] IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863,
|
|
_theResult___exp__h76428,
|
|
_theResult___fst_exp__h75266,
|
|
_theResult___fst_exp__h75269,
|
|
_theResult___fst_exp__h75289,
|
|
_theResult___fst_exp__h75305,
|
|
_theResult___fst_exp__h75344,
|
|
_theResult___fst_exp__h75350,
|
|
_theResult___fst_exp__h75353,
|
|
_theResult___fst_exp__h76509,
|
|
din_inc___2_exp__h76519,
|
|
fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8,
|
|
fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5,
|
|
out_exp__h76431;
|
|
wire [6 : 0] IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237,
|
|
x__h24992;
|
|
wire [5 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458,
|
|
IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772,
|
|
x__h65722;
|
|
wire [2 : 0] IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813;
|
|
wire [1 : 0] IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7,
|
|
_theResult___snd_fst__h75372,
|
|
guard__h66951,
|
|
x__h75654;
|
|
wire _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775,
|
|
int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264,
|
|
int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299,
|
|
int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649,
|
|
int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684,
|
|
int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719,
|
|
int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754,
|
|
int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789,
|
|
int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824,
|
|
int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859,
|
|
int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894,
|
|
int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929,
|
|
int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964,
|
|
int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334,
|
|
int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999,
|
|
int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034,
|
|
int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069,
|
|
int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104,
|
|
int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139,
|
|
int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174,
|
|
int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209,
|
|
int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244,
|
|
int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279,
|
|
int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314,
|
|
int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369,
|
|
int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349,
|
|
int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384,
|
|
int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419,
|
|
int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454,
|
|
int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489,
|
|
int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524,
|
|
int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559,
|
|
int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594,
|
|
int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629,
|
|
int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664,
|
|
int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404,
|
|
int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699,
|
|
int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734,
|
|
int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769,
|
|
int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804,
|
|
int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839,
|
|
int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874,
|
|
int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909,
|
|
int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944,
|
|
int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979,
|
|
int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014,
|
|
int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439,
|
|
int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049,
|
|
int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084,
|
|
int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119,
|
|
int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154,
|
|
int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189,
|
|
int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224,
|
|
int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259,
|
|
int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294,
|
|
int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474,
|
|
int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509,
|
|
int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544,
|
|
int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579,
|
|
int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614,
|
|
value_BIT_52___h58260;
|
|
|
|
// action method request_put
|
|
assign RDY_request_put = fpu_fOperand_S0$FULL_N ;
|
|
assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ;
|
|
assign WILL_FIRE_request_put = EN_request_put ;
|
|
|
|
// actionvalue method response_get
|
|
assign response_get = fpu_fResult_S5$D_OUT ;
|
|
assign RDY_response_get = fpu_fResult_S5$EMPTY_N ;
|
|
assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ;
|
|
assign WILL_FIRE_response_get = EN_response_get ;
|
|
|
|
// submodule fpu_fOperand_S0
|
|
FIFOL1 #(.width(32'd67)) fpu_fOperand_S0(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fOperand_S0$D_IN),
|
|
.ENQ(fpu_fOperand_S0$ENQ),
|
|
.DEQ(fpu_fOperand_S0$DEQ),
|
|
.CLR(fpu_fOperand_S0$CLR),
|
|
.D_OUT(fpu_fOperand_S0$D_OUT),
|
|
.FULL_N(fpu_fOperand_S0$FULL_N),
|
|
.EMPTY_N(fpu_fOperand_S0$EMPTY_N));
|
|
|
|
// submodule fpu_fResult_S5
|
|
FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fResult_S5$D_IN),
|
|
.ENQ(fpu_fResult_S5$ENQ),
|
|
.DEQ(fpu_fResult_S5$DEQ),
|
|
.CLR(fpu_fResult_S5$CLR),
|
|
.D_OUT(fpu_fResult_S5$D_OUT),
|
|
.FULL_N(fpu_fResult_S5$FULL_N),
|
|
.EMPTY_N(fpu_fResult_S5$EMPTY_N));
|
|
|
|
// submodule fpu_fState_S1
|
|
FIFOL1 #(.width(32'd195)) fpu_fState_S1(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fState_S1$D_IN),
|
|
.ENQ(fpu_fState_S1$ENQ),
|
|
.DEQ(fpu_fState_S1$DEQ),
|
|
.CLR(fpu_fState_S1$CLR),
|
|
.D_OUT(fpu_fState_S1$D_OUT),
|
|
.FULL_N(fpu_fState_S1$FULL_N),
|
|
.EMPTY_N(fpu_fState_S1$EMPTY_N));
|
|
|
|
// submodule fpu_fState_S2
|
|
FIFOL1 #(.width(32'd137)) fpu_fState_S2(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fState_S2$D_IN),
|
|
.ENQ(fpu_fState_S2$ENQ),
|
|
.DEQ(fpu_fState_S2$DEQ),
|
|
.CLR(fpu_fState_S2$CLR),
|
|
.D_OUT(fpu_fState_S2$D_OUT),
|
|
.FULL_N(fpu_fState_S2$FULL_N),
|
|
.EMPTY_N(fpu_fState_S2$EMPTY_N));
|
|
|
|
// submodule fpu_fState_S3
|
|
FIFOL1 #(.width(32'd196)) fpu_fState_S3(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fState_S3$D_IN),
|
|
.ENQ(fpu_fState_S3$ENQ),
|
|
.DEQ(fpu_fState_S3$DEQ),
|
|
.CLR(fpu_fState_S3$CLR),
|
|
.D_OUT(fpu_fState_S3$D_OUT),
|
|
.FULL_N(fpu_fState_S3$FULL_N),
|
|
.EMPTY_N(fpu_fState_S3$EMPTY_N));
|
|
|
|
// submodule fpu_fState_S4
|
|
FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fState_S4$D_IN),
|
|
.ENQ(fpu_fState_S4$ENQ),
|
|
.DEQ(fpu_fState_S4$DEQ),
|
|
.CLR(fpu_fState_S4$CLR),
|
|
.D_OUT(fpu_fState_S4$D_OUT),
|
|
.FULL_N(fpu_fState_S4$FULL_N),
|
|
.EMPTY_N(fpu_fState_S4$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fFirst
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fFirst(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fFirst$D_IN),
|
|
.ENQ(int_sqrt_fFirst$ENQ),
|
|
.DEQ(int_sqrt_fFirst$DEQ),
|
|
.CLR(int_sqrt_fFirst$CLR),
|
|
.D_OUT(int_sqrt_fFirst$D_OUT),
|
|
.FULL_N(int_sqrt_fFirst$FULL_N),
|
|
.EMPTY_N(int_sqrt_fFirst$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_0
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_0(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_0$D_IN),
|
|
.ENQ(int_sqrt_fNext_0$ENQ),
|
|
.DEQ(int_sqrt_fNext_0$DEQ),
|
|
.CLR(int_sqrt_fNext_0$CLR),
|
|
.D_OUT(int_sqrt_fNext_0$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_0$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_0$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_1
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_1(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_1$D_IN),
|
|
.ENQ(int_sqrt_fNext_1$ENQ),
|
|
.DEQ(int_sqrt_fNext_1$DEQ),
|
|
.CLR(int_sqrt_fNext_1$CLR),
|
|
.D_OUT(int_sqrt_fNext_1$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_1$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_1$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_10
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_10(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_10$D_IN),
|
|
.ENQ(int_sqrt_fNext_10$ENQ),
|
|
.DEQ(int_sqrt_fNext_10$DEQ),
|
|
.CLR(int_sqrt_fNext_10$CLR),
|
|
.D_OUT(int_sqrt_fNext_10$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_10$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_10$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_11
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_11(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_11$D_IN),
|
|
.ENQ(int_sqrt_fNext_11$ENQ),
|
|
.DEQ(int_sqrt_fNext_11$DEQ),
|
|
.CLR(int_sqrt_fNext_11$CLR),
|
|
.D_OUT(int_sqrt_fNext_11$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_11$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_11$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_12
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_12(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_12$D_IN),
|
|
.ENQ(int_sqrt_fNext_12$ENQ),
|
|
.DEQ(int_sqrt_fNext_12$DEQ),
|
|
.CLR(int_sqrt_fNext_12$CLR),
|
|
.D_OUT(int_sqrt_fNext_12$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_12$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_12$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_13
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_13(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_13$D_IN),
|
|
.ENQ(int_sqrt_fNext_13$ENQ),
|
|
.DEQ(int_sqrt_fNext_13$DEQ),
|
|
.CLR(int_sqrt_fNext_13$CLR),
|
|
.D_OUT(int_sqrt_fNext_13$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_13$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_13$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_14
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_14(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_14$D_IN),
|
|
.ENQ(int_sqrt_fNext_14$ENQ),
|
|
.DEQ(int_sqrt_fNext_14$DEQ),
|
|
.CLR(int_sqrt_fNext_14$CLR),
|
|
.D_OUT(int_sqrt_fNext_14$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_14$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_14$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_15
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_15(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_15$D_IN),
|
|
.ENQ(int_sqrt_fNext_15$ENQ),
|
|
.DEQ(int_sqrt_fNext_15$DEQ),
|
|
.CLR(int_sqrt_fNext_15$CLR),
|
|
.D_OUT(int_sqrt_fNext_15$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_15$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_15$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_16
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_16(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_16$D_IN),
|
|
.ENQ(int_sqrt_fNext_16$ENQ),
|
|
.DEQ(int_sqrt_fNext_16$DEQ),
|
|
.CLR(int_sqrt_fNext_16$CLR),
|
|
.D_OUT(int_sqrt_fNext_16$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_16$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_16$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_17
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_17(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_17$D_IN),
|
|
.ENQ(int_sqrt_fNext_17$ENQ),
|
|
.DEQ(int_sqrt_fNext_17$DEQ),
|
|
.CLR(int_sqrt_fNext_17$CLR),
|
|
.D_OUT(int_sqrt_fNext_17$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_17$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_17$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_18
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_18(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_18$D_IN),
|
|
.ENQ(int_sqrt_fNext_18$ENQ),
|
|
.DEQ(int_sqrt_fNext_18$DEQ),
|
|
.CLR(int_sqrt_fNext_18$CLR),
|
|
.D_OUT(int_sqrt_fNext_18$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_18$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_18$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_19
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_19(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_19$D_IN),
|
|
.ENQ(int_sqrt_fNext_19$ENQ),
|
|
.DEQ(int_sqrt_fNext_19$DEQ),
|
|
.CLR(int_sqrt_fNext_19$CLR),
|
|
.D_OUT(int_sqrt_fNext_19$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_19$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_19$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_2
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_2(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_2$D_IN),
|
|
.ENQ(int_sqrt_fNext_2$ENQ),
|
|
.DEQ(int_sqrt_fNext_2$DEQ),
|
|
.CLR(int_sqrt_fNext_2$CLR),
|
|
.D_OUT(int_sqrt_fNext_2$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_2$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_2$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_20
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_20(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_20$D_IN),
|
|
.ENQ(int_sqrt_fNext_20$ENQ),
|
|
.DEQ(int_sqrt_fNext_20$DEQ),
|
|
.CLR(int_sqrt_fNext_20$CLR),
|
|
.D_OUT(int_sqrt_fNext_20$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_20$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_20$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_21
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_21(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_21$D_IN),
|
|
.ENQ(int_sqrt_fNext_21$ENQ),
|
|
.DEQ(int_sqrt_fNext_21$DEQ),
|
|
.CLR(int_sqrt_fNext_21$CLR),
|
|
.D_OUT(int_sqrt_fNext_21$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_21$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_21$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_22
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_22(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_22$D_IN),
|
|
.ENQ(int_sqrt_fNext_22$ENQ),
|
|
.DEQ(int_sqrt_fNext_22$DEQ),
|
|
.CLR(int_sqrt_fNext_22$CLR),
|
|
.D_OUT(int_sqrt_fNext_22$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_22$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_22$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_23
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_23(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_23$D_IN),
|
|
.ENQ(int_sqrt_fNext_23$ENQ),
|
|
.DEQ(int_sqrt_fNext_23$DEQ),
|
|
.CLR(int_sqrt_fNext_23$CLR),
|
|
.D_OUT(int_sqrt_fNext_23$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_23$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_23$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_24
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_24(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_24$D_IN),
|
|
.ENQ(int_sqrt_fNext_24$ENQ),
|
|
.DEQ(int_sqrt_fNext_24$DEQ),
|
|
.CLR(int_sqrt_fNext_24$CLR),
|
|
.D_OUT(int_sqrt_fNext_24$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_24$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_24$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_25
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_25(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_25$D_IN),
|
|
.ENQ(int_sqrt_fNext_25$ENQ),
|
|
.DEQ(int_sqrt_fNext_25$DEQ),
|
|
.CLR(int_sqrt_fNext_25$CLR),
|
|
.D_OUT(int_sqrt_fNext_25$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_25$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_25$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_26
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_26(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_26$D_IN),
|
|
.ENQ(int_sqrt_fNext_26$ENQ),
|
|
.DEQ(int_sqrt_fNext_26$DEQ),
|
|
.CLR(int_sqrt_fNext_26$CLR),
|
|
.D_OUT(int_sqrt_fNext_26$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_26$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_26$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_27
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_27(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_27$D_IN),
|
|
.ENQ(int_sqrt_fNext_27$ENQ),
|
|
.DEQ(int_sqrt_fNext_27$DEQ),
|
|
.CLR(int_sqrt_fNext_27$CLR),
|
|
.D_OUT(int_sqrt_fNext_27$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_27$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_27$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_28
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_28(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_28$D_IN),
|
|
.ENQ(int_sqrt_fNext_28$ENQ),
|
|
.DEQ(int_sqrt_fNext_28$DEQ),
|
|
.CLR(int_sqrt_fNext_28$CLR),
|
|
.D_OUT(int_sqrt_fNext_28$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_28$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_28$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_29
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_29(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_29$D_IN),
|
|
.ENQ(int_sqrt_fNext_29$ENQ),
|
|
.DEQ(int_sqrt_fNext_29$DEQ),
|
|
.CLR(int_sqrt_fNext_29$CLR),
|
|
.D_OUT(int_sqrt_fNext_29$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_29$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_29$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_3
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_3(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_3$D_IN),
|
|
.ENQ(int_sqrt_fNext_3$ENQ),
|
|
.DEQ(int_sqrt_fNext_3$DEQ),
|
|
.CLR(int_sqrt_fNext_3$CLR),
|
|
.D_OUT(int_sqrt_fNext_3$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_3$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_3$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_30
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_30(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_30$D_IN),
|
|
.ENQ(int_sqrt_fNext_30$ENQ),
|
|
.DEQ(int_sqrt_fNext_30$DEQ),
|
|
.CLR(int_sqrt_fNext_30$CLR),
|
|
.D_OUT(int_sqrt_fNext_30$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_30$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_30$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_31
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_31(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_31$D_IN),
|
|
.ENQ(int_sqrt_fNext_31$ENQ),
|
|
.DEQ(int_sqrt_fNext_31$DEQ),
|
|
.CLR(int_sqrt_fNext_31$CLR),
|
|
.D_OUT(int_sqrt_fNext_31$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_31$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_31$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_32
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_32(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_32$D_IN),
|
|
.ENQ(int_sqrt_fNext_32$ENQ),
|
|
.DEQ(int_sqrt_fNext_32$DEQ),
|
|
.CLR(int_sqrt_fNext_32$CLR),
|
|
.D_OUT(int_sqrt_fNext_32$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_32$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_32$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_33
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_33(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_33$D_IN),
|
|
.ENQ(int_sqrt_fNext_33$ENQ),
|
|
.DEQ(int_sqrt_fNext_33$DEQ),
|
|
.CLR(int_sqrt_fNext_33$CLR),
|
|
.D_OUT(int_sqrt_fNext_33$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_33$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_33$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_34
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_34(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_34$D_IN),
|
|
.ENQ(int_sqrt_fNext_34$ENQ),
|
|
.DEQ(int_sqrt_fNext_34$DEQ),
|
|
.CLR(int_sqrt_fNext_34$CLR),
|
|
.D_OUT(int_sqrt_fNext_34$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_34$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_34$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_35
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_35(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_35$D_IN),
|
|
.ENQ(int_sqrt_fNext_35$ENQ),
|
|
.DEQ(int_sqrt_fNext_35$DEQ),
|
|
.CLR(int_sqrt_fNext_35$CLR),
|
|
.D_OUT(int_sqrt_fNext_35$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_35$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_35$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_36
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_36(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_36$D_IN),
|
|
.ENQ(int_sqrt_fNext_36$ENQ),
|
|
.DEQ(int_sqrt_fNext_36$DEQ),
|
|
.CLR(int_sqrt_fNext_36$CLR),
|
|
.D_OUT(int_sqrt_fNext_36$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_36$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_36$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_37
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_37(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_37$D_IN),
|
|
.ENQ(int_sqrt_fNext_37$ENQ),
|
|
.DEQ(int_sqrt_fNext_37$DEQ),
|
|
.CLR(int_sqrt_fNext_37$CLR),
|
|
.D_OUT(int_sqrt_fNext_37$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_37$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_37$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_38
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_38(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_38$D_IN),
|
|
.ENQ(int_sqrt_fNext_38$ENQ),
|
|
.DEQ(int_sqrt_fNext_38$DEQ),
|
|
.CLR(int_sqrt_fNext_38$CLR),
|
|
.D_OUT(int_sqrt_fNext_38$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_38$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_38$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_39
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_39(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_39$D_IN),
|
|
.ENQ(int_sqrt_fNext_39$ENQ),
|
|
.DEQ(int_sqrt_fNext_39$DEQ),
|
|
.CLR(int_sqrt_fNext_39$CLR),
|
|
.D_OUT(int_sqrt_fNext_39$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_39$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_39$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_4
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_4(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_4$D_IN),
|
|
.ENQ(int_sqrt_fNext_4$ENQ),
|
|
.DEQ(int_sqrt_fNext_4$DEQ),
|
|
.CLR(int_sqrt_fNext_4$CLR),
|
|
.D_OUT(int_sqrt_fNext_4$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_4$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_4$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_40
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_40(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_40$D_IN),
|
|
.ENQ(int_sqrt_fNext_40$ENQ),
|
|
.DEQ(int_sqrt_fNext_40$DEQ),
|
|
.CLR(int_sqrt_fNext_40$CLR),
|
|
.D_OUT(int_sqrt_fNext_40$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_40$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_40$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_41
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_41(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_41$D_IN),
|
|
.ENQ(int_sqrt_fNext_41$ENQ),
|
|
.DEQ(int_sqrt_fNext_41$DEQ),
|
|
.CLR(int_sqrt_fNext_41$CLR),
|
|
.D_OUT(int_sqrt_fNext_41$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_41$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_41$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_42
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_42(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_42$D_IN),
|
|
.ENQ(int_sqrt_fNext_42$ENQ),
|
|
.DEQ(int_sqrt_fNext_42$DEQ),
|
|
.CLR(int_sqrt_fNext_42$CLR),
|
|
.D_OUT(int_sqrt_fNext_42$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_42$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_42$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_43
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_43(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_43$D_IN),
|
|
.ENQ(int_sqrt_fNext_43$ENQ),
|
|
.DEQ(int_sqrt_fNext_43$DEQ),
|
|
.CLR(int_sqrt_fNext_43$CLR),
|
|
.D_OUT(int_sqrt_fNext_43$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_43$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_43$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_44
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_44(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_44$D_IN),
|
|
.ENQ(int_sqrt_fNext_44$ENQ),
|
|
.DEQ(int_sqrt_fNext_44$DEQ),
|
|
.CLR(int_sqrt_fNext_44$CLR),
|
|
.D_OUT(int_sqrt_fNext_44$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_44$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_44$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_45
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_45(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_45$D_IN),
|
|
.ENQ(int_sqrt_fNext_45$ENQ),
|
|
.DEQ(int_sqrt_fNext_45$DEQ),
|
|
.CLR(int_sqrt_fNext_45$CLR),
|
|
.D_OUT(int_sqrt_fNext_45$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_45$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_45$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_46
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_46(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_46$D_IN),
|
|
.ENQ(int_sqrt_fNext_46$ENQ),
|
|
.DEQ(int_sqrt_fNext_46$DEQ),
|
|
.CLR(int_sqrt_fNext_46$CLR),
|
|
.D_OUT(int_sqrt_fNext_46$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_46$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_46$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_47
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_47(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_47$D_IN),
|
|
.ENQ(int_sqrt_fNext_47$ENQ),
|
|
.DEQ(int_sqrt_fNext_47$DEQ),
|
|
.CLR(int_sqrt_fNext_47$CLR),
|
|
.D_OUT(int_sqrt_fNext_47$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_47$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_47$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_48
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_48(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_48$D_IN),
|
|
.ENQ(int_sqrt_fNext_48$ENQ),
|
|
.DEQ(int_sqrt_fNext_48$DEQ),
|
|
.CLR(int_sqrt_fNext_48$CLR),
|
|
.D_OUT(int_sqrt_fNext_48$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_48$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_48$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_49
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_49(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_49$D_IN),
|
|
.ENQ(int_sqrt_fNext_49$ENQ),
|
|
.DEQ(int_sqrt_fNext_49$DEQ),
|
|
.CLR(int_sqrt_fNext_49$CLR),
|
|
.D_OUT(int_sqrt_fNext_49$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_49$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_49$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_5
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_5(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_5$D_IN),
|
|
.ENQ(int_sqrt_fNext_5$ENQ),
|
|
.DEQ(int_sqrt_fNext_5$DEQ),
|
|
.CLR(int_sqrt_fNext_5$CLR),
|
|
.D_OUT(int_sqrt_fNext_5$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_5$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_5$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_50
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_50(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_50$D_IN),
|
|
.ENQ(int_sqrt_fNext_50$ENQ),
|
|
.DEQ(int_sqrt_fNext_50$DEQ),
|
|
.CLR(int_sqrt_fNext_50$CLR),
|
|
.D_OUT(int_sqrt_fNext_50$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_50$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_50$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_51
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_51(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_51$D_IN),
|
|
.ENQ(int_sqrt_fNext_51$ENQ),
|
|
.DEQ(int_sqrt_fNext_51$DEQ),
|
|
.CLR(int_sqrt_fNext_51$CLR),
|
|
.D_OUT(int_sqrt_fNext_51$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_51$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_51$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_52
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_52(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_52$D_IN),
|
|
.ENQ(int_sqrt_fNext_52$ENQ),
|
|
.DEQ(int_sqrt_fNext_52$DEQ),
|
|
.CLR(int_sqrt_fNext_52$CLR),
|
|
.D_OUT(int_sqrt_fNext_52$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_52$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_52$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_53
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_53(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_53$D_IN),
|
|
.ENQ(int_sqrt_fNext_53$ENQ),
|
|
.DEQ(int_sqrt_fNext_53$DEQ),
|
|
.CLR(int_sqrt_fNext_53$CLR),
|
|
.D_OUT(int_sqrt_fNext_53$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_53$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_53$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_54
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_54(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_54$D_IN),
|
|
.ENQ(int_sqrt_fNext_54$ENQ),
|
|
.DEQ(int_sqrt_fNext_54$DEQ),
|
|
.CLR(int_sqrt_fNext_54$CLR),
|
|
.D_OUT(int_sqrt_fNext_54$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_54$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_54$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_55
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_55(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_55$D_IN),
|
|
.ENQ(int_sqrt_fNext_55$ENQ),
|
|
.DEQ(int_sqrt_fNext_55$DEQ),
|
|
.CLR(int_sqrt_fNext_55$CLR),
|
|
.D_OUT(int_sqrt_fNext_55$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_55$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_55$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_56
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_56(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_56$D_IN),
|
|
.ENQ(int_sqrt_fNext_56$ENQ),
|
|
.DEQ(int_sqrt_fNext_56$DEQ),
|
|
.CLR(int_sqrt_fNext_56$CLR),
|
|
.D_OUT(int_sqrt_fNext_56$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_56$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_56$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_57
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_57(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_57$D_IN),
|
|
.ENQ(int_sqrt_fNext_57$ENQ),
|
|
.DEQ(int_sqrt_fNext_57$DEQ),
|
|
.CLR(int_sqrt_fNext_57$CLR),
|
|
.D_OUT(int_sqrt_fNext_57$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_57$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_57$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_58
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_58(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_58$D_IN),
|
|
.ENQ(int_sqrt_fNext_58$ENQ),
|
|
.DEQ(int_sqrt_fNext_58$DEQ),
|
|
.CLR(int_sqrt_fNext_58$CLR),
|
|
.D_OUT(int_sqrt_fNext_58$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_58$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_58$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_6
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_6(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_6$D_IN),
|
|
.ENQ(int_sqrt_fNext_6$ENQ),
|
|
.DEQ(int_sqrt_fNext_6$DEQ),
|
|
.CLR(int_sqrt_fNext_6$CLR),
|
|
.D_OUT(int_sqrt_fNext_6$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_6$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_6$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_7
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_7(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_7$D_IN),
|
|
.ENQ(int_sqrt_fNext_7$ENQ),
|
|
.DEQ(int_sqrt_fNext_7$DEQ),
|
|
.CLR(int_sqrt_fNext_7$CLR),
|
|
.D_OUT(int_sqrt_fNext_7$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_7$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_7$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_8
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_8(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_8$D_IN),
|
|
.ENQ(int_sqrt_fNext_8$ENQ),
|
|
.DEQ(int_sqrt_fNext_8$DEQ),
|
|
.CLR(int_sqrt_fNext_8$CLR),
|
|
.D_OUT(int_sqrt_fNext_8$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_8$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_8$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fNext_9
|
|
FIFOL1 #(.width(32'd465)) int_sqrt_fNext_9(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fNext_9$D_IN),
|
|
.ENQ(int_sqrt_fNext_9$ENQ),
|
|
.DEQ(int_sqrt_fNext_9$DEQ),
|
|
.CLR(int_sqrt_fNext_9$CLR),
|
|
.D_OUT(int_sqrt_fNext_9$D_OUT),
|
|
.FULL_N(int_sqrt_fNext_9$FULL_N),
|
|
.EMPTY_N(int_sqrt_fNext_9$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fRequest
|
|
FIFOL1 #(.width(32'd116)) int_sqrt_fRequest(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fRequest$D_IN),
|
|
.ENQ(int_sqrt_fRequest$ENQ),
|
|
.DEQ(int_sqrt_fRequest$DEQ),
|
|
.CLR(int_sqrt_fRequest$CLR),
|
|
.D_OUT(int_sqrt_fRequest$D_OUT),
|
|
.FULL_N(int_sqrt_fRequest$FULL_N),
|
|
.EMPTY_N(int_sqrt_fRequest$EMPTY_N));
|
|
|
|
// submodule int_sqrt_fResponse
|
|
FIFOL1 #(.width(32'd117)) int_sqrt_fResponse(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_sqrt_fResponse$D_IN),
|
|
.ENQ(int_sqrt_fResponse$ENQ),
|
|
.DEQ(int_sqrt_fResponse$DEQ),
|
|
.CLR(int_sqrt_fResponse$CLR),
|
|
.D_OUT(int_sqrt_fResponse$D_OUT),
|
|
.FULL_N(int_sqrt_fResponse$FULL_N),
|
|
.EMPTY_N(int_sqrt_fResponse$EMPTY_N));
|
|
|
|
// rule RL_fpu_s5_stage
|
|
assign CAN_FIRE_RL_fpu_s5_stage =
|
|
fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ;
|
|
assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ;
|
|
|
|
// rule RL_fpu_s4_stage
|
|
assign CAN_FIRE_RL_fpu_s4_stage =
|
|
fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ;
|
|
assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ;
|
|
|
|
// rule RL_fpu_s3_stage
|
|
assign CAN_FIRE_RL_fpu_s3_stage =
|
|
fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N &&
|
|
(fpu_fState_S2$D_OUT[136] || int_sqrt_fResponse$EMPTY_N) ;
|
|
assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ;
|
|
|
|
// rule RL_int_sqrt_finish
|
|
assign CAN_FIRE_RL_int_sqrt_finish =
|
|
int_sqrt_fNext_58$EMPTY_N && int_sqrt_fResponse$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_finish = CAN_FIRE_RL_int_sqrt_finish ;
|
|
|
|
// rule RL_int_sqrt_work_58
|
|
assign CAN_FIRE_RL_int_sqrt_work_58 =
|
|
int_sqrt_fNext_57$EMPTY_N && int_sqrt_fNext_58$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_58 = CAN_FIRE_RL_int_sqrt_work_58 ;
|
|
|
|
// rule RL_int_sqrt_work_57
|
|
assign CAN_FIRE_RL_int_sqrt_work_57 =
|
|
int_sqrt_fNext_56$EMPTY_N && int_sqrt_fNext_57$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_57 = CAN_FIRE_RL_int_sqrt_work_57 ;
|
|
|
|
// rule RL_int_sqrt_work_56
|
|
assign CAN_FIRE_RL_int_sqrt_work_56 =
|
|
int_sqrt_fNext_55$EMPTY_N && int_sqrt_fNext_56$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_56 = CAN_FIRE_RL_int_sqrt_work_56 ;
|
|
|
|
// rule RL_int_sqrt_work_55
|
|
assign CAN_FIRE_RL_int_sqrt_work_55 =
|
|
int_sqrt_fNext_54$EMPTY_N && int_sqrt_fNext_55$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_55 = CAN_FIRE_RL_int_sqrt_work_55 ;
|
|
|
|
// rule RL_int_sqrt_work_54
|
|
assign CAN_FIRE_RL_int_sqrt_work_54 =
|
|
int_sqrt_fNext_53$EMPTY_N && int_sqrt_fNext_54$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_54 = CAN_FIRE_RL_int_sqrt_work_54 ;
|
|
|
|
// rule RL_int_sqrt_work_53
|
|
assign CAN_FIRE_RL_int_sqrt_work_53 =
|
|
int_sqrt_fNext_52$EMPTY_N && int_sqrt_fNext_53$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_53 = CAN_FIRE_RL_int_sqrt_work_53 ;
|
|
|
|
// rule RL_int_sqrt_work_52
|
|
assign CAN_FIRE_RL_int_sqrt_work_52 =
|
|
int_sqrt_fNext_51$EMPTY_N && int_sqrt_fNext_52$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_52 = CAN_FIRE_RL_int_sqrt_work_52 ;
|
|
|
|
// rule RL_int_sqrt_work_51
|
|
assign CAN_FIRE_RL_int_sqrt_work_51 =
|
|
int_sqrt_fNext_50$EMPTY_N && int_sqrt_fNext_51$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_51 = CAN_FIRE_RL_int_sqrt_work_51 ;
|
|
|
|
// rule RL_int_sqrt_work_50
|
|
assign CAN_FIRE_RL_int_sqrt_work_50 =
|
|
int_sqrt_fNext_49$EMPTY_N && int_sqrt_fNext_50$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_50 = CAN_FIRE_RL_int_sqrt_work_50 ;
|
|
|
|
// rule RL_int_sqrt_work_49
|
|
assign CAN_FIRE_RL_int_sqrt_work_49 =
|
|
int_sqrt_fNext_48$EMPTY_N && int_sqrt_fNext_49$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_49 = CAN_FIRE_RL_int_sqrt_work_49 ;
|
|
|
|
// rule RL_int_sqrt_work_48
|
|
assign CAN_FIRE_RL_int_sqrt_work_48 =
|
|
int_sqrt_fNext_47$EMPTY_N && int_sqrt_fNext_48$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_48 = CAN_FIRE_RL_int_sqrt_work_48 ;
|
|
|
|
// rule RL_int_sqrt_work_47
|
|
assign CAN_FIRE_RL_int_sqrt_work_47 =
|
|
int_sqrt_fNext_46$EMPTY_N && int_sqrt_fNext_47$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_47 = CAN_FIRE_RL_int_sqrt_work_47 ;
|
|
|
|
// rule RL_int_sqrt_work_46
|
|
assign CAN_FIRE_RL_int_sqrt_work_46 =
|
|
int_sqrt_fNext_45$EMPTY_N && int_sqrt_fNext_46$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_46 = CAN_FIRE_RL_int_sqrt_work_46 ;
|
|
|
|
// rule RL_int_sqrt_work_45
|
|
assign CAN_FIRE_RL_int_sqrt_work_45 =
|
|
int_sqrt_fNext_44$EMPTY_N && int_sqrt_fNext_45$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_45 = CAN_FIRE_RL_int_sqrt_work_45 ;
|
|
|
|
// rule RL_int_sqrt_work_44
|
|
assign CAN_FIRE_RL_int_sqrt_work_44 =
|
|
int_sqrt_fNext_43$EMPTY_N && int_sqrt_fNext_44$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_44 = CAN_FIRE_RL_int_sqrt_work_44 ;
|
|
|
|
// rule RL_int_sqrt_work_43
|
|
assign CAN_FIRE_RL_int_sqrt_work_43 =
|
|
int_sqrt_fNext_42$EMPTY_N && int_sqrt_fNext_43$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_43 = CAN_FIRE_RL_int_sqrt_work_43 ;
|
|
|
|
// rule RL_int_sqrt_work_42
|
|
assign CAN_FIRE_RL_int_sqrt_work_42 =
|
|
int_sqrt_fNext_41$EMPTY_N && int_sqrt_fNext_42$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_42 = CAN_FIRE_RL_int_sqrt_work_42 ;
|
|
|
|
// rule RL_int_sqrt_work_41
|
|
assign CAN_FIRE_RL_int_sqrt_work_41 =
|
|
int_sqrt_fNext_40$EMPTY_N && int_sqrt_fNext_41$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_41 = CAN_FIRE_RL_int_sqrt_work_41 ;
|
|
|
|
// rule RL_int_sqrt_work_40
|
|
assign CAN_FIRE_RL_int_sqrt_work_40 =
|
|
int_sqrt_fNext_39$EMPTY_N && int_sqrt_fNext_40$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_40 = CAN_FIRE_RL_int_sqrt_work_40 ;
|
|
|
|
// rule RL_int_sqrt_work_39
|
|
assign CAN_FIRE_RL_int_sqrt_work_39 =
|
|
int_sqrt_fNext_38$EMPTY_N && int_sqrt_fNext_39$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_39 = CAN_FIRE_RL_int_sqrt_work_39 ;
|
|
|
|
// rule RL_int_sqrt_work_38
|
|
assign CAN_FIRE_RL_int_sqrt_work_38 =
|
|
int_sqrt_fNext_37$EMPTY_N && int_sqrt_fNext_38$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_38 = CAN_FIRE_RL_int_sqrt_work_38 ;
|
|
|
|
// rule RL_int_sqrt_work_37
|
|
assign CAN_FIRE_RL_int_sqrt_work_37 =
|
|
int_sqrt_fNext_36$EMPTY_N && int_sqrt_fNext_37$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_37 = CAN_FIRE_RL_int_sqrt_work_37 ;
|
|
|
|
// rule RL_int_sqrt_work_36
|
|
assign CAN_FIRE_RL_int_sqrt_work_36 =
|
|
int_sqrt_fNext_35$EMPTY_N && int_sqrt_fNext_36$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_36 = CAN_FIRE_RL_int_sqrt_work_36 ;
|
|
|
|
// rule RL_int_sqrt_work_35
|
|
assign CAN_FIRE_RL_int_sqrt_work_35 =
|
|
int_sqrt_fNext_34$EMPTY_N && int_sqrt_fNext_35$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_35 = CAN_FIRE_RL_int_sqrt_work_35 ;
|
|
|
|
// rule RL_int_sqrt_work_34
|
|
assign CAN_FIRE_RL_int_sqrt_work_34 =
|
|
int_sqrt_fNext_33$EMPTY_N && int_sqrt_fNext_34$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_34 = CAN_FIRE_RL_int_sqrt_work_34 ;
|
|
|
|
// rule RL_int_sqrt_work_33
|
|
assign CAN_FIRE_RL_int_sqrt_work_33 =
|
|
int_sqrt_fNext_32$EMPTY_N && int_sqrt_fNext_33$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_33 = CAN_FIRE_RL_int_sqrt_work_33 ;
|
|
|
|
// rule RL_int_sqrt_work_32
|
|
assign CAN_FIRE_RL_int_sqrt_work_32 =
|
|
int_sqrt_fNext_31$EMPTY_N && int_sqrt_fNext_32$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_32 = CAN_FIRE_RL_int_sqrt_work_32 ;
|
|
|
|
// rule RL_int_sqrt_work_31
|
|
assign CAN_FIRE_RL_int_sqrt_work_31 =
|
|
int_sqrt_fNext_30$EMPTY_N && int_sqrt_fNext_31$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_31 = CAN_FIRE_RL_int_sqrt_work_31 ;
|
|
|
|
// rule RL_int_sqrt_work_30
|
|
assign CAN_FIRE_RL_int_sqrt_work_30 =
|
|
int_sqrt_fNext_29$EMPTY_N && int_sqrt_fNext_30$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_30 = CAN_FIRE_RL_int_sqrt_work_30 ;
|
|
|
|
// rule RL_int_sqrt_work_29
|
|
assign CAN_FIRE_RL_int_sqrt_work_29 =
|
|
int_sqrt_fNext_28$EMPTY_N && int_sqrt_fNext_29$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_29 = CAN_FIRE_RL_int_sqrt_work_29 ;
|
|
|
|
// rule RL_int_sqrt_work_28
|
|
assign CAN_FIRE_RL_int_sqrt_work_28 =
|
|
int_sqrt_fNext_27$EMPTY_N && int_sqrt_fNext_28$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_28 = CAN_FIRE_RL_int_sqrt_work_28 ;
|
|
|
|
// rule RL_int_sqrt_work_27
|
|
assign CAN_FIRE_RL_int_sqrt_work_27 =
|
|
int_sqrt_fNext_26$EMPTY_N && int_sqrt_fNext_27$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_27 = CAN_FIRE_RL_int_sqrt_work_27 ;
|
|
|
|
// rule RL_int_sqrt_work_26
|
|
assign CAN_FIRE_RL_int_sqrt_work_26 =
|
|
int_sqrt_fNext_25$EMPTY_N && int_sqrt_fNext_26$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_26 = CAN_FIRE_RL_int_sqrt_work_26 ;
|
|
|
|
// rule RL_int_sqrt_work_25
|
|
assign CAN_FIRE_RL_int_sqrt_work_25 =
|
|
int_sqrt_fNext_24$EMPTY_N && int_sqrt_fNext_25$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_25 = CAN_FIRE_RL_int_sqrt_work_25 ;
|
|
|
|
// rule RL_int_sqrt_work_24
|
|
assign CAN_FIRE_RL_int_sqrt_work_24 =
|
|
int_sqrt_fNext_23$EMPTY_N && int_sqrt_fNext_24$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_24 = CAN_FIRE_RL_int_sqrt_work_24 ;
|
|
|
|
// rule RL_int_sqrt_work_23
|
|
assign CAN_FIRE_RL_int_sqrt_work_23 =
|
|
int_sqrt_fNext_22$EMPTY_N && int_sqrt_fNext_23$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_23 = CAN_FIRE_RL_int_sqrt_work_23 ;
|
|
|
|
// rule RL_int_sqrt_work_22
|
|
assign CAN_FIRE_RL_int_sqrt_work_22 =
|
|
int_sqrt_fNext_21$EMPTY_N && int_sqrt_fNext_22$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_22 = CAN_FIRE_RL_int_sqrt_work_22 ;
|
|
|
|
// rule RL_int_sqrt_work_21
|
|
assign CAN_FIRE_RL_int_sqrt_work_21 =
|
|
int_sqrt_fNext_20$EMPTY_N && int_sqrt_fNext_21$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_21 = CAN_FIRE_RL_int_sqrt_work_21 ;
|
|
|
|
// rule RL_int_sqrt_work_20
|
|
assign CAN_FIRE_RL_int_sqrt_work_20 =
|
|
int_sqrt_fNext_19$EMPTY_N && int_sqrt_fNext_20$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_20 = CAN_FIRE_RL_int_sqrt_work_20 ;
|
|
|
|
// rule RL_int_sqrt_work_19
|
|
assign CAN_FIRE_RL_int_sqrt_work_19 =
|
|
int_sqrt_fNext_18$EMPTY_N && int_sqrt_fNext_19$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_19 = CAN_FIRE_RL_int_sqrt_work_19 ;
|
|
|
|
// rule RL_int_sqrt_work_18
|
|
assign CAN_FIRE_RL_int_sqrt_work_18 =
|
|
int_sqrt_fNext_17$EMPTY_N && int_sqrt_fNext_18$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_18 = CAN_FIRE_RL_int_sqrt_work_18 ;
|
|
|
|
// rule RL_int_sqrt_work_17
|
|
assign CAN_FIRE_RL_int_sqrt_work_17 =
|
|
int_sqrt_fNext_16$EMPTY_N && int_sqrt_fNext_17$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_17 = CAN_FIRE_RL_int_sqrt_work_17 ;
|
|
|
|
// rule RL_int_sqrt_work_16
|
|
assign CAN_FIRE_RL_int_sqrt_work_16 =
|
|
int_sqrt_fNext_15$EMPTY_N && int_sqrt_fNext_16$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_16 = CAN_FIRE_RL_int_sqrt_work_16 ;
|
|
|
|
// rule RL_int_sqrt_work_15
|
|
assign CAN_FIRE_RL_int_sqrt_work_15 =
|
|
int_sqrt_fNext_14$EMPTY_N && int_sqrt_fNext_15$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_15 = CAN_FIRE_RL_int_sqrt_work_15 ;
|
|
|
|
// rule RL_int_sqrt_work_14
|
|
assign CAN_FIRE_RL_int_sqrt_work_14 =
|
|
int_sqrt_fNext_13$EMPTY_N && int_sqrt_fNext_14$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_14 = CAN_FIRE_RL_int_sqrt_work_14 ;
|
|
|
|
// rule RL_int_sqrt_work_13
|
|
assign CAN_FIRE_RL_int_sqrt_work_13 =
|
|
int_sqrt_fNext_12$EMPTY_N && int_sqrt_fNext_13$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_13 = CAN_FIRE_RL_int_sqrt_work_13 ;
|
|
|
|
// rule RL_int_sqrt_work_12
|
|
assign CAN_FIRE_RL_int_sqrt_work_12 =
|
|
int_sqrt_fNext_11$EMPTY_N && int_sqrt_fNext_12$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_12 = CAN_FIRE_RL_int_sqrt_work_12 ;
|
|
|
|
// rule RL_int_sqrt_work_11
|
|
assign CAN_FIRE_RL_int_sqrt_work_11 =
|
|
int_sqrt_fNext_10$EMPTY_N && int_sqrt_fNext_11$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_11 = CAN_FIRE_RL_int_sqrt_work_11 ;
|
|
|
|
// rule RL_int_sqrt_work_10
|
|
assign CAN_FIRE_RL_int_sqrt_work_10 =
|
|
int_sqrt_fNext_9$EMPTY_N && int_sqrt_fNext_10$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_10 = CAN_FIRE_RL_int_sqrt_work_10 ;
|
|
|
|
// rule RL_int_sqrt_work_9
|
|
assign CAN_FIRE_RL_int_sqrt_work_9 =
|
|
int_sqrt_fNext_8$EMPTY_N && int_sqrt_fNext_9$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_9 = CAN_FIRE_RL_int_sqrt_work_9 ;
|
|
|
|
// rule RL_int_sqrt_work_8
|
|
assign CAN_FIRE_RL_int_sqrt_work_8 =
|
|
int_sqrt_fNext_7$EMPTY_N && int_sqrt_fNext_8$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_8 = CAN_FIRE_RL_int_sqrt_work_8 ;
|
|
|
|
// rule RL_int_sqrt_work_7
|
|
assign CAN_FIRE_RL_int_sqrt_work_7 =
|
|
int_sqrt_fNext_6$EMPTY_N && int_sqrt_fNext_7$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_7 = CAN_FIRE_RL_int_sqrt_work_7 ;
|
|
|
|
// rule RL_int_sqrt_work_6
|
|
assign CAN_FIRE_RL_int_sqrt_work_6 =
|
|
int_sqrt_fNext_5$EMPTY_N && int_sqrt_fNext_6$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_6 = CAN_FIRE_RL_int_sqrt_work_6 ;
|
|
|
|
// rule RL_int_sqrt_work_5
|
|
assign CAN_FIRE_RL_int_sqrt_work_5 =
|
|
int_sqrt_fNext_4$EMPTY_N && int_sqrt_fNext_5$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_5 = CAN_FIRE_RL_int_sqrt_work_5 ;
|
|
|
|
// rule RL_int_sqrt_work_4
|
|
assign CAN_FIRE_RL_int_sqrt_work_4 =
|
|
int_sqrt_fNext_3$EMPTY_N && int_sqrt_fNext_4$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_4 = CAN_FIRE_RL_int_sqrt_work_4 ;
|
|
|
|
// rule RL_int_sqrt_work_3
|
|
assign CAN_FIRE_RL_int_sqrt_work_3 =
|
|
int_sqrt_fNext_2$EMPTY_N && int_sqrt_fNext_3$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_3 = CAN_FIRE_RL_int_sqrt_work_3 ;
|
|
|
|
// rule RL_int_sqrt_work_2
|
|
assign CAN_FIRE_RL_int_sqrt_work_2 =
|
|
int_sqrt_fNext_1$EMPTY_N && int_sqrt_fNext_2$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_2 = CAN_FIRE_RL_int_sqrt_work_2 ;
|
|
|
|
// rule RL_int_sqrt_work_1
|
|
assign CAN_FIRE_RL_int_sqrt_work_1 =
|
|
int_sqrt_fNext_0$EMPTY_N && int_sqrt_fNext_1$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work_1 = CAN_FIRE_RL_int_sqrt_work_1 ;
|
|
|
|
// rule RL_int_sqrt_work
|
|
assign CAN_FIRE_RL_int_sqrt_work =
|
|
int_sqrt_fFirst$EMPTY_N && int_sqrt_fNext_0$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_work = CAN_FIRE_RL_int_sqrt_work ;
|
|
|
|
// rule RL_int_sqrt_start
|
|
assign CAN_FIRE_RL_int_sqrt_start =
|
|
int_sqrt_fRequest$EMPTY_N && int_sqrt_fFirst$FULL_N ;
|
|
assign WILL_FIRE_RL_int_sqrt_start = CAN_FIRE_RL_int_sqrt_start ;
|
|
|
|
// rule RL_fpu_s2_stage
|
|
assign CAN_FIRE_RL_fpu_s2_stage =
|
|
fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N &&
|
|
(fpu_fState_S1$D_OUT[194] || int_sqrt_fRequest$FULL_N) ;
|
|
assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ;
|
|
|
|
// rule RL_fpu_s1_stage
|
|
assign CAN_FIRE_RL_fpu_s1_stage =
|
|
fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ;
|
|
assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ;
|
|
|
|
// submodule fpu_fOperand_S0
|
|
assign fpu_fOperand_S0$D_IN = request_put ;
|
|
assign fpu_fOperand_S0$ENQ = EN_request_put ;
|
|
assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ;
|
|
assign fpu_fOperand_S0$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fResult_S5
|
|
assign fpu_fResult_S5$D_IN =
|
|
fpu_fState_S4$D_OUT[138] ?
|
|
fpu_fState_S4$D_OUT[137:69] :
|
|
{ (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ?
|
|
fpu_fState_S4$D_OUT[65:2] :
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15,
|
|
fpu_fState_S4$D_OUT[73:69] |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h76509 == 11'd2047 &&
|
|
_theResult___fst_sfd__h76510 == 52'd0,
|
|
1'd0,
|
|
fpu_fState_S4$D_OUT[64:54] != 11'd2047 &&
|
|
fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ;
|
|
assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ;
|
|
assign fpu_fResult_S5$DEQ = EN_response_get ;
|
|
assign fpu_fResult_S5$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fState_S1
|
|
assign fpu_fState_S1$D_IN =
|
|
(fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperand_S0$D_OUT[54:3] != 52'd0 &&
|
|
!fpu_fOperand_S0$D_OUT[54]) ?
|
|
{ 1'd1,
|
|
fpu_fOperand_S0$D_OUT[66:55],
|
|
sfd__h49989,
|
|
5'd16,
|
|
125'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } :
|
|
IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 ;
|
|
assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ;
|
|
assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ;
|
|
assign fpu_fState_S1$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fState_S2
|
|
assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[194:58] ;
|
|
assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ;
|
|
assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ;
|
|
assign fpu_fState_S2$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fState_S3
|
|
assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT, x__h66665 } ;
|
|
assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ;
|
|
assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ;
|
|
assign fpu_fState_S3$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fState_S4
|
|
assign fpu_fState_S4$D_IN =
|
|
{ fpu_fState_S3$D_OUT[195:131],
|
|
fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[130],
|
|
fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[129],
|
|
IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813,
|
|
fpu_fState_S3$D_OUT[125:122],
|
|
fpu_fState_S3$D_OUT[195] ?
|
|
fpu_fState_S3$D_OUT[121:59] :
|
|
IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820,
|
|
x__h75654 } ;
|
|
assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ;
|
|
assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ;
|
|
assign fpu_fState_S4$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fFirst
|
|
assign int_sqrt_fFirst$D_IN =
|
|
{ 1'd0,
|
|
116'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
int_sqrt_fRequest$D_OUT,
|
|
116'd0,
|
|
x__h402 } ;
|
|
assign int_sqrt_fFirst$ENQ = CAN_FIRE_RL_int_sqrt_start ;
|
|
assign int_sqrt_fFirst$DEQ = CAN_FIRE_RL_int_sqrt_work ;
|
|
assign int_sqrt_fFirst$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_0
|
|
assign int_sqrt_fNext_0$D_IN =
|
|
{ int_sqrt_fFirst$D_OUT[464] ||
|
|
int_sqrt_fFirst$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fFirst$D_OUT[464] ?
|
|
int_sqrt_fFirst$D_OUT[463:348] :
|
|
((int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fFirst$D_OUT[231:116] :
|
|
int_sqrt_fFirst$D_OUT[463:348]),
|
|
int_sqrt_fFirst$D_OUT[464] ?
|
|
int_sqrt_fFirst$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h25299,
|
|
(int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fFirst$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h25377, b__h25374 } } } ;
|
|
assign int_sqrt_fNext_0$ENQ = CAN_FIRE_RL_int_sqrt_work ;
|
|
assign int_sqrt_fNext_0$DEQ = CAN_FIRE_RL_int_sqrt_work_1 ;
|
|
assign int_sqrt_fNext_0$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_1
|
|
assign int_sqrt_fNext_1$D_IN =
|
|
{ int_sqrt_fNext_0$D_OUT[464] ||
|
|
int_sqrt_fNext_0$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_0$D_OUT[464] ?
|
|
int_sqrt_fNext_0$D_OUT[463:348] :
|
|
((int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_0$D_OUT[231:116] :
|
|
int_sqrt_fNext_0$D_OUT[463:348]),
|
|
int_sqrt_fNext_0$D_OUT[464] ?
|
|
int_sqrt_fNext_0$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h25701,
|
|
(int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_0$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h25777, b__h25774 } } } ;
|
|
assign int_sqrt_fNext_1$ENQ = CAN_FIRE_RL_int_sqrt_work_1 ;
|
|
assign int_sqrt_fNext_1$DEQ = CAN_FIRE_RL_int_sqrt_work_2 ;
|
|
assign int_sqrt_fNext_1$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_10
|
|
assign int_sqrt_fNext_10$D_IN =
|
|
{ int_sqrt_fNext_9$D_OUT[464] ||
|
|
int_sqrt_fNext_9$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_9$D_OUT[464] ?
|
|
int_sqrt_fNext_9$D_OUT[463:348] :
|
|
((int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_9$D_OUT[231:116] :
|
|
int_sqrt_fNext_9$D_OUT[463:348]),
|
|
int_sqrt_fNext_9$D_OUT[464] ?
|
|
int_sqrt_fNext_9$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h29301,
|
|
(int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_9$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h29377, b__h29374 } } } ;
|
|
assign int_sqrt_fNext_10$ENQ = CAN_FIRE_RL_int_sqrt_work_10 ;
|
|
assign int_sqrt_fNext_10$DEQ = CAN_FIRE_RL_int_sqrt_work_11 ;
|
|
assign int_sqrt_fNext_10$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_11
|
|
assign int_sqrt_fNext_11$D_IN =
|
|
{ int_sqrt_fNext_10$D_OUT[464] ||
|
|
int_sqrt_fNext_10$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_10$D_OUT[464] ?
|
|
int_sqrt_fNext_10$D_OUT[463:348] :
|
|
((int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_10$D_OUT[231:116] :
|
|
int_sqrt_fNext_10$D_OUT[463:348]),
|
|
int_sqrt_fNext_10$D_OUT[464] ?
|
|
int_sqrt_fNext_10$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h29701,
|
|
(int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_10$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h29777, b__h29774 } } } ;
|
|
assign int_sqrt_fNext_11$ENQ = CAN_FIRE_RL_int_sqrt_work_11 ;
|
|
assign int_sqrt_fNext_11$DEQ = CAN_FIRE_RL_int_sqrt_work_12 ;
|
|
assign int_sqrt_fNext_11$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_12
|
|
assign int_sqrt_fNext_12$D_IN =
|
|
{ int_sqrt_fNext_11$D_OUT[464] ||
|
|
int_sqrt_fNext_11$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_11$D_OUT[464] ?
|
|
int_sqrt_fNext_11$D_OUT[463:348] :
|
|
((int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_11$D_OUT[231:116] :
|
|
int_sqrt_fNext_11$D_OUT[463:348]),
|
|
int_sqrt_fNext_11$D_OUT[464] ?
|
|
int_sqrt_fNext_11$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h30101,
|
|
(int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_11$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h30177, b__h30174 } } } ;
|
|
assign int_sqrt_fNext_12$ENQ = CAN_FIRE_RL_int_sqrt_work_12 ;
|
|
assign int_sqrt_fNext_12$DEQ = CAN_FIRE_RL_int_sqrt_work_13 ;
|
|
assign int_sqrt_fNext_12$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_13
|
|
assign int_sqrt_fNext_13$D_IN =
|
|
{ int_sqrt_fNext_12$D_OUT[464] ||
|
|
int_sqrt_fNext_12$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_12$D_OUT[464] ?
|
|
int_sqrt_fNext_12$D_OUT[463:348] :
|
|
((int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_12$D_OUT[231:116] :
|
|
int_sqrt_fNext_12$D_OUT[463:348]),
|
|
int_sqrt_fNext_12$D_OUT[464] ?
|
|
int_sqrt_fNext_12$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h30501,
|
|
(int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_12$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h30577, b__h30574 } } } ;
|
|
assign int_sqrt_fNext_13$ENQ = CAN_FIRE_RL_int_sqrt_work_13 ;
|
|
assign int_sqrt_fNext_13$DEQ = CAN_FIRE_RL_int_sqrt_work_14 ;
|
|
assign int_sqrt_fNext_13$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_14
|
|
assign int_sqrt_fNext_14$D_IN =
|
|
{ int_sqrt_fNext_13$D_OUT[464] ||
|
|
int_sqrt_fNext_13$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_13$D_OUT[464] ?
|
|
int_sqrt_fNext_13$D_OUT[463:348] :
|
|
((int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_13$D_OUT[231:116] :
|
|
int_sqrt_fNext_13$D_OUT[463:348]),
|
|
int_sqrt_fNext_13$D_OUT[464] ?
|
|
int_sqrt_fNext_13$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h30901,
|
|
(int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_13$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h30977, b__h30974 } } } ;
|
|
assign int_sqrt_fNext_14$ENQ = CAN_FIRE_RL_int_sqrt_work_14 ;
|
|
assign int_sqrt_fNext_14$DEQ = CAN_FIRE_RL_int_sqrt_work_15 ;
|
|
assign int_sqrt_fNext_14$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_15
|
|
assign int_sqrt_fNext_15$D_IN =
|
|
{ int_sqrt_fNext_14$D_OUT[464] ||
|
|
int_sqrt_fNext_14$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_14$D_OUT[464] ?
|
|
int_sqrt_fNext_14$D_OUT[463:348] :
|
|
((int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_14$D_OUT[231:116] :
|
|
int_sqrt_fNext_14$D_OUT[463:348]),
|
|
int_sqrt_fNext_14$D_OUT[464] ?
|
|
int_sqrt_fNext_14$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h31301,
|
|
(int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_14$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h31377, b__h31374 } } } ;
|
|
assign int_sqrt_fNext_15$ENQ = CAN_FIRE_RL_int_sqrt_work_15 ;
|
|
assign int_sqrt_fNext_15$DEQ = CAN_FIRE_RL_int_sqrt_work_16 ;
|
|
assign int_sqrt_fNext_15$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_16
|
|
assign int_sqrt_fNext_16$D_IN =
|
|
{ int_sqrt_fNext_15$D_OUT[464] ||
|
|
int_sqrt_fNext_15$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_15$D_OUT[464] ?
|
|
int_sqrt_fNext_15$D_OUT[463:348] :
|
|
((int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_15$D_OUT[231:116] :
|
|
int_sqrt_fNext_15$D_OUT[463:348]),
|
|
int_sqrt_fNext_15$D_OUT[464] ?
|
|
int_sqrt_fNext_15$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h31701,
|
|
(int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_15$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h31777, b__h31774 } } } ;
|
|
assign int_sqrt_fNext_16$ENQ = CAN_FIRE_RL_int_sqrt_work_16 ;
|
|
assign int_sqrt_fNext_16$DEQ = CAN_FIRE_RL_int_sqrt_work_17 ;
|
|
assign int_sqrt_fNext_16$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_17
|
|
assign int_sqrt_fNext_17$D_IN =
|
|
{ int_sqrt_fNext_16$D_OUT[464] ||
|
|
int_sqrt_fNext_16$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_16$D_OUT[464] ?
|
|
int_sqrt_fNext_16$D_OUT[463:348] :
|
|
((int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_16$D_OUT[231:116] :
|
|
int_sqrt_fNext_16$D_OUT[463:348]),
|
|
int_sqrt_fNext_16$D_OUT[464] ?
|
|
int_sqrt_fNext_16$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h32101,
|
|
(int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_16$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h32177, b__h32174 } } } ;
|
|
assign int_sqrt_fNext_17$ENQ = CAN_FIRE_RL_int_sqrt_work_17 ;
|
|
assign int_sqrt_fNext_17$DEQ = CAN_FIRE_RL_int_sqrt_work_18 ;
|
|
assign int_sqrt_fNext_17$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_18
|
|
assign int_sqrt_fNext_18$D_IN =
|
|
{ int_sqrt_fNext_17$D_OUT[464] ||
|
|
int_sqrt_fNext_17$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_17$D_OUT[464] ?
|
|
int_sqrt_fNext_17$D_OUT[463:348] :
|
|
((int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_17$D_OUT[231:116] :
|
|
int_sqrt_fNext_17$D_OUT[463:348]),
|
|
int_sqrt_fNext_17$D_OUT[464] ?
|
|
int_sqrt_fNext_17$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h32501,
|
|
(int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_17$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h32577, b__h32574 } } } ;
|
|
assign int_sqrt_fNext_18$ENQ = CAN_FIRE_RL_int_sqrt_work_18 ;
|
|
assign int_sqrt_fNext_18$DEQ = CAN_FIRE_RL_int_sqrt_work_19 ;
|
|
assign int_sqrt_fNext_18$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_19
|
|
assign int_sqrt_fNext_19$D_IN =
|
|
{ int_sqrt_fNext_18$D_OUT[464] ||
|
|
int_sqrt_fNext_18$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_18$D_OUT[464] ?
|
|
int_sqrt_fNext_18$D_OUT[463:348] :
|
|
((int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_18$D_OUT[231:116] :
|
|
int_sqrt_fNext_18$D_OUT[463:348]),
|
|
int_sqrt_fNext_18$D_OUT[464] ?
|
|
int_sqrt_fNext_18$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h32901,
|
|
(int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_18$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h32977, b__h32974 } } } ;
|
|
assign int_sqrt_fNext_19$ENQ = CAN_FIRE_RL_int_sqrt_work_19 ;
|
|
assign int_sqrt_fNext_19$DEQ = CAN_FIRE_RL_int_sqrt_work_20 ;
|
|
assign int_sqrt_fNext_19$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_2
|
|
assign int_sqrt_fNext_2$D_IN =
|
|
{ int_sqrt_fNext_1$D_OUT[464] ||
|
|
int_sqrt_fNext_1$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_1$D_OUT[464] ?
|
|
int_sqrt_fNext_1$D_OUT[463:348] :
|
|
((int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_1$D_OUT[231:116] :
|
|
int_sqrt_fNext_1$D_OUT[463:348]),
|
|
int_sqrt_fNext_1$D_OUT[464] ?
|
|
int_sqrt_fNext_1$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h26101,
|
|
(int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_1$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h26177, b__h26174 } } } ;
|
|
assign int_sqrt_fNext_2$ENQ = CAN_FIRE_RL_int_sqrt_work_2 ;
|
|
assign int_sqrt_fNext_2$DEQ = CAN_FIRE_RL_int_sqrt_work_3 ;
|
|
assign int_sqrt_fNext_2$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_20
|
|
assign int_sqrt_fNext_20$D_IN =
|
|
{ int_sqrt_fNext_19$D_OUT[464] ||
|
|
int_sqrt_fNext_19$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_19$D_OUT[464] ?
|
|
int_sqrt_fNext_19$D_OUT[463:348] :
|
|
((int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_19$D_OUT[231:116] :
|
|
int_sqrt_fNext_19$D_OUT[463:348]),
|
|
int_sqrt_fNext_19$D_OUT[464] ?
|
|
int_sqrt_fNext_19$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h33301,
|
|
(int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_19$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h33377, b__h33374 } } } ;
|
|
assign int_sqrt_fNext_20$ENQ = CAN_FIRE_RL_int_sqrt_work_20 ;
|
|
assign int_sqrt_fNext_20$DEQ = CAN_FIRE_RL_int_sqrt_work_21 ;
|
|
assign int_sqrt_fNext_20$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_21
|
|
assign int_sqrt_fNext_21$D_IN =
|
|
{ int_sqrt_fNext_20$D_OUT[464] ||
|
|
int_sqrt_fNext_20$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_20$D_OUT[464] ?
|
|
int_sqrt_fNext_20$D_OUT[463:348] :
|
|
((int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_20$D_OUT[231:116] :
|
|
int_sqrt_fNext_20$D_OUT[463:348]),
|
|
int_sqrt_fNext_20$D_OUT[464] ?
|
|
int_sqrt_fNext_20$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h33701,
|
|
(int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_20$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h33777, b__h33774 } } } ;
|
|
assign int_sqrt_fNext_21$ENQ = CAN_FIRE_RL_int_sqrt_work_21 ;
|
|
assign int_sqrt_fNext_21$DEQ = CAN_FIRE_RL_int_sqrt_work_22 ;
|
|
assign int_sqrt_fNext_21$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_22
|
|
assign int_sqrt_fNext_22$D_IN =
|
|
{ int_sqrt_fNext_21$D_OUT[464] ||
|
|
int_sqrt_fNext_21$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_21$D_OUT[464] ?
|
|
int_sqrt_fNext_21$D_OUT[463:348] :
|
|
((int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_21$D_OUT[231:116] :
|
|
int_sqrt_fNext_21$D_OUT[463:348]),
|
|
int_sqrt_fNext_21$D_OUT[464] ?
|
|
int_sqrt_fNext_21$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h34101,
|
|
(int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_21$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h34177, b__h34174 } } } ;
|
|
assign int_sqrt_fNext_22$ENQ = CAN_FIRE_RL_int_sqrt_work_22 ;
|
|
assign int_sqrt_fNext_22$DEQ = CAN_FIRE_RL_int_sqrt_work_23 ;
|
|
assign int_sqrt_fNext_22$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_23
|
|
assign int_sqrt_fNext_23$D_IN =
|
|
{ int_sqrt_fNext_22$D_OUT[464] ||
|
|
int_sqrt_fNext_22$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_22$D_OUT[464] ?
|
|
int_sqrt_fNext_22$D_OUT[463:348] :
|
|
((int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_22$D_OUT[231:116] :
|
|
int_sqrt_fNext_22$D_OUT[463:348]),
|
|
int_sqrt_fNext_22$D_OUT[464] ?
|
|
int_sqrt_fNext_22$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h34501,
|
|
(int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_22$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h34577, b__h34574 } } } ;
|
|
assign int_sqrt_fNext_23$ENQ = CAN_FIRE_RL_int_sqrt_work_23 ;
|
|
assign int_sqrt_fNext_23$DEQ = CAN_FIRE_RL_int_sqrt_work_24 ;
|
|
assign int_sqrt_fNext_23$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_24
|
|
assign int_sqrt_fNext_24$D_IN =
|
|
{ int_sqrt_fNext_23$D_OUT[464] ||
|
|
int_sqrt_fNext_23$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_23$D_OUT[464] ?
|
|
int_sqrt_fNext_23$D_OUT[463:348] :
|
|
((int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_23$D_OUT[231:116] :
|
|
int_sqrt_fNext_23$D_OUT[463:348]),
|
|
int_sqrt_fNext_23$D_OUT[464] ?
|
|
int_sqrt_fNext_23$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h34901,
|
|
(int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_23$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h34977, b__h34974 } } } ;
|
|
assign int_sqrt_fNext_24$ENQ = CAN_FIRE_RL_int_sqrt_work_24 ;
|
|
assign int_sqrt_fNext_24$DEQ = CAN_FIRE_RL_int_sqrt_work_25 ;
|
|
assign int_sqrt_fNext_24$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_25
|
|
assign int_sqrt_fNext_25$D_IN =
|
|
{ int_sqrt_fNext_24$D_OUT[464] ||
|
|
int_sqrt_fNext_24$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_24$D_OUT[464] ?
|
|
int_sqrt_fNext_24$D_OUT[463:348] :
|
|
((int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_24$D_OUT[231:116] :
|
|
int_sqrt_fNext_24$D_OUT[463:348]),
|
|
int_sqrt_fNext_24$D_OUT[464] ?
|
|
int_sqrt_fNext_24$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h35301,
|
|
(int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_24$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h35377, b__h35374 } } } ;
|
|
assign int_sqrt_fNext_25$ENQ = CAN_FIRE_RL_int_sqrt_work_25 ;
|
|
assign int_sqrt_fNext_25$DEQ = CAN_FIRE_RL_int_sqrt_work_26 ;
|
|
assign int_sqrt_fNext_25$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_26
|
|
assign int_sqrt_fNext_26$D_IN =
|
|
{ int_sqrt_fNext_25$D_OUT[464] ||
|
|
int_sqrt_fNext_25$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_25$D_OUT[464] ?
|
|
int_sqrt_fNext_25$D_OUT[463:348] :
|
|
((int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_25$D_OUT[231:116] :
|
|
int_sqrt_fNext_25$D_OUT[463:348]),
|
|
int_sqrt_fNext_25$D_OUT[464] ?
|
|
int_sqrt_fNext_25$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h35701,
|
|
(int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_25$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h35777, b__h35774 } } } ;
|
|
assign int_sqrt_fNext_26$ENQ = CAN_FIRE_RL_int_sqrt_work_26 ;
|
|
assign int_sqrt_fNext_26$DEQ = CAN_FIRE_RL_int_sqrt_work_27 ;
|
|
assign int_sqrt_fNext_26$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_27
|
|
assign int_sqrt_fNext_27$D_IN =
|
|
{ int_sqrt_fNext_26$D_OUT[464] ||
|
|
int_sqrt_fNext_26$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_26$D_OUT[464] ?
|
|
int_sqrt_fNext_26$D_OUT[463:348] :
|
|
((int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_26$D_OUT[231:116] :
|
|
int_sqrt_fNext_26$D_OUT[463:348]),
|
|
int_sqrt_fNext_26$D_OUT[464] ?
|
|
int_sqrt_fNext_26$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h36101,
|
|
(int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_26$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h36177, b__h36174 } } } ;
|
|
assign int_sqrt_fNext_27$ENQ = CAN_FIRE_RL_int_sqrt_work_27 ;
|
|
assign int_sqrt_fNext_27$DEQ = CAN_FIRE_RL_int_sqrt_work_28 ;
|
|
assign int_sqrt_fNext_27$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_28
|
|
assign int_sqrt_fNext_28$D_IN =
|
|
{ int_sqrt_fNext_27$D_OUT[464] ||
|
|
int_sqrt_fNext_27$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_27$D_OUT[464] ?
|
|
int_sqrt_fNext_27$D_OUT[463:348] :
|
|
((int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_27$D_OUT[231:116] :
|
|
int_sqrt_fNext_27$D_OUT[463:348]),
|
|
int_sqrt_fNext_27$D_OUT[464] ?
|
|
int_sqrt_fNext_27$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h36501,
|
|
(int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_27$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h36577, b__h36574 } } } ;
|
|
assign int_sqrt_fNext_28$ENQ = CAN_FIRE_RL_int_sqrt_work_28 ;
|
|
assign int_sqrt_fNext_28$DEQ = CAN_FIRE_RL_int_sqrt_work_29 ;
|
|
assign int_sqrt_fNext_28$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_29
|
|
assign int_sqrt_fNext_29$D_IN =
|
|
{ int_sqrt_fNext_28$D_OUT[464] ||
|
|
int_sqrt_fNext_28$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_28$D_OUT[464] ?
|
|
int_sqrt_fNext_28$D_OUT[463:348] :
|
|
((int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_28$D_OUT[231:116] :
|
|
int_sqrt_fNext_28$D_OUT[463:348]),
|
|
int_sqrt_fNext_28$D_OUT[464] ?
|
|
int_sqrt_fNext_28$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h36901,
|
|
(int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_28$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h36977, b__h36974 } } } ;
|
|
assign int_sqrt_fNext_29$ENQ = CAN_FIRE_RL_int_sqrt_work_29 ;
|
|
assign int_sqrt_fNext_29$DEQ = CAN_FIRE_RL_int_sqrt_work_30 ;
|
|
assign int_sqrt_fNext_29$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_3
|
|
assign int_sqrt_fNext_3$D_IN =
|
|
{ int_sqrt_fNext_2$D_OUT[464] ||
|
|
int_sqrt_fNext_2$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_2$D_OUT[464] ?
|
|
int_sqrt_fNext_2$D_OUT[463:348] :
|
|
((int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_2$D_OUT[231:116] :
|
|
int_sqrt_fNext_2$D_OUT[463:348]),
|
|
int_sqrt_fNext_2$D_OUT[464] ?
|
|
int_sqrt_fNext_2$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h26501,
|
|
(int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_2$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h26577, b__h26574 } } } ;
|
|
assign int_sqrt_fNext_3$ENQ = CAN_FIRE_RL_int_sqrt_work_3 ;
|
|
assign int_sqrt_fNext_3$DEQ = CAN_FIRE_RL_int_sqrt_work_4 ;
|
|
assign int_sqrt_fNext_3$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_30
|
|
assign int_sqrt_fNext_30$D_IN =
|
|
{ int_sqrt_fNext_29$D_OUT[464] ||
|
|
int_sqrt_fNext_29$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_29$D_OUT[464] ?
|
|
int_sqrt_fNext_29$D_OUT[463:348] :
|
|
((int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_29$D_OUT[231:116] :
|
|
int_sqrt_fNext_29$D_OUT[463:348]),
|
|
int_sqrt_fNext_29$D_OUT[464] ?
|
|
int_sqrt_fNext_29$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h37301,
|
|
(int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_29$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h37377, b__h37374 } } } ;
|
|
assign int_sqrt_fNext_30$ENQ = CAN_FIRE_RL_int_sqrt_work_30 ;
|
|
assign int_sqrt_fNext_30$DEQ = CAN_FIRE_RL_int_sqrt_work_31 ;
|
|
assign int_sqrt_fNext_30$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_31
|
|
assign int_sqrt_fNext_31$D_IN =
|
|
{ int_sqrt_fNext_30$D_OUT[464] ||
|
|
int_sqrt_fNext_30$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_30$D_OUT[464] ?
|
|
int_sqrt_fNext_30$D_OUT[463:348] :
|
|
((int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_30$D_OUT[231:116] :
|
|
int_sqrt_fNext_30$D_OUT[463:348]),
|
|
int_sqrt_fNext_30$D_OUT[464] ?
|
|
int_sqrt_fNext_30$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h37701,
|
|
(int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_30$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h37777, b__h37774 } } } ;
|
|
assign int_sqrt_fNext_31$ENQ = CAN_FIRE_RL_int_sqrt_work_31 ;
|
|
assign int_sqrt_fNext_31$DEQ = CAN_FIRE_RL_int_sqrt_work_32 ;
|
|
assign int_sqrt_fNext_31$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_32
|
|
assign int_sqrt_fNext_32$D_IN =
|
|
{ int_sqrt_fNext_31$D_OUT[464] ||
|
|
int_sqrt_fNext_31$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_31$D_OUT[464] ?
|
|
int_sqrt_fNext_31$D_OUT[463:348] :
|
|
((int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_31$D_OUT[231:116] :
|
|
int_sqrt_fNext_31$D_OUT[463:348]),
|
|
int_sqrt_fNext_31$D_OUT[464] ?
|
|
int_sqrt_fNext_31$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h38101,
|
|
(int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_31$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h38177, b__h38174 } } } ;
|
|
assign int_sqrt_fNext_32$ENQ = CAN_FIRE_RL_int_sqrt_work_32 ;
|
|
assign int_sqrt_fNext_32$DEQ = CAN_FIRE_RL_int_sqrt_work_33 ;
|
|
assign int_sqrt_fNext_32$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_33
|
|
assign int_sqrt_fNext_33$D_IN =
|
|
{ int_sqrt_fNext_32$D_OUT[464] ||
|
|
int_sqrt_fNext_32$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_32$D_OUT[464] ?
|
|
int_sqrt_fNext_32$D_OUT[463:348] :
|
|
((int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_32$D_OUT[231:116] :
|
|
int_sqrt_fNext_32$D_OUT[463:348]),
|
|
int_sqrt_fNext_32$D_OUT[464] ?
|
|
int_sqrt_fNext_32$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h38501,
|
|
(int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_32$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h38577, b__h38574 } } } ;
|
|
assign int_sqrt_fNext_33$ENQ = CAN_FIRE_RL_int_sqrt_work_33 ;
|
|
assign int_sqrt_fNext_33$DEQ = CAN_FIRE_RL_int_sqrt_work_34 ;
|
|
assign int_sqrt_fNext_33$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_34
|
|
assign int_sqrt_fNext_34$D_IN =
|
|
{ int_sqrt_fNext_33$D_OUT[464] ||
|
|
int_sqrt_fNext_33$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_33$D_OUT[464] ?
|
|
int_sqrt_fNext_33$D_OUT[463:348] :
|
|
((int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_33$D_OUT[231:116] :
|
|
int_sqrt_fNext_33$D_OUT[463:348]),
|
|
int_sqrt_fNext_33$D_OUT[464] ?
|
|
int_sqrt_fNext_33$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h38901,
|
|
(int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_33$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h38977, b__h38974 } } } ;
|
|
assign int_sqrt_fNext_34$ENQ = CAN_FIRE_RL_int_sqrt_work_34 ;
|
|
assign int_sqrt_fNext_34$DEQ = CAN_FIRE_RL_int_sqrt_work_35 ;
|
|
assign int_sqrt_fNext_34$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_35
|
|
assign int_sqrt_fNext_35$D_IN =
|
|
{ int_sqrt_fNext_34$D_OUT[464] ||
|
|
int_sqrt_fNext_34$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_34$D_OUT[464] ?
|
|
int_sqrt_fNext_34$D_OUT[463:348] :
|
|
((int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_34$D_OUT[231:116] :
|
|
int_sqrt_fNext_34$D_OUT[463:348]),
|
|
int_sqrt_fNext_34$D_OUT[464] ?
|
|
int_sqrt_fNext_34$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h39301,
|
|
(int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_34$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h39377, b__h39374 } } } ;
|
|
assign int_sqrt_fNext_35$ENQ = CAN_FIRE_RL_int_sqrt_work_35 ;
|
|
assign int_sqrt_fNext_35$DEQ = CAN_FIRE_RL_int_sqrt_work_36 ;
|
|
assign int_sqrt_fNext_35$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_36
|
|
assign int_sqrt_fNext_36$D_IN =
|
|
{ int_sqrt_fNext_35$D_OUT[464] ||
|
|
int_sqrt_fNext_35$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_35$D_OUT[464] ?
|
|
int_sqrt_fNext_35$D_OUT[463:348] :
|
|
((int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_35$D_OUT[231:116] :
|
|
int_sqrt_fNext_35$D_OUT[463:348]),
|
|
int_sqrt_fNext_35$D_OUT[464] ?
|
|
int_sqrt_fNext_35$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h39701,
|
|
(int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_35$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h39777, b__h39774 } } } ;
|
|
assign int_sqrt_fNext_36$ENQ = CAN_FIRE_RL_int_sqrt_work_36 ;
|
|
assign int_sqrt_fNext_36$DEQ = CAN_FIRE_RL_int_sqrt_work_37 ;
|
|
assign int_sqrt_fNext_36$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_37
|
|
assign int_sqrt_fNext_37$D_IN =
|
|
{ int_sqrt_fNext_36$D_OUT[464] ||
|
|
int_sqrt_fNext_36$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_36$D_OUT[464] ?
|
|
int_sqrt_fNext_36$D_OUT[463:348] :
|
|
((int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_36$D_OUT[231:116] :
|
|
int_sqrt_fNext_36$D_OUT[463:348]),
|
|
int_sqrt_fNext_36$D_OUT[464] ?
|
|
int_sqrt_fNext_36$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h40101,
|
|
(int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_36$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h40177, b__h40174 } } } ;
|
|
assign int_sqrt_fNext_37$ENQ = CAN_FIRE_RL_int_sqrt_work_37 ;
|
|
assign int_sqrt_fNext_37$DEQ = CAN_FIRE_RL_int_sqrt_work_38 ;
|
|
assign int_sqrt_fNext_37$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_38
|
|
assign int_sqrt_fNext_38$D_IN =
|
|
{ int_sqrt_fNext_37$D_OUT[464] ||
|
|
int_sqrt_fNext_37$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_37$D_OUT[464] ?
|
|
int_sqrt_fNext_37$D_OUT[463:348] :
|
|
((int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_37$D_OUT[231:116] :
|
|
int_sqrt_fNext_37$D_OUT[463:348]),
|
|
int_sqrt_fNext_37$D_OUT[464] ?
|
|
int_sqrt_fNext_37$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h40501,
|
|
(int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_37$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h40577, b__h40574 } } } ;
|
|
assign int_sqrt_fNext_38$ENQ = CAN_FIRE_RL_int_sqrt_work_38 ;
|
|
assign int_sqrt_fNext_38$DEQ = CAN_FIRE_RL_int_sqrt_work_39 ;
|
|
assign int_sqrt_fNext_38$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_39
|
|
assign int_sqrt_fNext_39$D_IN =
|
|
{ int_sqrt_fNext_38$D_OUT[464] ||
|
|
int_sqrt_fNext_38$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_38$D_OUT[464] ?
|
|
int_sqrt_fNext_38$D_OUT[463:348] :
|
|
((int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_38$D_OUT[231:116] :
|
|
int_sqrt_fNext_38$D_OUT[463:348]),
|
|
int_sqrt_fNext_38$D_OUT[464] ?
|
|
int_sqrt_fNext_38$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h40901,
|
|
(int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_38$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h40977, b__h40974 } } } ;
|
|
assign int_sqrt_fNext_39$ENQ = CAN_FIRE_RL_int_sqrt_work_39 ;
|
|
assign int_sqrt_fNext_39$DEQ = CAN_FIRE_RL_int_sqrt_work_40 ;
|
|
assign int_sqrt_fNext_39$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_4
|
|
assign int_sqrt_fNext_4$D_IN =
|
|
{ int_sqrt_fNext_3$D_OUT[464] ||
|
|
int_sqrt_fNext_3$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_3$D_OUT[464] ?
|
|
int_sqrt_fNext_3$D_OUT[463:348] :
|
|
((int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_3$D_OUT[231:116] :
|
|
int_sqrt_fNext_3$D_OUT[463:348]),
|
|
int_sqrt_fNext_3$D_OUT[464] ?
|
|
int_sqrt_fNext_3$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h26901,
|
|
(int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_3$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h26977, b__h26974 } } } ;
|
|
assign int_sqrt_fNext_4$ENQ = CAN_FIRE_RL_int_sqrt_work_4 ;
|
|
assign int_sqrt_fNext_4$DEQ = CAN_FIRE_RL_int_sqrt_work_5 ;
|
|
assign int_sqrt_fNext_4$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_40
|
|
assign int_sqrt_fNext_40$D_IN =
|
|
{ int_sqrt_fNext_39$D_OUT[464] ||
|
|
int_sqrt_fNext_39$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_39$D_OUT[464] ?
|
|
int_sqrt_fNext_39$D_OUT[463:348] :
|
|
((int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_39$D_OUT[231:116] :
|
|
int_sqrt_fNext_39$D_OUT[463:348]),
|
|
int_sqrt_fNext_39$D_OUT[464] ?
|
|
int_sqrt_fNext_39$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h41301,
|
|
(int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_39$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h41377, b__h41374 } } } ;
|
|
assign int_sqrt_fNext_40$ENQ = CAN_FIRE_RL_int_sqrt_work_40 ;
|
|
assign int_sqrt_fNext_40$DEQ = CAN_FIRE_RL_int_sqrt_work_41 ;
|
|
assign int_sqrt_fNext_40$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_41
|
|
assign int_sqrt_fNext_41$D_IN =
|
|
{ int_sqrt_fNext_40$D_OUT[464] ||
|
|
int_sqrt_fNext_40$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_40$D_OUT[464] ?
|
|
int_sqrt_fNext_40$D_OUT[463:348] :
|
|
((int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_40$D_OUT[231:116] :
|
|
int_sqrt_fNext_40$D_OUT[463:348]),
|
|
int_sqrt_fNext_40$D_OUT[464] ?
|
|
int_sqrt_fNext_40$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h41701,
|
|
(int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_40$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h41777, b__h41774 } } } ;
|
|
assign int_sqrt_fNext_41$ENQ = CAN_FIRE_RL_int_sqrt_work_41 ;
|
|
assign int_sqrt_fNext_41$DEQ = CAN_FIRE_RL_int_sqrt_work_42 ;
|
|
assign int_sqrt_fNext_41$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_42
|
|
assign int_sqrt_fNext_42$D_IN =
|
|
{ int_sqrt_fNext_41$D_OUT[464] ||
|
|
int_sqrt_fNext_41$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_41$D_OUT[464] ?
|
|
int_sqrt_fNext_41$D_OUT[463:348] :
|
|
((int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_41$D_OUT[231:116] :
|
|
int_sqrt_fNext_41$D_OUT[463:348]),
|
|
int_sqrt_fNext_41$D_OUT[464] ?
|
|
int_sqrt_fNext_41$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h42101,
|
|
(int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_41$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h42177, b__h42174 } } } ;
|
|
assign int_sqrt_fNext_42$ENQ = CAN_FIRE_RL_int_sqrt_work_42 ;
|
|
assign int_sqrt_fNext_42$DEQ = CAN_FIRE_RL_int_sqrt_work_43 ;
|
|
assign int_sqrt_fNext_42$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_43
|
|
assign int_sqrt_fNext_43$D_IN =
|
|
{ int_sqrt_fNext_42$D_OUT[464] ||
|
|
int_sqrt_fNext_42$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_42$D_OUT[464] ?
|
|
int_sqrt_fNext_42$D_OUT[463:348] :
|
|
((int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_42$D_OUT[231:116] :
|
|
int_sqrt_fNext_42$D_OUT[463:348]),
|
|
int_sqrt_fNext_42$D_OUT[464] ?
|
|
int_sqrt_fNext_42$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h42501,
|
|
(int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_42$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h42577, b__h42574 } } } ;
|
|
assign int_sqrt_fNext_43$ENQ = CAN_FIRE_RL_int_sqrt_work_43 ;
|
|
assign int_sqrt_fNext_43$DEQ = CAN_FIRE_RL_int_sqrt_work_44 ;
|
|
assign int_sqrt_fNext_43$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_44
|
|
assign int_sqrt_fNext_44$D_IN =
|
|
{ int_sqrt_fNext_43$D_OUT[464] ||
|
|
int_sqrt_fNext_43$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_43$D_OUT[464] ?
|
|
int_sqrt_fNext_43$D_OUT[463:348] :
|
|
((int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_43$D_OUT[231:116] :
|
|
int_sqrt_fNext_43$D_OUT[463:348]),
|
|
int_sqrt_fNext_43$D_OUT[464] ?
|
|
int_sqrt_fNext_43$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h42901,
|
|
(int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_43$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h42977, b__h42974 } } } ;
|
|
assign int_sqrt_fNext_44$ENQ = CAN_FIRE_RL_int_sqrt_work_44 ;
|
|
assign int_sqrt_fNext_44$DEQ = CAN_FIRE_RL_int_sqrt_work_45 ;
|
|
assign int_sqrt_fNext_44$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_45
|
|
assign int_sqrt_fNext_45$D_IN =
|
|
{ int_sqrt_fNext_44$D_OUT[464] ||
|
|
int_sqrt_fNext_44$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_44$D_OUT[464] ?
|
|
int_sqrt_fNext_44$D_OUT[463:348] :
|
|
((int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_44$D_OUT[231:116] :
|
|
int_sqrt_fNext_44$D_OUT[463:348]),
|
|
int_sqrt_fNext_44$D_OUT[464] ?
|
|
int_sqrt_fNext_44$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h43301,
|
|
(int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_44$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h43377, b__h43374 } } } ;
|
|
assign int_sqrt_fNext_45$ENQ = CAN_FIRE_RL_int_sqrt_work_45 ;
|
|
assign int_sqrt_fNext_45$DEQ = CAN_FIRE_RL_int_sqrt_work_46 ;
|
|
assign int_sqrt_fNext_45$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_46
|
|
assign int_sqrt_fNext_46$D_IN =
|
|
{ int_sqrt_fNext_45$D_OUT[464] ||
|
|
int_sqrt_fNext_45$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_45$D_OUT[464] ?
|
|
int_sqrt_fNext_45$D_OUT[463:348] :
|
|
((int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_45$D_OUT[231:116] :
|
|
int_sqrt_fNext_45$D_OUT[463:348]),
|
|
int_sqrt_fNext_45$D_OUT[464] ?
|
|
int_sqrt_fNext_45$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h43701,
|
|
(int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_45$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h43777, b__h43774 } } } ;
|
|
assign int_sqrt_fNext_46$ENQ = CAN_FIRE_RL_int_sqrt_work_46 ;
|
|
assign int_sqrt_fNext_46$DEQ = CAN_FIRE_RL_int_sqrt_work_47 ;
|
|
assign int_sqrt_fNext_46$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_47
|
|
assign int_sqrt_fNext_47$D_IN =
|
|
{ int_sqrt_fNext_46$D_OUT[464] ||
|
|
int_sqrt_fNext_46$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_46$D_OUT[464] ?
|
|
int_sqrt_fNext_46$D_OUT[463:348] :
|
|
((int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_46$D_OUT[231:116] :
|
|
int_sqrt_fNext_46$D_OUT[463:348]),
|
|
int_sqrt_fNext_46$D_OUT[464] ?
|
|
int_sqrt_fNext_46$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h44101,
|
|
(int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_46$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h44177, b__h44174 } } } ;
|
|
assign int_sqrt_fNext_47$ENQ = CAN_FIRE_RL_int_sqrt_work_47 ;
|
|
assign int_sqrt_fNext_47$DEQ = CAN_FIRE_RL_int_sqrt_work_48 ;
|
|
assign int_sqrt_fNext_47$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_48
|
|
assign int_sqrt_fNext_48$D_IN =
|
|
{ int_sqrt_fNext_47$D_OUT[464] ||
|
|
int_sqrt_fNext_47$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_47$D_OUT[464] ?
|
|
int_sqrt_fNext_47$D_OUT[463:348] :
|
|
((int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_47$D_OUT[231:116] :
|
|
int_sqrt_fNext_47$D_OUT[463:348]),
|
|
int_sqrt_fNext_47$D_OUT[464] ?
|
|
int_sqrt_fNext_47$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h44501,
|
|
(int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_47$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h44577, b__h44574 } } } ;
|
|
assign int_sqrt_fNext_48$ENQ = CAN_FIRE_RL_int_sqrt_work_48 ;
|
|
assign int_sqrt_fNext_48$DEQ = CAN_FIRE_RL_int_sqrt_work_49 ;
|
|
assign int_sqrt_fNext_48$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_49
|
|
assign int_sqrt_fNext_49$D_IN =
|
|
{ int_sqrt_fNext_48$D_OUT[464] ||
|
|
int_sqrt_fNext_48$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_48$D_OUT[464] ?
|
|
int_sqrt_fNext_48$D_OUT[463:348] :
|
|
((int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_48$D_OUT[231:116] :
|
|
int_sqrt_fNext_48$D_OUT[463:348]),
|
|
int_sqrt_fNext_48$D_OUT[464] ?
|
|
int_sqrt_fNext_48$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h44901,
|
|
(int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_48$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h44977, b__h44974 } } } ;
|
|
assign int_sqrt_fNext_49$ENQ = CAN_FIRE_RL_int_sqrt_work_49 ;
|
|
assign int_sqrt_fNext_49$DEQ = CAN_FIRE_RL_int_sqrt_work_50 ;
|
|
assign int_sqrt_fNext_49$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_5
|
|
assign int_sqrt_fNext_5$D_IN =
|
|
{ int_sqrt_fNext_4$D_OUT[464] ||
|
|
int_sqrt_fNext_4$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_4$D_OUT[464] ?
|
|
int_sqrt_fNext_4$D_OUT[463:348] :
|
|
((int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_4$D_OUT[231:116] :
|
|
int_sqrt_fNext_4$D_OUT[463:348]),
|
|
int_sqrt_fNext_4$D_OUT[464] ?
|
|
int_sqrt_fNext_4$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h27301,
|
|
(int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_4$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h27377, b__h27374 } } } ;
|
|
assign int_sqrt_fNext_5$ENQ = CAN_FIRE_RL_int_sqrt_work_5 ;
|
|
assign int_sqrt_fNext_5$DEQ = CAN_FIRE_RL_int_sqrt_work_6 ;
|
|
assign int_sqrt_fNext_5$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_50
|
|
assign int_sqrt_fNext_50$D_IN =
|
|
{ int_sqrt_fNext_49$D_OUT[464] ||
|
|
int_sqrt_fNext_49$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_49$D_OUT[464] ?
|
|
int_sqrt_fNext_49$D_OUT[463:348] :
|
|
((int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_49$D_OUT[231:116] :
|
|
int_sqrt_fNext_49$D_OUT[463:348]),
|
|
int_sqrt_fNext_49$D_OUT[464] ?
|
|
int_sqrt_fNext_49$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h45301,
|
|
(int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_49$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h45377, b__h45374 } } } ;
|
|
assign int_sqrt_fNext_50$ENQ = CAN_FIRE_RL_int_sqrt_work_50 ;
|
|
assign int_sqrt_fNext_50$DEQ = CAN_FIRE_RL_int_sqrt_work_51 ;
|
|
assign int_sqrt_fNext_50$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_51
|
|
assign int_sqrt_fNext_51$D_IN =
|
|
{ int_sqrt_fNext_50$D_OUT[464] ||
|
|
int_sqrt_fNext_50$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_50$D_OUT[464] ?
|
|
int_sqrt_fNext_50$D_OUT[463:348] :
|
|
((int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_50$D_OUT[231:116] :
|
|
int_sqrt_fNext_50$D_OUT[463:348]),
|
|
int_sqrt_fNext_50$D_OUT[464] ?
|
|
int_sqrt_fNext_50$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h45701,
|
|
(int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_50$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h45777, b__h45774 } } } ;
|
|
assign int_sqrt_fNext_51$ENQ = CAN_FIRE_RL_int_sqrt_work_51 ;
|
|
assign int_sqrt_fNext_51$DEQ = CAN_FIRE_RL_int_sqrt_work_52 ;
|
|
assign int_sqrt_fNext_51$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_52
|
|
assign int_sqrt_fNext_52$D_IN =
|
|
{ int_sqrt_fNext_51$D_OUT[464] ||
|
|
int_sqrt_fNext_51$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_51$D_OUT[464] ?
|
|
int_sqrt_fNext_51$D_OUT[463:348] :
|
|
((int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_51$D_OUT[231:116] :
|
|
int_sqrt_fNext_51$D_OUT[463:348]),
|
|
int_sqrt_fNext_51$D_OUT[464] ?
|
|
int_sqrt_fNext_51$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h46101,
|
|
(int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_51$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h46177, b__h46174 } } } ;
|
|
assign int_sqrt_fNext_52$ENQ = CAN_FIRE_RL_int_sqrt_work_52 ;
|
|
assign int_sqrt_fNext_52$DEQ = CAN_FIRE_RL_int_sqrt_work_53 ;
|
|
assign int_sqrt_fNext_52$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_53
|
|
assign int_sqrt_fNext_53$D_IN =
|
|
{ int_sqrt_fNext_52$D_OUT[464] ||
|
|
int_sqrt_fNext_52$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_52$D_OUT[464] ?
|
|
int_sqrt_fNext_52$D_OUT[463:348] :
|
|
((int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_52$D_OUT[231:116] :
|
|
int_sqrt_fNext_52$D_OUT[463:348]),
|
|
int_sqrt_fNext_52$D_OUT[464] ?
|
|
int_sqrt_fNext_52$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h46501,
|
|
(int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_52$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h46577, b__h46574 } } } ;
|
|
assign int_sqrt_fNext_53$ENQ = CAN_FIRE_RL_int_sqrt_work_53 ;
|
|
assign int_sqrt_fNext_53$DEQ = CAN_FIRE_RL_int_sqrt_work_54 ;
|
|
assign int_sqrt_fNext_53$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_54
|
|
assign int_sqrt_fNext_54$D_IN =
|
|
{ int_sqrt_fNext_53$D_OUT[464] ||
|
|
int_sqrt_fNext_53$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_53$D_OUT[464] ?
|
|
int_sqrt_fNext_53$D_OUT[463:348] :
|
|
((int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_53$D_OUT[231:116] :
|
|
int_sqrt_fNext_53$D_OUT[463:348]),
|
|
int_sqrt_fNext_53$D_OUT[464] ?
|
|
int_sqrt_fNext_53$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h46901,
|
|
(int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_53$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h46977, b__h46974 } } } ;
|
|
assign int_sqrt_fNext_54$ENQ = CAN_FIRE_RL_int_sqrt_work_54 ;
|
|
assign int_sqrt_fNext_54$DEQ = CAN_FIRE_RL_int_sqrt_work_55 ;
|
|
assign int_sqrt_fNext_54$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_55
|
|
assign int_sqrt_fNext_55$D_IN =
|
|
{ int_sqrt_fNext_54$D_OUT[464] ||
|
|
int_sqrt_fNext_54$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_54$D_OUT[464] ?
|
|
int_sqrt_fNext_54$D_OUT[463:348] :
|
|
((int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_54$D_OUT[231:116] :
|
|
int_sqrt_fNext_54$D_OUT[463:348]),
|
|
int_sqrt_fNext_54$D_OUT[464] ?
|
|
int_sqrt_fNext_54$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h47301,
|
|
(int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_54$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h47377, b__h47374 } } } ;
|
|
assign int_sqrt_fNext_55$ENQ = CAN_FIRE_RL_int_sqrt_work_55 ;
|
|
assign int_sqrt_fNext_55$DEQ = CAN_FIRE_RL_int_sqrt_work_56 ;
|
|
assign int_sqrt_fNext_55$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_56
|
|
assign int_sqrt_fNext_56$D_IN =
|
|
{ int_sqrt_fNext_55$D_OUT[464] ||
|
|
int_sqrt_fNext_55$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_55$D_OUT[464] ?
|
|
int_sqrt_fNext_55$D_OUT[463:348] :
|
|
((int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_55$D_OUT[231:116] :
|
|
int_sqrt_fNext_55$D_OUT[463:348]),
|
|
int_sqrt_fNext_55$D_OUT[464] ?
|
|
int_sqrt_fNext_55$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h47701,
|
|
(int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_55$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h47777, b__h47774 } } } ;
|
|
assign int_sqrt_fNext_56$ENQ = CAN_FIRE_RL_int_sqrt_work_56 ;
|
|
assign int_sqrt_fNext_56$DEQ = CAN_FIRE_RL_int_sqrt_work_57 ;
|
|
assign int_sqrt_fNext_56$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_57
|
|
assign int_sqrt_fNext_57$D_IN =
|
|
{ int_sqrt_fNext_56$D_OUT[464] ||
|
|
int_sqrt_fNext_56$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_56$D_OUT[464] ?
|
|
int_sqrt_fNext_56$D_OUT[463:348] :
|
|
((int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_56$D_OUT[231:116] :
|
|
int_sqrt_fNext_56$D_OUT[463:348]),
|
|
int_sqrt_fNext_56$D_OUT[464] ?
|
|
int_sqrt_fNext_56$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h48101,
|
|
(int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_56$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h48177, b__h48174 } } } ;
|
|
assign int_sqrt_fNext_57$ENQ = CAN_FIRE_RL_int_sqrt_work_57 ;
|
|
assign int_sqrt_fNext_57$DEQ = CAN_FIRE_RL_int_sqrt_work_58 ;
|
|
assign int_sqrt_fNext_57$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_58
|
|
assign int_sqrt_fNext_58$D_IN =
|
|
{ int_sqrt_fNext_57$D_OUT[464] ||
|
|
int_sqrt_fNext_57$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_57$D_OUT[464] ?
|
|
int_sqrt_fNext_57$D_OUT[463:348] :
|
|
((int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_57$D_OUT[231:116] :
|
|
int_sqrt_fNext_57$D_OUT[463:348]),
|
|
int_sqrt_fNext_57$D_OUT[464] ?
|
|
int_sqrt_fNext_57$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h48501,
|
|
(int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_57$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h48577, b__h48574 } } } ;
|
|
assign int_sqrt_fNext_58$ENQ = CAN_FIRE_RL_int_sqrt_work_58 ;
|
|
assign int_sqrt_fNext_58$DEQ = CAN_FIRE_RL_int_sqrt_finish ;
|
|
assign int_sqrt_fNext_58$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_6
|
|
assign int_sqrt_fNext_6$D_IN =
|
|
{ int_sqrt_fNext_5$D_OUT[464] ||
|
|
int_sqrt_fNext_5$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_5$D_OUT[464] ?
|
|
int_sqrt_fNext_5$D_OUT[463:348] :
|
|
((int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_5$D_OUT[231:116] :
|
|
int_sqrt_fNext_5$D_OUT[463:348]),
|
|
int_sqrt_fNext_5$D_OUT[464] ?
|
|
int_sqrt_fNext_5$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h27701,
|
|
(int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_5$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h27777, b__h27774 } } } ;
|
|
assign int_sqrt_fNext_6$ENQ = CAN_FIRE_RL_int_sqrt_work_6 ;
|
|
assign int_sqrt_fNext_6$DEQ = CAN_FIRE_RL_int_sqrt_work_7 ;
|
|
assign int_sqrt_fNext_6$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_7
|
|
assign int_sqrt_fNext_7$D_IN =
|
|
{ int_sqrt_fNext_6$D_OUT[464] ||
|
|
int_sqrt_fNext_6$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_6$D_OUT[464] ?
|
|
int_sqrt_fNext_6$D_OUT[463:348] :
|
|
((int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_6$D_OUT[231:116] :
|
|
int_sqrt_fNext_6$D_OUT[463:348]),
|
|
int_sqrt_fNext_6$D_OUT[464] ?
|
|
int_sqrt_fNext_6$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h28101,
|
|
(int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_6$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h28177, b__h28174 } } } ;
|
|
assign int_sqrt_fNext_7$ENQ = CAN_FIRE_RL_int_sqrt_work_7 ;
|
|
assign int_sqrt_fNext_7$DEQ = CAN_FIRE_RL_int_sqrt_work_8 ;
|
|
assign int_sqrt_fNext_7$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_8
|
|
assign int_sqrt_fNext_8$D_IN =
|
|
{ int_sqrt_fNext_7$D_OUT[464] ||
|
|
int_sqrt_fNext_7$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_7$D_OUT[464] ?
|
|
int_sqrt_fNext_7$D_OUT[463:348] :
|
|
((int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_7$D_OUT[231:116] :
|
|
int_sqrt_fNext_7$D_OUT[463:348]),
|
|
int_sqrt_fNext_7$D_OUT[464] ?
|
|
int_sqrt_fNext_7$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h28501,
|
|
(int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_7$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h28577, b__h28574 } } } ;
|
|
assign int_sqrt_fNext_8$ENQ = CAN_FIRE_RL_int_sqrt_work_8 ;
|
|
assign int_sqrt_fNext_8$DEQ = CAN_FIRE_RL_int_sqrt_work_9 ;
|
|
assign int_sqrt_fNext_8$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fNext_9
|
|
assign int_sqrt_fNext_9$D_IN =
|
|
{ int_sqrt_fNext_8$D_OUT[464] ||
|
|
int_sqrt_fNext_8$D_OUT[115:0] == 116'd0,
|
|
int_sqrt_fNext_8$D_OUT[464] ?
|
|
int_sqrt_fNext_8$D_OUT[463:348] :
|
|
((int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_8$D_OUT[231:116] :
|
|
int_sqrt_fNext_8$D_OUT[463:348]),
|
|
int_sqrt_fNext_8$D_OUT[464] ?
|
|
int_sqrt_fNext_8$D_OUT[347:0] :
|
|
{ _theResult___snd_fst__h28901,
|
|
(int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ?
|
|
int_sqrt_fNext_8$D_OUT[231:0] :
|
|
{ _theResult___snd_snd__h28977, b__h28974 } } } ;
|
|
assign int_sqrt_fNext_9$ENQ = CAN_FIRE_RL_int_sqrt_work_9 ;
|
|
assign int_sqrt_fNext_9$DEQ = CAN_FIRE_RL_int_sqrt_work_10 ;
|
|
assign int_sqrt_fNext_9$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fRequest
|
|
assign int_sqrt_fRequest$D_IN = { fpu_fState_S1$D_OUT[57:0], 58'd0 } ;
|
|
assign int_sqrt_fRequest$ENQ =
|
|
WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[194] ;
|
|
assign int_sqrt_fRequest$DEQ = CAN_FIRE_RL_int_sqrt_start ;
|
|
assign int_sqrt_fRequest$CLR = 1'b0 ;
|
|
|
|
// submodule int_sqrt_fResponse
|
|
assign int_sqrt_fResponse$D_IN =
|
|
{ b__h48712, int_sqrt_fNext_58$D_OUT[347:232] != 116'd0 } ;
|
|
assign int_sqrt_fResponse$ENQ = CAN_FIRE_RL_int_sqrt_finish ;
|
|
assign int_sqrt_fResponse$DEQ =
|
|
WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[136] ;
|
|
assign int_sqrt_fResponse$CLR = 1'b0 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6 =
|
|
_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 ?
|
|
_theResult___snd__h75342 :
|
|
_theResult___snd__h75337 ;
|
|
assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 =
|
|
sfd__h75932[53] ?
|
|
((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ?
|
|
63'h7FF0000000000000 :
|
|
{ din_inc___2_exp__h76519, sfd__h75932[52:1] }) :
|
|
{ IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863,
|
|
sfd__h75932[51:0] } ;
|
|
assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 =
|
|
(fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ?
|
|
(fpu_fOperand_S0$D_OUT[54] ?
|
|
6'd2 :
|
|
(fpu_fOperand_S0$D_OUT[53] ?
|
|
6'd3 :
|
|
(fpu_fOperand_S0$D_OUT[52] ?
|
|
6'd4 :
|
|
(fpu_fOperand_S0$D_OUT[51] ?
|
|
6'd5 :
|
|
(fpu_fOperand_S0$D_OUT[50] ?
|
|
6'd6 :
|
|
(fpu_fOperand_S0$D_OUT[49] ?
|
|
6'd7 :
|
|
(fpu_fOperand_S0$D_OUT[48] ?
|
|
6'd8 :
|
|
(fpu_fOperand_S0$D_OUT[47] ?
|
|
6'd9 :
|
|
(fpu_fOperand_S0$D_OUT[46] ?
|
|
6'd10 :
|
|
(fpu_fOperand_S0$D_OUT[45] ?
|
|
6'd11 :
|
|
(fpu_fOperand_S0$D_OUT[44] ?
|
|
6'd12 :
|
|
(fpu_fOperand_S0$D_OUT[43] ?
|
|
6'd13 :
|
|
(fpu_fOperand_S0$D_OUT[42] ?
|
|
6'd14 :
|
|
(fpu_fOperand_S0$D_OUT[41] ?
|
|
6'd15 :
|
|
(fpu_fOperand_S0$D_OUT[40] ?
|
|
6'd16 :
|
|
(fpu_fOperand_S0$D_OUT[39] ?
|
|
6'd17 :
|
|
(fpu_fOperand_S0$D_OUT[38] ?
|
|
6'd18 :
|
|
(fpu_fOperand_S0$D_OUT[37] ?
|
|
6'd19 :
|
|
(fpu_fOperand_S0$D_OUT[36] ?
|
|
6'd20 :
|
|
(fpu_fOperand_S0$D_OUT[35] ?
|
|
6'd21 :
|
|
(fpu_fOperand_S0$D_OUT[34] ?
|
|
6'd22 :
|
|
(fpu_fOperand_S0$D_OUT[33] ?
|
|
6'd23 :
|
|
(fpu_fOperand_S0$D_OUT[32] ?
|
|
6'd24 :
|
|
(fpu_fOperand_S0$D_OUT[31] ?
|
|
6'd25 :
|
|
(fpu_fOperand_S0$D_OUT[30] ?
|
|
6'd26 :
|
|
(fpu_fOperand_S0$D_OUT[29] ?
|
|
6'd27 :
|
|
(fpu_fOperand_S0$D_OUT[28] ?
|
|
6'd28 :
|
|
(fpu_fOperand_S0$D_OUT[27] ?
|
|
6'd29 :
|
|
(fpu_fOperand_S0$D_OUT[26] ?
|
|
6'd30 :
|
|
(fpu_fOperand_S0$D_OUT[25] ?
|
|
6'd31 :
|
|
(fpu_fOperand_S0$D_OUT[24] ?
|
|
6'd32 :
|
|
(fpu_fOperand_S0$D_OUT[23] ?
|
|
6'd33 :
|
|
(fpu_fOperand_S0$D_OUT[22] ?
|
|
6'd34 :
|
|
(fpu_fOperand_S0$D_OUT[21] ?
|
|
6'd35 :
|
|
(fpu_fOperand_S0$D_OUT[20] ?
|
|
6'd36 :
|
|
(fpu_fOperand_S0$D_OUT[19] ?
|
|
6'd37 :
|
|
(fpu_fOperand_S0$D_OUT[18] ?
|
|
6'd38 :
|
|
(fpu_fOperand_S0$D_OUT[17] ?
|
|
6'd39 :
|
|
(fpu_fOperand_S0$D_OUT[16] ?
|
|
6'd40 :
|
|
(fpu_fOperand_S0$D_OUT[15] ?
|
|
6'd41 :
|
|
(fpu_fOperand_S0$D_OUT[14] ?
|
|
6'd42 :
|
|
(fpu_fOperand_S0$D_OUT[13] ?
|
|
6'd43 :
|
|
(fpu_fOperand_S0$D_OUT[12] ?
|
|
6'd44 :
|
|
(fpu_fOperand_S0$D_OUT[11] ?
|
|
6'd45 :
|
|
(fpu_fOperand_S0$D_OUT[10] ?
|
|
6'd46 :
|
|
(fpu_fOperand_S0$D_OUT[9] ?
|
|
6'd47 :
|
|
(fpu_fOperand_S0$D_OUT[8] ?
|
|
6'd48 :
|
|
(fpu_fOperand_S0$D_OUT[7] ?
|
|
6'd49 :
|
|
(fpu_fOperand_S0$D_OUT[6] ?
|
|
6'd50 :
|
|
(fpu_fOperand_S0$D_OUT[5] ?
|
|
6'd51 :
|
|
(fpu_fOperand_S0$D_OUT[4] ?
|
|
6'd52 :
|
|
(fpu_fOperand_S0$D_OUT[3] ?
|
|
6'd53 :
|
|
6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) :
|
|
6'd1 ;
|
|
assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460 =
|
|
((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ?
|
|
13'd7170 :
|
|
{ {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8[10]}},
|
|
fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 }) -
|
|
{ 7'd0,
|
|
IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 } ;
|
|
assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 =
|
|
(fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperand_S0$D_OUT[54] ||
|
|
fpu_fOperand_S0$D_OUT[65:55] == 11'd0 &&
|
|
fpu_fOperand_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperand_S0$D_OUT[54:3] == 52'd0 &&
|
|
!fpu_fOperand_S0$D_OUT[66]) ?
|
|
{ 1'd1,
|
|
fpu_fOperand_S0$D_OUT[66:3],
|
|
5'd0,
|
|
125'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } :
|
|
(fpu_fOperand_S0$D_OUT[66] ?
|
|
{ 70'h2FFF00000000000010,
|
|
125'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } :
|
|
{ 1'd0,
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
5'd0,
|
|
fpu_fOperand_S0$D_OUT[2:0],
|
|
fpu_fOperand_S0$D_OUT[66],
|
|
x__h57541[10:0],
|
|
fpu_fOperand_S0$D_OUT[54:3],
|
|
x__h65683 }) ;
|
|
assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 =
|
|
IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[12:1] ;
|
|
assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 =
|
|
(fpu_fState_S3$D_OUT[121:111] == 11'd0) ?
|
|
12'd3074 :
|
|
{ fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5[10],
|
|
fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 } ;
|
|
assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 =
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 -
|
|
12'd3074 ;
|
|
assign IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813 =
|
|
fpu_fState_S3$D_OUT[195] ?
|
|
fpu_fState_S3$D_OUT[128:126] :
|
|
{ fpu_fState_S3$D_OUT[58] &&
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 ==
|
|
12'd1023,
|
|
_theResult___fst_exp__h75269 == 11'd0 &&
|
|
guard__h66951 != 2'd0,
|
|
fpu_fState_S3$D_OUT[58] &&
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 ==
|
|
12'd1023 } ;
|
|
assign IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820 =
|
|
(fpu_fState_S3$D_OUT[58] &&
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 ==
|
|
12'd1023) ?
|
|
63'h7FEFFFFFFFFFFFFF :
|
|
{ _theResult___fst_exp__h75266, sfdin__h75260[58:7] } ;
|
|
assign IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 =
|
|
(fpu_fState_S3$D_OUT[58] ?
|
|
6'd0 :
|
|
(fpu_fState_S3$D_OUT[57] ?
|
|
6'd1 :
|
|
(fpu_fState_S3$D_OUT[56] ?
|
|
6'd2 :
|
|
(fpu_fState_S3$D_OUT[55] ?
|
|
6'd3 :
|
|
(fpu_fState_S3$D_OUT[54] ?
|
|
6'd4 :
|
|
(fpu_fState_S3$D_OUT[53] ?
|
|
6'd5 :
|
|
(fpu_fState_S3$D_OUT[52] ?
|
|
6'd6 :
|
|
(fpu_fState_S3$D_OUT[51] ?
|
|
6'd7 :
|
|
(fpu_fState_S3$D_OUT[50] ?
|
|
6'd8 :
|
|
(fpu_fState_S3$D_OUT[49] ?
|
|
6'd9 :
|
|
(fpu_fState_S3$D_OUT[48] ?
|
|
6'd10 :
|
|
(fpu_fState_S3$D_OUT[47] ?
|
|
6'd11 :
|
|
(fpu_fState_S3$D_OUT[46] ?
|
|
6'd12 :
|
|
(fpu_fState_S3$D_OUT[45] ?
|
|
6'd13 :
|
|
(fpu_fState_S3$D_OUT[44] ?
|
|
6'd14 :
|
|
(fpu_fState_S3$D_OUT[43] ?
|
|
6'd15 :
|
|
(fpu_fState_S3$D_OUT[42] ?
|
|
6'd16 :
|
|
(fpu_fState_S3$D_OUT[41] ?
|
|
6'd17 :
|
|
(fpu_fState_S3$D_OUT[40] ?
|
|
6'd18 :
|
|
(fpu_fState_S3$D_OUT[39] ?
|
|
6'd19 :
|
|
(fpu_fState_S3$D_OUT[38] ?
|
|
6'd20 :
|
|
(fpu_fState_S3$D_OUT[37] ?
|
|
6'd21 :
|
|
(fpu_fState_S3$D_OUT[36] ?
|
|
6'd22 :
|
|
(fpu_fState_S3$D_OUT[35] ?
|
|
6'd23 :
|
|
(fpu_fState_S3$D_OUT[34] ?
|
|
6'd24 :
|
|
(fpu_fState_S3$D_OUT[33] ?
|
|
6'd25 :
|
|
(fpu_fState_S3$D_OUT[32] ?
|
|
6'd26 :
|
|
(fpu_fState_S3$D_OUT[31] ?
|
|
6'd27 :
|
|
(fpu_fState_S3$D_OUT[30] ?
|
|
6'd28 :
|
|
(fpu_fState_S3$D_OUT[29] ?
|
|
6'd29 :
|
|
(fpu_fState_S3$D_OUT[28] ?
|
|
6'd30 :
|
|
(fpu_fState_S3$D_OUT[27] ?
|
|
6'd31 :
|
|
(fpu_fState_S3$D_OUT[26] ?
|
|
6'd32 :
|
|
(fpu_fState_S3$D_OUT[25] ?
|
|
6'd33 :
|
|
(fpu_fState_S3$D_OUT[24] ?
|
|
6'd34 :
|
|
(fpu_fState_S3$D_OUT[23] ?
|
|
6'd35 :
|
|
(fpu_fState_S3$D_OUT[22] ?
|
|
6'd36 :
|
|
(fpu_fState_S3$D_OUT[21] ?
|
|
6'd37 :
|
|
(fpu_fState_S3$D_OUT[20] ?
|
|
6'd38 :
|
|
(fpu_fState_S3$D_OUT[19] ?
|
|
6'd39 :
|
|
(fpu_fState_S3$D_OUT[18] ?
|
|
6'd40 :
|
|
(fpu_fState_S3$D_OUT[17] ?
|
|
6'd41 :
|
|
(fpu_fState_S3$D_OUT[16] ?
|
|
6'd42 :
|
|
(fpu_fState_S3$D_OUT[15] ?
|
|
6'd43 :
|
|
(fpu_fState_S3$D_OUT[14] ?
|
|
6'd44 :
|
|
(fpu_fState_S3$D_OUT[13] ?
|
|
6'd45 :
|
|
(fpu_fState_S3$D_OUT[12] ?
|
|
6'd46 :
|
|
(fpu_fState_S3$D_OUT[11] ?
|
|
6'd47 :
|
|
(fpu_fState_S3$D_OUT[10] ?
|
|
6'd48 :
|
|
(fpu_fState_S3$D_OUT[9] ?
|
|
6'd49 :
|
|
(fpu_fState_S3$D_OUT[8] ?
|
|
6'd50 :
|
|
(fpu_fState_S3$D_OUT[7] ?
|
|
6'd51 :
|
|
(fpu_fState_S3$D_OUT[6] ?
|
|
6'd52 :
|
|
(fpu_fState_S3$D_OUT[5] ?
|
|
6'd53 :
|
|
(fpu_fState_S3$D_OUT[4] ?
|
|
6'd54 :
|
|
(fpu_fState_S3$D_OUT[3] ?
|
|
6'd55 :
|
|
(fpu_fState_S3$D_OUT[2] ?
|
|
6'd56 :
|
|
(fpu_fState_S3$D_OUT[1] ?
|
|
6'd57 :
|
|
(fpu_fState_S3$D_OUT[0] ?
|
|
6'd58 :
|
|
6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 =
|
|
(fpu_fState_S4$D_OUT[64:54] == 11'd0 &&
|
|
sfd__h75932[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
fpu_fState_S4$D_OUT[64:54] ;
|
|
assign IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 =
|
|
(int_sqrt_fRequest$D_OUT[115] ?
|
|
7'd0 :
|
|
(int_sqrt_fRequest$D_OUT[114] ?
|
|
7'd1 :
|
|
(int_sqrt_fRequest$D_OUT[113] ?
|
|
7'd2 :
|
|
(int_sqrt_fRequest$D_OUT[112] ?
|
|
7'd3 :
|
|
(int_sqrt_fRequest$D_OUT[111] ?
|
|
7'd4 :
|
|
(int_sqrt_fRequest$D_OUT[110] ?
|
|
7'd5 :
|
|
(int_sqrt_fRequest$D_OUT[109] ?
|
|
7'd6 :
|
|
(int_sqrt_fRequest$D_OUT[108] ?
|
|
7'd7 :
|
|
(int_sqrt_fRequest$D_OUT[107] ?
|
|
7'd8 :
|
|
(int_sqrt_fRequest$D_OUT[106] ?
|
|
7'd9 :
|
|
(int_sqrt_fRequest$D_OUT[105] ?
|
|
7'd10 :
|
|
(int_sqrt_fRequest$D_OUT[104] ?
|
|
7'd11 :
|
|
(int_sqrt_fRequest$D_OUT[103] ?
|
|
7'd12 :
|
|
(int_sqrt_fRequest$D_OUT[102] ?
|
|
7'd13 :
|
|
(int_sqrt_fRequest$D_OUT[101] ?
|
|
7'd14 :
|
|
(int_sqrt_fRequest$D_OUT[100] ?
|
|
7'd15 :
|
|
(int_sqrt_fRequest$D_OUT[99] ?
|
|
7'd16 :
|
|
(int_sqrt_fRequest$D_OUT[98] ?
|
|
7'd17 :
|
|
(int_sqrt_fRequest$D_OUT[97] ?
|
|
7'd18 :
|
|
(int_sqrt_fRequest$D_OUT[96] ?
|
|
7'd19 :
|
|
(int_sqrt_fRequest$D_OUT[95] ?
|
|
7'd20 :
|
|
(int_sqrt_fRequest$D_OUT[94] ?
|
|
7'd21 :
|
|
(int_sqrt_fRequest$D_OUT[93] ?
|
|
7'd22 :
|
|
(int_sqrt_fRequest$D_OUT[92] ?
|
|
7'd23 :
|
|
(int_sqrt_fRequest$D_OUT[91] ?
|
|
7'd24 :
|
|
(int_sqrt_fRequest$D_OUT[90] ?
|
|
7'd25 :
|
|
(int_sqrt_fRequest$D_OUT[89] ?
|
|
7'd26 :
|
|
(int_sqrt_fRequest$D_OUT[88] ?
|
|
7'd27 :
|
|
(int_sqrt_fRequest$D_OUT[87] ?
|
|
7'd28 :
|
|
(int_sqrt_fRequest$D_OUT[86] ?
|
|
7'd29 :
|
|
(int_sqrt_fRequest$D_OUT[85] ?
|
|
7'd30 :
|
|
(int_sqrt_fRequest$D_OUT[84] ?
|
|
7'd31 :
|
|
(int_sqrt_fRequest$D_OUT[83] ?
|
|
7'd32 :
|
|
(int_sqrt_fRequest$D_OUT[82] ?
|
|
7'd33 :
|
|
(int_sqrt_fRequest$D_OUT[81] ?
|
|
7'd34 :
|
|
(int_sqrt_fRequest$D_OUT[80] ?
|
|
7'd35 :
|
|
(int_sqrt_fRequest$D_OUT[79] ?
|
|
7'd36 :
|
|
(int_sqrt_fRequest$D_OUT[78] ?
|
|
7'd37 :
|
|
(int_sqrt_fRequest$D_OUT[77] ?
|
|
7'd38 :
|
|
(int_sqrt_fRequest$D_OUT[76] ?
|
|
7'd39 :
|
|
(int_sqrt_fRequest$D_OUT[75] ?
|
|
7'd40 :
|
|
(int_sqrt_fRequest$D_OUT[74] ?
|
|
7'd41 :
|
|
(int_sqrt_fRequest$D_OUT[73] ?
|
|
7'd42 :
|
|
(int_sqrt_fRequest$D_OUT[72] ?
|
|
7'd43 :
|
|
(int_sqrt_fRequest$D_OUT[71] ?
|
|
7'd44 :
|
|
(int_sqrt_fRequest$D_OUT[70] ?
|
|
7'd45 :
|
|
(int_sqrt_fRequest$D_OUT[69] ?
|
|
7'd46 :
|
|
(int_sqrt_fRequest$D_OUT[68] ?
|
|
7'd47 :
|
|
(int_sqrt_fRequest$D_OUT[67] ?
|
|
7'd48 :
|
|
(int_sqrt_fRequest$D_OUT[66] ?
|
|
7'd49 :
|
|
(int_sqrt_fRequest$D_OUT[65] ?
|
|
7'd50 :
|
|
(int_sqrt_fRequest$D_OUT[64] ?
|
|
7'd51 :
|
|
(int_sqrt_fRequest$D_OUT[63] ?
|
|
7'd52 :
|
|
(int_sqrt_fRequest$D_OUT[62] ?
|
|
7'd53 :
|
|
(int_sqrt_fRequest$D_OUT[61] ?
|
|
7'd54 :
|
|
(int_sqrt_fRequest$D_OUT[60] ?
|
|
7'd55 :
|
|
(int_sqrt_fRequest$D_OUT[59] ?
|
|
7'd56 :
|
|
(int_sqrt_fRequest$D_OUT[58] ?
|
|
7'd57 :
|
|
(int_sqrt_fRequest$D_OUT[57] ?
|
|
7'd58 :
|
|
(int_sqrt_fRequest$D_OUT[56] ?
|
|
7'd59 :
|
|
(int_sqrt_fRequest$D_OUT[55] ?
|
|
7'd60 :
|
|
(int_sqrt_fRequest$D_OUT[54] ?
|
|
7'd61 :
|
|
(int_sqrt_fRequest$D_OUT[53] ?
|
|
7'd62 :
|
|
(int_sqrt_fRequest$D_OUT[52] ?
|
|
7'd63 :
|
|
(int_sqrt_fRequest$D_OUT[51] ?
|
|
7'd64 :
|
|
(int_sqrt_fRequest$D_OUT[50] ?
|
|
7'd65 :
|
|
(int_sqrt_fRequest$D_OUT[49] ?
|
|
7'd66 :
|
|
(int_sqrt_fRequest$D_OUT[48] ?
|
|
7'd67 :
|
|
(int_sqrt_fRequest$D_OUT[47] ?
|
|
7'd68 :
|
|
(int_sqrt_fRequest$D_OUT[46] ?
|
|
7'd69 :
|
|
(int_sqrt_fRequest$D_OUT[45] ?
|
|
7'd70 :
|
|
(int_sqrt_fRequest$D_OUT[44] ?
|
|
7'd71 :
|
|
(int_sqrt_fRequest$D_OUT[43] ?
|
|
7'd72 :
|
|
(int_sqrt_fRequest$D_OUT[42] ?
|
|
7'd73 :
|
|
(int_sqrt_fRequest$D_OUT[41] ?
|
|
7'd74 :
|
|
(int_sqrt_fRequest$D_OUT[40] ?
|
|
7'd75 :
|
|
(int_sqrt_fRequest$D_OUT[39] ?
|
|
7'd76 :
|
|
(int_sqrt_fRequest$D_OUT[38] ?
|
|
7'd77 :
|
|
(int_sqrt_fRequest$D_OUT[37] ?
|
|
7'd78 :
|
|
(int_sqrt_fRequest$D_OUT[36] ?
|
|
7'd79 :
|
|
(int_sqrt_fRequest$D_OUT[35] ?
|
|
7'd80 :
|
|
(int_sqrt_fRequest$D_OUT[34] ?
|
|
7'd81 :
|
|
(int_sqrt_fRequest$D_OUT[33] ?
|
|
7'd82 :
|
|
(int_sqrt_fRequest$D_OUT[32] ?
|
|
7'd83 :
|
|
(int_sqrt_fRequest$D_OUT[31] ?
|
|
7'd84 :
|
|
(int_sqrt_fRequest$D_OUT[30] ?
|
|
7'd85 :
|
|
(int_sqrt_fRequest$D_OUT[29] ?
|
|
7'd86 :
|
|
(int_sqrt_fRequest$D_OUT[28] ?
|
|
7'd87 :
|
|
(int_sqrt_fRequest$D_OUT[27] ?
|
|
7'd88 :
|
|
(int_sqrt_fRequest$D_OUT[26] ?
|
|
7'd89 :
|
|
(int_sqrt_fRequest$D_OUT[25] ?
|
|
7'd90 :
|
|
(int_sqrt_fRequest$D_OUT[24] ?
|
|
7'd91 :
|
|
(int_sqrt_fRequest$D_OUT[23] ?
|
|
7'd92 :
|
|
(int_sqrt_fRequest$D_OUT[22] ?
|
|
7'd93 :
|
|
(int_sqrt_fRequest$D_OUT[21] ?
|
|
7'd94 :
|
|
(int_sqrt_fRequest$D_OUT[20] ?
|
|
7'd95 :
|
|
(int_sqrt_fRequest$D_OUT[19] ?
|
|
7'd96 :
|
|
(int_sqrt_fRequest$D_OUT[18] ?
|
|
7'd97 :
|
|
(int_sqrt_fRequest$D_OUT[17] ?
|
|
7'd98 :
|
|
(int_sqrt_fRequest$D_OUT[16] ?
|
|
7'd99 :
|
|
(int_sqrt_fRequest$D_OUT[15] ?
|
|
7'd100 :
|
|
(int_sqrt_fRequest$D_OUT[14] ?
|
|
7'd101 :
|
|
(int_sqrt_fRequest$D_OUT[13] ?
|
|
7'd102 :
|
|
(int_sqrt_fRequest$D_OUT[12] ?
|
|
7'd103 :
|
|
(int_sqrt_fRequest$D_OUT[11] ?
|
|
7'd104 :
|
|
(int_sqrt_fRequest$D_OUT[10] ?
|
|
7'd105 :
|
|
(int_sqrt_fRequest$D_OUT[9] ?
|
|
7'd106 :
|
|
(int_sqrt_fRequest$D_OUT[8] ?
|
|
7'd107 :
|
|
(int_sqrt_fRequest$D_OUT[7] ?
|
|
7'd108 :
|
|
(int_sqrt_fRequest$D_OUT[6] ?
|
|
7'd109 :
|
|
(int_sqrt_fRequest$D_OUT[5] ?
|
|
7'd110 :
|
|
(int_sqrt_fRequest$D_OUT[4] ?
|
|
7'd111 :
|
|
(int_sqrt_fRequest$D_OUT[3] ?
|
|
7'd112 :
|
|
(int_sqrt_fRequest$D_OUT[2] ?
|
|
7'd113 :
|
|
(int_sqrt_fRequest$D_OUT[1] ?
|
|
7'd114 :
|
|
(int_sqrt_fRequest$D_OUT[0] ?
|
|
7'd115 :
|
|
7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
7'd1 ;
|
|
assign IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7 =
|
|
sfdin__h75260[6] ? 2'd2 : 2'd0 ;
|
|
assign _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 =
|
|
({ 6'd0,
|
|
IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ^
|
|
12'h800) <=
|
|
(IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ^
|
|
12'h800) ;
|
|
assign _theResult___exp__h76428 =
|
|
sfd__h75932[53] ?
|
|
((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h76519) :
|
|
IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 ;
|
|
assign _theResult___fst_exp__h75266 =
|
|
fpu_fState_S3$D_OUT[58] ?
|
|
_theResult___fst_exp__h75289 :
|
|
_theResult___fst_exp__h75353 ;
|
|
assign _theResult___fst_exp__h75269 =
|
|
(fpu_fState_S3$D_OUT[58] &&
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 ==
|
|
12'd1023) ?
|
|
11'd2046 :
|
|
_theResult___fst_exp__h75266 ;
|
|
assign _theResult___fst_exp__h75289 =
|
|
(fpu_fState_S3$D_OUT[121:111] == 11'd0) ?
|
|
11'd2 :
|
|
fpu_fState_S3$D_OUT[121:111] + 11'd1 ;
|
|
assign _theResult___fst_exp__h75305 =
|
|
(fpu_fState_S3$D_OUT[121:111] == 11'd0) ?
|
|
11'd1 :
|
|
fpu_fState_S3$D_OUT[121:111] ;
|
|
assign _theResult___fst_exp__h75344 =
|
|
fpu_fState_S3$D_OUT[121:111] -
|
|
{ 5'd0,
|
|
IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ;
|
|
assign _theResult___fst_exp__h75350 =
|
|
(!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] &&
|
|
!fpu_fState_S3$D_OUT[56] &&
|
|
!fpu_fState_S3$D_OUT[55] &&
|
|
!fpu_fState_S3$D_OUT[54] &&
|
|
!fpu_fState_S3$D_OUT[53] &&
|
|
!fpu_fState_S3$D_OUT[52] &&
|
|
!fpu_fState_S3$D_OUT[51] &&
|
|
!fpu_fState_S3$D_OUT[50] &&
|
|
!fpu_fState_S3$D_OUT[49] &&
|
|
!fpu_fState_S3$D_OUT[48] &&
|
|
!fpu_fState_S3$D_OUT[47] &&
|
|
!fpu_fState_S3$D_OUT[46] &&
|
|
!fpu_fState_S3$D_OUT[45] &&
|
|
!fpu_fState_S3$D_OUT[44] &&
|
|
!fpu_fState_S3$D_OUT[43] &&
|
|
!fpu_fState_S3$D_OUT[42] &&
|
|
!fpu_fState_S3$D_OUT[41] &&
|
|
!fpu_fState_S3$D_OUT[40] &&
|
|
!fpu_fState_S3$D_OUT[39] &&
|
|
!fpu_fState_S3$D_OUT[38] &&
|
|
!fpu_fState_S3$D_OUT[37] &&
|
|
!fpu_fState_S3$D_OUT[36] &&
|
|
!fpu_fState_S3$D_OUT[35] &&
|
|
!fpu_fState_S3$D_OUT[34] &&
|
|
!fpu_fState_S3$D_OUT[33] &&
|
|
!fpu_fState_S3$D_OUT[32] &&
|
|
!fpu_fState_S3$D_OUT[31] &&
|
|
!fpu_fState_S3$D_OUT[30] &&
|
|
!fpu_fState_S3$D_OUT[29] &&
|
|
!fpu_fState_S3$D_OUT[28] &&
|
|
!fpu_fState_S3$D_OUT[27] &&
|
|
!fpu_fState_S3$D_OUT[26] &&
|
|
!fpu_fState_S3$D_OUT[25] &&
|
|
!fpu_fState_S3$D_OUT[24] &&
|
|
!fpu_fState_S3$D_OUT[23] &&
|
|
!fpu_fState_S3$D_OUT[22] &&
|
|
!fpu_fState_S3$D_OUT[21] &&
|
|
!fpu_fState_S3$D_OUT[20] &&
|
|
!fpu_fState_S3$D_OUT[19] &&
|
|
!fpu_fState_S3$D_OUT[18] &&
|
|
!fpu_fState_S3$D_OUT[17] &&
|
|
!fpu_fState_S3$D_OUT[16] &&
|
|
!fpu_fState_S3$D_OUT[15] &&
|
|
!fpu_fState_S3$D_OUT[14] &&
|
|
!fpu_fState_S3$D_OUT[13] &&
|
|
!fpu_fState_S3$D_OUT[12] &&
|
|
!fpu_fState_S3$D_OUT[11] &&
|
|
!fpu_fState_S3$D_OUT[10] &&
|
|
!fpu_fState_S3$D_OUT[9] &&
|
|
!fpu_fState_S3$D_OUT[8] &&
|
|
!fpu_fState_S3$D_OUT[7] &&
|
|
!fpu_fState_S3$D_OUT[6] &&
|
|
!fpu_fState_S3$D_OUT[5] &&
|
|
!fpu_fState_S3$D_OUT[4] &&
|
|
!fpu_fState_S3$D_OUT[3] &&
|
|
!fpu_fState_S3$D_OUT[2] &&
|
|
!fpu_fState_S3$D_OUT[1] &&
|
|
!fpu_fState_S3$D_OUT[0] ||
|
|
!_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h75344 ;
|
|
assign _theResult___fst_exp__h75353 =
|
|
(!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ?
|
|
_theResult___fst_exp__h75305 :
|
|
_theResult___fst_exp__h75350 ;
|
|
assign _theResult___fst_exp__h76509 =
|
|
(fpu_fState_S4$D_OUT[64:54] == 11'd2047) ?
|
|
fpu_fState_S4$D_OUT[64:54] :
|
|
_theResult___fst_exp__h76506 ;
|
|
assign _theResult___fst_sfd__h76510 =
|
|
(fpu_fState_S4$D_OUT[64:54] == 11'd2047) ?
|
|
fpu_fState_S4$D_OUT[53:2] :
|
|
_theResult___fst_sfd__h76507 ;
|
|
assign _theResult___sfd__h76429 =
|
|
sfd__h75932[53] ?
|
|
((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h75932[52:1]) :
|
|
sfd__h75932[51:0] ;
|
|
assign _theResult___snd__h75283 = { fpu_fState_S3$D_OUT[57:0], 1'd0 } ;
|
|
assign _theResult___snd__h75298 =
|
|
(!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ?
|
|
_theResult___snd__h75300 :
|
|
_theResult___snd__h75313 ;
|
|
assign _theResult___snd__h75300 = { fpu_fState_S3$D_OUT[56:0], 2'd0 } ;
|
|
assign _theResult___snd__h75313 =
|
|
(!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] &&
|
|
!fpu_fState_S3$D_OUT[56] &&
|
|
!fpu_fState_S3$D_OUT[55] &&
|
|
!fpu_fState_S3$D_OUT[54] &&
|
|
!fpu_fState_S3$D_OUT[53] &&
|
|
!fpu_fState_S3$D_OUT[52] &&
|
|
!fpu_fState_S3$D_OUT[51] &&
|
|
!fpu_fState_S3$D_OUT[50] &&
|
|
!fpu_fState_S3$D_OUT[49] &&
|
|
!fpu_fState_S3$D_OUT[48] &&
|
|
!fpu_fState_S3$D_OUT[47] &&
|
|
!fpu_fState_S3$D_OUT[46] &&
|
|
!fpu_fState_S3$D_OUT[45] &&
|
|
!fpu_fState_S3$D_OUT[44] &&
|
|
!fpu_fState_S3$D_OUT[43] &&
|
|
!fpu_fState_S3$D_OUT[42] &&
|
|
!fpu_fState_S3$D_OUT[41] &&
|
|
!fpu_fState_S3$D_OUT[40] &&
|
|
!fpu_fState_S3$D_OUT[39] &&
|
|
!fpu_fState_S3$D_OUT[38] &&
|
|
!fpu_fState_S3$D_OUT[37] &&
|
|
!fpu_fState_S3$D_OUT[36] &&
|
|
!fpu_fState_S3$D_OUT[35] &&
|
|
!fpu_fState_S3$D_OUT[34] &&
|
|
!fpu_fState_S3$D_OUT[33] &&
|
|
!fpu_fState_S3$D_OUT[32] &&
|
|
!fpu_fState_S3$D_OUT[31] &&
|
|
!fpu_fState_S3$D_OUT[30] &&
|
|
!fpu_fState_S3$D_OUT[29] &&
|
|
!fpu_fState_S3$D_OUT[28] &&
|
|
!fpu_fState_S3$D_OUT[27] &&
|
|
!fpu_fState_S3$D_OUT[26] &&
|
|
!fpu_fState_S3$D_OUT[25] &&
|
|
!fpu_fState_S3$D_OUT[24] &&
|
|
!fpu_fState_S3$D_OUT[23] &&
|
|
!fpu_fState_S3$D_OUT[22] &&
|
|
!fpu_fState_S3$D_OUT[21] &&
|
|
!fpu_fState_S3$D_OUT[20] &&
|
|
!fpu_fState_S3$D_OUT[19] &&
|
|
!fpu_fState_S3$D_OUT[18] &&
|
|
!fpu_fState_S3$D_OUT[17] &&
|
|
!fpu_fState_S3$D_OUT[16] &&
|
|
!fpu_fState_S3$D_OUT[15] &&
|
|
!fpu_fState_S3$D_OUT[14] &&
|
|
!fpu_fState_S3$D_OUT[13] &&
|
|
!fpu_fState_S3$D_OUT[12] &&
|
|
!fpu_fState_S3$D_OUT[11] &&
|
|
!fpu_fState_S3$D_OUT[10] &&
|
|
!fpu_fState_S3$D_OUT[9] &&
|
|
!fpu_fState_S3$D_OUT[8] &&
|
|
!fpu_fState_S3$D_OUT[7] &&
|
|
!fpu_fState_S3$D_OUT[6] &&
|
|
!fpu_fState_S3$D_OUT[5] &&
|
|
!fpu_fState_S3$D_OUT[4] &&
|
|
!fpu_fState_S3$D_OUT[3] &&
|
|
!fpu_fState_S3$D_OUT[2] &&
|
|
!fpu_fState_S3$D_OUT[1] &&
|
|
!fpu_fState_S3$D_OUT[0]) ?
|
|
fpu_fState_S3$D_OUT[58:0] :
|
|
_theResult___snd__h75319 ;
|
|
assign _theResult___snd__h75319 =
|
|
{ IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6[56:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h75337 =
|
|
fpu_fState_S3$D_OUT[58:0] <<
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ;
|
|
assign _theResult___snd__h75342 =
|
|
fpu_fState_S3$D_OUT[58:0] <<
|
|
IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 ;
|
|
assign _theResult___snd_fst__h25299 =
|
|
(int_sqrt_fFirst$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264) ?
|
|
int_sqrt_fFirst$D_OUT[347:232] :
|
|
s__h25385 ;
|
|
assign _theResult___snd_fst__h25701 =
|
|
(int_sqrt_fNext_0$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299) ?
|
|
int_sqrt_fNext_0$D_OUT[347:232] :
|
|
s__h25785 ;
|
|
assign _theResult___snd_fst__h26101 =
|
|
(int_sqrt_fNext_1$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334) ?
|
|
int_sqrt_fNext_1$D_OUT[347:232] :
|
|
s__h26185 ;
|
|
assign _theResult___snd_fst__h26501 =
|
|
(int_sqrt_fNext_2$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369) ?
|
|
int_sqrt_fNext_2$D_OUT[347:232] :
|
|
s__h26585 ;
|
|
assign _theResult___snd_fst__h26901 =
|
|
(int_sqrt_fNext_3$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404) ?
|
|
int_sqrt_fNext_3$D_OUT[347:232] :
|
|
s__h26985 ;
|
|
assign _theResult___snd_fst__h27301 =
|
|
(int_sqrt_fNext_4$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439) ?
|
|
int_sqrt_fNext_4$D_OUT[347:232] :
|
|
s__h27385 ;
|
|
assign _theResult___snd_fst__h27701 =
|
|
(int_sqrt_fNext_5$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474) ?
|
|
int_sqrt_fNext_5$D_OUT[347:232] :
|
|
s__h27785 ;
|
|
assign _theResult___snd_fst__h28101 =
|
|
(int_sqrt_fNext_6$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509) ?
|
|
int_sqrt_fNext_6$D_OUT[347:232] :
|
|
s__h28185 ;
|
|
assign _theResult___snd_fst__h28501 =
|
|
(int_sqrt_fNext_7$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544) ?
|
|
int_sqrt_fNext_7$D_OUT[347:232] :
|
|
s__h28585 ;
|
|
assign _theResult___snd_fst__h28901 =
|
|
(int_sqrt_fNext_8$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579) ?
|
|
int_sqrt_fNext_8$D_OUT[347:232] :
|
|
s__h28985 ;
|
|
assign _theResult___snd_fst__h29301 =
|
|
(int_sqrt_fNext_9$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614) ?
|
|
int_sqrt_fNext_9$D_OUT[347:232] :
|
|
s__h29385 ;
|
|
assign _theResult___snd_fst__h29701 =
|
|
(int_sqrt_fNext_10$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649) ?
|
|
int_sqrt_fNext_10$D_OUT[347:232] :
|
|
s__h29785 ;
|
|
assign _theResult___snd_fst__h30101 =
|
|
(int_sqrt_fNext_11$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684) ?
|
|
int_sqrt_fNext_11$D_OUT[347:232] :
|
|
s__h30185 ;
|
|
assign _theResult___snd_fst__h30501 =
|
|
(int_sqrt_fNext_12$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719) ?
|
|
int_sqrt_fNext_12$D_OUT[347:232] :
|
|
s__h30585 ;
|
|
assign _theResult___snd_fst__h30901 =
|
|
(int_sqrt_fNext_13$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754) ?
|
|
int_sqrt_fNext_13$D_OUT[347:232] :
|
|
s__h30985 ;
|
|
assign _theResult___snd_fst__h31301 =
|
|
(int_sqrt_fNext_14$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789) ?
|
|
int_sqrt_fNext_14$D_OUT[347:232] :
|
|
s__h31385 ;
|
|
assign _theResult___snd_fst__h31701 =
|
|
(int_sqrt_fNext_15$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824) ?
|
|
int_sqrt_fNext_15$D_OUT[347:232] :
|
|
s__h31785 ;
|
|
assign _theResult___snd_fst__h32101 =
|
|
(int_sqrt_fNext_16$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859) ?
|
|
int_sqrt_fNext_16$D_OUT[347:232] :
|
|
s__h32185 ;
|
|
assign _theResult___snd_fst__h32501 =
|
|
(int_sqrt_fNext_17$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894) ?
|
|
int_sqrt_fNext_17$D_OUT[347:232] :
|
|
s__h32585 ;
|
|
assign _theResult___snd_fst__h32901 =
|
|
(int_sqrt_fNext_18$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929) ?
|
|
int_sqrt_fNext_18$D_OUT[347:232] :
|
|
s__h32985 ;
|
|
assign _theResult___snd_fst__h33301 =
|
|
(int_sqrt_fNext_19$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964) ?
|
|
int_sqrt_fNext_19$D_OUT[347:232] :
|
|
s__h33385 ;
|
|
assign _theResult___snd_fst__h33701 =
|
|
(int_sqrt_fNext_20$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999) ?
|
|
int_sqrt_fNext_20$D_OUT[347:232] :
|
|
s__h33785 ;
|
|
assign _theResult___snd_fst__h34101 =
|
|
(int_sqrt_fNext_21$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034) ?
|
|
int_sqrt_fNext_21$D_OUT[347:232] :
|
|
s__h34185 ;
|
|
assign _theResult___snd_fst__h34501 =
|
|
(int_sqrt_fNext_22$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069) ?
|
|
int_sqrt_fNext_22$D_OUT[347:232] :
|
|
s__h34585 ;
|
|
assign _theResult___snd_fst__h34901 =
|
|
(int_sqrt_fNext_23$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104) ?
|
|
int_sqrt_fNext_23$D_OUT[347:232] :
|
|
s__h34985 ;
|
|
assign _theResult___snd_fst__h35301 =
|
|
(int_sqrt_fNext_24$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139) ?
|
|
int_sqrt_fNext_24$D_OUT[347:232] :
|
|
s__h35385 ;
|
|
assign _theResult___snd_fst__h35701 =
|
|
(int_sqrt_fNext_25$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174) ?
|
|
int_sqrt_fNext_25$D_OUT[347:232] :
|
|
s__h35785 ;
|
|
assign _theResult___snd_fst__h36101 =
|
|
(int_sqrt_fNext_26$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209) ?
|
|
int_sqrt_fNext_26$D_OUT[347:232] :
|
|
s__h36185 ;
|
|
assign _theResult___snd_fst__h36501 =
|
|
(int_sqrt_fNext_27$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244) ?
|
|
int_sqrt_fNext_27$D_OUT[347:232] :
|
|
s__h36585 ;
|
|
assign _theResult___snd_fst__h36901 =
|
|
(int_sqrt_fNext_28$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279) ?
|
|
int_sqrt_fNext_28$D_OUT[347:232] :
|
|
s__h36985 ;
|
|
assign _theResult___snd_fst__h37301 =
|
|
(int_sqrt_fNext_29$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314) ?
|
|
int_sqrt_fNext_29$D_OUT[347:232] :
|
|
s__h37385 ;
|
|
assign _theResult___snd_fst__h37701 =
|
|
(int_sqrt_fNext_30$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349) ?
|
|
int_sqrt_fNext_30$D_OUT[347:232] :
|
|
s__h37785 ;
|
|
assign _theResult___snd_fst__h38101 =
|
|
(int_sqrt_fNext_31$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384) ?
|
|
int_sqrt_fNext_31$D_OUT[347:232] :
|
|
s__h38185 ;
|
|
assign _theResult___snd_fst__h38501 =
|
|
(int_sqrt_fNext_32$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419) ?
|
|
int_sqrt_fNext_32$D_OUT[347:232] :
|
|
s__h38585 ;
|
|
assign _theResult___snd_fst__h38901 =
|
|
(int_sqrt_fNext_33$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454) ?
|
|
int_sqrt_fNext_33$D_OUT[347:232] :
|
|
s__h38985 ;
|
|
assign _theResult___snd_fst__h39301 =
|
|
(int_sqrt_fNext_34$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489) ?
|
|
int_sqrt_fNext_34$D_OUT[347:232] :
|
|
s__h39385 ;
|
|
assign _theResult___snd_fst__h39701 =
|
|
(int_sqrt_fNext_35$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524) ?
|
|
int_sqrt_fNext_35$D_OUT[347:232] :
|
|
s__h39785 ;
|
|
assign _theResult___snd_fst__h40101 =
|
|
(int_sqrt_fNext_36$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559) ?
|
|
int_sqrt_fNext_36$D_OUT[347:232] :
|
|
s__h40185 ;
|
|
assign _theResult___snd_fst__h40501 =
|
|
(int_sqrt_fNext_37$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594) ?
|
|
int_sqrt_fNext_37$D_OUT[347:232] :
|
|
s__h40585 ;
|
|
assign _theResult___snd_fst__h40901 =
|
|
(int_sqrt_fNext_38$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629) ?
|
|
int_sqrt_fNext_38$D_OUT[347:232] :
|
|
s__h40985 ;
|
|
assign _theResult___snd_fst__h41301 =
|
|
(int_sqrt_fNext_39$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664) ?
|
|
int_sqrt_fNext_39$D_OUT[347:232] :
|
|
s__h41385 ;
|
|
assign _theResult___snd_fst__h41701 =
|
|
(int_sqrt_fNext_40$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699) ?
|
|
int_sqrt_fNext_40$D_OUT[347:232] :
|
|
s__h41785 ;
|
|
assign _theResult___snd_fst__h42101 =
|
|
(int_sqrt_fNext_41$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734) ?
|
|
int_sqrt_fNext_41$D_OUT[347:232] :
|
|
s__h42185 ;
|
|
assign _theResult___snd_fst__h42501 =
|
|
(int_sqrt_fNext_42$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769) ?
|
|
int_sqrt_fNext_42$D_OUT[347:232] :
|
|
s__h42585 ;
|
|
assign _theResult___snd_fst__h42901 =
|
|
(int_sqrt_fNext_43$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804) ?
|
|
int_sqrt_fNext_43$D_OUT[347:232] :
|
|
s__h42985 ;
|
|
assign _theResult___snd_fst__h43301 =
|
|
(int_sqrt_fNext_44$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839) ?
|
|
int_sqrt_fNext_44$D_OUT[347:232] :
|
|
s__h43385 ;
|
|
assign _theResult___snd_fst__h43701 =
|
|
(int_sqrt_fNext_45$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874) ?
|
|
int_sqrt_fNext_45$D_OUT[347:232] :
|
|
s__h43785 ;
|
|
assign _theResult___snd_fst__h44101 =
|
|
(int_sqrt_fNext_46$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909) ?
|
|
int_sqrt_fNext_46$D_OUT[347:232] :
|
|
s__h44185 ;
|
|
assign _theResult___snd_fst__h44501 =
|
|
(int_sqrt_fNext_47$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944) ?
|
|
int_sqrt_fNext_47$D_OUT[347:232] :
|
|
s__h44585 ;
|
|
assign _theResult___snd_fst__h44901 =
|
|
(int_sqrt_fNext_48$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979) ?
|
|
int_sqrt_fNext_48$D_OUT[347:232] :
|
|
s__h44985 ;
|
|
assign _theResult___snd_fst__h45301 =
|
|
(int_sqrt_fNext_49$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014) ?
|
|
int_sqrt_fNext_49$D_OUT[347:232] :
|
|
s__h45385 ;
|
|
assign _theResult___snd_fst__h45701 =
|
|
(int_sqrt_fNext_50$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049) ?
|
|
int_sqrt_fNext_50$D_OUT[347:232] :
|
|
s__h45785 ;
|
|
assign _theResult___snd_fst__h46101 =
|
|
(int_sqrt_fNext_51$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084) ?
|
|
int_sqrt_fNext_51$D_OUT[347:232] :
|
|
s__h46185 ;
|
|
assign _theResult___snd_fst__h46501 =
|
|
(int_sqrt_fNext_52$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119) ?
|
|
int_sqrt_fNext_52$D_OUT[347:232] :
|
|
s__h46585 ;
|
|
assign _theResult___snd_fst__h46901 =
|
|
(int_sqrt_fNext_53$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154) ?
|
|
int_sqrt_fNext_53$D_OUT[347:232] :
|
|
s__h46985 ;
|
|
assign _theResult___snd_fst__h47301 =
|
|
(int_sqrt_fNext_54$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189) ?
|
|
int_sqrt_fNext_54$D_OUT[347:232] :
|
|
s__h47385 ;
|
|
assign _theResult___snd_fst__h47701 =
|
|
(int_sqrt_fNext_55$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224) ?
|
|
int_sqrt_fNext_55$D_OUT[347:232] :
|
|
s__h47785 ;
|
|
assign _theResult___snd_fst__h48101 =
|
|
(int_sqrt_fNext_56$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259) ?
|
|
int_sqrt_fNext_56$D_OUT[347:232] :
|
|
s__h48185 ;
|
|
assign _theResult___snd_fst__h48501 =
|
|
(int_sqrt_fNext_57$D_OUT[115:0] == 116'd0 ||
|
|
int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294) ?
|
|
int_sqrt_fNext_57$D_OUT[347:232] :
|
|
s__h48585 ;
|
|
assign _theResult___snd_fst__h75372 =
|
|
{ IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7[1],
|
|
{ sfdin__h75260[5:0], 52'd0 } != 58'd0 } ;
|
|
assign _theResult___snd_snd__h25377 =
|
|
int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 ?
|
|
r__h25394 :
|
|
r__h25386 ;
|
|
assign _theResult___snd_snd__h25777 =
|
|
int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 ?
|
|
r__h25794 :
|
|
r__h25786 ;
|
|
assign _theResult___snd_snd__h26177 =
|
|
int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 ?
|
|
r__h26194 :
|
|
r__h26186 ;
|
|
assign _theResult___snd_snd__h26577 =
|
|
int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 ?
|
|
r__h26594 :
|
|
r__h26586 ;
|
|
assign _theResult___snd_snd__h26977 =
|
|
int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 ?
|
|
r__h26994 :
|
|
r__h26986 ;
|
|
assign _theResult___snd_snd__h27377 =
|
|
int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 ?
|
|
r__h27394 :
|
|
r__h27386 ;
|
|
assign _theResult___snd_snd__h27777 =
|
|
int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 ?
|
|
r__h27794 :
|
|
r__h27786 ;
|
|
assign _theResult___snd_snd__h28177 =
|
|
int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 ?
|
|
r__h28194 :
|
|
r__h28186 ;
|
|
assign _theResult___snd_snd__h28577 =
|
|
int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 ?
|
|
r__h28594 :
|
|
r__h28586 ;
|
|
assign _theResult___snd_snd__h28977 =
|
|
int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 ?
|
|
r__h28994 :
|
|
r__h28986 ;
|
|
assign _theResult___snd_snd__h29377 =
|
|
int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 ?
|
|
r__h29394 :
|
|
r__h29386 ;
|
|
assign _theResult___snd_snd__h29777 =
|
|
int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 ?
|
|
r__h29794 :
|
|
r__h29786 ;
|
|
assign _theResult___snd_snd__h30177 =
|
|
int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 ?
|
|
r__h30194 :
|
|
r__h30186 ;
|
|
assign _theResult___snd_snd__h30577 =
|
|
int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 ?
|
|
r__h30594 :
|
|
r__h30586 ;
|
|
assign _theResult___snd_snd__h30977 =
|
|
int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 ?
|
|
r__h30994 :
|
|
r__h30986 ;
|
|
assign _theResult___snd_snd__h31377 =
|
|
int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 ?
|
|
r__h31394 :
|
|
r__h31386 ;
|
|
assign _theResult___snd_snd__h31777 =
|
|
int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 ?
|
|
r__h31794 :
|
|
r__h31786 ;
|
|
assign _theResult___snd_snd__h32177 =
|
|
int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 ?
|
|
r__h32194 :
|
|
r__h32186 ;
|
|
assign _theResult___snd_snd__h32577 =
|
|
int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 ?
|
|
r__h32594 :
|
|
r__h32586 ;
|
|
assign _theResult___snd_snd__h32977 =
|
|
int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 ?
|
|
r__h32994 :
|
|
r__h32986 ;
|
|
assign _theResult___snd_snd__h33377 =
|
|
int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 ?
|
|
r__h33394 :
|
|
r__h33386 ;
|
|
assign _theResult___snd_snd__h33777 =
|
|
int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 ?
|
|
r__h33794 :
|
|
r__h33786 ;
|
|
assign _theResult___snd_snd__h34177 =
|
|
int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 ?
|
|
r__h34194 :
|
|
r__h34186 ;
|
|
assign _theResult___snd_snd__h34577 =
|
|
int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 ?
|
|
r__h34594 :
|
|
r__h34586 ;
|
|
assign _theResult___snd_snd__h34977 =
|
|
int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 ?
|
|
r__h34994 :
|
|
r__h34986 ;
|
|
assign _theResult___snd_snd__h35377 =
|
|
int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 ?
|
|
r__h35394 :
|
|
r__h35386 ;
|
|
assign _theResult___snd_snd__h35777 =
|
|
int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 ?
|
|
r__h35794 :
|
|
r__h35786 ;
|
|
assign _theResult___snd_snd__h36177 =
|
|
int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 ?
|
|
r__h36194 :
|
|
r__h36186 ;
|
|
assign _theResult___snd_snd__h36577 =
|
|
int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 ?
|
|
r__h36594 :
|
|
r__h36586 ;
|
|
assign _theResult___snd_snd__h36977 =
|
|
int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 ?
|
|
r__h36994 :
|
|
r__h36986 ;
|
|
assign _theResult___snd_snd__h37377 =
|
|
int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 ?
|
|
r__h37394 :
|
|
r__h37386 ;
|
|
assign _theResult___snd_snd__h37777 =
|
|
int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 ?
|
|
r__h37794 :
|
|
r__h37786 ;
|
|
assign _theResult___snd_snd__h38177 =
|
|
int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 ?
|
|
r__h38194 :
|
|
r__h38186 ;
|
|
assign _theResult___snd_snd__h38577 =
|
|
int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 ?
|
|
r__h38594 :
|
|
r__h38586 ;
|
|
assign _theResult___snd_snd__h38977 =
|
|
int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 ?
|
|
r__h38994 :
|
|
r__h38986 ;
|
|
assign _theResult___snd_snd__h39377 =
|
|
int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 ?
|
|
r__h39394 :
|
|
r__h39386 ;
|
|
assign _theResult___snd_snd__h39777 =
|
|
int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 ?
|
|
r__h39794 :
|
|
r__h39786 ;
|
|
assign _theResult___snd_snd__h40177 =
|
|
int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 ?
|
|
r__h40194 :
|
|
r__h40186 ;
|
|
assign _theResult___snd_snd__h40577 =
|
|
int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 ?
|
|
r__h40594 :
|
|
r__h40586 ;
|
|
assign _theResult___snd_snd__h40977 =
|
|
int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 ?
|
|
r__h40994 :
|
|
r__h40986 ;
|
|
assign _theResult___snd_snd__h41377 =
|
|
int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 ?
|
|
r__h41394 :
|
|
r__h41386 ;
|
|
assign _theResult___snd_snd__h41777 =
|
|
int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 ?
|
|
r__h41794 :
|
|
r__h41786 ;
|
|
assign _theResult___snd_snd__h42177 =
|
|
int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 ?
|
|
r__h42194 :
|
|
r__h42186 ;
|
|
assign _theResult___snd_snd__h42577 =
|
|
int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 ?
|
|
r__h42594 :
|
|
r__h42586 ;
|
|
assign _theResult___snd_snd__h42977 =
|
|
int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 ?
|
|
r__h42994 :
|
|
r__h42986 ;
|
|
assign _theResult___snd_snd__h43377 =
|
|
int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 ?
|
|
r__h43394 :
|
|
r__h43386 ;
|
|
assign _theResult___snd_snd__h43777 =
|
|
int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 ?
|
|
r__h43794 :
|
|
r__h43786 ;
|
|
assign _theResult___snd_snd__h44177 =
|
|
int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 ?
|
|
r__h44194 :
|
|
r__h44186 ;
|
|
assign _theResult___snd_snd__h44577 =
|
|
int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 ?
|
|
r__h44594 :
|
|
r__h44586 ;
|
|
assign _theResult___snd_snd__h44977 =
|
|
int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 ?
|
|
r__h44994 :
|
|
r__h44986 ;
|
|
assign _theResult___snd_snd__h45377 =
|
|
int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 ?
|
|
r__h45394 :
|
|
r__h45386 ;
|
|
assign _theResult___snd_snd__h45777 =
|
|
int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 ?
|
|
r__h45794 :
|
|
r__h45786 ;
|
|
assign _theResult___snd_snd__h46177 =
|
|
int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 ?
|
|
r__h46194 :
|
|
r__h46186 ;
|
|
assign _theResult___snd_snd__h46577 =
|
|
int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 ?
|
|
r__h46594 :
|
|
r__h46586 ;
|
|
assign _theResult___snd_snd__h46977 =
|
|
int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 ?
|
|
r__h46994 :
|
|
r__h46986 ;
|
|
assign _theResult___snd_snd__h47377 =
|
|
int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 ?
|
|
r__h47394 :
|
|
r__h47386 ;
|
|
assign _theResult___snd_snd__h47777 =
|
|
int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 ?
|
|
r__h47794 :
|
|
r__h47786 ;
|
|
assign _theResult___snd_snd__h48177 =
|
|
int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 ?
|
|
r__h48194 :
|
|
r__h48186 ;
|
|
assign _theResult___snd_snd__h48577 =
|
|
int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 ?
|
|
r__h48594 :
|
|
r__h48586 ;
|
|
assign b___1__h16687 = 116'h40000000000000000000000000000 >> x__h24992 ;
|
|
assign b__h25374 = { 2'd0, int_sqrt_fFirst$D_OUT[115:2] } ;
|
|
assign b__h25774 = { 2'd0, int_sqrt_fNext_0$D_OUT[115:2] } ;
|
|
assign b__h26174 = { 2'd0, int_sqrt_fNext_1$D_OUT[115:2] } ;
|
|
assign b__h26574 = { 2'd0, int_sqrt_fNext_2$D_OUT[115:2] } ;
|
|
assign b__h26974 = { 2'd0, int_sqrt_fNext_3$D_OUT[115:2] } ;
|
|
assign b__h27374 = { 2'd0, int_sqrt_fNext_4$D_OUT[115:2] } ;
|
|
assign b__h27774 = { 2'd0, int_sqrt_fNext_5$D_OUT[115:2] } ;
|
|
assign b__h28174 = { 2'd0, int_sqrt_fNext_6$D_OUT[115:2] } ;
|
|
assign b__h28574 = { 2'd0, int_sqrt_fNext_7$D_OUT[115:2] } ;
|
|
assign b__h28974 = { 2'd0, int_sqrt_fNext_8$D_OUT[115:2] } ;
|
|
assign b__h29374 = { 2'd0, int_sqrt_fNext_9$D_OUT[115:2] } ;
|
|
assign b__h29774 = { 2'd0, int_sqrt_fNext_10$D_OUT[115:2] } ;
|
|
assign b__h30174 = { 2'd0, int_sqrt_fNext_11$D_OUT[115:2] } ;
|
|
assign b__h30574 = { 2'd0, int_sqrt_fNext_12$D_OUT[115:2] } ;
|
|
assign b__h30974 = { 2'd0, int_sqrt_fNext_13$D_OUT[115:2] } ;
|
|
assign b__h31374 = { 2'd0, int_sqrt_fNext_14$D_OUT[115:2] } ;
|
|
assign b__h31774 = { 2'd0, int_sqrt_fNext_15$D_OUT[115:2] } ;
|
|
assign b__h32174 = { 2'd0, int_sqrt_fNext_16$D_OUT[115:2] } ;
|
|
assign b__h32574 = { 2'd0, int_sqrt_fNext_17$D_OUT[115:2] } ;
|
|
assign b__h32974 = { 2'd0, int_sqrt_fNext_18$D_OUT[115:2] } ;
|
|
assign b__h33374 = { 2'd0, int_sqrt_fNext_19$D_OUT[115:2] } ;
|
|
assign b__h33774 = { 2'd0, int_sqrt_fNext_20$D_OUT[115:2] } ;
|
|
assign b__h34174 = { 2'd0, int_sqrt_fNext_21$D_OUT[115:2] } ;
|
|
assign b__h34574 = { 2'd0, int_sqrt_fNext_22$D_OUT[115:2] } ;
|
|
assign b__h34974 = { 2'd0, int_sqrt_fNext_23$D_OUT[115:2] } ;
|
|
assign b__h35374 = { 2'd0, int_sqrt_fNext_24$D_OUT[115:2] } ;
|
|
assign b__h35774 = { 2'd0, int_sqrt_fNext_25$D_OUT[115:2] } ;
|
|
assign b__h36174 = { 2'd0, int_sqrt_fNext_26$D_OUT[115:2] } ;
|
|
assign b__h36574 = { 2'd0, int_sqrt_fNext_27$D_OUT[115:2] } ;
|
|
assign b__h36974 = { 2'd0, int_sqrt_fNext_28$D_OUT[115:2] } ;
|
|
assign b__h37374 = { 2'd0, int_sqrt_fNext_29$D_OUT[115:2] } ;
|
|
assign b__h37774 = { 2'd0, int_sqrt_fNext_30$D_OUT[115:2] } ;
|
|
assign b__h38174 = { 2'd0, int_sqrt_fNext_31$D_OUT[115:2] } ;
|
|
assign b__h38574 = { 2'd0, int_sqrt_fNext_32$D_OUT[115:2] } ;
|
|
assign b__h38974 = { 2'd0, int_sqrt_fNext_33$D_OUT[115:2] } ;
|
|
assign b__h39374 = { 2'd0, int_sqrt_fNext_34$D_OUT[115:2] } ;
|
|
assign b__h39774 = { 2'd0, int_sqrt_fNext_35$D_OUT[115:2] } ;
|
|
assign b__h40174 = { 2'd0, int_sqrt_fNext_36$D_OUT[115:2] } ;
|
|
assign b__h40574 = { 2'd0, int_sqrt_fNext_37$D_OUT[115:2] } ;
|
|
assign b__h40974 = { 2'd0, int_sqrt_fNext_38$D_OUT[115:2] } ;
|
|
assign b__h41374 = { 2'd0, int_sqrt_fNext_39$D_OUT[115:2] } ;
|
|
assign b__h41774 = { 2'd0, int_sqrt_fNext_40$D_OUT[115:2] } ;
|
|
assign b__h42174 = { 2'd0, int_sqrt_fNext_41$D_OUT[115:2] } ;
|
|
assign b__h42574 = { 2'd0, int_sqrt_fNext_42$D_OUT[115:2] } ;
|
|
assign b__h42974 = { 2'd0, int_sqrt_fNext_43$D_OUT[115:2] } ;
|
|
assign b__h43374 = { 2'd0, int_sqrt_fNext_44$D_OUT[115:2] } ;
|
|
assign b__h43774 = { 2'd0, int_sqrt_fNext_45$D_OUT[115:2] } ;
|
|
assign b__h44174 = { 2'd0, int_sqrt_fNext_46$D_OUT[115:2] } ;
|
|
assign b__h44574 = { 2'd0, int_sqrt_fNext_47$D_OUT[115:2] } ;
|
|
assign b__h44974 = { 2'd0, int_sqrt_fNext_48$D_OUT[115:2] } ;
|
|
assign b__h45374 = { 2'd0, int_sqrt_fNext_49$D_OUT[115:2] } ;
|
|
assign b__h45774 = { 2'd0, int_sqrt_fNext_50$D_OUT[115:2] } ;
|
|
assign b__h46174 = { 2'd0, int_sqrt_fNext_51$D_OUT[115:2] } ;
|
|
assign b__h46574 = { 2'd0, int_sqrt_fNext_52$D_OUT[115:2] } ;
|
|
assign b__h46974 = { 2'd0, int_sqrt_fNext_53$D_OUT[115:2] } ;
|
|
assign b__h47374 = { 2'd0, int_sqrt_fNext_54$D_OUT[115:2] } ;
|
|
assign b__h47774 = { 2'd0, int_sqrt_fNext_55$D_OUT[115:2] } ;
|
|
assign b__h48174 = { 2'd0, int_sqrt_fNext_56$D_OUT[115:2] } ;
|
|
assign b__h48574 = { 2'd0, int_sqrt_fNext_57$D_OUT[115:2] } ;
|
|
assign b__h48712 =
|
|
int_sqrt_fNext_58$D_OUT[464] ?
|
|
int_sqrt_fNext_58$D_OUT[463:348] :
|
|
116'd0 ;
|
|
assign din_inc___2_exp__h76519 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ;
|
|
assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 =
|
|
fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ;
|
|
assign fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 =
|
|
fpu_fState_S3$D_OUT[121:111] - 11'd1023 ;
|
|
assign guard__h66951 = x__h75654 ;
|
|
assign int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 =
|
|
int_sqrt_fFirst$D_OUT[347:232] < sum__h25372 ;
|
|
assign int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 =
|
|
int_sqrt_fNext_0$D_OUT[347:232] < sum__h25772 ;
|
|
assign int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 =
|
|
int_sqrt_fNext_10$D_OUT[347:232] < sum__h29772 ;
|
|
assign int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 =
|
|
int_sqrt_fNext_11$D_OUT[347:232] < sum__h30172 ;
|
|
assign int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 =
|
|
int_sqrt_fNext_12$D_OUT[347:232] < sum__h30572 ;
|
|
assign int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 =
|
|
int_sqrt_fNext_13$D_OUT[347:232] < sum__h30972 ;
|
|
assign int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 =
|
|
int_sqrt_fNext_14$D_OUT[347:232] < sum__h31372 ;
|
|
assign int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 =
|
|
int_sqrt_fNext_15$D_OUT[347:232] < sum__h31772 ;
|
|
assign int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 =
|
|
int_sqrt_fNext_16$D_OUT[347:232] < sum__h32172 ;
|
|
assign int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 =
|
|
int_sqrt_fNext_17$D_OUT[347:232] < sum__h32572 ;
|
|
assign int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 =
|
|
int_sqrt_fNext_18$D_OUT[347:232] < sum__h32972 ;
|
|
assign int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 =
|
|
int_sqrt_fNext_19$D_OUT[347:232] < sum__h33372 ;
|
|
assign int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 =
|
|
int_sqrt_fNext_1$D_OUT[347:232] < sum__h26172 ;
|
|
assign int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 =
|
|
int_sqrt_fNext_20$D_OUT[347:232] < sum__h33772 ;
|
|
assign int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 =
|
|
int_sqrt_fNext_21$D_OUT[347:232] < sum__h34172 ;
|
|
assign int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 =
|
|
int_sqrt_fNext_22$D_OUT[347:232] < sum__h34572 ;
|
|
assign int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 =
|
|
int_sqrt_fNext_23$D_OUT[347:232] < sum__h34972 ;
|
|
assign int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 =
|
|
int_sqrt_fNext_24$D_OUT[347:232] < sum__h35372 ;
|
|
assign int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 =
|
|
int_sqrt_fNext_25$D_OUT[347:232] < sum__h35772 ;
|
|
assign int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 =
|
|
int_sqrt_fNext_26$D_OUT[347:232] < sum__h36172 ;
|
|
assign int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 =
|
|
int_sqrt_fNext_27$D_OUT[347:232] < sum__h36572 ;
|
|
assign int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 =
|
|
int_sqrt_fNext_28$D_OUT[347:232] < sum__h36972 ;
|
|
assign int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 =
|
|
int_sqrt_fNext_29$D_OUT[347:232] < sum__h37372 ;
|
|
assign int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 =
|
|
int_sqrt_fNext_2$D_OUT[347:232] < sum__h26572 ;
|
|
assign int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 =
|
|
int_sqrt_fNext_30$D_OUT[347:232] < sum__h37772 ;
|
|
assign int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 =
|
|
int_sqrt_fNext_31$D_OUT[347:232] < sum__h38172 ;
|
|
assign int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 =
|
|
int_sqrt_fNext_32$D_OUT[347:232] < sum__h38572 ;
|
|
assign int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 =
|
|
int_sqrt_fNext_33$D_OUT[347:232] < sum__h38972 ;
|
|
assign int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 =
|
|
int_sqrt_fNext_34$D_OUT[347:232] < sum__h39372 ;
|
|
assign int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 =
|
|
int_sqrt_fNext_35$D_OUT[347:232] < sum__h39772 ;
|
|
assign int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 =
|
|
int_sqrt_fNext_36$D_OUT[347:232] < sum__h40172 ;
|
|
assign int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 =
|
|
int_sqrt_fNext_37$D_OUT[347:232] < sum__h40572 ;
|
|
assign int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 =
|
|
int_sqrt_fNext_38$D_OUT[347:232] < sum__h40972 ;
|
|
assign int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 =
|
|
int_sqrt_fNext_39$D_OUT[347:232] < sum__h41372 ;
|
|
assign int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 =
|
|
int_sqrt_fNext_3$D_OUT[347:232] < sum__h26972 ;
|
|
assign int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 =
|
|
int_sqrt_fNext_40$D_OUT[347:232] < sum__h41772 ;
|
|
assign int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 =
|
|
int_sqrt_fNext_41$D_OUT[347:232] < sum__h42172 ;
|
|
assign int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 =
|
|
int_sqrt_fNext_42$D_OUT[347:232] < sum__h42572 ;
|
|
assign int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 =
|
|
int_sqrt_fNext_43$D_OUT[347:232] < sum__h42972 ;
|
|
assign int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 =
|
|
int_sqrt_fNext_44$D_OUT[347:232] < sum__h43372 ;
|
|
assign int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 =
|
|
int_sqrt_fNext_45$D_OUT[347:232] < sum__h43772 ;
|
|
assign int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 =
|
|
int_sqrt_fNext_46$D_OUT[347:232] < sum__h44172 ;
|
|
assign int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 =
|
|
int_sqrt_fNext_47$D_OUT[347:232] < sum__h44572 ;
|
|
assign int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 =
|
|
int_sqrt_fNext_48$D_OUT[347:232] < sum__h44972 ;
|
|
assign int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 =
|
|
int_sqrt_fNext_49$D_OUT[347:232] < sum__h45372 ;
|
|
assign int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 =
|
|
int_sqrt_fNext_4$D_OUT[347:232] < sum__h27372 ;
|
|
assign int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 =
|
|
int_sqrt_fNext_50$D_OUT[347:232] < sum__h45772 ;
|
|
assign int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 =
|
|
int_sqrt_fNext_51$D_OUT[347:232] < sum__h46172 ;
|
|
assign int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 =
|
|
int_sqrt_fNext_52$D_OUT[347:232] < sum__h46572 ;
|
|
assign int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 =
|
|
int_sqrt_fNext_53$D_OUT[347:232] < sum__h46972 ;
|
|
assign int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 =
|
|
int_sqrt_fNext_54$D_OUT[347:232] < sum__h47372 ;
|
|
assign int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 =
|
|
int_sqrt_fNext_55$D_OUT[347:232] < sum__h47772 ;
|
|
assign int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 =
|
|
int_sqrt_fNext_56$D_OUT[347:232] < sum__h48172 ;
|
|
assign int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 =
|
|
int_sqrt_fNext_57$D_OUT[347:232] < sum__h48572 ;
|
|
assign int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 =
|
|
int_sqrt_fNext_5$D_OUT[347:232] < sum__h27772 ;
|
|
assign int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 =
|
|
int_sqrt_fNext_6$D_OUT[347:232] < sum__h28172 ;
|
|
assign int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 =
|
|
int_sqrt_fNext_7$D_OUT[347:232] < sum__h28572 ;
|
|
assign int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 =
|
|
int_sqrt_fNext_8$D_OUT[347:232] < sum__h28972 ;
|
|
assign int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 =
|
|
int_sqrt_fNext_9$D_OUT[347:232] < sum__h29372 ;
|
|
assign out_exp__h76431 =
|
|
fpu_fState_S4$D_OUT[2] ?
|
|
_theResult___exp__h76428 :
|
|
fpu_fState_S4$D_OUT[64:54] ;
|
|
assign out_sfd__h76432 =
|
|
fpu_fState_S4$D_OUT[2] ?
|
|
_theResult___sfd__h76429 :
|
|
fpu_fState_S4$D_OUT[53:2] ;
|
|
assign r__h25386 = r__h25394 + int_sqrt_fFirst$D_OUT[115:0] ;
|
|
assign r__h25394 = { 1'd0, int_sqrt_fFirst$D_OUT[231:117] } ;
|
|
assign r__h25786 = r__h25794 + int_sqrt_fNext_0$D_OUT[115:0] ;
|
|
assign r__h25794 = { 1'd0, int_sqrt_fNext_0$D_OUT[231:117] } ;
|
|
assign r__h26186 = r__h26194 + int_sqrt_fNext_1$D_OUT[115:0] ;
|
|
assign r__h26194 = { 1'd0, int_sqrt_fNext_1$D_OUT[231:117] } ;
|
|
assign r__h26586 = r__h26594 + int_sqrt_fNext_2$D_OUT[115:0] ;
|
|
assign r__h26594 = { 1'd0, int_sqrt_fNext_2$D_OUT[231:117] } ;
|
|
assign r__h26986 = r__h26994 + int_sqrt_fNext_3$D_OUT[115:0] ;
|
|
assign r__h26994 = { 1'd0, int_sqrt_fNext_3$D_OUT[231:117] } ;
|
|
assign r__h27386 = r__h27394 + int_sqrt_fNext_4$D_OUT[115:0] ;
|
|
assign r__h27394 = { 1'd0, int_sqrt_fNext_4$D_OUT[231:117] } ;
|
|
assign r__h27786 = r__h27794 + int_sqrt_fNext_5$D_OUT[115:0] ;
|
|
assign r__h27794 = { 1'd0, int_sqrt_fNext_5$D_OUT[231:117] } ;
|
|
assign r__h28186 = r__h28194 + int_sqrt_fNext_6$D_OUT[115:0] ;
|
|
assign r__h28194 = { 1'd0, int_sqrt_fNext_6$D_OUT[231:117] } ;
|
|
assign r__h28586 = r__h28594 + int_sqrt_fNext_7$D_OUT[115:0] ;
|
|
assign r__h28594 = { 1'd0, int_sqrt_fNext_7$D_OUT[231:117] } ;
|
|
assign r__h28986 = r__h28994 + int_sqrt_fNext_8$D_OUT[115:0] ;
|
|
assign r__h28994 = { 1'd0, int_sqrt_fNext_8$D_OUT[231:117] } ;
|
|
assign r__h29386 = r__h29394 + int_sqrt_fNext_9$D_OUT[115:0] ;
|
|
assign r__h29394 = { 1'd0, int_sqrt_fNext_9$D_OUT[231:117] } ;
|
|
assign r__h29786 = r__h29794 + int_sqrt_fNext_10$D_OUT[115:0] ;
|
|
assign r__h29794 = { 1'd0, int_sqrt_fNext_10$D_OUT[231:117] } ;
|
|
assign r__h30186 = r__h30194 + int_sqrt_fNext_11$D_OUT[115:0] ;
|
|
assign r__h30194 = { 1'd0, int_sqrt_fNext_11$D_OUT[231:117] } ;
|
|
assign r__h30586 = r__h30594 + int_sqrt_fNext_12$D_OUT[115:0] ;
|
|
assign r__h30594 = { 1'd0, int_sqrt_fNext_12$D_OUT[231:117] } ;
|
|
assign r__h30986 = r__h30994 + int_sqrt_fNext_13$D_OUT[115:0] ;
|
|
assign r__h30994 = { 1'd0, int_sqrt_fNext_13$D_OUT[231:117] } ;
|
|
assign r__h31386 = r__h31394 + int_sqrt_fNext_14$D_OUT[115:0] ;
|
|
assign r__h31394 = { 1'd0, int_sqrt_fNext_14$D_OUT[231:117] } ;
|
|
assign r__h31786 = r__h31794 + int_sqrt_fNext_15$D_OUT[115:0] ;
|
|
assign r__h31794 = { 1'd0, int_sqrt_fNext_15$D_OUT[231:117] } ;
|
|
assign r__h32186 = r__h32194 + int_sqrt_fNext_16$D_OUT[115:0] ;
|
|
assign r__h32194 = { 1'd0, int_sqrt_fNext_16$D_OUT[231:117] } ;
|
|
assign r__h32586 = r__h32594 + int_sqrt_fNext_17$D_OUT[115:0] ;
|
|
assign r__h32594 = { 1'd0, int_sqrt_fNext_17$D_OUT[231:117] } ;
|
|
assign r__h32986 = r__h32994 + int_sqrt_fNext_18$D_OUT[115:0] ;
|
|
assign r__h32994 = { 1'd0, int_sqrt_fNext_18$D_OUT[231:117] } ;
|
|
assign r__h33386 = r__h33394 + int_sqrt_fNext_19$D_OUT[115:0] ;
|
|
assign r__h33394 = { 1'd0, int_sqrt_fNext_19$D_OUT[231:117] } ;
|
|
assign r__h33786 = r__h33794 + int_sqrt_fNext_20$D_OUT[115:0] ;
|
|
assign r__h33794 = { 1'd0, int_sqrt_fNext_20$D_OUT[231:117] } ;
|
|
assign r__h34186 = r__h34194 + int_sqrt_fNext_21$D_OUT[115:0] ;
|
|
assign r__h34194 = { 1'd0, int_sqrt_fNext_21$D_OUT[231:117] } ;
|
|
assign r__h34586 = r__h34594 + int_sqrt_fNext_22$D_OUT[115:0] ;
|
|
assign r__h34594 = { 1'd0, int_sqrt_fNext_22$D_OUT[231:117] } ;
|
|
assign r__h34986 = r__h34994 + int_sqrt_fNext_23$D_OUT[115:0] ;
|
|
assign r__h34994 = { 1'd0, int_sqrt_fNext_23$D_OUT[231:117] } ;
|
|
assign r__h35386 = r__h35394 + int_sqrt_fNext_24$D_OUT[115:0] ;
|
|
assign r__h35394 = { 1'd0, int_sqrt_fNext_24$D_OUT[231:117] } ;
|
|
assign r__h35786 = r__h35794 + int_sqrt_fNext_25$D_OUT[115:0] ;
|
|
assign r__h35794 = { 1'd0, int_sqrt_fNext_25$D_OUT[231:117] } ;
|
|
assign r__h36186 = r__h36194 + int_sqrt_fNext_26$D_OUT[115:0] ;
|
|
assign r__h36194 = { 1'd0, int_sqrt_fNext_26$D_OUT[231:117] } ;
|
|
assign r__h36586 = r__h36594 + int_sqrt_fNext_27$D_OUT[115:0] ;
|
|
assign r__h36594 = { 1'd0, int_sqrt_fNext_27$D_OUT[231:117] } ;
|
|
assign r__h36986 = r__h36994 + int_sqrt_fNext_28$D_OUT[115:0] ;
|
|
assign r__h36994 = { 1'd0, int_sqrt_fNext_28$D_OUT[231:117] } ;
|
|
assign r__h37386 = r__h37394 + int_sqrt_fNext_29$D_OUT[115:0] ;
|
|
assign r__h37394 = { 1'd0, int_sqrt_fNext_29$D_OUT[231:117] } ;
|
|
assign r__h37786 = r__h37794 + int_sqrt_fNext_30$D_OUT[115:0] ;
|
|
assign r__h37794 = { 1'd0, int_sqrt_fNext_30$D_OUT[231:117] } ;
|
|
assign r__h38186 = r__h38194 + int_sqrt_fNext_31$D_OUT[115:0] ;
|
|
assign r__h38194 = { 1'd0, int_sqrt_fNext_31$D_OUT[231:117] } ;
|
|
assign r__h38586 = r__h38594 + int_sqrt_fNext_32$D_OUT[115:0] ;
|
|
assign r__h38594 = { 1'd0, int_sqrt_fNext_32$D_OUT[231:117] } ;
|
|
assign r__h38986 = r__h38994 + int_sqrt_fNext_33$D_OUT[115:0] ;
|
|
assign r__h38994 = { 1'd0, int_sqrt_fNext_33$D_OUT[231:117] } ;
|
|
assign r__h39386 = r__h39394 + int_sqrt_fNext_34$D_OUT[115:0] ;
|
|
assign r__h39394 = { 1'd0, int_sqrt_fNext_34$D_OUT[231:117] } ;
|
|
assign r__h39786 = r__h39794 + int_sqrt_fNext_35$D_OUT[115:0] ;
|
|
assign r__h39794 = { 1'd0, int_sqrt_fNext_35$D_OUT[231:117] } ;
|
|
assign r__h40186 = r__h40194 + int_sqrt_fNext_36$D_OUT[115:0] ;
|
|
assign r__h40194 = { 1'd0, int_sqrt_fNext_36$D_OUT[231:117] } ;
|
|
assign r__h40586 = r__h40594 + int_sqrt_fNext_37$D_OUT[115:0] ;
|
|
assign r__h40594 = { 1'd0, int_sqrt_fNext_37$D_OUT[231:117] } ;
|
|
assign r__h40986 = r__h40994 + int_sqrt_fNext_38$D_OUT[115:0] ;
|
|
assign r__h40994 = { 1'd0, int_sqrt_fNext_38$D_OUT[231:117] } ;
|
|
assign r__h41386 = r__h41394 + int_sqrt_fNext_39$D_OUT[115:0] ;
|
|
assign r__h41394 = { 1'd0, int_sqrt_fNext_39$D_OUT[231:117] } ;
|
|
assign r__h41786 = r__h41794 + int_sqrt_fNext_40$D_OUT[115:0] ;
|
|
assign r__h41794 = { 1'd0, int_sqrt_fNext_40$D_OUT[231:117] } ;
|
|
assign r__h42186 = r__h42194 + int_sqrt_fNext_41$D_OUT[115:0] ;
|
|
assign r__h42194 = { 1'd0, int_sqrt_fNext_41$D_OUT[231:117] } ;
|
|
assign r__h42586 = r__h42594 + int_sqrt_fNext_42$D_OUT[115:0] ;
|
|
assign r__h42594 = { 1'd0, int_sqrt_fNext_42$D_OUT[231:117] } ;
|
|
assign r__h42986 = r__h42994 + int_sqrt_fNext_43$D_OUT[115:0] ;
|
|
assign r__h42994 = { 1'd0, int_sqrt_fNext_43$D_OUT[231:117] } ;
|
|
assign r__h43386 = r__h43394 + int_sqrt_fNext_44$D_OUT[115:0] ;
|
|
assign r__h43394 = { 1'd0, int_sqrt_fNext_44$D_OUT[231:117] } ;
|
|
assign r__h43786 = r__h43794 + int_sqrt_fNext_45$D_OUT[115:0] ;
|
|
assign r__h43794 = { 1'd0, int_sqrt_fNext_45$D_OUT[231:117] } ;
|
|
assign r__h44186 = r__h44194 + int_sqrt_fNext_46$D_OUT[115:0] ;
|
|
assign r__h44194 = { 1'd0, int_sqrt_fNext_46$D_OUT[231:117] } ;
|
|
assign r__h44586 = r__h44594 + int_sqrt_fNext_47$D_OUT[115:0] ;
|
|
assign r__h44594 = { 1'd0, int_sqrt_fNext_47$D_OUT[231:117] } ;
|
|
assign r__h44986 = r__h44994 + int_sqrt_fNext_48$D_OUT[115:0] ;
|
|
assign r__h44994 = { 1'd0, int_sqrt_fNext_48$D_OUT[231:117] } ;
|
|
assign r__h45386 = r__h45394 + int_sqrt_fNext_49$D_OUT[115:0] ;
|
|
assign r__h45394 = { 1'd0, int_sqrt_fNext_49$D_OUT[231:117] } ;
|
|
assign r__h45786 = r__h45794 + int_sqrt_fNext_50$D_OUT[115:0] ;
|
|
assign r__h45794 = { 1'd0, int_sqrt_fNext_50$D_OUT[231:117] } ;
|
|
assign r__h46186 = r__h46194 + int_sqrt_fNext_51$D_OUT[115:0] ;
|
|
assign r__h46194 = { 1'd0, int_sqrt_fNext_51$D_OUT[231:117] } ;
|
|
assign r__h46586 = r__h46594 + int_sqrt_fNext_52$D_OUT[115:0] ;
|
|
assign r__h46594 = { 1'd0, int_sqrt_fNext_52$D_OUT[231:117] } ;
|
|
assign r__h46986 = r__h46994 + int_sqrt_fNext_53$D_OUT[115:0] ;
|
|
assign r__h46994 = { 1'd0, int_sqrt_fNext_53$D_OUT[231:117] } ;
|
|
assign r__h47386 = r__h47394 + int_sqrt_fNext_54$D_OUT[115:0] ;
|
|
assign r__h47394 = { 1'd0, int_sqrt_fNext_54$D_OUT[231:117] } ;
|
|
assign r__h47786 = r__h47794 + int_sqrt_fNext_55$D_OUT[115:0] ;
|
|
assign r__h47794 = { 1'd0, int_sqrt_fNext_55$D_OUT[231:117] } ;
|
|
assign r__h48186 = r__h48194 + int_sqrt_fNext_56$D_OUT[115:0] ;
|
|
assign r__h48194 = { 1'd0, int_sqrt_fNext_56$D_OUT[231:117] } ;
|
|
assign r__h48586 = r__h48594 + int_sqrt_fNext_57$D_OUT[115:0] ;
|
|
assign r__h48594 = { 1'd0, int_sqrt_fNext_57$D_OUT[231:117] } ;
|
|
assign result__h66451 = { int_sqrt_fResponse$D_OUT[59:2], 1'd1 } ;
|
|
assign s__h25385 = int_sqrt_fFirst$D_OUT[347:232] - sum__h25372 ;
|
|
assign s__h25785 = int_sqrt_fNext_0$D_OUT[347:232] - sum__h25772 ;
|
|
assign s__h26185 = int_sqrt_fNext_1$D_OUT[347:232] - sum__h26172 ;
|
|
assign s__h26585 = int_sqrt_fNext_2$D_OUT[347:232] - sum__h26572 ;
|
|
assign s__h26985 = int_sqrt_fNext_3$D_OUT[347:232] - sum__h26972 ;
|
|
assign s__h27385 = int_sqrt_fNext_4$D_OUT[347:232] - sum__h27372 ;
|
|
assign s__h27785 = int_sqrt_fNext_5$D_OUT[347:232] - sum__h27772 ;
|
|
assign s__h28185 = int_sqrt_fNext_6$D_OUT[347:232] - sum__h28172 ;
|
|
assign s__h28585 = int_sqrt_fNext_7$D_OUT[347:232] - sum__h28572 ;
|
|
assign s__h28985 = int_sqrt_fNext_8$D_OUT[347:232] - sum__h28972 ;
|
|
assign s__h29385 = int_sqrt_fNext_9$D_OUT[347:232] - sum__h29372 ;
|
|
assign s__h29785 = int_sqrt_fNext_10$D_OUT[347:232] - sum__h29772 ;
|
|
assign s__h30185 = int_sqrt_fNext_11$D_OUT[347:232] - sum__h30172 ;
|
|
assign s__h30585 = int_sqrt_fNext_12$D_OUT[347:232] - sum__h30572 ;
|
|
assign s__h30985 = int_sqrt_fNext_13$D_OUT[347:232] - sum__h30972 ;
|
|
assign s__h31385 = int_sqrt_fNext_14$D_OUT[347:232] - sum__h31372 ;
|
|
assign s__h31785 = int_sqrt_fNext_15$D_OUT[347:232] - sum__h31772 ;
|
|
assign s__h32185 = int_sqrt_fNext_16$D_OUT[347:232] - sum__h32172 ;
|
|
assign s__h32585 = int_sqrt_fNext_17$D_OUT[347:232] - sum__h32572 ;
|
|
assign s__h32985 = int_sqrt_fNext_18$D_OUT[347:232] - sum__h32972 ;
|
|
assign s__h33385 = int_sqrt_fNext_19$D_OUT[347:232] - sum__h33372 ;
|
|
assign s__h33785 = int_sqrt_fNext_20$D_OUT[347:232] - sum__h33772 ;
|
|
assign s__h34185 = int_sqrt_fNext_21$D_OUT[347:232] - sum__h34172 ;
|
|
assign s__h34585 = int_sqrt_fNext_22$D_OUT[347:232] - sum__h34572 ;
|
|
assign s__h34985 = int_sqrt_fNext_23$D_OUT[347:232] - sum__h34972 ;
|
|
assign s__h35385 = int_sqrt_fNext_24$D_OUT[347:232] - sum__h35372 ;
|
|
assign s__h35785 = int_sqrt_fNext_25$D_OUT[347:232] - sum__h35772 ;
|
|
assign s__h36185 = int_sqrt_fNext_26$D_OUT[347:232] - sum__h36172 ;
|
|
assign s__h36585 = int_sqrt_fNext_27$D_OUT[347:232] - sum__h36572 ;
|
|
assign s__h36985 = int_sqrt_fNext_28$D_OUT[347:232] - sum__h36972 ;
|
|
assign s__h37385 = int_sqrt_fNext_29$D_OUT[347:232] - sum__h37372 ;
|
|
assign s__h37785 = int_sqrt_fNext_30$D_OUT[347:232] - sum__h37772 ;
|
|
assign s__h38185 = int_sqrt_fNext_31$D_OUT[347:232] - sum__h38172 ;
|
|
assign s__h38585 = int_sqrt_fNext_32$D_OUT[347:232] - sum__h38572 ;
|
|
assign s__h38985 = int_sqrt_fNext_33$D_OUT[347:232] - sum__h38972 ;
|
|
assign s__h39385 = int_sqrt_fNext_34$D_OUT[347:232] - sum__h39372 ;
|
|
assign s__h39785 = int_sqrt_fNext_35$D_OUT[347:232] - sum__h39772 ;
|
|
assign s__h40185 = int_sqrt_fNext_36$D_OUT[347:232] - sum__h40172 ;
|
|
assign s__h40585 = int_sqrt_fNext_37$D_OUT[347:232] - sum__h40572 ;
|
|
assign s__h40985 = int_sqrt_fNext_38$D_OUT[347:232] - sum__h40972 ;
|
|
assign s__h41385 = int_sqrt_fNext_39$D_OUT[347:232] - sum__h41372 ;
|
|
assign s__h41785 = int_sqrt_fNext_40$D_OUT[347:232] - sum__h41772 ;
|
|
assign s__h42185 = int_sqrt_fNext_41$D_OUT[347:232] - sum__h42172 ;
|
|
assign s__h42585 = int_sqrt_fNext_42$D_OUT[347:232] - sum__h42572 ;
|
|
assign s__h42985 = int_sqrt_fNext_43$D_OUT[347:232] - sum__h42972 ;
|
|
assign s__h43385 = int_sqrt_fNext_44$D_OUT[347:232] - sum__h43372 ;
|
|
assign s__h43785 = int_sqrt_fNext_45$D_OUT[347:232] - sum__h43772 ;
|
|
assign s__h44185 = int_sqrt_fNext_46$D_OUT[347:232] - sum__h44172 ;
|
|
assign s__h44585 = int_sqrt_fNext_47$D_OUT[347:232] - sum__h44572 ;
|
|
assign s__h44985 = int_sqrt_fNext_48$D_OUT[347:232] - sum__h44972 ;
|
|
assign s__h45385 = int_sqrt_fNext_49$D_OUT[347:232] - sum__h45372 ;
|
|
assign s__h45785 = int_sqrt_fNext_50$D_OUT[347:232] - sum__h45772 ;
|
|
assign s__h46185 = int_sqrt_fNext_51$D_OUT[347:232] - sum__h46172 ;
|
|
assign s__h46585 = int_sqrt_fNext_52$D_OUT[347:232] - sum__h46572 ;
|
|
assign s__h46985 = int_sqrt_fNext_53$D_OUT[347:232] - sum__h46972 ;
|
|
assign s__h47385 = int_sqrt_fNext_54$D_OUT[347:232] - sum__h47372 ;
|
|
assign s__h47785 = int_sqrt_fNext_55$D_OUT[347:232] - sum__h47772 ;
|
|
assign s__h48185 = int_sqrt_fNext_56$D_OUT[347:232] - sum__h48172 ;
|
|
assign s__h48585 = int_sqrt_fNext_57$D_OUT[347:232] - sum__h48572 ;
|
|
assign sfd___1__h65692 = { 1'd0, sfd__h49938[57:1] } ;
|
|
assign sfd__h49936 = { value__h58164, 4'd0 } ;
|
|
assign sfd__h49938 = sfd__h49936 << x__h65722 ;
|
|
assign sfd__h49989 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ;
|
|
assign sfd__h75932 =
|
|
{ 1'b0,
|
|
fpu_fState_S4$D_OUT[64:54] != 11'd0,
|
|
fpu_fState_S4$D_OUT[53:2] } +
|
|
54'd1 ;
|
|
assign sfdin__h75260 =
|
|
fpu_fState_S3$D_OUT[58] ?
|
|
_theResult___snd__h75283 :
|
|
_theResult___snd__h75298 ;
|
|
assign sum__h25372 =
|
|
int_sqrt_fFirst$D_OUT[231:116] + int_sqrt_fFirst$D_OUT[115:0] ;
|
|
assign sum__h25772 =
|
|
int_sqrt_fNext_0$D_OUT[231:116] + int_sqrt_fNext_0$D_OUT[115:0] ;
|
|
assign sum__h26172 =
|
|
int_sqrt_fNext_1$D_OUT[231:116] + int_sqrt_fNext_1$D_OUT[115:0] ;
|
|
assign sum__h26572 =
|
|
int_sqrt_fNext_2$D_OUT[231:116] + int_sqrt_fNext_2$D_OUT[115:0] ;
|
|
assign sum__h26972 =
|
|
int_sqrt_fNext_3$D_OUT[231:116] + int_sqrt_fNext_3$D_OUT[115:0] ;
|
|
assign sum__h27372 =
|
|
int_sqrt_fNext_4$D_OUT[231:116] + int_sqrt_fNext_4$D_OUT[115:0] ;
|
|
assign sum__h27772 =
|
|
int_sqrt_fNext_5$D_OUT[231:116] + int_sqrt_fNext_5$D_OUT[115:0] ;
|
|
assign sum__h28172 =
|
|
int_sqrt_fNext_6$D_OUT[231:116] + int_sqrt_fNext_6$D_OUT[115:0] ;
|
|
assign sum__h28572 =
|
|
int_sqrt_fNext_7$D_OUT[231:116] + int_sqrt_fNext_7$D_OUT[115:0] ;
|
|
assign sum__h28972 =
|
|
int_sqrt_fNext_8$D_OUT[231:116] + int_sqrt_fNext_8$D_OUT[115:0] ;
|
|
assign sum__h29372 =
|
|
int_sqrt_fNext_9$D_OUT[231:116] + int_sqrt_fNext_9$D_OUT[115:0] ;
|
|
assign sum__h29772 =
|
|
int_sqrt_fNext_10$D_OUT[231:116] +
|
|
int_sqrt_fNext_10$D_OUT[115:0] ;
|
|
assign sum__h30172 =
|
|
int_sqrt_fNext_11$D_OUT[231:116] +
|
|
int_sqrt_fNext_11$D_OUT[115:0] ;
|
|
assign sum__h30572 =
|
|
int_sqrt_fNext_12$D_OUT[231:116] +
|
|
int_sqrt_fNext_12$D_OUT[115:0] ;
|
|
assign sum__h30972 =
|
|
int_sqrt_fNext_13$D_OUT[231:116] +
|
|
int_sqrt_fNext_13$D_OUT[115:0] ;
|
|
assign sum__h31372 =
|
|
int_sqrt_fNext_14$D_OUT[231:116] +
|
|
int_sqrt_fNext_14$D_OUT[115:0] ;
|
|
assign sum__h31772 =
|
|
int_sqrt_fNext_15$D_OUT[231:116] +
|
|
int_sqrt_fNext_15$D_OUT[115:0] ;
|
|
assign sum__h32172 =
|
|
int_sqrt_fNext_16$D_OUT[231:116] +
|
|
int_sqrt_fNext_16$D_OUT[115:0] ;
|
|
assign sum__h32572 =
|
|
int_sqrt_fNext_17$D_OUT[231:116] +
|
|
int_sqrt_fNext_17$D_OUT[115:0] ;
|
|
assign sum__h32972 =
|
|
int_sqrt_fNext_18$D_OUT[231:116] +
|
|
int_sqrt_fNext_18$D_OUT[115:0] ;
|
|
assign sum__h33372 =
|
|
int_sqrt_fNext_19$D_OUT[231:116] +
|
|
int_sqrt_fNext_19$D_OUT[115:0] ;
|
|
assign sum__h33772 =
|
|
int_sqrt_fNext_20$D_OUT[231:116] +
|
|
int_sqrt_fNext_20$D_OUT[115:0] ;
|
|
assign sum__h34172 =
|
|
int_sqrt_fNext_21$D_OUT[231:116] +
|
|
int_sqrt_fNext_21$D_OUT[115:0] ;
|
|
assign sum__h34572 =
|
|
int_sqrt_fNext_22$D_OUT[231:116] +
|
|
int_sqrt_fNext_22$D_OUT[115:0] ;
|
|
assign sum__h34972 =
|
|
int_sqrt_fNext_23$D_OUT[231:116] +
|
|
int_sqrt_fNext_23$D_OUT[115:0] ;
|
|
assign sum__h35372 =
|
|
int_sqrt_fNext_24$D_OUT[231:116] +
|
|
int_sqrt_fNext_24$D_OUT[115:0] ;
|
|
assign sum__h35772 =
|
|
int_sqrt_fNext_25$D_OUT[231:116] +
|
|
int_sqrt_fNext_25$D_OUT[115:0] ;
|
|
assign sum__h36172 =
|
|
int_sqrt_fNext_26$D_OUT[231:116] +
|
|
int_sqrt_fNext_26$D_OUT[115:0] ;
|
|
assign sum__h36572 =
|
|
int_sqrt_fNext_27$D_OUT[231:116] +
|
|
int_sqrt_fNext_27$D_OUT[115:0] ;
|
|
assign sum__h36972 =
|
|
int_sqrt_fNext_28$D_OUT[231:116] +
|
|
int_sqrt_fNext_28$D_OUT[115:0] ;
|
|
assign sum__h37372 =
|
|
int_sqrt_fNext_29$D_OUT[231:116] +
|
|
int_sqrt_fNext_29$D_OUT[115:0] ;
|
|
assign sum__h37772 =
|
|
int_sqrt_fNext_30$D_OUT[231:116] +
|
|
int_sqrt_fNext_30$D_OUT[115:0] ;
|
|
assign sum__h38172 =
|
|
int_sqrt_fNext_31$D_OUT[231:116] +
|
|
int_sqrt_fNext_31$D_OUT[115:0] ;
|
|
assign sum__h38572 =
|
|
int_sqrt_fNext_32$D_OUT[231:116] +
|
|
int_sqrt_fNext_32$D_OUT[115:0] ;
|
|
assign sum__h38972 =
|
|
int_sqrt_fNext_33$D_OUT[231:116] +
|
|
int_sqrt_fNext_33$D_OUT[115:0] ;
|
|
assign sum__h39372 =
|
|
int_sqrt_fNext_34$D_OUT[231:116] +
|
|
int_sqrt_fNext_34$D_OUT[115:0] ;
|
|
assign sum__h39772 =
|
|
int_sqrt_fNext_35$D_OUT[231:116] +
|
|
int_sqrt_fNext_35$D_OUT[115:0] ;
|
|
assign sum__h40172 =
|
|
int_sqrt_fNext_36$D_OUT[231:116] +
|
|
int_sqrt_fNext_36$D_OUT[115:0] ;
|
|
assign sum__h40572 =
|
|
int_sqrt_fNext_37$D_OUT[231:116] +
|
|
int_sqrt_fNext_37$D_OUT[115:0] ;
|
|
assign sum__h40972 =
|
|
int_sqrt_fNext_38$D_OUT[231:116] +
|
|
int_sqrt_fNext_38$D_OUT[115:0] ;
|
|
assign sum__h41372 =
|
|
int_sqrt_fNext_39$D_OUT[231:116] +
|
|
int_sqrt_fNext_39$D_OUT[115:0] ;
|
|
assign sum__h41772 =
|
|
int_sqrt_fNext_40$D_OUT[231:116] +
|
|
int_sqrt_fNext_40$D_OUT[115:0] ;
|
|
assign sum__h42172 =
|
|
int_sqrt_fNext_41$D_OUT[231:116] +
|
|
int_sqrt_fNext_41$D_OUT[115:0] ;
|
|
assign sum__h42572 =
|
|
int_sqrt_fNext_42$D_OUT[231:116] +
|
|
int_sqrt_fNext_42$D_OUT[115:0] ;
|
|
assign sum__h42972 =
|
|
int_sqrt_fNext_43$D_OUT[231:116] +
|
|
int_sqrt_fNext_43$D_OUT[115:0] ;
|
|
assign sum__h43372 =
|
|
int_sqrt_fNext_44$D_OUT[231:116] +
|
|
int_sqrt_fNext_44$D_OUT[115:0] ;
|
|
assign sum__h43772 =
|
|
int_sqrt_fNext_45$D_OUT[231:116] +
|
|
int_sqrt_fNext_45$D_OUT[115:0] ;
|
|
assign sum__h44172 =
|
|
int_sqrt_fNext_46$D_OUT[231:116] +
|
|
int_sqrt_fNext_46$D_OUT[115:0] ;
|
|
assign sum__h44572 =
|
|
int_sqrt_fNext_47$D_OUT[231:116] +
|
|
int_sqrt_fNext_47$D_OUT[115:0] ;
|
|
assign sum__h44972 =
|
|
int_sqrt_fNext_48$D_OUT[231:116] +
|
|
int_sqrt_fNext_48$D_OUT[115:0] ;
|
|
assign sum__h45372 =
|
|
int_sqrt_fNext_49$D_OUT[231:116] +
|
|
int_sqrt_fNext_49$D_OUT[115:0] ;
|
|
assign sum__h45772 =
|
|
int_sqrt_fNext_50$D_OUT[231:116] +
|
|
int_sqrt_fNext_50$D_OUT[115:0] ;
|
|
assign sum__h46172 =
|
|
int_sqrt_fNext_51$D_OUT[231:116] +
|
|
int_sqrt_fNext_51$D_OUT[115:0] ;
|
|
assign sum__h46572 =
|
|
int_sqrt_fNext_52$D_OUT[231:116] +
|
|
int_sqrt_fNext_52$D_OUT[115:0] ;
|
|
assign sum__h46972 =
|
|
int_sqrt_fNext_53$D_OUT[231:116] +
|
|
int_sqrt_fNext_53$D_OUT[115:0] ;
|
|
assign sum__h47372 =
|
|
int_sqrt_fNext_54$D_OUT[231:116] +
|
|
int_sqrt_fNext_54$D_OUT[115:0] ;
|
|
assign sum__h47772 =
|
|
int_sqrt_fNext_55$D_OUT[231:116] +
|
|
int_sqrt_fNext_55$D_OUT[115:0] ;
|
|
assign sum__h48172 =
|
|
int_sqrt_fNext_56$D_OUT[231:116] +
|
|
int_sqrt_fNext_56$D_OUT[115:0] ;
|
|
assign sum__h48572 =
|
|
int_sqrt_fNext_57$D_OUT[231:116] +
|
|
int_sqrt_fNext_57$D_OUT[115:0] ;
|
|
assign value_BIT_52___h58260 = fpu_fOperand_S0$D_OUT[65:55] != 11'd0 ;
|
|
assign value__h58164 =
|
|
{ 1'b0, value_BIT_52___h58260, fpu_fOperand_S0$D_OUT[54:3] } ;
|
|
assign x__h24992 =
|
|
IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237[0] ?
|
|
IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 +
|
|
7'd1 :
|
|
IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 ;
|
|
assign x__h402 =
|
|
int_sqrt_fRequest$D_OUT[115] ?
|
|
116'h40000000000000000000000000000 :
|
|
b___1__h16687 ;
|
|
assign x__h57541 = x__h57559 + 13'd1024 ;
|
|
assign x__h57559 =
|
|
{ IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9[11],
|
|
IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 } ;
|
|
assign x__h65683 =
|
|
IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[0] ?
|
|
sfd__h49938 :
|
|
sfd___1__h65692 ;
|
|
assign x__h65722 =
|
|
IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 -
|
|
6'd1 ;
|
|
assign x__h66665 =
|
|
int_sqrt_fResponse$D_OUT[0] ?
|
|
result__h66451 :
|
|
int_sqrt_fResponse$D_OUT[59:1] ;
|
|
assign x__h75654 =
|
|
(fpu_fState_S3$D_OUT[58] &&
|
|
IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 ==
|
|
12'd1023) ?
|
|
2'd3 :
|
|
_theResult___snd_fst__h75372 ;
|
|
always@(fpu_fState_S4$D_OUT or out_sfd__h76432 or _theResult___sfd__h76429)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0, 2'b01:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 =
|
|
fpu_fState_S4$D_OUT[53:2];
|
|
2'b10:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 =
|
|
out_sfd__h76432;
|
|
2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 =
|
|
_theResult___sfd__h76429;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or _theResult___sfd__h76429)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 =
|
|
fpu_fState_S4$D_OUT[53:2];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 =
|
|
_theResult___sfd__h76429;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or
|
|
_theResult___sfd__h76429)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd0:
|
|
_theResult___fst_sfd__h76507 =
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1;
|
|
3'd1:
|
|
_theResult___fst_sfd__h76507 =
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2;
|
|
3'd2:
|
|
_theResult___fst_sfd__h76507 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ?
|
|
fpu_fState_S4$D_OUT[53:2] :
|
|
_theResult___sfd__h76429;
|
|
3'd3:
|
|
_theResult___fst_sfd__h76507 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0) ?
|
|
fpu_fState_S4$D_OUT[53:2] :
|
|
(fpu_fState_S4$D_OUT[65] ?
|
|
_theResult___sfd__h76429 :
|
|
fpu_fState_S4$D_OUT[53:2]);
|
|
3'd4: _theResult___fst_sfd__h76507 = fpu_fState_S4$D_OUT[53:2];
|
|
default: _theResult___fst_sfd__h76507 = 52'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or out_exp__h76431 or _theResult___exp__h76428)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0, 2'b01:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 =
|
|
fpu_fState_S4$D_OUT[64:54];
|
|
2'b10:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 =
|
|
out_exp__h76431;
|
|
2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 =
|
|
_theResult___exp__h76428;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or _theResult___exp__h76428)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 =
|
|
fpu_fState_S4$D_OUT[64:54];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 =
|
|
_theResult___exp__h76428;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 or
|
|
_theResult___exp__h76428)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd0:
|
|
_theResult___fst_exp__h76506 =
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3;
|
|
3'd1:
|
|
_theResult___fst_exp__h76506 =
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4;
|
|
3'd2:
|
|
_theResult___fst_exp__h76506 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ?
|
|
fpu_fState_S4$D_OUT[64:54] :
|
|
_theResult___exp__h76428;
|
|
3'd3:
|
|
_theResult___fst_exp__h76506 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0) ?
|
|
fpu_fState_S4$D_OUT[64:54] :
|
|
(fpu_fState_S4$D_OUT[65] ?
|
|
_theResult___exp__h76428 :
|
|
fpu_fState_S4$D_OUT[64:54]);
|
|
3'd4: _theResult___fst_exp__h76506 = fpu_fState_S4$D_OUT[64:54];
|
|
default: _theResult___fst_exp__h76506 = 11'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd2, 3'd3:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 =
|
|
fpu_fState_S4$D_OUT[65];
|
|
default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 =
|
|
fpu_fState_S4$D_OUT[68:66] == 3'd4 &&
|
|
fpu_fState_S4$D_OUT[65];
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd2:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ?
|
|
fpu_fState_S4$D_OUT[64:2] :
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866;
|
|
3'd3:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0) ?
|
|
fpu_fState_S4$D_OUT[64:2] :
|
|
(fpu_fState_S4$D_OUT[65] ?
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 :
|
|
fpu_fState_S4$D_OUT[64:2]);
|
|
3'd4:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 =
|
|
fpu_fState_S4$D_OUT[64:2];
|
|
default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = 63'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 =
|
|
fpu_fState_S4$D_OUT[65];
|
|
2'd3:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 =
|
|
fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65];
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0, 2'b01:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 =
|
|
fpu_fState_S4$D_OUT[64:2];
|
|
2'b10:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 =
|
|
fpu_fState_S4$D_OUT[2] ?
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 :
|
|
fpu_fState_S4$D_OUT[64:2];
|
|
2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 =
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = 63'd0;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 =
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd0:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 =
|
|
{ CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 };
|
|
3'd1:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0) ?
|
|
fpu_fState_S4$D_OUT[65:2] :
|
|
{ (fpu_fState_S4$D_OUT[1:0] == 2'b01 ||
|
|
fpu_fState_S4$D_OUT[1:0] == 2'b10 ||
|
|
fpu_fState_S4$D_OUT[1:0] == 2'b11) &&
|
|
fpu_fState_S4$D_OUT[65],
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 };
|
|
default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 =
|
|
{ CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10,
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 };
|
|
endcase
|
|
end
|
|
endmodule // mkDoubleSqrt
|
|
|