5686 lines
227 KiB
Verilog
5686 lines
227 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:15:31 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// flush_done O 1
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// RDY_flush_done O 1 const
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// RDY_flush O 1
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// RDY_updateVMInfo O 1 const
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// noPendingReq O 1
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// RDY_noPendingReq O 1 const
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// RDY_to_proc_request_put O 1
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// to_proc_response_get O 70
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// RDY_to_proc_response_get O 1
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// toParent_rqToP_notEmpty O 1
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// RDY_toParent_rqToP_notEmpty O 1 const
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// RDY_toParent_rqToP_deq O 1
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// toParent_rqToP_first O 27
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// RDY_toParent_rqToP_first O 1
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// toParent_rsFromP_notFull O 1
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// RDY_toParent_rsFromP_notFull O 1 const
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// RDY_toParent_rsFromP_enq O 1
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// RDY_toParent_flush_request_get O 1
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// RDY_toParent_flush_response_put O 1
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// RDY_perf_setStatus O 1 const
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// RDY_perf_req O 1
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// perf_resp O 67
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// RDY_perf_resp O 1
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// perf_respValid O 1
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// RDY_perf_respValid O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// updateVMInfo_vm I 49 reg
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// to_proc_request_put I 64
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// toParent_rsFromP_enq_x I 81
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// perf_setStatus_doStats I 1 unused
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// perf_req_r I 3
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// EN_flush I 1
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// EN_updateVMInfo I 1
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// EN_to_proc_request_put I 1
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// EN_toParent_rqToP_deq I 1
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// EN_toParent_rsFromP_enq I 1
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// EN_toParent_flush_request_get I 1
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// EN_toParent_flush_response_put I 1
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// EN_perf_setStatus I 1 unused
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// EN_perf_req I 1
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// EN_to_proc_response_get I 1
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// EN_perf_resp I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkITlb(CLK,
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RST_N,
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flush_done,
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RDY_flush_done,
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EN_flush,
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RDY_flush,
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updateVMInfo_vm,
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EN_updateVMInfo,
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RDY_updateVMInfo,
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noPendingReq,
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RDY_noPendingReq,
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to_proc_request_put,
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EN_to_proc_request_put,
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RDY_to_proc_request_put,
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EN_to_proc_response_get,
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to_proc_response_get,
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RDY_to_proc_response_get,
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toParent_rqToP_notEmpty,
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RDY_toParent_rqToP_notEmpty,
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EN_toParent_rqToP_deq,
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RDY_toParent_rqToP_deq,
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toParent_rqToP_first,
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RDY_toParent_rqToP_first,
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toParent_rsFromP_notFull,
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RDY_toParent_rsFromP_notFull,
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toParent_rsFromP_enq_x,
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EN_toParent_rsFromP_enq,
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RDY_toParent_rsFromP_enq,
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EN_toParent_flush_request_get,
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RDY_toParent_flush_request_get,
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EN_toParent_flush_response_put,
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RDY_toParent_flush_response_put,
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perf_setStatus_doStats,
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EN_perf_setStatus,
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RDY_perf_setStatus,
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perf_req_r,
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EN_perf_req,
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RDY_perf_req,
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EN_perf_resp,
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perf_resp,
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RDY_perf_resp,
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perf_respValid,
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RDY_perf_respValid);
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input CLK;
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input RST_N;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// action method updateVMInfo
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input [48 : 0] updateVMInfo_vm;
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input EN_updateVMInfo;
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output RDY_updateVMInfo;
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// value method noPendingReq
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output noPendingReq;
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output RDY_noPendingReq;
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// action method to_proc_request_put
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input [63 : 0] to_proc_request_put;
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input EN_to_proc_request_put;
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output RDY_to_proc_request_put;
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// actionvalue method to_proc_response_get
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input EN_to_proc_response_get;
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output [69 : 0] to_proc_response_get;
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output RDY_to_proc_response_get;
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// value method toParent_rqToP_notEmpty
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output toParent_rqToP_notEmpty;
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output RDY_toParent_rqToP_notEmpty;
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// action method toParent_rqToP_deq
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input EN_toParent_rqToP_deq;
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output RDY_toParent_rqToP_deq;
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// value method toParent_rqToP_first
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output [26 : 0] toParent_rqToP_first;
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output RDY_toParent_rqToP_first;
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// value method toParent_rsFromP_notFull
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output toParent_rsFromP_notFull;
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output RDY_toParent_rsFromP_notFull;
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// action method toParent_rsFromP_enq
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input [80 : 0] toParent_rsFromP_enq_x;
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input EN_toParent_rsFromP_enq;
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output RDY_toParent_rsFromP_enq;
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// action method toParent_flush_request_get
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input EN_toParent_flush_request_get;
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output RDY_toParent_flush_request_get;
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// action method toParent_flush_response_put
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input EN_toParent_flush_response_put;
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output RDY_toParent_flush_response_put;
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// action method perf_setStatus
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input perf_setStatus_doStats;
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input EN_perf_setStatus;
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output RDY_perf_setStatus;
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// action method perf_req
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input [2 : 0] perf_req_r;
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input EN_perf_req;
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output RDY_perf_req;
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// actionvalue method perf_resp
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input EN_perf_resp;
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output [66 : 0] perf_resp;
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output RDY_perf_resp;
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// value method perf_respValid
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output perf_respValid;
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output RDY_perf_respValid;
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// signals for module outputs
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reg [26 : 0] toParent_rqToP_first;
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wire [69 : 0] to_proc_response_get;
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wire [66 : 0] perf_resp;
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wire RDY_flush,
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RDY_flush_done,
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RDY_noPendingReq,
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RDY_perf_req,
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RDY_perf_resp,
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RDY_perf_respValid,
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RDY_perf_setStatus,
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RDY_toParent_flush_request_get,
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RDY_toParent_flush_response_put,
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RDY_toParent_rqToP_deq,
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RDY_toParent_rqToP_first,
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RDY_toParent_rqToP_notEmpty,
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RDY_toParent_rsFromP_enq,
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RDY_toParent_rsFromP_notFull,
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RDY_to_proc_request_put,
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RDY_to_proc_response_get,
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RDY_updateVMInfo,
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flush_done,
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noPendingReq,
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perf_respValid,
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toParent_rqToP_notEmpty,
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toParent_rsFromP_notFull;
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// inlined wires
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wire [81 : 0] rsFromPQ_enqReq_lat_0$wget, rsFromPQ_enqReq_lat_2$wget;
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wire [70 : 0] hitQ_enqReq_lat_0$wget, hitQ_enqReq_lat_2$wget;
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wire [27 : 0] rqToPQ_enqReq_lat_0$wget, rqToPQ_enqReq_lat_2$wget;
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wire [5 : 0] tlb_m_updRepIdx_lat_0$wget, tlb_m_updRepIdx_lat_1$wget;
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wire [3 : 0] perfReqQ_enqReq_lat_0$wget, perfReqQ_enqReq_lat_2$wget;
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wire hitQ_enqReq_lat_0$whas,
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tlb_m_lruBit_lat_0$whas,
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tlb_m_updRepIdx_lat_0$whas,
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tlb_m_updRepIdx_lat_1$whas;
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// register flushRqToPQ_clearReq_rl
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reg flushRqToPQ_clearReq_rl;
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wire flushRqToPQ_clearReq_rl$D_IN, flushRqToPQ_clearReq_rl$EN;
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// register flushRqToPQ_deqReq_rl
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reg flushRqToPQ_deqReq_rl;
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wire flushRqToPQ_deqReq_rl$D_IN, flushRqToPQ_deqReq_rl$EN;
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// register flushRqToPQ_empty
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reg flushRqToPQ_empty;
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wire flushRqToPQ_empty$D_IN, flushRqToPQ_empty$EN;
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// register flushRqToPQ_enqReq_rl
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reg flushRqToPQ_enqReq_rl;
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wire flushRqToPQ_enqReq_rl$D_IN, flushRqToPQ_enqReq_rl$EN;
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// register flushRqToPQ_full
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reg flushRqToPQ_full;
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wire flushRqToPQ_full$D_IN, flushRqToPQ_full$EN;
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// register flushRsFromPQ_clearReq_rl
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reg flushRsFromPQ_clearReq_rl;
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wire flushRsFromPQ_clearReq_rl$D_IN, flushRsFromPQ_clearReq_rl$EN;
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// register flushRsFromPQ_deqReq_rl
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reg flushRsFromPQ_deqReq_rl;
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wire flushRsFromPQ_deqReq_rl$D_IN, flushRsFromPQ_deqReq_rl$EN;
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// register flushRsFromPQ_empty
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reg flushRsFromPQ_empty;
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wire flushRsFromPQ_empty$D_IN, flushRsFromPQ_empty$EN;
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// register flushRsFromPQ_enqReq_rl
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reg flushRsFromPQ_enqReq_rl;
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wire flushRsFromPQ_enqReq_rl$D_IN, flushRsFromPQ_enqReq_rl$EN;
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// register flushRsFromPQ_full
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reg flushRsFromPQ_full;
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wire flushRsFromPQ_full$D_IN, flushRsFromPQ_full$EN;
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// register hitQ_clearReq_rl
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reg hitQ_clearReq_rl;
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wire hitQ_clearReq_rl$D_IN, hitQ_clearReq_rl$EN;
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// register hitQ_data_0
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reg [69 : 0] hitQ_data_0;
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wire [69 : 0] hitQ_data_0$D_IN;
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wire hitQ_data_0$EN;
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// register hitQ_data_1
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reg [69 : 0] hitQ_data_1;
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wire [69 : 0] hitQ_data_1$D_IN;
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wire hitQ_data_1$EN;
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// register hitQ_deqP
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reg hitQ_deqP;
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wire hitQ_deqP$D_IN, hitQ_deqP$EN;
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// register hitQ_deqReq_rl
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reg hitQ_deqReq_rl;
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wire hitQ_deqReq_rl$D_IN, hitQ_deqReq_rl$EN;
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// register hitQ_empty
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reg hitQ_empty;
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wire hitQ_empty$D_IN, hitQ_empty$EN;
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// register hitQ_enqP
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reg hitQ_enqP;
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wire hitQ_enqP$D_IN, hitQ_enqP$EN;
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// register hitQ_enqReq_rl
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reg [70 : 0] hitQ_enqReq_rl;
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wire [70 : 0] hitQ_enqReq_rl$D_IN;
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wire hitQ_enqReq_rl$EN;
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// register hitQ_full
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reg hitQ_full;
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wire hitQ_full$D_IN, hitQ_full$EN;
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// register miss
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reg [64 : 0] miss;
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wire [64 : 0] miss$D_IN;
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wire miss$EN;
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// register needFlush
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reg needFlush;
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wire needFlush$D_IN, needFlush$EN;
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// register perfReqQ_clearReq_rl
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reg perfReqQ_clearReq_rl;
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wire perfReqQ_clearReq_rl$D_IN, perfReqQ_clearReq_rl$EN;
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// register perfReqQ_data_0
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reg [2 : 0] perfReqQ_data_0;
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wire [2 : 0] perfReqQ_data_0$D_IN;
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wire perfReqQ_data_0$EN;
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// register perfReqQ_deqReq_rl
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reg perfReqQ_deqReq_rl;
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wire perfReqQ_deqReq_rl$D_IN, perfReqQ_deqReq_rl$EN;
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// register perfReqQ_empty
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reg perfReqQ_empty;
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wire perfReqQ_empty$D_IN, perfReqQ_empty$EN;
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// register perfReqQ_enqReq_rl
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reg [3 : 0] perfReqQ_enqReq_rl;
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wire [3 : 0] perfReqQ_enqReq_rl$D_IN;
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wire perfReqQ_enqReq_rl$EN;
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// register perfReqQ_full
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reg perfReqQ_full;
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wire perfReqQ_full$D_IN, perfReqQ_full$EN;
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// register rqToPQ_clearReq_rl
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reg rqToPQ_clearReq_rl;
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wire rqToPQ_clearReq_rl$D_IN, rqToPQ_clearReq_rl$EN;
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// register rqToPQ_data_0
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reg [26 : 0] rqToPQ_data_0;
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wire [26 : 0] rqToPQ_data_0$D_IN;
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wire rqToPQ_data_0$EN;
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// register rqToPQ_data_1
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reg [26 : 0] rqToPQ_data_1;
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wire [26 : 0] rqToPQ_data_1$D_IN;
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wire rqToPQ_data_1$EN;
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// register rqToPQ_deqP
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reg rqToPQ_deqP;
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wire rqToPQ_deqP$D_IN, rqToPQ_deqP$EN;
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// register rqToPQ_deqReq_rl
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reg rqToPQ_deqReq_rl;
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wire rqToPQ_deqReq_rl$D_IN, rqToPQ_deqReq_rl$EN;
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// register rqToPQ_empty
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reg rqToPQ_empty;
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wire rqToPQ_empty$D_IN, rqToPQ_empty$EN;
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// register rqToPQ_enqP
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reg rqToPQ_enqP;
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wire rqToPQ_enqP$D_IN, rqToPQ_enqP$EN;
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// register rqToPQ_enqReq_rl
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reg [27 : 0] rqToPQ_enqReq_rl;
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wire [27 : 0] rqToPQ_enqReq_rl$D_IN;
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wire rqToPQ_enqReq_rl$EN;
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// register rqToPQ_full
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reg rqToPQ_full;
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wire rqToPQ_full$D_IN, rqToPQ_full$EN;
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// register rsFromPQ_clearReq_rl
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reg rsFromPQ_clearReq_rl;
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wire rsFromPQ_clearReq_rl$D_IN, rsFromPQ_clearReq_rl$EN;
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// register rsFromPQ_data_0
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reg [80 : 0] rsFromPQ_data_0;
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wire [80 : 0] rsFromPQ_data_0$D_IN;
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wire rsFromPQ_data_0$EN;
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// register rsFromPQ_data_1
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reg [80 : 0] rsFromPQ_data_1;
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wire [80 : 0] rsFromPQ_data_1$D_IN;
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wire rsFromPQ_data_1$EN;
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// register rsFromPQ_deqP
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reg rsFromPQ_deqP;
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wire rsFromPQ_deqP$D_IN, rsFromPQ_deqP$EN;
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// register rsFromPQ_deqReq_rl
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reg rsFromPQ_deqReq_rl;
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wire rsFromPQ_deqReq_rl$D_IN, rsFromPQ_deqReq_rl$EN;
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// register rsFromPQ_empty
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reg rsFromPQ_empty;
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wire rsFromPQ_empty$D_IN, rsFromPQ_empty$EN;
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// register rsFromPQ_enqP
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reg rsFromPQ_enqP;
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wire rsFromPQ_enqP$D_IN, rsFromPQ_enqP$EN;
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// register rsFromPQ_enqReq_rl
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reg [81 : 0] rsFromPQ_enqReq_rl;
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wire [81 : 0] rsFromPQ_enqReq_rl$D_IN;
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wire rsFromPQ_enqReq_rl$EN;
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// register rsFromPQ_full
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reg rsFromPQ_full;
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wire rsFromPQ_full$D_IN, rsFromPQ_full$EN;
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// register tlb_m_entryVec_0
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reg [79 : 0] tlb_m_entryVec_0;
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wire [79 : 0] tlb_m_entryVec_0$D_IN;
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wire tlb_m_entryVec_0$EN;
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// register tlb_m_entryVec_1
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reg [79 : 0] tlb_m_entryVec_1;
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wire [79 : 0] tlb_m_entryVec_1$D_IN;
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wire tlb_m_entryVec_1$EN;
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// register tlb_m_entryVec_10
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reg [79 : 0] tlb_m_entryVec_10;
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wire [79 : 0] tlb_m_entryVec_10$D_IN;
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wire tlb_m_entryVec_10$EN;
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// register tlb_m_entryVec_11
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reg [79 : 0] tlb_m_entryVec_11;
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wire [79 : 0] tlb_m_entryVec_11$D_IN;
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wire tlb_m_entryVec_11$EN;
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// register tlb_m_entryVec_12
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reg [79 : 0] tlb_m_entryVec_12;
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wire [79 : 0] tlb_m_entryVec_12$D_IN;
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wire tlb_m_entryVec_12$EN;
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// register tlb_m_entryVec_13
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reg [79 : 0] tlb_m_entryVec_13;
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wire [79 : 0] tlb_m_entryVec_13$D_IN;
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wire tlb_m_entryVec_13$EN;
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// register tlb_m_entryVec_14
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reg [79 : 0] tlb_m_entryVec_14;
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wire [79 : 0] tlb_m_entryVec_14$D_IN;
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wire tlb_m_entryVec_14$EN;
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// register tlb_m_entryVec_15
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reg [79 : 0] tlb_m_entryVec_15;
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wire [79 : 0] tlb_m_entryVec_15$D_IN;
|
|
wire tlb_m_entryVec_15$EN;
|
|
|
|
// register tlb_m_entryVec_16
|
|
reg [79 : 0] tlb_m_entryVec_16;
|
|
wire [79 : 0] tlb_m_entryVec_16$D_IN;
|
|
wire tlb_m_entryVec_16$EN;
|
|
|
|
// register tlb_m_entryVec_17
|
|
reg [79 : 0] tlb_m_entryVec_17;
|
|
wire [79 : 0] tlb_m_entryVec_17$D_IN;
|
|
wire tlb_m_entryVec_17$EN;
|
|
|
|
// register tlb_m_entryVec_18
|
|
reg [79 : 0] tlb_m_entryVec_18;
|
|
wire [79 : 0] tlb_m_entryVec_18$D_IN;
|
|
wire tlb_m_entryVec_18$EN;
|
|
|
|
// register tlb_m_entryVec_19
|
|
reg [79 : 0] tlb_m_entryVec_19;
|
|
wire [79 : 0] tlb_m_entryVec_19$D_IN;
|
|
wire tlb_m_entryVec_19$EN;
|
|
|
|
// register tlb_m_entryVec_2
|
|
reg [79 : 0] tlb_m_entryVec_2;
|
|
wire [79 : 0] tlb_m_entryVec_2$D_IN;
|
|
wire tlb_m_entryVec_2$EN;
|
|
|
|
// register tlb_m_entryVec_20
|
|
reg [79 : 0] tlb_m_entryVec_20;
|
|
wire [79 : 0] tlb_m_entryVec_20$D_IN;
|
|
wire tlb_m_entryVec_20$EN;
|
|
|
|
// register tlb_m_entryVec_21
|
|
reg [79 : 0] tlb_m_entryVec_21;
|
|
wire [79 : 0] tlb_m_entryVec_21$D_IN;
|
|
wire tlb_m_entryVec_21$EN;
|
|
|
|
// register tlb_m_entryVec_22
|
|
reg [79 : 0] tlb_m_entryVec_22;
|
|
wire [79 : 0] tlb_m_entryVec_22$D_IN;
|
|
wire tlb_m_entryVec_22$EN;
|
|
|
|
// register tlb_m_entryVec_23
|
|
reg [79 : 0] tlb_m_entryVec_23;
|
|
wire [79 : 0] tlb_m_entryVec_23$D_IN;
|
|
wire tlb_m_entryVec_23$EN;
|
|
|
|
// register tlb_m_entryVec_24
|
|
reg [79 : 0] tlb_m_entryVec_24;
|
|
wire [79 : 0] tlb_m_entryVec_24$D_IN;
|
|
wire tlb_m_entryVec_24$EN;
|
|
|
|
// register tlb_m_entryVec_25
|
|
reg [79 : 0] tlb_m_entryVec_25;
|
|
wire [79 : 0] tlb_m_entryVec_25$D_IN;
|
|
wire tlb_m_entryVec_25$EN;
|
|
|
|
// register tlb_m_entryVec_26
|
|
reg [79 : 0] tlb_m_entryVec_26;
|
|
wire [79 : 0] tlb_m_entryVec_26$D_IN;
|
|
wire tlb_m_entryVec_26$EN;
|
|
|
|
// register tlb_m_entryVec_27
|
|
reg [79 : 0] tlb_m_entryVec_27;
|
|
wire [79 : 0] tlb_m_entryVec_27$D_IN;
|
|
wire tlb_m_entryVec_27$EN;
|
|
|
|
// register tlb_m_entryVec_28
|
|
reg [79 : 0] tlb_m_entryVec_28;
|
|
wire [79 : 0] tlb_m_entryVec_28$D_IN;
|
|
wire tlb_m_entryVec_28$EN;
|
|
|
|
// register tlb_m_entryVec_29
|
|
reg [79 : 0] tlb_m_entryVec_29;
|
|
wire [79 : 0] tlb_m_entryVec_29$D_IN;
|
|
wire tlb_m_entryVec_29$EN;
|
|
|
|
// register tlb_m_entryVec_3
|
|
reg [79 : 0] tlb_m_entryVec_3;
|
|
wire [79 : 0] tlb_m_entryVec_3$D_IN;
|
|
wire tlb_m_entryVec_3$EN;
|
|
|
|
// register tlb_m_entryVec_30
|
|
reg [79 : 0] tlb_m_entryVec_30;
|
|
wire [79 : 0] tlb_m_entryVec_30$D_IN;
|
|
wire tlb_m_entryVec_30$EN;
|
|
|
|
// register tlb_m_entryVec_31
|
|
reg [79 : 0] tlb_m_entryVec_31;
|
|
wire [79 : 0] tlb_m_entryVec_31$D_IN;
|
|
wire tlb_m_entryVec_31$EN;
|
|
|
|
// register tlb_m_entryVec_4
|
|
reg [79 : 0] tlb_m_entryVec_4;
|
|
wire [79 : 0] tlb_m_entryVec_4$D_IN;
|
|
wire tlb_m_entryVec_4$EN;
|
|
|
|
// register tlb_m_entryVec_5
|
|
reg [79 : 0] tlb_m_entryVec_5;
|
|
wire [79 : 0] tlb_m_entryVec_5$D_IN;
|
|
wire tlb_m_entryVec_5$EN;
|
|
|
|
// register tlb_m_entryVec_6
|
|
reg [79 : 0] tlb_m_entryVec_6;
|
|
wire [79 : 0] tlb_m_entryVec_6$D_IN;
|
|
wire tlb_m_entryVec_6$EN;
|
|
|
|
// register tlb_m_entryVec_7
|
|
reg [79 : 0] tlb_m_entryVec_7;
|
|
wire [79 : 0] tlb_m_entryVec_7$D_IN;
|
|
wire tlb_m_entryVec_7$EN;
|
|
|
|
// register tlb_m_entryVec_8
|
|
reg [79 : 0] tlb_m_entryVec_8;
|
|
wire [79 : 0] tlb_m_entryVec_8$D_IN;
|
|
wire tlb_m_entryVec_8$EN;
|
|
|
|
// register tlb_m_entryVec_9
|
|
reg [79 : 0] tlb_m_entryVec_9;
|
|
wire [79 : 0] tlb_m_entryVec_9$D_IN;
|
|
wire tlb_m_entryVec_9$EN;
|
|
|
|
// register tlb_m_lruBit_rl
|
|
reg [31 : 0] tlb_m_lruBit_rl;
|
|
wire [31 : 0] tlb_m_lruBit_rl$D_IN;
|
|
wire tlb_m_lruBit_rl$EN;
|
|
|
|
// register tlb_m_randIdx
|
|
reg [4 : 0] tlb_m_randIdx;
|
|
wire [4 : 0] tlb_m_randIdx$D_IN;
|
|
wire tlb_m_randIdx$EN;
|
|
|
|
// register tlb_m_updRepIdx_rl
|
|
reg [5 : 0] tlb_m_updRepIdx_rl;
|
|
wire [5 : 0] tlb_m_updRepIdx_rl$D_IN;
|
|
wire tlb_m_updRepIdx_rl$EN;
|
|
|
|
// register tlb_m_validVec_0
|
|
reg tlb_m_validVec_0;
|
|
wire tlb_m_validVec_0$D_IN, tlb_m_validVec_0$EN;
|
|
|
|
// register tlb_m_validVec_1
|
|
reg tlb_m_validVec_1;
|
|
wire tlb_m_validVec_1$D_IN, tlb_m_validVec_1$EN;
|
|
|
|
// register tlb_m_validVec_10
|
|
reg tlb_m_validVec_10;
|
|
wire tlb_m_validVec_10$D_IN, tlb_m_validVec_10$EN;
|
|
|
|
// register tlb_m_validVec_11
|
|
reg tlb_m_validVec_11;
|
|
wire tlb_m_validVec_11$D_IN, tlb_m_validVec_11$EN;
|
|
|
|
// register tlb_m_validVec_12
|
|
reg tlb_m_validVec_12;
|
|
wire tlb_m_validVec_12$D_IN, tlb_m_validVec_12$EN;
|
|
|
|
// register tlb_m_validVec_13
|
|
reg tlb_m_validVec_13;
|
|
wire tlb_m_validVec_13$D_IN, tlb_m_validVec_13$EN;
|
|
|
|
// register tlb_m_validVec_14
|
|
reg tlb_m_validVec_14;
|
|
wire tlb_m_validVec_14$D_IN, tlb_m_validVec_14$EN;
|
|
|
|
// register tlb_m_validVec_15
|
|
reg tlb_m_validVec_15;
|
|
wire tlb_m_validVec_15$D_IN, tlb_m_validVec_15$EN;
|
|
|
|
// register tlb_m_validVec_16
|
|
reg tlb_m_validVec_16;
|
|
wire tlb_m_validVec_16$D_IN, tlb_m_validVec_16$EN;
|
|
|
|
// register tlb_m_validVec_17
|
|
reg tlb_m_validVec_17;
|
|
wire tlb_m_validVec_17$D_IN, tlb_m_validVec_17$EN;
|
|
|
|
// register tlb_m_validVec_18
|
|
reg tlb_m_validVec_18;
|
|
wire tlb_m_validVec_18$D_IN, tlb_m_validVec_18$EN;
|
|
|
|
// register tlb_m_validVec_19
|
|
reg tlb_m_validVec_19;
|
|
wire tlb_m_validVec_19$D_IN, tlb_m_validVec_19$EN;
|
|
|
|
// register tlb_m_validVec_2
|
|
reg tlb_m_validVec_2;
|
|
wire tlb_m_validVec_2$D_IN, tlb_m_validVec_2$EN;
|
|
|
|
// register tlb_m_validVec_20
|
|
reg tlb_m_validVec_20;
|
|
wire tlb_m_validVec_20$D_IN, tlb_m_validVec_20$EN;
|
|
|
|
// register tlb_m_validVec_21
|
|
reg tlb_m_validVec_21;
|
|
wire tlb_m_validVec_21$D_IN, tlb_m_validVec_21$EN;
|
|
|
|
// register tlb_m_validVec_22
|
|
reg tlb_m_validVec_22;
|
|
wire tlb_m_validVec_22$D_IN, tlb_m_validVec_22$EN;
|
|
|
|
// register tlb_m_validVec_23
|
|
reg tlb_m_validVec_23;
|
|
wire tlb_m_validVec_23$D_IN, tlb_m_validVec_23$EN;
|
|
|
|
// register tlb_m_validVec_24
|
|
reg tlb_m_validVec_24;
|
|
wire tlb_m_validVec_24$D_IN, tlb_m_validVec_24$EN;
|
|
|
|
// register tlb_m_validVec_25
|
|
reg tlb_m_validVec_25;
|
|
wire tlb_m_validVec_25$D_IN, tlb_m_validVec_25$EN;
|
|
|
|
// register tlb_m_validVec_26
|
|
reg tlb_m_validVec_26;
|
|
wire tlb_m_validVec_26$D_IN, tlb_m_validVec_26$EN;
|
|
|
|
// register tlb_m_validVec_27
|
|
reg tlb_m_validVec_27;
|
|
wire tlb_m_validVec_27$D_IN, tlb_m_validVec_27$EN;
|
|
|
|
// register tlb_m_validVec_28
|
|
reg tlb_m_validVec_28;
|
|
wire tlb_m_validVec_28$D_IN, tlb_m_validVec_28$EN;
|
|
|
|
// register tlb_m_validVec_29
|
|
reg tlb_m_validVec_29;
|
|
wire tlb_m_validVec_29$D_IN, tlb_m_validVec_29$EN;
|
|
|
|
// register tlb_m_validVec_3
|
|
reg tlb_m_validVec_3;
|
|
wire tlb_m_validVec_3$D_IN, tlb_m_validVec_3$EN;
|
|
|
|
// register tlb_m_validVec_30
|
|
reg tlb_m_validVec_30;
|
|
wire tlb_m_validVec_30$D_IN, tlb_m_validVec_30$EN;
|
|
|
|
// register tlb_m_validVec_31
|
|
reg tlb_m_validVec_31;
|
|
wire tlb_m_validVec_31$D_IN, tlb_m_validVec_31$EN;
|
|
|
|
// register tlb_m_validVec_4
|
|
reg tlb_m_validVec_4;
|
|
wire tlb_m_validVec_4$D_IN, tlb_m_validVec_4$EN;
|
|
|
|
// register tlb_m_validVec_5
|
|
reg tlb_m_validVec_5;
|
|
wire tlb_m_validVec_5$D_IN, tlb_m_validVec_5$EN;
|
|
|
|
// register tlb_m_validVec_6
|
|
reg tlb_m_validVec_6;
|
|
wire tlb_m_validVec_6$D_IN, tlb_m_validVec_6$EN;
|
|
|
|
// register tlb_m_validVec_7
|
|
reg tlb_m_validVec_7;
|
|
wire tlb_m_validVec_7$D_IN, tlb_m_validVec_7$EN;
|
|
|
|
// register tlb_m_validVec_8
|
|
reg tlb_m_validVec_8;
|
|
wire tlb_m_validVec_8$D_IN, tlb_m_validVec_8$EN;
|
|
|
|
// register tlb_m_validVec_9
|
|
reg tlb_m_validVec_9;
|
|
wire tlb_m_validVec_9$D_IN, tlb_m_validVec_9$EN;
|
|
|
|
// register vm_info
|
|
reg [48 : 0] vm_info;
|
|
wire [48 : 0] vm_info$D_IN;
|
|
wire vm_info$EN;
|
|
|
|
// register waitFlushP
|
|
reg waitFlushP;
|
|
wire waitFlushP$D_IN, waitFlushP$EN;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_doFinishFlush,
|
|
CAN_FIRE_RL_doRsFromP,
|
|
CAN_FIRE_RL_doStartFlush,
|
|
CAN_FIRE_RL_flushRqToPQ_canonicalize,
|
|
CAN_FIRE_RL_flushRqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_flushRqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_flushRqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_flushRsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_hitQ_canonicalize,
|
|
CAN_FIRE_RL_hitQ_clearReq_canon,
|
|
CAN_FIRE_RL_hitQ_deqReq_canon,
|
|
CAN_FIRE_RL_hitQ_enqReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_canonicalize,
|
|
CAN_FIRE_RL_perfReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_canonicalize,
|
|
CAN_FIRE_RL_rqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_rsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_set_no_pending,
|
|
CAN_FIRE_RL_tlb_m_doUpdateRep,
|
|
CAN_FIRE_RL_tlb_m_incRandIdx,
|
|
CAN_FIRE_RL_tlb_m_lruBit_canon,
|
|
CAN_FIRE_RL_tlb_m_updRepIdx_canon,
|
|
CAN_FIRE_flush,
|
|
CAN_FIRE_perf_req,
|
|
CAN_FIRE_perf_resp,
|
|
CAN_FIRE_perf_setStatus,
|
|
CAN_FIRE_toParent_flush_request_get,
|
|
CAN_FIRE_toParent_flush_response_put,
|
|
CAN_FIRE_toParent_rqToP_deq,
|
|
CAN_FIRE_toParent_rsFromP_enq,
|
|
CAN_FIRE_to_proc_request_put,
|
|
CAN_FIRE_to_proc_response_get,
|
|
CAN_FIRE_updateVMInfo,
|
|
WILL_FIRE_RL_doFinishFlush,
|
|
WILL_FIRE_RL_doRsFromP,
|
|
WILL_FIRE_RL_doStartFlush,
|
|
WILL_FIRE_RL_flushRqToPQ_canonicalize,
|
|
WILL_FIRE_RL_flushRqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_flushRqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_flushRqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_flushRsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_hitQ_canonicalize,
|
|
WILL_FIRE_RL_hitQ_clearReq_canon,
|
|
WILL_FIRE_RL_hitQ_deqReq_canon,
|
|
WILL_FIRE_RL_hitQ_enqReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_canonicalize,
|
|
WILL_FIRE_RL_perfReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_canonicalize,
|
|
WILL_FIRE_RL_rqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_rsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_set_no_pending,
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep,
|
|
WILL_FIRE_RL_tlb_m_incRandIdx,
|
|
WILL_FIRE_RL_tlb_m_lruBit_canon,
|
|
WILL_FIRE_RL_tlb_m_updRepIdx_canon,
|
|
WILL_FIRE_flush,
|
|
WILL_FIRE_perf_req,
|
|
WILL_FIRE_perf_resp,
|
|
WILL_FIRE_perf_setStatus,
|
|
WILL_FIRE_toParent_flush_request_get,
|
|
WILL_FIRE_toParent_flush_response_put,
|
|
WILL_FIRE_toParent_rqToP_deq,
|
|
WILL_FIRE_toParent_rsFromP_enq,
|
|
WILL_FIRE_to_proc_request_put,
|
|
WILL_FIRE_to_proc_response_get,
|
|
WILL_FIRE_updateVMInfo;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [70 : 0] MUX_hitQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_2;
|
|
wire [64 : 0] MUX_miss$write_1__VAL_1, MUX_miss$write_1__VAL_2;
|
|
wire [31 : 0] MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1;
|
|
wire [5 : 0] MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1,
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2;
|
|
wire MUX_hitQ_enqReq_lat_0$wset_1__SEL_1,
|
|
MUX_miss$write_1__SEL_1,
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1,
|
|
MUX_tlb_m_validVec_0$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_1$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_10$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_11$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_12$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_13$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_14$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_15$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_16$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_17$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_18$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_19$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_2$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_20$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_21$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_22$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_23$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_24$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_25$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_26$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_27$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_28$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_29$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_3$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_30$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_31$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_4$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_5$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_6$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_7$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_8$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_9$write_1__SEL_1,
|
|
MUX_waitFlushP$write_1__SEL_1;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] x__h74094;
|
|
reg [55 : 0] x__h64360, x__h73869;
|
|
reg [43 : 0] CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q4,
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556,
|
|
ppn__h73865;
|
|
reg [26 : 0] CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q3,
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q6,
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q15,
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q16,
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q17,
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q18,
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q19,
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q20,
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q21,
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q22,
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q23,
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q24,
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q5,
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q25,
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q26,
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q27,
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q28,
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q29,
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q30,
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q31,
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q32,
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q33,
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q34,
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q7,
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q35,
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q36,
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q8,
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q9,
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q10,
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q11,
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q12,
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q13,
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q14,
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640;
|
|
reg [4 : 0] CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_1_hit_ETC__q2;
|
|
reg [1 : 0] level__h32531, level__h69148;
|
|
reg CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q1,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q38,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q37,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q39,
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538,
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240,
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526,
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173,
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091,
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990;
|
|
wire [69 : 0] IF_vm_info_43_BIT_46_79_THEN_IF_SEL_ARR_tlb_m__ETC___d2264;
|
|
wire [63 : 0] x__h64352, x__h73861, x__h8655;
|
|
wire [31 : 0] INV_n__read5079__q40,
|
|
n__read__h45079,
|
|
upd__h45106,
|
|
val__h5317,
|
|
x__h5375;
|
|
wire [8 : 0] SEL_ARR_rsFromPQ_data_0_21_BIT_8_526_rsFromPQ__ETC___d1537;
|
|
wire [4 : 0] IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1960,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1962,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1964,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1966,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1968,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1970,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1972,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1974,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1976,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1978,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1980,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1982,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1984,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1986,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1988,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27,
|
|
IF_tlb_m_validVec_0_071_AND_tlb_m_validVec_1_0_ETC___d1328,
|
|
IF_tlb_m_validVec_0_071_AND_tlb_m_validVec_1_0_ETC___d1329,
|
|
IF_tlb_m_validVec_12_093_AND_tlb_m_validVec_13_ETC___d1318,
|
|
IF_tlb_m_validVec_16_102_AND_tlb_m_validVec_17_ETC___d1313,
|
|
IF_tlb_m_validVec_16_102_AND_tlb_m_validVec_17_ETC___d1314,
|
|
IF_tlb_m_validVec_20_109_AND_tlb_m_validVec_21_ETC___d1310,
|
|
IF_tlb_m_validVec_24_117_AND_tlb_m_validVec_25_ETC___d1306,
|
|
IF_tlb_m_validVec_24_117_AND_tlb_m_validVec_25_ETC___d1307,
|
|
IF_tlb_m_validVec_28_124_AND_tlb_m_validVec_29_ETC___d1303,
|
|
IF_tlb_m_validVec_4_078_AND_tlb_m_validVec_5_0_ETC___d1325,
|
|
IF_tlb_m_validVec_8_086_AND_tlb_m_validVec_9_0_ETC___d1321,
|
|
IF_tlb_m_validVec_8_086_AND_tlb_m_validVec_9_0_ETC___d1322,
|
|
addIdx__h49754,
|
|
addIdx__h54605,
|
|
idx__h69134,
|
|
v__h39526,
|
|
v__h44343,
|
|
v__h45871;
|
|
wire [3 : 0] SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d1535;
|
|
wire IF_IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_t_ETC___d2243,
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d125,
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d134,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d215,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d224,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d229,
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d316,
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d325,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1894,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1895,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1896,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1897,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1898,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1899,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1900,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1901,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1902,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1903,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1904,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1905,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1906,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1907,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1908,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1909,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1910,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1911,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1912,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1913,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1914,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1915,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1916,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1917,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1918,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1919,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1920,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1921,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1922,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1923,
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1924,
|
|
IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqReq__ETC___d101,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52,
|
|
IF_perfReqQ_enqReq_lat_1_whas__42_THEN_perfReq_ETC___d451,
|
|
IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_de_ETC___d191,
|
|
IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165,
|
|
IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFromP_ETC___d292,
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_NOT_rsF_ETC___d257,
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250,
|
|
IF_tlb_m_entryVec_10_76_BITS_1_TO_0_80_EQ_0_64_ETC___d1652,
|
|
IF_tlb_m_entryVec_11_88_BITS_1_TO_0_92_EQ_0_65_ETC___d1662,
|
|
IF_tlb_m_entryVec_12_00_BITS_1_TO_0_04_EQ_0_66_ETC___d1672,
|
|
IF_tlb_m_entryVec_13_12_BITS_1_TO_0_16_EQ_0_67_ETC___d1682,
|
|
IF_tlb_m_entryVec_14_24_BITS_1_TO_0_28_EQ_0_68_ETC___d1692,
|
|
IF_tlb_m_entryVec_15_36_BITS_1_TO_0_40_EQ_0_69_ETC___d1702,
|
|
IF_tlb_m_entryVec_16_48_BITS_1_TO_0_52_EQ_0_70_ETC___d1712,
|
|
IF_tlb_m_entryVec_17_60_BITS_1_TO_0_64_EQ_0_71_ETC___d1722,
|
|
IF_tlb_m_entryVec_18_72_BITS_1_TO_0_76_EQ_0_72_ETC___d1732,
|
|
IF_tlb_m_entryVec_19_84_BITS_1_TO_0_88_EQ_0_73_ETC___d1742,
|
|
IF_tlb_m_entryVec_1_68_BITS_1_TO_0_72_EQ_0_556_ETC___d1562,
|
|
IF_tlb_m_entryVec_20_96_BITS_1_TO_0_00_EQ_0_74_ETC___d1752,
|
|
IF_tlb_m_entryVec_21_08_BITS_1_TO_0_12_EQ_0_75_ETC___d1762,
|
|
IF_tlb_m_entryVec_22_20_BITS_1_TO_0_24_EQ_0_76_ETC___d1772,
|
|
IF_tlb_m_entryVec_23_32_BITS_1_TO_0_36_EQ_0_77_ETC___d1782,
|
|
IF_tlb_m_entryVec_24_44_BITS_1_TO_0_48_EQ_0_78_ETC___d1792,
|
|
IF_tlb_m_entryVec_25_56_BITS_1_TO_0_60_EQ_0_79_ETC___d1802,
|
|
IF_tlb_m_entryVec_26_68_BITS_1_TO_0_72_EQ_0_80_ETC___d1812,
|
|
IF_tlb_m_entryVec_27_80_BITS_1_TO_0_84_EQ_0_81_ETC___d1822,
|
|
IF_tlb_m_entryVec_28_92_BITS_1_TO_0_96_EQ_0_82_ETC___d1832,
|
|
IF_tlb_m_entryVec_29_004_BITS_1_TO_0_008_EQ_0__ETC___d1842,
|
|
IF_tlb_m_entryVec_2_80_BITS_1_TO_0_84_EQ_0_566_ETC___d1572,
|
|
IF_tlb_m_entryVec_30_016_BITS_1_TO_0_020_EQ_0__ETC___d1852,
|
|
IF_tlb_m_entryVec_31_028_BITS_1_TO_0_032_EQ_0__ETC___d1862,
|
|
IF_tlb_m_entryVec_3_92_BITS_1_TO_0_96_EQ_0_576_ETC___d1582,
|
|
IF_tlb_m_entryVec_4_04_BITS_1_TO_0_08_EQ_0_586_ETC___d1592,
|
|
IF_tlb_m_entryVec_5_16_BITS_1_TO_0_20_EQ_0_596_ETC___d1602,
|
|
IF_tlb_m_entryVec_6_28_BITS_1_TO_0_32_EQ_0_606_ETC___d1612,
|
|
IF_tlb_m_entryVec_7_40_BITS_1_TO_0_44_EQ_0_616_ETC___d1622,
|
|
IF_tlb_m_entryVec_8_52_BITS_1_TO_0_56_EQ_0_626_ETC___d1632,
|
|
IF_tlb_m_entryVec_9_64_BITS_1_TO_0_68_EQ_0_636_ETC___d1642,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17,
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609,
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991__ETC___d2247,
|
|
NOT_SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46__ETC___d582,
|
|
NOT_tlb_m_entryVec_0_52_BITS_79_TO_53_53_EQ_SE_ETC___d667,
|
|
NOT_tlb_m_entryVec_10_76_BITS_79_TO_53_77_EQ_S_ETC___d787,
|
|
NOT_tlb_m_entryVec_11_88_BITS_79_TO_53_89_EQ_S_ETC___d799,
|
|
NOT_tlb_m_entryVec_12_00_BITS_79_TO_53_01_EQ_S_ETC___d811,
|
|
NOT_tlb_m_entryVec_13_12_BITS_79_TO_53_13_EQ_S_ETC___d1057,
|
|
NOT_tlb_m_entryVec_13_12_BITS_79_TO_53_13_EQ_S_ETC___d823,
|
|
NOT_tlb_m_entryVec_14_24_BITS_79_TO_53_25_EQ_S_ETC___d835,
|
|
NOT_tlb_m_entryVec_15_36_BITS_79_TO_53_37_EQ_S_ETC___d847,
|
|
NOT_tlb_m_entryVec_16_48_BITS_79_TO_53_49_EQ_S_ETC___d859,
|
|
NOT_tlb_m_entryVec_17_60_BITS_79_TO_53_61_EQ_S_ETC___d871,
|
|
NOT_tlb_m_entryVec_18_72_BITS_79_TO_53_73_EQ_S_ETC___d883,
|
|
NOT_tlb_m_entryVec_19_84_BITS_79_TO_53_85_EQ_S_ETC___d1051,
|
|
NOT_tlb_m_entryVec_19_84_BITS_79_TO_53_85_EQ_S_ETC___d895,
|
|
NOT_tlb_m_entryVec_1_68_BITS_79_TO_53_69_EQ_SE_ETC___d1069,
|
|
NOT_tlb_m_entryVec_1_68_BITS_79_TO_53_69_EQ_SE_ETC___d679,
|
|
NOT_tlb_m_entryVec_20_96_BITS_79_TO_53_97_EQ_S_ETC___d907,
|
|
NOT_tlb_m_entryVec_21_08_BITS_79_TO_53_09_EQ_S_ETC___d919,
|
|
NOT_tlb_m_entryVec_22_20_BITS_79_TO_53_21_EQ_S_ETC___d931,
|
|
NOT_tlb_m_entryVec_23_32_BITS_79_TO_53_33_EQ_S_ETC___d943,
|
|
NOT_tlb_m_entryVec_24_44_BITS_79_TO_53_45_EQ_S_ETC___d955,
|
|
NOT_tlb_m_entryVec_25_56_BITS_79_TO_53_57_EQ_S_ETC___d1045,
|
|
NOT_tlb_m_entryVec_25_56_BITS_79_TO_53_57_EQ_S_ETC___d967,
|
|
NOT_tlb_m_entryVec_26_68_BITS_79_TO_53_69_EQ_S_ETC___d979,
|
|
NOT_tlb_m_entryVec_27_80_BITS_79_TO_53_81_EQ_S_ETC___d991,
|
|
NOT_tlb_m_entryVec_28_92_BITS_79_TO_53_93_EQ_S_ETC___d1003,
|
|
NOT_tlb_m_entryVec_29_004_BITS_79_TO_53_005_EQ_ETC___d1015,
|
|
NOT_tlb_m_entryVec_2_80_BITS_79_TO_53_81_EQ_SE_ETC___d691,
|
|
NOT_tlb_m_entryVec_30_016_BITS_79_TO_53_017_EQ_ETC___d1027,
|
|
NOT_tlb_m_entryVec_31_028_BITS_79_TO_53_029_EQ_ETC___d1039,
|
|
NOT_tlb_m_entryVec_3_92_BITS_79_TO_53_93_EQ_SE_ETC___d703,
|
|
NOT_tlb_m_entryVec_4_04_BITS_79_TO_53_05_EQ_SE_ETC___d715,
|
|
NOT_tlb_m_entryVec_5_16_BITS_79_TO_53_17_EQ_SE_ETC___d727,
|
|
NOT_tlb_m_entryVec_6_28_BITS_79_TO_53_29_EQ_SE_ETC___d739,
|
|
NOT_tlb_m_entryVec_7_40_BITS_79_TO_53_41_EQ_SE_ETC___d1063,
|
|
NOT_tlb_m_entryVec_7_40_BITS_79_TO_53_41_EQ_SE_ETC___d751,
|
|
NOT_tlb_m_entryVec_8_52_BITS_79_TO_53_53_EQ_SE_ETC___d763,
|
|
NOT_tlb_m_entryVec_9_64_BITS_79_TO_53_65_EQ_SE_ETC___d775,
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d589,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1555,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1575,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1595,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1615,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1635,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1655,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1675,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1695,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1715,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1735,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1755,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1775,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1795,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1815,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1835,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1855,
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_tlb_m_vali_ETC___d1252,
|
|
NOT_tlb_m_validVec_11_090_257_OR_NOT_tlb_m_ent_ETC___d1449,
|
|
NOT_tlb_m_validVec_13_094_261_OR_NOT_tlb_m_ent_ETC___d1447,
|
|
NOT_tlb_m_validVec_15_097_264_OR_NOT_tlb_m_ent_ETC___d1445,
|
|
NOT_tlb_m_validVec_16_102_269_OR_NOT_tlb_m_val_ETC___d1283,
|
|
NOT_tlb_m_validVec_17_103_270_OR_NOT_tlb_m_ent_ETC___d1443,
|
|
NOT_tlb_m_validVec_19_106_273_OR_NOT_tlb_m_ent_ETC___d1441,
|
|
NOT_tlb_m_validVec_1_072_239_OR_NOT_tlb_m_entr_ETC___d1459,
|
|
NOT_tlb_m_validVec_21_110_277_OR_NOT_tlb_m_ent_ETC___d1439,
|
|
NOT_tlb_m_validVec_23_113_280_OR_NOT_tlb_m_ent_ETC___d1437,
|
|
NOT_tlb_m_validVec_24_117_284_OR_NOT_tlb_m_val_ETC___d1298,
|
|
NOT_tlb_m_validVec_25_118_285_OR_NOT_tlb_m_ent_ETC___d1435,
|
|
NOT_tlb_m_validVec_27_121_288_OR_NOT_tlb_m_ent_ETC___d1433,
|
|
NOT_tlb_m_validVec_29_125_292_OR_NOT_tlb_m_ent_ETC___d1431,
|
|
NOT_tlb_m_validVec_3_075_242_OR_NOT_tlb_m_entr_ETC___d1457,
|
|
NOT_tlb_m_validVec_5_079_246_OR_NOT_tlb_m_entr_ETC___d1455,
|
|
NOT_tlb_m_validVec_7_082_249_OR_NOT_tlb_m_entr_ETC___d1453,
|
|
NOT_tlb_m_validVec_8_086_253_OR_NOT_tlb_m_vali_ETC___d1267,
|
|
NOT_tlb_m_validVec_9_087_254_OR_NOT_tlb_m_entr_ETC___d1451,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d587,
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46_rsFr_ETC___d604,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1236,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d635,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d650,
|
|
_theResult_____2__h12659,
|
|
_theResult_____2__h17274,
|
|
_theResult_____2__h9023,
|
|
next_deqP___1__h12848,
|
|
next_deqP___1__h17463,
|
|
next_deqP___1__h9212,
|
|
tlb_m_validVec_0_071_AND_tlb_m_validVec_1_072__ETC___d1085,
|
|
tlb_m_validVec_0_071_AND_tlb_m_validVec_1_072__ETC___d1234,
|
|
tlb_m_validVec_16_102_AND_tlb_m_validVec_17_10_ETC___d1116,
|
|
tlb_m_validVec_24_117_AND_tlb_m_validVec_25_11_ETC___d1131,
|
|
tlb_m_validVec_8_086_AND_tlb_m_validVec_9_087__ETC___d1100,
|
|
v__h12287,
|
|
v__h12438,
|
|
v__h16232,
|
|
v__h16383,
|
|
v__h8385,
|
|
v__h8536,
|
|
vm_info_43_BIT_46_79_AND_IF_NOT_tlb_m_validVec_ETC___d2267,
|
|
vm_info_43_BIT_46_79_AND_NOT_tlb_m_validVec_0__ETC___d2272;
|
|
|
|
// value method flush_done
|
|
assign flush_done = !needFlush ;
|
|
assign RDY_flush_done = 1'd1 ;
|
|
|
|
// action method flush
|
|
assign RDY_flush = !needFlush ;
|
|
assign CAN_FIRE_flush = !needFlush ;
|
|
assign WILL_FIRE_flush = EN_flush ;
|
|
|
|
// action method updateVMInfo
|
|
assign RDY_updateVMInfo = 1'd1 ;
|
|
assign CAN_FIRE_updateVMInfo = 1'd1 ;
|
|
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
|
|
|
|
// value method noPendingReq
|
|
assign noPendingReq = !miss[64] ;
|
|
assign RDY_noPendingReq = 1'd1 ;
|
|
|
|
// action method to_proc_request_put
|
|
assign RDY_to_proc_request_put =
|
|
!needFlush && !miss[64] && !hitQ_full && !rqToPQ_full &&
|
|
(!vm_info[46] ||
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d589) ;
|
|
assign CAN_FIRE_to_proc_request_put = RDY_to_proc_request_put ;
|
|
assign WILL_FIRE_to_proc_request_put = EN_to_proc_request_put ;
|
|
|
|
// actionvalue method to_proc_response_get
|
|
assign to_proc_response_get =
|
|
{ x__h74094,
|
|
!CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q1,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_1_hit_ETC__q2 } ;
|
|
assign RDY_to_proc_response_get = !hitQ_empty ;
|
|
assign CAN_FIRE_to_proc_response_get = !hitQ_empty ;
|
|
assign WILL_FIRE_to_proc_response_get = EN_to_proc_response_get ;
|
|
|
|
// value method toParent_rqToP_notEmpty
|
|
assign toParent_rqToP_notEmpty = !rqToPQ_empty ;
|
|
assign RDY_toParent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method toParent_rqToP_deq
|
|
assign RDY_toParent_rqToP_deq = !rqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_rqToP_deq = !rqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_rqToP_deq = EN_toParent_rqToP_deq ;
|
|
|
|
// value method toParent_rqToP_first
|
|
always@(rqToPQ_deqP or rqToPQ_data_0 or rqToPQ_data_1)
|
|
begin
|
|
case (rqToPQ_deqP)
|
|
1'd0: toParent_rqToP_first = rqToPQ_data_0;
|
|
1'd1: toParent_rqToP_first = rqToPQ_data_1;
|
|
endcase
|
|
end
|
|
assign RDY_toParent_rqToP_first = !rqToPQ_empty ;
|
|
|
|
// value method toParent_rsFromP_notFull
|
|
assign toParent_rsFromP_notFull = !rsFromPQ_full ;
|
|
assign RDY_toParent_rsFromP_notFull = 1'd1 ;
|
|
|
|
// action method toParent_rsFromP_enq
|
|
assign RDY_toParent_rsFromP_enq = !rsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_rsFromP_enq = !rsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_rsFromP_enq = EN_toParent_rsFromP_enq ;
|
|
|
|
// action method toParent_flush_request_get
|
|
assign RDY_toParent_flush_request_get = !flushRqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_flush_request_get = !flushRqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_flush_request_get =
|
|
EN_toParent_flush_request_get ;
|
|
|
|
// action method toParent_flush_response_put
|
|
assign RDY_toParent_flush_response_put = !flushRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_flush_response_put = !flushRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_flush_response_put =
|
|
EN_toParent_flush_response_put ;
|
|
|
|
// action method perf_setStatus
|
|
assign RDY_perf_setStatus = 1'd1 ;
|
|
assign CAN_FIRE_perf_setStatus = 1'd1 ;
|
|
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
|
|
|
|
// action method perf_req
|
|
assign RDY_perf_req = !perfReqQ_full ;
|
|
assign CAN_FIRE_perf_req = !perfReqQ_full ;
|
|
assign WILL_FIRE_perf_req = EN_perf_req ;
|
|
|
|
// actionvalue method perf_resp
|
|
assign perf_resp = { perfReqQ_data_0, 64'd0 } ;
|
|
assign RDY_perf_resp = !perfReqQ_empty ;
|
|
assign CAN_FIRE_perf_resp = !perfReqQ_empty ;
|
|
assign WILL_FIRE_perf_resp = EN_perf_resp ;
|
|
|
|
// value method perf_respValid
|
|
assign perf_respValid = !perfReqQ_empty ;
|
|
assign RDY_perf_respValid = 1'd1 ;
|
|
|
|
// rule RL_doStartFlush
|
|
assign CAN_FIRE_RL_doStartFlush =
|
|
!flushRqToPQ_full && needFlush && !waitFlushP && !miss[64] ;
|
|
assign WILL_FIRE_RL_doStartFlush = CAN_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doFinishFlush
|
|
assign CAN_FIRE_RL_doFinishFlush =
|
|
!flushRsFromPQ_empty && needFlush && waitFlushP && !miss[64] ;
|
|
assign WILL_FIRE_RL_doFinishFlush = CAN_FIRE_RL_doFinishFlush ;
|
|
|
|
// rule RL_set_no_pending
|
|
assign CAN_FIRE_RL_set_no_pending = 1'd1 ;
|
|
assign WILL_FIRE_RL_set_no_pending = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_doUpdateRep
|
|
assign CAN_FIRE_RL_tlb_m_doUpdateRep =
|
|
!CAN_FIRE_RL_doStartFlush && tlb_m_updRepIdx_rl[5] ;
|
|
assign WILL_FIRE_RL_tlb_m_doUpdateRep =
|
|
CAN_FIRE_RL_tlb_m_doUpdateRep && !WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doRsFromP
|
|
assign CAN_FIRE_RL_doRsFromP =
|
|
!hitQ_full && !rsFromPQ_empty &&
|
|
(!SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 ||
|
|
!SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 ||
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d587 ||
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d589) &&
|
|
miss[64] ;
|
|
assign WILL_FIRE_RL_doRsFromP = CAN_FIRE_RL_doRsFromP ;
|
|
|
|
// rule RL_tlb_m_incRandIdx
|
|
assign CAN_FIRE_RL_tlb_m_incRandIdx = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_incRandIdx = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_lruBit_canon
|
|
assign CAN_FIRE_RL_tlb_m_lruBit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_lruBit_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_updRepIdx_canon
|
|
assign CAN_FIRE_RL_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_canonicalize
|
|
assign CAN_FIRE_RL_hitQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_hitQ_enqReq_canon
|
|
assign CAN_FIRE_RL_hitQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_deqReq_canon
|
|
assign CAN_FIRE_RL_hitQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_clearReq_canon
|
|
assign CAN_FIRE_RL_hitQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_rqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_rsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_flushRqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_deqReq_canon
|
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assign CAN_FIRE_RL_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
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assign WILL_FIRE_RL_flushRsFromPQ_deqReq_canon = 1'd1 ;
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|
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// rule RL_flushRsFromPQ_clearReq_canon
|
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assign CAN_FIRE_RL_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
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assign WILL_FIRE_RL_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
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// rule RL_perfReqQ_canonicalize
|
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assign CAN_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
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assign WILL_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
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|
|
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// rule RL_perfReqQ_enqReq_canon
|
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assign CAN_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
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assign WILL_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
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|
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// rule RL_perfReqQ_deqReq_canon
|
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assign CAN_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
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assign WILL_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
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|
|
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// rule RL_perfReqQ_clearReq_canon
|
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assign CAN_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
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assign WILL_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
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|
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// inputs to muxes for submodule ports
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__SEL_1 =
|
|
EN_to_proc_request_put &&
|
|
(IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1924 ||
|
|
!vm_info[46]) ;
|
|
assign MUX_miss$write_1__SEL_1 =
|
|
EN_to_proc_request_put &&
|
|
vm_info_43_BIT_46_79_AND_NOT_tlb_m_validVec_0__ETC___d2272 ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 =
|
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WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
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SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
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assign MUX_tlb_m_validVec_0$write_1__SEL_1 =
|
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WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd0 &&
|
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SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
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assign MUX_tlb_m_validVec_1$write_1__SEL_1 =
|
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WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd1 &&
|
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SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
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SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
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assign MUX_tlb_m_validVec_10$write_1__SEL_1 =
|
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WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd10 &&
|
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SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
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SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
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assign MUX_tlb_m_validVec_11$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd11 &&
|
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SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
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|
assign MUX_tlb_m_validVec_12$write_1__SEL_1 =
|
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WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd12 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_13$write_1__SEL_1 =
|
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WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd13 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
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assign MUX_tlb_m_validVec_14$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd14 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
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|
assign MUX_tlb_m_validVec_15$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd15 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_16$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd16 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_17$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd17 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_18$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd18 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_19$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd19 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_2$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_20$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd20 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_21$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd21 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_22$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd22 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_23$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd23 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_24$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd24 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_25$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd25 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_26$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd26 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_27$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd27 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_28$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd28 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_29$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd29 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd3 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_30$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd30 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_31$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd31 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_4$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd4 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_5$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd5 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_6$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd6 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_7$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd7 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_8$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd8 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_tlb_m_validVec_9$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd9 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ;
|
|
assign MUX_waitFlushP$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doFinishFlush || EN_flush ;
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
IF_vm_info_43_BIT_46_79_THEN_IF_SEL_ARR_tlb_m__ETC___d2264 } ;
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 ?
|
|
((SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609) ?
|
|
{ x__h64352, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
{ 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
6'd44 }) :
|
|
{ 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
6'd44 } } ;
|
|
assign MUX_miss$write_1__VAL_1 = { 1'd1, to_proc_request_put } ;
|
|
assign MUX_miss$write_1__VAL_2 =
|
|
{ 1'd0,
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1 =
|
|
(val__h5317 == 32'hFFFFFFFF) ? x__h5375 : val__h5317 ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, v__h39526 } ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, idx__h69134 } ;
|
|
|
|
// inlined wires
|
|
assign tlb_m_lruBit_lat_0$whas =
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep || WILL_FIRE_RL_doStartFlush ;
|
|
assign tlb_m_updRepIdx_lat_0$wget =
|
|
{ 1'd0, 5'bxxxxx /* unspecified value */ } ;
|
|
assign tlb_m_updRepIdx_lat_0$whas =
|
|
WILL_FIRE_RL_doStartFlush || WILL_FIRE_RL_tlb_m_doUpdateRep ;
|
|
assign tlb_m_updRepIdx_lat_1$wget =
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 ?
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 :
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 ;
|
|
assign tlb_m_updRepIdx_lat_1$whas =
|
|
WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
EN_to_proc_request_put &&
|
|
vm_info_43_BIT_46_79_AND_IF_NOT_tlb_m_validVec_ETC___d2267 ;
|
|
assign hitQ_enqReq_lat_0$wget =
|
|
MUX_hitQ_enqReq_lat_0$wset_1__SEL_1 ?
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign hitQ_enqReq_lat_0$whas =
|
|
EN_to_proc_request_put &&
|
|
(IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1924 ||
|
|
!vm_info[46]) ||
|
|
WILL_FIRE_RL_doRsFromP ;
|
|
assign hitQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
70'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign rqToPQ_enqReq_lat_0$wget = { 1'd1, to_proc_request_put[38:12] } ;
|
|
assign rqToPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
27'bxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign rsFromPQ_enqReq_lat_0$wget = { 1'd1, toParent_rsFromP_enq_x } ;
|
|
assign rsFromPQ_enqReq_lat_2$wget =
|
|
{ 1'd0,
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ } ;
|
|
assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
assign perfReqQ_enqReq_lat_2$wget =
|
|
{ 1'd0, 3'bxxx /* unspecified value */ } ;
|
|
|
|
// register flushRqToPQ_clearReq_rl
|
|
assign flushRqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_deqReq_rl
|
|
assign flushRqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_empty
|
|
assign flushRqToPQ_empty$D_IN =
|
|
flushRqToPQ_clearReq_rl ||
|
|
!CAN_FIRE_RL_doStartFlush && !flushRqToPQ_enqReq_rl &&
|
|
(EN_toParent_flush_request_get || flushRqToPQ_deqReq_rl ||
|
|
flushRqToPQ_empty) ;
|
|
assign flushRqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_enqReq_rl
|
|
assign flushRqToPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_full
|
|
assign flushRqToPQ_full$D_IN =
|
|
!flushRqToPQ_clearReq_rl &&
|
|
(CAN_FIRE_RL_doStartFlush || flushRqToPQ_enqReq_rl ||
|
|
!EN_toParent_flush_request_get && !flushRqToPQ_deqReq_rl &&
|
|
flushRqToPQ_full) ;
|
|
assign flushRqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_clearReq_rl
|
|
assign flushRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_deqReq_rl
|
|
assign flushRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_empty
|
|
assign flushRsFromPQ_empty$D_IN =
|
|
flushRsFromPQ_clearReq_rl ||
|
|
!EN_toParent_flush_response_put && !flushRsFromPQ_enqReq_rl &&
|
|
(CAN_FIRE_RL_doFinishFlush || flushRsFromPQ_deqReq_rl ||
|
|
flushRsFromPQ_empty) ;
|
|
assign flushRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_enqReq_rl
|
|
assign flushRsFromPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_full
|
|
assign flushRsFromPQ_full$D_IN =
|
|
!flushRsFromPQ_clearReq_rl &&
|
|
(EN_toParent_flush_response_put || flushRsFromPQ_enqReq_rl ||
|
|
!CAN_FIRE_RL_doFinishFlush && !flushRsFromPQ_deqReq_rl &&
|
|
flushRsFromPQ_full) ;
|
|
assign flushRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register hitQ_clearReq_rl
|
|
assign hitQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign hitQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_data_0
|
|
assign hitQ_data_0$D_IN =
|
|
{ x__h8655,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 ||
|
|
(hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[5] :
|
|
hitQ_enqReq_rl[5]),
|
|
hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[4:0] :
|
|
hitQ_enqReq_rl[4:0] } ;
|
|
assign hitQ_data_0$EN =
|
|
hitQ_enqP == 1'd0 && !hitQ_clearReq_rl &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ;
|
|
|
|
// register hitQ_data_1
|
|
assign hitQ_data_1$D_IN = hitQ_data_0$D_IN ;
|
|
assign hitQ_data_1$EN =
|
|
hitQ_enqP == 1'd1 && !hitQ_clearReq_rl &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ;
|
|
|
|
// register hitQ_deqP
|
|
assign hitQ_deqP$D_IN = !hitQ_clearReq_rl && _theResult_____2__h9023 ;
|
|
assign hitQ_deqP$EN = 1'd1 ;
|
|
|
|
// register hitQ_deqReq_rl
|
|
assign hitQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign hitQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_empty
|
|
assign hitQ_empty$D_IN =
|
|
hitQ_clearReq_rl ||
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d125 &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 &&
|
|
(IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqReq__ETC___d101 ||
|
|
hitQ_empty) ;
|
|
assign hitQ_empty$EN = 1'd1 ;
|
|
|
|
// register hitQ_enqP
|
|
assign hitQ_enqP$D_IN = !hitQ_clearReq_rl && v__h8385 ;
|
|
assign hitQ_enqP$EN = 1'd1 ;
|
|
|
|
// register hitQ_enqReq_rl
|
|
assign hitQ_enqReq_rl$D_IN = hitQ_enqReq_lat_2$wget ;
|
|
assign hitQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_full
|
|
assign hitQ_full$D_IN =
|
|
!hitQ_clearReq_rl &&
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d134 ;
|
|
assign hitQ_full$EN = 1'd1 ;
|
|
|
|
// register miss
|
|
assign miss$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
MUX_miss$write_1__VAL_1 :
|
|
MUX_miss$write_1__VAL_2 ;
|
|
assign miss$EN =
|
|
EN_to_proc_request_put &&
|
|
vm_info_43_BIT_46_79_AND_NOT_tlb_m_validVec_0__ETC___d2272 ||
|
|
WILL_FIRE_RL_doRsFromP ;
|
|
|
|
// register needFlush
|
|
assign needFlush$D_IN = !WILL_FIRE_RL_doFinishFlush ;
|
|
assign needFlush$EN = MUX_waitFlushP$write_1__SEL_1 ;
|
|
|
|
// register perfReqQ_clearReq_rl
|
|
assign perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_data_0
|
|
assign perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[2:0] :
|
|
perfReqQ_enqReq_rl[2:0] ;
|
|
assign perfReqQ_data_0$EN =
|
|
!perfReqQ_clearReq_rl &&
|
|
IF_perfReqQ_enqReq_lat_1_whas__42_THEN_perfReq_ETC___d451 ;
|
|
|
|
// register perfReqQ_deqReq_rl
|
|
assign perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_empty
|
|
assign perfReqQ_empty$D_IN =
|
|
perfReqQ_clearReq_rl ||
|
|
(EN_perf_req ?
|
|
!perfReqQ_enqReq_lat_0$wget[3] :
|
|
!perfReqQ_enqReq_rl[3]) &&
|
|
(EN_perf_resp || perfReqQ_deqReq_rl || perfReqQ_empty) ;
|
|
assign perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_enqReq_rl
|
|
assign perfReqQ_enqReq_rl$D_IN = perfReqQ_enqReq_lat_2$wget ;
|
|
assign perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_full
|
|
assign perfReqQ_full$D_IN =
|
|
!perfReqQ_clearReq_rl &&
|
|
(IF_perfReqQ_enqReq_lat_1_whas__42_THEN_perfReq_ETC___d451 ||
|
|
!EN_perf_resp && !perfReqQ_deqReq_rl && perfReqQ_full) ;
|
|
assign perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_clearReq_rl
|
|
assign rqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign rqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_data_0
|
|
assign rqToPQ_data_0$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[26:0] :
|
|
rqToPQ_enqReq_rl[26:0] ;
|
|
assign rqToPQ_data_0$EN =
|
|
rqToPQ_enqP == 1'd0 && !rqToPQ_clearReq_rl &&
|
|
IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 ;
|
|
|
|
// register rqToPQ_data_1
|
|
assign rqToPQ_data_1$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[26:0] :
|
|
rqToPQ_enqReq_rl[26:0] ;
|
|
assign rqToPQ_data_1$EN =
|
|
rqToPQ_enqP == 1'd1 && !rqToPQ_clearReq_rl &&
|
|
IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 ;
|
|
|
|
// register rqToPQ_deqP
|
|
assign rqToPQ_deqP$D_IN = !rqToPQ_clearReq_rl && _theResult_____2__h12659 ;
|
|
assign rqToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_deqReq_rl
|
|
assign rqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign rqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_empty
|
|
assign rqToPQ_empty$D_IN =
|
|
rqToPQ_clearReq_rl ||
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d229 ;
|
|
assign rqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_enqP
|
|
assign rqToPQ_enqP$D_IN = !rqToPQ_clearReq_rl && v__h12287 ;
|
|
assign rqToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_enqReq_rl
|
|
assign rqToPQ_enqReq_rl$D_IN = rqToPQ_enqReq_lat_2$wget ;
|
|
assign rqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_full
|
|
assign rqToPQ_full$D_IN =
|
|
!rqToPQ_clearReq_rl &&
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d224 ;
|
|
assign rqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_clearReq_rl
|
|
assign rsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign rsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_data_0
|
|
assign rsFromPQ_data_0$D_IN =
|
|
{ IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_NOT_rsF_ETC___d257 ||
|
|
(EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[80] :
|
|
rsFromPQ_enqReq_rl[80]),
|
|
EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[79:0] :
|
|
rsFromPQ_enqReq_rl[79:0] } ;
|
|
assign rsFromPQ_data_0$EN =
|
|
rsFromPQ_enqP == 1'd0 && !rsFromPQ_clearReq_rl &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 ;
|
|
|
|
// register rsFromPQ_data_1
|
|
assign rsFromPQ_data_1$D_IN = rsFromPQ_data_0$D_IN ;
|
|
assign rsFromPQ_data_1$EN =
|
|
rsFromPQ_enqP == 1'd1 && !rsFromPQ_clearReq_rl &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 ;
|
|
|
|
// register rsFromPQ_deqP
|
|
assign rsFromPQ_deqP$D_IN =
|
|
!rsFromPQ_clearReq_rl && _theResult_____2__h17274 ;
|
|
assign rsFromPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_deqReq_rl
|
|
assign rsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign rsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_empty
|
|
assign rsFromPQ_empty$D_IN =
|
|
rsFromPQ_clearReq_rl ||
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d316 &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_NOT_rsF_ETC___d257 &&
|
|
(IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFromP_ETC___d292 ||
|
|
rsFromPQ_empty) ;
|
|
assign rsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_enqP
|
|
assign rsFromPQ_enqP$D_IN = !rsFromPQ_clearReq_rl && v__h16232 ;
|
|
assign rsFromPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_enqReq_rl
|
|
assign rsFromPQ_enqReq_rl$D_IN = rsFromPQ_enqReq_lat_2$wget ;
|
|
assign rsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_full
|
|
assign rsFromPQ_full$D_IN =
|
|
!rsFromPQ_clearReq_rl &&
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d325 ;
|
|
assign rsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register tlb_m_entryVec_0
|
|
assign tlb_m_entryVec_0$D_IN =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640,
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_8_526_rsFromPQ__ETC___d1537 } ;
|
|
assign tlb_m_entryVec_0$EN = MUX_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_1
|
|
assign tlb_m_entryVec_1$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_1$EN = MUX_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_10
|
|
assign tlb_m_entryVec_10$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_10$EN = MUX_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_11
|
|
assign tlb_m_entryVec_11$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_11$EN = MUX_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_12
|
|
assign tlb_m_entryVec_12$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_12$EN = MUX_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_13
|
|
assign tlb_m_entryVec_13$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_13$EN = MUX_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_14
|
|
assign tlb_m_entryVec_14$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_14$EN = MUX_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_15
|
|
assign tlb_m_entryVec_15$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_15$EN = MUX_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_16
|
|
assign tlb_m_entryVec_16$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_16$EN = MUX_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_17
|
|
assign tlb_m_entryVec_17$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_17$EN = MUX_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_18
|
|
assign tlb_m_entryVec_18$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_18$EN = MUX_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_19
|
|
assign tlb_m_entryVec_19$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_19$EN = MUX_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_2
|
|
assign tlb_m_entryVec_2$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_2$EN = MUX_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_20
|
|
assign tlb_m_entryVec_20$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_20$EN = MUX_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_21
|
|
assign tlb_m_entryVec_21$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_21$EN = MUX_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_22
|
|
assign tlb_m_entryVec_22$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_22$EN = MUX_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_23
|
|
assign tlb_m_entryVec_23$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_23$EN = MUX_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_24
|
|
assign tlb_m_entryVec_24$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_24$EN = MUX_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_25
|
|
assign tlb_m_entryVec_25$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_25$EN = MUX_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_26
|
|
assign tlb_m_entryVec_26$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_26$EN = MUX_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_27
|
|
assign tlb_m_entryVec_27$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_27$EN = MUX_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_28
|
|
assign tlb_m_entryVec_28$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_28$EN = MUX_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_29
|
|
assign tlb_m_entryVec_29$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_29$EN = MUX_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_3
|
|
assign tlb_m_entryVec_3$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_3$EN = MUX_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_30
|
|
assign tlb_m_entryVec_30$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_30$EN = MUX_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_31
|
|
assign tlb_m_entryVec_31$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_31$EN = MUX_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_4
|
|
assign tlb_m_entryVec_4$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_4$EN = MUX_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_5
|
|
assign tlb_m_entryVec_5$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_5$EN = MUX_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_6
|
|
assign tlb_m_entryVec_6$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_6$EN = MUX_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_7
|
|
assign tlb_m_entryVec_7$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_7$EN = MUX_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_8
|
|
assign tlb_m_entryVec_8$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_8$EN = MUX_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_9
|
|
assign tlb_m_entryVec_9$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_9$EN = MUX_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_lruBit_rl
|
|
assign tlb_m_lruBit_rl$D_IN = n__read__h45079 ;
|
|
assign tlb_m_lruBit_rl$EN = 1'd1 ;
|
|
|
|
// register tlb_m_randIdx
|
|
assign tlb_m_randIdx$D_IN = tlb_m_randIdx + 5'd1 ;
|
|
assign tlb_m_randIdx$EN = 1'd1 ;
|
|
|
|
// register tlb_m_updRepIdx_rl
|
|
assign tlb_m_updRepIdx_rl$D_IN =
|
|
{ IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27 } ;
|
|
assign tlb_m_updRepIdx_rl$EN = 1'd1 ;
|
|
|
|
// register tlb_m_validVec_0
|
|
assign tlb_m_validVec_0$D_IN = MUX_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_0$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd0 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_1
|
|
assign tlb_m_validVec_1$D_IN = MUX_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_1$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd1 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_10
|
|
assign tlb_m_validVec_10$D_IN = MUX_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_10$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd10 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_11
|
|
assign tlb_m_validVec_11$D_IN = MUX_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_11$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd11 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_12
|
|
assign tlb_m_validVec_12$D_IN = MUX_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_12$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd12 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_13
|
|
assign tlb_m_validVec_13$D_IN = MUX_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_13$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd13 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_14
|
|
assign tlb_m_validVec_14$D_IN = MUX_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_14$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd14 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_15
|
|
assign tlb_m_validVec_15$D_IN = MUX_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_15$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd15 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_16
|
|
assign tlb_m_validVec_16$D_IN = MUX_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_16$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd16 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_17
|
|
assign tlb_m_validVec_17$D_IN = MUX_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_17$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd17 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_18
|
|
assign tlb_m_validVec_18$D_IN = MUX_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_18$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd18 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_19
|
|
assign tlb_m_validVec_19$D_IN = MUX_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_19$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd19 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_2
|
|
assign tlb_m_validVec_2$D_IN = MUX_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_2$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_20
|
|
assign tlb_m_validVec_20$D_IN = MUX_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_20$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd20 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_21
|
|
assign tlb_m_validVec_21$D_IN = MUX_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_21$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd21 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_22
|
|
assign tlb_m_validVec_22$D_IN = MUX_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_22$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd22 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_23
|
|
assign tlb_m_validVec_23$D_IN = MUX_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_23$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd23 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_24
|
|
assign tlb_m_validVec_24$D_IN = MUX_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_24$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd24 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_25
|
|
assign tlb_m_validVec_25$D_IN = MUX_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_25$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd25 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_26
|
|
assign tlb_m_validVec_26$D_IN = MUX_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_26$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd26 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_27
|
|
assign tlb_m_validVec_27$D_IN = MUX_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_27$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd27 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_28
|
|
assign tlb_m_validVec_28$D_IN = MUX_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_28$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd28 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_29
|
|
assign tlb_m_validVec_29$D_IN = MUX_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_29$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd29 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_3
|
|
assign tlb_m_validVec_3$D_IN = MUX_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_3$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd3 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_30
|
|
assign tlb_m_validVec_30$D_IN = MUX_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_30$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd30 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_31
|
|
assign tlb_m_validVec_31$D_IN = MUX_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_31$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd31 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_4
|
|
assign tlb_m_validVec_4$D_IN = MUX_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_4$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd4 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_5
|
|
assign tlb_m_validVec_5$D_IN = MUX_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_5$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd5 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_6
|
|
assign tlb_m_validVec_6$D_IN = MUX_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_6$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd6 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_7
|
|
assign tlb_m_validVec_7$D_IN = MUX_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_7$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd7 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_8
|
|
assign tlb_m_validVec_8$D_IN = MUX_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_8$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd8 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_9
|
|
assign tlb_m_validVec_9$D_IN = MUX_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_9$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h39526 == 5'd9 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register vm_info
|
|
assign vm_info$D_IN = updateVMInfo_vm ;
|
|
assign vm_info$EN = EN_updateVMInfo ;
|
|
|
|
// register waitFlushP
|
|
assign waitFlushP$D_IN = !MUX_waitFlushP$write_1__SEL_1 ;
|
|
assign waitFlushP$EN =
|
|
WILL_FIRE_RL_doFinishFlush || EN_flush ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_t_ETC___d2243 =
|
|
(level__h69148 == 2'd0 ||
|
|
((level__h69148 == 2'd1) ?
|
|
ppn__h73865[8:0] == 9'd0 :
|
|
level__h69148 == 2'd2 && ppn__h73865[17:0] == 18'd0)) &&
|
|
(!SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 ||
|
|
!SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240) ;
|
|
assign IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d125 =
|
|
_theResult_____2__h9023 == v__h8385 ;
|
|
assign IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d134 =
|
|
IF_IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqR_ETC___d125 &&
|
|
(IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ||
|
|
!EN_to_proc_response_get && !hitQ_deqReq_rl && hitQ_full) ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d215 =
|
|
_theResult_____2__h12659 == v__h12287 ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d224 =
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d215 &&
|
|
(IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 ||
|
|
!EN_toParent_rqToP_deq && !rqToPQ_deqReq_rl && rqToPQ_full) ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d229 =
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_ETC___d215 &&
|
|
(MUX_miss$write_1__SEL_1 ?
|
|
!rqToPQ_enqReq_lat_0$wget[27] :
|
|
!rqToPQ_enqReq_rl[27]) &&
|
|
(IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_de_ETC___d191 ||
|
|
rqToPQ_empty) ;
|
|
assign IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d316 =
|
|
_theResult_____2__h17274 == v__h16232 ;
|
|
assign IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d325 =
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFr_ETC___d316 &&
|
|
(IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 ||
|
|
!CAN_FIRE_RL_doRsFromP && !rsFromPQ_deqReq_rl &&
|
|
rsFromPQ_full) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1894 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1555 ?
|
|
tlb_m_validVec_1 &&
|
|
IF_tlb_m_entryVec_1_68_BITS_1_TO_0_72_EQ_0_556_ETC___d1562 :
|
|
tlb_m_validVec_0 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1895 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1555 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_68_BITS_1_TO_0_72_EQ_0_556_ETC___d1562)) ?
|
|
tlb_m_validVec_2 &&
|
|
IF_tlb_m_entryVec_2_80_BITS_1_TO_0_84_EQ_0_566_ETC___d1572 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1894 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1896 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1575 ?
|
|
tlb_m_validVec_3 &&
|
|
IF_tlb_m_entryVec_3_92_BITS_1_TO_0_96_EQ_0_576_ETC___d1582 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1895 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1897 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1575 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_92_BITS_1_TO_0_96_EQ_0_576_ETC___d1582)) ?
|
|
tlb_m_validVec_4 &&
|
|
IF_tlb_m_entryVec_4_04_BITS_1_TO_0_08_EQ_0_586_ETC___d1592 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1896 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1898 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1595 ?
|
|
tlb_m_validVec_5 &&
|
|
IF_tlb_m_entryVec_5_16_BITS_1_TO_0_20_EQ_0_596_ETC___d1602 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1897 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1899 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1595 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_16_BITS_1_TO_0_20_EQ_0_596_ETC___d1602)) ?
|
|
tlb_m_validVec_6 &&
|
|
IF_tlb_m_entryVec_6_28_BITS_1_TO_0_32_EQ_0_606_ETC___d1612 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1898 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1900 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1615 ?
|
|
tlb_m_validVec_7 &&
|
|
IF_tlb_m_entryVec_7_40_BITS_1_TO_0_44_EQ_0_616_ETC___d1622 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1899 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1901 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1615 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_40_BITS_1_TO_0_44_EQ_0_616_ETC___d1622)) ?
|
|
tlb_m_validVec_8 &&
|
|
IF_tlb_m_entryVec_8_52_BITS_1_TO_0_56_EQ_0_626_ETC___d1632 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1900 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1902 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1635 ?
|
|
tlb_m_validVec_9 &&
|
|
IF_tlb_m_entryVec_9_64_BITS_1_TO_0_68_EQ_0_636_ETC___d1642 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1901 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1903 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1635 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_64_BITS_1_TO_0_68_EQ_0_636_ETC___d1642)) ?
|
|
tlb_m_validVec_10 &&
|
|
IF_tlb_m_entryVec_10_76_BITS_1_TO_0_80_EQ_0_64_ETC___d1652 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1902 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1904 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1655 ?
|
|
tlb_m_validVec_11 &&
|
|
IF_tlb_m_entryVec_11_88_BITS_1_TO_0_92_EQ_0_65_ETC___d1662 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1903 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1905 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1655 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_88_BITS_1_TO_0_92_EQ_0_65_ETC___d1662)) ?
|
|
tlb_m_validVec_12 &&
|
|
IF_tlb_m_entryVec_12_00_BITS_1_TO_0_04_EQ_0_66_ETC___d1672 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1904 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1906 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1675 ?
|
|
tlb_m_validVec_13 &&
|
|
IF_tlb_m_entryVec_13_12_BITS_1_TO_0_16_EQ_0_67_ETC___d1682 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1905 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1907 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1675 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_12_BITS_1_TO_0_16_EQ_0_67_ETC___d1682)) ?
|
|
tlb_m_validVec_14 &&
|
|
IF_tlb_m_entryVec_14_24_BITS_1_TO_0_28_EQ_0_68_ETC___d1692 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1906 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1908 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1695 ?
|
|
tlb_m_validVec_15 &&
|
|
IF_tlb_m_entryVec_15_36_BITS_1_TO_0_40_EQ_0_69_ETC___d1702 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1907 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1909 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1695 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_36_BITS_1_TO_0_40_EQ_0_69_ETC___d1702)) ?
|
|
tlb_m_validVec_16 &&
|
|
IF_tlb_m_entryVec_16_48_BITS_1_TO_0_52_EQ_0_70_ETC___d1712 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1908 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1910 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1715 ?
|
|
tlb_m_validVec_17 &&
|
|
IF_tlb_m_entryVec_17_60_BITS_1_TO_0_64_EQ_0_71_ETC___d1722 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1909 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1911 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1715 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_60_BITS_1_TO_0_64_EQ_0_71_ETC___d1722)) ?
|
|
tlb_m_validVec_18 &&
|
|
IF_tlb_m_entryVec_18_72_BITS_1_TO_0_76_EQ_0_72_ETC___d1732 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1910 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1912 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1735 ?
|
|
tlb_m_validVec_19 &&
|
|
IF_tlb_m_entryVec_19_84_BITS_1_TO_0_88_EQ_0_73_ETC___d1742 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1911 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1913 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1735 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_84_BITS_1_TO_0_88_EQ_0_73_ETC___d1742)) ?
|
|
tlb_m_validVec_20 &&
|
|
IF_tlb_m_entryVec_20_96_BITS_1_TO_0_00_EQ_0_74_ETC___d1752 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1912 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1914 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1755 ?
|
|
tlb_m_validVec_21 &&
|
|
IF_tlb_m_entryVec_21_08_BITS_1_TO_0_12_EQ_0_75_ETC___d1762 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1913 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1915 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1755 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_08_BITS_1_TO_0_12_EQ_0_75_ETC___d1762)) ?
|
|
tlb_m_validVec_22 &&
|
|
IF_tlb_m_entryVec_22_20_BITS_1_TO_0_24_EQ_0_76_ETC___d1772 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1914 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1916 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1775 ?
|
|
tlb_m_validVec_23 &&
|
|
IF_tlb_m_entryVec_23_32_BITS_1_TO_0_36_EQ_0_77_ETC___d1782 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1915 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1917 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1775 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_32_BITS_1_TO_0_36_EQ_0_77_ETC___d1782)) ?
|
|
tlb_m_validVec_24 &&
|
|
IF_tlb_m_entryVec_24_44_BITS_1_TO_0_48_EQ_0_78_ETC___d1792 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1916 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1918 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1795 ?
|
|
tlb_m_validVec_25 &&
|
|
IF_tlb_m_entryVec_25_56_BITS_1_TO_0_60_EQ_0_79_ETC___d1802 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1917 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1919 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1795 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_56_BITS_1_TO_0_60_EQ_0_79_ETC___d1802)) ?
|
|
tlb_m_validVec_26 &&
|
|
IF_tlb_m_entryVec_26_68_BITS_1_TO_0_72_EQ_0_80_ETC___d1812 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1918 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1920 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1815 ?
|
|
tlb_m_validVec_27 &&
|
|
IF_tlb_m_entryVec_27_80_BITS_1_TO_0_84_EQ_0_81_ETC___d1822 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1919 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1921 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1815 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_80_BITS_1_TO_0_84_EQ_0_81_ETC___d1822)) ?
|
|
tlb_m_validVec_28 &&
|
|
IF_tlb_m_entryVec_28_92_BITS_1_TO_0_96_EQ_0_82_ETC___d1832 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1920 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1922 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1835 ?
|
|
tlb_m_validVec_29 &&
|
|
IF_tlb_m_entryVec_29_004_BITS_1_TO_0_008_EQ_0__ETC___d1842 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1921 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1923 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1835 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_004_BITS_1_TO_0_008_EQ_0__ETC___d1842)) ?
|
|
tlb_m_validVec_30 &&
|
|
IF_tlb_m_entryVec_30_016_BITS_1_TO_0_020_EQ_0__ETC___d1852 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1922 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1924 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1855 ?
|
|
tlb_m_validVec_31 &&
|
|
IF_tlb_m_entryVec_31_028_BITS_1_TO_0_032_EQ_0__ETC___d1862 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1923 ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1960 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1555 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_68_BITS_1_TO_0_72_EQ_0_556_ETC___d1562)) ?
|
|
5'd2 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1555 ?
|
|
5'd1 :
|
|
5'd0) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1962 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1575 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_92_BITS_1_TO_0_96_EQ_0_576_ETC___d1582)) ?
|
|
5'd4 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1575 ?
|
|
5'd3 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1960) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1964 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1595 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_16_BITS_1_TO_0_20_EQ_0_596_ETC___d1602)) ?
|
|
5'd6 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1595 ?
|
|
5'd5 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1962) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1966 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1615 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_40_BITS_1_TO_0_44_EQ_0_616_ETC___d1622)) ?
|
|
5'd8 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1615 ?
|
|
5'd7 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1964) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1968 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1635 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_64_BITS_1_TO_0_68_EQ_0_636_ETC___d1642)) ?
|
|
5'd10 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1635 ?
|
|
5'd9 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1966) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1970 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1655 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_88_BITS_1_TO_0_92_EQ_0_65_ETC___d1662)) ?
|
|
5'd12 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1655 ?
|
|
5'd11 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1968) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1972 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1675 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_12_BITS_1_TO_0_16_EQ_0_67_ETC___d1682)) ?
|
|
5'd14 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1675 ?
|
|
5'd13 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1970) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1974 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1695 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_36_BITS_1_TO_0_40_EQ_0_69_ETC___d1702)) ?
|
|
5'd16 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1695 ?
|
|
5'd15 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1972) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1976 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1715 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_60_BITS_1_TO_0_64_EQ_0_71_ETC___d1722)) ?
|
|
5'd18 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1715 ?
|
|
5'd17 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1974) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1978 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1735 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_84_BITS_1_TO_0_88_EQ_0_73_ETC___d1742)) ?
|
|
5'd20 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1735 ?
|
|
5'd19 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1976) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1980 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1755 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_08_BITS_1_TO_0_12_EQ_0_75_ETC___d1762)) ?
|
|
5'd22 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1755 ?
|
|
5'd21 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1978) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1982 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1775 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_32_BITS_1_TO_0_36_EQ_0_77_ETC___d1782)) ?
|
|
5'd24 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1775 ?
|
|
5'd23 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1980) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1984 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1795 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_56_BITS_1_TO_0_60_EQ_0_79_ETC___d1802)) ?
|
|
5'd26 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1795 ?
|
|
5'd25 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1982) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1986 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1815 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_80_BITS_1_TO_0_84_EQ_0_81_ETC___d1822)) ?
|
|
5'd28 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1815 ?
|
|
5'd27 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1984) ;
|
|
assign IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1988 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1835 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_004_BITS_1_TO_0_008_EQ_0__ETC___d1842)) ?
|
|
5'd30 :
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1835 ?
|
|
5'd29 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1986) ;
|
|
assign IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqReq__ETC___d101 =
|
|
EN_to_proc_response_get || hitQ_deqReq_rl ;
|
|
assign IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
!hitQ_enqReq_lat_0$wget[70] :
|
|
!hitQ_enqReq_rl[70] ;
|
|
assign IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[70] :
|
|
hitQ_enqReq_rl[70] ;
|
|
assign IF_perfReqQ_enqReq_lat_1_whas__42_THEN_perfReq_ETC___d451 =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[3] :
|
|
perfReqQ_enqReq_rl[3] ;
|
|
assign IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_de_ETC___d191 =
|
|
EN_toParent_rqToP_deq || rqToPQ_deqReq_rl ;
|
|
assign IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[27] :
|
|
rqToPQ_enqReq_rl[27] ;
|
|
assign IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFromP_ETC___d292 =
|
|
CAN_FIRE_RL_doRsFromP || rsFromPQ_deqReq_rl ;
|
|
assign IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_NOT_rsF_ETC___d257 =
|
|
EN_toParent_rsFromP_enq ?
|
|
!rsFromPQ_enqReq_lat_0$wget[81] :
|
|
!rsFromPQ_enqReq_rl[81] ;
|
|
assign IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 =
|
|
EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[81] :
|
|
rsFromPQ_enqReq_rl[81] ;
|
|
assign IF_tlb_m_entryVec_10_76_BITS_1_TO_0_80_EQ_0_64_ETC___d1652 =
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q15 ==
|
|
tlb_m_entryVec_10[79:53] ;
|
|
assign IF_tlb_m_entryVec_11_88_BITS_1_TO_0_92_EQ_0_65_ETC___d1662 =
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q16 ==
|
|
tlb_m_entryVec_11[79:53] ;
|
|
assign IF_tlb_m_entryVec_12_00_BITS_1_TO_0_04_EQ_0_66_ETC___d1672 =
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q17 ==
|
|
tlb_m_entryVec_12[79:53] ;
|
|
assign IF_tlb_m_entryVec_13_12_BITS_1_TO_0_16_EQ_0_67_ETC___d1682 =
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q18 ==
|
|
tlb_m_entryVec_13[79:53] ;
|
|
assign IF_tlb_m_entryVec_14_24_BITS_1_TO_0_28_EQ_0_68_ETC___d1692 =
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q19 ==
|
|
tlb_m_entryVec_14[79:53] ;
|
|
assign IF_tlb_m_entryVec_15_36_BITS_1_TO_0_40_EQ_0_69_ETC___d1702 =
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q20 ==
|
|
tlb_m_entryVec_15[79:53] ;
|
|
assign IF_tlb_m_entryVec_16_48_BITS_1_TO_0_52_EQ_0_70_ETC___d1712 =
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q21 ==
|
|
tlb_m_entryVec_16[79:53] ;
|
|
assign IF_tlb_m_entryVec_17_60_BITS_1_TO_0_64_EQ_0_71_ETC___d1722 =
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q22 ==
|
|
tlb_m_entryVec_17[79:53] ;
|
|
assign IF_tlb_m_entryVec_18_72_BITS_1_TO_0_76_EQ_0_72_ETC___d1732 =
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q23 ==
|
|
tlb_m_entryVec_18[79:53] ;
|
|
assign IF_tlb_m_entryVec_19_84_BITS_1_TO_0_88_EQ_0_73_ETC___d1742 =
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q24 ==
|
|
tlb_m_entryVec_19[79:53] ;
|
|
assign IF_tlb_m_entryVec_1_68_BITS_1_TO_0_72_EQ_0_556_ETC___d1562 =
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q5 ==
|
|
tlb_m_entryVec_1[79:53] ;
|
|
assign IF_tlb_m_entryVec_20_96_BITS_1_TO_0_00_EQ_0_74_ETC___d1752 =
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q25 ==
|
|
tlb_m_entryVec_20[79:53] ;
|
|
assign IF_tlb_m_entryVec_21_08_BITS_1_TO_0_12_EQ_0_75_ETC___d1762 =
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q26 ==
|
|
tlb_m_entryVec_21[79:53] ;
|
|
assign IF_tlb_m_entryVec_22_20_BITS_1_TO_0_24_EQ_0_76_ETC___d1772 =
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q27 ==
|
|
tlb_m_entryVec_22[79:53] ;
|
|
assign IF_tlb_m_entryVec_23_32_BITS_1_TO_0_36_EQ_0_77_ETC___d1782 =
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q28 ==
|
|
tlb_m_entryVec_23[79:53] ;
|
|
assign IF_tlb_m_entryVec_24_44_BITS_1_TO_0_48_EQ_0_78_ETC___d1792 =
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q29 ==
|
|
tlb_m_entryVec_24[79:53] ;
|
|
assign IF_tlb_m_entryVec_25_56_BITS_1_TO_0_60_EQ_0_79_ETC___d1802 =
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q30 ==
|
|
tlb_m_entryVec_25[79:53] ;
|
|
assign IF_tlb_m_entryVec_26_68_BITS_1_TO_0_72_EQ_0_80_ETC___d1812 =
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q31 ==
|
|
tlb_m_entryVec_26[79:53] ;
|
|
assign IF_tlb_m_entryVec_27_80_BITS_1_TO_0_84_EQ_0_81_ETC___d1822 =
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q32 ==
|
|
tlb_m_entryVec_27[79:53] ;
|
|
assign IF_tlb_m_entryVec_28_92_BITS_1_TO_0_96_EQ_0_82_ETC___d1832 =
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q33 ==
|
|
tlb_m_entryVec_28[79:53] ;
|
|
assign IF_tlb_m_entryVec_29_004_BITS_1_TO_0_008_EQ_0__ETC___d1842 =
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q34 ==
|
|
tlb_m_entryVec_29[79:53] ;
|
|
assign IF_tlb_m_entryVec_2_80_BITS_1_TO_0_84_EQ_0_566_ETC___d1572 =
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q7 ==
|
|
tlb_m_entryVec_2[79:53] ;
|
|
assign IF_tlb_m_entryVec_30_016_BITS_1_TO_0_020_EQ_0__ETC___d1852 =
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q35 ==
|
|
tlb_m_entryVec_30[79:53] ;
|
|
assign IF_tlb_m_entryVec_31_028_BITS_1_TO_0_032_EQ_0__ETC___d1862 =
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q36 ==
|
|
tlb_m_entryVec_31[79:53] ;
|
|
assign IF_tlb_m_entryVec_3_92_BITS_1_TO_0_96_EQ_0_576_ETC___d1582 =
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q8 ==
|
|
tlb_m_entryVec_3[79:53] ;
|
|
assign IF_tlb_m_entryVec_4_04_BITS_1_TO_0_08_EQ_0_586_ETC___d1592 =
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q9 ==
|
|
tlb_m_entryVec_4[79:53] ;
|
|
assign IF_tlb_m_entryVec_5_16_BITS_1_TO_0_20_EQ_0_596_ETC___d1602 =
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q10 ==
|
|
tlb_m_entryVec_5[79:53] ;
|
|
assign IF_tlb_m_entryVec_6_28_BITS_1_TO_0_32_EQ_0_606_ETC___d1612 =
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q11 ==
|
|
tlb_m_entryVec_6[79:53] ;
|
|
assign IF_tlb_m_entryVec_7_40_BITS_1_TO_0_44_EQ_0_616_ETC___d1622 =
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q12 ==
|
|
tlb_m_entryVec_7[79:53] ;
|
|
assign IF_tlb_m_entryVec_8_52_BITS_1_TO_0_56_EQ_0_626_ETC___d1632 =
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q13 ==
|
|
tlb_m_entryVec_8[79:53] ;
|
|
assign IF_tlb_m_entryVec_9_64_BITS_1_TO_0_68_EQ_0_636_ETC___d1642 =
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q14 ==
|
|
tlb_m_entryVec_9[79:53] ;
|
|
assign IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17 =
|
|
tlb_m_updRepIdx_lat_1$whas ?
|
|
tlb_m_updRepIdx_lat_1$wget[5] :
|
|
(tlb_m_updRepIdx_lat_0$whas ?
|
|
tlb_m_updRepIdx_lat_0$wget[5] :
|
|
tlb_m_updRepIdx_rl[5]) ;
|
|
assign IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27 =
|
|
tlb_m_updRepIdx_lat_1$whas ?
|
|
tlb_m_updRepIdx_lat_1$wget[4:0] :
|
|
(tlb_m_updRepIdx_lat_0$whas ?
|
|
tlb_m_updRepIdx_lat_0$wget[4:0] :
|
|
tlb_m_updRepIdx_rl[4:0]) ;
|
|
assign IF_tlb_m_validVec_0_071_AND_tlb_m_validVec_1_0_ETC___d1328 =
|
|
(tlb_m_validVec_0 && tlb_m_validVec_1) ?
|
|
(tlb_m_validVec_2 ? 5'd3 : 5'd2) :
|
|
(tlb_m_validVec_0 ? 5'd1 : 5'd0) ;
|
|
assign IF_tlb_m_validVec_0_071_AND_tlb_m_validVec_1_0_ETC___d1329 =
|
|
(tlb_m_validVec_0 && tlb_m_validVec_1 && tlb_m_validVec_2 &&
|
|
tlb_m_validVec_3) ?
|
|
IF_tlb_m_validVec_4_078_AND_tlb_m_validVec_5_0_ETC___d1325 :
|
|
IF_tlb_m_validVec_0_071_AND_tlb_m_validVec_1_0_ETC___d1328 ;
|
|
assign IF_tlb_m_validVec_12_093_AND_tlb_m_validVec_13_ETC___d1318 =
|
|
(tlb_m_validVec_12 && tlb_m_validVec_13) ?
|
|
(tlb_m_validVec_14 ? 5'd15 : 5'd14) :
|
|
(tlb_m_validVec_12 ? 5'd13 : 5'd12) ;
|
|
assign IF_tlb_m_validVec_16_102_AND_tlb_m_validVec_17_ETC___d1313 =
|
|
(tlb_m_validVec_16 && tlb_m_validVec_17) ?
|
|
(tlb_m_validVec_18 ? 5'd19 : 5'd18) :
|
|
(tlb_m_validVec_16 ? 5'd17 : 5'd16) ;
|
|
assign IF_tlb_m_validVec_16_102_AND_tlb_m_validVec_17_ETC___d1314 =
|
|
(tlb_m_validVec_16 && tlb_m_validVec_17 && tlb_m_validVec_18 &&
|
|
tlb_m_validVec_19) ?
|
|
IF_tlb_m_validVec_20_109_AND_tlb_m_validVec_21_ETC___d1310 :
|
|
IF_tlb_m_validVec_16_102_AND_tlb_m_validVec_17_ETC___d1313 ;
|
|
assign IF_tlb_m_validVec_20_109_AND_tlb_m_validVec_21_ETC___d1310 =
|
|
(tlb_m_validVec_20 && tlb_m_validVec_21) ?
|
|
(tlb_m_validVec_22 ? 5'd23 : 5'd22) :
|
|
(tlb_m_validVec_20 ? 5'd21 : 5'd20) ;
|
|
assign IF_tlb_m_validVec_24_117_AND_tlb_m_validVec_25_ETC___d1306 =
|
|
(tlb_m_validVec_24 && tlb_m_validVec_25) ?
|
|
(tlb_m_validVec_26 ? 5'd27 : 5'd26) :
|
|
(tlb_m_validVec_24 ? 5'd25 : 5'd24) ;
|
|
assign IF_tlb_m_validVec_24_117_AND_tlb_m_validVec_25_ETC___d1307 =
|
|
(tlb_m_validVec_24 && tlb_m_validVec_25 && tlb_m_validVec_26 &&
|
|
tlb_m_validVec_27) ?
|
|
IF_tlb_m_validVec_28_124_AND_tlb_m_validVec_29_ETC___d1303 :
|
|
IF_tlb_m_validVec_24_117_AND_tlb_m_validVec_25_ETC___d1306 ;
|
|
assign IF_tlb_m_validVec_28_124_AND_tlb_m_validVec_29_ETC___d1303 =
|
|
(tlb_m_validVec_28 && tlb_m_validVec_29) ?
|
|
(tlb_m_validVec_30 ? 5'd31 : 5'd30) :
|
|
(tlb_m_validVec_28 ? 5'd29 : 5'd28) ;
|
|
assign IF_tlb_m_validVec_4_078_AND_tlb_m_validVec_5_0_ETC___d1325 =
|
|
(tlb_m_validVec_4 && tlb_m_validVec_5) ?
|
|
(tlb_m_validVec_6 ? 5'd7 : 5'd6) :
|
|
(tlb_m_validVec_4 ? 5'd5 : 5'd4) ;
|
|
assign IF_tlb_m_validVec_8_086_AND_tlb_m_validVec_9_0_ETC___d1321 =
|
|
(tlb_m_validVec_8 && tlb_m_validVec_9) ?
|
|
(tlb_m_validVec_10 ? 5'd11 : 5'd10) :
|
|
(tlb_m_validVec_8 ? 5'd9 : 5'd8) ;
|
|
assign IF_tlb_m_validVec_8_086_AND_tlb_m_validVec_9_0_ETC___d1322 =
|
|
(tlb_m_validVec_8 && tlb_m_validVec_9 && tlb_m_validVec_10 &&
|
|
tlb_m_validVec_11) ?
|
|
IF_tlb_m_validVec_12_093_AND_tlb_m_validVec_13_ETC___d1318 :
|
|
IF_tlb_m_validVec_8_086_AND_tlb_m_validVec_9_0_ETC___d1321 ;
|
|
assign IF_vm_info_43_BIT_46_79_THEN_IF_SEL_ARR_tlb_m__ETC___d2264 =
|
|
vm_info[46] ?
|
|
((SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 &&
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991__ETC___d2247) ?
|
|
{ x__h73861, 1'd0, 5'bxxxxx /* unspecified value */ } :
|
|
{ 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
6'd44 }) :
|
|
{ to_proc_request_put,
|
|
1'd0,
|
|
5'bxxxxx /* unspecified value */ } ;
|
|
assign INV_n__read5079__q40 = ~n__read__h45079 ;
|
|
assign NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609 =
|
|
!SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538 &&
|
|
(SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542 ?
|
|
vm_info[48:47] != 2'd1 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46_rsFr_ETC___d604 :
|
|
vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46_rsFr_ETC___d604) ;
|
|
assign NOT_SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991__ETC___d2247 =
|
|
!SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 &&
|
|
(SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 ?
|
|
vm_info[48:47] != 2'd1 &&
|
|
IF_IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_t_ETC___d2243 :
|
|
vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_t_ETC___d2243) ;
|
|
assign NOT_SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46__ETC___d582 =
|
|
level__h32531 != 2'd0 &&
|
|
((level__h32531 == 2'd1) ?
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[8:0] !=
|
|
9'd0 :
|
|
level__h32531 != 2'd2 ||
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571 &&
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577 ||
|
|
!vm_info[46] ;
|
|
assign NOT_tlb_m_entryVec_0_52_BITS_79_TO_53_53_EQ_SE_ETC___d667 =
|
|
tlb_m_entryVec_0[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_0[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_0[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_10_76_BITS_79_TO_53_77_EQ_S_ETC___d787 =
|
|
tlb_m_entryVec_10[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_10[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_10[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_11_88_BITS_79_TO_53_89_EQ_S_ETC___d799 =
|
|
tlb_m_entryVec_11[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_11[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_11[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_12_00_BITS_79_TO_53_01_EQ_S_ETC___d811 =
|
|
tlb_m_entryVec_12[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_12[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_12[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_13_12_BITS_79_TO_53_13_EQ_S_ETC___d1057 =
|
|
NOT_tlb_m_entryVec_13_12_BITS_79_TO_53_13_EQ_S_ETC___d823 &&
|
|
NOT_tlb_m_entryVec_14_24_BITS_79_TO_53_25_EQ_S_ETC___d835 &&
|
|
NOT_tlb_m_entryVec_15_36_BITS_79_TO_53_37_EQ_S_ETC___d847 &&
|
|
NOT_tlb_m_entryVec_16_48_BITS_79_TO_53_49_EQ_S_ETC___d859 &&
|
|
NOT_tlb_m_entryVec_17_60_BITS_79_TO_53_61_EQ_S_ETC___d871 &&
|
|
NOT_tlb_m_entryVec_18_72_BITS_79_TO_53_73_EQ_S_ETC___d883 &&
|
|
NOT_tlb_m_entryVec_19_84_BITS_79_TO_53_85_EQ_S_ETC___d1051 ;
|
|
assign NOT_tlb_m_entryVec_13_12_BITS_79_TO_53_13_EQ_S_ETC___d823 =
|
|
tlb_m_entryVec_13[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_13[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_13[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_14_24_BITS_79_TO_53_25_EQ_S_ETC___d835 =
|
|
tlb_m_entryVec_14[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_14[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_14[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_15_36_BITS_79_TO_53_37_EQ_S_ETC___d847 =
|
|
tlb_m_entryVec_15[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_15[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_15[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_16_48_BITS_79_TO_53_49_EQ_S_ETC___d859 =
|
|
tlb_m_entryVec_16[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_16[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_16[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_17_60_BITS_79_TO_53_61_EQ_S_ETC___d871 =
|
|
tlb_m_entryVec_17[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_17[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_17[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_18_72_BITS_79_TO_53_73_EQ_S_ETC___d883 =
|
|
tlb_m_entryVec_18[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_18[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_18[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_19_84_BITS_79_TO_53_85_EQ_S_ETC___d1051 =
|
|
NOT_tlb_m_entryVec_19_84_BITS_79_TO_53_85_EQ_S_ETC___d895 &&
|
|
NOT_tlb_m_entryVec_20_96_BITS_79_TO_53_97_EQ_S_ETC___d907 &&
|
|
NOT_tlb_m_entryVec_21_08_BITS_79_TO_53_09_EQ_S_ETC___d919 &&
|
|
NOT_tlb_m_entryVec_22_20_BITS_79_TO_53_21_EQ_S_ETC___d931 &&
|
|
NOT_tlb_m_entryVec_23_32_BITS_79_TO_53_33_EQ_S_ETC___d943 &&
|
|
NOT_tlb_m_entryVec_24_44_BITS_79_TO_53_45_EQ_S_ETC___d955 &&
|
|
NOT_tlb_m_entryVec_25_56_BITS_79_TO_53_57_EQ_S_ETC___d1045 ;
|
|
assign NOT_tlb_m_entryVec_19_84_BITS_79_TO_53_85_EQ_S_ETC___d895 =
|
|
tlb_m_entryVec_19[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_19[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_19[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_1_68_BITS_79_TO_53_69_EQ_SE_ETC___d1069 =
|
|
NOT_tlb_m_entryVec_1_68_BITS_79_TO_53_69_EQ_SE_ETC___d679 &&
|
|
NOT_tlb_m_entryVec_2_80_BITS_79_TO_53_81_EQ_SE_ETC___d691 &&
|
|
NOT_tlb_m_entryVec_3_92_BITS_79_TO_53_93_EQ_SE_ETC___d703 &&
|
|
NOT_tlb_m_entryVec_4_04_BITS_79_TO_53_05_EQ_SE_ETC___d715 &&
|
|
NOT_tlb_m_entryVec_5_16_BITS_79_TO_53_17_EQ_SE_ETC___d727 &&
|
|
NOT_tlb_m_entryVec_6_28_BITS_79_TO_53_29_EQ_SE_ETC___d739 &&
|
|
NOT_tlb_m_entryVec_7_40_BITS_79_TO_53_41_EQ_SE_ETC___d1063 ;
|
|
assign NOT_tlb_m_entryVec_1_68_BITS_79_TO_53_69_EQ_SE_ETC___d679 =
|
|
tlb_m_entryVec_1[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_1[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_1[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_20_96_BITS_79_TO_53_97_EQ_S_ETC___d907 =
|
|
tlb_m_entryVec_20[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_20[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_20[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_21_08_BITS_79_TO_53_09_EQ_S_ETC___d919 =
|
|
tlb_m_entryVec_21[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_21[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_21[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_22_20_BITS_79_TO_53_21_EQ_S_ETC___d931 =
|
|
tlb_m_entryVec_22[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_22[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_22[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_23_32_BITS_79_TO_53_33_EQ_S_ETC___d943 =
|
|
tlb_m_entryVec_23[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_23[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_23[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_24_44_BITS_79_TO_53_45_EQ_S_ETC___d955 =
|
|
tlb_m_entryVec_24[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_24[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_24[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_25_56_BITS_79_TO_53_57_EQ_S_ETC___d1045 =
|
|
NOT_tlb_m_entryVec_25_56_BITS_79_TO_53_57_EQ_S_ETC___d967 &&
|
|
NOT_tlb_m_entryVec_26_68_BITS_79_TO_53_69_EQ_S_ETC___d979 &&
|
|
NOT_tlb_m_entryVec_27_80_BITS_79_TO_53_81_EQ_S_ETC___d991 &&
|
|
NOT_tlb_m_entryVec_28_92_BITS_79_TO_53_93_EQ_S_ETC___d1003 &&
|
|
NOT_tlb_m_entryVec_29_004_BITS_79_TO_53_005_EQ_ETC___d1015 &&
|
|
NOT_tlb_m_entryVec_30_016_BITS_79_TO_53_017_EQ_ETC___d1027 &&
|
|
NOT_tlb_m_entryVec_31_028_BITS_79_TO_53_029_EQ_ETC___d1039 ;
|
|
assign NOT_tlb_m_entryVec_25_56_BITS_79_TO_53_57_EQ_S_ETC___d967 =
|
|
tlb_m_entryVec_25[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_25[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_25[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_26_68_BITS_79_TO_53_69_EQ_S_ETC___d979 =
|
|
tlb_m_entryVec_26[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_26[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_26[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_27_80_BITS_79_TO_53_81_EQ_S_ETC___d991 =
|
|
tlb_m_entryVec_27[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_27[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_27[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_28_92_BITS_79_TO_53_93_EQ_S_ETC___d1003 =
|
|
tlb_m_entryVec_28[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_28[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_28[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_29_004_BITS_79_TO_53_005_EQ_ETC___d1015 =
|
|
tlb_m_entryVec_29[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_29[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_29[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_2_80_BITS_79_TO_53_81_EQ_SE_ETC___d691 =
|
|
tlb_m_entryVec_2[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_2[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_2[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_30_016_BITS_79_TO_53_017_EQ_ETC___d1027 =
|
|
tlb_m_entryVec_30[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_30[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_30[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_31_028_BITS_79_TO_53_029_EQ_ETC___d1039 =
|
|
tlb_m_entryVec_31[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_31[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_31[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_3_92_BITS_79_TO_53_93_EQ_SE_ETC___d703 =
|
|
tlb_m_entryVec_3[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_3[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_3[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_4_04_BITS_79_TO_53_05_EQ_SE_ETC___d715 =
|
|
tlb_m_entryVec_4[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_4[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_4[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_5_16_BITS_79_TO_53_17_EQ_SE_ETC___d727 =
|
|
tlb_m_entryVec_5[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_5[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_5[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_6_28_BITS_79_TO_53_29_EQ_SE_ETC___d739 =
|
|
tlb_m_entryVec_6[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_6[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_6[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_7_40_BITS_79_TO_53_41_EQ_SE_ETC___d1063 =
|
|
NOT_tlb_m_entryVec_7_40_BITS_79_TO_53_41_EQ_SE_ETC___d751 &&
|
|
NOT_tlb_m_entryVec_8_52_BITS_79_TO_53_53_EQ_SE_ETC___d763 &&
|
|
NOT_tlb_m_entryVec_9_64_BITS_79_TO_53_65_EQ_SE_ETC___d775 &&
|
|
NOT_tlb_m_entryVec_10_76_BITS_79_TO_53_77_EQ_S_ETC___d787 &&
|
|
NOT_tlb_m_entryVec_11_88_BITS_79_TO_53_89_EQ_S_ETC___d799 &&
|
|
NOT_tlb_m_entryVec_12_00_BITS_79_TO_53_01_EQ_S_ETC___d811 &&
|
|
NOT_tlb_m_entryVec_13_12_BITS_79_TO_53_13_EQ_S_ETC___d1057 ;
|
|
assign NOT_tlb_m_entryVec_7_40_BITS_79_TO_53_41_EQ_SE_ETC___d751 =
|
|
tlb_m_entryVec_7[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_7[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_7[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_8_52_BITS_79_TO_53_53_EQ_SE_ETC___d763 =
|
|
tlb_m_entryVec_8[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_8[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_8[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_entryVec_9_64_BITS_79_TO_53_65_EQ_SE_ETC___d775 =
|
|
tlb_m_entryVec_9[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 ||
|
|
tlb_m_entryVec_9[1:0] != level__h32531 ||
|
|
tlb_m_entryVec_9[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 ;
|
|
assign NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d589 =
|
|
!CAN_FIRE_RL_doStartFlush &&
|
|
(tlb_m_updRepIdx_lat_0$whas ?
|
|
!tlb_m_updRepIdx_lat_0$wget[5] :
|
|
!tlb_m_updRepIdx_rl[5]) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1555 =
|
|
!tlb_m_validVec_0 ||
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q6 !=
|
|
tlb_m_entryVec_0[79:53] ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1575 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1555 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_68_BITS_1_TO_0_72_EQ_0_556_ETC___d1562) &&
|
|
(!tlb_m_validVec_2 ||
|
|
!IF_tlb_m_entryVec_2_80_BITS_1_TO_0_84_EQ_0_566_ETC___d1572) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1595 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1575 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_92_BITS_1_TO_0_96_EQ_0_576_ETC___d1582) &&
|
|
(!tlb_m_validVec_4 ||
|
|
!IF_tlb_m_entryVec_4_04_BITS_1_TO_0_08_EQ_0_586_ETC___d1592) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1615 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1595 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_16_BITS_1_TO_0_20_EQ_0_596_ETC___d1602) &&
|
|
(!tlb_m_validVec_6 ||
|
|
!IF_tlb_m_entryVec_6_28_BITS_1_TO_0_32_EQ_0_606_ETC___d1612) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1635 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1615 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_40_BITS_1_TO_0_44_EQ_0_616_ETC___d1622) &&
|
|
(!tlb_m_validVec_8 ||
|
|
!IF_tlb_m_entryVec_8_52_BITS_1_TO_0_56_EQ_0_626_ETC___d1632) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1655 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1635 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_64_BITS_1_TO_0_68_EQ_0_636_ETC___d1642) &&
|
|
(!tlb_m_validVec_10 ||
|
|
!IF_tlb_m_entryVec_10_76_BITS_1_TO_0_80_EQ_0_64_ETC___d1652) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1675 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1655 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_88_BITS_1_TO_0_92_EQ_0_65_ETC___d1662) &&
|
|
(!tlb_m_validVec_12 ||
|
|
!IF_tlb_m_entryVec_12_00_BITS_1_TO_0_04_EQ_0_66_ETC___d1672) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1695 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1675 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_12_BITS_1_TO_0_16_EQ_0_67_ETC___d1682) &&
|
|
(!tlb_m_validVec_14 ||
|
|
!IF_tlb_m_entryVec_14_24_BITS_1_TO_0_28_EQ_0_68_ETC___d1692) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1715 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1695 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_36_BITS_1_TO_0_40_EQ_0_69_ETC___d1702) &&
|
|
(!tlb_m_validVec_16 ||
|
|
!IF_tlb_m_entryVec_16_48_BITS_1_TO_0_52_EQ_0_70_ETC___d1712) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1735 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1715 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_60_BITS_1_TO_0_64_EQ_0_71_ETC___d1722) &&
|
|
(!tlb_m_validVec_18 ||
|
|
!IF_tlb_m_entryVec_18_72_BITS_1_TO_0_76_EQ_0_72_ETC___d1732) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1755 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1735 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_84_BITS_1_TO_0_88_EQ_0_73_ETC___d1742) &&
|
|
(!tlb_m_validVec_20 ||
|
|
!IF_tlb_m_entryVec_20_96_BITS_1_TO_0_00_EQ_0_74_ETC___d1752) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1775 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1755 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_08_BITS_1_TO_0_12_EQ_0_75_ETC___d1762) &&
|
|
(!tlb_m_validVec_22 ||
|
|
!IF_tlb_m_entryVec_22_20_BITS_1_TO_0_24_EQ_0_76_ETC___d1772) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1795 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1775 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_32_BITS_1_TO_0_36_EQ_0_77_ETC___d1782) &&
|
|
(!tlb_m_validVec_24 ||
|
|
!IF_tlb_m_entryVec_24_44_BITS_1_TO_0_48_EQ_0_78_ETC___d1792) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1815 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1795 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_56_BITS_1_TO_0_60_EQ_0_79_ETC___d1802) &&
|
|
(!tlb_m_validVec_26 ||
|
|
!IF_tlb_m_entryVec_26_68_BITS_1_TO_0_72_EQ_0_80_ETC___d1812) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1835 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1815 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_80_BITS_1_TO_0_84_EQ_0_81_ETC___d1822) &&
|
|
(!tlb_m_validVec_28 ||
|
|
!IF_tlb_m_entryVec_28_92_BITS_1_TO_0_96_EQ_0_82_ETC___d1832) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1855 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1835 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_004_BITS_1_TO_0_008_EQ_0__ETC___d1842) &&
|
|
(!tlb_m_validVec_30 ||
|
|
!IF_tlb_m_entryVec_30_016_BITS_1_TO_0_020_EQ_0__ETC___d1852) ;
|
|
assign NOT_tlb_m_validVec_0_071_238_OR_NOT_tlb_m_vali_ETC___d1252 =
|
|
!tlb_m_validVec_0 || !tlb_m_validVec_1 || !tlb_m_validVec_2 ||
|
|
!tlb_m_validVec_3 ||
|
|
!tlb_m_validVec_4 ||
|
|
!tlb_m_validVec_5 ||
|
|
!tlb_m_validVec_6 ||
|
|
!tlb_m_validVec_7 ;
|
|
assign NOT_tlb_m_validVec_11_090_257_OR_NOT_tlb_m_ent_ETC___d1449 =
|
|
(!tlb_m_validVec_11 ||
|
|
NOT_tlb_m_entryVec_11_88_BITS_79_TO_53_89_EQ_S_ETC___d799) &&
|
|
(!tlb_m_validVec_12 ||
|
|
NOT_tlb_m_entryVec_12_00_BITS_79_TO_53_01_EQ_S_ETC___d811) &&
|
|
NOT_tlb_m_validVec_13_094_261_OR_NOT_tlb_m_ent_ETC___d1447 ;
|
|
assign NOT_tlb_m_validVec_13_094_261_OR_NOT_tlb_m_ent_ETC___d1447 =
|
|
(!tlb_m_validVec_13 ||
|
|
NOT_tlb_m_entryVec_13_12_BITS_79_TO_53_13_EQ_S_ETC___d823) &&
|
|
(!tlb_m_validVec_14 ||
|
|
NOT_tlb_m_entryVec_14_24_BITS_79_TO_53_25_EQ_S_ETC___d835) &&
|
|
NOT_tlb_m_validVec_15_097_264_OR_NOT_tlb_m_ent_ETC___d1445 ;
|
|
assign NOT_tlb_m_validVec_15_097_264_OR_NOT_tlb_m_ent_ETC___d1445 =
|
|
(!tlb_m_validVec_15 ||
|
|
NOT_tlb_m_entryVec_15_36_BITS_79_TO_53_37_EQ_S_ETC___d847) &&
|
|
(!tlb_m_validVec_16 ||
|
|
NOT_tlb_m_entryVec_16_48_BITS_79_TO_53_49_EQ_S_ETC___d859) &&
|
|
NOT_tlb_m_validVec_17_103_270_OR_NOT_tlb_m_ent_ETC___d1443 ;
|
|
assign NOT_tlb_m_validVec_16_102_269_OR_NOT_tlb_m_val_ETC___d1283 =
|
|
!tlb_m_validVec_16 || !tlb_m_validVec_17 || !tlb_m_validVec_18 ||
|
|
!tlb_m_validVec_19 ||
|
|
!tlb_m_validVec_20 ||
|
|
!tlb_m_validVec_21 ||
|
|
!tlb_m_validVec_22 ||
|
|
!tlb_m_validVec_23 ;
|
|
assign NOT_tlb_m_validVec_17_103_270_OR_NOT_tlb_m_ent_ETC___d1443 =
|
|
(!tlb_m_validVec_17 ||
|
|
NOT_tlb_m_entryVec_17_60_BITS_79_TO_53_61_EQ_S_ETC___d871) &&
|
|
(!tlb_m_validVec_18 ||
|
|
NOT_tlb_m_entryVec_18_72_BITS_79_TO_53_73_EQ_S_ETC___d883) &&
|
|
NOT_tlb_m_validVec_19_106_273_OR_NOT_tlb_m_ent_ETC___d1441 ;
|
|
assign NOT_tlb_m_validVec_19_106_273_OR_NOT_tlb_m_ent_ETC___d1441 =
|
|
(!tlb_m_validVec_19 ||
|
|
NOT_tlb_m_entryVec_19_84_BITS_79_TO_53_85_EQ_S_ETC___d895) &&
|
|
(!tlb_m_validVec_20 ||
|
|
NOT_tlb_m_entryVec_20_96_BITS_79_TO_53_97_EQ_S_ETC___d907) &&
|
|
NOT_tlb_m_validVec_21_110_277_OR_NOT_tlb_m_ent_ETC___d1439 ;
|
|
assign NOT_tlb_m_validVec_1_072_239_OR_NOT_tlb_m_entr_ETC___d1459 =
|
|
(!tlb_m_validVec_1 ||
|
|
NOT_tlb_m_entryVec_1_68_BITS_79_TO_53_69_EQ_SE_ETC___d679) &&
|
|
(!tlb_m_validVec_2 ||
|
|
NOT_tlb_m_entryVec_2_80_BITS_79_TO_53_81_EQ_SE_ETC___d691) &&
|
|
NOT_tlb_m_validVec_3_075_242_OR_NOT_tlb_m_entr_ETC___d1457 ;
|
|
assign NOT_tlb_m_validVec_21_110_277_OR_NOT_tlb_m_ent_ETC___d1439 =
|
|
(!tlb_m_validVec_21 ||
|
|
NOT_tlb_m_entryVec_21_08_BITS_79_TO_53_09_EQ_S_ETC___d919) &&
|
|
(!tlb_m_validVec_22 ||
|
|
NOT_tlb_m_entryVec_22_20_BITS_79_TO_53_21_EQ_S_ETC___d931) &&
|
|
NOT_tlb_m_validVec_23_113_280_OR_NOT_tlb_m_ent_ETC___d1437 ;
|
|
assign NOT_tlb_m_validVec_23_113_280_OR_NOT_tlb_m_ent_ETC___d1437 =
|
|
(!tlb_m_validVec_23 ||
|
|
NOT_tlb_m_entryVec_23_32_BITS_79_TO_53_33_EQ_S_ETC___d943) &&
|
|
(!tlb_m_validVec_24 ||
|
|
NOT_tlb_m_entryVec_24_44_BITS_79_TO_53_45_EQ_S_ETC___d955) &&
|
|
NOT_tlb_m_validVec_25_118_285_OR_NOT_tlb_m_ent_ETC___d1435 ;
|
|
assign NOT_tlb_m_validVec_24_117_284_OR_NOT_tlb_m_val_ETC___d1298 =
|
|
!tlb_m_validVec_24 || !tlb_m_validVec_25 || !tlb_m_validVec_26 ||
|
|
!tlb_m_validVec_27 ||
|
|
!tlb_m_validVec_28 ||
|
|
!tlb_m_validVec_29 ||
|
|
!tlb_m_validVec_30 ||
|
|
!tlb_m_validVec_31 ;
|
|
assign NOT_tlb_m_validVec_25_118_285_OR_NOT_tlb_m_ent_ETC___d1435 =
|
|
(!tlb_m_validVec_25 ||
|
|
NOT_tlb_m_entryVec_25_56_BITS_79_TO_53_57_EQ_S_ETC___d967) &&
|
|
(!tlb_m_validVec_26 ||
|
|
NOT_tlb_m_entryVec_26_68_BITS_79_TO_53_69_EQ_S_ETC___d979) &&
|
|
NOT_tlb_m_validVec_27_121_288_OR_NOT_tlb_m_ent_ETC___d1433 ;
|
|
assign NOT_tlb_m_validVec_27_121_288_OR_NOT_tlb_m_ent_ETC___d1433 =
|
|
(!tlb_m_validVec_27 ||
|
|
NOT_tlb_m_entryVec_27_80_BITS_79_TO_53_81_EQ_S_ETC___d991) &&
|
|
(!tlb_m_validVec_28 ||
|
|
NOT_tlb_m_entryVec_28_92_BITS_79_TO_53_93_EQ_S_ETC___d1003) &&
|
|
NOT_tlb_m_validVec_29_125_292_OR_NOT_tlb_m_ent_ETC___d1431 ;
|
|
assign NOT_tlb_m_validVec_29_125_292_OR_NOT_tlb_m_ent_ETC___d1431 =
|
|
(!tlb_m_validVec_29 ||
|
|
NOT_tlb_m_entryVec_29_004_BITS_79_TO_53_005_EQ_ETC___d1015) &&
|
|
(!tlb_m_validVec_30 ||
|
|
NOT_tlb_m_entryVec_30_016_BITS_79_TO_53_017_EQ_ETC___d1027) &&
|
|
(!tlb_m_validVec_31 ||
|
|
NOT_tlb_m_entryVec_31_028_BITS_79_TO_53_029_EQ_ETC___d1039) ;
|
|
assign NOT_tlb_m_validVec_3_075_242_OR_NOT_tlb_m_entr_ETC___d1457 =
|
|
(!tlb_m_validVec_3 ||
|
|
NOT_tlb_m_entryVec_3_92_BITS_79_TO_53_93_EQ_SE_ETC___d703) &&
|
|
(!tlb_m_validVec_4 ||
|
|
NOT_tlb_m_entryVec_4_04_BITS_79_TO_53_05_EQ_SE_ETC___d715) &&
|
|
NOT_tlb_m_validVec_5_079_246_OR_NOT_tlb_m_entr_ETC___d1455 ;
|
|
assign NOT_tlb_m_validVec_5_079_246_OR_NOT_tlb_m_entr_ETC___d1455 =
|
|
(!tlb_m_validVec_5 ||
|
|
NOT_tlb_m_entryVec_5_16_BITS_79_TO_53_17_EQ_SE_ETC___d727) &&
|
|
(!tlb_m_validVec_6 ||
|
|
NOT_tlb_m_entryVec_6_28_BITS_79_TO_53_29_EQ_SE_ETC___d739) &&
|
|
NOT_tlb_m_validVec_7_082_249_OR_NOT_tlb_m_entr_ETC___d1453 ;
|
|
assign NOT_tlb_m_validVec_7_082_249_OR_NOT_tlb_m_entr_ETC___d1453 =
|
|
(!tlb_m_validVec_7 ||
|
|
NOT_tlb_m_entryVec_7_40_BITS_79_TO_53_41_EQ_SE_ETC___d751) &&
|
|
(!tlb_m_validVec_8 ||
|
|
NOT_tlb_m_entryVec_8_52_BITS_79_TO_53_53_EQ_SE_ETC___d763) &&
|
|
NOT_tlb_m_validVec_9_087_254_OR_NOT_tlb_m_entr_ETC___d1451 ;
|
|
assign NOT_tlb_m_validVec_8_086_253_OR_NOT_tlb_m_vali_ETC___d1267 =
|
|
!tlb_m_validVec_8 || !tlb_m_validVec_9 || !tlb_m_validVec_10 ||
|
|
!tlb_m_validVec_11 ||
|
|
!tlb_m_validVec_12 ||
|
|
!tlb_m_validVec_13 ||
|
|
!tlb_m_validVec_14 ||
|
|
!tlb_m_validVec_15 ;
|
|
assign NOT_tlb_m_validVec_9_087_254_OR_NOT_tlb_m_entr_ETC___d1451 =
|
|
(!tlb_m_validVec_9 ||
|
|
NOT_tlb_m_entryVec_9_64_BITS_79_TO_53_65_EQ_SE_ETC___d775) &&
|
|
(!tlb_m_validVec_10 ||
|
|
NOT_tlb_m_entryVec_10_76_BITS_79_TO_53_77_EQ_S_ETC___d787) &&
|
|
NOT_tlb_m_validVec_11_090_257_OR_NOT_tlb_m_ent_ETC___d1449 ;
|
|
assign SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d587 =
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538 ||
|
|
(SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542 ?
|
|
vm_info[48:47] == 2'd1 ||
|
|
NOT_SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46__ETC___d582 :
|
|
vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46__ETC___d582) ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BITS_1_TO_0_46_rsFr_ETC___d604 =
|
|
(level__h32531 == 2'd0 ||
|
|
((level__h32531 == 2'd1) ?
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[8:0] ==
|
|
9'd0 :
|
|
level__h32531 == 2'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[17:0] ==
|
|
18'd0)) &&
|
|
(!SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571 ||
|
|
!SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577) &&
|
|
vm_info[46] ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d1535 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q37,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q38 } ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1236 =
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609 &&
|
|
NOT_tlb_m_entryVec_0_52_BITS_79_TO_53_53_EQ_SE_ETC___d667 &&
|
|
NOT_tlb_m_entryVec_1_68_BITS_79_TO_53_69_EQ_SE_ETC___d1069 &&
|
|
tlb_m_validVec_0_071_AND_tlb_m_validVec_1_072__ETC___d1234 ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1461 =
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609 &&
|
|
(!tlb_m_validVec_0 ||
|
|
NOT_tlb_m_entryVec_0_52_BITS_79_TO_53_53_EQ_SE_ETC___d667) &&
|
|
NOT_tlb_m_validVec_1_072_239_OR_NOT_tlb_m_entr_ETC___d1459 ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d635 =
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556 !=
|
|
CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q4 ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d650 =
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_ETC___d609 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 !=
|
|
CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q3 ;
|
|
assign SEL_ARR_rsFromPQ_data_0_21_BIT_8_526_rsFromPQ__ETC___d1537 =
|
|
{ CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q39,
|
|
1'd1,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664,
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d1535,
|
|
level__h32531 } ;
|
|
assign _theResult_____2__h12659 =
|
|
IF_rqToPQ_deqReq_lat_1_whas__85_THEN_rqToPQ_de_ETC___d191 ?
|
|
next_deqP___1__h12848 :
|
|
rqToPQ_deqP ;
|
|
assign _theResult_____2__h17274 =
|
|
IF_rsFromPQ_deqReq_lat_1_whas__86_THEN_rsFromP_ETC___d292 ?
|
|
next_deqP___1__h17463 :
|
|
rsFromPQ_deqP ;
|
|
assign _theResult_____2__h9023 =
|
|
IF_hitQ_deqReq_lat_1_whas__5_THEN_hitQ_deqReq__ETC___d101 ?
|
|
next_deqP___1__h9212 :
|
|
hitQ_deqP ;
|
|
assign addIdx__h49754 =
|
|
(!INV_n__read5079__q40[0] && !INV_n__read5079__q40[1] &&
|
|
!INV_n__read5079__q40[2] &&
|
|
!INV_n__read5079__q40[3] &&
|
|
!INV_n__read5079__q40[4] &&
|
|
!INV_n__read5079__q40[5] &&
|
|
!INV_n__read5079__q40[6] &&
|
|
!INV_n__read5079__q40[7] &&
|
|
!INV_n__read5079__q40[8] &&
|
|
!INV_n__read5079__q40[9] &&
|
|
!INV_n__read5079__q40[10] &&
|
|
!INV_n__read5079__q40[11] &&
|
|
!INV_n__read5079__q40[12] &&
|
|
!INV_n__read5079__q40[13] &&
|
|
!INV_n__read5079__q40[14] &&
|
|
!INV_n__read5079__q40[15]) ?
|
|
((!INV_n__read5079__q40[16] && !INV_n__read5079__q40[17] &&
|
|
!INV_n__read5079__q40[18] &&
|
|
!INV_n__read5079__q40[19] &&
|
|
!INV_n__read5079__q40[20] &&
|
|
!INV_n__read5079__q40[21] &&
|
|
!INV_n__read5079__q40[22] &&
|
|
!INV_n__read5079__q40[23]) ?
|
|
((!INV_n__read5079__q40[24] && !INV_n__read5079__q40[25] &&
|
|
!INV_n__read5079__q40[26] &&
|
|
!INV_n__read5079__q40[27]) ?
|
|
((!INV_n__read5079__q40[28] &&
|
|
!INV_n__read5079__q40[29]) ?
|
|
(INV_n__read5079__q40[30] ? 5'd30 : 5'd31) :
|
|
(INV_n__read5079__q40[28] ? 5'd28 : 5'd29)) :
|
|
((!INV_n__read5079__q40[24] &&
|
|
!INV_n__read5079__q40[25]) ?
|
|
(INV_n__read5079__q40[26] ? 5'd26 : 5'd27) :
|
|
(INV_n__read5079__q40[24] ? 5'd24 : 5'd25))) :
|
|
((!INV_n__read5079__q40[16] && !INV_n__read5079__q40[17] &&
|
|
!INV_n__read5079__q40[18] &&
|
|
!INV_n__read5079__q40[19]) ?
|
|
((!INV_n__read5079__q40[20] &&
|
|
!INV_n__read5079__q40[21]) ?
|
|
(INV_n__read5079__q40[22] ? 5'd22 : 5'd23) :
|
|
(INV_n__read5079__q40[20] ? 5'd20 : 5'd21)) :
|
|
((!INV_n__read5079__q40[16] &&
|
|
!INV_n__read5079__q40[17]) ?
|
|
(INV_n__read5079__q40[18] ? 5'd18 : 5'd19) :
|
|
(INV_n__read5079__q40[16] ? 5'd16 : 5'd17)))) :
|
|
((!INV_n__read5079__q40[0] && !INV_n__read5079__q40[1] &&
|
|
!INV_n__read5079__q40[2] &&
|
|
!INV_n__read5079__q40[3] &&
|
|
!INV_n__read5079__q40[4] &&
|
|
!INV_n__read5079__q40[5] &&
|
|
!INV_n__read5079__q40[6] &&
|
|
!INV_n__read5079__q40[7]) ?
|
|
((!INV_n__read5079__q40[8] && !INV_n__read5079__q40[9] &&
|
|
!INV_n__read5079__q40[10] &&
|
|
!INV_n__read5079__q40[11]) ?
|
|
((!INV_n__read5079__q40[12] &&
|
|
!INV_n__read5079__q40[13]) ?
|
|
(INV_n__read5079__q40[14] ? 5'd14 : 5'd15) :
|
|
(INV_n__read5079__q40[12] ? 5'd12 : 5'd13)) :
|
|
((!INV_n__read5079__q40[8] && !INV_n__read5079__q40[9]) ?
|
|
(INV_n__read5079__q40[10] ? 5'd10 : 5'd11) :
|
|
(INV_n__read5079__q40[8] ? 5'd8 : 5'd9))) :
|
|
((!INV_n__read5079__q40[0] && !INV_n__read5079__q40[1] &&
|
|
!INV_n__read5079__q40[2] &&
|
|
!INV_n__read5079__q40[3]) ?
|
|
((!INV_n__read5079__q40[4] && !INV_n__read5079__q40[5]) ?
|
|
(INV_n__read5079__q40[6] ? 5'd6 : 5'd7) :
|
|
(INV_n__read5079__q40[4] ? 5'd4 : 5'd5)) :
|
|
((!INV_n__read5079__q40[0] && !INV_n__read5079__q40[1]) ?
|
|
(INV_n__read5079__q40[2] ? 5'd2 : 5'd3) :
|
|
(INV_n__read5079__q40[0] ? 5'd0 : 5'd1)))) ;
|
|
assign addIdx__h54605 =
|
|
(tlb_m_validVec_0_071_AND_tlb_m_validVec_1_072__ETC___d1085 &&
|
|
tlb_m_validVec_8_086_AND_tlb_m_validVec_9_087__ETC___d1100) ?
|
|
(tlb_m_validVec_16_102_AND_tlb_m_validVec_17_10_ETC___d1116 ?
|
|
IF_tlb_m_validVec_24_117_AND_tlb_m_validVec_25_ETC___d1307 :
|
|
IF_tlb_m_validVec_16_102_AND_tlb_m_validVec_17_ETC___d1314) :
|
|
(tlb_m_validVec_0_071_AND_tlb_m_validVec_1_072__ETC___d1085 ?
|
|
IF_tlb_m_validVec_8_086_AND_tlb_m_validVec_9_0_ETC___d1322 :
|
|
IF_tlb_m_validVec_0_071_AND_tlb_m_validVec_1_0_ETC___d1329) ;
|
|
assign idx__h69134 =
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1855 ?
|
|
5'd31 :
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1988 ;
|
|
assign n__read__h45079 =
|
|
tlb_m_lruBit_lat_0$whas ? upd__h45106 : tlb_m_lruBit_rl ;
|
|
assign next_deqP___1__h12848 = rqToPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h17463 = rsFromPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h9212 = hitQ_deqP + 1'd1 ;
|
|
assign tlb_m_validVec_0_071_AND_tlb_m_validVec_1_072__ETC___d1085 =
|
|
tlb_m_validVec_0 && tlb_m_validVec_1 && tlb_m_validVec_2 &&
|
|
tlb_m_validVec_3 &&
|
|
tlb_m_validVec_4 &&
|
|
tlb_m_validVec_5 &&
|
|
tlb_m_validVec_6 &&
|
|
tlb_m_validVec_7 ;
|
|
assign tlb_m_validVec_0_071_AND_tlb_m_validVec_1_072__ETC___d1234 =
|
|
tlb_m_validVec_0_071_AND_tlb_m_validVec_1_072__ETC___d1085 &&
|
|
tlb_m_validVec_8_086_AND_tlb_m_validVec_9_087__ETC___d1100 &&
|
|
tlb_m_validVec_16_102_AND_tlb_m_validVec_17_10_ETC___d1116 &&
|
|
tlb_m_validVec_24_117_AND_tlb_m_validVec_25_11_ETC___d1131 &&
|
|
!SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 &&
|
|
!INV_n__read5079__q40[0] &&
|
|
!INV_n__read5079__q40[1] &&
|
|
!INV_n__read5079__q40[2] &&
|
|
!INV_n__read5079__q40[3] &&
|
|
!INV_n__read5079__q40[4] &&
|
|
!INV_n__read5079__q40[5] &&
|
|
!INV_n__read5079__q40[6] &&
|
|
!INV_n__read5079__q40[7] &&
|
|
!INV_n__read5079__q40[8] &&
|
|
!INV_n__read5079__q40[9] &&
|
|
!INV_n__read5079__q40[10] &&
|
|
!INV_n__read5079__q40[11] &&
|
|
!INV_n__read5079__q40[12] &&
|
|
!INV_n__read5079__q40[13] &&
|
|
!INV_n__read5079__q40[14] &&
|
|
!INV_n__read5079__q40[15] &&
|
|
!INV_n__read5079__q40[16] &&
|
|
!INV_n__read5079__q40[17] &&
|
|
!INV_n__read5079__q40[18] &&
|
|
!INV_n__read5079__q40[19] &&
|
|
!INV_n__read5079__q40[20] &&
|
|
!INV_n__read5079__q40[21] &&
|
|
!INV_n__read5079__q40[22] &&
|
|
!INV_n__read5079__q40[23] &&
|
|
!INV_n__read5079__q40[24] &&
|
|
!INV_n__read5079__q40[25] &&
|
|
!INV_n__read5079__q40[26] &&
|
|
!INV_n__read5079__q40[27] &&
|
|
!INV_n__read5079__q40[28] &&
|
|
!INV_n__read5079__q40[29] &&
|
|
!INV_n__read5079__q40[30] &&
|
|
!INV_n__read5079__q40[31] ;
|
|
assign tlb_m_validVec_16_102_AND_tlb_m_validVec_17_10_ETC___d1116 =
|
|
tlb_m_validVec_16 && tlb_m_validVec_17 && tlb_m_validVec_18 &&
|
|
tlb_m_validVec_19 &&
|
|
tlb_m_validVec_20 &&
|
|
tlb_m_validVec_21 &&
|
|
tlb_m_validVec_22 &&
|
|
tlb_m_validVec_23 ;
|
|
assign tlb_m_validVec_24_117_AND_tlb_m_validVec_25_11_ETC___d1131 =
|
|
tlb_m_validVec_24 && tlb_m_validVec_25 && tlb_m_validVec_26 &&
|
|
tlb_m_validVec_27 &&
|
|
tlb_m_validVec_28 &&
|
|
tlb_m_validVec_29 &&
|
|
tlb_m_validVec_30 &&
|
|
tlb_m_validVec_31 ;
|
|
assign tlb_m_validVec_8_086_AND_tlb_m_validVec_9_087__ETC___d1100 =
|
|
tlb_m_validVec_8 && tlb_m_validVec_9 && tlb_m_validVec_10 &&
|
|
tlb_m_validVec_11 &&
|
|
tlb_m_validVec_12 &&
|
|
tlb_m_validVec_13 &&
|
|
tlb_m_validVec_14 &&
|
|
tlb_m_validVec_15 ;
|
|
assign upd__h45106 =
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep ?
|
|
MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1 :
|
|
32'd0 ;
|
|
assign v__h12287 =
|
|
IF_rqToPQ_enqReq_lat_1_whas__56_THEN_rqToPQ_en_ETC___d165 ?
|
|
v__h12438 :
|
|
rqToPQ_enqP ;
|
|
assign v__h12438 = rqToPQ_enqP + 1'd1 ;
|
|
assign v__h16232 =
|
|
IF_rsFromPQ_enqReq_lat_1_whas__41_THEN_rsFromP_ETC___d250 ?
|
|
v__h16383 :
|
|
rsFromPQ_enqP ;
|
|
assign v__h16383 = rsFromPQ_enqP + 1'd1 ;
|
|
assign v__h39526 =
|
|
(NOT_tlb_m_validVec_0_071_238_OR_NOT_tlb_m_vali_ETC___d1252 ||
|
|
NOT_tlb_m_validVec_8_086_253_OR_NOT_tlb_m_vali_ETC___d1267 ||
|
|
NOT_tlb_m_validVec_16_102_269_OR_NOT_tlb_m_val_ETC___d1283 ||
|
|
NOT_tlb_m_validVec_24_117_284_OR_NOT_tlb_m_val_ETC___d1298) ?
|
|
addIdx__h54605 :
|
|
v__h44343 ;
|
|
assign v__h44343 =
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 ?
|
|
tlb_m_randIdx :
|
|
v__h45871 ;
|
|
assign v__h45871 =
|
|
(INV_n__read5079__q40[0] || INV_n__read5079__q40[1] ||
|
|
INV_n__read5079__q40[2] ||
|
|
INV_n__read5079__q40[3] ||
|
|
INV_n__read5079__q40[4] ||
|
|
INV_n__read5079__q40[5] ||
|
|
INV_n__read5079__q40[6] ||
|
|
INV_n__read5079__q40[7] ||
|
|
INV_n__read5079__q40[8] ||
|
|
INV_n__read5079__q40[9] ||
|
|
INV_n__read5079__q40[10] ||
|
|
INV_n__read5079__q40[11] ||
|
|
INV_n__read5079__q40[12] ||
|
|
INV_n__read5079__q40[13] ||
|
|
INV_n__read5079__q40[14] ||
|
|
INV_n__read5079__q40[15] ||
|
|
INV_n__read5079__q40[16] ||
|
|
INV_n__read5079__q40[17] ||
|
|
INV_n__read5079__q40[18] ||
|
|
INV_n__read5079__q40[19] ||
|
|
INV_n__read5079__q40[20] ||
|
|
INV_n__read5079__q40[21] ||
|
|
INV_n__read5079__q40[22] ||
|
|
INV_n__read5079__q40[23] ||
|
|
INV_n__read5079__q40[24] ||
|
|
INV_n__read5079__q40[25] ||
|
|
INV_n__read5079__q40[26] ||
|
|
INV_n__read5079__q40[27] ||
|
|
INV_n__read5079__q40[28] ||
|
|
INV_n__read5079__q40[29] ||
|
|
INV_n__read5079__q40[30] ||
|
|
INV_n__read5079__q40[31]) ?
|
|
addIdx__h49754 :
|
|
5'd0 ;
|
|
assign v__h8385 =
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ?
|
|
v__h8536 :
|
|
hitQ_enqP ;
|
|
assign v__h8536 = hitQ_enqP + 1'd1 ;
|
|
assign val__h5317 = tlb_m_lruBit_rl | x__h5375 ;
|
|
assign vm_info_43_BIT_46_79_AND_IF_NOT_tlb_m_validVec_ETC___d2267 =
|
|
vm_info[46] &&
|
|
IF_NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb__ETC___d1924 &&
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 &&
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991__ETC___d2247 ;
|
|
assign vm_info_43_BIT_46_79_AND_NOT_tlb_m_validVec_0__ETC___d2272 =
|
|
vm_info[46] &&
|
|
NOT_tlb_m_validVec_0_071_238_OR_NOT_IF_tlb_m_e_ETC___d1855 &&
|
|
(!tlb_m_validVec_31 ||
|
|
!IF_tlb_m_entryVec_31_028_BITS_1_TO_0_032_EQ_0__ETC___d1862) ;
|
|
assign x__h5375 = 32'd1 << tlb_m_updRepIdx_rl[4:0] ;
|
|
assign x__h64352 = { 8'd0, x__h64360 } ;
|
|
assign x__h73861 = { 8'd0, x__h73869 } ;
|
|
assign x__h8655 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[69:6] :
|
|
hitQ_enqReq_rl[69:6] ;
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0: level__h32531 = rsFromPQ_data_0[1:0];
|
|
1'd1: level__h32531 = rsFromPQ_data_1[1:0];
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0: x__h74094 = hitQ_data_0[69:6];
|
|
1'd1: x__h74094 = hitQ_data_1[69:6];
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q1 =
|
|
!hitQ_data_0[5];
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q1 =
|
|
!hitQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_1_hit_ETC__q2 =
|
|
hitQ_data_0[4:0];
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_1_hit_ETC__q2 =
|
|
hitQ_data_1[4:0];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 =
|
|
rsFromPQ_data_0[79:53];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640 =
|
|
rsFromPQ_data_1[79:53];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 =
|
|
rsFromPQ_data_0[80];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 =
|
|
rsFromPQ_data_1[80];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 =
|
|
rsFromPQ_data_0[7];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d531 =
|
|
rsFromPQ_data_1[7];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556 =
|
|
rsFromPQ_data_0[52:9];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556 =
|
|
rsFromPQ_data_1[52:9];
|
|
endcase
|
|
end
|
|
always@(level__h32531 or
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556 or miss)
|
|
begin
|
|
case (level__h32531)
|
|
2'd0:
|
|
x__h64360 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556,
|
|
miss[11:0] };
|
|
2'd1:
|
|
x__h64360 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[43:9],
|
|
miss[20:0] };
|
|
2'd2:
|
|
x__h64360 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[43:18],
|
|
miss[29:0] };
|
|
2'd3: x__h64360 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571 =
|
|
rsFromPQ_data_0[3];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_3_68_rsFromPQ_d_ETC___d571 =
|
|
rsFromPQ_data_1[3];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542 =
|
|
rsFromPQ_data_0[5];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_5_39_rsFromPQ_d_ETC___d542 =
|
|
rsFromPQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577 =
|
|
!rsFromPQ_data_0[2];
|
|
1'd1:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_2_72_73_NOT_ETC___d577 =
|
|
!rsFromPQ_data_1[2];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538 =
|
|
!rsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_21_BIT_4_33_34_NOT_ETC___d538 =
|
|
!rsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(level__h32531 or
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640)
|
|
begin
|
|
case (level__h32531)
|
|
2'd0:
|
|
CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q3 =
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640;
|
|
2'd1:
|
|
CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q3 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640[26:9],
|
|
9'd0 };
|
|
2'd2:
|
|
CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q3 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_79_TO_53_37_rs_ETC___d640[26:18],
|
|
18'd0 };
|
|
2'd3: CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q3 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(level__h32531 or
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556)
|
|
begin
|
|
case (level__h32531)
|
|
2'd0:
|
|
CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q4 =
|
|
SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556;
|
|
2'd1:
|
|
CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q4 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[43:9],
|
|
9'd0 };
|
|
2'd2:
|
|
CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q4 =
|
|
{ SEL_ARR_rsFromPQ_data_0_21_BITS_52_TO_9_53_rsF_ETC___d556[43:18],
|
|
18'd0 };
|
|
2'd3: CASE_level2531_0_SEL_ARR_rsFromPQ_data_0_21_BI_ETC__q4 = 44'd0;
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 =
|
|
rsFromPQ_data_0[6];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_6_61_rsFromPQ_d_ETC___d664 =
|
|
rsFromPQ_data_1[6];
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_1 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_1[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q5 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_0 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_0[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q6 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_2 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_2[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q7 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_3 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_3[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q8 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_4 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_4[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q9 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_5 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_5[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q10 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_6 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_6[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q11 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q11 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q11 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q11 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_7 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_7[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q12 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q12 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q12 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q12 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_8 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_8[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q13 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q13 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q13 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q13 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_9 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_9[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q14 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q14 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q14 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q14 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_10 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_10[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q15 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_11 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_11[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q16 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_12 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_12[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q17 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_13 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_13[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q18 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_14 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_14[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q19 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_15 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_15[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q20 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_16 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_16[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q21 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_17 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_17[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q22 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_18 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_18[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q23 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_19 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_19[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q24 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_20 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_20[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q25 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_21 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_21[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q26 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_22 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_22[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q27 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_23 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_23[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q28 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_24 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_24[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q29 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_25 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_25[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q30 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_26 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_26[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q31 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_27 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_27[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q32 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_28 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_28[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q33 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q33 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q33 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q33 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_29 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_29[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q34 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q34 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q34 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q34 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_30 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_30[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q35 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q35 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q35 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q35 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_31 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_31[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q36 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q36 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q36 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q36 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h69134 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h69134)
|
|
5'd0: ppn__h73865 = tlb_m_entryVec_0[52:9];
|
|
5'd1: ppn__h73865 = tlb_m_entryVec_1[52:9];
|
|
5'd2: ppn__h73865 = tlb_m_entryVec_2[52:9];
|
|
5'd3: ppn__h73865 = tlb_m_entryVec_3[52:9];
|
|
5'd4: ppn__h73865 = tlb_m_entryVec_4[52:9];
|
|
5'd5: ppn__h73865 = tlb_m_entryVec_5[52:9];
|
|
5'd6: ppn__h73865 = tlb_m_entryVec_6[52:9];
|
|
5'd7: ppn__h73865 = tlb_m_entryVec_7[52:9];
|
|
5'd8: ppn__h73865 = tlb_m_entryVec_8[52:9];
|
|
5'd9: ppn__h73865 = tlb_m_entryVec_9[52:9];
|
|
5'd10: ppn__h73865 = tlb_m_entryVec_10[52:9];
|
|
5'd11: ppn__h73865 = tlb_m_entryVec_11[52:9];
|
|
5'd12: ppn__h73865 = tlb_m_entryVec_12[52:9];
|
|
5'd13: ppn__h73865 = tlb_m_entryVec_13[52:9];
|
|
5'd14: ppn__h73865 = tlb_m_entryVec_14[52:9];
|
|
5'd15: ppn__h73865 = tlb_m_entryVec_15[52:9];
|
|
5'd16: ppn__h73865 = tlb_m_entryVec_16[52:9];
|
|
5'd17: ppn__h73865 = tlb_m_entryVec_17[52:9];
|
|
5'd18: ppn__h73865 = tlb_m_entryVec_18[52:9];
|
|
5'd19: ppn__h73865 = tlb_m_entryVec_19[52:9];
|
|
5'd20: ppn__h73865 = tlb_m_entryVec_20[52:9];
|
|
5'd21: ppn__h73865 = tlb_m_entryVec_21[52:9];
|
|
5'd22: ppn__h73865 = tlb_m_entryVec_22[52:9];
|
|
5'd23: ppn__h73865 = tlb_m_entryVec_23[52:9];
|
|
5'd24: ppn__h73865 = tlb_m_entryVec_24[52:9];
|
|
5'd25: ppn__h73865 = tlb_m_entryVec_25[52:9];
|
|
5'd26: ppn__h73865 = tlb_m_entryVec_26[52:9];
|
|
5'd27: ppn__h73865 = tlb_m_entryVec_27[52:9];
|
|
5'd28: ppn__h73865 = tlb_m_entryVec_28[52:9];
|
|
5'd29: ppn__h73865 = tlb_m_entryVec_29[52:9];
|
|
5'd30: ppn__h73865 = tlb_m_entryVec_30[52:9];
|
|
5'd31: ppn__h73865 = tlb_m_entryVec_31[52:9];
|
|
endcase
|
|
end
|
|
always@(idx__h69134 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h69134)
|
|
5'd0: level__h69148 = tlb_m_entryVec_0[1:0];
|
|
5'd1: level__h69148 = tlb_m_entryVec_1[1:0];
|
|
5'd2: level__h69148 = tlb_m_entryVec_2[1:0];
|
|
5'd3: level__h69148 = tlb_m_entryVec_3[1:0];
|
|
5'd4: level__h69148 = tlb_m_entryVec_4[1:0];
|
|
5'd5: level__h69148 = tlb_m_entryVec_5[1:0];
|
|
5'd6: level__h69148 = tlb_m_entryVec_6[1:0];
|
|
5'd7: level__h69148 = tlb_m_entryVec_7[1:0];
|
|
5'd8: level__h69148 = tlb_m_entryVec_8[1:0];
|
|
5'd9: level__h69148 = tlb_m_entryVec_9[1:0];
|
|
5'd10: level__h69148 = tlb_m_entryVec_10[1:0];
|
|
5'd11: level__h69148 = tlb_m_entryVec_11[1:0];
|
|
5'd12: level__h69148 = tlb_m_entryVec_12[1:0];
|
|
5'd13: level__h69148 = tlb_m_entryVec_13[1:0];
|
|
5'd14: level__h69148 = tlb_m_entryVec_14[1:0];
|
|
5'd15: level__h69148 = tlb_m_entryVec_15[1:0];
|
|
5'd16: level__h69148 = tlb_m_entryVec_16[1:0];
|
|
5'd17: level__h69148 = tlb_m_entryVec_17[1:0];
|
|
5'd18: level__h69148 = tlb_m_entryVec_18[1:0];
|
|
5'd19: level__h69148 = tlb_m_entryVec_19[1:0];
|
|
5'd20: level__h69148 = tlb_m_entryVec_20[1:0];
|
|
5'd21: level__h69148 = tlb_m_entryVec_21[1:0];
|
|
5'd22: level__h69148 = tlb_m_entryVec_22[1:0];
|
|
5'd23: level__h69148 = tlb_m_entryVec_23[1:0];
|
|
5'd24: level__h69148 = tlb_m_entryVec_24[1:0];
|
|
5'd25: level__h69148 = tlb_m_entryVec_25[1:0];
|
|
5'd26: level__h69148 = tlb_m_entryVec_26[1:0];
|
|
5'd27: level__h69148 = tlb_m_entryVec_27[1:0];
|
|
5'd28: level__h69148 = tlb_m_entryVec_28[1:0];
|
|
5'd29: level__h69148 = tlb_m_entryVec_29[1:0];
|
|
5'd30: level__h69148 = tlb_m_entryVec_30[1:0];
|
|
5'd31: level__h69148 = tlb_m_entryVec_31[1:0];
|
|
endcase
|
|
end
|
|
always@(level__h69148 or ppn__h73865 or to_proc_request_put)
|
|
begin
|
|
case (level__h69148)
|
|
2'd0: x__h73869 = { ppn__h73865, to_proc_request_put[11:0] };
|
|
2'd1: x__h73869 = { ppn__h73865[43:9], to_proc_request_put[20:0] };
|
|
2'd2: x__h73869 = { ppn__h73865[43:18], to_proc_request_put[29:0] };
|
|
2'd3: x__h73869 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h69134 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h69134)
|
|
5'd0:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_0[4];
|
|
5'd1:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_1[4];
|
|
5'd2:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_2[4];
|
|
5'd3:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_3[4];
|
|
5'd4:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_4[4];
|
|
5'd5:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_5[4];
|
|
5'd6:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_6[4];
|
|
5'd7:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_7[4];
|
|
5'd8:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_8[4];
|
|
5'd9:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_9[4];
|
|
5'd10:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_10[4];
|
|
5'd11:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_11[4];
|
|
5'd12:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_12[4];
|
|
5'd13:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_13[4];
|
|
5'd14:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_14[4];
|
|
5'd15:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_15[4];
|
|
5'd16:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_16[4];
|
|
5'd17:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_17[4];
|
|
5'd18:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_18[4];
|
|
5'd19:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_19[4];
|
|
5'd20:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_20[4];
|
|
5'd21:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_21[4];
|
|
5'd22:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_22[4];
|
|
5'd23:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_23[4];
|
|
5'd24:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_24[4];
|
|
5'd25:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_25[4];
|
|
5'd26:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_26[4];
|
|
5'd27:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_27[4];
|
|
5'd28:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_28[4];
|
|
5'd29:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_29[4];
|
|
5'd30:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_30[4];
|
|
5'd31:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_4_991_992__ETC___d2056 =
|
|
!tlb_m_entryVec_31[4];
|
|
endcase
|
|
end
|
|
always@(idx__h69134 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h69134)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_0[3];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_1[3];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_2[3];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_3[3];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_4[3];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_5[3];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_6[3];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_7[3];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_8[3];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_9[3];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_10[3];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_11[3];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_12[3];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_13[3];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_14[3];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_15[3];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_16[3];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_17[3];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_18[3];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_19[3];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_20[3];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_21[3];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_22[3];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_23[3];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_24[3];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_25[3];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_26[3];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_27[3];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_28[3];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_29[3];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_30[3];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_3_140_tlb_m_en_ETC___d2173 =
|
|
tlb_m_entryVec_31[3];
|
|
endcase
|
|
end
|
|
always@(idx__h69134 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h69134)
|
|
5'd0:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_52_BIT_2_175_176__ETC___d2240 =
|
|
!tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h69134 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h69134)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_0[5];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_1[5];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_2[5];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_3[5];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_4[5];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_5[5];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_6[5];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_7[5];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_8[5];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_9[5];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_10[5];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_11[5];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_12[5];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_13[5];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_14[5];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_15[5];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_16[5];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_17[5];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_18[5];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_19[5];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_20[5];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_21[5];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_22[5];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_23[5];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_24[5];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_25[5];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_26[5];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_27[5];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_28[5];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_29[5];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_30[5];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_5_058_tlb_m_en_ETC___d2091 =
|
|
tlb_m_entryVec_31[5];
|
|
endcase
|
|
end
|
|
always@(idx__h69134 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h69134)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_0[7];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_1[7];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_2[7];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_3[7];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_4[7];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_5[7];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_6[7];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_7[7];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_8[7];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_9[7];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_10[7];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_11[7];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_12[7];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_13[7];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_14[7];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_15[7];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_16[7];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_17[7];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_18[7];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_19[7];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_20[7];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_21[7];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_22[7];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_23[7];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_24[7];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_25[7];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_26[7];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_27[7];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_28[7];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_29[7];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_30[7];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_52_BIT_7_926_tlb_m_en_ETC___d1990 =
|
|
tlb_m_entryVec_31[7];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q37 =
|
|
rsFromPQ_data_0[4];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q37 =
|
|
rsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q38 =
|
|
rsFromPQ_data_0[2];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q38 =
|
|
rsFromPQ_data_1[2];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q39 =
|
|
rsFromPQ_data_0[8];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q39 =
|
|
rsFromPQ_data_1[8];
|
|
endcase
|
|
end
|
|
always@(tlb_m_randIdx or INV_n__read5079__q40)
|
|
begin
|
|
case (tlb_m_randIdx)
|
|
5'd0:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[0];
|
|
5'd1:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[1];
|
|
5'd2:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[2];
|
|
5'd3:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[3];
|
|
5'd4:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[4];
|
|
5'd5:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[5];
|
|
5'd6:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[6];
|
|
5'd7:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[7];
|
|
5'd8:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[8];
|
|
5'd9:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[9];
|
|
5'd10:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[10];
|
|
5'd11:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[11];
|
|
5'd12:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[12];
|
|
5'd13:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[13];
|
|
5'd14:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[14];
|
|
5'd15:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[15];
|
|
5'd16:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[16];
|
|
5'd17:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[17];
|
|
5'd18:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[18];
|
|
5'd19:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[19];
|
|
5'd20:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[20];
|
|
5'd21:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[21];
|
|
5'd22:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[22];
|
|
5'd23:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[23];
|
|
5'd24:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[24];
|
|
5'd25:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[25];
|
|
5'd26:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[26];
|
|
5'd27:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[27];
|
|
5'd28:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[28];
|
|
5'd29:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[29];
|
|
5'd30:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[30];
|
|
5'd31:
|
|
SEL_ARR_INV_IF_tlb_m_lruBit_lat_0_whas_THEN_tl_ETC___d1168 =
|
|
INV_n__read5079__q40[31];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 65'd0, 5'bxxxxx /* unspecified value */ };
|
|
hitQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 65'd0, 5'bxxxxx /* unspecified value */ };
|
|
hitQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
hitQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
70'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
hitQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
miss <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
needFlush <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 3'bxxx /* unspecified value */ };
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 27'd0;
|
|
rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 27'd0;
|
|
rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
27'bxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
rqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
80'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
rsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
80'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
rsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0,
|
|
81'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ };
|
|
rsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 32'd0;
|
|
tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY 5'd0;
|
|
tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
{ 1'd0, 5'bxxxxx /* unspecified value */ };
|
|
tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
vm_info <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
waitFlushP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (flushRqToPQ_clearReq_rl$EN)
|
|
flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_clearReq_rl$D_IN;
|
|
if (flushRqToPQ_deqReq_rl$EN)
|
|
flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_deqReq_rl$D_IN;
|
|
if (flushRqToPQ_empty$EN)
|
|
flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY flushRqToPQ_empty$D_IN;
|
|
if (flushRqToPQ_enqReq_rl$EN)
|
|
flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_enqReq_rl$D_IN;
|
|
if (flushRqToPQ_full$EN)
|
|
flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY flushRqToPQ_full$D_IN;
|
|
if (flushRsFromPQ_clearReq_rl$EN)
|
|
flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_clearReq_rl$D_IN;
|
|
if (flushRsFromPQ_deqReq_rl$EN)
|
|
flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_deqReq_rl$D_IN;
|
|
if (flushRsFromPQ_empty$EN)
|
|
flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_empty$D_IN;
|
|
if (flushRsFromPQ_enqReq_rl$EN)
|
|
flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_enqReq_rl$D_IN;
|
|
if (flushRsFromPQ_full$EN)
|
|
flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY flushRsFromPQ_full$D_IN;
|
|
if (hitQ_clearReq_rl$EN)
|
|
hitQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_clearReq_rl$D_IN;
|
|
if (hitQ_data_0$EN)
|
|
hitQ_data_0 <= `BSV_ASSIGNMENT_DELAY hitQ_data_0$D_IN;
|
|
if (hitQ_data_1$EN)
|
|
hitQ_data_1 <= `BSV_ASSIGNMENT_DELAY hitQ_data_1$D_IN;
|
|
if (hitQ_deqP$EN) hitQ_deqP <= `BSV_ASSIGNMENT_DELAY hitQ_deqP$D_IN;
|
|
if (hitQ_deqReq_rl$EN)
|
|
hitQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_deqReq_rl$D_IN;
|
|
if (hitQ_empty$EN)
|
|
hitQ_empty <= `BSV_ASSIGNMENT_DELAY hitQ_empty$D_IN;
|
|
if (hitQ_enqP$EN) hitQ_enqP <= `BSV_ASSIGNMENT_DELAY hitQ_enqP$D_IN;
|
|
if (hitQ_enqReq_rl$EN)
|
|
hitQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_enqReq_rl$D_IN;
|
|
if (hitQ_full$EN) hitQ_full <= `BSV_ASSIGNMENT_DELAY hitQ_full$D_IN;
|
|
if (miss$EN) miss <= `BSV_ASSIGNMENT_DELAY miss$D_IN;
|
|
if (needFlush$EN) needFlush <= `BSV_ASSIGNMENT_DELAY needFlush$D_IN;
|
|
if (perfReqQ_clearReq_rl$EN)
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
perfReqQ_clearReq_rl$D_IN;
|
|
if (perfReqQ_data_0$EN)
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY perfReqQ_data_0$D_IN;
|
|
if (perfReqQ_deqReq_rl$EN)
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_deqReq_rl$D_IN;
|
|
if (perfReqQ_empty$EN)
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY perfReqQ_empty$D_IN;
|
|
if (perfReqQ_enqReq_rl$EN)
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN;
|
|
if (perfReqQ_full$EN)
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN;
|
|
if (rqToPQ_clearReq_rl$EN)
|
|
rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_clearReq_rl$D_IN;
|
|
if (rqToPQ_data_0$EN)
|
|
rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY rqToPQ_data_0$D_IN;
|
|
if (rqToPQ_data_1$EN)
|
|
rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY rqToPQ_data_1$D_IN;
|
|
if (rqToPQ_deqP$EN)
|
|
rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY rqToPQ_deqP$D_IN;
|
|
if (rqToPQ_deqReq_rl$EN)
|
|
rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_deqReq_rl$D_IN;
|
|
if (rqToPQ_empty$EN)
|
|
rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY rqToPQ_empty$D_IN;
|
|
if (rqToPQ_enqP$EN)
|
|
rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY rqToPQ_enqP$D_IN;
|
|
if (rqToPQ_enqReq_rl$EN)
|
|
rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_enqReq_rl$D_IN;
|
|
if (rqToPQ_full$EN)
|
|
rqToPQ_full <= `BSV_ASSIGNMENT_DELAY rqToPQ_full$D_IN;
|
|
if (rsFromPQ_clearReq_rl$EN)
|
|
rsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
rsFromPQ_clearReq_rl$D_IN;
|
|
if (rsFromPQ_data_0$EN)
|
|
rsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY rsFromPQ_data_0$D_IN;
|
|
if (rsFromPQ_data_1$EN)
|
|
rsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY rsFromPQ_data_1$D_IN;
|
|
if (rsFromPQ_deqP$EN)
|
|
rsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY rsFromPQ_deqP$D_IN;
|
|
if (rsFromPQ_deqReq_rl$EN)
|
|
rsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY rsFromPQ_deqReq_rl$D_IN;
|
|
if (rsFromPQ_empty$EN)
|
|
rsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY rsFromPQ_empty$D_IN;
|
|
if (rsFromPQ_enqP$EN)
|
|
rsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY rsFromPQ_enqP$D_IN;
|
|
if (rsFromPQ_enqReq_rl$EN)
|
|
rsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY rsFromPQ_enqReq_rl$D_IN;
|
|
if (rsFromPQ_full$EN)
|
|
rsFromPQ_full <= `BSV_ASSIGNMENT_DELAY rsFromPQ_full$D_IN;
|
|
if (tlb_m_lruBit_rl$EN)
|
|
tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY tlb_m_lruBit_rl$D_IN;
|
|
if (tlb_m_randIdx$EN)
|
|
tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY tlb_m_randIdx$D_IN;
|
|
if (tlb_m_updRepIdx_rl$EN)
|
|
tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY tlb_m_updRepIdx_rl$D_IN;
|
|
if (tlb_m_validVec_0$EN)
|
|
tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_0$D_IN;
|
|
if (tlb_m_validVec_1$EN)
|
|
tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_1$D_IN;
|
|
if (tlb_m_validVec_10$EN)
|
|
tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_10$D_IN;
|
|
if (tlb_m_validVec_11$EN)
|
|
tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_11$D_IN;
|
|
if (tlb_m_validVec_12$EN)
|
|
tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_12$D_IN;
|
|
if (tlb_m_validVec_13$EN)
|
|
tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_13$D_IN;
|
|
if (tlb_m_validVec_14$EN)
|
|
tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_14$D_IN;
|
|
if (tlb_m_validVec_15$EN)
|
|
tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_15$D_IN;
|
|
if (tlb_m_validVec_16$EN)
|
|
tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_16$D_IN;
|
|
if (tlb_m_validVec_17$EN)
|
|
tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_17$D_IN;
|
|
if (tlb_m_validVec_18$EN)
|
|
tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_18$D_IN;
|
|
if (tlb_m_validVec_19$EN)
|
|
tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_19$D_IN;
|
|
if (tlb_m_validVec_2$EN)
|
|
tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_2$D_IN;
|
|
if (tlb_m_validVec_20$EN)
|
|
tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_20$D_IN;
|
|
if (tlb_m_validVec_21$EN)
|
|
tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_21$D_IN;
|
|
if (tlb_m_validVec_22$EN)
|
|
tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_22$D_IN;
|
|
if (tlb_m_validVec_23$EN)
|
|
tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_23$D_IN;
|
|
if (tlb_m_validVec_24$EN)
|
|
tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_24$D_IN;
|
|
if (tlb_m_validVec_25$EN)
|
|
tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_25$D_IN;
|
|
if (tlb_m_validVec_26$EN)
|
|
tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_26$D_IN;
|
|
if (tlb_m_validVec_27$EN)
|
|
tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_27$D_IN;
|
|
if (tlb_m_validVec_28$EN)
|
|
tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_28$D_IN;
|
|
if (tlb_m_validVec_29$EN)
|
|
tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_29$D_IN;
|
|
if (tlb_m_validVec_3$EN)
|
|
tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_3$D_IN;
|
|
if (tlb_m_validVec_30$EN)
|
|
tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_30$D_IN;
|
|
if (tlb_m_validVec_31$EN)
|
|
tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_31$D_IN;
|
|
if (tlb_m_validVec_4$EN)
|
|
tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_4$D_IN;
|
|
if (tlb_m_validVec_5$EN)
|
|
tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_5$D_IN;
|
|
if (tlb_m_validVec_6$EN)
|
|
tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_6$D_IN;
|
|
if (tlb_m_validVec_7$EN)
|
|
tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_7$D_IN;
|
|
if (tlb_m_validVec_8$EN)
|
|
tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_8$D_IN;
|
|
if (tlb_m_validVec_9$EN)
|
|
tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_9$D_IN;
|
|
if (vm_info$EN) vm_info <= `BSV_ASSIGNMENT_DELAY vm_info$D_IN;
|
|
if (waitFlushP$EN)
|
|
waitFlushP <= `BSV_ASSIGNMENT_DELAY waitFlushP$D_IN;
|
|
end
|
|
if (tlb_m_entryVec_0$EN)
|
|
tlb_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_0$D_IN;
|
|
if (tlb_m_entryVec_1$EN)
|
|
tlb_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_1$D_IN;
|
|
if (tlb_m_entryVec_10$EN)
|
|
tlb_m_entryVec_10 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_10$D_IN;
|
|
if (tlb_m_entryVec_11$EN)
|
|
tlb_m_entryVec_11 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_11$D_IN;
|
|
if (tlb_m_entryVec_12$EN)
|
|
tlb_m_entryVec_12 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_12$D_IN;
|
|
if (tlb_m_entryVec_13$EN)
|
|
tlb_m_entryVec_13 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_13$D_IN;
|
|
if (tlb_m_entryVec_14$EN)
|
|
tlb_m_entryVec_14 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_14$D_IN;
|
|
if (tlb_m_entryVec_15$EN)
|
|
tlb_m_entryVec_15 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_15$D_IN;
|
|
if (tlb_m_entryVec_16$EN)
|
|
tlb_m_entryVec_16 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_16$D_IN;
|
|
if (tlb_m_entryVec_17$EN)
|
|
tlb_m_entryVec_17 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_17$D_IN;
|
|
if (tlb_m_entryVec_18$EN)
|
|
tlb_m_entryVec_18 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_18$D_IN;
|
|
if (tlb_m_entryVec_19$EN)
|
|
tlb_m_entryVec_19 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_19$D_IN;
|
|
if (tlb_m_entryVec_2$EN)
|
|
tlb_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_2$D_IN;
|
|
if (tlb_m_entryVec_20$EN)
|
|
tlb_m_entryVec_20 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_20$D_IN;
|
|
if (tlb_m_entryVec_21$EN)
|
|
tlb_m_entryVec_21 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_21$D_IN;
|
|
if (tlb_m_entryVec_22$EN)
|
|
tlb_m_entryVec_22 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_22$D_IN;
|
|
if (tlb_m_entryVec_23$EN)
|
|
tlb_m_entryVec_23 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_23$D_IN;
|
|
if (tlb_m_entryVec_24$EN)
|
|
tlb_m_entryVec_24 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_24$D_IN;
|
|
if (tlb_m_entryVec_25$EN)
|
|
tlb_m_entryVec_25 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_25$D_IN;
|
|
if (tlb_m_entryVec_26$EN)
|
|
tlb_m_entryVec_26 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_26$D_IN;
|
|
if (tlb_m_entryVec_27$EN)
|
|
tlb_m_entryVec_27 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_27$D_IN;
|
|
if (tlb_m_entryVec_28$EN)
|
|
tlb_m_entryVec_28 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_28$D_IN;
|
|
if (tlb_m_entryVec_29$EN)
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tlb_m_entryVec_29 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_29$D_IN;
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if (tlb_m_entryVec_3$EN)
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tlb_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_3$D_IN;
|
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if (tlb_m_entryVec_30$EN)
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|
tlb_m_entryVec_30 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_30$D_IN;
|
|
if (tlb_m_entryVec_31$EN)
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tlb_m_entryVec_31 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_31$D_IN;
|
|
if (tlb_m_entryVec_4$EN)
|
|
tlb_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_4$D_IN;
|
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if (tlb_m_entryVec_5$EN)
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tlb_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_5$D_IN;
|
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if (tlb_m_entryVec_6$EN)
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|
tlb_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_6$D_IN;
|
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if (tlb_m_entryVec_7$EN)
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tlb_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_7$D_IN;
|
|
if (tlb_m_entryVec_8$EN)
|
|
tlb_m_entryVec_8 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_8$D_IN;
|
|
if (tlb_m_entryVec_9$EN)
|
|
tlb_m_entryVec_9 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_9$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
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|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
flushRqToPQ_clearReq_rl = 1'h0;
|
|
flushRqToPQ_deqReq_rl = 1'h0;
|
|
flushRqToPQ_empty = 1'h0;
|
|
flushRqToPQ_enqReq_rl = 1'h0;
|
|
flushRqToPQ_full = 1'h0;
|
|
flushRsFromPQ_clearReq_rl = 1'h0;
|
|
flushRsFromPQ_deqReq_rl = 1'h0;
|
|
flushRsFromPQ_empty = 1'h0;
|
|
flushRsFromPQ_enqReq_rl = 1'h0;
|
|
flushRsFromPQ_full = 1'h0;
|
|
hitQ_clearReq_rl = 1'h0;
|
|
hitQ_data_0 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
hitQ_data_1 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
hitQ_deqP = 1'h0;
|
|
hitQ_deqReq_rl = 1'h0;
|
|
hitQ_empty = 1'h0;
|
|
hitQ_enqP = 1'h0;
|
|
hitQ_enqReq_rl = 71'h2AAAAAAAAAAAAAAAAA;
|
|
hitQ_full = 1'h0;
|
|
miss = 65'h0AAAAAAAAAAAAAAAA;
|
|
needFlush = 1'h0;
|
|
perfReqQ_clearReq_rl = 1'h0;
|
|
perfReqQ_data_0 = 3'h2;
|
|
perfReqQ_deqReq_rl = 1'h0;
|
|
perfReqQ_empty = 1'h0;
|
|
perfReqQ_enqReq_rl = 4'hA;
|
|
perfReqQ_full = 1'h0;
|
|
rqToPQ_clearReq_rl = 1'h0;
|
|
rqToPQ_data_0 = 27'h2AAAAAA;
|
|
rqToPQ_data_1 = 27'h2AAAAAA;
|
|
rqToPQ_deqP = 1'h0;
|
|
rqToPQ_deqReq_rl = 1'h0;
|
|
rqToPQ_empty = 1'h0;
|
|
rqToPQ_enqP = 1'h0;
|
|
rqToPQ_enqReq_rl = 28'hAAAAAAA;
|
|
rqToPQ_full = 1'h0;
|
|
rsFromPQ_clearReq_rl = 1'h0;
|
|
rsFromPQ_data_0 = 81'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_data_1 = 81'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_deqP = 1'h0;
|
|
rsFromPQ_deqReq_rl = 1'h0;
|
|
rsFromPQ_empty = 1'h0;
|
|
rsFromPQ_enqP = 1'h0;
|
|
rsFromPQ_enqReq_rl = 82'h2AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_full = 1'h0;
|
|
tlb_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_10 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_11 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_12 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_13 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_14 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_15 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_16 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_17 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_18 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_19 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_20 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_21 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_22 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_23 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_24 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_25 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_26 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_27 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_28 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_29 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_30 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_31 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_8 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_9 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_lruBit_rl = 32'hAAAAAAAA;
|
|
tlb_m_randIdx = 5'h0A;
|
|
tlb_m_updRepIdx_rl = 6'h2A;
|
|
tlb_m_validVec_0 = 1'h0;
|
|
tlb_m_validVec_1 = 1'h0;
|
|
tlb_m_validVec_10 = 1'h0;
|
|
tlb_m_validVec_11 = 1'h0;
|
|
tlb_m_validVec_12 = 1'h0;
|
|
tlb_m_validVec_13 = 1'h0;
|
|
tlb_m_validVec_14 = 1'h0;
|
|
tlb_m_validVec_15 = 1'h0;
|
|
tlb_m_validVec_16 = 1'h0;
|
|
tlb_m_validVec_17 = 1'h0;
|
|
tlb_m_validVec_18 = 1'h0;
|
|
tlb_m_validVec_19 = 1'h0;
|
|
tlb_m_validVec_2 = 1'h0;
|
|
tlb_m_validVec_20 = 1'h0;
|
|
tlb_m_validVec_21 = 1'h0;
|
|
tlb_m_validVec_22 = 1'h0;
|
|
tlb_m_validVec_23 = 1'h0;
|
|
tlb_m_validVec_24 = 1'h0;
|
|
tlb_m_validVec_25 = 1'h0;
|
|
tlb_m_validVec_26 = 1'h0;
|
|
tlb_m_validVec_27 = 1'h0;
|
|
tlb_m_validVec_28 = 1'h0;
|
|
tlb_m_validVec_29 = 1'h0;
|
|
tlb_m_validVec_3 = 1'h0;
|
|
tlb_m_validVec_30 = 1'h0;
|
|
tlb_m_validVec_31 = 1'h0;
|
|
tlb_m_validVec_4 = 1'h0;
|
|
tlb_m_validVec_5 = 1'h0;
|
|
tlb_m_validVec_6 = 1'h0;
|
|
tlb_m_validVec_7 = 1'h0;
|
|
tlb_m_validVec_8 = 1'h0;
|
|
tlb_m_validVec_9 = 1'h0;
|
|
vm_info = 49'h0AAAAAAAAAAAA;
|
|
waitFlushP = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d635)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d650)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_80_22_rsFromPQ__ETC___d526 &&
|
|
SEL_ARR_rsFromPQ_data_0_21_BIT_7_28_rsFromPQ_d_ETC___d1236)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkITlb
|
|
|