103 lines
2.6 KiB
Verilog
103 lines
2.6 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:22:47 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_request_put O 1 reg
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// response_get O 69 reg
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// RDY_response_get O 1 reg
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// CLK I 1 clock
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// RST_N I 1 reset
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// request_put I 131
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// EN_request_put I 1
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// EN_response_get I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkXilinxFpDiv(CLK,
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RST_N,
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request_put,
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EN_request_put,
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RDY_request_put,
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EN_response_get,
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response_get,
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RDY_response_get);
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input CLK;
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input RST_N;
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// action method request_put
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input [130 : 0] request_put;
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input EN_request_put;
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output RDY_request_put;
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// actionvalue method response_get
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input EN_response_get;
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output [68 : 0] response_get;
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output RDY_response_get;
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// signals for module outputs
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wire [68 : 0] response_get;
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wire RDY_request_put, RDY_response_get;
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// ports of submodule m
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wire [130 : 0] m$request_put;
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wire [68 : 0] m$response_get;
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wire m$EN_request_put,
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m$EN_response_get,
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m$RDY_request_put,
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m$RDY_response_get;
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// rule scheduling signals
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wire CAN_FIRE_request_put,
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CAN_FIRE_response_get,
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WILL_FIRE_request_put,
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WILL_FIRE_response_get;
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// action method request_put
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assign RDY_request_put = m$RDY_request_put ;
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assign CAN_FIRE_request_put = m$RDY_request_put ;
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assign WILL_FIRE_request_put = EN_request_put ;
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// actionvalue method response_get
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assign response_get = m$response_get ;
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assign RDY_response_get = m$RDY_response_get ;
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assign CAN_FIRE_response_get = m$RDY_response_get ;
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assign WILL_FIRE_response_get = EN_response_get ;
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// submodule m
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mkXilinxFpDivSim m(.CLK(CLK),
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.RST_N(RST_N),
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.request_put(m$request_put),
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.EN_request_put(m$EN_request_put),
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.EN_response_get(m$EN_response_get),
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.RDY_request_put(m$RDY_request_put),
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.response_get(m$response_get),
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.RDY_response_get(m$RDY_response_get));
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// submodule m
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assign m$request_put = request_put ;
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assign m$EN_request_put = EN_request_put ;
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assign m$EN_response_get = EN_response_get ;
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endmodule // mkXilinxFpDiv
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