111 lines
3.0 KiB
Verilog
111 lines
3.0 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:14:59 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// alu O 64
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// alu_a I 64
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// alu_b I 64
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// alu_func I 5
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//
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// Combinational paths from inputs to outputs:
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// (alu_a, alu_b, alu_func) -> alu
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_alu(alu_a,
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alu_b,
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alu_func,
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alu);
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// value method alu
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input [63 : 0] alu_a;
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input [63 : 0] alu_b;
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input [4 : 0] alu_func;
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output [63 : 0] alu;
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// signals for module outputs
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reg [63 : 0] alu;
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// remaining internal signals
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wire [63 : 0] alu_a_OR_alu_b___d16, alu_a_PLUS_alu_b___d2, y__h569;
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wire [31 : 0] alu_a_BITS_31_TO_0__q1,
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alu_a_PLUS_alu_b_BITS_31_TO_0__q2,
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x__h109,
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x__h266,
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x__h420,
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x__h490;
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wire x__h205, x__h213;
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// value method alu
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always@(alu_func or
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alu_a_PLUS_alu_b___d2 or
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alu_a_PLUS_alu_b_BITS_31_TO_0__q2 or
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alu_a or
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alu_b or
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x__h109 or
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alu_a_OR_alu_b___d16 or
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x__h205 or x__h213 or x__h266 or x__h490 or x__h420 or y__h569)
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begin
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case (alu_func)
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5'd0: alu = alu_a_PLUS_alu_b___d2;
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5'd1:
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alu =
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{ {32{alu_a_PLUS_alu_b_BITS_31_TO_0__q2[31]}},
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alu_a_PLUS_alu_b_BITS_31_TO_0__q2 };
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5'd2: alu = alu_a - alu_b;
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5'd3: alu = { {32{x__h109[31]}}, x__h109 };
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5'd4: alu = alu_a & alu_b;
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5'd5, 5'd16: alu = alu_a_OR_alu_b___d16;
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5'd6: alu = alu_a ^ alu_b;
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5'd7: alu = { 63'd0, x__h205 };
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5'd8: alu = { 63'd0, x__h213 };
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5'd9: alu = alu_a << alu_b[5:0];
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5'd10: alu = { {32{x__h266[31]}}, x__h266 };
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5'd11:
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alu =
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alu_a >> alu_b[5:0] |
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~(64'hFFFFFFFFFFFFFFFF >> alu_b[5:0]) & {64{alu_a[63]}};
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5'd12: alu = { {32{x__h490[31]}}, x__h490 };
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5'd13: alu = alu_a >> alu_b[5:0];
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5'd14: alu = { {32{x__h420[31]}}, x__h420 };
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5'd15: alu = alu_b;
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5'd17: alu = alu_a & y__h569;
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default: alu = 64'd0;
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endcase
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end
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// remaining internal signals
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assign alu_a_BITS_31_TO_0__q1 = alu_a[31:0] ;
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assign alu_a_OR_alu_b___d16 = alu_a | alu_b ;
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assign alu_a_PLUS_alu_b_BITS_31_TO_0__q2 = alu_a_PLUS_alu_b___d2[31:0] ;
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assign alu_a_PLUS_alu_b___d2 = alu_a + alu_b ;
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assign x__h109 = alu_a[31:0] - alu_b[31:0] ;
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assign x__h205 =
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(alu_a ^ 64'h8000000000000000) < (alu_b ^ 64'h8000000000000000) ;
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assign x__h213 = alu_a < alu_b ;
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assign x__h266 = alu_a[31:0] << alu_b[4:0] ;
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assign x__h420 = alu_a[31:0] >> alu_b[4:0] ;
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assign x__h490 =
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alu_a[31:0] >> alu_b[4:0] |
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~(32'hFFFFFFFF >> alu_b[4:0]) &
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{32{alu_a_BITS_31_TO_0__q1[31]}} ;
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assign y__h569 = ~alu_b ;
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endmodule // module_alu
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