566 lines
25 KiB
Verilog
566 lines
25 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:15:01 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// specialRWALU O 163
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// specialRWALU_cap I 163
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// specialRWALU_oldCap I 163
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// specialRWALU_scrType I 5
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//
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// Combinational paths from inputs to outputs:
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// (specialRWALU_cap,
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// specialRWALU_oldCap,
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// specialRWALU_scrType) -> specialRWALU
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_specialRWALU(specialRWALU_cap,
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specialRWALU_oldCap,
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specialRWALU_scrType,
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specialRWALU);
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// value method specialRWALU
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input [162 : 0] specialRWALU_cap;
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input [162 : 0] specialRWALU_oldCap;
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input [4 : 0] specialRWALU_scrType;
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output [162 : 0] specialRWALU;
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// signals for module outputs
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wire [162 : 0] specialRWALU;
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// remaining internal signals
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reg [65 : 0] IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d168;
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reg [63 : 0] IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35;
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reg [13 : 0] CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1;
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reg [4 : 0] CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3;
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reg [2 : 0] CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q5,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8;
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reg CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q2,
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CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4,
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CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q6;
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wire [71 : 0] IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_IF_ETC___d207;
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wire [65 : 0] IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d169,
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in__h1130,
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in__h393,
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res_capFat_address__h1799,
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x__h1148,
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x__h411,
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y__h1147,
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y__h410;
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wire [63 : 0] SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95,
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addBase__h1869,
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addBase__h2053,
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bot__h1872,
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bot__h2056,
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offsetAddr__h130,
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offsetAddr__h1389,
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offsetAddr__h696,
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offsetAddr__h992,
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oldOffset__h23,
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x__h1048,
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x__h1050,
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x__h1267,
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x__h1516,
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x__h284,
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x__h286,
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x__h565,
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x__h870,
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y__h767;
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wire [49 : 0] highOffsetBits__h1393,
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highOffsetBits__h700,
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mask__h1962,
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mask__h2146,
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signBits__h1390,
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signBits__h697,
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x__h1420,
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x__h727;
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wire [15 : 0] newAddrBits__h1671,
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newAddrBits__h1705,
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newAddrBits__h1739,
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newAddrBits__h1773,
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offset__h1036,
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offset__h272,
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x__h1926,
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x__h2110;
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wire [13 : 0] IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d192,
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d198,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d178,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d184,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d201,
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res_capFat_addrBits__h1800,
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toBoundsM1__h1403,
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toBoundsM1__h710,
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toBounds__h1402,
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toBounds__h709;
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wire [9 : 0] IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d282,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d284,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d283;
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wire [5 : 0] IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d281;
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wire [4 : 0] IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d265,
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d277;
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wire [3 : 0] IF_specialRWALU_oldCap_BITS_37_TO_35_11_ULT_sp_ETC___d225,
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IF_specialRWALU_oldCap_BITS_37_TO_35_11_ULT_sp_ETC___d239;
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wire [2 : 0] repBound__h2681, repBound__h2703;
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wire IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d56,
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IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d75,
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IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d116,
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IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d134,
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d255,
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d267,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d215,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d229,
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d63,
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d78,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d144,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d143,
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NOT_specialRWALU_cap_BITS_43_TO_38_8_ULT_50_18___d119,
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NOT_specialRWALU_oldCap_BITS_43_TO_38_3_ULT_50_8___d59,
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SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d123,
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SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d139,
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specialRWALU_cap_BITS_23_TO_21_43_ULT_specialR_ETC___d251,
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specialRWALU_cap_BITS_37_TO_35_47_ULT_specialR_ETC___d248,
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specialRWALU_oldCap_BITS_23_TO_21_09_ULT_speci_ETC___d213,
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specialRWALU_oldCap_BITS_37_TO_35_11_ULT_speci_ETC___d212;
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// value method specialRWALU
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assign specialRWALU =
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{ IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d144,
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res_capFat_address__h1799,
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res_capFat_addrBits__h1800,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_IF_ETC___d207,
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d284 } ;
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// remaining internal signals
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assign IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d56 =
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63] ?
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x__h565[13:0] >= toBounds__h709 :
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x__h565[13:0] <= toBoundsM1__h710 ;
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assign IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d75 =
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63] ?
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x__h870[13:0] >= toBounds__h709 :
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x__h870[13:0] <= toBoundsM1__h710 ;
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assign IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d281 =
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{ CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q2,
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CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3 } ;
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assign IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d282 =
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{ CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q5,
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CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q6,
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IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d281 } ;
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assign IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d116 =
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SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63] ?
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x__h1267[13:0] >= toBounds__h1402 :
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x__h1267[13:0] <= toBoundsM1__h1403 ;
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assign IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d134 =
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SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63] ?
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x__h1516[13:0] >= toBounds__h1402 :
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x__h1516[13:0] <= toBoundsM1__h1403 ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d192 =
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(specialRWALU_cap[43:38] == 6'd52) ?
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{ 1'b0, newAddrBits__h1739[12:0] } :
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newAddrBits__h1739[13:0] ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d198 =
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(specialRWALU_cap[43:38] == 6'd52) ?
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{ 1'b0, newAddrBits__h1773[12:0] } :
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newAddrBits__h1773[13:0] ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d255 =
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d192[13:11] <
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repBound__h2703 ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d265 =
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{ IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d255,
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(specialRWALU_cap_BITS_37_TO_35_47_ULT_specialR_ETC___d248 ==
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d255) ?
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2'd0 :
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((specialRWALU_cap_BITS_37_TO_35_47_ULT_specialR_ETC___d248 &&
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!IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d255) ?
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2'd1 :
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2'd3),
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(specialRWALU_cap_BITS_23_TO_21_43_ULT_specialR_ETC___d251 ==
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d255) ?
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2'd0 :
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((specialRWALU_cap_BITS_23_TO_21_43_ULT_specialR_ETC___d251 &&
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!IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d255) ?
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2'd1 :
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2'd3) } ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d267 =
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d198[13:11] <
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repBound__h2703 ;
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assign IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d277 =
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{ IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d267,
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(specialRWALU_cap_BITS_37_TO_35_47_ULT_specialR_ETC___d248 ==
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d267) ?
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2'd0 :
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((specialRWALU_cap_BITS_37_TO_35_47_ULT_specialR_ETC___d248 &&
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!IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d267) ?
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2'd1 :
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2'd3),
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(specialRWALU_cap_BITS_23_TO_21_43_ULT_specialR_ETC___d251 ==
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IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d267) ?
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2'd0 :
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((specialRWALU_cap_BITS_23_TO_21_43_ULT_specialR_ETC___d251 &&
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!IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d267) ?
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2'd1 :
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2'd3) } ;
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assign IF_specialRWALU_oldCap_BITS_37_TO_35_11_ULT_sp_ETC___d225 =
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{ (specialRWALU_oldCap_BITS_37_TO_35_11_ULT_speci_ETC___d212 ==
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d215) ?
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2'd0 :
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((specialRWALU_oldCap_BITS_37_TO_35_11_ULT_speci_ETC___d212 &&
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!IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d215) ?
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2'd1 :
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2'd3),
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(specialRWALU_oldCap_BITS_23_TO_21_09_ULT_speci_ETC___d213 ==
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d215) ?
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2'd0 :
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((specialRWALU_oldCap_BITS_23_TO_21_09_ULT_speci_ETC___d213 &&
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!IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d215) ?
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2'd1 :
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2'd3) } ;
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assign IF_specialRWALU_oldCap_BITS_37_TO_35_11_ULT_sp_ETC___d239 =
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{ (specialRWALU_oldCap_BITS_37_TO_35_11_ULT_speci_ETC___d212 ==
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d229) ?
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2'd0 :
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((specialRWALU_oldCap_BITS_37_TO_35_11_ULT_speci_ETC___d212 &&
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!IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d229) ?
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2'd1 :
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2'd3),
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(specialRWALU_oldCap_BITS_23_TO_21_09_ULT_speci_ETC___d213 ==
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d229) ?
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2'd0 :
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((specialRWALU_oldCap_BITS_23_TO_21_09_ULT_speci_ETC___d213 &&
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!IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d229) ?
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2'd1 :
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2'd3) } ;
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assign IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d178 =
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(specialRWALU_oldCap[43:38] == 6'd52) ?
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{ 1'b0, newAddrBits__h1671[12:0] } :
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newAddrBits__h1671[13:0] ;
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assign IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d184 =
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(specialRWALU_oldCap[43:38] == 6'd52) ?
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{ 1'b0, newAddrBits__h1705[12:0] } :
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newAddrBits__h1705[13:0] ;
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assign IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d215 =
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d178[13:11] <
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repBound__h2681 ;
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assign IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d229 =
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d184[13:11] <
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repBound__h2681 ;
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assign IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d63 =
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(highOffsetBits__h700 == 50'd0 &&
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IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d56 ||
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NOT_specialRWALU_oldCap_BITS_43_TO_38_3_ULT_50_8___d59) &&
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specialRWALU_oldCap[62:45] == 18'd262143 ;
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assign IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d78 =
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(highOffsetBits__h700 == 50'd0 &&
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IF_IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0__ETC___d75 ||
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NOT_specialRWALU_oldCap_BITS_43_TO_38_3_ULT_50_8___d59) &&
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specialRWALU_oldCap[62:45] == 18'd262143 ;
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assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_IF_ETC___d207 =
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(specialRWALU_scrType[4:2] == 3'd0 ||
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
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3'd0 ||
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specialRWALU_scrType[4:2] == 3'd1 ||
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
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3'd1) ?
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specialRWALU_oldCap[81:10] :
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specialRWALU_cap[81:10] ;
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assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d144 =
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(specialRWALU_scrType[4:2] == 3'd0 ||
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specialRWALU_scrType[4:2] != 3'd1 &&
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
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3'd0) ?
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IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d63 &&
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specialRWALU_oldCap[162] :
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d143 ;
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assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_0_OR_NO_ETC___d284 =
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(specialRWALU_scrType[4:2] == 3'd0 ||
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specialRWALU_scrType[4:2] != 3'd1 &&
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
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3'd0) ?
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{ repBound__h2681,
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specialRWALU_oldCap_BITS_37_TO_35_11_ULT_speci_ETC___d212,
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specialRWALU_oldCap_BITS_23_TO_21_09_ULT_speci_ETC___d213,
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IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d215,
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IF_specialRWALU_oldCap_BITS_37_TO_35_11_ULT_sp_ETC___d225 } :
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IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d283 ;
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assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d143 =
|
|
(specialRWALU_scrType[4:2] == 3'd1 ||
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd1) ?
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d78 &&
|
|
specialRWALU_oldCap[162] :
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4 ;
|
|
assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d169 =
|
|
(specialRWALU_scrType[4:2] == 3'd1 ||
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd1) ?
|
|
{ 2'd0, bot__h1872 } + { 2'd0, offsetAddr__h696 } :
|
|
IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d168 ;
|
|
assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d201 =
|
|
(specialRWALU_scrType[4:2] == 3'd1 ||
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd1) ?
|
|
IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d184 :
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1 ;
|
|
assign IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d283 =
|
|
(specialRWALU_scrType[4:2] == 3'd1 ||
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd1) ?
|
|
{ repBound__h2681,
|
|
specialRWALU_oldCap_BITS_37_TO_35_11_ULT_speci_ETC___d212,
|
|
specialRWALU_oldCap_BITS_23_TO_21_09_ULT_speci_ETC___d213,
|
|
IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d229,
|
|
IF_specialRWALU_oldCap_BITS_37_TO_35_11_ULT_sp_ETC___d239 } :
|
|
IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d282 ;
|
|
assign NOT_specialRWALU_cap_BITS_43_TO_38_8_ULT_50_18___d119 =
|
|
specialRWALU_cap[43:38] >= 6'd50 ;
|
|
assign NOT_specialRWALU_oldCap_BITS_43_TO_38_3_ULT_50_8___d59 =
|
|
specialRWALU_oldCap[43:38] >= 6'd50 ;
|
|
assign SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d123 =
|
|
(highOffsetBits__h1393 == 50'd0 &&
|
|
IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d116 ||
|
|
NOT_specialRWALU_cap_BITS_43_TO_38_8_ULT_50_18___d119) &&
|
|
specialRWALU_cap[62:45] == 18'd262143 ;
|
|
assign SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d139 =
|
|
(highOffsetBits__h1393 == 50'd0 &&
|
|
IF_SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO__ETC___d134 ||
|
|
NOT_specialRWALU_cap_BITS_43_TO_38_8_ULT_50_18___d119) &&
|
|
(specialRWALU_cap[62:45] == 18'd262143 ||
|
|
!SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[0]) ;
|
|
assign SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95 =
|
|
x__h1048 | in__h1130[63:0] ;
|
|
assign addBase__h1869 =
|
|
{ {48{x__h1926[15]}}, x__h1926 } << specialRWALU_oldCap[43:38] ;
|
|
assign addBase__h2053 =
|
|
{ {48{x__h2110[15]}}, x__h2110 } << specialRWALU_cap[43:38] ;
|
|
assign bot__h1872 =
|
|
{ specialRWALU_oldCap[159:110] & mask__h1962, 14'd0 } +
|
|
addBase__h1869 ;
|
|
assign bot__h2056 =
|
|
{ specialRWALU_cap[159:110] & mask__h2146, 14'd0 } +
|
|
addBase__h2053 ;
|
|
assign highOffsetBits__h1393 = x__h1420 & mask__h2146 ;
|
|
assign highOffsetBits__h700 = x__h727 & mask__h1962 ;
|
|
assign in__h1130 = specialRWALU_cap[161:96] & y__h1147 ;
|
|
assign in__h393 = specialRWALU_oldCap[161:96] & y__h410 ;
|
|
assign mask__h1962 = 50'h3FFFFFFFFFFFF << specialRWALU_oldCap[43:38] ;
|
|
assign mask__h2146 = 50'h3FFFFFFFFFFFF << specialRWALU_cap[43:38] ;
|
|
assign newAddrBits__h1671 =
|
|
{ 2'd0, specialRWALU_oldCap[23:10] } + { 2'd0, x__h565[13:0] } ;
|
|
assign newAddrBits__h1705 =
|
|
{ 2'd0, specialRWALU_oldCap[23:10] } + { 2'd0, x__h870[13:0] } ;
|
|
assign newAddrBits__h1739 =
|
|
{ 2'd0, specialRWALU_cap[23:10] } + { 2'd0, x__h1267[13:0] } ;
|
|
assign newAddrBits__h1773 =
|
|
{ 2'd0, specialRWALU_cap[23:10] } + { 2'd0, x__h1516[13:0] } ;
|
|
assign offsetAddr__h130 =
|
|
{ IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63:2],
|
|
1'd0,
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[0] } ;
|
|
assign offsetAddr__h1389 =
|
|
{ SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63:1],
|
|
1'd0 } ;
|
|
assign offsetAddr__h696 =
|
|
{ IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63:1],
|
|
1'd0 } ;
|
|
assign offsetAddr__h992 =
|
|
{ SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63:2],
|
|
1'd0,
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[0] } ;
|
|
assign offset__h1036 = { 2'd0, specialRWALU_cap[95:82] } - x__h2110 ;
|
|
assign offset__h272 = { 2'd0, specialRWALU_oldCap[95:82] } - x__h1926 ;
|
|
assign oldOffset__h23 = x__h284 | in__h393[63:0] ;
|
|
assign repBound__h2681 = specialRWALU_oldCap[23:21] - 3'b001 ;
|
|
assign repBound__h2703 = specialRWALU_cap[23:21] - 3'b001 ;
|
|
assign res_capFat_addrBits__h1800 =
|
|
(specialRWALU_scrType[4:2] == 3'd0 ||
|
|
specialRWALU_scrType[4:2] != 3'd1 &&
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd0) ?
|
|
IF_specialRWALU_oldCap_BITS_43_TO_38_3_EQ_52_7_ETC___d178 :
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d201 ;
|
|
assign res_capFat_address__h1799 =
|
|
(specialRWALU_scrType[4:2] == 3'd0 ||
|
|
specialRWALU_scrType[4:2] != 3'd1 &&
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 ==
|
|
3'd0) ?
|
|
{ 2'd0, bot__h1872 } + { 2'd0, offsetAddr__h130 } :
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_1_OR_IF_ETC___d169 ;
|
|
assign signBits__h1390 =
|
|
{50{SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63]}} ;
|
|
assign signBits__h697 =
|
|
{50{IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63]}} ;
|
|
assign specialRWALU_cap_BITS_23_TO_21_43_ULT_specialR_ETC___d251 =
|
|
specialRWALU_cap[23:21] < repBound__h2703 ;
|
|
assign specialRWALU_cap_BITS_37_TO_35_47_ULT_specialR_ETC___d248 =
|
|
specialRWALU_cap[37:35] < repBound__h2703 ;
|
|
assign specialRWALU_oldCap_BITS_23_TO_21_09_ULT_speci_ETC___d213 =
|
|
specialRWALU_oldCap[23:21] < repBound__h2681 ;
|
|
assign specialRWALU_oldCap_BITS_37_TO_35_11_ULT_speci_ETC___d212 =
|
|
specialRWALU_oldCap[37:35] < repBound__h2681 ;
|
|
assign toBoundsM1__h1403 = { 3'b110, ~specialRWALU_cap[20:10] } ;
|
|
assign toBoundsM1__h710 = { 3'b110, ~specialRWALU_oldCap[20:10] } ;
|
|
assign toBounds__h1402 = 14'd14336 - { 3'b0, specialRWALU_cap[20:10] } ;
|
|
assign toBounds__h709 = 14'd14336 - { 3'b0, specialRWALU_oldCap[20:10] } ;
|
|
assign x__h1048 = x__h1050 << specialRWALU_cap[43:38] ;
|
|
assign x__h1050 = { {48{offset__h1036[15]}}, offset__h1036 } ;
|
|
assign x__h1148 = 66'h3FFFFFFFFFFFFFFFF << specialRWALU_cap[43:38] ;
|
|
assign x__h1267 = offsetAddr__h992 >> specialRWALU_cap[43:38] ;
|
|
assign x__h1420 =
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d95[63:14] ^
|
|
signBits__h1390 ;
|
|
assign x__h1516 = offsetAddr__h1389 >> specialRWALU_cap[43:38] ;
|
|
assign x__h1926 = { specialRWALU_oldCap[1:0], specialRWALU_oldCap[23:10] } ;
|
|
assign x__h2110 = { specialRWALU_cap[1:0], specialRWALU_cap[23:10] } ;
|
|
assign x__h284 = x__h286 << specialRWALU_oldCap[43:38] ;
|
|
assign x__h286 = { {48{offset__h272[15]}}, offset__h272 } ;
|
|
assign x__h411 = 66'h3FFFFFFFFFFFFFFFF << specialRWALU_oldCap[43:38] ;
|
|
assign x__h565 = offsetAddr__h130 >> specialRWALU_oldCap[43:38] ;
|
|
assign x__h727 =
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35[63:14] ^
|
|
signBits__h697 ;
|
|
assign x__h870 = offsetAddr__h696 >> specialRWALU_oldCap[43:38] ;
|
|
assign y__h1147 = ~x__h1148 ;
|
|
assign y__h410 = ~x__h411 ;
|
|
assign y__h767 = ~specialRWALU_cap[159:96] ;
|
|
always@(specialRWALU_scrType)
|
|
begin
|
|
case (specialRWALU_scrType[4:2])
|
|
3'd2, 3'd3:
|
|
IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 =
|
|
specialRWALU_scrType[4:2];
|
|
default: IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 = 3'd4;
|
|
endcase
|
|
end
|
|
always@(specialRWALU_scrType or
|
|
oldOffset__h23 or y__h767 or specialRWALU_cap)
|
|
begin
|
|
case (specialRWALU_scrType[1:0])
|
|
2'd0:
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35 =
|
|
specialRWALU_cap[159:96];
|
|
2'd1:
|
|
IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35 =
|
|
oldOffset__h23 | specialRWALU_cap[159:96];
|
|
default: IF_specialRWALU_scrType_BITS_1_TO_0_2_EQ_0_3_T_ETC___d35 =
|
|
oldOffset__h23 & y__h767;
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
bot__h2056 or offsetAddr__h992 or offsetAddr__h1389)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2:
|
|
IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d168 =
|
|
{ 2'd0, bot__h2056 } + { 2'd0, offsetAddr__h992 };
|
|
3'd3:
|
|
IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d168 =
|
|
{ 2'd0, bot__h2056 } + { 2'd0, offsetAddr__h1389 };
|
|
default: IF_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_ETC___d168 =
|
|
specialRWALU_cap[161:96];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d192 or
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d198)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1 =
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d192;
|
|
3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1 =
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d198;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q1 =
|
|
specialRWALU_cap[95:82];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
specialRWALU_cap_BITS_23_TO_21_43_ULT_specialR_ETC___d251)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2, 3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q2 =
|
|
specialRWALU_cap_BITS_23_TO_21_43_ULT_specialR_ETC___d251;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q2 =
|
|
specialRWALU_cap[5];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d265 or
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d277)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3 =
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d265;
|
|
3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3 =
|
|
IF_specialRWALU_cap_BITS_43_TO_38_8_EQ_52_85_T_ETC___d277;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q3 =
|
|
specialRWALU_cap[4:0];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d123 or
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d139)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4 =
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d123 &&
|
|
specialRWALU_cap[162];
|
|
3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4 =
|
|
SEXT__0_CONCAT_specialRWALU_cap_BITS_95_TO_82__ETC___d139 &&
|
|
specialRWALU_cap[162];
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q4 =
|
|
specialRWALU_cap[162];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or repBound__h2703)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2, 3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q5 =
|
|
repBound__h2703;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q5 =
|
|
specialRWALU_cap[9:7];
|
|
endcase
|
|
end
|
|
always@(IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8 or
|
|
specialRWALU_cap or
|
|
specialRWALU_cap_BITS_37_TO_35_47_ULT_specialR_ETC___d248)
|
|
begin
|
|
case (IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2_OR_sp_ETC___d8)
|
|
3'd2, 3'd3:
|
|
CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q6 =
|
|
specialRWALU_cap_BITS_37_TO_35_47_ULT_specialR_ETC___d248;
|
|
default: CASE_IF_specialRWALU_scrType_BITS_4_TO_2_EQ_2__ETC__q6 =
|
|
specialRWALU_cap[6];
|
|
endcase
|
|
end
|
|
endmodule // module_specialRWALU
|
|
|