131 lines
4.0 KiB
Verilog
131 lines
4.0 KiB
Verilog
// Copyright (c) 2000-2013 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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//
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// Transfer takes 2 dCLK to see data,
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// sRDY recovers takes 2 dCLK + 2 sCLK
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module SyncHandshake(
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sCLK,
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sRST,
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dCLK,
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sEN,
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sRDY,
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dPulse
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);
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parameter init = 1'b0;
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parameter delayreturn = 1'b0;
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// Source clock port signal
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input sCLK ;
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input sRST ;
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input sEN ;
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output sRDY ;
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// Destination clock port signal
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input dCLK ;
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output dPulse ;
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// Flops to hold data
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reg dSyncReg1, dSyncReg2 ;
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reg dLastState ;
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reg sToggleReg ;
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reg sSyncReg1, sSyncReg2 ;
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// Output signal
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assign dPulse = dSyncReg2 != dLastState ;
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assign sRDY = sSyncReg2 == sToggleReg;
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wire ackValue = delayreturn ? dLastState : dSyncReg2 ;
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always @(posedge sCLK or `BSV_RESET_EDGE sRST)
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begin
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if (sRST == `BSV_RESET_VALUE)
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begin
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sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ! init ; // Reset hi so sRDY is low during reset
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sSyncReg2 <= `BSV_ASSIGNMENT_DELAY ! init ;
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sToggleReg <= `BSV_ASSIGNMENT_DELAY init ;
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end
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else
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begin
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// hadshake return synchronizer
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sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ackValue ;// clock domain crossing
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sSyncReg2 <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;
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// Pulse send
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if ( sEN )
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begin
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sToggleReg <= `BSV_ASSIGNMENT_DELAY ! sToggleReg ;
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end // if ( sEN )
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end
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end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
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always @(posedge dCLK or `BSV_RESET_EDGE sRST)
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begin
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if (sRST == `BSV_RESET_VALUE)
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begin
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dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init;
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dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init;
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dLastState <= `BSV_ASSIGNMENT_DELAY init ;
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end
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else
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begin
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dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sToggleReg ;// domain crossing
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dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
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dLastState <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;
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end
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end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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// synopsys translate_off
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initial
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begin
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dSyncReg1 = init ;
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dSyncReg2 = init ;
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dLastState = init ;
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sToggleReg = init ;
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sSyncReg1 = ! init ;
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sSyncReg2 = ! init ;
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end // initial begin
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// synopsys translate_on
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`endif // BSV_NO_INITIAL_BLOCKS
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endmodule // HandshakeSync
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