113f888d37
New method 'debug_external_interrupt_req' to support emulation of a debug module starts at P3_Core interface and is plumbed all the way in to the CSR register MIP as interrupt [14]. The corresponding MIE[14] is always 1, so it is never masked. Still todo: should not be masked by MSTATUS interrupt-enables either. Also expanded interrupt-detection logic, mcause etc. to extend up to interrupt 14. Builds in standalone mode, runs ISA tests. Builds in src_SSITH_P3, generating RTL.
103 lines
2.6 KiB
Verilog
103 lines
2.6 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_request_put O 1 reg
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// response_get O 69 reg
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// RDY_response_get O 1 reg
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// CLK I 1 clock
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// RST_N I 1 reset
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// request_put I 131
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// EN_request_put I 1
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// EN_response_get I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDoubleDiv(CLK,
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RST_N,
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request_put,
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EN_request_put,
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RDY_request_put,
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EN_response_get,
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response_get,
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RDY_response_get);
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input CLK;
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input RST_N;
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// action method request_put
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input [130 : 0] request_put;
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input EN_request_put;
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output RDY_request_put;
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// actionvalue method response_get
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input EN_response_get;
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output [68 : 0] response_get;
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output RDY_response_get;
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// signals for module outputs
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wire [68 : 0] response_get;
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wire RDY_request_put, RDY_response_get;
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// ports of submodule fpu
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wire [130 : 0] fpu$request_put;
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wire [68 : 0] fpu$response_get;
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wire fpu$EN_request_put,
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fpu$EN_response_get,
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fpu$RDY_request_put,
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fpu$RDY_response_get;
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// rule scheduling signals
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wire CAN_FIRE_request_put,
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CAN_FIRE_response_get,
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WILL_FIRE_request_put,
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WILL_FIRE_response_get;
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// action method request_put
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assign RDY_request_put = fpu$RDY_request_put ;
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assign CAN_FIRE_request_put = fpu$RDY_request_put ;
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assign WILL_FIRE_request_put = EN_request_put ;
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// actionvalue method response_get
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assign response_get = fpu$response_get ;
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assign RDY_response_get = fpu$RDY_response_get ;
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assign CAN_FIRE_response_get = fpu$RDY_response_get ;
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assign WILL_FIRE_response_get = EN_response_get ;
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// submodule fpu
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mkXilinxFpDiv fpu(.CLK(CLK),
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.RST_N(RST_N),
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.request_put(fpu$request_put),
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.EN_request_put(fpu$EN_request_put),
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.EN_response_get(fpu$EN_response_get),
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.RDY_request_put(fpu$RDY_request_put),
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.response_get(fpu$response_get),
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.RDY_response_get(fpu$RDY_response_get));
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// submodule fpu
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assign fpu$request_put = request_put ;
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assign fpu$EN_request_put = EN_request_put ;
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assign fpu$EN_response_get = EN_response_get ;
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endmodule // mkDoubleDiv
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