Cheri-research/Toooba
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Toooba/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v
rsnikhil 113f888d37 Added support for 'debug_external_interrupt_req' 
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00

4881 lines
182 KiB
Verilog
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//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// getEmptyEntryInit O 3 reg
// RDY_getEmptyEntryInit O 1
// RDY_sendRsToC_releaseEntry O 1
// sendRsToC_getResult O 67
// RDY_sendRsToC_getResult O 1 const
// sendRsToP_cRq_getRq O 64
// RDY_sendRsToP_cRq_getRq O 1 const
// sendRsToP_cRq_getSlot O 56
// RDY_sendRsToP_cRq_getSlot O 1 const
// sendRqToP_getRq O 64
// RDY_sendRqToP_getRq O 1 const
// sendRqToP_getSlot O 56
// RDY_sendRqToP_getSlot O 1 const
// pipelineResp_getState O 3
// RDY_pipelineResp_getState O 1 const
// pipelineResp_getRq O 64
// RDY_pipelineResp_getRq O 1 const
// pipelineResp_getSlot O 56
// RDY_pipelineResp_getSlot O 1 const
// RDY_pipelineResp_setResult O 1 const
// RDY_pipelineResp_setStateSlot O 1 const
// pipelineResp_getSucc O 4
// RDY_pipelineResp_getSucc O 1 const
// RDY_pipelineResp_setSucc O 1 const
// pipelineResp_searchEndOfChain O 4
// RDY_pipelineResp_searchEndOfChain O 1 const
// emptyForFlush O 1
// RDY_emptyForFlush O 1 const
// stuck_get O 68 const
// RDY_stuck_get O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// getEmptyEntryInit_r I 64
// sendRsToC_releaseEntry_n I 3
// sendRsToC_getResult_n I 3
// sendRsToP_cRq_getRq_n I 3
// sendRsToP_cRq_getSlot_n I 3
// sendRqToP_getRq_n I 3
// sendRqToP_getSlot_n I 3
// pipelineResp_getState_n I 3
// pipelineResp_getRq_n I 3
// pipelineResp_getSlot_n I 3
// pipelineResp_setResult_n I 3
// pipelineResp_setResult_r I 66
// pipelineResp_setStateSlot_n I 3
// pipelineResp_setStateSlot_state I 3
// pipelineResp_setStateSlot_slot I 56
// pipelineResp_getSucc_n I 3
// pipelineResp_setSucc_n I 3
// pipelineResp_setSucc_succ I 4
// pipelineResp_searchEndOfChain_addr I 64
// EN_sendRsToC_releaseEntry I 1
// EN_pipelineResp_setResult I 1
// EN_pipelineResp_setStateSlot I 1
// EN_pipelineResp_setSucc I 1
// EN_getEmptyEntryInit I 1
// EN_stuck_get I 1 unused
//
// Combinational paths from inputs to outputs:
// (sendRsToC_getResult_n,
// pipelineResp_setResult_n,
// pipelineResp_setResult_r,
// EN_pipelineResp_setResult) -> sendRsToC_getResult
// sendRsToP_cRq_getRq_n -> sendRsToP_cRq_getRq
// sendRsToP_cRq_getSlot_n -> sendRsToP_cRq_getSlot
// sendRqToP_getRq_n -> sendRqToP_getRq
// sendRqToP_getSlot_n -> sendRqToP_getSlot
// pipelineResp_getState_n -> pipelineResp_getState
// pipelineResp_getRq_n -> pipelineResp_getRq
// pipelineResp_getSlot_n -> pipelineResp_getSlot
// pipelineResp_getSucc_n -> pipelineResp_getSucc
// pipelineResp_searchEndOfChain_addr -> pipelineResp_searchEndOfChain
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkICRqMshrWrapper(CLK,
RST_N,
getEmptyEntryInit_r,
EN_getEmptyEntryInit,
getEmptyEntryInit,
RDY_getEmptyEntryInit,
sendRsToC_releaseEntry_n,
EN_sendRsToC_releaseEntry,
RDY_sendRsToC_releaseEntry,
sendRsToC_getResult_n,
sendRsToC_getResult,
RDY_sendRsToC_getResult,
sendRsToP_cRq_getRq_n,
sendRsToP_cRq_getRq,
RDY_sendRsToP_cRq_getRq,
sendRsToP_cRq_getSlot_n,
sendRsToP_cRq_getSlot,
RDY_sendRsToP_cRq_getSlot,
sendRqToP_getRq_n,
sendRqToP_getRq,
RDY_sendRqToP_getRq,
sendRqToP_getSlot_n,
sendRqToP_getSlot,
RDY_sendRqToP_getSlot,
pipelineResp_getState_n,
pipelineResp_getState,
RDY_pipelineResp_getState,
pipelineResp_getRq_n,
pipelineResp_getRq,
RDY_pipelineResp_getRq,
pipelineResp_getSlot_n,
pipelineResp_getSlot,
RDY_pipelineResp_getSlot,
pipelineResp_setResult_n,
pipelineResp_setResult_r,
EN_pipelineResp_setResult,
RDY_pipelineResp_setResult,
pipelineResp_setStateSlot_n,
pipelineResp_setStateSlot_state,
pipelineResp_setStateSlot_slot,
EN_pipelineResp_setStateSlot,
RDY_pipelineResp_setStateSlot,
pipelineResp_getSucc_n,
pipelineResp_getSucc,
RDY_pipelineResp_getSucc,
pipelineResp_setSucc_n,
pipelineResp_setSucc_succ,
EN_pipelineResp_setSucc,
RDY_pipelineResp_setSucc,
pipelineResp_searchEndOfChain_addr,
pipelineResp_searchEndOfChain,
RDY_pipelineResp_searchEndOfChain,
emptyForFlush,
RDY_emptyForFlush,
EN_stuck_get,
stuck_get,
RDY_stuck_get);
input CLK;
input RST_N;
// actionvalue method getEmptyEntryInit
input [63 : 0] getEmptyEntryInit_r;
input EN_getEmptyEntryInit;
output [2 : 0] getEmptyEntryInit;
output RDY_getEmptyEntryInit;
// action method sendRsToC_releaseEntry
input [2 : 0] sendRsToC_releaseEntry_n;
input EN_sendRsToC_releaseEntry;
output RDY_sendRsToC_releaseEntry;
// value method sendRsToC_getResult
input [2 : 0] sendRsToC_getResult_n;
output [66 : 0] sendRsToC_getResult;
output RDY_sendRsToC_getResult;
// value method sendRsToP_cRq_getRq
input [2 : 0] sendRsToP_cRq_getRq_n;
output [63 : 0] sendRsToP_cRq_getRq;
output RDY_sendRsToP_cRq_getRq;
// value method sendRsToP_cRq_getSlot
input [2 : 0] sendRsToP_cRq_getSlot_n;
output [55 : 0] sendRsToP_cRq_getSlot;
output RDY_sendRsToP_cRq_getSlot;
// value method sendRqToP_getRq
input [2 : 0] sendRqToP_getRq_n;
output [63 : 0] sendRqToP_getRq;
output RDY_sendRqToP_getRq;
// value method sendRqToP_getSlot
input [2 : 0] sendRqToP_getSlot_n;
output [55 : 0] sendRqToP_getSlot;
output RDY_sendRqToP_getSlot;
// value method pipelineResp_getState
input [2 : 0] pipelineResp_getState_n;
output [2 : 0] pipelineResp_getState;
output RDY_pipelineResp_getState;
// value method pipelineResp_getRq
input [2 : 0] pipelineResp_getRq_n;
output [63 : 0] pipelineResp_getRq;
output RDY_pipelineResp_getRq;
// value method pipelineResp_getSlot
input [2 : 0] pipelineResp_getSlot_n;
output [55 : 0] pipelineResp_getSlot;
output RDY_pipelineResp_getSlot;
// action method pipelineResp_setResult
input [2 : 0] pipelineResp_setResult_n;
input [65 : 0] pipelineResp_setResult_r;
input EN_pipelineResp_setResult;
output RDY_pipelineResp_setResult;
// action method pipelineResp_setStateSlot
input [2 : 0] pipelineResp_setStateSlot_n;
input [2 : 0] pipelineResp_setStateSlot_state;
input [55 : 0] pipelineResp_setStateSlot_slot;
input EN_pipelineResp_setStateSlot;
output RDY_pipelineResp_setStateSlot;
// value method pipelineResp_getSucc
input [2 : 0] pipelineResp_getSucc_n;
output [3 : 0] pipelineResp_getSucc;
output RDY_pipelineResp_getSucc;
// action method pipelineResp_setSucc
input [2 : 0] pipelineResp_setSucc_n;
input [3 : 0] pipelineResp_setSucc_succ;
input EN_pipelineResp_setSucc;
output RDY_pipelineResp_setSucc;
// value method pipelineResp_searchEndOfChain
input [63 : 0] pipelineResp_searchEndOfChain_addr;
output [3 : 0] pipelineResp_searchEndOfChain;
output RDY_pipelineResp_searchEndOfChain;
// value method emptyForFlush
output emptyForFlush;
output RDY_emptyForFlush;
// actionvalue method stuck_get
input EN_stuck_get;
output [67 : 0] stuck_get;
output RDY_stuck_get;
// signals for module outputs
reg [63 : 0] pipelineResp_getRq, sendRqToP_getRq, sendRsToP_cRq_getRq;
reg [2 : 0] pipelineResp_getState;
wire [67 : 0] stuck_get;
wire [66 : 0] sendRsToC_getResult;
wire [55 : 0] pipelineResp_getSlot,
sendRqToP_getSlot,
sendRsToP_cRq_getSlot;
wire [3 : 0] pipelineResp_getSucc, pipelineResp_searchEndOfChain;
wire [2 : 0] getEmptyEntryInit;
wire RDY_emptyForFlush,
RDY_getEmptyEntryInit,
RDY_pipelineResp_getRq,
RDY_pipelineResp_getSlot,
RDY_pipelineResp_getState,
RDY_pipelineResp_getSucc,
RDY_pipelineResp_searchEndOfChain,
RDY_pipelineResp_setResult,
RDY_pipelineResp_setStateSlot,
RDY_pipelineResp_setSucc,
RDY_sendRqToP_getRq,
RDY_sendRqToP_getSlot,
RDY_sendRsToC_getResult,
RDY_sendRsToC_releaseEntry,
RDY_sendRsToP_cRq_getRq,
RDY_sendRsToP_cRq_getSlot,
RDY_stuck_get,
emptyForFlush;
// inlined wires
wire [66 : 0] m_m_resultVec_0_lat_0$wget;
wire m_m_resultVec_0_lat_0$whas,
m_m_resultVec_1_lat_0$whas,
m_m_resultVec_2_lat_0$whas,
m_m_resultVec_3_lat_0$whas,
m_m_resultVec_4_lat_0$whas,
m_m_resultVec_5_lat_0$whas,
m_m_resultVec_6_lat_0$whas,
m_m_resultVec_7_lat_0$whas,
m_m_stateVec_0_lat_0$whas,
m_m_stateVec_0_lat_1$whas,
m_m_stateVec_0_lat_2$whas,
m_m_stateVec_1_lat_0$whas,
m_m_stateVec_1_lat_1$whas,
m_m_stateVec_1_lat_2$whas,
m_m_stateVec_2_lat_0$whas,
m_m_stateVec_2_lat_1$whas,
m_m_stateVec_2_lat_2$whas,
m_m_stateVec_3_lat_0$whas,
m_m_stateVec_3_lat_1$whas,
m_m_stateVec_3_lat_2$whas,
m_m_stateVec_4_dummy_1_0$wget,
m_m_stateVec_4_lat_1$whas,
m_m_stateVec_4_lat_2$whas,
m_m_stateVec_5_lat_0$whas,
m_m_stateVec_5_lat_1$whas,
m_m_stateVec_5_lat_2$whas,
m_m_stateVec_6_lat_0$whas,
m_m_stateVec_6_lat_1$whas,
m_m_stateVec_6_lat_2$whas,
m_m_stateVec_7_lat_0$whas,
m_m_stateVec_7_lat_1$whas,
m_m_stateVec_7_lat_2$whas,
m_m_succValidVec_0_lat_0$whas,
m_m_succValidVec_1_lat_0$whas,
m_m_succValidVec_2_lat_0$whas,
m_m_succValidVec_3_lat_0$whas,
m_m_succValidVec_4_lat_0$whas,
m_m_succValidVec_5_lat_0$whas,
m_m_succValidVec_6_lat_0$whas,
m_m_succValidVec_7_lat_0$whas;
// register m_m_initIdx
reg [2 : 0] m_m_initIdx;
wire [2 : 0] m_m_initIdx$D_IN;
wire m_m_initIdx$EN;
// register m_m_inited
reg m_m_inited;
wire m_m_inited$D_IN, m_m_inited$EN;
// register m_m_reqVec_0_rl
reg [63 : 0] m_m_reqVec_0_rl;
wire [63 : 0] m_m_reqVec_0_rl$D_IN;
wire m_m_reqVec_0_rl$EN;
// register m_m_reqVec_1_rl
reg [63 : 0] m_m_reqVec_1_rl;
wire [63 : 0] m_m_reqVec_1_rl$D_IN;
wire m_m_reqVec_1_rl$EN;
// register m_m_reqVec_2_rl
reg [63 : 0] m_m_reqVec_2_rl;
wire [63 : 0] m_m_reqVec_2_rl$D_IN;
wire m_m_reqVec_2_rl$EN;
// register m_m_reqVec_3_rl
reg [63 : 0] m_m_reqVec_3_rl;
wire [63 : 0] m_m_reqVec_3_rl$D_IN;
wire m_m_reqVec_3_rl$EN;
// register m_m_reqVec_4_rl
reg [63 : 0] m_m_reqVec_4_rl;
wire [63 : 0] m_m_reqVec_4_rl$D_IN;
wire m_m_reqVec_4_rl$EN;
// register m_m_reqVec_5_rl
reg [63 : 0] m_m_reqVec_5_rl;
wire [63 : 0] m_m_reqVec_5_rl$D_IN;
wire m_m_reqVec_5_rl$EN;
// register m_m_reqVec_6_rl
reg [63 : 0] m_m_reqVec_6_rl;
wire [63 : 0] m_m_reqVec_6_rl$D_IN;
wire m_m_reqVec_6_rl$EN;
// register m_m_reqVec_7_rl
reg [63 : 0] m_m_reqVec_7_rl;
wire [63 : 0] m_m_reqVec_7_rl$D_IN;
wire m_m_reqVec_7_rl$EN;
// register m_m_resultVec_0_rl
reg [66 : 0] m_m_resultVec_0_rl;
wire [66 : 0] m_m_resultVec_0_rl$D_IN;
wire m_m_resultVec_0_rl$EN;
// register m_m_resultVec_1_rl
reg [66 : 0] m_m_resultVec_1_rl;
wire [66 : 0] m_m_resultVec_1_rl$D_IN;
wire m_m_resultVec_1_rl$EN;
// register m_m_resultVec_2_rl
reg [66 : 0] m_m_resultVec_2_rl;
wire [66 : 0] m_m_resultVec_2_rl$D_IN;
wire m_m_resultVec_2_rl$EN;
// register m_m_resultVec_3_rl
reg [66 : 0] m_m_resultVec_3_rl;
wire [66 : 0] m_m_resultVec_3_rl$D_IN;
wire m_m_resultVec_3_rl$EN;
// register m_m_resultVec_4_rl
reg [66 : 0] m_m_resultVec_4_rl;
wire [66 : 0] m_m_resultVec_4_rl$D_IN;
wire m_m_resultVec_4_rl$EN;
// register m_m_resultVec_5_rl
reg [66 : 0] m_m_resultVec_5_rl;
wire [66 : 0] m_m_resultVec_5_rl$D_IN;
wire m_m_resultVec_5_rl$EN;
// register m_m_resultVec_6_rl
reg [66 : 0] m_m_resultVec_6_rl;
wire [66 : 0] m_m_resultVec_6_rl$D_IN;
wire m_m_resultVec_6_rl$EN;
// register m_m_resultVec_7_rl
reg [66 : 0] m_m_resultVec_7_rl;
wire [66 : 0] m_m_resultVec_7_rl$D_IN;
wire m_m_resultVec_7_rl$EN;
// register m_m_slotVec_0_rl
reg [55 : 0] m_m_slotVec_0_rl;
wire [55 : 0] m_m_slotVec_0_rl$D_IN;
wire m_m_slotVec_0_rl$EN;
// register m_m_slotVec_1_rl
reg [55 : 0] m_m_slotVec_1_rl;
wire [55 : 0] m_m_slotVec_1_rl$D_IN;
wire m_m_slotVec_1_rl$EN;
// register m_m_slotVec_2_rl
reg [55 : 0] m_m_slotVec_2_rl;
wire [55 : 0] m_m_slotVec_2_rl$D_IN;
wire m_m_slotVec_2_rl$EN;
// register m_m_slotVec_3_rl
reg [55 : 0] m_m_slotVec_3_rl;
wire [55 : 0] m_m_slotVec_3_rl$D_IN;
wire m_m_slotVec_3_rl$EN;
// register m_m_slotVec_4_rl
reg [55 : 0] m_m_slotVec_4_rl;
wire [55 : 0] m_m_slotVec_4_rl$D_IN;
wire m_m_slotVec_4_rl$EN;
// register m_m_slotVec_5_rl
reg [55 : 0] m_m_slotVec_5_rl;
wire [55 : 0] m_m_slotVec_5_rl$D_IN;
wire m_m_slotVec_5_rl$EN;
// register m_m_slotVec_6_rl
reg [55 : 0] m_m_slotVec_6_rl;
wire [55 : 0] m_m_slotVec_6_rl$D_IN;
wire m_m_slotVec_6_rl$EN;
// register m_m_slotVec_7_rl
reg [55 : 0] m_m_slotVec_7_rl;
wire [55 : 0] m_m_slotVec_7_rl$D_IN;
wire m_m_slotVec_7_rl$EN;
// register m_m_stateVec_0_rl
reg [2 : 0] m_m_stateVec_0_rl;
wire [2 : 0] m_m_stateVec_0_rl$D_IN;
wire m_m_stateVec_0_rl$EN;
// register m_m_stateVec_1_rl
reg [2 : 0] m_m_stateVec_1_rl;
wire [2 : 0] m_m_stateVec_1_rl$D_IN;
wire m_m_stateVec_1_rl$EN;
// register m_m_stateVec_2_rl
reg [2 : 0] m_m_stateVec_2_rl;
wire [2 : 0] m_m_stateVec_2_rl$D_IN;
wire m_m_stateVec_2_rl$EN;
// register m_m_stateVec_3_rl
reg [2 : 0] m_m_stateVec_3_rl;
wire [2 : 0] m_m_stateVec_3_rl$D_IN;
wire m_m_stateVec_3_rl$EN;
// register m_m_stateVec_4_rl
reg [2 : 0] m_m_stateVec_4_rl;
wire [2 : 0] m_m_stateVec_4_rl$D_IN;
wire m_m_stateVec_4_rl$EN;
// register m_m_stateVec_5_rl
reg [2 : 0] m_m_stateVec_5_rl;
wire [2 : 0] m_m_stateVec_5_rl$D_IN;
wire m_m_stateVec_5_rl$EN;
// register m_m_stateVec_6_rl
reg [2 : 0] m_m_stateVec_6_rl;
wire [2 : 0] m_m_stateVec_6_rl$D_IN;
wire m_m_stateVec_6_rl$EN;
// register m_m_stateVec_7_rl
reg [2 : 0] m_m_stateVec_7_rl;
wire [2 : 0] m_m_stateVec_7_rl$D_IN;
wire m_m_stateVec_7_rl$EN;
// register m_m_succValidVec_0_rl
reg m_m_succValidVec_0_rl;
wire m_m_succValidVec_0_rl$D_IN, m_m_succValidVec_0_rl$EN;
// register m_m_succValidVec_1_rl
reg m_m_succValidVec_1_rl;
wire m_m_succValidVec_1_rl$D_IN, m_m_succValidVec_1_rl$EN;
// register m_m_succValidVec_2_rl
reg m_m_succValidVec_2_rl;
wire m_m_succValidVec_2_rl$D_IN, m_m_succValidVec_2_rl$EN;
// register m_m_succValidVec_3_rl
reg m_m_succValidVec_3_rl;
wire m_m_succValidVec_3_rl$D_IN, m_m_succValidVec_3_rl$EN;
// register m_m_succValidVec_4_rl
reg m_m_succValidVec_4_rl;
wire m_m_succValidVec_4_rl$D_IN, m_m_succValidVec_4_rl$EN;
// register m_m_succValidVec_5_rl
reg m_m_succValidVec_5_rl;
wire m_m_succValidVec_5_rl$D_IN, m_m_succValidVec_5_rl$EN;
// register m_m_succValidVec_6_rl
reg m_m_succValidVec_6_rl;
wire m_m_succValidVec_6_rl$D_IN, m_m_succValidVec_6_rl$EN;
// register m_m_succValidVec_7_rl
reg m_m_succValidVec_7_rl;
wire m_m_succValidVec_7_rl$D_IN, m_m_succValidVec_7_rl$EN;
// ports of submodule m_m_emptyEntryQ
wire [2 : 0] m_m_emptyEntryQ$D_IN, m_m_emptyEntryQ$D_OUT;
wire m_m_emptyEntryQ$CLR,
m_m_emptyEntryQ$DEQ,
m_m_emptyEntryQ$EMPTY_N,
m_m_emptyEntryQ$ENQ,
m_m_emptyEntryQ$FULL_N;
// ports of submodule m_m_reqVec_0_dummy2_0
wire m_m_reqVec_0_dummy2_0$D_IN,
m_m_reqVec_0_dummy2_0$EN,
m_m_reqVec_0_dummy2_0$Q_OUT;
// ports of submodule m_m_reqVec_0_dummy2_1
wire m_m_reqVec_0_dummy2_1$D_IN,
m_m_reqVec_0_dummy2_1$EN,
m_m_reqVec_0_dummy2_1$Q_OUT;
// ports of submodule m_m_reqVec_0_dummy2_2
wire m_m_reqVec_0_dummy2_2$D_IN,
m_m_reqVec_0_dummy2_2$EN,
m_m_reqVec_0_dummy2_2$Q_OUT;
// ports of submodule m_m_reqVec_1_dummy2_0
wire m_m_reqVec_1_dummy2_0$D_IN,
m_m_reqVec_1_dummy2_0$EN,
m_m_reqVec_1_dummy2_0$Q_OUT;
// ports of submodule m_m_reqVec_1_dummy2_1
wire m_m_reqVec_1_dummy2_1$D_IN,
m_m_reqVec_1_dummy2_1$EN,
m_m_reqVec_1_dummy2_1$Q_OUT;
// ports of submodule m_m_reqVec_1_dummy2_2
wire m_m_reqVec_1_dummy2_2$D_IN,
m_m_reqVec_1_dummy2_2$EN,
m_m_reqVec_1_dummy2_2$Q_OUT;
// ports of submodule m_m_reqVec_2_dummy2_0
wire m_m_reqVec_2_dummy2_0$D_IN,
m_m_reqVec_2_dummy2_0$EN,
m_m_reqVec_2_dummy2_0$Q_OUT;
// ports of submodule m_m_reqVec_2_dummy2_1
wire m_m_reqVec_2_dummy2_1$D_IN,
m_m_reqVec_2_dummy2_1$EN,
m_m_reqVec_2_dummy2_1$Q_OUT;
// ports of submodule m_m_reqVec_2_dummy2_2
wire m_m_reqVec_2_dummy2_2$D_IN,
m_m_reqVec_2_dummy2_2$EN,
m_m_reqVec_2_dummy2_2$Q_OUT;
// ports of submodule m_m_reqVec_3_dummy2_0
wire m_m_reqVec_3_dummy2_0$D_IN,
m_m_reqVec_3_dummy2_0$EN,
m_m_reqVec_3_dummy2_0$Q_OUT;
// ports of submodule m_m_reqVec_3_dummy2_1
wire m_m_reqVec_3_dummy2_1$D_IN,
m_m_reqVec_3_dummy2_1$EN,
m_m_reqVec_3_dummy2_1$Q_OUT;
// ports of submodule m_m_reqVec_3_dummy2_2
wire m_m_reqVec_3_dummy2_2$D_IN,
m_m_reqVec_3_dummy2_2$EN,
m_m_reqVec_3_dummy2_2$Q_OUT;
// ports of submodule m_m_reqVec_4_dummy2_0
wire m_m_reqVec_4_dummy2_0$D_IN,
m_m_reqVec_4_dummy2_0$EN,
m_m_reqVec_4_dummy2_0$Q_OUT;
// ports of submodule m_m_reqVec_4_dummy2_1
wire m_m_reqVec_4_dummy2_1$D_IN,
m_m_reqVec_4_dummy2_1$EN,
m_m_reqVec_4_dummy2_1$Q_OUT;
// ports of submodule m_m_reqVec_4_dummy2_2
wire m_m_reqVec_4_dummy2_2$D_IN,
m_m_reqVec_4_dummy2_2$EN,
m_m_reqVec_4_dummy2_2$Q_OUT;
// ports of submodule m_m_reqVec_5_dummy2_0
wire m_m_reqVec_5_dummy2_0$D_IN,
m_m_reqVec_5_dummy2_0$EN,
m_m_reqVec_5_dummy2_0$Q_OUT;
// ports of submodule m_m_reqVec_5_dummy2_1
wire m_m_reqVec_5_dummy2_1$D_IN,
m_m_reqVec_5_dummy2_1$EN,
m_m_reqVec_5_dummy2_1$Q_OUT;
// ports of submodule m_m_reqVec_5_dummy2_2
wire m_m_reqVec_5_dummy2_2$D_IN,
m_m_reqVec_5_dummy2_2$EN,
m_m_reqVec_5_dummy2_2$Q_OUT;
// ports of submodule m_m_reqVec_6_dummy2_0
wire m_m_reqVec_6_dummy2_0$D_IN,
m_m_reqVec_6_dummy2_0$EN,
m_m_reqVec_6_dummy2_0$Q_OUT;
// ports of submodule m_m_reqVec_6_dummy2_1
wire m_m_reqVec_6_dummy2_1$D_IN,
m_m_reqVec_6_dummy2_1$EN,
m_m_reqVec_6_dummy2_1$Q_OUT;
// ports of submodule m_m_reqVec_6_dummy2_2
wire m_m_reqVec_6_dummy2_2$D_IN,
m_m_reqVec_6_dummy2_2$EN,
m_m_reqVec_6_dummy2_2$Q_OUT;
// ports of submodule m_m_reqVec_7_dummy2_0
wire m_m_reqVec_7_dummy2_0$D_IN,
m_m_reqVec_7_dummy2_0$EN,
m_m_reqVec_7_dummy2_0$Q_OUT;
// ports of submodule m_m_reqVec_7_dummy2_1
wire m_m_reqVec_7_dummy2_1$D_IN,
m_m_reqVec_7_dummy2_1$EN,
m_m_reqVec_7_dummy2_1$Q_OUT;
// ports of submodule m_m_reqVec_7_dummy2_2
wire m_m_reqVec_7_dummy2_2$D_IN,
m_m_reqVec_7_dummy2_2$EN,
m_m_reqVec_7_dummy2_2$Q_OUT;
// ports of submodule m_m_resultVec_0_dummy2_0
wire m_m_resultVec_0_dummy2_0$D_IN, m_m_resultVec_0_dummy2_0$EN;
// ports of submodule m_m_resultVec_0_dummy2_1
wire m_m_resultVec_0_dummy2_1$D_IN,
m_m_resultVec_0_dummy2_1$EN,
m_m_resultVec_0_dummy2_1$Q_OUT;
// ports of submodule m_m_resultVec_0_dummy2_2
wire m_m_resultVec_0_dummy2_2$D_IN,
m_m_resultVec_0_dummy2_2$EN,
m_m_resultVec_0_dummy2_2$Q_OUT;
// ports of submodule m_m_resultVec_1_dummy2_0
wire m_m_resultVec_1_dummy2_0$D_IN, m_m_resultVec_1_dummy2_0$EN;
// ports of submodule m_m_resultVec_1_dummy2_1
wire m_m_resultVec_1_dummy2_1$D_IN,
m_m_resultVec_1_dummy2_1$EN,
m_m_resultVec_1_dummy2_1$Q_OUT;
// ports of submodule m_m_resultVec_1_dummy2_2
wire m_m_resultVec_1_dummy2_2$D_IN,
m_m_resultVec_1_dummy2_2$EN,
m_m_resultVec_1_dummy2_2$Q_OUT;
// ports of submodule m_m_resultVec_2_dummy2_0
wire m_m_resultVec_2_dummy2_0$D_IN, m_m_resultVec_2_dummy2_0$EN;
// ports of submodule m_m_resultVec_2_dummy2_1
wire m_m_resultVec_2_dummy2_1$D_IN,
m_m_resultVec_2_dummy2_1$EN,
m_m_resultVec_2_dummy2_1$Q_OUT;
// ports of submodule m_m_resultVec_2_dummy2_2
wire m_m_resultVec_2_dummy2_2$D_IN,
m_m_resultVec_2_dummy2_2$EN,
m_m_resultVec_2_dummy2_2$Q_OUT;
// ports of submodule m_m_resultVec_3_dummy2_0
wire m_m_resultVec_3_dummy2_0$D_IN, m_m_resultVec_3_dummy2_0$EN;
// ports of submodule m_m_resultVec_3_dummy2_1
wire m_m_resultVec_3_dummy2_1$D_IN,
m_m_resultVec_3_dummy2_1$EN,
m_m_resultVec_3_dummy2_1$Q_OUT;
// ports of submodule m_m_resultVec_3_dummy2_2
wire m_m_resultVec_3_dummy2_2$D_IN,
m_m_resultVec_3_dummy2_2$EN,
m_m_resultVec_3_dummy2_2$Q_OUT;
// ports of submodule m_m_resultVec_4_dummy2_0
wire m_m_resultVec_4_dummy2_0$D_IN, m_m_resultVec_4_dummy2_0$EN;
// ports of submodule m_m_resultVec_4_dummy2_1
wire m_m_resultVec_4_dummy2_1$D_IN,
m_m_resultVec_4_dummy2_1$EN,
m_m_resultVec_4_dummy2_1$Q_OUT;
// ports of submodule m_m_resultVec_4_dummy2_2
wire m_m_resultVec_4_dummy2_2$D_IN,
m_m_resultVec_4_dummy2_2$EN,
m_m_resultVec_4_dummy2_2$Q_OUT;
// ports of submodule m_m_resultVec_5_dummy2_0
wire m_m_resultVec_5_dummy2_0$D_IN, m_m_resultVec_5_dummy2_0$EN;
// ports of submodule m_m_resultVec_5_dummy2_1
wire m_m_resultVec_5_dummy2_1$D_IN,
m_m_resultVec_5_dummy2_1$EN,
m_m_resultVec_5_dummy2_1$Q_OUT;
// ports of submodule m_m_resultVec_5_dummy2_2
wire m_m_resultVec_5_dummy2_2$D_IN,
m_m_resultVec_5_dummy2_2$EN,
m_m_resultVec_5_dummy2_2$Q_OUT;
// ports of submodule m_m_resultVec_6_dummy2_0
wire m_m_resultVec_6_dummy2_0$D_IN, m_m_resultVec_6_dummy2_0$EN;
// ports of submodule m_m_resultVec_6_dummy2_1
wire m_m_resultVec_6_dummy2_1$D_IN,
m_m_resultVec_6_dummy2_1$EN,
m_m_resultVec_6_dummy2_1$Q_OUT;
// ports of submodule m_m_resultVec_6_dummy2_2
wire m_m_resultVec_6_dummy2_2$D_IN,
m_m_resultVec_6_dummy2_2$EN,
m_m_resultVec_6_dummy2_2$Q_OUT;
// ports of submodule m_m_resultVec_7_dummy2_0
wire m_m_resultVec_7_dummy2_0$D_IN, m_m_resultVec_7_dummy2_0$EN;
// ports of submodule m_m_resultVec_7_dummy2_1
wire m_m_resultVec_7_dummy2_1$D_IN,
m_m_resultVec_7_dummy2_1$EN,
m_m_resultVec_7_dummy2_1$Q_OUT;
// ports of submodule m_m_resultVec_7_dummy2_2
wire m_m_resultVec_7_dummy2_2$D_IN,
m_m_resultVec_7_dummy2_2$EN,
m_m_resultVec_7_dummy2_2$Q_OUT;
// ports of submodule m_m_slotVec_0_dummy2_0
wire m_m_slotVec_0_dummy2_0$D_IN,
m_m_slotVec_0_dummy2_0$EN,
m_m_slotVec_0_dummy2_0$Q_OUT;
// ports of submodule m_m_slotVec_0_dummy2_1
wire m_m_slotVec_0_dummy2_1$D_IN,
m_m_slotVec_0_dummy2_1$EN,
m_m_slotVec_0_dummy2_1$Q_OUT;
// ports of submodule m_m_slotVec_0_dummy2_2
wire m_m_slotVec_0_dummy2_2$D_IN,
m_m_slotVec_0_dummy2_2$EN,
m_m_slotVec_0_dummy2_2$Q_OUT;
// ports of submodule m_m_slotVec_1_dummy2_0
wire m_m_slotVec_1_dummy2_0$D_IN,
m_m_slotVec_1_dummy2_0$EN,
m_m_slotVec_1_dummy2_0$Q_OUT;
// ports of submodule m_m_slotVec_1_dummy2_1
wire m_m_slotVec_1_dummy2_1$D_IN,
m_m_slotVec_1_dummy2_1$EN,
m_m_slotVec_1_dummy2_1$Q_OUT;
// ports of submodule m_m_slotVec_1_dummy2_2
wire m_m_slotVec_1_dummy2_2$D_IN,
m_m_slotVec_1_dummy2_2$EN,
m_m_slotVec_1_dummy2_2$Q_OUT;
// ports of submodule m_m_slotVec_2_dummy2_0
wire m_m_slotVec_2_dummy2_0$D_IN,
m_m_slotVec_2_dummy2_0$EN,
m_m_slotVec_2_dummy2_0$Q_OUT;
// ports of submodule m_m_slotVec_2_dummy2_1
wire m_m_slotVec_2_dummy2_1$D_IN,
m_m_slotVec_2_dummy2_1$EN,
m_m_slotVec_2_dummy2_1$Q_OUT;
// ports of submodule m_m_slotVec_2_dummy2_2
wire m_m_slotVec_2_dummy2_2$D_IN,
m_m_slotVec_2_dummy2_2$EN,
m_m_slotVec_2_dummy2_2$Q_OUT;
// ports of submodule m_m_slotVec_3_dummy2_0
wire m_m_slotVec_3_dummy2_0$D_IN,
m_m_slotVec_3_dummy2_0$EN,
m_m_slotVec_3_dummy2_0$Q_OUT;
// ports of submodule m_m_slotVec_3_dummy2_1
wire m_m_slotVec_3_dummy2_1$D_IN,
m_m_slotVec_3_dummy2_1$EN,
m_m_slotVec_3_dummy2_1$Q_OUT;
// ports of submodule m_m_slotVec_3_dummy2_2
wire m_m_slotVec_3_dummy2_2$D_IN,
m_m_slotVec_3_dummy2_2$EN,
m_m_slotVec_3_dummy2_2$Q_OUT;
// ports of submodule m_m_slotVec_4_dummy2_0
wire m_m_slotVec_4_dummy2_0$D_IN,
m_m_slotVec_4_dummy2_0$EN,
m_m_slotVec_4_dummy2_0$Q_OUT;
// ports of submodule m_m_slotVec_4_dummy2_1
wire m_m_slotVec_4_dummy2_1$D_IN,
m_m_slotVec_4_dummy2_1$EN,
m_m_slotVec_4_dummy2_1$Q_OUT;
// ports of submodule m_m_slotVec_4_dummy2_2
wire m_m_slotVec_4_dummy2_2$D_IN,
m_m_slotVec_4_dummy2_2$EN,
m_m_slotVec_4_dummy2_2$Q_OUT;
// ports of submodule m_m_slotVec_5_dummy2_0
wire m_m_slotVec_5_dummy2_0$D_IN,
m_m_slotVec_5_dummy2_0$EN,
m_m_slotVec_5_dummy2_0$Q_OUT;
// ports of submodule m_m_slotVec_5_dummy2_1
wire m_m_slotVec_5_dummy2_1$D_IN,
m_m_slotVec_5_dummy2_1$EN,
m_m_slotVec_5_dummy2_1$Q_OUT;
// ports of submodule m_m_slotVec_5_dummy2_2
wire m_m_slotVec_5_dummy2_2$D_IN,
m_m_slotVec_5_dummy2_2$EN,
m_m_slotVec_5_dummy2_2$Q_OUT;
// ports of submodule m_m_slotVec_6_dummy2_0
wire m_m_slotVec_6_dummy2_0$D_IN,
m_m_slotVec_6_dummy2_0$EN,
m_m_slotVec_6_dummy2_0$Q_OUT;
// ports of submodule m_m_slotVec_6_dummy2_1
wire m_m_slotVec_6_dummy2_1$D_IN,
m_m_slotVec_6_dummy2_1$EN,
m_m_slotVec_6_dummy2_1$Q_OUT;
// ports of submodule m_m_slotVec_6_dummy2_2
wire m_m_slotVec_6_dummy2_2$D_IN,
m_m_slotVec_6_dummy2_2$EN,
m_m_slotVec_6_dummy2_2$Q_OUT;
// ports of submodule m_m_slotVec_7_dummy2_0
wire m_m_slotVec_7_dummy2_0$D_IN,
m_m_slotVec_7_dummy2_0$EN,
m_m_slotVec_7_dummy2_0$Q_OUT;
// ports of submodule m_m_slotVec_7_dummy2_1
wire m_m_slotVec_7_dummy2_1$D_IN,
m_m_slotVec_7_dummy2_1$EN,
m_m_slotVec_7_dummy2_1$Q_OUT;
// ports of submodule m_m_slotVec_7_dummy2_2
wire m_m_slotVec_7_dummy2_2$D_IN,
m_m_slotVec_7_dummy2_2$EN,
m_m_slotVec_7_dummy2_2$Q_OUT;
// ports of submodule m_m_stateVec_0_dummy2_0
wire m_m_stateVec_0_dummy2_0$D_IN,
m_m_stateVec_0_dummy2_0$EN,
m_m_stateVec_0_dummy2_0$Q_OUT;
// ports of submodule m_m_stateVec_0_dummy2_1
wire m_m_stateVec_0_dummy2_1$D_IN,
m_m_stateVec_0_dummy2_1$EN,
m_m_stateVec_0_dummy2_1$Q_OUT;
// ports of submodule m_m_stateVec_0_dummy2_2
wire m_m_stateVec_0_dummy2_2$D_IN,
m_m_stateVec_0_dummy2_2$EN,
m_m_stateVec_0_dummy2_2$Q_OUT;
// ports of submodule m_m_stateVec_1_dummy2_0
wire m_m_stateVec_1_dummy2_0$D_IN,
m_m_stateVec_1_dummy2_0$EN,
m_m_stateVec_1_dummy2_0$Q_OUT;
// ports of submodule m_m_stateVec_1_dummy2_1
wire m_m_stateVec_1_dummy2_1$D_IN,
m_m_stateVec_1_dummy2_1$EN,
m_m_stateVec_1_dummy2_1$Q_OUT;
// ports of submodule m_m_stateVec_1_dummy2_2
wire m_m_stateVec_1_dummy2_2$D_IN,
m_m_stateVec_1_dummy2_2$EN,
m_m_stateVec_1_dummy2_2$Q_OUT;
// ports of submodule m_m_stateVec_2_dummy2_0
wire m_m_stateVec_2_dummy2_0$D_IN,
m_m_stateVec_2_dummy2_0$EN,
m_m_stateVec_2_dummy2_0$Q_OUT;
// ports of submodule m_m_stateVec_2_dummy2_1
wire m_m_stateVec_2_dummy2_1$D_IN,
m_m_stateVec_2_dummy2_1$EN,
m_m_stateVec_2_dummy2_1$Q_OUT;
// ports of submodule m_m_stateVec_2_dummy2_2
wire m_m_stateVec_2_dummy2_2$D_IN,
m_m_stateVec_2_dummy2_2$EN,
m_m_stateVec_2_dummy2_2$Q_OUT;
// ports of submodule m_m_stateVec_3_dummy2_0
wire m_m_stateVec_3_dummy2_0$D_IN,
m_m_stateVec_3_dummy2_0$EN,
m_m_stateVec_3_dummy2_0$Q_OUT;
// ports of submodule m_m_stateVec_3_dummy2_1
wire m_m_stateVec_3_dummy2_1$D_IN,
m_m_stateVec_3_dummy2_1$EN,
m_m_stateVec_3_dummy2_1$Q_OUT;
// ports of submodule m_m_stateVec_3_dummy2_2
wire m_m_stateVec_3_dummy2_2$D_IN,
m_m_stateVec_3_dummy2_2$EN,
m_m_stateVec_3_dummy2_2$Q_OUT;
// ports of submodule m_m_stateVec_4_dummy2_0
wire m_m_stateVec_4_dummy2_0$D_IN,
m_m_stateVec_4_dummy2_0$EN,
m_m_stateVec_4_dummy2_0$Q_OUT;
// ports of submodule m_m_stateVec_4_dummy2_1
wire m_m_stateVec_4_dummy2_1$D_IN,
m_m_stateVec_4_dummy2_1$EN,
m_m_stateVec_4_dummy2_1$Q_OUT;
// ports of submodule m_m_stateVec_4_dummy2_2
wire m_m_stateVec_4_dummy2_2$D_IN,
m_m_stateVec_4_dummy2_2$EN,
m_m_stateVec_4_dummy2_2$Q_OUT;
// ports of submodule m_m_stateVec_5_dummy2_0
wire m_m_stateVec_5_dummy2_0$D_IN,
m_m_stateVec_5_dummy2_0$EN,
m_m_stateVec_5_dummy2_0$Q_OUT;
// ports of submodule m_m_stateVec_5_dummy2_1
wire m_m_stateVec_5_dummy2_1$D_IN,
m_m_stateVec_5_dummy2_1$EN,
m_m_stateVec_5_dummy2_1$Q_OUT;
// ports of submodule m_m_stateVec_5_dummy2_2
wire m_m_stateVec_5_dummy2_2$D_IN,
m_m_stateVec_5_dummy2_2$EN,
m_m_stateVec_5_dummy2_2$Q_OUT;
// ports of submodule m_m_stateVec_6_dummy2_0
wire m_m_stateVec_6_dummy2_0$D_IN,
m_m_stateVec_6_dummy2_0$EN,
m_m_stateVec_6_dummy2_0$Q_OUT;
// ports of submodule m_m_stateVec_6_dummy2_1
wire m_m_stateVec_6_dummy2_1$D_IN,
m_m_stateVec_6_dummy2_1$EN,
m_m_stateVec_6_dummy2_1$Q_OUT;
// ports of submodule m_m_stateVec_6_dummy2_2
wire m_m_stateVec_6_dummy2_2$D_IN,
m_m_stateVec_6_dummy2_2$EN,
m_m_stateVec_6_dummy2_2$Q_OUT;
// ports of submodule m_m_stateVec_7_dummy2_0
wire m_m_stateVec_7_dummy2_0$D_IN,
m_m_stateVec_7_dummy2_0$EN,
m_m_stateVec_7_dummy2_0$Q_OUT;
// ports of submodule m_m_stateVec_7_dummy2_1
wire m_m_stateVec_7_dummy2_1$D_IN,
m_m_stateVec_7_dummy2_1$EN,
m_m_stateVec_7_dummy2_1$Q_OUT;
// ports of submodule m_m_stateVec_7_dummy2_2
wire m_m_stateVec_7_dummy2_2$D_IN,
m_m_stateVec_7_dummy2_2$EN,
m_m_stateVec_7_dummy2_2$Q_OUT;
// ports of submodule m_m_succFile
wire [2 : 0] m_m_succFile$ADDR_1,
m_m_succFile$ADDR_2,
m_m_succFile$ADDR_3,
m_m_succFile$ADDR_4,
m_m_succFile$ADDR_5,
m_m_succFile$ADDR_IN,
m_m_succFile$D_IN,
m_m_succFile$D_OUT_1;
wire m_m_succFile$WE;
// ports of submodule m_m_succValidVec_0_dummy2_0
wire m_m_succValidVec_0_dummy2_0$D_IN,
m_m_succValidVec_0_dummy2_0$EN,
m_m_succValidVec_0_dummy2_0$Q_OUT;
// ports of submodule m_m_succValidVec_0_dummy2_1
wire m_m_succValidVec_0_dummy2_1$D_IN,
m_m_succValidVec_0_dummy2_1$EN,
m_m_succValidVec_0_dummy2_1$Q_OUT;
// ports of submodule m_m_succValidVec_0_dummy2_2
wire m_m_succValidVec_0_dummy2_2$D_IN,
m_m_succValidVec_0_dummy2_2$EN,
m_m_succValidVec_0_dummy2_2$Q_OUT;
// ports of submodule m_m_succValidVec_1_dummy2_0
wire m_m_succValidVec_1_dummy2_0$D_IN,
m_m_succValidVec_1_dummy2_0$EN,
m_m_succValidVec_1_dummy2_0$Q_OUT;
// ports of submodule m_m_succValidVec_1_dummy2_1
wire m_m_succValidVec_1_dummy2_1$D_IN,
m_m_succValidVec_1_dummy2_1$EN,
m_m_succValidVec_1_dummy2_1$Q_OUT;
// ports of submodule m_m_succValidVec_1_dummy2_2
wire m_m_succValidVec_1_dummy2_2$D_IN,
m_m_succValidVec_1_dummy2_2$EN,
m_m_succValidVec_1_dummy2_2$Q_OUT;
// ports of submodule m_m_succValidVec_2_dummy2_0
wire m_m_succValidVec_2_dummy2_0$D_IN,
m_m_succValidVec_2_dummy2_0$EN,
m_m_succValidVec_2_dummy2_0$Q_OUT;
// ports of submodule m_m_succValidVec_2_dummy2_1
wire m_m_succValidVec_2_dummy2_1$D_IN,
m_m_succValidVec_2_dummy2_1$EN,
m_m_succValidVec_2_dummy2_1$Q_OUT;
// ports of submodule m_m_succValidVec_2_dummy2_2
wire m_m_succValidVec_2_dummy2_2$D_IN,
m_m_succValidVec_2_dummy2_2$EN,
m_m_succValidVec_2_dummy2_2$Q_OUT;
// ports of submodule m_m_succValidVec_3_dummy2_0
wire m_m_succValidVec_3_dummy2_0$D_IN,
m_m_succValidVec_3_dummy2_0$EN,
m_m_succValidVec_3_dummy2_0$Q_OUT;
// ports of submodule m_m_succValidVec_3_dummy2_1
wire m_m_succValidVec_3_dummy2_1$D_IN,
m_m_succValidVec_3_dummy2_1$EN,
m_m_succValidVec_3_dummy2_1$Q_OUT;
// ports of submodule m_m_succValidVec_3_dummy2_2
wire m_m_succValidVec_3_dummy2_2$D_IN,
m_m_succValidVec_3_dummy2_2$EN,
m_m_succValidVec_3_dummy2_2$Q_OUT;
// ports of submodule m_m_succValidVec_4_dummy2_0
wire m_m_succValidVec_4_dummy2_0$D_IN,
m_m_succValidVec_4_dummy2_0$EN,
m_m_succValidVec_4_dummy2_0$Q_OUT;
// ports of submodule m_m_succValidVec_4_dummy2_1
wire m_m_succValidVec_4_dummy2_1$D_IN,
m_m_succValidVec_4_dummy2_1$EN,
m_m_succValidVec_4_dummy2_1$Q_OUT;
// ports of submodule m_m_succValidVec_4_dummy2_2
wire m_m_succValidVec_4_dummy2_2$D_IN,
m_m_succValidVec_4_dummy2_2$EN,
m_m_succValidVec_4_dummy2_2$Q_OUT;
// ports of submodule m_m_succValidVec_5_dummy2_0
wire m_m_succValidVec_5_dummy2_0$D_IN,
m_m_succValidVec_5_dummy2_0$EN,
m_m_succValidVec_5_dummy2_0$Q_OUT;
// ports of submodule m_m_succValidVec_5_dummy2_1
wire m_m_succValidVec_5_dummy2_1$D_IN,
m_m_succValidVec_5_dummy2_1$EN,
m_m_succValidVec_5_dummy2_1$Q_OUT;
// ports of submodule m_m_succValidVec_5_dummy2_2
wire m_m_succValidVec_5_dummy2_2$D_IN,
m_m_succValidVec_5_dummy2_2$EN,
m_m_succValidVec_5_dummy2_2$Q_OUT;
// ports of submodule m_m_succValidVec_6_dummy2_0
wire m_m_succValidVec_6_dummy2_0$D_IN,
m_m_succValidVec_6_dummy2_0$EN,
m_m_succValidVec_6_dummy2_0$Q_OUT;
// ports of submodule m_m_succValidVec_6_dummy2_1
wire m_m_succValidVec_6_dummy2_1$D_IN,
m_m_succValidVec_6_dummy2_1$EN,
m_m_succValidVec_6_dummy2_1$Q_OUT;
// ports of submodule m_m_succValidVec_6_dummy2_2
wire m_m_succValidVec_6_dummy2_2$D_IN,
m_m_succValidVec_6_dummy2_2$EN,
m_m_succValidVec_6_dummy2_2$Q_OUT;
// ports of submodule m_m_succValidVec_7_dummy2_0
wire m_m_succValidVec_7_dummy2_0$D_IN,
m_m_succValidVec_7_dummy2_0$EN,
m_m_succValidVec_7_dummy2_0$Q_OUT;
// ports of submodule m_m_succValidVec_7_dummy2_1
wire m_m_succValidVec_7_dummy2_1$D_IN,
m_m_succValidVec_7_dummy2_1$EN,
m_m_succValidVec_7_dummy2_1$Q_OUT;
// ports of submodule m_m_succValidVec_7_dummy2_2
wire m_m_succValidVec_7_dummy2_2$D_IN,
m_m_succValidVec_7_dummy2_2$EN,
m_m_succValidVec_7_dummy2_2$Q_OUT;
// rule scheduling signals
wire CAN_FIRE_RL_m_m_initEmptyEntry,
CAN_FIRE_RL_m_m_reqVec_0_canon,
CAN_FIRE_RL_m_m_reqVec_1_canon,
CAN_FIRE_RL_m_m_reqVec_2_canon,
CAN_FIRE_RL_m_m_reqVec_3_canon,
CAN_FIRE_RL_m_m_reqVec_4_canon,
CAN_FIRE_RL_m_m_reqVec_5_canon,
CAN_FIRE_RL_m_m_reqVec_6_canon,
CAN_FIRE_RL_m_m_reqVec_7_canon,
CAN_FIRE_RL_m_m_resultVec_0_canon,
CAN_FIRE_RL_m_m_resultVec_1_canon,
CAN_FIRE_RL_m_m_resultVec_2_canon,
CAN_FIRE_RL_m_m_resultVec_3_canon,
CAN_FIRE_RL_m_m_resultVec_4_canon,
CAN_FIRE_RL_m_m_resultVec_5_canon,
CAN_FIRE_RL_m_m_resultVec_6_canon,
CAN_FIRE_RL_m_m_resultVec_7_canon,
CAN_FIRE_RL_m_m_slotVec_0_canon,
CAN_FIRE_RL_m_m_slotVec_1_canon,
CAN_FIRE_RL_m_m_slotVec_2_canon,
CAN_FIRE_RL_m_m_slotVec_3_canon,
CAN_FIRE_RL_m_m_slotVec_4_canon,
CAN_FIRE_RL_m_m_slotVec_5_canon,
CAN_FIRE_RL_m_m_slotVec_6_canon,
CAN_FIRE_RL_m_m_slotVec_7_canon,
CAN_FIRE_RL_m_m_stateVec_0_canon,
CAN_FIRE_RL_m_m_stateVec_1_canon,
CAN_FIRE_RL_m_m_stateVec_2_canon,
CAN_FIRE_RL_m_m_stateVec_3_canon,
CAN_FIRE_RL_m_m_stateVec_4_canon,
CAN_FIRE_RL_m_m_stateVec_5_canon,
CAN_FIRE_RL_m_m_stateVec_6_canon,
CAN_FIRE_RL_m_m_stateVec_7_canon,
CAN_FIRE_RL_m_m_succValidVec_0_canon,
CAN_FIRE_RL_m_m_succValidVec_1_canon,
CAN_FIRE_RL_m_m_succValidVec_2_canon,
CAN_FIRE_RL_m_m_succValidVec_3_canon,
CAN_FIRE_RL_m_m_succValidVec_4_canon,
CAN_FIRE_RL_m_m_succValidVec_5_canon,
CAN_FIRE_RL_m_m_succValidVec_6_canon,
CAN_FIRE_RL_m_m_succValidVec_7_canon,
CAN_FIRE_getEmptyEntryInit,
CAN_FIRE_pipelineResp_setResult,
CAN_FIRE_pipelineResp_setStateSlot,
CAN_FIRE_pipelineResp_setSucc,
CAN_FIRE_sendRsToC_releaseEntry,
CAN_FIRE_stuck_get,
WILL_FIRE_RL_m_m_initEmptyEntry,
WILL_FIRE_RL_m_m_reqVec_0_canon,
WILL_FIRE_RL_m_m_reqVec_1_canon,
WILL_FIRE_RL_m_m_reqVec_2_canon,
WILL_FIRE_RL_m_m_reqVec_3_canon,
WILL_FIRE_RL_m_m_reqVec_4_canon,
WILL_FIRE_RL_m_m_reqVec_5_canon,
WILL_FIRE_RL_m_m_reqVec_6_canon,
WILL_FIRE_RL_m_m_reqVec_7_canon,
WILL_FIRE_RL_m_m_resultVec_0_canon,
WILL_FIRE_RL_m_m_resultVec_1_canon,
WILL_FIRE_RL_m_m_resultVec_2_canon,
WILL_FIRE_RL_m_m_resultVec_3_canon,
WILL_FIRE_RL_m_m_resultVec_4_canon,
WILL_FIRE_RL_m_m_resultVec_5_canon,
WILL_FIRE_RL_m_m_resultVec_6_canon,
WILL_FIRE_RL_m_m_resultVec_7_canon,
WILL_FIRE_RL_m_m_slotVec_0_canon,
WILL_FIRE_RL_m_m_slotVec_1_canon,
WILL_FIRE_RL_m_m_slotVec_2_canon,
WILL_FIRE_RL_m_m_slotVec_3_canon,
WILL_FIRE_RL_m_m_slotVec_4_canon,
WILL_FIRE_RL_m_m_slotVec_5_canon,
WILL_FIRE_RL_m_m_slotVec_6_canon,
WILL_FIRE_RL_m_m_slotVec_7_canon,
WILL_FIRE_RL_m_m_stateVec_0_canon,
WILL_FIRE_RL_m_m_stateVec_1_canon,
WILL_FIRE_RL_m_m_stateVec_2_canon,
WILL_FIRE_RL_m_m_stateVec_3_canon,
WILL_FIRE_RL_m_m_stateVec_4_canon,
WILL_FIRE_RL_m_m_stateVec_5_canon,
WILL_FIRE_RL_m_m_stateVec_6_canon,
WILL_FIRE_RL_m_m_stateVec_7_canon,
WILL_FIRE_RL_m_m_succValidVec_0_canon,
WILL_FIRE_RL_m_m_succValidVec_1_canon,
WILL_FIRE_RL_m_m_succValidVec_2_canon,
WILL_FIRE_RL_m_m_succValidVec_3_canon,
WILL_FIRE_RL_m_m_succValidVec_4_canon,
WILL_FIRE_RL_m_m_succValidVec_5_canon,
WILL_FIRE_RL_m_m_succValidVec_6_canon,
WILL_FIRE_RL_m_m_succValidVec_7_canon,
WILL_FIRE_getEmptyEntryInit,
WILL_FIRE_pipelineResp_setResult,
WILL_FIRE_pipelineResp_setStateSlot,
WILL_FIRE_pipelineResp_setSucc,
WILL_FIRE_sendRsToC_releaseEntry,
WILL_FIRE_stuck_get;
// declarations used by system tasks
// synopsys translate_off
reg [63 : 0] v__h67404;
// synopsys translate_on
// remaining internal signals
reg [51 : 0] x__h100344, x__h99438, x__h99566;
reg [31 : 0] SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948,
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954;
reg [2 : 0] x__h100307, x__h98681, x__h99529;
reg SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945,
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951,
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942,
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100,
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103,
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155,
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231;
wire [65 : 0] IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306,
IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374,
IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442,
IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510,
IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578,
IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646,
IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714,
IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782;
wire [63 : 0] n__read_addr__h98103,
n__read_addr__h98184,
n__read_addr__h98265,
n__read_addr__h98346,
n__read_addr__h98427,
n__read_addr__h98508,
n__read_addr__h98589,
n__read_addr__h98670;
wire [51 : 0] n__read_repTag__h98815,
n__read_repTag__h98900,
n__read_repTag__h98985,
n__read_repTag__h99070,
n__read_repTag__h99155,
n__read_repTag__h99240,
n__read_repTag__h99325,
n__read_repTag__h99410;
wire [31 : 0] IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280,
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302,
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348,
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370,
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416,
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438,
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484,
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506,
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552,
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574,
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620,
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642,
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688,
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710,
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756,
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778;
wire [2 : 0] IF_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m__ETC___d1457,
IF_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m__ETC___d1458,
IF_IF_m_m_stateVec_4_dummy2_0_read__128_AND_m__ETC___d1454,
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109,
IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9,
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115,
IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19,
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121,
IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29,
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127,
IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39,
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133,
IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49,
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139,
IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59,
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145,
IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69,
IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_m_s_ETC___d1151,
IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79,
n__read_way__h98814,
n__read_way__h98899,
n__read_way__h98984,
n__read_way__h99069,
n__read_way__h99154,
n__read_way__h99239,
n__read_way__h99324,
n__read_way__h99409;
wire IF_m_m_reqVec_0_dummy2_0_read__58_AND_m_m_reqV_ETC___d1255,
IF_m_m_reqVec_1_dummy2_0_read__64_AND_m_m_reqV_ETC___d1274,
IF_m_m_reqVec_2_dummy2_0_read__70_AND_m_m_reqV_ETC___d1294,
IF_m_m_reqVec_3_dummy2_0_read__76_AND_m_m_reqV_ETC___d1313,
IF_m_m_reqVec_4_dummy2_0_read__82_AND_m_m_reqV_ETC___d1334,
IF_m_m_reqVec_5_dummy2_0_read__88_AND_m_m_reqV_ETC___d1353,
IF_m_m_reqVec_6_dummy2_0_read__94_AND_m_m_reqV_ETC___d1373,
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1409,
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1414,
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1465,
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1420,
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1432,
NOT_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_ETC___d1264,
NOT_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_ETC___d1404,
NOT_IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_ETC___d1283,
NOT_IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_ETC___d1303,
NOT_IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_ETC___d1322,
NOT_IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_ETC___d1343,
NOT_IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_ETC___d1362,
NOT_IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_ETC___d1382,
NOT_IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_ETC___d1401,
NOT_m_m_resultVec_0_dummy2_1_read__93_94_OR_NO_ETC___d898,
NOT_m_m_resultVec_1_dummy2_1_read__99_00_OR_NO_ETC___d904,
NOT_m_m_resultVec_2_dummy2_1_read__05_06_OR_NO_ETC___d910,
NOT_m_m_resultVec_3_dummy2_1_read__11_12_OR_NO_ETC___d916,
NOT_m_m_resultVec_4_dummy2_1_read__17_18_OR_NO_ETC___d922,
NOT_m_m_resultVec_5_dummy2_1_read__23_24_OR_NO_ETC___d928,
NOT_m_m_resultVec_6_dummy2_1_read__29_30_OR_NO_ETC___d934,
NOT_m_m_resultVec_7_dummy2_1_read__35_36_OR_NO_ETC___d940,
m_m_slotVec_0_dummy2_0_read__007_AND_m_m_slotV_ETC___d1084,
m_m_slotVec_1_dummy2_0_read__014_AND_m_m_slotV_ETC___d1086,
m_m_slotVec_2_dummy2_0_read__021_AND_m_m_slotV_ETC___d1088,
m_m_slotVec_3_dummy2_0_read__028_AND_m_m_slotV_ETC___d1090,
m_m_slotVec_4_dummy2_0_read__035_AND_m_m_slotV_ETC___d1092,
m_m_slotVec_5_dummy2_0_read__042_AND_m_m_slotV_ETC___d1094,
m_m_slotVec_6_dummy2_0_read__049_AND_m_m_slotV_ETC___d1096,
m_m_slotVec_7_dummy2_0_read__056_AND_m_m_slotV_ETC___d1098,
m_m_succValidVec_0_dummy2_0_read__182_AND_m_m__ETC___d1187,
m_m_succValidVec_1_dummy2_0_read__188_AND_m_m__ETC___d1193,
m_m_succValidVec_2_dummy2_0_read__194_AND_m_m__ETC___d1199,
m_m_succValidVec_3_dummy2_0_read__200_AND_m_m__ETC___d1205,
m_m_succValidVec_4_dummy2_0_read__206_AND_m_m__ETC___d1211,
m_m_succValidVec_5_dummy2_0_read__212_AND_m_m__ETC___d1217,
m_m_succValidVec_6_dummy2_0_read__218_AND_m_m__ETC___d1223;
// actionvalue method getEmptyEntryInit
assign getEmptyEntryInit = m_m_emptyEntryQ$D_OUT ;
assign RDY_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
assign CAN_FIRE_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
assign WILL_FIRE_getEmptyEntryInit = EN_getEmptyEntryInit ;
// action method sendRsToC_releaseEntry
assign RDY_sendRsToC_releaseEntry = m_m_inited && m_m_emptyEntryQ$FULL_N ;
assign CAN_FIRE_sendRsToC_releaseEntry =
m_m_inited && m_m_emptyEntryQ$FULL_N ;
assign WILL_FIRE_sendRsToC_releaseEntry = EN_sendRsToC_releaseEntry ;
// value method sendRsToC_getResult
assign sendRsToC_getResult =
{ !SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942,
!SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945,
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948,
!SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951,
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 } ;
assign RDY_sendRsToC_getResult = 1'd1 ;
// value method sendRsToP_cRq_getRq
always@(sendRsToP_cRq_getRq_n or
n__read_addr__h98103 or
n__read_addr__h98184 or
n__read_addr__h98265 or
n__read_addr__h98346 or
n__read_addr__h98427 or
n__read_addr__h98508 or
n__read_addr__h98589 or n__read_addr__h98670)
begin
case (sendRsToP_cRq_getRq_n)
3'd0: sendRsToP_cRq_getRq = n__read_addr__h98103;
3'd1: sendRsToP_cRq_getRq = n__read_addr__h98184;
3'd2: sendRsToP_cRq_getRq = n__read_addr__h98265;
3'd3: sendRsToP_cRq_getRq = n__read_addr__h98346;
3'd4: sendRsToP_cRq_getRq = n__read_addr__h98427;
3'd5: sendRsToP_cRq_getRq = n__read_addr__h98508;
3'd6: sendRsToP_cRq_getRq = n__read_addr__h98589;
3'd7: sendRsToP_cRq_getRq = n__read_addr__h98670;
endcase
end
assign RDY_sendRsToP_cRq_getRq = 1'd1 ;
// value method sendRsToP_cRq_getSlot
assign sendRsToP_cRq_getSlot =
{ x__h98681,
x__h99438,
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 } ;
assign RDY_sendRsToP_cRq_getSlot = 1'd1 ;
// value method sendRqToP_getRq
always@(sendRqToP_getRq_n or
n__read_addr__h98103 or
n__read_addr__h98184 or
n__read_addr__h98265 or
n__read_addr__h98346 or
n__read_addr__h98427 or
n__read_addr__h98508 or
n__read_addr__h98589 or n__read_addr__h98670)
begin
case (sendRqToP_getRq_n)
3'd0: sendRqToP_getRq = n__read_addr__h98103;
3'd1: sendRqToP_getRq = n__read_addr__h98184;
3'd2: sendRqToP_getRq = n__read_addr__h98265;
3'd3: sendRqToP_getRq = n__read_addr__h98346;
3'd4: sendRqToP_getRq = n__read_addr__h98427;
3'd5: sendRqToP_getRq = n__read_addr__h98508;
3'd6: sendRqToP_getRq = n__read_addr__h98589;
3'd7: sendRqToP_getRq = n__read_addr__h98670;
endcase
end
assign RDY_sendRqToP_getRq = 1'd1 ;
// value method sendRqToP_getSlot
assign sendRqToP_getSlot =
{ x__h99529,
x__h99566,
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 } ;
assign RDY_sendRqToP_getSlot = 1'd1 ;
// value method pipelineResp_getState
always@(pipelineResp_getState_n or
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 or
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 or
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 or
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 or
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 or
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 or
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 or
IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_m_s_ETC___d1151)
begin
case (pipelineResp_getState_n)
3'd0:
pipelineResp_getState =
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109;
3'd1:
pipelineResp_getState =
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115;
3'd2:
pipelineResp_getState =
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121;
3'd3:
pipelineResp_getState =
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127;
3'd4:
pipelineResp_getState =
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133;
3'd5:
pipelineResp_getState =
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139;
3'd6:
pipelineResp_getState =
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145;
3'd7:
pipelineResp_getState =
IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_m_s_ETC___d1151;
endcase
end
assign RDY_pipelineResp_getState = 1'd1 ;
// value method pipelineResp_getRq
always@(pipelineResp_getRq_n or
n__read_addr__h98103 or
n__read_addr__h98184 or
n__read_addr__h98265 or
n__read_addr__h98346 or
n__read_addr__h98427 or
n__read_addr__h98508 or
n__read_addr__h98589 or n__read_addr__h98670)
begin
case (pipelineResp_getRq_n)
3'd0: pipelineResp_getRq = n__read_addr__h98103;
3'd1: pipelineResp_getRq = n__read_addr__h98184;
3'd2: pipelineResp_getRq = n__read_addr__h98265;
3'd3: pipelineResp_getRq = n__read_addr__h98346;
3'd4: pipelineResp_getRq = n__read_addr__h98427;
3'd5: pipelineResp_getRq = n__read_addr__h98508;
3'd6: pipelineResp_getRq = n__read_addr__h98589;
3'd7: pipelineResp_getRq = n__read_addr__h98670;
endcase
end
assign RDY_pipelineResp_getRq = 1'd1 ;
// value method pipelineResp_getSlot
assign pipelineResp_getSlot =
{ x__h100307,
x__h100344,
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 } ;
assign RDY_pipelineResp_getSlot = 1'd1 ;
// action method pipelineResp_setResult
assign RDY_pipelineResp_setResult = 1'd1 ;
assign CAN_FIRE_pipelineResp_setResult = 1'd1 ;
assign WILL_FIRE_pipelineResp_setResult = EN_pipelineResp_setResult ;
// action method pipelineResp_setStateSlot
assign RDY_pipelineResp_setStateSlot = 1'd1 ;
assign CAN_FIRE_pipelineResp_setStateSlot = 1'd1 ;
assign WILL_FIRE_pipelineResp_setStateSlot = EN_pipelineResp_setStateSlot ;
// value method pipelineResp_getSucc
assign pipelineResp_getSucc =
{ SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231,
m_m_succFile$D_OUT_1 } ;
assign RDY_pipelineResp_getSucc = 1'd1 ;
// action method pipelineResp_setSucc
assign RDY_pipelineResp_setSucc = 1'd1 ;
assign CAN_FIRE_pipelineResp_setSucc = 1'd1 ;
assign WILL_FIRE_pipelineResp_setSucc = EN_pipelineResp_setSucc ;
// value method pipelineResp_searchEndOfChain
assign pipelineResp_searchEndOfChain =
{ NOT_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_ETC___d1404,
IF_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m__ETC___d1458 } ;
assign RDY_pipelineResp_searchEndOfChain = 1'd1 ;
// value method emptyForFlush
assign emptyForFlush =
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 ==
3'd0 &&
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1465 ;
assign RDY_emptyForFlush = 1'd1 ;
// actionvalue method stuck_get
assign stuck_get = 68'hAAAAAAAAAAAAAAAAA ;
assign RDY_stuck_get = 1'd0 ;
assign CAN_FIRE_stuck_get = 1'd0 ;
assign WILL_FIRE_stuck_get = EN_stuck_get ;
// submodule m_m_emptyEntryQ
SizedFIFO #(.p1width(32'd3),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) m_m_emptyEntryQ(.RST(RST_N),
.CLK(CLK),
.D_IN(m_m_emptyEntryQ$D_IN),
.ENQ(m_m_emptyEntryQ$ENQ),
.DEQ(m_m_emptyEntryQ$DEQ),
.CLR(m_m_emptyEntryQ$CLR),
.D_OUT(m_m_emptyEntryQ$D_OUT),
.FULL_N(m_m_emptyEntryQ$FULL_N),
.EMPTY_N(m_m_emptyEntryQ$EMPTY_N));
// submodule m_m_reqVec_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_0(.CLK(CLK),
.D_IN(m_m_reqVec_0_dummy2_0$D_IN),
.EN(m_m_reqVec_0_dummy2_0$EN),
.Q_OUT(m_m_reqVec_0_dummy2_0$Q_OUT));
// submodule m_m_reqVec_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_1(.CLK(CLK),
.D_IN(m_m_reqVec_0_dummy2_1$D_IN),
.EN(m_m_reqVec_0_dummy2_1$EN),
.Q_OUT(m_m_reqVec_0_dummy2_1$Q_OUT));
// submodule m_m_reqVec_0_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_2(.CLK(CLK),
.D_IN(m_m_reqVec_0_dummy2_2$D_IN),
.EN(m_m_reqVec_0_dummy2_2$EN),
.Q_OUT(m_m_reqVec_0_dummy2_2$Q_OUT));
// submodule m_m_reqVec_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_0(.CLK(CLK),
.D_IN(m_m_reqVec_1_dummy2_0$D_IN),
.EN(m_m_reqVec_1_dummy2_0$EN),
.Q_OUT(m_m_reqVec_1_dummy2_0$Q_OUT));
// submodule m_m_reqVec_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_1(.CLK(CLK),
.D_IN(m_m_reqVec_1_dummy2_1$D_IN),
.EN(m_m_reqVec_1_dummy2_1$EN),
.Q_OUT(m_m_reqVec_1_dummy2_1$Q_OUT));
// submodule m_m_reqVec_1_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_2(.CLK(CLK),
.D_IN(m_m_reqVec_1_dummy2_2$D_IN),
.EN(m_m_reqVec_1_dummy2_2$EN),
.Q_OUT(m_m_reqVec_1_dummy2_2$Q_OUT));
// submodule m_m_reqVec_2_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_0(.CLK(CLK),
.D_IN(m_m_reqVec_2_dummy2_0$D_IN),
.EN(m_m_reqVec_2_dummy2_0$EN),
.Q_OUT(m_m_reqVec_2_dummy2_0$Q_OUT));
// submodule m_m_reqVec_2_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_1(.CLK(CLK),
.D_IN(m_m_reqVec_2_dummy2_1$D_IN),
.EN(m_m_reqVec_2_dummy2_1$EN),
.Q_OUT(m_m_reqVec_2_dummy2_1$Q_OUT));
// submodule m_m_reqVec_2_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_2(.CLK(CLK),
.D_IN(m_m_reqVec_2_dummy2_2$D_IN),
.EN(m_m_reqVec_2_dummy2_2$EN),
.Q_OUT(m_m_reqVec_2_dummy2_2$Q_OUT));
// submodule m_m_reqVec_3_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_0(.CLK(CLK),
.D_IN(m_m_reqVec_3_dummy2_0$D_IN),
.EN(m_m_reqVec_3_dummy2_0$EN),
.Q_OUT(m_m_reqVec_3_dummy2_0$Q_OUT));
// submodule m_m_reqVec_3_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_1(.CLK(CLK),
.D_IN(m_m_reqVec_3_dummy2_1$D_IN),
.EN(m_m_reqVec_3_dummy2_1$EN),
.Q_OUT(m_m_reqVec_3_dummy2_1$Q_OUT));
// submodule m_m_reqVec_3_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_2(.CLK(CLK),
.D_IN(m_m_reqVec_3_dummy2_2$D_IN),
.EN(m_m_reqVec_3_dummy2_2$EN),
.Q_OUT(m_m_reqVec_3_dummy2_2$Q_OUT));
// submodule m_m_reqVec_4_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_0(.CLK(CLK),
.D_IN(m_m_reqVec_4_dummy2_0$D_IN),
.EN(m_m_reqVec_4_dummy2_0$EN),
.Q_OUT(m_m_reqVec_4_dummy2_0$Q_OUT));
// submodule m_m_reqVec_4_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_1(.CLK(CLK),
.D_IN(m_m_reqVec_4_dummy2_1$D_IN),
.EN(m_m_reqVec_4_dummy2_1$EN),
.Q_OUT(m_m_reqVec_4_dummy2_1$Q_OUT));
// submodule m_m_reqVec_4_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_2(.CLK(CLK),
.D_IN(m_m_reqVec_4_dummy2_2$D_IN),
.EN(m_m_reqVec_4_dummy2_2$EN),
.Q_OUT(m_m_reqVec_4_dummy2_2$Q_OUT));
// submodule m_m_reqVec_5_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_0(.CLK(CLK),
.D_IN(m_m_reqVec_5_dummy2_0$D_IN),
.EN(m_m_reqVec_5_dummy2_0$EN),
.Q_OUT(m_m_reqVec_5_dummy2_0$Q_OUT));
// submodule m_m_reqVec_5_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_1(.CLK(CLK),
.D_IN(m_m_reqVec_5_dummy2_1$D_IN),
.EN(m_m_reqVec_5_dummy2_1$EN),
.Q_OUT(m_m_reqVec_5_dummy2_1$Q_OUT));
// submodule m_m_reqVec_5_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_2(.CLK(CLK),
.D_IN(m_m_reqVec_5_dummy2_2$D_IN),
.EN(m_m_reqVec_5_dummy2_2$EN),
.Q_OUT(m_m_reqVec_5_dummy2_2$Q_OUT));
// submodule m_m_reqVec_6_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_0(.CLK(CLK),
.D_IN(m_m_reqVec_6_dummy2_0$D_IN),
.EN(m_m_reqVec_6_dummy2_0$EN),
.Q_OUT(m_m_reqVec_6_dummy2_0$Q_OUT));
// submodule m_m_reqVec_6_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_1(.CLK(CLK),
.D_IN(m_m_reqVec_6_dummy2_1$D_IN),
.EN(m_m_reqVec_6_dummy2_1$EN),
.Q_OUT(m_m_reqVec_6_dummy2_1$Q_OUT));
// submodule m_m_reqVec_6_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_2(.CLK(CLK),
.D_IN(m_m_reqVec_6_dummy2_2$D_IN),
.EN(m_m_reqVec_6_dummy2_2$EN),
.Q_OUT(m_m_reqVec_6_dummy2_2$Q_OUT));
// submodule m_m_reqVec_7_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_0(.CLK(CLK),
.D_IN(m_m_reqVec_7_dummy2_0$D_IN),
.EN(m_m_reqVec_7_dummy2_0$EN),
.Q_OUT(m_m_reqVec_7_dummy2_0$Q_OUT));
// submodule m_m_reqVec_7_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_1(.CLK(CLK),
.D_IN(m_m_reqVec_7_dummy2_1$D_IN),
.EN(m_m_reqVec_7_dummy2_1$EN),
.Q_OUT(m_m_reqVec_7_dummy2_1$Q_OUT));
// submodule m_m_reqVec_7_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_2(.CLK(CLK),
.D_IN(m_m_reqVec_7_dummy2_2$D_IN),
.EN(m_m_reqVec_7_dummy2_2$EN),
.Q_OUT(m_m_reqVec_7_dummy2_2$Q_OUT));
// submodule m_m_resultVec_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_0_dummy2_0(.CLK(CLK),
.D_IN(m_m_resultVec_0_dummy2_0$D_IN),
.EN(m_m_resultVec_0_dummy2_0$EN),
.Q_OUT());
// submodule m_m_resultVec_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_0_dummy2_1(.CLK(CLK),
.D_IN(m_m_resultVec_0_dummy2_1$D_IN),
.EN(m_m_resultVec_0_dummy2_1$EN),
.Q_OUT(m_m_resultVec_0_dummy2_1$Q_OUT));
// submodule m_m_resultVec_0_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_0_dummy2_2(.CLK(CLK),
.D_IN(m_m_resultVec_0_dummy2_2$D_IN),
.EN(m_m_resultVec_0_dummy2_2$EN),
.Q_OUT(m_m_resultVec_0_dummy2_2$Q_OUT));
// submodule m_m_resultVec_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_1_dummy2_0(.CLK(CLK),
.D_IN(m_m_resultVec_1_dummy2_0$D_IN),
.EN(m_m_resultVec_1_dummy2_0$EN),
.Q_OUT());
// submodule m_m_resultVec_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_1_dummy2_1(.CLK(CLK),
.D_IN(m_m_resultVec_1_dummy2_1$D_IN),
.EN(m_m_resultVec_1_dummy2_1$EN),
.Q_OUT(m_m_resultVec_1_dummy2_1$Q_OUT));
// submodule m_m_resultVec_1_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_1_dummy2_2(.CLK(CLK),
.D_IN(m_m_resultVec_1_dummy2_2$D_IN),
.EN(m_m_resultVec_1_dummy2_2$EN),
.Q_OUT(m_m_resultVec_1_dummy2_2$Q_OUT));
// submodule m_m_resultVec_2_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_2_dummy2_0(.CLK(CLK),
.D_IN(m_m_resultVec_2_dummy2_0$D_IN),
.EN(m_m_resultVec_2_dummy2_0$EN),
.Q_OUT());
// submodule m_m_resultVec_2_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_2_dummy2_1(.CLK(CLK),
.D_IN(m_m_resultVec_2_dummy2_1$D_IN),
.EN(m_m_resultVec_2_dummy2_1$EN),
.Q_OUT(m_m_resultVec_2_dummy2_1$Q_OUT));
// submodule m_m_resultVec_2_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_2_dummy2_2(.CLK(CLK),
.D_IN(m_m_resultVec_2_dummy2_2$D_IN),
.EN(m_m_resultVec_2_dummy2_2$EN),
.Q_OUT(m_m_resultVec_2_dummy2_2$Q_OUT));
// submodule m_m_resultVec_3_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_3_dummy2_0(.CLK(CLK),
.D_IN(m_m_resultVec_3_dummy2_0$D_IN),
.EN(m_m_resultVec_3_dummy2_0$EN),
.Q_OUT());
// submodule m_m_resultVec_3_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_3_dummy2_1(.CLK(CLK),
.D_IN(m_m_resultVec_3_dummy2_1$D_IN),
.EN(m_m_resultVec_3_dummy2_1$EN),
.Q_OUT(m_m_resultVec_3_dummy2_1$Q_OUT));
// submodule m_m_resultVec_3_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_3_dummy2_2(.CLK(CLK),
.D_IN(m_m_resultVec_3_dummy2_2$D_IN),
.EN(m_m_resultVec_3_dummy2_2$EN),
.Q_OUT(m_m_resultVec_3_dummy2_2$Q_OUT));
// submodule m_m_resultVec_4_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_4_dummy2_0(.CLK(CLK),
.D_IN(m_m_resultVec_4_dummy2_0$D_IN),
.EN(m_m_resultVec_4_dummy2_0$EN),
.Q_OUT());
// submodule m_m_resultVec_4_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_4_dummy2_1(.CLK(CLK),
.D_IN(m_m_resultVec_4_dummy2_1$D_IN),
.EN(m_m_resultVec_4_dummy2_1$EN),
.Q_OUT(m_m_resultVec_4_dummy2_1$Q_OUT));
// submodule m_m_resultVec_4_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_4_dummy2_2(.CLK(CLK),
.D_IN(m_m_resultVec_4_dummy2_2$D_IN),
.EN(m_m_resultVec_4_dummy2_2$EN),
.Q_OUT(m_m_resultVec_4_dummy2_2$Q_OUT));
// submodule m_m_resultVec_5_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_5_dummy2_0(.CLK(CLK),
.D_IN(m_m_resultVec_5_dummy2_0$D_IN),
.EN(m_m_resultVec_5_dummy2_0$EN),
.Q_OUT());
// submodule m_m_resultVec_5_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_5_dummy2_1(.CLK(CLK),
.D_IN(m_m_resultVec_5_dummy2_1$D_IN),
.EN(m_m_resultVec_5_dummy2_1$EN),
.Q_OUT(m_m_resultVec_5_dummy2_1$Q_OUT));
// submodule m_m_resultVec_5_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_5_dummy2_2(.CLK(CLK),
.D_IN(m_m_resultVec_5_dummy2_2$D_IN),
.EN(m_m_resultVec_5_dummy2_2$EN),
.Q_OUT(m_m_resultVec_5_dummy2_2$Q_OUT));
// submodule m_m_resultVec_6_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_6_dummy2_0(.CLK(CLK),
.D_IN(m_m_resultVec_6_dummy2_0$D_IN),
.EN(m_m_resultVec_6_dummy2_0$EN),
.Q_OUT());
// submodule m_m_resultVec_6_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_6_dummy2_1(.CLK(CLK),
.D_IN(m_m_resultVec_6_dummy2_1$D_IN),
.EN(m_m_resultVec_6_dummy2_1$EN),
.Q_OUT(m_m_resultVec_6_dummy2_1$Q_OUT));
// submodule m_m_resultVec_6_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_6_dummy2_2(.CLK(CLK),
.D_IN(m_m_resultVec_6_dummy2_2$D_IN),
.EN(m_m_resultVec_6_dummy2_2$EN),
.Q_OUT(m_m_resultVec_6_dummy2_2$Q_OUT));
// submodule m_m_resultVec_7_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_7_dummy2_0(.CLK(CLK),
.D_IN(m_m_resultVec_7_dummy2_0$D_IN),
.EN(m_m_resultVec_7_dummy2_0$EN),
.Q_OUT());
// submodule m_m_resultVec_7_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_7_dummy2_1(.CLK(CLK),
.D_IN(m_m_resultVec_7_dummy2_1$D_IN),
.EN(m_m_resultVec_7_dummy2_1$EN),
.Q_OUT(m_m_resultVec_7_dummy2_1$Q_OUT));
// submodule m_m_resultVec_7_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_7_dummy2_2(.CLK(CLK),
.D_IN(m_m_resultVec_7_dummy2_2$D_IN),
.EN(m_m_resultVec_7_dummy2_2$EN),
.Q_OUT(m_m_resultVec_7_dummy2_2$Q_OUT));
// submodule m_m_slotVec_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_0(.CLK(CLK),
.D_IN(m_m_slotVec_0_dummy2_0$D_IN),
.EN(m_m_slotVec_0_dummy2_0$EN),
.Q_OUT(m_m_slotVec_0_dummy2_0$Q_OUT));
// submodule m_m_slotVec_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_1(.CLK(CLK),
.D_IN(m_m_slotVec_0_dummy2_1$D_IN),
.EN(m_m_slotVec_0_dummy2_1$EN),
.Q_OUT(m_m_slotVec_0_dummy2_1$Q_OUT));
// submodule m_m_slotVec_0_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_2(.CLK(CLK),
.D_IN(m_m_slotVec_0_dummy2_2$D_IN),
.EN(m_m_slotVec_0_dummy2_2$EN),
.Q_OUT(m_m_slotVec_0_dummy2_2$Q_OUT));
// submodule m_m_slotVec_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_0(.CLK(CLK),
.D_IN(m_m_slotVec_1_dummy2_0$D_IN),
.EN(m_m_slotVec_1_dummy2_0$EN),
.Q_OUT(m_m_slotVec_1_dummy2_0$Q_OUT));
// submodule m_m_slotVec_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_1(.CLK(CLK),
.D_IN(m_m_slotVec_1_dummy2_1$D_IN),
.EN(m_m_slotVec_1_dummy2_1$EN),
.Q_OUT(m_m_slotVec_1_dummy2_1$Q_OUT));
// submodule m_m_slotVec_1_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_2(.CLK(CLK),
.D_IN(m_m_slotVec_1_dummy2_2$D_IN),
.EN(m_m_slotVec_1_dummy2_2$EN),
.Q_OUT(m_m_slotVec_1_dummy2_2$Q_OUT));
// submodule m_m_slotVec_2_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_0(.CLK(CLK),
.D_IN(m_m_slotVec_2_dummy2_0$D_IN),
.EN(m_m_slotVec_2_dummy2_0$EN),
.Q_OUT(m_m_slotVec_2_dummy2_0$Q_OUT));
// submodule m_m_slotVec_2_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_1(.CLK(CLK),
.D_IN(m_m_slotVec_2_dummy2_1$D_IN),
.EN(m_m_slotVec_2_dummy2_1$EN),
.Q_OUT(m_m_slotVec_2_dummy2_1$Q_OUT));
// submodule m_m_slotVec_2_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_2(.CLK(CLK),
.D_IN(m_m_slotVec_2_dummy2_2$D_IN),
.EN(m_m_slotVec_2_dummy2_2$EN),
.Q_OUT(m_m_slotVec_2_dummy2_2$Q_OUT));
// submodule m_m_slotVec_3_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_0(.CLK(CLK),
.D_IN(m_m_slotVec_3_dummy2_0$D_IN),
.EN(m_m_slotVec_3_dummy2_0$EN),
.Q_OUT(m_m_slotVec_3_dummy2_0$Q_OUT));
// submodule m_m_slotVec_3_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_1(.CLK(CLK),
.D_IN(m_m_slotVec_3_dummy2_1$D_IN),
.EN(m_m_slotVec_3_dummy2_1$EN),
.Q_OUT(m_m_slotVec_3_dummy2_1$Q_OUT));
// submodule m_m_slotVec_3_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_2(.CLK(CLK),
.D_IN(m_m_slotVec_3_dummy2_2$D_IN),
.EN(m_m_slotVec_3_dummy2_2$EN),
.Q_OUT(m_m_slotVec_3_dummy2_2$Q_OUT));
// submodule m_m_slotVec_4_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_0(.CLK(CLK),
.D_IN(m_m_slotVec_4_dummy2_0$D_IN),
.EN(m_m_slotVec_4_dummy2_0$EN),
.Q_OUT(m_m_slotVec_4_dummy2_0$Q_OUT));
// submodule m_m_slotVec_4_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_1(.CLK(CLK),
.D_IN(m_m_slotVec_4_dummy2_1$D_IN),
.EN(m_m_slotVec_4_dummy2_1$EN),
.Q_OUT(m_m_slotVec_4_dummy2_1$Q_OUT));
// submodule m_m_slotVec_4_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_2(.CLK(CLK),
.D_IN(m_m_slotVec_4_dummy2_2$D_IN),
.EN(m_m_slotVec_4_dummy2_2$EN),
.Q_OUT(m_m_slotVec_4_dummy2_2$Q_OUT));
// submodule m_m_slotVec_5_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_0(.CLK(CLK),
.D_IN(m_m_slotVec_5_dummy2_0$D_IN),
.EN(m_m_slotVec_5_dummy2_0$EN),
.Q_OUT(m_m_slotVec_5_dummy2_0$Q_OUT));
// submodule m_m_slotVec_5_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_1(.CLK(CLK),
.D_IN(m_m_slotVec_5_dummy2_1$D_IN),
.EN(m_m_slotVec_5_dummy2_1$EN),
.Q_OUT(m_m_slotVec_5_dummy2_1$Q_OUT));
// submodule m_m_slotVec_5_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_2(.CLK(CLK),
.D_IN(m_m_slotVec_5_dummy2_2$D_IN),
.EN(m_m_slotVec_5_dummy2_2$EN),
.Q_OUT(m_m_slotVec_5_dummy2_2$Q_OUT));
// submodule m_m_slotVec_6_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_0(.CLK(CLK),
.D_IN(m_m_slotVec_6_dummy2_0$D_IN),
.EN(m_m_slotVec_6_dummy2_0$EN),
.Q_OUT(m_m_slotVec_6_dummy2_0$Q_OUT));
// submodule m_m_slotVec_6_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_1(.CLK(CLK),
.D_IN(m_m_slotVec_6_dummy2_1$D_IN),
.EN(m_m_slotVec_6_dummy2_1$EN),
.Q_OUT(m_m_slotVec_6_dummy2_1$Q_OUT));
// submodule m_m_slotVec_6_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_2(.CLK(CLK),
.D_IN(m_m_slotVec_6_dummy2_2$D_IN),
.EN(m_m_slotVec_6_dummy2_2$EN),
.Q_OUT(m_m_slotVec_6_dummy2_2$Q_OUT));
// submodule m_m_slotVec_7_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_0(.CLK(CLK),
.D_IN(m_m_slotVec_7_dummy2_0$D_IN),
.EN(m_m_slotVec_7_dummy2_0$EN),
.Q_OUT(m_m_slotVec_7_dummy2_0$Q_OUT));
// submodule m_m_slotVec_7_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_1(.CLK(CLK),
.D_IN(m_m_slotVec_7_dummy2_1$D_IN),
.EN(m_m_slotVec_7_dummy2_1$EN),
.Q_OUT(m_m_slotVec_7_dummy2_1$Q_OUT));
// submodule m_m_slotVec_7_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_2(.CLK(CLK),
.D_IN(m_m_slotVec_7_dummy2_2$D_IN),
.EN(m_m_slotVec_7_dummy2_2$EN),
.Q_OUT(m_m_slotVec_7_dummy2_2$Q_OUT));
// submodule m_m_stateVec_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_0(.CLK(CLK),
.D_IN(m_m_stateVec_0_dummy2_0$D_IN),
.EN(m_m_stateVec_0_dummy2_0$EN),
.Q_OUT(m_m_stateVec_0_dummy2_0$Q_OUT));
// submodule m_m_stateVec_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_1(.CLK(CLK),
.D_IN(m_m_stateVec_0_dummy2_1$D_IN),
.EN(m_m_stateVec_0_dummy2_1$EN),
.Q_OUT(m_m_stateVec_0_dummy2_1$Q_OUT));
// submodule m_m_stateVec_0_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_2(.CLK(CLK),
.D_IN(m_m_stateVec_0_dummy2_2$D_IN),
.EN(m_m_stateVec_0_dummy2_2$EN),
.Q_OUT(m_m_stateVec_0_dummy2_2$Q_OUT));
// submodule m_m_stateVec_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_0(.CLK(CLK),
.D_IN(m_m_stateVec_1_dummy2_0$D_IN),
.EN(m_m_stateVec_1_dummy2_0$EN),
.Q_OUT(m_m_stateVec_1_dummy2_0$Q_OUT));
// submodule m_m_stateVec_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_1(.CLK(CLK),
.D_IN(m_m_stateVec_1_dummy2_1$D_IN),
.EN(m_m_stateVec_1_dummy2_1$EN),
.Q_OUT(m_m_stateVec_1_dummy2_1$Q_OUT));
// submodule m_m_stateVec_1_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_2(.CLK(CLK),
.D_IN(m_m_stateVec_1_dummy2_2$D_IN),
.EN(m_m_stateVec_1_dummy2_2$EN),
.Q_OUT(m_m_stateVec_1_dummy2_2$Q_OUT));
// submodule m_m_stateVec_2_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_0(.CLK(CLK),
.D_IN(m_m_stateVec_2_dummy2_0$D_IN),
.EN(m_m_stateVec_2_dummy2_0$EN),
.Q_OUT(m_m_stateVec_2_dummy2_0$Q_OUT));
// submodule m_m_stateVec_2_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_1(.CLK(CLK),
.D_IN(m_m_stateVec_2_dummy2_1$D_IN),
.EN(m_m_stateVec_2_dummy2_1$EN),
.Q_OUT(m_m_stateVec_2_dummy2_1$Q_OUT));
// submodule m_m_stateVec_2_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_2(.CLK(CLK),
.D_IN(m_m_stateVec_2_dummy2_2$D_IN),
.EN(m_m_stateVec_2_dummy2_2$EN),
.Q_OUT(m_m_stateVec_2_dummy2_2$Q_OUT));
// submodule m_m_stateVec_3_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_0(.CLK(CLK),
.D_IN(m_m_stateVec_3_dummy2_0$D_IN),
.EN(m_m_stateVec_3_dummy2_0$EN),
.Q_OUT(m_m_stateVec_3_dummy2_0$Q_OUT));
// submodule m_m_stateVec_3_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_1(.CLK(CLK),
.D_IN(m_m_stateVec_3_dummy2_1$D_IN),
.EN(m_m_stateVec_3_dummy2_1$EN),
.Q_OUT(m_m_stateVec_3_dummy2_1$Q_OUT));
// submodule m_m_stateVec_3_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_2(.CLK(CLK),
.D_IN(m_m_stateVec_3_dummy2_2$D_IN),
.EN(m_m_stateVec_3_dummy2_2$EN),
.Q_OUT(m_m_stateVec_3_dummy2_2$Q_OUT));
// submodule m_m_stateVec_4_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_0(.CLK(CLK),
.D_IN(m_m_stateVec_4_dummy2_0$D_IN),
.EN(m_m_stateVec_4_dummy2_0$EN),
.Q_OUT(m_m_stateVec_4_dummy2_0$Q_OUT));
// submodule m_m_stateVec_4_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_1(.CLK(CLK),
.D_IN(m_m_stateVec_4_dummy2_1$D_IN),
.EN(m_m_stateVec_4_dummy2_1$EN),
.Q_OUT(m_m_stateVec_4_dummy2_1$Q_OUT));
// submodule m_m_stateVec_4_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_2(.CLK(CLK),
.D_IN(m_m_stateVec_4_dummy2_2$D_IN),
.EN(m_m_stateVec_4_dummy2_2$EN),
.Q_OUT(m_m_stateVec_4_dummy2_2$Q_OUT));
// submodule m_m_stateVec_5_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_0(.CLK(CLK),
.D_IN(m_m_stateVec_5_dummy2_0$D_IN),
.EN(m_m_stateVec_5_dummy2_0$EN),
.Q_OUT(m_m_stateVec_5_dummy2_0$Q_OUT));
// submodule m_m_stateVec_5_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_1(.CLK(CLK),
.D_IN(m_m_stateVec_5_dummy2_1$D_IN),
.EN(m_m_stateVec_5_dummy2_1$EN),
.Q_OUT(m_m_stateVec_5_dummy2_1$Q_OUT));
// submodule m_m_stateVec_5_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_2(.CLK(CLK),
.D_IN(m_m_stateVec_5_dummy2_2$D_IN),
.EN(m_m_stateVec_5_dummy2_2$EN),
.Q_OUT(m_m_stateVec_5_dummy2_2$Q_OUT));
// submodule m_m_stateVec_6_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_0(.CLK(CLK),
.D_IN(m_m_stateVec_6_dummy2_0$D_IN),
.EN(m_m_stateVec_6_dummy2_0$EN),
.Q_OUT(m_m_stateVec_6_dummy2_0$Q_OUT));
// submodule m_m_stateVec_6_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_1(.CLK(CLK),
.D_IN(m_m_stateVec_6_dummy2_1$D_IN),
.EN(m_m_stateVec_6_dummy2_1$EN),
.Q_OUT(m_m_stateVec_6_dummy2_1$Q_OUT));
// submodule m_m_stateVec_6_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_2(.CLK(CLK),
.D_IN(m_m_stateVec_6_dummy2_2$D_IN),
.EN(m_m_stateVec_6_dummy2_2$EN),
.Q_OUT(m_m_stateVec_6_dummy2_2$Q_OUT));
// submodule m_m_stateVec_7_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_0(.CLK(CLK),
.D_IN(m_m_stateVec_7_dummy2_0$D_IN),
.EN(m_m_stateVec_7_dummy2_0$EN),
.Q_OUT(m_m_stateVec_7_dummy2_0$Q_OUT));
// submodule m_m_stateVec_7_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_1(.CLK(CLK),
.D_IN(m_m_stateVec_7_dummy2_1$D_IN),
.EN(m_m_stateVec_7_dummy2_1$EN),
.Q_OUT(m_m_stateVec_7_dummy2_1$Q_OUT));
// submodule m_m_stateVec_7_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_2(.CLK(CLK),
.D_IN(m_m_stateVec_7_dummy2_2$D_IN),
.EN(m_m_stateVec_7_dummy2_2$EN),
.Q_OUT(m_m_stateVec_7_dummy2_2$Q_OUT));
// submodule m_m_succFile
RegFile #(.addr_width(32'd3),
.data_width(32'd3),
.lo(3'd0),
.hi(3'd7)) m_m_succFile(.CLK(CLK),
.ADDR_1(m_m_succFile$ADDR_1),
.ADDR_2(m_m_succFile$ADDR_2),
.ADDR_3(m_m_succFile$ADDR_3),
.ADDR_4(m_m_succFile$ADDR_4),
.ADDR_5(m_m_succFile$ADDR_5),
.ADDR_IN(m_m_succFile$ADDR_IN),
.D_IN(m_m_succFile$D_IN),
.WE(m_m_succFile$WE),
.D_OUT_1(m_m_succFile$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule m_m_succValidVec_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_0_dummy2_0(.CLK(CLK),
.D_IN(m_m_succValidVec_0_dummy2_0$D_IN),
.EN(m_m_succValidVec_0_dummy2_0$EN),
.Q_OUT(m_m_succValidVec_0_dummy2_0$Q_OUT));
// submodule m_m_succValidVec_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_0_dummy2_1(.CLK(CLK),
.D_IN(m_m_succValidVec_0_dummy2_1$D_IN),
.EN(m_m_succValidVec_0_dummy2_1$EN),
.Q_OUT(m_m_succValidVec_0_dummy2_1$Q_OUT));
// submodule m_m_succValidVec_0_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_0_dummy2_2(.CLK(CLK),
.D_IN(m_m_succValidVec_0_dummy2_2$D_IN),
.EN(m_m_succValidVec_0_dummy2_2$EN),
.Q_OUT(m_m_succValidVec_0_dummy2_2$Q_OUT));
// submodule m_m_succValidVec_1_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_1_dummy2_0(.CLK(CLK),
.D_IN(m_m_succValidVec_1_dummy2_0$D_IN),
.EN(m_m_succValidVec_1_dummy2_0$EN),
.Q_OUT(m_m_succValidVec_1_dummy2_0$Q_OUT));
// submodule m_m_succValidVec_1_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_1_dummy2_1(.CLK(CLK),
.D_IN(m_m_succValidVec_1_dummy2_1$D_IN),
.EN(m_m_succValidVec_1_dummy2_1$EN),
.Q_OUT(m_m_succValidVec_1_dummy2_1$Q_OUT));
// submodule m_m_succValidVec_1_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_1_dummy2_2(.CLK(CLK),
.D_IN(m_m_succValidVec_1_dummy2_2$D_IN),
.EN(m_m_succValidVec_1_dummy2_2$EN),
.Q_OUT(m_m_succValidVec_1_dummy2_2$Q_OUT));
// submodule m_m_succValidVec_2_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_2_dummy2_0(.CLK(CLK),
.D_IN(m_m_succValidVec_2_dummy2_0$D_IN),
.EN(m_m_succValidVec_2_dummy2_0$EN),
.Q_OUT(m_m_succValidVec_2_dummy2_0$Q_OUT));
// submodule m_m_succValidVec_2_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_2_dummy2_1(.CLK(CLK),
.D_IN(m_m_succValidVec_2_dummy2_1$D_IN),
.EN(m_m_succValidVec_2_dummy2_1$EN),
.Q_OUT(m_m_succValidVec_2_dummy2_1$Q_OUT));
// submodule m_m_succValidVec_2_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_2_dummy2_2(.CLK(CLK),
.D_IN(m_m_succValidVec_2_dummy2_2$D_IN),
.EN(m_m_succValidVec_2_dummy2_2$EN),
.Q_OUT(m_m_succValidVec_2_dummy2_2$Q_OUT));
// submodule m_m_succValidVec_3_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_3_dummy2_0(.CLK(CLK),
.D_IN(m_m_succValidVec_3_dummy2_0$D_IN),
.EN(m_m_succValidVec_3_dummy2_0$EN),
.Q_OUT(m_m_succValidVec_3_dummy2_0$Q_OUT));
// submodule m_m_succValidVec_3_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_3_dummy2_1(.CLK(CLK),
.D_IN(m_m_succValidVec_3_dummy2_1$D_IN),
.EN(m_m_succValidVec_3_dummy2_1$EN),
.Q_OUT(m_m_succValidVec_3_dummy2_1$Q_OUT));
// submodule m_m_succValidVec_3_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_3_dummy2_2(.CLK(CLK),
.D_IN(m_m_succValidVec_3_dummy2_2$D_IN),
.EN(m_m_succValidVec_3_dummy2_2$EN),
.Q_OUT(m_m_succValidVec_3_dummy2_2$Q_OUT));
// submodule m_m_succValidVec_4_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_4_dummy2_0(.CLK(CLK),
.D_IN(m_m_succValidVec_4_dummy2_0$D_IN),
.EN(m_m_succValidVec_4_dummy2_0$EN),
.Q_OUT(m_m_succValidVec_4_dummy2_0$Q_OUT));
// submodule m_m_succValidVec_4_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_4_dummy2_1(.CLK(CLK),
.D_IN(m_m_succValidVec_4_dummy2_1$D_IN),
.EN(m_m_succValidVec_4_dummy2_1$EN),
.Q_OUT(m_m_succValidVec_4_dummy2_1$Q_OUT));
// submodule m_m_succValidVec_4_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_4_dummy2_2(.CLK(CLK),
.D_IN(m_m_succValidVec_4_dummy2_2$D_IN),
.EN(m_m_succValidVec_4_dummy2_2$EN),
.Q_OUT(m_m_succValidVec_4_dummy2_2$Q_OUT));
// submodule m_m_succValidVec_5_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_5_dummy2_0(.CLK(CLK),
.D_IN(m_m_succValidVec_5_dummy2_0$D_IN),
.EN(m_m_succValidVec_5_dummy2_0$EN),
.Q_OUT(m_m_succValidVec_5_dummy2_0$Q_OUT));
// submodule m_m_succValidVec_5_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_5_dummy2_1(.CLK(CLK),
.D_IN(m_m_succValidVec_5_dummy2_1$D_IN),
.EN(m_m_succValidVec_5_dummy2_1$EN),
.Q_OUT(m_m_succValidVec_5_dummy2_1$Q_OUT));
// submodule m_m_succValidVec_5_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_5_dummy2_2(.CLK(CLK),
.D_IN(m_m_succValidVec_5_dummy2_2$D_IN),
.EN(m_m_succValidVec_5_dummy2_2$EN),
.Q_OUT(m_m_succValidVec_5_dummy2_2$Q_OUT));
// submodule m_m_succValidVec_6_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_6_dummy2_0(.CLK(CLK),
.D_IN(m_m_succValidVec_6_dummy2_0$D_IN),
.EN(m_m_succValidVec_6_dummy2_0$EN),
.Q_OUT(m_m_succValidVec_6_dummy2_0$Q_OUT));
// submodule m_m_succValidVec_6_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_6_dummy2_1(.CLK(CLK),
.D_IN(m_m_succValidVec_6_dummy2_1$D_IN),
.EN(m_m_succValidVec_6_dummy2_1$EN),
.Q_OUT(m_m_succValidVec_6_dummy2_1$Q_OUT));
// submodule m_m_succValidVec_6_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_6_dummy2_2(.CLK(CLK),
.D_IN(m_m_succValidVec_6_dummy2_2$D_IN),
.EN(m_m_succValidVec_6_dummy2_2$EN),
.Q_OUT(m_m_succValidVec_6_dummy2_2$Q_OUT));
// submodule m_m_succValidVec_7_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_7_dummy2_0(.CLK(CLK),
.D_IN(m_m_succValidVec_7_dummy2_0$D_IN),
.EN(m_m_succValidVec_7_dummy2_0$EN),
.Q_OUT(m_m_succValidVec_7_dummy2_0$Q_OUT));
// submodule m_m_succValidVec_7_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_7_dummy2_1(.CLK(CLK),
.D_IN(m_m_succValidVec_7_dummy2_1$D_IN),
.EN(m_m_succValidVec_7_dummy2_1$EN),
.Q_OUT(m_m_succValidVec_7_dummy2_1$Q_OUT));
// submodule m_m_succValidVec_7_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_m_succValidVec_7_dummy2_2(.CLK(CLK),
.D_IN(m_m_succValidVec_7_dummy2_2$D_IN),
.EN(m_m_succValidVec_7_dummy2_2$EN),
.Q_OUT(m_m_succValidVec_7_dummy2_2$Q_OUT));
// rule RL_m_m_initEmptyEntry
assign CAN_FIRE_RL_m_m_initEmptyEntry =
m_m_emptyEntryQ$FULL_N && !m_m_inited ;
assign WILL_FIRE_RL_m_m_initEmptyEntry = CAN_FIRE_RL_m_m_initEmptyEntry ;
// rule RL_m_m_stateVec_0_canon
assign CAN_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
// rule RL_m_m_stateVec_1_canon
assign CAN_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
// rule RL_m_m_stateVec_2_canon
assign CAN_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
// rule RL_m_m_stateVec_3_canon
assign CAN_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
// rule RL_m_m_stateVec_4_canon
assign CAN_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
// rule RL_m_m_stateVec_5_canon
assign CAN_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
// rule RL_m_m_stateVec_6_canon
assign CAN_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
// rule RL_m_m_stateVec_7_canon
assign CAN_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
// rule RL_m_m_reqVec_0_canon
assign CAN_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
// rule RL_m_m_reqVec_1_canon
assign CAN_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
// rule RL_m_m_reqVec_2_canon
assign CAN_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
// rule RL_m_m_reqVec_3_canon
assign CAN_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
// rule RL_m_m_reqVec_4_canon
assign CAN_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
// rule RL_m_m_reqVec_5_canon
assign CAN_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
// rule RL_m_m_reqVec_6_canon
assign CAN_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
// rule RL_m_m_reqVec_7_canon
assign CAN_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
// rule RL_m_m_slotVec_0_canon
assign CAN_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
// rule RL_m_m_slotVec_1_canon
assign CAN_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
// rule RL_m_m_slotVec_2_canon
assign CAN_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
// rule RL_m_m_slotVec_3_canon
assign CAN_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
// rule RL_m_m_slotVec_4_canon
assign CAN_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
// rule RL_m_m_slotVec_5_canon
assign CAN_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
// rule RL_m_m_slotVec_6_canon
assign CAN_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
// rule RL_m_m_slotVec_7_canon
assign CAN_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
// rule RL_m_m_resultVec_0_canon
assign CAN_FIRE_RL_m_m_resultVec_0_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_resultVec_0_canon = 1'd1 ;
// rule RL_m_m_resultVec_1_canon
assign CAN_FIRE_RL_m_m_resultVec_1_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_resultVec_1_canon = 1'd1 ;
// rule RL_m_m_resultVec_2_canon
assign CAN_FIRE_RL_m_m_resultVec_2_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_resultVec_2_canon = 1'd1 ;
// rule RL_m_m_resultVec_3_canon
assign CAN_FIRE_RL_m_m_resultVec_3_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_resultVec_3_canon = 1'd1 ;
// rule RL_m_m_resultVec_4_canon
assign CAN_FIRE_RL_m_m_resultVec_4_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_resultVec_4_canon = 1'd1 ;
// rule RL_m_m_resultVec_5_canon
assign CAN_FIRE_RL_m_m_resultVec_5_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_resultVec_5_canon = 1'd1 ;
// rule RL_m_m_resultVec_6_canon
assign CAN_FIRE_RL_m_m_resultVec_6_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_resultVec_6_canon = 1'd1 ;
// rule RL_m_m_resultVec_7_canon
assign CAN_FIRE_RL_m_m_resultVec_7_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_resultVec_7_canon = 1'd1 ;
// rule RL_m_m_succValidVec_0_canon
assign CAN_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
// rule RL_m_m_succValidVec_1_canon
assign CAN_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
// rule RL_m_m_succValidVec_2_canon
assign CAN_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
// rule RL_m_m_succValidVec_3_canon
assign CAN_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
// rule RL_m_m_succValidVec_4_canon
assign CAN_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
// rule RL_m_m_succValidVec_5_canon
assign CAN_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
// rule RL_m_m_succValidVec_6_canon
assign CAN_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
// rule RL_m_m_succValidVec_7_canon
assign CAN_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
// inlined wires
assign m_m_stateVec_0_lat_0$whas =
EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_n == 3'd0 ;
assign m_m_stateVec_0_lat_1$whas =
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd0 ;
assign m_m_stateVec_0_lat_2$whas =
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd0 ;
assign m_m_stateVec_1_lat_0$whas =
EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_n == 3'd1 ;
assign m_m_stateVec_1_lat_1$whas =
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd1 ;
assign m_m_stateVec_1_lat_2$whas =
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd1 ;
assign m_m_stateVec_2_lat_0$whas =
EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_n == 3'd2 ;
assign m_m_stateVec_2_lat_1$whas =
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd2 ;
assign m_m_stateVec_2_lat_2$whas =
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd2 ;
assign m_m_stateVec_3_lat_0$whas =
EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_n == 3'd3 ;
assign m_m_stateVec_3_lat_1$whas =
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd3 ;
assign m_m_stateVec_3_lat_2$whas =
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd3 ;
assign m_m_stateVec_4_lat_1$whas =
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd4 ;
assign m_m_stateVec_4_lat_2$whas =
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd4 ;
assign m_m_stateVec_4_dummy_1_0$wget =
EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_n == 3'd4 ;
assign m_m_stateVec_5_lat_0$whas =
EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_n == 3'd5 ;
assign m_m_stateVec_5_lat_1$whas =
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd5 ;
assign m_m_stateVec_5_lat_2$whas =
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd5 ;
assign m_m_stateVec_6_lat_0$whas =
EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_n == 3'd6 ;
assign m_m_stateVec_6_lat_1$whas =
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd6 ;
assign m_m_stateVec_6_lat_2$whas =
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd6 ;
assign m_m_stateVec_7_lat_0$whas =
EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_n == 3'd7 ;
assign m_m_stateVec_7_lat_1$whas =
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd7 ;
assign m_m_stateVec_7_lat_2$whas =
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd7 ;
assign m_m_resultVec_0_lat_0$wget = { 1'd1, pipelineResp_setResult_r } ;
assign m_m_resultVec_0_lat_0$whas =
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd0 ;
assign m_m_resultVec_1_lat_0$whas =
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd1 ;
assign m_m_resultVec_2_lat_0$whas =
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd2 ;
assign m_m_resultVec_3_lat_0$whas =
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd3 ;
assign m_m_resultVec_4_lat_0$whas =
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd4 ;
assign m_m_resultVec_5_lat_0$whas =
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd5 ;
assign m_m_resultVec_6_lat_0$whas =
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd6 ;
assign m_m_resultVec_7_lat_0$whas =
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd7 ;
assign m_m_succValidVec_0_lat_0$whas =
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd0 ;
assign m_m_succValidVec_1_lat_0$whas =
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd1 ;
assign m_m_succValidVec_2_lat_0$whas =
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd2 ;
assign m_m_succValidVec_3_lat_0$whas =
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd3 ;
assign m_m_succValidVec_4_lat_0$whas =
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd4 ;
assign m_m_succValidVec_5_lat_0$whas =
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd5 ;
assign m_m_succValidVec_6_lat_0$whas =
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd6 ;
assign m_m_succValidVec_7_lat_0$whas =
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd7 ;
// register m_m_initIdx
assign m_m_initIdx$D_IN = m_m_initIdx + 3'd1 ;
assign m_m_initIdx$EN = CAN_FIRE_RL_m_m_initEmptyEntry ;
// register m_m_inited
assign m_m_inited$D_IN = 1'd1 ;
assign m_m_inited$EN =
WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 3'd7 ;
// register m_m_reqVec_0_rl
assign m_m_reqVec_0_rl$D_IN =
m_m_stateVec_0_lat_2$whas ?
getEmptyEntryInit_r :
m_m_reqVec_0_rl ;
assign m_m_reqVec_0_rl$EN = 1'd1 ;
// register m_m_reqVec_1_rl
assign m_m_reqVec_1_rl$D_IN =
m_m_stateVec_1_lat_2$whas ?
getEmptyEntryInit_r :
m_m_reqVec_1_rl ;
assign m_m_reqVec_1_rl$EN = 1'd1 ;
// register m_m_reqVec_2_rl
assign m_m_reqVec_2_rl$D_IN =
m_m_stateVec_2_lat_2$whas ?
getEmptyEntryInit_r :
m_m_reqVec_2_rl ;
assign m_m_reqVec_2_rl$EN = 1'd1 ;
// register m_m_reqVec_3_rl
assign m_m_reqVec_3_rl$D_IN =
m_m_stateVec_3_lat_2$whas ?
getEmptyEntryInit_r :
m_m_reqVec_3_rl ;
assign m_m_reqVec_3_rl$EN = 1'd1 ;
// register m_m_reqVec_4_rl
assign m_m_reqVec_4_rl$D_IN =
m_m_stateVec_4_lat_2$whas ?
getEmptyEntryInit_r :
m_m_reqVec_4_rl ;
assign m_m_reqVec_4_rl$EN = 1'd1 ;
// register m_m_reqVec_5_rl
assign m_m_reqVec_5_rl$D_IN =
m_m_stateVec_5_lat_2$whas ?
getEmptyEntryInit_r :
m_m_reqVec_5_rl ;
assign m_m_reqVec_5_rl$EN = 1'd1 ;
// register m_m_reqVec_6_rl
assign m_m_reqVec_6_rl$D_IN =
m_m_stateVec_6_lat_2$whas ?
getEmptyEntryInit_r :
m_m_reqVec_6_rl ;
assign m_m_reqVec_6_rl$EN = 1'd1 ;
// register m_m_reqVec_7_rl
assign m_m_reqVec_7_rl$D_IN =
m_m_stateVec_7_lat_2$whas ?
getEmptyEntryInit_r :
m_m_reqVec_7_rl ;
assign m_m_reqVec_7_rl$EN = 1'd1 ;
// register m_m_resultVec_0_rl
assign m_m_resultVec_0_rl$D_IN =
{ !m_m_stateVec_0_lat_2$whas &&
(m_m_resultVec_0_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[66] :
m_m_resultVec_0_rl[66]),
IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306 } ;
assign m_m_resultVec_0_rl$EN = 1'd1 ;
// register m_m_resultVec_1_rl
assign m_m_resultVec_1_rl$D_IN =
{ !m_m_stateVec_1_lat_2$whas &&
(m_m_resultVec_1_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[66] :
m_m_resultVec_1_rl[66]),
IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374 } ;
assign m_m_resultVec_1_rl$EN = 1'd1 ;
// register m_m_resultVec_2_rl
assign m_m_resultVec_2_rl$D_IN =
{ !m_m_stateVec_2_lat_2$whas &&
(m_m_resultVec_2_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[66] :
m_m_resultVec_2_rl[66]),
IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442 } ;
assign m_m_resultVec_2_rl$EN = 1'd1 ;
// register m_m_resultVec_3_rl
assign m_m_resultVec_3_rl$D_IN =
{ !m_m_stateVec_3_lat_2$whas &&
(m_m_resultVec_3_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[66] :
m_m_resultVec_3_rl[66]),
IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510 } ;
assign m_m_resultVec_3_rl$EN = 1'd1 ;
// register m_m_resultVec_4_rl
assign m_m_resultVec_4_rl$D_IN =
{ !m_m_stateVec_4_lat_2$whas &&
(m_m_resultVec_4_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[66] :
m_m_resultVec_4_rl[66]),
IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578 } ;
assign m_m_resultVec_4_rl$EN = 1'd1 ;
// register m_m_resultVec_5_rl
assign m_m_resultVec_5_rl$D_IN =
{ !m_m_stateVec_5_lat_2$whas &&
(m_m_resultVec_5_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[66] :
m_m_resultVec_5_rl[66]),
IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646 } ;
assign m_m_resultVec_5_rl$EN = 1'd1 ;
// register m_m_resultVec_6_rl
assign m_m_resultVec_6_rl$D_IN =
{ !m_m_stateVec_6_lat_2$whas &&
(m_m_resultVec_6_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[66] :
m_m_resultVec_6_rl[66]),
IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714 } ;
assign m_m_resultVec_6_rl$EN = 1'd1 ;
// register m_m_resultVec_7_rl
assign m_m_resultVec_7_rl$D_IN =
{ !m_m_stateVec_7_lat_2$whas &&
(m_m_resultVec_7_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[66] :
m_m_resultVec_7_rl[66]),
IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782 } ;
assign m_m_resultVec_7_rl$EN = 1'd1 ;
// register m_m_slotVec_0_rl
assign m_m_slotVec_0_rl$D_IN =
m_m_stateVec_0_lat_2$whas ?
56'h55555555555554 :
(m_m_stateVec_0_lat_0$whas ?
pipelineResp_setStateSlot_slot :
m_m_slotVec_0_rl) ;
assign m_m_slotVec_0_rl$EN = 1'd1 ;
// register m_m_slotVec_1_rl
assign m_m_slotVec_1_rl$D_IN =
m_m_stateVec_1_lat_2$whas ?
56'h55555555555554 :
(m_m_stateVec_1_lat_0$whas ?
pipelineResp_setStateSlot_slot :
m_m_slotVec_1_rl) ;
assign m_m_slotVec_1_rl$EN = 1'd1 ;
// register m_m_slotVec_2_rl
assign m_m_slotVec_2_rl$D_IN =
m_m_stateVec_2_lat_2$whas ?
56'h55555555555554 :
(m_m_stateVec_2_lat_0$whas ?
pipelineResp_setStateSlot_slot :
m_m_slotVec_2_rl) ;
assign m_m_slotVec_2_rl$EN = 1'd1 ;
// register m_m_slotVec_3_rl
assign m_m_slotVec_3_rl$D_IN =
m_m_stateVec_3_lat_2$whas ?
56'h55555555555554 :
(m_m_stateVec_3_lat_0$whas ?
pipelineResp_setStateSlot_slot :
m_m_slotVec_3_rl) ;
assign m_m_slotVec_3_rl$EN = 1'd1 ;
// register m_m_slotVec_4_rl
assign m_m_slotVec_4_rl$D_IN =
m_m_stateVec_4_lat_2$whas ?
56'h55555555555554 :
(m_m_stateVec_4_dummy_1_0$wget ?
pipelineResp_setStateSlot_slot :
m_m_slotVec_4_rl) ;
assign m_m_slotVec_4_rl$EN = 1'd1 ;
// register m_m_slotVec_5_rl
assign m_m_slotVec_5_rl$D_IN =
m_m_stateVec_5_lat_2$whas ?
56'h55555555555554 :
(m_m_stateVec_5_lat_0$whas ?
pipelineResp_setStateSlot_slot :
m_m_slotVec_5_rl) ;
assign m_m_slotVec_5_rl$EN = 1'd1 ;
// register m_m_slotVec_6_rl
assign m_m_slotVec_6_rl$D_IN =
m_m_stateVec_6_lat_2$whas ?
56'h55555555555554 :
(m_m_stateVec_6_lat_0$whas ?
pipelineResp_setStateSlot_slot :
m_m_slotVec_6_rl) ;
assign m_m_slotVec_6_rl$EN = 1'd1 ;
// register m_m_slotVec_7_rl
assign m_m_slotVec_7_rl$D_IN =
m_m_stateVec_7_lat_2$whas ?
56'h55555555555554 :
(m_m_stateVec_7_lat_0$whas ?
pipelineResp_setStateSlot_slot :
m_m_slotVec_7_rl) ;
assign m_m_slotVec_7_rl$EN = 1'd1 ;
// register m_m_stateVec_0_rl
assign m_m_stateVec_0_rl$D_IN =
m_m_stateVec_0_lat_2$whas ?
3'd1 :
IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9 ;
assign m_m_stateVec_0_rl$EN = 1'd1 ;
// register m_m_stateVec_1_rl
assign m_m_stateVec_1_rl$D_IN =
m_m_stateVec_1_lat_2$whas ?
3'd1 :
IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19 ;
assign m_m_stateVec_1_rl$EN = 1'd1 ;
// register m_m_stateVec_2_rl
assign m_m_stateVec_2_rl$D_IN =
m_m_stateVec_2_lat_2$whas ?
3'd1 :
IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29 ;
assign m_m_stateVec_2_rl$EN = 1'd1 ;
// register m_m_stateVec_3_rl
assign m_m_stateVec_3_rl$D_IN =
m_m_stateVec_3_lat_2$whas ?
3'd1 :
IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39 ;
assign m_m_stateVec_3_rl$EN = 1'd1 ;
// register m_m_stateVec_4_rl
assign m_m_stateVec_4_rl$D_IN =
m_m_stateVec_4_lat_2$whas ?
3'd1 :
IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49 ;
assign m_m_stateVec_4_rl$EN = 1'd1 ;
// register m_m_stateVec_5_rl
assign m_m_stateVec_5_rl$D_IN =
m_m_stateVec_5_lat_2$whas ?
3'd1 :
IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59 ;
assign m_m_stateVec_5_rl$EN = 1'd1 ;
// register m_m_stateVec_6_rl
assign m_m_stateVec_6_rl$D_IN =
m_m_stateVec_6_lat_2$whas ?
3'd1 :
IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69 ;
assign m_m_stateVec_6_rl$EN = 1'd1 ;
// register m_m_stateVec_7_rl
assign m_m_stateVec_7_rl$D_IN =
m_m_stateVec_7_lat_2$whas ?
3'd1 :
IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79 ;
assign m_m_stateVec_7_rl$EN = 1'd1 ;
// register m_m_succValidVec_0_rl
assign m_m_succValidVec_0_rl$D_IN =
!m_m_stateVec_0_lat_2$whas &&
(m_m_succValidVec_0_lat_0$whas ?
pipelineResp_setSucc_succ[3] :
m_m_succValidVec_0_rl) ;
assign m_m_succValidVec_0_rl$EN = 1'd1 ;
// register m_m_succValidVec_1_rl
assign m_m_succValidVec_1_rl$D_IN =
!m_m_stateVec_1_lat_2$whas &&
(m_m_succValidVec_1_lat_0$whas ?
pipelineResp_setSucc_succ[3] :
m_m_succValidVec_1_rl) ;
assign m_m_succValidVec_1_rl$EN = 1'd1 ;
// register m_m_succValidVec_2_rl
assign m_m_succValidVec_2_rl$D_IN =
!m_m_stateVec_2_lat_2$whas &&
(m_m_succValidVec_2_lat_0$whas ?
pipelineResp_setSucc_succ[3] :
m_m_succValidVec_2_rl) ;
assign m_m_succValidVec_2_rl$EN = 1'd1 ;
// register m_m_succValidVec_3_rl
assign m_m_succValidVec_3_rl$D_IN =
!m_m_stateVec_3_lat_2$whas &&
(m_m_succValidVec_3_lat_0$whas ?
pipelineResp_setSucc_succ[3] :
m_m_succValidVec_3_rl) ;
assign m_m_succValidVec_3_rl$EN = 1'd1 ;
// register m_m_succValidVec_4_rl
assign m_m_succValidVec_4_rl$D_IN =
!m_m_stateVec_4_lat_2$whas &&
(m_m_succValidVec_4_lat_0$whas ?
pipelineResp_setSucc_succ[3] :
m_m_succValidVec_4_rl) ;
assign m_m_succValidVec_4_rl$EN = 1'd1 ;
// register m_m_succValidVec_5_rl
assign m_m_succValidVec_5_rl$D_IN =
!m_m_stateVec_5_lat_2$whas &&
(m_m_succValidVec_5_lat_0$whas ?
pipelineResp_setSucc_succ[3] :
m_m_succValidVec_5_rl) ;
assign m_m_succValidVec_5_rl$EN = 1'd1 ;
// register m_m_succValidVec_6_rl
assign m_m_succValidVec_6_rl$D_IN =
!m_m_stateVec_6_lat_2$whas &&
(m_m_succValidVec_6_lat_0$whas ?
pipelineResp_setSucc_succ[3] :
m_m_succValidVec_6_rl) ;
assign m_m_succValidVec_6_rl$EN = 1'd1 ;
// register m_m_succValidVec_7_rl
assign m_m_succValidVec_7_rl$D_IN =
!m_m_stateVec_7_lat_2$whas &&
(m_m_succValidVec_7_lat_0$whas ?
pipelineResp_setSucc_succ[3] :
m_m_succValidVec_7_rl) ;
assign m_m_succValidVec_7_rl$EN = 1'd1 ;
// submodule m_m_emptyEntryQ
assign m_m_emptyEntryQ$D_IN =
EN_sendRsToC_releaseEntry ?
sendRsToC_releaseEntry_n :
m_m_initIdx ;
assign m_m_emptyEntryQ$ENQ =
EN_sendRsToC_releaseEntry || WILL_FIRE_RL_m_m_initEmptyEntry ;
assign m_m_emptyEntryQ$DEQ = EN_getEmptyEntryInit ;
assign m_m_emptyEntryQ$CLR = 1'b0 ;
// submodule m_m_reqVec_0_dummy2_0
assign m_m_reqVec_0_dummy2_0$D_IN = 1'b0 ;
assign m_m_reqVec_0_dummy2_0$EN = 1'b0 ;
// submodule m_m_reqVec_0_dummy2_1
assign m_m_reqVec_0_dummy2_1$D_IN = 1'b0 ;
assign m_m_reqVec_0_dummy2_1$EN = 1'b0 ;
// submodule m_m_reqVec_0_dummy2_2
assign m_m_reqVec_0_dummy2_2$D_IN = 1'd1 ;
assign m_m_reqVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
// submodule m_m_reqVec_1_dummy2_0
assign m_m_reqVec_1_dummy2_0$D_IN = 1'b0 ;
assign m_m_reqVec_1_dummy2_0$EN = 1'b0 ;
// submodule m_m_reqVec_1_dummy2_1
assign m_m_reqVec_1_dummy2_1$D_IN = 1'b0 ;
assign m_m_reqVec_1_dummy2_1$EN = 1'b0 ;
// submodule m_m_reqVec_1_dummy2_2
assign m_m_reqVec_1_dummy2_2$D_IN = 1'd1 ;
assign m_m_reqVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
// submodule m_m_reqVec_2_dummy2_0
assign m_m_reqVec_2_dummy2_0$D_IN = 1'b0 ;
assign m_m_reqVec_2_dummy2_0$EN = 1'b0 ;
// submodule m_m_reqVec_2_dummy2_1
assign m_m_reqVec_2_dummy2_1$D_IN = 1'b0 ;
assign m_m_reqVec_2_dummy2_1$EN = 1'b0 ;
// submodule m_m_reqVec_2_dummy2_2
assign m_m_reqVec_2_dummy2_2$D_IN = 1'd1 ;
assign m_m_reqVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
// submodule m_m_reqVec_3_dummy2_0
assign m_m_reqVec_3_dummy2_0$D_IN = 1'b0 ;
assign m_m_reqVec_3_dummy2_0$EN = 1'b0 ;
// submodule m_m_reqVec_3_dummy2_1
assign m_m_reqVec_3_dummy2_1$D_IN = 1'b0 ;
assign m_m_reqVec_3_dummy2_1$EN = 1'b0 ;
// submodule m_m_reqVec_3_dummy2_2
assign m_m_reqVec_3_dummy2_2$D_IN = 1'd1 ;
assign m_m_reqVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
// submodule m_m_reqVec_4_dummy2_0
assign m_m_reqVec_4_dummy2_0$D_IN = 1'b0 ;
assign m_m_reqVec_4_dummy2_0$EN = 1'b0 ;
// submodule m_m_reqVec_4_dummy2_1
assign m_m_reqVec_4_dummy2_1$D_IN = 1'b0 ;
assign m_m_reqVec_4_dummy2_1$EN = 1'b0 ;
// submodule m_m_reqVec_4_dummy2_2
assign m_m_reqVec_4_dummy2_2$D_IN = 1'd1 ;
assign m_m_reqVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
// submodule m_m_reqVec_5_dummy2_0
assign m_m_reqVec_5_dummy2_0$D_IN = 1'b0 ;
assign m_m_reqVec_5_dummy2_0$EN = 1'b0 ;
// submodule m_m_reqVec_5_dummy2_1
assign m_m_reqVec_5_dummy2_1$D_IN = 1'b0 ;
assign m_m_reqVec_5_dummy2_1$EN = 1'b0 ;
// submodule m_m_reqVec_5_dummy2_2
assign m_m_reqVec_5_dummy2_2$D_IN = 1'd1 ;
assign m_m_reqVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
// submodule m_m_reqVec_6_dummy2_0
assign m_m_reqVec_6_dummy2_0$D_IN = 1'b0 ;
assign m_m_reqVec_6_dummy2_0$EN = 1'b0 ;
// submodule m_m_reqVec_6_dummy2_1
assign m_m_reqVec_6_dummy2_1$D_IN = 1'b0 ;
assign m_m_reqVec_6_dummy2_1$EN = 1'b0 ;
// submodule m_m_reqVec_6_dummy2_2
assign m_m_reqVec_6_dummy2_2$D_IN = 1'd1 ;
assign m_m_reqVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
// submodule m_m_reqVec_7_dummy2_0
assign m_m_reqVec_7_dummy2_0$D_IN = 1'b0 ;
assign m_m_reqVec_7_dummy2_0$EN = 1'b0 ;
// submodule m_m_reqVec_7_dummy2_1
assign m_m_reqVec_7_dummy2_1$D_IN = 1'b0 ;
assign m_m_reqVec_7_dummy2_1$EN = 1'b0 ;
// submodule m_m_reqVec_7_dummy2_2
assign m_m_reqVec_7_dummy2_2$D_IN = 1'd1 ;
assign m_m_reqVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
// submodule m_m_resultVec_0_dummy2_0
assign m_m_resultVec_0_dummy2_0$D_IN = 1'd1 ;
assign m_m_resultVec_0_dummy2_0$EN = m_m_resultVec_0_lat_0$whas ;
// submodule m_m_resultVec_0_dummy2_1
assign m_m_resultVec_0_dummy2_1$D_IN = 1'b0 ;
assign m_m_resultVec_0_dummy2_1$EN = 1'b0 ;
// submodule m_m_resultVec_0_dummy2_2
assign m_m_resultVec_0_dummy2_2$D_IN = 1'd1 ;
assign m_m_resultVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
// submodule m_m_resultVec_1_dummy2_0
assign m_m_resultVec_1_dummy2_0$D_IN = 1'd1 ;
assign m_m_resultVec_1_dummy2_0$EN = m_m_resultVec_1_lat_0$whas ;
// submodule m_m_resultVec_1_dummy2_1
assign m_m_resultVec_1_dummy2_1$D_IN = 1'b0 ;
assign m_m_resultVec_1_dummy2_1$EN = 1'b0 ;
// submodule m_m_resultVec_1_dummy2_2
assign m_m_resultVec_1_dummy2_2$D_IN = 1'd1 ;
assign m_m_resultVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
// submodule m_m_resultVec_2_dummy2_0
assign m_m_resultVec_2_dummy2_0$D_IN = 1'd1 ;
assign m_m_resultVec_2_dummy2_0$EN = m_m_resultVec_2_lat_0$whas ;
// submodule m_m_resultVec_2_dummy2_1
assign m_m_resultVec_2_dummy2_1$D_IN = 1'b0 ;
assign m_m_resultVec_2_dummy2_1$EN = 1'b0 ;
// submodule m_m_resultVec_2_dummy2_2
assign m_m_resultVec_2_dummy2_2$D_IN = 1'd1 ;
assign m_m_resultVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
// submodule m_m_resultVec_3_dummy2_0
assign m_m_resultVec_3_dummy2_0$D_IN = 1'd1 ;
assign m_m_resultVec_3_dummy2_0$EN = m_m_resultVec_3_lat_0$whas ;
// submodule m_m_resultVec_3_dummy2_1
assign m_m_resultVec_3_dummy2_1$D_IN = 1'b0 ;
assign m_m_resultVec_3_dummy2_1$EN = 1'b0 ;
// submodule m_m_resultVec_3_dummy2_2
assign m_m_resultVec_3_dummy2_2$D_IN = 1'd1 ;
assign m_m_resultVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
// submodule m_m_resultVec_4_dummy2_0
assign m_m_resultVec_4_dummy2_0$D_IN = 1'd1 ;
assign m_m_resultVec_4_dummy2_0$EN = m_m_resultVec_4_lat_0$whas ;
// submodule m_m_resultVec_4_dummy2_1
assign m_m_resultVec_4_dummy2_1$D_IN = 1'b0 ;
assign m_m_resultVec_4_dummy2_1$EN = 1'b0 ;
// submodule m_m_resultVec_4_dummy2_2
assign m_m_resultVec_4_dummy2_2$D_IN = 1'd1 ;
assign m_m_resultVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
// submodule m_m_resultVec_5_dummy2_0
assign m_m_resultVec_5_dummy2_0$D_IN = 1'd1 ;
assign m_m_resultVec_5_dummy2_0$EN = m_m_resultVec_5_lat_0$whas ;
// submodule m_m_resultVec_5_dummy2_1
assign m_m_resultVec_5_dummy2_1$D_IN = 1'b0 ;
assign m_m_resultVec_5_dummy2_1$EN = 1'b0 ;
// submodule m_m_resultVec_5_dummy2_2
assign m_m_resultVec_5_dummy2_2$D_IN = 1'd1 ;
assign m_m_resultVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
// submodule m_m_resultVec_6_dummy2_0
assign m_m_resultVec_6_dummy2_0$D_IN = 1'd1 ;
assign m_m_resultVec_6_dummy2_0$EN = m_m_resultVec_6_lat_0$whas ;
// submodule m_m_resultVec_6_dummy2_1
assign m_m_resultVec_6_dummy2_1$D_IN = 1'b0 ;
assign m_m_resultVec_6_dummy2_1$EN = 1'b0 ;
// submodule m_m_resultVec_6_dummy2_2
assign m_m_resultVec_6_dummy2_2$D_IN = 1'd1 ;
assign m_m_resultVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
// submodule m_m_resultVec_7_dummy2_0
assign m_m_resultVec_7_dummy2_0$D_IN = 1'd1 ;
assign m_m_resultVec_7_dummy2_0$EN = m_m_resultVec_7_lat_0$whas ;
// submodule m_m_resultVec_7_dummy2_1
assign m_m_resultVec_7_dummy2_1$D_IN = 1'b0 ;
assign m_m_resultVec_7_dummy2_1$EN = 1'b0 ;
// submodule m_m_resultVec_7_dummy2_2
assign m_m_resultVec_7_dummy2_2$D_IN = 1'd1 ;
assign m_m_resultVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
// submodule m_m_slotVec_0_dummy2_0
assign m_m_slotVec_0_dummy2_0$D_IN = 1'd1 ;
assign m_m_slotVec_0_dummy2_0$EN = m_m_stateVec_0_lat_0$whas ;
// submodule m_m_slotVec_0_dummy2_1
assign m_m_slotVec_0_dummy2_1$D_IN = 1'b0 ;
assign m_m_slotVec_0_dummy2_1$EN = 1'b0 ;
// submodule m_m_slotVec_0_dummy2_2
assign m_m_slotVec_0_dummy2_2$D_IN = 1'd1 ;
assign m_m_slotVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
// submodule m_m_slotVec_1_dummy2_0
assign m_m_slotVec_1_dummy2_0$D_IN = 1'd1 ;
assign m_m_slotVec_1_dummy2_0$EN = m_m_stateVec_1_lat_0$whas ;
// submodule m_m_slotVec_1_dummy2_1
assign m_m_slotVec_1_dummy2_1$D_IN = 1'b0 ;
assign m_m_slotVec_1_dummy2_1$EN = 1'b0 ;
// submodule m_m_slotVec_1_dummy2_2
assign m_m_slotVec_1_dummy2_2$D_IN = 1'd1 ;
assign m_m_slotVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
// submodule m_m_slotVec_2_dummy2_0
assign m_m_slotVec_2_dummy2_0$D_IN = 1'd1 ;
assign m_m_slotVec_2_dummy2_0$EN = m_m_stateVec_2_lat_0$whas ;
// submodule m_m_slotVec_2_dummy2_1
assign m_m_slotVec_2_dummy2_1$D_IN = 1'b0 ;
assign m_m_slotVec_2_dummy2_1$EN = 1'b0 ;
// submodule m_m_slotVec_2_dummy2_2
assign m_m_slotVec_2_dummy2_2$D_IN = 1'd1 ;
assign m_m_slotVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
// submodule m_m_slotVec_3_dummy2_0
assign m_m_slotVec_3_dummy2_0$D_IN = 1'd1 ;
assign m_m_slotVec_3_dummy2_0$EN = m_m_stateVec_3_lat_0$whas ;
// submodule m_m_slotVec_3_dummy2_1
assign m_m_slotVec_3_dummy2_1$D_IN = 1'b0 ;
assign m_m_slotVec_3_dummy2_1$EN = 1'b0 ;
// submodule m_m_slotVec_3_dummy2_2
assign m_m_slotVec_3_dummy2_2$D_IN = 1'd1 ;
assign m_m_slotVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
// submodule m_m_slotVec_4_dummy2_0
assign m_m_slotVec_4_dummy2_0$D_IN = 1'd1 ;
assign m_m_slotVec_4_dummy2_0$EN = m_m_stateVec_4_dummy_1_0$wget ;
// submodule m_m_slotVec_4_dummy2_1
assign m_m_slotVec_4_dummy2_1$D_IN = 1'b0 ;
assign m_m_slotVec_4_dummy2_1$EN = 1'b0 ;
// submodule m_m_slotVec_4_dummy2_2
assign m_m_slotVec_4_dummy2_2$D_IN = 1'd1 ;
assign m_m_slotVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
// submodule m_m_slotVec_5_dummy2_0
assign m_m_slotVec_5_dummy2_0$D_IN = 1'd1 ;
assign m_m_slotVec_5_dummy2_0$EN = m_m_stateVec_5_lat_0$whas ;
// submodule m_m_slotVec_5_dummy2_1
assign m_m_slotVec_5_dummy2_1$D_IN = 1'b0 ;
assign m_m_slotVec_5_dummy2_1$EN = 1'b0 ;
// submodule m_m_slotVec_5_dummy2_2
assign m_m_slotVec_5_dummy2_2$D_IN = 1'd1 ;
assign m_m_slotVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
// submodule m_m_slotVec_6_dummy2_0
assign m_m_slotVec_6_dummy2_0$D_IN = 1'd1 ;
assign m_m_slotVec_6_dummy2_0$EN = m_m_stateVec_6_lat_0$whas ;
// submodule m_m_slotVec_6_dummy2_1
assign m_m_slotVec_6_dummy2_1$D_IN = 1'b0 ;
assign m_m_slotVec_6_dummy2_1$EN = 1'b0 ;
// submodule m_m_slotVec_6_dummy2_2
assign m_m_slotVec_6_dummy2_2$D_IN = 1'd1 ;
assign m_m_slotVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
// submodule m_m_slotVec_7_dummy2_0
assign m_m_slotVec_7_dummy2_0$D_IN = 1'd1 ;
assign m_m_slotVec_7_dummy2_0$EN = m_m_stateVec_7_lat_0$whas ;
// submodule m_m_slotVec_7_dummy2_1
assign m_m_slotVec_7_dummy2_1$D_IN = 1'b0 ;
assign m_m_slotVec_7_dummy2_1$EN = 1'b0 ;
// submodule m_m_slotVec_7_dummy2_2
assign m_m_slotVec_7_dummy2_2$D_IN = 1'd1 ;
assign m_m_slotVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
// submodule m_m_stateVec_0_dummy2_0
assign m_m_stateVec_0_dummy2_0$D_IN = 1'd1 ;
assign m_m_stateVec_0_dummy2_0$EN = m_m_stateVec_0_lat_0$whas ;
// submodule m_m_stateVec_0_dummy2_1
assign m_m_stateVec_0_dummy2_1$D_IN = 1'd1 ;
assign m_m_stateVec_0_dummy2_1$EN = m_m_stateVec_0_lat_1$whas ;
// submodule m_m_stateVec_0_dummy2_2
assign m_m_stateVec_0_dummy2_2$D_IN = 1'd1 ;
assign m_m_stateVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
// submodule m_m_stateVec_1_dummy2_0
assign m_m_stateVec_1_dummy2_0$D_IN = 1'd1 ;
assign m_m_stateVec_1_dummy2_0$EN = m_m_stateVec_1_lat_0$whas ;
// submodule m_m_stateVec_1_dummy2_1
assign m_m_stateVec_1_dummy2_1$D_IN = 1'd1 ;
assign m_m_stateVec_1_dummy2_1$EN = m_m_stateVec_1_lat_1$whas ;
// submodule m_m_stateVec_1_dummy2_2
assign m_m_stateVec_1_dummy2_2$D_IN = 1'd1 ;
assign m_m_stateVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
// submodule m_m_stateVec_2_dummy2_0
assign m_m_stateVec_2_dummy2_0$D_IN = 1'd1 ;
assign m_m_stateVec_2_dummy2_0$EN = m_m_stateVec_2_lat_0$whas ;
// submodule m_m_stateVec_2_dummy2_1
assign m_m_stateVec_2_dummy2_1$D_IN = 1'd1 ;
assign m_m_stateVec_2_dummy2_1$EN = m_m_stateVec_2_lat_1$whas ;
// submodule m_m_stateVec_2_dummy2_2
assign m_m_stateVec_2_dummy2_2$D_IN = 1'd1 ;
assign m_m_stateVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
// submodule m_m_stateVec_3_dummy2_0
assign m_m_stateVec_3_dummy2_0$D_IN = 1'd1 ;
assign m_m_stateVec_3_dummy2_0$EN = m_m_stateVec_3_lat_0$whas ;
// submodule m_m_stateVec_3_dummy2_1
assign m_m_stateVec_3_dummy2_1$D_IN = 1'd1 ;
assign m_m_stateVec_3_dummy2_1$EN = m_m_stateVec_3_lat_1$whas ;
// submodule m_m_stateVec_3_dummy2_2
assign m_m_stateVec_3_dummy2_2$D_IN = 1'd1 ;
assign m_m_stateVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
// submodule m_m_stateVec_4_dummy2_0
assign m_m_stateVec_4_dummy2_0$D_IN = 1'd1 ;
assign m_m_stateVec_4_dummy2_0$EN = m_m_stateVec_4_dummy_1_0$wget ;
// submodule m_m_stateVec_4_dummy2_1
assign m_m_stateVec_4_dummy2_1$D_IN = 1'd1 ;
assign m_m_stateVec_4_dummy2_1$EN = m_m_stateVec_4_lat_1$whas ;
// submodule m_m_stateVec_4_dummy2_2
assign m_m_stateVec_4_dummy2_2$D_IN = 1'd1 ;
assign m_m_stateVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
// submodule m_m_stateVec_5_dummy2_0
assign m_m_stateVec_5_dummy2_0$D_IN = 1'd1 ;
assign m_m_stateVec_5_dummy2_0$EN = m_m_stateVec_5_lat_0$whas ;
// submodule m_m_stateVec_5_dummy2_1
assign m_m_stateVec_5_dummy2_1$D_IN = 1'd1 ;
assign m_m_stateVec_5_dummy2_1$EN = m_m_stateVec_5_lat_1$whas ;
// submodule m_m_stateVec_5_dummy2_2
assign m_m_stateVec_5_dummy2_2$D_IN = 1'd1 ;
assign m_m_stateVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
// submodule m_m_stateVec_6_dummy2_0
assign m_m_stateVec_6_dummy2_0$D_IN = 1'd1 ;
assign m_m_stateVec_6_dummy2_0$EN = m_m_stateVec_6_lat_0$whas ;
// submodule m_m_stateVec_6_dummy2_1
assign m_m_stateVec_6_dummy2_1$D_IN = 1'd1 ;
assign m_m_stateVec_6_dummy2_1$EN = m_m_stateVec_6_lat_1$whas ;
// submodule m_m_stateVec_6_dummy2_2
assign m_m_stateVec_6_dummy2_2$D_IN = 1'd1 ;
assign m_m_stateVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
// submodule m_m_stateVec_7_dummy2_0
assign m_m_stateVec_7_dummy2_0$D_IN = 1'd1 ;
assign m_m_stateVec_7_dummy2_0$EN = m_m_stateVec_7_lat_0$whas ;
// submodule m_m_stateVec_7_dummy2_1
assign m_m_stateVec_7_dummy2_1$D_IN = 1'd1 ;
assign m_m_stateVec_7_dummy2_1$EN = m_m_stateVec_7_lat_1$whas ;
// submodule m_m_stateVec_7_dummy2_2
assign m_m_stateVec_7_dummy2_2$D_IN = 1'd1 ;
assign m_m_stateVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
// submodule m_m_succFile
assign m_m_succFile$ADDR_1 = pipelineResp_getSucc_n ;
assign m_m_succFile$ADDR_2 = 3'h0 ;
assign m_m_succFile$ADDR_3 = 3'h0 ;
assign m_m_succFile$ADDR_4 = 3'h0 ;
assign m_m_succFile$ADDR_5 = 3'h0 ;
assign m_m_succFile$ADDR_IN = pipelineResp_setSucc_n ;
assign m_m_succFile$D_IN = pipelineResp_setSucc_succ[2:0] ;
assign m_m_succFile$WE = EN_pipelineResp_setSucc ;
// submodule m_m_succValidVec_0_dummy2_0
assign m_m_succValidVec_0_dummy2_0$D_IN = 1'd1 ;
assign m_m_succValidVec_0_dummy2_0$EN = m_m_succValidVec_0_lat_0$whas ;
// submodule m_m_succValidVec_0_dummy2_1
assign m_m_succValidVec_0_dummy2_1$D_IN = 1'b0 ;
assign m_m_succValidVec_0_dummy2_1$EN = 1'b0 ;
// submodule m_m_succValidVec_0_dummy2_2
assign m_m_succValidVec_0_dummy2_2$D_IN = 1'd1 ;
assign m_m_succValidVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
// submodule m_m_succValidVec_1_dummy2_0
assign m_m_succValidVec_1_dummy2_0$D_IN = 1'd1 ;
assign m_m_succValidVec_1_dummy2_0$EN = m_m_succValidVec_1_lat_0$whas ;
// submodule m_m_succValidVec_1_dummy2_1
assign m_m_succValidVec_1_dummy2_1$D_IN = 1'b0 ;
assign m_m_succValidVec_1_dummy2_1$EN = 1'b0 ;
// submodule m_m_succValidVec_1_dummy2_2
assign m_m_succValidVec_1_dummy2_2$D_IN = 1'd1 ;
assign m_m_succValidVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
// submodule m_m_succValidVec_2_dummy2_0
assign m_m_succValidVec_2_dummy2_0$D_IN = 1'd1 ;
assign m_m_succValidVec_2_dummy2_0$EN = m_m_succValidVec_2_lat_0$whas ;
// submodule m_m_succValidVec_2_dummy2_1
assign m_m_succValidVec_2_dummy2_1$D_IN = 1'b0 ;
assign m_m_succValidVec_2_dummy2_1$EN = 1'b0 ;
// submodule m_m_succValidVec_2_dummy2_2
assign m_m_succValidVec_2_dummy2_2$D_IN = 1'd1 ;
assign m_m_succValidVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
// submodule m_m_succValidVec_3_dummy2_0
assign m_m_succValidVec_3_dummy2_0$D_IN = 1'd1 ;
assign m_m_succValidVec_3_dummy2_0$EN = m_m_succValidVec_3_lat_0$whas ;
// submodule m_m_succValidVec_3_dummy2_1
assign m_m_succValidVec_3_dummy2_1$D_IN = 1'b0 ;
assign m_m_succValidVec_3_dummy2_1$EN = 1'b0 ;
// submodule m_m_succValidVec_3_dummy2_2
assign m_m_succValidVec_3_dummy2_2$D_IN = 1'd1 ;
assign m_m_succValidVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
// submodule m_m_succValidVec_4_dummy2_0
assign m_m_succValidVec_4_dummy2_0$D_IN = 1'd1 ;
assign m_m_succValidVec_4_dummy2_0$EN = m_m_succValidVec_4_lat_0$whas ;
// submodule m_m_succValidVec_4_dummy2_1
assign m_m_succValidVec_4_dummy2_1$D_IN = 1'b0 ;
assign m_m_succValidVec_4_dummy2_1$EN = 1'b0 ;
// submodule m_m_succValidVec_4_dummy2_2
assign m_m_succValidVec_4_dummy2_2$D_IN = 1'd1 ;
assign m_m_succValidVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
// submodule m_m_succValidVec_5_dummy2_0
assign m_m_succValidVec_5_dummy2_0$D_IN = 1'd1 ;
assign m_m_succValidVec_5_dummy2_0$EN = m_m_succValidVec_5_lat_0$whas ;
// submodule m_m_succValidVec_5_dummy2_1
assign m_m_succValidVec_5_dummy2_1$D_IN = 1'b0 ;
assign m_m_succValidVec_5_dummy2_1$EN = 1'b0 ;
// submodule m_m_succValidVec_5_dummy2_2
assign m_m_succValidVec_5_dummy2_2$D_IN = 1'd1 ;
assign m_m_succValidVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
// submodule m_m_succValidVec_6_dummy2_0
assign m_m_succValidVec_6_dummy2_0$D_IN = 1'd1 ;
assign m_m_succValidVec_6_dummy2_0$EN = m_m_succValidVec_6_lat_0$whas ;
// submodule m_m_succValidVec_6_dummy2_1
assign m_m_succValidVec_6_dummy2_1$D_IN = 1'b0 ;
assign m_m_succValidVec_6_dummy2_1$EN = 1'b0 ;
// submodule m_m_succValidVec_6_dummy2_2
assign m_m_succValidVec_6_dummy2_2$D_IN = 1'd1 ;
assign m_m_succValidVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
// submodule m_m_succValidVec_7_dummy2_0
assign m_m_succValidVec_7_dummy2_0$D_IN = 1'd1 ;
assign m_m_succValidVec_7_dummy2_0$EN = m_m_succValidVec_7_lat_0$whas ;
// submodule m_m_succValidVec_7_dummy2_1
assign m_m_succValidVec_7_dummy2_1$D_IN = 1'b0 ;
assign m_m_succValidVec_7_dummy2_1$EN = 1'b0 ;
// submodule m_m_succValidVec_7_dummy2_2
assign m_m_succValidVec_7_dummy2_2$D_IN = 1'd1 ;
assign m_m_succValidVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
// remaining internal signals
assign IF_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m__ETC___d1457 =
(IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1409 &&
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1414) ?
(IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1420 ?
3'd3 :
3'd2) :
(IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1409 ?
3'd1 :
3'd0) ;
assign IF_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m__ETC___d1458 =
(IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1409 &&
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1414 &&
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1420 &&
(IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 ==
3'd3 ||
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 ==
3'd0 ||
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 ==
3'd1 ||
!IF_m_m_reqVec_3_dummy2_0_read__76_AND_m_m_reqV_ETC___d1313 ||
m_m_succValidVec_3_dummy2_0_read__200_AND_m_m__ETC___d1205)) ?
IF_IF_m_m_stateVec_4_dummy2_0_read__128_AND_m__ETC___d1454 :
IF_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m__ETC___d1457 ;
assign IF_IF_m_m_stateVec_4_dummy2_0_read__128_AND_m__ETC___d1454 =
(IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1432 &&
(IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 ==
3'd3 ||
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 ==
3'd0 ||
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 ==
3'd1 ||
!IF_m_m_reqVec_5_dummy2_0_read__88_AND_m_m_reqV_ETC___d1353 ||
m_m_succValidVec_5_dummy2_0_read__212_AND_m_m__ETC___d1217)) ?
((IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 ==
3'd3 ||
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 ==
3'd0 ||
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 ==
3'd1 ||
!IF_m_m_reqVec_6_dummy2_0_read__94_AND_m_m_reqV_ETC___d1373 ||
m_m_succValidVec_6_dummy2_0_read__218_AND_m_m__ETC___d1223) ?
3'd7 :
3'd6) :
(IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1432 ?
3'd5 :
3'd4) ;
assign IF_m_m_reqVec_0_dummy2_0_read__58_AND_m_m_reqV_ETC___d1255 =
n__read_addr__h98103[63:6] ==
pipelineResp_searchEndOfChain_addr[63:6] ;
assign IF_m_m_reqVec_1_dummy2_0_read__64_AND_m_m_reqV_ETC___d1274 =
n__read_addr__h98184[63:6] ==
pipelineResp_searchEndOfChain_addr[63:6] ;
assign IF_m_m_reqVec_2_dummy2_0_read__70_AND_m_m_reqV_ETC___d1294 =
n__read_addr__h98265[63:6] ==
pipelineResp_searchEndOfChain_addr[63:6] ;
assign IF_m_m_reqVec_3_dummy2_0_read__76_AND_m_m_reqV_ETC___d1313 =
n__read_addr__h98346[63:6] ==
pipelineResp_searchEndOfChain_addr[63:6] ;
assign IF_m_m_reqVec_4_dummy2_0_read__82_AND_m_m_reqV_ETC___d1334 =
n__read_addr__h98427[63:6] ==
pipelineResp_searchEndOfChain_addr[63:6] ;
assign IF_m_m_reqVec_5_dummy2_0_read__88_AND_m_m_reqV_ETC___d1353 =
n__read_addr__h98508[63:6] ==
pipelineResp_searchEndOfChain_addr[63:6] ;
assign IF_m_m_reqVec_6_dummy2_0_read__94_AND_m_m_reqV_ETC___d1373 =
n__read_addr__h98589[63:6] ==
pipelineResp_searchEndOfChain_addr[63:6] ;
assign IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280 =
m_m_resultVec_0_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[64:33] :
m_m_resultVec_0_rl[64:33] ;
assign IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 =
m_m_resultVec_0_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[31:0] :
m_m_resultVec_0_rl[31:0] ;
assign IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306 =
{ m_m_stateVec_0_lat_2$whas ||
(m_m_resultVec_0_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[65] :
m_m_resultVec_0_rl[65]),
m_m_stateVec_0_lat_2$whas ?
32'b01010101010101010101010101010101 :
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280,
!m_m_stateVec_0_lat_2$whas &&
(m_m_resultVec_0_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[32] :
m_m_resultVec_0_rl[32]),
m_m_stateVec_0_lat_2$whas ?
32'hAAAAAAAA :
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 } ;
assign IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348 =
m_m_resultVec_1_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[64:33] :
m_m_resultVec_1_rl[64:33] ;
assign IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 =
m_m_resultVec_1_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[31:0] :
m_m_resultVec_1_rl[31:0] ;
assign IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374 =
{ m_m_stateVec_1_lat_2$whas ||
(m_m_resultVec_1_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[65] :
m_m_resultVec_1_rl[65]),
m_m_stateVec_1_lat_2$whas ?
32'b01010101010101010101010101010101 :
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348,
!m_m_stateVec_1_lat_2$whas &&
(m_m_resultVec_1_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[32] :
m_m_resultVec_1_rl[32]),
m_m_stateVec_1_lat_2$whas ?
32'hAAAAAAAA :
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 } ;
assign IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416 =
m_m_resultVec_2_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[64:33] :
m_m_resultVec_2_rl[64:33] ;
assign IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 =
m_m_resultVec_2_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[31:0] :
m_m_resultVec_2_rl[31:0] ;
assign IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442 =
{ m_m_stateVec_2_lat_2$whas ||
(m_m_resultVec_2_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[65] :
m_m_resultVec_2_rl[65]),
m_m_stateVec_2_lat_2$whas ?
32'b01010101010101010101010101010101 :
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416,
!m_m_stateVec_2_lat_2$whas &&
(m_m_resultVec_2_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[32] :
m_m_resultVec_2_rl[32]),
m_m_stateVec_2_lat_2$whas ?
32'hAAAAAAAA :
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 } ;
assign IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484 =
m_m_resultVec_3_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[64:33] :
m_m_resultVec_3_rl[64:33] ;
assign IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 =
m_m_resultVec_3_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[31:0] :
m_m_resultVec_3_rl[31:0] ;
assign IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510 =
{ m_m_stateVec_3_lat_2$whas ||
(m_m_resultVec_3_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[65] :
m_m_resultVec_3_rl[65]),
m_m_stateVec_3_lat_2$whas ?
32'b01010101010101010101010101010101 :
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484,
!m_m_stateVec_3_lat_2$whas &&
(m_m_resultVec_3_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[32] :
m_m_resultVec_3_rl[32]),
m_m_stateVec_3_lat_2$whas ?
32'hAAAAAAAA :
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 } ;
assign IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552 =
m_m_resultVec_4_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[64:33] :
m_m_resultVec_4_rl[64:33] ;
assign IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 =
m_m_resultVec_4_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[31:0] :
m_m_resultVec_4_rl[31:0] ;
assign IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578 =
{ m_m_stateVec_4_lat_2$whas ||
(m_m_resultVec_4_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[65] :
m_m_resultVec_4_rl[65]),
m_m_stateVec_4_lat_2$whas ?
32'b01010101010101010101010101010101 :
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552,
!m_m_stateVec_4_lat_2$whas &&
(m_m_resultVec_4_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[32] :
m_m_resultVec_4_rl[32]),
m_m_stateVec_4_lat_2$whas ?
32'hAAAAAAAA :
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 } ;
assign IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620 =
m_m_resultVec_5_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[64:33] :
m_m_resultVec_5_rl[64:33] ;
assign IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 =
m_m_resultVec_5_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[31:0] :
m_m_resultVec_5_rl[31:0] ;
assign IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646 =
{ m_m_stateVec_5_lat_2$whas ||
(m_m_resultVec_5_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[65] :
m_m_resultVec_5_rl[65]),
m_m_stateVec_5_lat_2$whas ?
32'b01010101010101010101010101010101 :
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620,
!m_m_stateVec_5_lat_2$whas &&
(m_m_resultVec_5_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[32] :
m_m_resultVec_5_rl[32]),
m_m_stateVec_5_lat_2$whas ?
32'hAAAAAAAA :
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 } ;
assign IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688 =
m_m_resultVec_6_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[64:33] :
m_m_resultVec_6_rl[64:33] ;
assign IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 =
m_m_resultVec_6_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[31:0] :
m_m_resultVec_6_rl[31:0] ;
assign IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714 =
{ m_m_stateVec_6_lat_2$whas ||
(m_m_resultVec_6_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[65] :
m_m_resultVec_6_rl[65]),
m_m_stateVec_6_lat_2$whas ?
32'b01010101010101010101010101010101 :
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688,
!m_m_stateVec_6_lat_2$whas &&
(m_m_resultVec_6_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[32] :
m_m_resultVec_6_rl[32]),
m_m_stateVec_6_lat_2$whas ?
32'hAAAAAAAA :
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 } ;
assign IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756 =
m_m_resultVec_7_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[64:33] :
m_m_resultVec_7_rl[64:33] ;
assign IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778 =
m_m_resultVec_7_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[31:0] :
m_m_resultVec_7_rl[31:0] ;
assign IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782 =
{ m_m_stateVec_7_lat_2$whas ||
(m_m_resultVec_7_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[65] :
m_m_resultVec_7_rl[65]),
m_m_stateVec_7_lat_2$whas ?
32'b01010101010101010101010101010101 :
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756,
!m_m_stateVec_7_lat_2$whas &&
(m_m_resultVec_7_lat_0$whas ?
m_m_resultVec_0_lat_0$wget[32] :
m_m_resultVec_7_rl[32]),
m_m_stateVec_7_lat_2$whas ?
32'hAAAAAAAA :
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778 } ;
assign IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 =
(m_m_stateVec_0_dummy2_0$Q_OUT &&
m_m_stateVec_0_dummy2_1$Q_OUT &&
m_m_stateVec_0_dummy2_2$Q_OUT) ?
m_m_stateVec_0_rl :
3'd0 ;
assign IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1409 =
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 ==
3'd3 ||
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 ==
3'd0 ||
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 ==
3'd1 ||
!IF_m_m_reqVec_0_dummy2_0_read__58_AND_m_m_reqV_ETC___d1255 ||
m_m_succValidVec_0_dummy2_0_read__182_AND_m_m__ETC___d1187 ;
assign IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9 =
m_m_stateVec_0_lat_1$whas ?
3'd0 :
(m_m_stateVec_0_lat_0$whas ?
pipelineResp_setStateSlot_state :
m_m_stateVec_0_rl) ;
assign IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 =
(m_m_stateVec_1_dummy2_0$Q_OUT &&
m_m_stateVec_1_dummy2_1$Q_OUT &&
m_m_stateVec_1_dummy2_2$Q_OUT) ?
m_m_stateVec_1_rl :
3'd0 ;
assign IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1414 =
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 ==
3'd3 ||
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 ==
3'd0 ||
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 ==
3'd1 ||
!IF_m_m_reqVec_1_dummy2_0_read__64_AND_m_m_reqV_ETC___d1274 ||
m_m_succValidVec_1_dummy2_0_read__188_AND_m_m__ETC___d1193 ;
assign IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1465 =
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 ==
3'd0 &&
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 ==
3'd0 &&
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 ==
3'd0 &&
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 ==
3'd0 &&
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 ==
3'd0 &&
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 ==
3'd0 &&
IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_m_s_ETC___d1151 ==
3'd0 ;
assign IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19 =
m_m_stateVec_1_lat_1$whas ?
3'd0 :
(m_m_stateVec_1_lat_0$whas ?
pipelineResp_setStateSlot_state :
m_m_stateVec_1_rl) ;
assign IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 =
(m_m_stateVec_2_dummy2_0$Q_OUT &&
m_m_stateVec_2_dummy2_1$Q_OUT &&
m_m_stateVec_2_dummy2_2$Q_OUT) ?
m_m_stateVec_2_rl :
3'd0 ;
assign IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1420 =
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 ==
3'd3 ||
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 ==
3'd0 ||
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 ==
3'd1 ||
!IF_m_m_reqVec_2_dummy2_0_read__70_AND_m_m_reqV_ETC___d1294 ||
m_m_succValidVec_2_dummy2_0_read__194_AND_m_m__ETC___d1199 ;
assign IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29 =
m_m_stateVec_2_lat_1$whas ?
3'd0 :
(m_m_stateVec_2_lat_0$whas ?
pipelineResp_setStateSlot_state :
m_m_stateVec_2_rl) ;
assign IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 =
(m_m_stateVec_3_dummy2_0$Q_OUT &&
m_m_stateVec_3_dummy2_1$Q_OUT &&
m_m_stateVec_3_dummy2_2$Q_OUT) ?
m_m_stateVec_3_rl :
3'd0 ;
assign IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39 =
m_m_stateVec_3_lat_1$whas ?
3'd0 :
(m_m_stateVec_3_lat_0$whas ?
pipelineResp_setStateSlot_state :
m_m_stateVec_3_rl) ;
assign IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 =
(m_m_stateVec_4_dummy2_0$Q_OUT &&
m_m_stateVec_4_dummy2_1$Q_OUT &&
m_m_stateVec_4_dummy2_2$Q_OUT) ?
m_m_stateVec_4_rl :
3'd0 ;
assign IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1432 =
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 ==
3'd3 ||
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 ==
3'd0 ||
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 ==
3'd1 ||
!IF_m_m_reqVec_4_dummy2_0_read__82_AND_m_m_reqV_ETC___d1334 ||
m_m_succValidVec_4_dummy2_0_read__206_AND_m_m__ETC___d1211 ;
assign IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49 =
m_m_stateVec_4_lat_1$whas ?
3'd0 :
(m_m_stateVec_4_dummy_1_0$wget ?
pipelineResp_setStateSlot_state :
m_m_stateVec_4_rl) ;
assign IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 =
(m_m_stateVec_5_dummy2_0$Q_OUT &&
m_m_stateVec_5_dummy2_1$Q_OUT &&
m_m_stateVec_5_dummy2_2$Q_OUT) ?
m_m_stateVec_5_rl :
3'd0 ;
assign IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59 =
m_m_stateVec_5_lat_1$whas ?
3'd0 :
(m_m_stateVec_5_lat_0$whas ?
pipelineResp_setStateSlot_state :
m_m_stateVec_5_rl) ;
assign IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 =
(m_m_stateVec_6_dummy2_0$Q_OUT &&
m_m_stateVec_6_dummy2_1$Q_OUT &&
m_m_stateVec_6_dummy2_2$Q_OUT) ?
m_m_stateVec_6_rl :
3'd0 ;
assign IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69 =
m_m_stateVec_6_lat_1$whas ?
3'd0 :
(m_m_stateVec_6_lat_0$whas ?
pipelineResp_setStateSlot_state :
m_m_stateVec_6_rl) ;
assign IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_m_s_ETC___d1151 =
(m_m_stateVec_7_dummy2_0$Q_OUT &&
m_m_stateVec_7_dummy2_1$Q_OUT &&
m_m_stateVec_7_dummy2_2$Q_OUT) ?
m_m_stateVec_7_rl :
3'd0 ;
assign IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79 =
m_m_stateVec_7_lat_1$whas ?
3'd0 :
(m_m_stateVec_7_lat_0$whas ?
pipelineResp_setStateSlot_state :
m_m_stateVec_7_rl) ;
assign NOT_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_ETC___d1264 =
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 !=
3'd3 &&
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 !=
3'd0 &&
IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_m_s_ETC___d1109 !=
3'd1 &&
IF_m_m_reqVec_0_dummy2_0_read__58_AND_m_m_reqV_ETC___d1255 &&
(!m_m_succValidVec_0_dummy2_0$Q_OUT ||
!m_m_succValidVec_0_dummy2_1$Q_OUT ||
!m_m_succValidVec_0_dummy2_2$Q_OUT ||
!m_m_succValidVec_0_rl) ;
assign NOT_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_ETC___d1404 =
NOT_IF_m_m_stateVec_0_dummy2_0_read__104_AND_m_ETC___d1264 ||
NOT_IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_ETC___d1283 ||
NOT_IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_ETC___d1303 ||
NOT_IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_ETC___d1322 ||
NOT_IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_ETC___d1343 ||
NOT_IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_ETC___d1362 ||
NOT_IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_ETC___d1382 ||
NOT_IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_ETC___d1401 ;
assign NOT_IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_ETC___d1283 =
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 !=
3'd3 &&
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 !=
3'd0 &&
IF_m_m_stateVec_1_dummy2_0_read__110_AND_m_m_s_ETC___d1115 !=
3'd1 &&
IF_m_m_reqVec_1_dummy2_0_read__64_AND_m_m_reqV_ETC___d1274 &&
(!m_m_succValidVec_1_dummy2_0$Q_OUT ||
!m_m_succValidVec_1_dummy2_1$Q_OUT ||
!m_m_succValidVec_1_dummy2_2$Q_OUT ||
!m_m_succValidVec_1_rl) ;
assign NOT_IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_ETC___d1303 =
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 !=
3'd3 &&
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 !=
3'd0 &&
IF_m_m_stateVec_2_dummy2_0_read__116_AND_m_m_s_ETC___d1121 !=
3'd1 &&
IF_m_m_reqVec_2_dummy2_0_read__70_AND_m_m_reqV_ETC___d1294 &&
(!m_m_succValidVec_2_dummy2_0$Q_OUT ||
!m_m_succValidVec_2_dummy2_1$Q_OUT ||
!m_m_succValidVec_2_dummy2_2$Q_OUT ||
!m_m_succValidVec_2_rl) ;
assign NOT_IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_ETC___d1322 =
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 !=
3'd3 &&
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 !=
3'd0 &&
IF_m_m_stateVec_3_dummy2_0_read__122_AND_m_m_s_ETC___d1127 !=
3'd1 &&
IF_m_m_reqVec_3_dummy2_0_read__76_AND_m_m_reqV_ETC___d1313 &&
(!m_m_succValidVec_3_dummy2_0$Q_OUT ||
!m_m_succValidVec_3_dummy2_1$Q_OUT ||
!m_m_succValidVec_3_dummy2_2$Q_OUT ||
!m_m_succValidVec_3_rl) ;
assign NOT_IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_ETC___d1343 =
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 !=
3'd3 &&
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 !=
3'd0 &&
IF_m_m_stateVec_4_dummy2_0_read__128_AND_m_m_s_ETC___d1133 !=
3'd1 &&
IF_m_m_reqVec_4_dummy2_0_read__82_AND_m_m_reqV_ETC___d1334 &&
(!m_m_succValidVec_4_dummy2_0$Q_OUT ||
!m_m_succValidVec_4_dummy2_1$Q_OUT ||
!m_m_succValidVec_4_dummy2_2$Q_OUT ||
!m_m_succValidVec_4_rl) ;
assign NOT_IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_ETC___d1362 =
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 !=
3'd3 &&
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 !=
3'd0 &&
IF_m_m_stateVec_5_dummy2_0_read__134_AND_m_m_s_ETC___d1139 !=
3'd1 &&
IF_m_m_reqVec_5_dummy2_0_read__88_AND_m_m_reqV_ETC___d1353 &&
(!m_m_succValidVec_5_dummy2_0$Q_OUT ||
!m_m_succValidVec_5_dummy2_1$Q_OUT ||
!m_m_succValidVec_5_dummy2_2$Q_OUT ||
!m_m_succValidVec_5_rl) ;
assign NOT_IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_ETC___d1382 =
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 !=
3'd3 &&
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 !=
3'd0 &&
IF_m_m_stateVec_6_dummy2_0_read__140_AND_m_m_s_ETC___d1145 !=
3'd1 &&
IF_m_m_reqVec_6_dummy2_0_read__94_AND_m_m_reqV_ETC___d1373 &&
(!m_m_succValidVec_6_dummy2_0$Q_OUT ||
!m_m_succValidVec_6_dummy2_1$Q_OUT ||
!m_m_succValidVec_6_dummy2_2$Q_OUT ||
!m_m_succValidVec_6_rl) ;
assign NOT_IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_ETC___d1401 =
IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_m_s_ETC___d1151 !=
3'd3 &&
IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_m_s_ETC___d1151 !=
3'd0 &&
IF_m_m_stateVec_7_dummy2_0_read__146_AND_m_m_s_ETC___d1151 !=
3'd1 &&
n__read_addr__h98670[63:6] ==
pipelineResp_searchEndOfChain_addr[63:6] &&
(!m_m_succValidVec_7_dummy2_0$Q_OUT ||
!m_m_succValidVec_7_dummy2_1$Q_OUT ||
!m_m_succValidVec_7_dummy2_2$Q_OUT ||
!m_m_succValidVec_7_rl) ;
assign NOT_m_m_resultVec_0_dummy2_1_read__93_94_OR_NO_ETC___d898 =
!m_m_resultVec_0_dummy2_1$Q_OUT ||
!m_m_resultVec_0_dummy2_2$Q_OUT ||
(m_m_resultVec_0_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[66] :
!m_m_resultVec_0_rl[66]) ;
assign NOT_m_m_resultVec_1_dummy2_1_read__99_00_OR_NO_ETC___d904 =
!m_m_resultVec_1_dummy2_1$Q_OUT ||
!m_m_resultVec_1_dummy2_2$Q_OUT ||
(m_m_resultVec_1_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[66] :
!m_m_resultVec_1_rl[66]) ;
assign NOT_m_m_resultVec_2_dummy2_1_read__05_06_OR_NO_ETC___d910 =
!m_m_resultVec_2_dummy2_1$Q_OUT ||
!m_m_resultVec_2_dummy2_2$Q_OUT ||
(m_m_resultVec_2_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[66] :
!m_m_resultVec_2_rl[66]) ;
assign NOT_m_m_resultVec_3_dummy2_1_read__11_12_OR_NO_ETC___d916 =
!m_m_resultVec_3_dummy2_1$Q_OUT ||
!m_m_resultVec_3_dummy2_2$Q_OUT ||
(m_m_resultVec_3_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[66] :
!m_m_resultVec_3_rl[66]) ;
assign NOT_m_m_resultVec_4_dummy2_1_read__17_18_OR_NO_ETC___d922 =
!m_m_resultVec_4_dummy2_1$Q_OUT ||
!m_m_resultVec_4_dummy2_2$Q_OUT ||
(m_m_resultVec_4_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[66] :
!m_m_resultVec_4_rl[66]) ;
assign NOT_m_m_resultVec_5_dummy2_1_read__23_24_OR_NO_ETC___d928 =
!m_m_resultVec_5_dummy2_1$Q_OUT ||
!m_m_resultVec_5_dummy2_2$Q_OUT ||
(m_m_resultVec_5_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[66] :
!m_m_resultVec_5_rl[66]) ;
assign NOT_m_m_resultVec_6_dummy2_1_read__29_30_OR_NO_ETC___d934 =
!m_m_resultVec_6_dummy2_1$Q_OUT ||
!m_m_resultVec_6_dummy2_2$Q_OUT ||
(m_m_resultVec_6_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[66] :
!m_m_resultVec_6_rl[66]) ;
assign NOT_m_m_resultVec_7_dummy2_1_read__35_36_OR_NO_ETC___d940 =
!m_m_resultVec_7_dummy2_1$Q_OUT ||
!m_m_resultVec_7_dummy2_2$Q_OUT ||
(m_m_resultVec_7_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[66] :
!m_m_resultVec_7_rl[66]) ;
assign m_m_slotVec_0_dummy2_0_read__007_AND_m_m_slotV_ETC___d1084 =
m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
m_m_slotVec_0_dummy2_2$Q_OUT &&
m_m_slotVec_0_rl[0] ;
assign m_m_slotVec_1_dummy2_0_read__014_AND_m_m_slotV_ETC___d1086 =
m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
m_m_slotVec_1_dummy2_2$Q_OUT &&
m_m_slotVec_1_rl[0] ;
assign m_m_slotVec_2_dummy2_0_read__021_AND_m_m_slotV_ETC___d1088 =
m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
m_m_slotVec_2_dummy2_2$Q_OUT &&
m_m_slotVec_2_rl[0] ;
assign m_m_slotVec_3_dummy2_0_read__028_AND_m_m_slotV_ETC___d1090 =
m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
m_m_slotVec_3_dummy2_2$Q_OUT &&
m_m_slotVec_3_rl[0] ;
assign m_m_slotVec_4_dummy2_0_read__035_AND_m_m_slotV_ETC___d1092 =
m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
m_m_slotVec_4_dummy2_2$Q_OUT &&
m_m_slotVec_4_rl[0] ;
assign m_m_slotVec_5_dummy2_0_read__042_AND_m_m_slotV_ETC___d1094 =
m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
m_m_slotVec_5_dummy2_2$Q_OUT &&
m_m_slotVec_5_rl[0] ;
assign m_m_slotVec_6_dummy2_0_read__049_AND_m_m_slotV_ETC___d1096 =
m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
m_m_slotVec_6_dummy2_2$Q_OUT &&
m_m_slotVec_6_rl[0] ;
assign m_m_slotVec_7_dummy2_0_read__056_AND_m_m_slotV_ETC___d1098 =
m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
m_m_slotVec_7_dummy2_2$Q_OUT &&
m_m_slotVec_7_rl[0] ;
assign m_m_succValidVec_0_dummy2_0_read__182_AND_m_m__ETC___d1187 =
m_m_succValidVec_0_dummy2_0$Q_OUT &&
m_m_succValidVec_0_dummy2_1$Q_OUT &&
m_m_succValidVec_0_dummy2_2$Q_OUT &&
m_m_succValidVec_0_rl ;
assign m_m_succValidVec_1_dummy2_0_read__188_AND_m_m__ETC___d1193 =
m_m_succValidVec_1_dummy2_0$Q_OUT &&
m_m_succValidVec_1_dummy2_1$Q_OUT &&
m_m_succValidVec_1_dummy2_2$Q_OUT &&
m_m_succValidVec_1_rl ;
assign m_m_succValidVec_2_dummy2_0_read__194_AND_m_m__ETC___d1199 =
m_m_succValidVec_2_dummy2_0$Q_OUT &&
m_m_succValidVec_2_dummy2_1$Q_OUT &&
m_m_succValidVec_2_dummy2_2$Q_OUT &&
m_m_succValidVec_2_rl ;
assign m_m_succValidVec_3_dummy2_0_read__200_AND_m_m__ETC___d1205 =
m_m_succValidVec_3_dummy2_0$Q_OUT &&
m_m_succValidVec_3_dummy2_1$Q_OUT &&
m_m_succValidVec_3_dummy2_2$Q_OUT &&
m_m_succValidVec_3_rl ;
assign m_m_succValidVec_4_dummy2_0_read__206_AND_m_m__ETC___d1211 =
m_m_succValidVec_4_dummy2_0$Q_OUT &&
m_m_succValidVec_4_dummy2_1$Q_OUT &&
m_m_succValidVec_4_dummy2_2$Q_OUT &&
m_m_succValidVec_4_rl ;
assign m_m_succValidVec_5_dummy2_0_read__212_AND_m_m__ETC___d1217 =
m_m_succValidVec_5_dummy2_0$Q_OUT &&
m_m_succValidVec_5_dummy2_1$Q_OUT &&
m_m_succValidVec_5_dummy2_2$Q_OUT &&
m_m_succValidVec_5_rl ;
assign m_m_succValidVec_6_dummy2_0_read__218_AND_m_m__ETC___d1223 =
m_m_succValidVec_6_dummy2_0$Q_OUT &&
m_m_succValidVec_6_dummy2_1$Q_OUT &&
m_m_succValidVec_6_dummy2_2$Q_OUT &&
m_m_succValidVec_6_rl ;
assign n__read_addr__h98103 =
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
m_m_reqVec_0_dummy2_2$Q_OUT) ?
m_m_reqVec_0_rl :
64'd0 ;
assign n__read_addr__h98184 =
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
m_m_reqVec_1_dummy2_2$Q_OUT) ?
m_m_reqVec_1_rl :
64'd0 ;
assign n__read_addr__h98265 =
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
m_m_reqVec_2_dummy2_2$Q_OUT) ?
m_m_reqVec_2_rl :
64'd0 ;
assign n__read_addr__h98346 =
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
m_m_reqVec_3_dummy2_2$Q_OUT) ?
m_m_reqVec_3_rl :
64'd0 ;
assign n__read_addr__h98427 =
(m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
m_m_reqVec_4_dummy2_2$Q_OUT) ?
m_m_reqVec_4_rl :
64'd0 ;
assign n__read_addr__h98508 =
(m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
m_m_reqVec_5_dummy2_2$Q_OUT) ?
m_m_reqVec_5_rl :
64'd0 ;
assign n__read_addr__h98589 =
(m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
m_m_reqVec_6_dummy2_2$Q_OUT) ?
m_m_reqVec_6_rl :
64'd0 ;
assign n__read_addr__h98670 =
(m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
m_m_reqVec_7_dummy2_2$Q_OUT) ?
m_m_reqVec_7_rl :
64'd0 ;
assign n__read_repTag__h98815 =
(m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
m_m_slotVec_0_dummy2_2$Q_OUT) ?
m_m_slotVec_0_rl[52:1] :
52'd0 ;
assign n__read_repTag__h98900 =
(m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
m_m_slotVec_1_dummy2_2$Q_OUT) ?
m_m_slotVec_1_rl[52:1] :
52'd0 ;
assign n__read_repTag__h98985 =
(m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
m_m_slotVec_2_dummy2_2$Q_OUT) ?
m_m_slotVec_2_rl[52:1] :
52'd0 ;
assign n__read_repTag__h99070 =
(m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
m_m_slotVec_3_dummy2_2$Q_OUT) ?
m_m_slotVec_3_rl[52:1] :
52'd0 ;
assign n__read_repTag__h99155 =
(m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
m_m_slotVec_4_dummy2_2$Q_OUT) ?
m_m_slotVec_4_rl[52:1] :
52'd0 ;
assign n__read_repTag__h99240 =
(m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
m_m_slotVec_5_dummy2_2$Q_OUT) ?
m_m_slotVec_5_rl[52:1] :
52'd0 ;
assign n__read_repTag__h99325 =
(m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
m_m_slotVec_6_dummy2_2$Q_OUT) ?
m_m_slotVec_6_rl[52:1] :
52'd0 ;
assign n__read_repTag__h99410 =
(m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
m_m_slotVec_7_dummy2_2$Q_OUT) ?
m_m_slotVec_7_rl[52:1] :
52'd0 ;
assign n__read_way__h98814 =
(m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
m_m_slotVec_0_dummy2_2$Q_OUT) ?
m_m_slotVec_0_rl[55:53] :
3'd0 ;
assign n__read_way__h98899 =
(m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
m_m_slotVec_1_dummy2_2$Q_OUT) ?
m_m_slotVec_1_rl[55:53] :
3'd0 ;
assign n__read_way__h98984 =
(m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
m_m_slotVec_2_dummy2_2$Q_OUT) ?
m_m_slotVec_2_rl[55:53] :
3'd0 ;
assign n__read_way__h99069 =
(m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
m_m_slotVec_3_dummy2_2$Q_OUT) ?
m_m_slotVec_3_rl[55:53] :
3'd0 ;
assign n__read_way__h99154 =
(m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
m_m_slotVec_4_dummy2_2$Q_OUT) ?
m_m_slotVec_4_rl[55:53] :
3'd0 ;
assign n__read_way__h99239 =
(m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
m_m_slotVec_5_dummy2_2$Q_OUT) ?
m_m_slotVec_5_rl[55:53] :
3'd0 ;
assign n__read_way__h99324 =
(m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
m_m_slotVec_6_dummy2_2$Q_OUT) ?
m_m_slotVec_6_rl[55:53] :
3'd0 ;
assign n__read_way__h99409 =
(m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
m_m_slotVec_7_dummy2_2$Q_OUT) ?
m_m_slotVec_7_rl[55:53] :
3'd0 ;
always@(sendRsToP_cRq_getSlot_n or
n__read_repTag__h98815 or
n__read_repTag__h98900 or
n__read_repTag__h98985 or
n__read_repTag__h99070 or
n__read_repTag__h99155 or
n__read_repTag__h99240 or
n__read_repTag__h99325 or n__read_repTag__h99410)
begin
case (sendRsToP_cRq_getSlot_n)
3'd0: x__h99438 = n__read_repTag__h98815;
3'd1: x__h99438 = n__read_repTag__h98900;
3'd2: x__h99438 = n__read_repTag__h98985;
3'd3: x__h99438 = n__read_repTag__h99070;
3'd4: x__h99438 = n__read_repTag__h99155;
3'd5: x__h99438 = n__read_repTag__h99240;
3'd6: x__h99438 = n__read_repTag__h99325;
3'd7: x__h99438 = n__read_repTag__h99410;
endcase
end
always@(sendRqToP_getSlot_n or
n__read_repTag__h98815 or
n__read_repTag__h98900 or
n__read_repTag__h98985 or
n__read_repTag__h99070 or
n__read_repTag__h99155 or
n__read_repTag__h99240 or
n__read_repTag__h99325 or n__read_repTag__h99410)
begin
case (sendRqToP_getSlot_n)
3'd0: x__h99566 = n__read_repTag__h98815;
3'd1: x__h99566 = n__read_repTag__h98900;
3'd2: x__h99566 = n__read_repTag__h98985;
3'd3: x__h99566 = n__read_repTag__h99070;
3'd4: x__h99566 = n__read_repTag__h99155;
3'd5: x__h99566 = n__read_repTag__h99240;
3'd6: x__h99566 = n__read_repTag__h99325;
3'd7: x__h99566 = n__read_repTag__h99410;
endcase
end
always@(pipelineResp_getSlot_n or
n__read_repTag__h98815 or
n__read_repTag__h98900 or
n__read_repTag__h98985 or
n__read_repTag__h99070 or
n__read_repTag__h99155 or
n__read_repTag__h99240 or
n__read_repTag__h99325 or n__read_repTag__h99410)
begin
case (pipelineResp_getSlot_n)
3'd0: x__h100344 = n__read_repTag__h98815;
3'd1: x__h100344 = n__read_repTag__h98900;
3'd2: x__h100344 = n__read_repTag__h98985;
3'd3: x__h100344 = n__read_repTag__h99070;
3'd4: x__h100344 = n__read_repTag__h99155;
3'd5: x__h100344 = n__read_repTag__h99240;
3'd6: x__h100344 = n__read_repTag__h99325;
3'd7: x__h100344 = n__read_repTag__h99410;
endcase
end
always@(sendRsToP_cRq_getSlot_n or
n__read_way__h98814 or
n__read_way__h98899 or
n__read_way__h98984 or
n__read_way__h99069 or
n__read_way__h99154 or
n__read_way__h99239 or n__read_way__h99324 or n__read_way__h99409)
begin
case (sendRsToP_cRq_getSlot_n)
3'd0: x__h98681 = n__read_way__h98814;
3'd1: x__h98681 = n__read_way__h98899;
3'd2: x__h98681 = n__read_way__h98984;
3'd3: x__h98681 = n__read_way__h99069;
3'd4: x__h98681 = n__read_way__h99154;
3'd5: x__h98681 = n__read_way__h99239;
3'd6: x__h98681 = n__read_way__h99324;
3'd7: x__h98681 = n__read_way__h99409;
endcase
end
always@(sendRqToP_getSlot_n or
n__read_way__h98814 or
n__read_way__h98899 or
n__read_way__h98984 or
n__read_way__h99069 or
n__read_way__h99154 or
n__read_way__h99239 or n__read_way__h99324 or n__read_way__h99409)
begin
case (sendRqToP_getSlot_n)
3'd0: x__h99529 = n__read_way__h98814;
3'd1: x__h99529 = n__read_way__h98899;
3'd2: x__h99529 = n__read_way__h98984;
3'd3: x__h99529 = n__read_way__h99069;
3'd4: x__h99529 = n__read_way__h99154;
3'd5: x__h99529 = n__read_way__h99239;
3'd6: x__h99529 = n__read_way__h99324;
3'd7: x__h99529 = n__read_way__h99409;
endcase
end
always@(pipelineResp_getSlot_n or
n__read_way__h98814 or
n__read_way__h98899 or
n__read_way__h98984 or
n__read_way__h99069 or
n__read_way__h99154 or
n__read_way__h99239 or n__read_way__h99324 or n__read_way__h99409)
begin
case (pipelineResp_getSlot_n)
3'd0: x__h100307 = n__read_way__h98814;
3'd1: x__h100307 = n__read_way__h98899;
3'd2: x__h100307 = n__read_way__h98984;
3'd3: x__h100307 = n__read_way__h99069;
3'd4: x__h100307 = n__read_way__h99154;
3'd5: x__h100307 = n__read_way__h99239;
3'd6: x__h100307 = n__read_way__h99324;
3'd7: x__h100307 = n__read_way__h99409;
endcase
end
always@(pipelineResp_getSucc_n or
m_m_succValidVec_0_dummy2_0_read__182_AND_m_m__ETC___d1187 or
m_m_succValidVec_1_dummy2_0_read__188_AND_m_m__ETC___d1193 or
m_m_succValidVec_2_dummy2_0_read__194_AND_m_m__ETC___d1199 or
m_m_succValidVec_3_dummy2_0_read__200_AND_m_m__ETC___d1205 or
m_m_succValidVec_4_dummy2_0_read__206_AND_m_m__ETC___d1211 or
m_m_succValidVec_5_dummy2_0_read__212_AND_m_m__ETC___d1217 or
m_m_succValidVec_6_dummy2_0_read__218_AND_m_m__ETC___d1223 or
m_m_succValidVec_7_dummy2_0$Q_OUT or
m_m_succValidVec_7_dummy2_1$Q_OUT or
m_m_succValidVec_7_dummy2_2$Q_OUT or m_m_succValidVec_7_rl)
begin
case (pipelineResp_getSucc_n)
3'd0:
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231 =
m_m_succValidVec_0_dummy2_0_read__182_AND_m_m__ETC___d1187;
3'd1:
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231 =
m_m_succValidVec_1_dummy2_0_read__188_AND_m_m__ETC___d1193;
3'd2:
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231 =
m_m_succValidVec_2_dummy2_0_read__194_AND_m_m__ETC___d1199;
3'd3:
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231 =
m_m_succValidVec_3_dummy2_0_read__200_AND_m_m__ETC___d1205;
3'd4:
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231 =
m_m_succValidVec_4_dummy2_0_read__206_AND_m_m__ETC___d1211;
3'd5:
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231 =
m_m_succValidVec_5_dummy2_0_read__212_AND_m_m__ETC___d1217;
3'd6:
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231 =
m_m_succValidVec_6_dummy2_0_read__218_AND_m_m__ETC___d1223;
3'd7:
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__182__ETC___d1231 =
m_m_succValidVec_7_dummy2_0$Q_OUT &&
m_m_succValidVec_7_dummy2_1$Q_OUT &&
m_m_succValidVec_7_dummy2_2$Q_OUT &&
m_m_succValidVec_7_rl;
endcase
end
always@(sendRsToP_cRq_getSlot_n or
m_m_slotVec_0_dummy2_0_read__007_AND_m_m_slotV_ETC___d1084 or
m_m_slotVec_1_dummy2_0_read__014_AND_m_m_slotV_ETC___d1086 or
m_m_slotVec_2_dummy2_0_read__021_AND_m_m_slotV_ETC___d1088 or
m_m_slotVec_3_dummy2_0_read__028_AND_m_m_slotV_ETC___d1090 or
m_m_slotVec_4_dummy2_0_read__035_AND_m_m_slotV_ETC___d1092 or
m_m_slotVec_5_dummy2_0_read__042_AND_m_m_slotV_ETC___d1094 or
m_m_slotVec_6_dummy2_0_read__049_AND_m_m_slotV_ETC___d1096 or
m_m_slotVec_7_dummy2_0_read__056_AND_m_m_slotV_ETC___d1098)
begin
case (sendRsToP_cRq_getSlot_n)
3'd0:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 =
m_m_slotVec_0_dummy2_0_read__007_AND_m_m_slotV_ETC___d1084;
3'd1:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 =
m_m_slotVec_1_dummy2_0_read__014_AND_m_m_slotV_ETC___d1086;
3'd2:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 =
m_m_slotVec_2_dummy2_0_read__021_AND_m_m_slotV_ETC___d1088;
3'd3:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 =
m_m_slotVec_3_dummy2_0_read__028_AND_m_m_slotV_ETC___d1090;
3'd4:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 =
m_m_slotVec_4_dummy2_0_read__035_AND_m_m_slotV_ETC___d1092;
3'd5:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 =
m_m_slotVec_5_dummy2_0_read__042_AND_m_m_slotV_ETC___d1094;
3'd6:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 =
m_m_slotVec_6_dummy2_0_read__049_AND_m_m_slotV_ETC___d1096;
3'd7:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1100 =
m_m_slotVec_7_dummy2_0_read__056_AND_m_m_slotV_ETC___d1098;
endcase
end
always@(sendRqToP_getSlot_n or
m_m_slotVec_0_dummy2_0_read__007_AND_m_m_slotV_ETC___d1084 or
m_m_slotVec_1_dummy2_0_read__014_AND_m_m_slotV_ETC___d1086 or
m_m_slotVec_2_dummy2_0_read__021_AND_m_m_slotV_ETC___d1088 or
m_m_slotVec_3_dummy2_0_read__028_AND_m_m_slotV_ETC___d1090 or
m_m_slotVec_4_dummy2_0_read__035_AND_m_m_slotV_ETC___d1092 or
m_m_slotVec_5_dummy2_0_read__042_AND_m_m_slotV_ETC___d1094 or
m_m_slotVec_6_dummy2_0_read__049_AND_m_m_slotV_ETC___d1096 or
m_m_slotVec_7_dummy2_0_read__056_AND_m_m_slotV_ETC___d1098)
begin
case (sendRqToP_getSlot_n)
3'd0:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 =
m_m_slotVec_0_dummy2_0_read__007_AND_m_m_slotV_ETC___d1084;
3'd1:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 =
m_m_slotVec_1_dummy2_0_read__014_AND_m_m_slotV_ETC___d1086;
3'd2:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 =
m_m_slotVec_2_dummy2_0_read__021_AND_m_m_slotV_ETC___d1088;
3'd3:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 =
m_m_slotVec_3_dummy2_0_read__028_AND_m_m_slotV_ETC___d1090;
3'd4:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 =
m_m_slotVec_4_dummy2_0_read__035_AND_m_m_slotV_ETC___d1092;
3'd5:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 =
m_m_slotVec_5_dummy2_0_read__042_AND_m_m_slotV_ETC___d1094;
3'd6:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 =
m_m_slotVec_6_dummy2_0_read__049_AND_m_m_slotV_ETC___d1096;
3'd7:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1103 =
m_m_slotVec_7_dummy2_0_read__056_AND_m_m_slotV_ETC___d1098;
endcase
end
always@(pipelineResp_getSlot_n or
m_m_slotVec_0_dummy2_0_read__007_AND_m_m_slotV_ETC___d1084 or
m_m_slotVec_1_dummy2_0_read__014_AND_m_m_slotV_ETC___d1086 or
m_m_slotVec_2_dummy2_0_read__021_AND_m_m_slotV_ETC___d1088 or
m_m_slotVec_3_dummy2_0_read__028_AND_m_m_slotV_ETC___d1090 or
m_m_slotVec_4_dummy2_0_read__035_AND_m_m_slotV_ETC___d1092 or
m_m_slotVec_5_dummy2_0_read__042_AND_m_m_slotV_ETC___d1094 or
m_m_slotVec_6_dummy2_0_read__049_AND_m_m_slotV_ETC___d1096 or
m_m_slotVec_7_dummy2_0_read__056_AND_m_m_slotV_ETC___d1098)
begin
case (pipelineResp_getSlot_n)
3'd0:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 =
m_m_slotVec_0_dummy2_0_read__007_AND_m_m_slotV_ETC___d1084;
3'd1:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 =
m_m_slotVec_1_dummy2_0_read__014_AND_m_m_slotV_ETC___d1086;
3'd2:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 =
m_m_slotVec_2_dummy2_0_read__021_AND_m_m_slotV_ETC___d1088;
3'd3:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 =
m_m_slotVec_3_dummy2_0_read__028_AND_m_m_slotV_ETC___d1090;
3'd4:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 =
m_m_slotVec_4_dummy2_0_read__035_AND_m_m_slotV_ETC___d1092;
3'd5:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 =
m_m_slotVec_5_dummy2_0_read__042_AND_m_m_slotV_ETC___d1094;
3'd6:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 =
m_m_slotVec_6_dummy2_0_read__049_AND_m_m_slotV_ETC___d1096;
3'd7:
SEL_ARR_m_m_slotVec_0_dummy2_0_read__007_AND_m_ETC___d1155 =
m_m_slotVec_7_dummy2_0_read__056_AND_m_m_slotV_ETC___d1098;
endcase
end
always@(sendRsToC_getResult_n or
NOT_m_m_resultVec_0_dummy2_1_read__93_94_OR_NO_ETC___d898 or
NOT_m_m_resultVec_1_dummy2_1_read__99_00_OR_NO_ETC___d904 or
NOT_m_m_resultVec_2_dummy2_1_read__05_06_OR_NO_ETC___d910 or
NOT_m_m_resultVec_3_dummy2_1_read__11_12_OR_NO_ETC___d916 or
NOT_m_m_resultVec_4_dummy2_1_read__17_18_OR_NO_ETC___d922 or
NOT_m_m_resultVec_5_dummy2_1_read__23_24_OR_NO_ETC___d928 or
NOT_m_m_resultVec_6_dummy2_1_read__29_30_OR_NO_ETC___d934 or
NOT_m_m_resultVec_7_dummy2_1_read__35_36_OR_NO_ETC___d940)
begin
case (sendRsToC_getResult_n)
3'd0:
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942 =
NOT_m_m_resultVec_0_dummy2_1_read__93_94_OR_NO_ETC___d898;
3'd1:
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942 =
NOT_m_m_resultVec_1_dummy2_1_read__99_00_OR_NO_ETC___d904;
3'd2:
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942 =
NOT_m_m_resultVec_2_dummy2_1_read__05_06_OR_NO_ETC___d910;
3'd3:
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942 =
NOT_m_m_resultVec_3_dummy2_1_read__11_12_OR_NO_ETC___d916;
3'd4:
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942 =
NOT_m_m_resultVec_4_dummy2_1_read__17_18_OR_NO_ETC___d922;
3'd5:
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942 =
NOT_m_m_resultVec_5_dummy2_1_read__23_24_OR_NO_ETC___d928;
3'd6:
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942 =
NOT_m_m_resultVec_6_dummy2_1_read__29_30_OR_NO_ETC___d934;
3'd7:
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__93__ETC___d942 =
NOT_m_m_resultVec_7_dummy2_1_read__35_36_OR_NO_ETC___d940;
endcase
end
always@(sendRsToC_getResult_n or
m_m_resultVec_0_lat_0$whas or
m_m_resultVec_0_lat_0$wget or
m_m_resultVec_0_rl or
m_m_resultVec_1_lat_0$whas or
m_m_resultVec_1_rl or
m_m_resultVec_2_lat_0$whas or
m_m_resultVec_2_rl or
m_m_resultVec_3_lat_0$whas or
m_m_resultVec_3_rl or
m_m_resultVec_4_lat_0$whas or
m_m_resultVec_4_rl or
m_m_resultVec_5_lat_0$whas or
m_m_resultVec_5_rl or
m_m_resultVec_6_lat_0$whas or
m_m_resultVec_6_rl or
m_m_resultVec_7_lat_0$whas or m_m_resultVec_7_rl)
begin
case (sendRsToC_getResult_n)
3'd0:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945 =
m_m_resultVec_0_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[65] :
!m_m_resultVec_0_rl[65];
3'd1:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945 =
m_m_resultVec_1_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[65] :
!m_m_resultVec_1_rl[65];
3'd2:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945 =
m_m_resultVec_2_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[65] :
!m_m_resultVec_2_rl[65];
3'd3:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945 =
m_m_resultVec_3_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[65] :
!m_m_resultVec_3_rl[65];
3'd4:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945 =
m_m_resultVec_4_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[65] :
!m_m_resultVec_4_rl[65];
3'd5:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945 =
m_m_resultVec_5_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[65] :
!m_m_resultVec_5_rl[65];
3'd6:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945 =
m_m_resultVec_6_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[65] :
!m_m_resultVec_6_rl[65];
3'd7:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d945 =
m_m_resultVec_7_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[65] :
!m_m_resultVec_7_rl[65];
endcase
end
always@(sendRsToC_getResult_n or
m_m_resultVec_0_lat_0$whas or
m_m_resultVec_0_lat_0$wget or
m_m_resultVec_0_rl or
m_m_resultVec_1_lat_0$whas or
m_m_resultVec_1_rl or
m_m_resultVec_2_lat_0$whas or
m_m_resultVec_2_rl or
m_m_resultVec_3_lat_0$whas or
m_m_resultVec_3_rl or
m_m_resultVec_4_lat_0$whas or
m_m_resultVec_4_rl or
m_m_resultVec_5_lat_0$whas or
m_m_resultVec_5_rl or
m_m_resultVec_6_lat_0$whas or
m_m_resultVec_6_rl or
m_m_resultVec_7_lat_0$whas or m_m_resultVec_7_rl)
begin
case (sendRsToC_getResult_n)
3'd0:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951 =
m_m_resultVec_0_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[32] :
!m_m_resultVec_0_rl[32];
3'd1:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951 =
m_m_resultVec_1_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[32] :
!m_m_resultVec_1_rl[32];
3'd2:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951 =
m_m_resultVec_2_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[32] :
!m_m_resultVec_2_rl[32];
3'd3:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951 =
m_m_resultVec_3_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[32] :
!m_m_resultVec_3_rl[32];
3'd4:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951 =
m_m_resultVec_4_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[32] :
!m_m_resultVec_4_rl[32];
3'd5:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951 =
m_m_resultVec_5_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[32] :
!m_m_resultVec_5_rl[32];
3'd6:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951 =
m_m_resultVec_6_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[32] :
!m_m_resultVec_6_rl[32];
3'd7:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d951 =
m_m_resultVec_7_lat_0$whas ?
!m_m_resultVec_0_lat_0$wget[32] :
!m_m_resultVec_7_rl[32];
endcase
end
always@(sendRsToC_getResult_n or
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280 or
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348 or
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416 or
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484 or
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552 or
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620 or
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688 or
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756)
begin
case (sendRsToC_getResult_n)
3'd0:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948 =
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280;
3'd1:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948 =
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348;
3'd2:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948 =
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416;
3'd3:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948 =
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484;
3'd4:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948 =
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552;
3'd5:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948 =
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620;
3'd6:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948 =
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688;
3'd7:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d948 =
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756;
endcase
end
always@(sendRsToC_getResult_n or
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 or
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 or
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 or
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 or
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 or
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 or
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 or
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778)
begin
case (sendRsToC_getResult_n)
3'd0:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 =
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302;
3'd1:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 =
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370;
3'd2:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 =
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438;
3'd3:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 =
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506;
3'd4:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 =
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574;
3'd5:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 =
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642;
3'd6:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 =
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710;
3'd7:
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d954 =
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_inited <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
m_m_resultVec_0_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_1_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_2_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_3_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_4_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_5_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_6_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_7_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (m_m_initIdx$EN)
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY m_m_initIdx$D_IN;
if (m_m_inited$EN)
m_m_inited <= `BSV_ASSIGNMENT_DELAY m_m_inited$D_IN;
if (m_m_reqVec_0_rl$EN)
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_0_rl$D_IN;
if (m_m_reqVec_1_rl$EN)
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_1_rl$D_IN;
if (m_m_reqVec_2_rl$EN)
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_2_rl$D_IN;
if (m_m_reqVec_3_rl$EN)
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_3_rl$D_IN;
if (m_m_reqVec_4_rl$EN)
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_4_rl$D_IN;
if (m_m_reqVec_5_rl$EN)
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_5_rl$D_IN;
if (m_m_reqVec_6_rl$EN)
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_6_rl$D_IN;
if (m_m_reqVec_7_rl$EN)
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_7_rl$D_IN;
if (m_m_resultVec_0_rl$EN)
m_m_resultVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_0_rl$D_IN;
if (m_m_resultVec_1_rl$EN)
m_m_resultVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_1_rl$D_IN;
if (m_m_resultVec_2_rl$EN)
m_m_resultVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_2_rl$D_IN;
if (m_m_resultVec_3_rl$EN)
m_m_resultVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_3_rl$D_IN;
if (m_m_resultVec_4_rl$EN)
m_m_resultVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_4_rl$D_IN;
if (m_m_resultVec_5_rl$EN)
m_m_resultVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_5_rl$D_IN;
if (m_m_resultVec_6_rl$EN)
m_m_resultVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_6_rl$D_IN;
if (m_m_resultVec_7_rl$EN)
m_m_resultVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_7_rl$D_IN;
if (m_m_slotVec_0_rl$EN)
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_0_rl$D_IN;
if (m_m_slotVec_1_rl$EN)
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_1_rl$D_IN;
if (m_m_slotVec_2_rl$EN)
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_2_rl$D_IN;
if (m_m_slotVec_3_rl$EN)
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_3_rl$D_IN;
if (m_m_slotVec_4_rl$EN)
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_4_rl$D_IN;
if (m_m_slotVec_5_rl$EN)
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_5_rl$D_IN;
if (m_m_slotVec_6_rl$EN)
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_6_rl$D_IN;
if (m_m_slotVec_7_rl$EN)
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_7_rl$D_IN;
if (m_m_stateVec_0_rl$EN)
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_0_rl$D_IN;
if (m_m_stateVec_1_rl$EN)
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_1_rl$D_IN;
if (m_m_stateVec_2_rl$EN)
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_2_rl$D_IN;
if (m_m_stateVec_3_rl$EN)
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_3_rl$D_IN;
if (m_m_stateVec_4_rl$EN)
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_4_rl$D_IN;
if (m_m_stateVec_5_rl$EN)
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_5_rl$D_IN;
if (m_m_stateVec_6_rl$EN)
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_6_rl$D_IN;
if (m_m_stateVec_7_rl$EN)
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_7_rl$D_IN;
if (m_m_succValidVec_0_rl$EN)
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY
m_m_succValidVec_0_rl$D_IN;
if (m_m_succValidVec_1_rl$EN)
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY
m_m_succValidVec_1_rl$D_IN;
if (m_m_succValidVec_2_rl$EN)
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY
m_m_succValidVec_2_rl$D_IN;
if (m_m_succValidVec_3_rl$EN)
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY
m_m_succValidVec_3_rl$D_IN;
if (m_m_succValidVec_4_rl$EN)
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY
m_m_succValidVec_4_rl$D_IN;
if (m_m_succValidVec_5_rl$EN)
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY
m_m_succValidVec_5_rl$D_IN;
if (m_m_succValidVec_6_rl$EN)
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY
m_m_succValidVec_6_rl$D_IN;
if (m_m_succValidVec_7_rl$EN)
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY
m_m_succValidVec_7_rl$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_m_initIdx = 3'h2;
m_m_inited = 1'h0;
m_m_reqVec_0_rl = 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_1_rl = 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_2_rl = 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_3_rl = 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_4_rl = 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_5_rl = 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_6_rl = 64'hAAAAAAAAAAAAAAAA;
m_m_reqVec_7_rl = 64'hAAAAAAAAAAAAAAAA;
m_m_resultVec_0_rl = 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_1_rl = 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_2_rl = 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_3_rl = 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_4_rl = 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_5_rl = 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_6_rl = 67'h2AAAAAAAAAAAAAAAA;
m_m_resultVec_7_rl = 67'h2AAAAAAAAAAAAAAAA;
m_m_slotVec_0_rl = 56'hAAAAAAAAAAAAAA;
m_m_slotVec_1_rl = 56'hAAAAAAAAAAAAAA;
m_m_slotVec_2_rl = 56'hAAAAAAAAAAAAAA;
m_m_slotVec_3_rl = 56'hAAAAAAAAAAAAAA;
m_m_slotVec_4_rl = 56'hAAAAAAAAAAAAAA;
m_m_slotVec_5_rl = 56'hAAAAAAAAAAAAAA;
m_m_slotVec_6_rl = 56'hAAAAAAAAAAAAAA;
m_m_slotVec_7_rl = 56'hAAAAAAAAAAAAAA;
m_m_stateVec_0_rl = 3'h2;
m_m_stateVec_1_rl = 3'h2;
m_m_stateVec_2_rl = 3'h2;
m_m_stateVec_3_rl = 3'h2;
m_m_stateVec_4_rl = 3'h2;
m_m_stateVec_5_rl = 3'h2;
m_m_stateVec_6_rl = 3'h2;
m_m_stateVec_7_rl = 3'h2;
m_m_succValidVec_0_rl = 1'h0;
m_m_succValidVec_1_rl = 1'h0;
m_m_succValidVec_2_rl = 1'h0;
m_m_succValidVec_3_rl = 1'h0;
m_m_succValidVec_4_rl = 1'h0;
m_m_succValidVec_5_rl = 1'h0;
m_m_succValidVec_6_rl = 1'h0;
m_m_succValidVec_7_rl = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_pipelineResp_setStateSlot &&
pipelineResp_setStateSlot_state == 3'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 3'd7)
begin
v__h67404 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 3'd7)
$display("%t ICRqMshrSafe %m: init empty entry done", v__h67404);
end
// synopsys translate_on
endmodule // mkICRqMshrWrapper
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