Cheri-research/Toooba
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Toooba/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v
rsnikhil 113f888d37 Added support for 'debug_external_interrupt_req' 
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00

8901 lines
357 KiB
Verilog
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//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_updateVMInfo O 1 const
// RDY_toChildren_rqFromC_put O 1
// toChildren_rsToC_notEmpty O 1
// RDY_toChildren_rsToC_notEmpty O 1 const
// RDY_toChildren_rsToC_deq O 1
// toChildren_rsToC_first O 84
// RDY_toChildren_rsToC_first O 1
// RDY_toChildren_iTlbReqFlush_put O 1
// RDY_toChildren_dTlbReqFlush_put O 1
// RDY_toChildren_flushDone_get O 1
// toMem_memReq_notEmpty O 1
// RDY_toMem_memReq_notEmpty O 1 const
// RDY_toMem_memReq_deq O 1
// toMem_memReq_first O 65
// RDY_toMem_memReq_first O 1
// toMem_respLd_notFull O 1
// RDY_toMem_respLd_notFull O 1 const
// RDY_toMem_respLd_enq O 1
// RDY_perf_setStatus O 1 const
// RDY_perf_req O 1
// perf_resp O 68
// RDY_perf_resp O 1
// perf_respValid O 1
// RDY_perf_respValid O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// updateVMInfo_vmI I 49 reg
// updateVMInfo_vmD I 49 reg
// toChildren_rqFromC_put I 30
// toMem_respLd_enq_x I 65
// perf_setStatus_doStats I 1 unused
// perf_req_r I 4
// EN_updateVMInfo I 1
// EN_toChildren_rqFromC_put I 1
// EN_toChildren_rsToC_deq I 1
// EN_toChildren_iTlbReqFlush_put I 1
// EN_toChildren_dTlbReqFlush_put I 1
// EN_toChildren_flushDone_get I 1
// EN_toMem_memReq_deq I 1
// EN_toMem_respLd_enq I 1
// EN_perf_setStatus I 1 unused
// EN_perf_req I 1
// EN_perf_resp I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkL2Tlb(CLK,
RST_N,
updateVMInfo_vmI,
updateVMInfo_vmD,
EN_updateVMInfo,
RDY_updateVMInfo,
toChildren_rqFromC_put,
EN_toChildren_rqFromC_put,
RDY_toChildren_rqFromC_put,
toChildren_rsToC_notEmpty,
RDY_toChildren_rsToC_notEmpty,
EN_toChildren_rsToC_deq,
RDY_toChildren_rsToC_deq,
toChildren_rsToC_first,
RDY_toChildren_rsToC_first,
EN_toChildren_iTlbReqFlush_put,
RDY_toChildren_iTlbReqFlush_put,
EN_toChildren_dTlbReqFlush_put,
RDY_toChildren_dTlbReqFlush_put,
EN_toChildren_flushDone_get,
RDY_toChildren_flushDone_get,
toMem_memReq_notEmpty,
RDY_toMem_memReq_notEmpty,
EN_toMem_memReq_deq,
RDY_toMem_memReq_deq,
toMem_memReq_first,
RDY_toMem_memReq_first,
toMem_respLd_notFull,
RDY_toMem_respLd_notFull,
toMem_respLd_enq_x,
EN_toMem_respLd_enq,
RDY_toMem_respLd_enq,
perf_setStatus_doStats,
EN_perf_setStatus,
RDY_perf_setStatus,
perf_req_r,
EN_perf_req,
RDY_perf_req,
EN_perf_resp,
perf_resp,
RDY_perf_resp,
perf_respValid,
RDY_perf_respValid);
input CLK;
input RST_N;
// action method updateVMInfo
input [48 : 0] updateVMInfo_vmI;
input [48 : 0] updateVMInfo_vmD;
input EN_updateVMInfo;
output RDY_updateVMInfo;
// action method toChildren_rqFromC_put
input [29 : 0] toChildren_rqFromC_put;
input EN_toChildren_rqFromC_put;
output RDY_toChildren_rqFromC_put;
// value method toChildren_rsToC_notEmpty
output toChildren_rsToC_notEmpty;
output RDY_toChildren_rsToC_notEmpty;
// action method toChildren_rsToC_deq
input EN_toChildren_rsToC_deq;
output RDY_toChildren_rsToC_deq;
// value method toChildren_rsToC_first
output [83 : 0] toChildren_rsToC_first;
output RDY_toChildren_rsToC_first;
// action method toChildren_iTlbReqFlush_put
input EN_toChildren_iTlbReqFlush_put;
output RDY_toChildren_iTlbReqFlush_put;
// action method toChildren_dTlbReqFlush_put
input EN_toChildren_dTlbReqFlush_put;
output RDY_toChildren_dTlbReqFlush_put;
// action method toChildren_flushDone_get
input EN_toChildren_flushDone_get;
output RDY_toChildren_flushDone_get;
// value method toMem_memReq_notEmpty
output toMem_memReq_notEmpty;
output RDY_toMem_memReq_notEmpty;
// action method toMem_memReq_deq
input EN_toMem_memReq_deq;
output RDY_toMem_memReq_deq;
// value method toMem_memReq_first
output [64 : 0] toMem_memReq_first;
output RDY_toMem_memReq_first;
// value method toMem_respLd_notFull
output toMem_respLd_notFull;
output RDY_toMem_respLd_notFull;
// action method toMem_respLd_enq
input [64 : 0] toMem_respLd_enq_x;
input EN_toMem_respLd_enq;
output RDY_toMem_respLd_enq;
// action method perf_setStatus
input perf_setStatus_doStats;
input EN_perf_setStatus;
output RDY_perf_setStatus;
// action method perf_req
input [3 : 0] perf_req_r;
input EN_perf_req;
output RDY_perf_req;
// actionvalue method perf_resp
input EN_perf_resp;
output [67 : 0] perf_resp;
output RDY_perf_resp;
// value method perf_respValid
output perf_respValid;
output RDY_perf_respValid;
// signals for module outputs
wire [83 : 0] toChildren_rsToC_first;
wire [67 : 0] perf_resp;
wire [64 : 0] toMem_memReq_first;
wire RDY_perf_req,
RDY_perf_resp,
RDY_perf_respValid,
RDY_perf_setStatus,
RDY_toChildren_dTlbReqFlush_put,
RDY_toChildren_flushDone_get,
RDY_toChildren_iTlbReqFlush_put,
RDY_toChildren_rqFromC_put,
RDY_toChildren_rsToC_deq,
RDY_toChildren_rsToC_first,
RDY_toChildren_rsToC_notEmpty,
RDY_toMem_memReq_deq,
RDY_toMem_memReq_first,
RDY_toMem_memReq_notEmpty,
RDY_toMem_respLd_enq,
RDY_toMem_respLd_notFull,
RDY_updateVMInfo,
perf_respValid,
toChildren_rsToC_notEmpty,
toMem_memReq_notEmpty,
toMem_respLd_notFull;
// inlined wires
wire [83 : 0] rsToCQ_data_0_lat_0$wget;
wire [81 : 0] tlb4KB_m_pendReq_lat_1$wget;
wire [65 : 0] memReqQ_enqReq_lat_0$wget, respLdQ_enqReq_lat_0$wget;
wire [8 : 0] tlb4KB_m_pendIndex$wget;
wire [4 : 0] perfReqQ_enqReq_lat_0$wget;
wire [3 : 0] tlbMG_m_updRepIdx_lat_1$wget;
wire [2 : 0] pendWait_0_lat_0$wget, pendWait_1_lat_0$wget;
wire memReqQ_enqReq_lat_0$whas,
pendValid_0_lat_0$whas,
pendValid_0_lat_1$whas,
pendValid_1_lat_0$whas,
pendValid_1_lat_1$whas,
pendWait_0_lat_0$whas,
pendWait_1_lat_0$whas,
respLdQ_deqReq_lat_0$whas,
rsToCQ_data_0_lat_0$whas,
rsToCQ_empty_dummy_1_0$wget,
rsToCQ_full_lat_0$whas,
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas,
tlbMG_m_updRepIdx_lat_1$whas,
transCacheReqQ_enqP_lat_0$whas;
// register dFlushReq
reg dFlushReq;
wire dFlushReq$D_IN, dFlushReq$EN;
// register flushDoneQ_clearReq_rl
reg flushDoneQ_clearReq_rl;
wire flushDoneQ_clearReq_rl$D_IN, flushDoneQ_clearReq_rl$EN;
// register flushDoneQ_deqReq_rl
reg flushDoneQ_deqReq_rl;
wire flushDoneQ_deqReq_rl$D_IN, flushDoneQ_deqReq_rl$EN;
// register flushDoneQ_empty
reg flushDoneQ_empty;
wire flushDoneQ_empty$D_IN, flushDoneQ_empty$EN;
// register flushDoneQ_enqReq_rl
reg flushDoneQ_enqReq_rl;
wire flushDoneQ_enqReq_rl$D_IN, flushDoneQ_enqReq_rl$EN;
// register flushDoneQ_full
reg flushDoneQ_full;
wire flushDoneQ_full$D_IN, flushDoneQ_full$EN;
// register iFlushReq
reg iFlushReq;
wire iFlushReq$D_IN, iFlushReq$EN;
// register memReqQ_clearReq_rl
reg memReqQ_clearReq_rl;
wire memReqQ_clearReq_rl$D_IN, memReqQ_clearReq_rl$EN;
// register memReqQ_data_0
reg [64 : 0] memReqQ_data_0;
wire [64 : 0] memReqQ_data_0$D_IN;
wire memReqQ_data_0$EN;
// register memReqQ_data_1
reg [64 : 0] memReqQ_data_1;
wire [64 : 0] memReqQ_data_1$D_IN;
wire memReqQ_data_1$EN;
// register memReqQ_deqP
reg memReqQ_deqP;
wire memReqQ_deqP$D_IN, memReqQ_deqP$EN;
// register memReqQ_deqReq_rl
reg memReqQ_deqReq_rl;
wire memReqQ_deqReq_rl$D_IN, memReqQ_deqReq_rl$EN;
// register memReqQ_empty
reg memReqQ_empty;
wire memReqQ_empty$D_IN, memReqQ_empty$EN;
// register memReqQ_enqP
reg memReqQ_enqP;
wire memReqQ_enqP$D_IN, memReqQ_enqP$EN;
// register memReqQ_enqReq_rl
reg [65 : 0] memReqQ_enqReq_rl;
wire [65 : 0] memReqQ_enqReq_rl$D_IN;
wire memReqQ_enqReq_rl$EN;
// register memReqQ_full
reg memReqQ_full;
wire memReqQ_full$D_IN, memReqQ_full$EN;
// register pendReq_0
reg [29 : 0] pendReq_0;
wire [29 : 0] pendReq_0$D_IN;
wire pendReq_0$EN;
// register pendReq_1
reg [29 : 0] pendReq_1;
wire [29 : 0] pendReq_1$D_IN;
wire pendReq_1$EN;
// register pendValid_0_rl
reg pendValid_0_rl;
wire pendValid_0_rl$D_IN, pendValid_0_rl$EN;
// register pendValid_1_rl
reg pendValid_1_rl;
wire pendValid_1_rl$D_IN, pendValid_1_rl$EN;
// register pendWait_0_rl
reg [2 : 0] pendWait_0_rl;
wire [2 : 0] pendWait_0_rl$D_IN;
wire pendWait_0_rl$EN;
// register pendWait_1_rl
reg [2 : 0] pendWait_1_rl;
wire [2 : 0] pendWait_1_rl$D_IN;
wire pendWait_1_rl$EN;
// register pendWalkAddr_0
reg [63 : 0] pendWalkAddr_0;
wire [63 : 0] pendWalkAddr_0$D_IN;
wire pendWalkAddr_0$EN;
// register pendWalkAddr_1
reg [63 : 0] pendWalkAddr_1;
wire [63 : 0] pendWalkAddr_1$D_IN;
wire pendWalkAddr_1$EN;
// register pendWalkLevel_0
reg [1 : 0] pendWalkLevel_0;
wire [1 : 0] pendWalkLevel_0$D_IN;
wire pendWalkLevel_0$EN;
// register pendWalkLevel_1
reg [1 : 0] pendWalkLevel_1;
wire [1 : 0] pendWalkLevel_1$D_IN;
wire pendWalkLevel_1$EN;
// register perfReqQ_clearReq_rl
reg perfReqQ_clearReq_rl;
wire perfReqQ_clearReq_rl$D_IN, perfReqQ_clearReq_rl$EN;
// register perfReqQ_data_0
reg [3 : 0] perfReqQ_data_0;
wire [3 : 0] perfReqQ_data_0$D_IN;
wire perfReqQ_data_0$EN;
// register perfReqQ_deqReq_rl
reg perfReqQ_deqReq_rl;
wire perfReqQ_deqReq_rl$D_IN, perfReqQ_deqReq_rl$EN;
// register perfReqQ_empty
reg perfReqQ_empty;
wire perfReqQ_empty$D_IN, perfReqQ_empty$EN;
// register perfReqQ_enqReq_rl
reg [4 : 0] perfReqQ_enqReq_rl;
wire [4 : 0] perfReqQ_enqReq_rl$D_IN;
wire perfReqQ_enqReq_rl$EN;
// register perfReqQ_full
reg perfReqQ_full;
wire perfReqQ_full$D_IN, perfReqQ_full$EN;
// register respForOtherReq
reg [1 : 0] respForOtherReq;
wire [1 : 0] respForOtherReq$D_IN;
wire respForOtherReq$EN;
// register respLdQ_clearReq_rl
reg respLdQ_clearReq_rl;
wire respLdQ_clearReq_rl$D_IN, respLdQ_clearReq_rl$EN;
// register respLdQ_data_0
reg [64 : 0] respLdQ_data_0;
wire [64 : 0] respLdQ_data_0$D_IN;
wire respLdQ_data_0$EN;
// register respLdQ_data_1
reg [64 : 0] respLdQ_data_1;
wire [64 : 0] respLdQ_data_1$D_IN;
wire respLdQ_data_1$EN;
// register respLdQ_deqP
reg respLdQ_deqP;
wire respLdQ_deqP$D_IN, respLdQ_deqP$EN;
// register respLdQ_deqReq_rl
reg respLdQ_deqReq_rl;
wire respLdQ_deqReq_rl$D_IN, respLdQ_deqReq_rl$EN;
// register respLdQ_empty
reg respLdQ_empty;
wire respLdQ_empty$D_IN, respLdQ_empty$EN;
// register respLdQ_enqP
reg respLdQ_enqP;
wire respLdQ_enqP$D_IN, respLdQ_enqP$EN;
// register respLdQ_enqReq_rl
reg [65 : 0] respLdQ_enqReq_rl;
wire [65 : 0] respLdQ_enqReq_rl$D_IN;
wire respLdQ_enqReq_rl$EN;
// register respLdQ_full
reg respLdQ_full;
wire respLdQ_full$D_IN, respLdQ_full$EN;
// register rqFromCQ_data_0_rl
reg [29 : 0] rqFromCQ_data_0_rl;
wire [29 : 0] rqFromCQ_data_0_rl$D_IN;
wire rqFromCQ_data_0_rl$EN;
// register rqFromCQ_empty_rl
reg rqFromCQ_empty_rl;
wire rqFromCQ_empty_rl$D_IN, rqFromCQ_empty_rl$EN;
// register rqFromCQ_full_rl
reg rqFromCQ_full_rl;
wire rqFromCQ_full_rl$D_IN, rqFromCQ_full_rl$EN;
// register rsToCQ_data_0_rl
reg [83 : 0] rsToCQ_data_0_rl;
wire [83 : 0] rsToCQ_data_0_rl$D_IN;
wire rsToCQ_data_0_rl$EN;
// register rsToCQ_empty_rl
reg rsToCQ_empty_rl;
wire rsToCQ_empty_rl$D_IN, rsToCQ_empty_rl$EN;
// register rsToCQ_full_rl
reg rsToCQ_full_rl;
wire rsToCQ_full_rl$D_IN, rsToCQ_full_rl$EN;
// register tlb4KB_m_flushIdx
reg [7 : 0] tlb4KB_m_flushIdx;
wire [7 : 0] tlb4KB_m_flushIdx$D_IN;
wire tlb4KB_m_flushIdx$EN;
// register tlb4KB_m_pendReq_rl
reg [81 : 0] tlb4KB_m_pendReq_rl;
wire [81 : 0] tlb4KB_m_pendReq_rl$D_IN;
wire tlb4KB_m_pendReq_rl$EN;
// register tlb4KB_m_repRam_rdReqQ_empty_rl
reg tlb4KB_m_repRam_rdReqQ_empty_rl;
wire tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN,
tlb4KB_m_repRam_rdReqQ_empty_rl$EN;
// register tlb4KB_m_repRam_rdReqQ_full_rl
reg tlb4KB_m_repRam_rdReqQ_full_rl;
wire tlb4KB_m_repRam_rdReqQ_full_rl$D_IN, tlb4KB_m_repRam_rdReqQ_full_rl$EN;
// register tlb4KB_m_state
reg tlb4KB_m_state;
wire tlb4KB_m_state$D_IN, tlb4KB_m_state$EN;
// register tlb4KB_m_tlbRam_0_rdReqQ_empty_rl
reg tlb4KB_m_tlbRam_0_rdReqQ_empty_rl;
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN;
// register tlb4KB_m_tlbRam_0_rdReqQ_full_rl
reg tlb4KB_m_tlbRam_0_rdReqQ_full_rl;
wire tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN;
// register tlb4KB_m_tlbRam_1_rdReqQ_empty_rl
reg tlb4KB_m_tlbRam_1_rdReqQ_empty_rl;
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN;
// register tlb4KB_m_tlbRam_1_rdReqQ_full_rl
reg tlb4KB_m_tlbRam_1_rdReqQ_full_rl;
wire tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN;
// register tlb4KB_m_tlbRam_2_rdReqQ_empty_rl
reg tlb4KB_m_tlbRam_2_rdReqQ_empty_rl;
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN;
// register tlb4KB_m_tlbRam_2_rdReqQ_full_rl
reg tlb4KB_m_tlbRam_2_rdReqQ_full_rl;
wire tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN;
// register tlb4KB_m_tlbRam_3_rdReqQ_empty_rl
reg tlb4KB_m_tlbRam_3_rdReqQ_empty_rl;
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN;
// register tlb4KB_m_tlbRam_3_rdReqQ_full_rl
reg tlb4KB_m_tlbRam_3_rdReqQ_full_rl;
wire tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN;
// register tlbMG_m_entryVec_0
reg [79 : 0] tlbMG_m_entryVec_0;
wire [79 : 0] tlbMG_m_entryVec_0$D_IN;
wire tlbMG_m_entryVec_0$EN;
// register tlbMG_m_entryVec_1
reg [79 : 0] tlbMG_m_entryVec_1;
wire [79 : 0] tlbMG_m_entryVec_1$D_IN;
wire tlbMG_m_entryVec_1$EN;
// register tlbMG_m_entryVec_2
reg [79 : 0] tlbMG_m_entryVec_2;
wire [79 : 0] tlbMG_m_entryVec_2$D_IN;
wire tlbMG_m_entryVec_2$EN;
// register tlbMG_m_entryVec_3
reg [79 : 0] tlbMG_m_entryVec_3;
wire [79 : 0] tlbMG_m_entryVec_3$D_IN;
wire tlbMG_m_entryVec_3$EN;
// register tlbMG_m_entryVec_4
reg [79 : 0] tlbMG_m_entryVec_4;
wire [79 : 0] tlbMG_m_entryVec_4$D_IN;
wire tlbMG_m_entryVec_4$EN;
// register tlbMG_m_entryVec_5
reg [79 : 0] tlbMG_m_entryVec_5;
wire [79 : 0] tlbMG_m_entryVec_5$D_IN;
wire tlbMG_m_entryVec_5$EN;
// register tlbMG_m_entryVec_6
reg [79 : 0] tlbMG_m_entryVec_6;
wire [79 : 0] tlbMG_m_entryVec_6$D_IN;
wire tlbMG_m_entryVec_6$EN;
// register tlbMG_m_entryVec_7
reg [79 : 0] tlbMG_m_entryVec_7;
wire [79 : 0] tlbMG_m_entryVec_7$D_IN;
wire tlbMG_m_entryVec_7$EN;
// register tlbMG_m_lruBit_rl
reg [7 : 0] tlbMG_m_lruBit_rl;
wire [7 : 0] tlbMG_m_lruBit_rl$D_IN;
wire tlbMG_m_lruBit_rl$EN;
// register tlbMG_m_randIdx
reg [2 : 0] tlbMG_m_randIdx;
wire [2 : 0] tlbMG_m_randIdx$D_IN;
wire tlbMG_m_randIdx$EN;
// register tlbMG_m_updRepIdx_rl
reg [3 : 0] tlbMG_m_updRepIdx_rl;
wire [3 : 0] tlbMG_m_updRepIdx_rl$D_IN;
wire tlbMG_m_updRepIdx_rl$EN;
// register tlbMG_m_validVec_0
reg tlbMG_m_validVec_0;
wire tlbMG_m_validVec_0$D_IN, tlbMG_m_validVec_0$EN;
// register tlbMG_m_validVec_1
reg tlbMG_m_validVec_1;
wire tlbMG_m_validVec_1$D_IN, tlbMG_m_validVec_1$EN;
// register tlbMG_m_validVec_2
reg tlbMG_m_validVec_2;
wire tlbMG_m_validVec_2$D_IN, tlbMG_m_validVec_2$EN;
// register tlbMG_m_validVec_3
reg tlbMG_m_validVec_3;
wire tlbMG_m_validVec_3$D_IN, tlbMG_m_validVec_3$EN;
// register tlbMG_m_validVec_4
reg tlbMG_m_validVec_4;
wire tlbMG_m_validVec_4$D_IN, tlbMG_m_validVec_4$EN;
// register tlbMG_m_validVec_5
reg tlbMG_m_validVec_5;
wire tlbMG_m_validVec_5$D_IN, tlbMG_m_validVec_5$EN;
// register tlbMG_m_validVec_6
reg tlbMG_m_validVec_6;
wire tlbMG_m_validVec_6$D_IN, tlbMG_m_validVec_6$EN;
// register tlbMG_m_validVec_7
reg tlbMG_m_validVec_7;
wire tlbMG_m_validVec_7$D_IN, tlbMG_m_validVec_7$EN;
// register tlbReqQ_data_0
reg tlbReqQ_data_0;
wire tlbReqQ_data_0$D_IN, tlbReqQ_data_0$EN;
// register tlbReqQ_empty_rl
reg tlbReqQ_empty_rl;
wire tlbReqQ_empty_rl$D_IN, tlbReqQ_empty_rl$EN;
// register tlbReqQ_full_rl
reg tlbReqQ_full_rl;
wire tlbReqQ_full_rl$D_IN, tlbReqQ_full_rl$EN;
// register transCacheReqQ_data_0
reg transCacheReqQ_data_0;
wire transCacheReqQ_data_0$D_IN, transCacheReqQ_data_0$EN;
// register transCacheReqQ_empty_rl
reg transCacheReqQ_empty_rl;
wire transCacheReqQ_empty_rl$D_IN, transCacheReqQ_empty_rl$EN;
// register transCacheReqQ_full_rl
reg transCacheReqQ_full_rl;
wire transCacheReqQ_full_rl$D_IN, transCacheReqQ_full_rl$EN;
// register vm_info_D
reg [48 : 0] vm_info_D;
wire [48 : 0] vm_info_D$D_IN;
wire vm_info_D$EN;
// register vm_info_I
reg [48 : 0] vm_info_I;
wire [48 : 0] vm_info_I$D_IN;
wire vm_info_I$EN;
// register waitFlushDone
reg waitFlushDone;
wire waitFlushDone$D_IN, waitFlushDone$EN;
// ports of submodule flushDoneQ_clearReq_dummy2_0
wire flushDoneQ_clearReq_dummy2_0$D_IN, flushDoneQ_clearReq_dummy2_0$EN;
// ports of submodule flushDoneQ_clearReq_dummy2_1
wire flushDoneQ_clearReq_dummy2_1$D_IN,
flushDoneQ_clearReq_dummy2_1$EN,
flushDoneQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule flushDoneQ_deqReq_dummy2_0
wire flushDoneQ_deqReq_dummy2_0$D_IN, flushDoneQ_deqReq_dummy2_0$EN;
// ports of submodule flushDoneQ_deqReq_dummy2_1
wire flushDoneQ_deqReq_dummy2_1$D_IN, flushDoneQ_deqReq_dummy2_1$EN;
// ports of submodule flushDoneQ_deqReq_dummy2_2
wire flushDoneQ_deqReq_dummy2_2$D_IN,
flushDoneQ_deqReq_dummy2_2$EN,
flushDoneQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule flushDoneQ_enqReq_dummy2_0
wire flushDoneQ_enqReq_dummy2_0$D_IN, flushDoneQ_enqReq_dummy2_0$EN;
// ports of submodule flushDoneQ_enqReq_dummy2_1
wire flushDoneQ_enqReq_dummy2_1$D_IN, flushDoneQ_enqReq_dummy2_1$EN;
// ports of submodule flushDoneQ_enqReq_dummy2_2
wire flushDoneQ_enqReq_dummy2_2$D_IN,
flushDoneQ_enqReq_dummy2_2$EN,
flushDoneQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule memReqQ_clearReq_dummy2_0
wire memReqQ_clearReq_dummy2_0$D_IN, memReqQ_clearReq_dummy2_0$EN;
// ports of submodule memReqQ_clearReq_dummy2_1
wire memReqQ_clearReq_dummy2_1$D_IN,
memReqQ_clearReq_dummy2_1$EN,
memReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule memReqQ_deqReq_dummy2_0
wire memReqQ_deqReq_dummy2_0$D_IN, memReqQ_deqReq_dummy2_0$EN;
// ports of submodule memReqQ_deqReq_dummy2_1
wire memReqQ_deqReq_dummy2_1$D_IN, memReqQ_deqReq_dummy2_1$EN;
// ports of submodule memReqQ_deqReq_dummy2_2
wire memReqQ_deqReq_dummy2_2$D_IN,
memReqQ_deqReq_dummy2_2$EN,
memReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule memReqQ_enqReq_dummy2_0
wire memReqQ_enqReq_dummy2_0$D_IN, memReqQ_enqReq_dummy2_0$EN;
// ports of submodule memReqQ_enqReq_dummy2_1
wire memReqQ_enqReq_dummy2_1$D_IN, memReqQ_enqReq_dummy2_1$EN;
// ports of submodule memReqQ_enqReq_dummy2_2
wire memReqQ_enqReq_dummy2_2$D_IN,
memReqQ_enqReq_dummy2_2$EN,
memReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule pendValid_0_dummy2_0
wire pendValid_0_dummy2_0$D_IN,
pendValid_0_dummy2_0$EN,
pendValid_0_dummy2_0$Q_OUT;
// ports of submodule pendValid_0_dummy2_1
wire pendValid_0_dummy2_1$D_IN,
pendValid_0_dummy2_1$EN,
pendValid_0_dummy2_1$Q_OUT;
// ports of submodule pendValid_1_dummy2_0
wire pendValid_1_dummy2_0$D_IN,
pendValid_1_dummy2_0$EN,
pendValid_1_dummy2_0$Q_OUT;
// ports of submodule pendValid_1_dummy2_1
wire pendValid_1_dummy2_1$D_IN,
pendValid_1_dummy2_1$EN,
pendValid_1_dummy2_1$Q_OUT;
// ports of submodule pendWait_0_dummy2_0
wire pendWait_0_dummy2_0$D_IN,
pendWait_0_dummy2_0$EN,
pendWait_0_dummy2_0$Q_OUT;
// ports of submodule pendWait_0_dummy2_1
wire pendWait_0_dummy2_1$D_IN,
pendWait_0_dummy2_1$EN,
pendWait_0_dummy2_1$Q_OUT;
// ports of submodule pendWait_1_dummy2_0
wire pendWait_1_dummy2_0$D_IN,
pendWait_1_dummy2_0$EN,
pendWait_1_dummy2_0$Q_OUT;
// ports of submodule pendWait_1_dummy2_1
wire pendWait_1_dummy2_1$D_IN,
pendWait_1_dummy2_1$EN,
pendWait_1_dummy2_1$Q_OUT;
// ports of submodule perfReqQ_clearReq_dummy2_0
wire perfReqQ_clearReq_dummy2_0$D_IN, perfReqQ_clearReq_dummy2_0$EN;
// ports of submodule perfReqQ_clearReq_dummy2_1
wire perfReqQ_clearReq_dummy2_1$D_IN,
perfReqQ_clearReq_dummy2_1$EN,
perfReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule perfReqQ_deqReq_dummy2_0
wire perfReqQ_deqReq_dummy2_0$D_IN, perfReqQ_deqReq_dummy2_0$EN;
// ports of submodule perfReqQ_deqReq_dummy2_1
wire perfReqQ_deqReq_dummy2_1$D_IN, perfReqQ_deqReq_dummy2_1$EN;
// ports of submodule perfReqQ_deqReq_dummy2_2
wire perfReqQ_deqReq_dummy2_2$D_IN,
perfReqQ_deqReq_dummy2_2$EN,
perfReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule perfReqQ_enqReq_dummy2_0
wire perfReqQ_enqReq_dummy2_0$D_IN, perfReqQ_enqReq_dummy2_0$EN;
// ports of submodule perfReqQ_enqReq_dummy2_1
wire perfReqQ_enqReq_dummy2_1$D_IN, perfReqQ_enqReq_dummy2_1$EN;
// ports of submodule perfReqQ_enqReq_dummy2_2
wire perfReqQ_enqReq_dummy2_2$D_IN,
perfReqQ_enqReq_dummy2_2$EN,
perfReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule respLdQ_clearReq_dummy2_0
wire respLdQ_clearReq_dummy2_0$D_IN, respLdQ_clearReq_dummy2_0$EN;
// ports of submodule respLdQ_clearReq_dummy2_1
wire respLdQ_clearReq_dummy2_1$D_IN,
respLdQ_clearReq_dummy2_1$EN,
respLdQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule respLdQ_deqReq_dummy2_0
wire respLdQ_deqReq_dummy2_0$D_IN, respLdQ_deqReq_dummy2_0$EN;
// ports of submodule respLdQ_deqReq_dummy2_1
wire respLdQ_deqReq_dummy2_1$D_IN, respLdQ_deqReq_dummy2_1$EN;
// ports of submodule respLdQ_deqReq_dummy2_2
wire respLdQ_deqReq_dummy2_2$D_IN,
respLdQ_deqReq_dummy2_2$EN,
respLdQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule respLdQ_enqReq_dummy2_0
wire respLdQ_enqReq_dummy2_0$D_IN, respLdQ_enqReq_dummy2_0$EN;
// ports of submodule respLdQ_enqReq_dummy2_1
wire respLdQ_enqReq_dummy2_1$D_IN, respLdQ_enqReq_dummy2_1$EN;
// ports of submodule respLdQ_enqReq_dummy2_2
wire respLdQ_enqReq_dummy2_2$D_IN,
respLdQ_enqReq_dummy2_2$EN,
respLdQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule rqFromCQ_data_0_dummy2_0
wire rqFromCQ_data_0_dummy2_0$D_IN, rqFromCQ_data_0_dummy2_0$EN;
// ports of submodule rqFromCQ_data_0_dummy2_1
wire rqFromCQ_data_0_dummy2_1$D_IN,
rqFromCQ_data_0_dummy2_1$EN,
rqFromCQ_data_0_dummy2_1$Q_OUT;
// ports of submodule rqFromCQ_deqP_dummy2_0
wire rqFromCQ_deqP_dummy2_0$D_IN, rqFromCQ_deqP_dummy2_0$EN;
// ports of submodule rqFromCQ_deqP_dummy2_1
wire rqFromCQ_deqP_dummy2_1$D_IN, rqFromCQ_deqP_dummy2_1$EN;
// ports of submodule rqFromCQ_empty_dummy2_0
wire rqFromCQ_empty_dummy2_0$D_IN, rqFromCQ_empty_dummy2_0$EN;
// ports of submodule rqFromCQ_empty_dummy2_1
wire rqFromCQ_empty_dummy2_1$D_IN,
rqFromCQ_empty_dummy2_1$EN,
rqFromCQ_empty_dummy2_1$Q_OUT;
// ports of submodule rqFromCQ_empty_dummy2_2
wire rqFromCQ_empty_dummy2_2$D_IN,
rqFromCQ_empty_dummy2_2$EN,
rqFromCQ_empty_dummy2_2$Q_OUT;
// ports of submodule rqFromCQ_enqP_dummy2_0
wire rqFromCQ_enqP_dummy2_0$D_IN, rqFromCQ_enqP_dummy2_0$EN;
// ports of submodule rqFromCQ_enqP_dummy2_1
wire rqFromCQ_enqP_dummy2_1$D_IN, rqFromCQ_enqP_dummy2_1$EN;
// ports of submodule rqFromCQ_full_dummy2_0
wire rqFromCQ_full_dummy2_0$D_IN,
rqFromCQ_full_dummy2_0$EN,
rqFromCQ_full_dummy2_0$Q_OUT;
// ports of submodule rqFromCQ_full_dummy2_1
wire rqFromCQ_full_dummy2_1$D_IN,
rqFromCQ_full_dummy2_1$EN,
rqFromCQ_full_dummy2_1$Q_OUT;
// ports of submodule rqFromCQ_full_dummy2_2
wire rqFromCQ_full_dummy2_2$D_IN,
rqFromCQ_full_dummy2_2$EN,
rqFromCQ_full_dummy2_2$Q_OUT;
// ports of submodule rsToCQ_data_0_dummy2_0
wire rsToCQ_data_0_dummy2_0$D_IN, rsToCQ_data_0_dummy2_0$EN;
// ports of submodule rsToCQ_data_0_dummy2_1
wire rsToCQ_data_0_dummy2_1$D_IN,
rsToCQ_data_0_dummy2_1$EN,
rsToCQ_data_0_dummy2_1$Q_OUT;
// ports of submodule rsToCQ_deqP_dummy2_0
wire rsToCQ_deqP_dummy2_0$D_IN, rsToCQ_deqP_dummy2_0$EN;
// ports of submodule rsToCQ_deqP_dummy2_1
wire rsToCQ_deqP_dummy2_1$D_IN, rsToCQ_deqP_dummy2_1$EN;
// ports of submodule rsToCQ_empty_dummy2_0
wire rsToCQ_empty_dummy2_0$D_IN, rsToCQ_empty_dummy2_0$EN;
// ports of submodule rsToCQ_empty_dummy2_1
wire rsToCQ_empty_dummy2_1$D_IN,
rsToCQ_empty_dummy2_1$EN,
rsToCQ_empty_dummy2_1$Q_OUT;
// ports of submodule rsToCQ_empty_dummy2_2
wire rsToCQ_empty_dummy2_2$D_IN,
rsToCQ_empty_dummy2_2$EN,
rsToCQ_empty_dummy2_2$Q_OUT;
// ports of submodule rsToCQ_enqP_dummy2_0
wire rsToCQ_enqP_dummy2_0$D_IN, rsToCQ_enqP_dummy2_0$EN;
// ports of submodule rsToCQ_enqP_dummy2_1
wire rsToCQ_enqP_dummy2_1$D_IN, rsToCQ_enqP_dummy2_1$EN;
// ports of submodule rsToCQ_full_dummy2_0
wire rsToCQ_full_dummy2_0$D_IN,
rsToCQ_full_dummy2_0$EN,
rsToCQ_full_dummy2_0$Q_OUT;
// ports of submodule rsToCQ_full_dummy2_1
wire rsToCQ_full_dummy2_1$D_IN,
rsToCQ_full_dummy2_1$EN,
rsToCQ_full_dummy2_1$Q_OUT;
// ports of submodule rsToCQ_full_dummy2_2
wire rsToCQ_full_dummy2_2$D_IN,
rsToCQ_full_dummy2_2$EN,
rsToCQ_full_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_pendReq_dummy2_0
wire tlb4KB_m_pendReq_dummy2_0$D_IN,
tlb4KB_m_pendReq_dummy2_0$EN,
tlb4KB_m_pendReq_dummy2_0$Q_OUT;
// ports of submodule tlb4KB_m_pendReq_dummy2_1
wire tlb4KB_m_pendReq_dummy2_1$D_IN,
tlb4KB_m_pendReq_dummy2_1$EN,
tlb4KB_m_pendReq_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_repRam_bram
reg [7 : 0] tlb4KB_m_repRam_bram$ADDRA, tlb4KB_m_repRam_bram$DIA;
wire [7 : 0] tlb4KB_m_repRam_bram$ADDRB,
tlb4KB_m_repRam_bram$DIB,
tlb4KB_m_repRam_bram$DOB;
wire tlb4KB_m_repRam_bram$ENA,
tlb4KB_m_repRam_bram$ENB,
tlb4KB_m_repRam_bram$WEA,
tlb4KB_m_repRam_bram$WEB;
// ports of submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0
wire tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$D_IN,
tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1
wire tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$D_IN,
tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_0
wire tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$D_IN,
tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$EN,
tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$Q_OUT;
// ports of submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_1
wire tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$D_IN,
tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$EN,
tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_2
wire tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$D_IN,
tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$EN,
tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0
wire tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$D_IN,
tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1
wire tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$D_IN,
tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_0
wire tlb4KB_m_repRam_rdReqQ_full_dummy2_0$D_IN,
tlb4KB_m_repRam_rdReqQ_full_dummy2_0$EN;
// ports of submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_1
wire tlb4KB_m_repRam_rdReqQ_full_dummy2_1$D_IN,
tlb4KB_m_repRam_rdReqQ_full_dummy2_1$EN,
tlb4KB_m_repRam_rdReqQ_full_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_2
wire tlb4KB_m_repRam_rdReqQ_full_dummy2_2$D_IN,
tlb4KB_m_repRam_rdReqQ_full_dummy2_2$EN,
tlb4KB_m_repRam_rdReqQ_full_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_0_bram
wire [80 : 0] tlb4KB_m_tlbRam_0_bram$DIA,
tlb4KB_m_tlbRam_0_bram$DIB,
tlb4KB_m_tlbRam_0_bram$DOB;
wire [7 : 0] tlb4KB_m_tlbRam_0_bram$ADDRA, tlb4KB_m_tlbRam_0_bram$ADDRB;
wire tlb4KB_m_tlbRam_0_bram$ENA,
tlb4KB_m_tlbRam_0_bram$ENB,
tlb4KB_m_tlbRam_0_bram$WEA,
tlb4KB_m_tlbRam_0_bram$WEB;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0
wire tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1
wire tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$EN,
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$EN,
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$EN,
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0
wire tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1
wire tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0
wire tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1
wire tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$EN,
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2
wire tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$D_IN,
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$EN,
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_1_bram
wire [80 : 0] tlb4KB_m_tlbRam_1_bram$DIA,
tlb4KB_m_tlbRam_1_bram$DIB,
tlb4KB_m_tlbRam_1_bram$DOB;
wire [7 : 0] tlb4KB_m_tlbRam_1_bram$ADDRA, tlb4KB_m_tlbRam_1_bram$ADDRB;
wire tlb4KB_m_tlbRam_1_bram$ENA,
tlb4KB_m_tlbRam_1_bram$ENB,
tlb4KB_m_tlbRam_1_bram$WEA,
tlb4KB_m_tlbRam_1_bram$WEB;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0
wire tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1
wire tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$EN,
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$EN,
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$EN,
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0
wire tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1
wire tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0
wire tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1
wire tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$EN,
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2
wire tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$D_IN,
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$EN,
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_2_bram
wire [80 : 0] tlb4KB_m_tlbRam_2_bram$DIA,
tlb4KB_m_tlbRam_2_bram$DIB,
tlb4KB_m_tlbRam_2_bram$DOB;
wire [7 : 0] tlb4KB_m_tlbRam_2_bram$ADDRA, tlb4KB_m_tlbRam_2_bram$ADDRB;
wire tlb4KB_m_tlbRam_2_bram$ENA,
tlb4KB_m_tlbRam_2_bram$ENB,
tlb4KB_m_tlbRam_2_bram$WEA,
tlb4KB_m_tlbRam_2_bram$WEB;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0
wire tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1
wire tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$EN,
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$EN,
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$EN,
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0
wire tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1
wire tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0
wire tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1
wire tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$EN,
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2
wire tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$D_IN,
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$EN,
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_3_bram
wire [80 : 0] tlb4KB_m_tlbRam_3_bram$DIA,
tlb4KB_m_tlbRam_3_bram$DIB,
tlb4KB_m_tlbRam_3_bram$DOB;
wire [7 : 0] tlb4KB_m_tlbRam_3_bram$ADDRA, tlb4KB_m_tlbRam_3_bram$ADDRB;
wire tlb4KB_m_tlbRam_3_bram$ENA,
tlb4KB_m_tlbRam_3_bram$ENB,
tlb4KB_m_tlbRam_3_bram$WEA,
tlb4KB_m_tlbRam_3_bram$WEB;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0
wire tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1
wire tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$EN,
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$EN,
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$EN,
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0
wire tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1
wire tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$EN;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0
wire tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$EN;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1
wire tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$EN,
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$Q_OUT;
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2
wire tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$D_IN,
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$EN,
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$Q_OUT;
// ports of submodule tlbMG_m_lruBit_dummy2_0
wire tlbMG_m_lruBit_dummy2_0$D_IN,
tlbMG_m_lruBit_dummy2_0$EN,
tlbMG_m_lruBit_dummy2_0$Q_OUT;
// ports of submodule tlbMG_m_lruBit_dummy2_1
wire tlbMG_m_lruBit_dummy2_1$D_IN,
tlbMG_m_lruBit_dummy2_1$EN,
tlbMG_m_lruBit_dummy2_1$Q_OUT;
// ports of submodule tlbMG_m_updRepIdx_dummy2_0
wire tlbMG_m_updRepIdx_dummy2_0$D_IN,
tlbMG_m_updRepIdx_dummy2_0$EN,
tlbMG_m_updRepIdx_dummy2_0$Q_OUT;
// ports of submodule tlbMG_m_updRepIdx_dummy2_1
wire tlbMG_m_updRepIdx_dummy2_1$D_IN,
tlbMG_m_updRepIdx_dummy2_1$EN,
tlbMG_m_updRepIdx_dummy2_1$Q_OUT;
// ports of submodule tlbReqQ_deqP_dummy2_0
wire tlbReqQ_deqP_dummy2_0$D_IN, tlbReqQ_deqP_dummy2_0$EN;
// ports of submodule tlbReqQ_deqP_dummy2_1
wire tlbReqQ_deqP_dummy2_1$D_IN, tlbReqQ_deqP_dummy2_1$EN;
// ports of submodule tlbReqQ_empty_dummy2_0
wire tlbReqQ_empty_dummy2_0$D_IN,
tlbReqQ_empty_dummy2_0$EN,
tlbReqQ_empty_dummy2_0$Q_OUT;
// ports of submodule tlbReqQ_empty_dummy2_1
wire tlbReqQ_empty_dummy2_1$D_IN,
tlbReqQ_empty_dummy2_1$EN,
tlbReqQ_empty_dummy2_1$Q_OUT;
// ports of submodule tlbReqQ_empty_dummy2_2
wire tlbReqQ_empty_dummy2_2$D_IN,
tlbReqQ_empty_dummy2_2$EN,
tlbReqQ_empty_dummy2_2$Q_OUT;
// ports of submodule tlbReqQ_enqP_dummy2_0
wire tlbReqQ_enqP_dummy2_0$D_IN, tlbReqQ_enqP_dummy2_0$EN;
// ports of submodule tlbReqQ_enqP_dummy2_1
wire tlbReqQ_enqP_dummy2_1$D_IN, tlbReqQ_enqP_dummy2_1$EN;
// ports of submodule tlbReqQ_full_dummy2_0
wire tlbReqQ_full_dummy2_0$D_IN, tlbReqQ_full_dummy2_0$EN;
// ports of submodule tlbReqQ_full_dummy2_1
wire tlbReqQ_full_dummy2_1$D_IN,
tlbReqQ_full_dummy2_1$EN,
tlbReqQ_full_dummy2_1$Q_OUT;
// ports of submodule tlbReqQ_full_dummy2_2
wire tlbReqQ_full_dummy2_2$D_IN,
tlbReqQ_full_dummy2_2$EN,
tlbReqQ_full_dummy2_2$Q_OUT;
// ports of submodule transCache
wire [45 : 0] transCache$resp;
wire [43 : 0] transCache$addEntry_ppn;
wire [26 : 0] transCache$addEntry_vpn, transCache$req_vpn;
wire [1 : 0] transCache$addEntry_level;
wire transCache$EN_addEntry,
transCache$EN_deqResp,
transCache$EN_flush,
transCache$EN_req,
transCache$RDY_addEntry,
transCache$RDY_deqResp,
transCache$RDY_req,
transCache$RDY_resp,
transCache$flush_done;
// ports of submodule transCacheReqQ_deqP_dummy2_0
wire transCacheReqQ_deqP_dummy2_0$D_IN, transCacheReqQ_deqP_dummy2_0$EN;
// ports of submodule transCacheReqQ_deqP_dummy2_1
wire transCacheReqQ_deqP_dummy2_1$D_IN, transCacheReqQ_deqP_dummy2_1$EN;
// ports of submodule transCacheReqQ_empty_dummy2_0
wire transCacheReqQ_empty_dummy2_0$D_IN,
transCacheReqQ_empty_dummy2_0$EN,
transCacheReqQ_empty_dummy2_0$Q_OUT;
// ports of submodule transCacheReqQ_empty_dummy2_1
wire transCacheReqQ_empty_dummy2_1$D_IN,
transCacheReqQ_empty_dummy2_1$EN,
transCacheReqQ_empty_dummy2_1$Q_OUT;
// ports of submodule transCacheReqQ_empty_dummy2_2
wire transCacheReqQ_empty_dummy2_2$D_IN,
transCacheReqQ_empty_dummy2_2$EN,
transCacheReqQ_empty_dummy2_2$Q_OUT;
// ports of submodule transCacheReqQ_enqP_dummy2_0
wire transCacheReqQ_enqP_dummy2_0$D_IN, transCacheReqQ_enqP_dummy2_0$EN;
// ports of submodule transCacheReqQ_enqP_dummy2_1
wire transCacheReqQ_enqP_dummy2_1$D_IN, transCacheReqQ_enqP_dummy2_1$EN;
// ports of submodule transCacheReqQ_full_dummy2_0
wire transCacheReqQ_full_dummy2_0$D_IN, transCacheReqQ_full_dummy2_0$EN;
// ports of submodule transCacheReqQ_full_dummy2_1
wire transCacheReqQ_full_dummy2_1$D_IN,
transCacheReqQ_full_dummy2_1$EN,
transCacheReqQ_full_dummy2_1$Q_OUT;
// ports of submodule transCacheReqQ_full_dummy2_2
wire transCacheReqQ_full_dummy2_2$D_IN,
transCacheReqQ_full_dummy2_2$EN,
transCacheReqQ_full_dummy2_2$Q_OUT;
// rule scheduling signals
wire CAN_FIRE_RL_doPageWalk,
CAN_FIRE_RL_doStartFlush,
CAN_FIRE_RL_doTlbReq,
CAN_FIRE_RL_doTlbResp,
CAN_FIRE_RL_doTranslationCacheResp,
CAN_FIRE_RL_doWaitFlush,
CAN_FIRE_RL_flushDoneQ_canonicalize,
CAN_FIRE_RL_flushDoneQ_clearReq_canon,
CAN_FIRE_RL_flushDoneQ_deqReq_canon,
CAN_FIRE_RL_flushDoneQ_enqReq_canon,
CAN_FIRE_RL_memReqQ_canonicalize,
CAN_FIRE_RL_memReqQ_clearReq_canon,
CAN_FIRE_RL_memReqQ_deqReq_canon,
CAN_FIRE_RL_memReqQ_enqReq_canon,
CAN_FIRE_RL_pendValid_0_canon,
CAN_FIRE_RL_pendValid_1_canon,
CAN_FIRE_RL_pendWait_0_canon,
CAN_FIRE_RL_pendWait_1_canon,
CAN_FIRE_RL_perfReqQ_canonicalize,
CAN_FIRE_RL_perfReqQ_clearReq_canon,
CAN_FIRE_RL_perfReqQ_deqReq_canon,
CAN_FIRE_RL_perfReqQ_enqReq_canon,
CAN_FIRE_RL_respLdQ_canonicalize,
CAN_FIRE_RL_respLdQ_clearReq_canon,
CAN_FIRE_RL_respLdQ_deqReq_canon,
CAN_FIRE_RL_respLdQ_enqReq_canon,
CAN_FIRE_RL_rqFromCQ_data_0_canon,
CAN_FIRE_RL_rqFromCQ_empty_canon,
CAN_FIRE_RL_rqFromCQ_full_canon,
CAN_FIRE_RL_rsToCQ_data_0_canon,
CAN_FIRE_RL_rsToCQ_empty_canon,
CAN_FIRE_RL_rsToCQ_full_canon,
CAN_FIRE_RL_tlb4KB_m_doAddEntry,
CAN_FIRE_RL_tlb4KB_m_doFlush,
CAN_FIRE_RL_tlb4KB_m_pendReq_canon,
CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon,
CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon,
CAN_FIRE_RL_tlb4KB_m_setPendIndex,
CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon,
CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon,
CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon,
CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon,
CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon,
CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon,
CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon,
CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon,
CAN_FIRE_RL_tlbMG_m_doUpdateRep,
CAN_FIRE_RL_tlbMG_m_incRandIdx,
CAN_FIRE_RL_tlbMG_m_lruBit_canon,
CAN_FIRE_RL_tlbMG_m_updRepIdx_canon,
CAN_FIRE_RL_tlbReqQ_empty_canon,
CAN_FIRE_RL_tlbReqQ_full_canon,
CAN_FIRE_RL_transCacheReqQ_empty_canon,
CAN_FIRE_RL_transCacheReqQ_full_canon,
CAN_FIRE_perf_req,
CAN_FIRE_perf_resp,
CAN_FIRE_perf_setStatus,
CAN_FIRE_toChildren_dTlbReqFlush_put,
CAN_FIRE_toChildren_flushDone_get,
CAN_FIRE_toChildren_iTlbReqFlush_put,
CAN_FIRE_toChildren_rqFromC_put,
CAN_FIRE_toChildren_rsToC_deq,
CAN_FIRE_toMem_memReq_deq,
CAN_FIRE_toMem_respLd_enq,
CAN_FIRE_updateVMInfo,
WILL_FIRE_RL_doPageWalk,
WILL_FIRE_RL_doStartFlush,
WILL_FIRE_RL_doTlbReq,
WILL_FIRE_RL_doTlbResp,
WILL_FIRE_RL_doTranslationCacheResp,
WILL_FIRE_RL_doWaitFlush,
WILL_FIRE_RL_flushDoneQ_canonicalize,
WILL_FIRE_RL_flushDoneQ_clearReq_canon,
WILL_FIRE_RL_flushDoneQ_deqReq_canon,
WILL_FIRE_RL_flushDoneQ_enqReq_canon,
WILL_FIRE_RL_memReqQ_canonicalize,
WILL_FIRE_RL_memReqQ_clearReq_canon,
WILL_FIRE_RL_memReqQ_deqReq_canon,
WILL_FIRE_RL_memReqQ_enqReq_canon,
WILL_FIRE_RL_pendValid_0_canon,
WILL_FIRE_RL_pendValid_1_canon,
WILL_FIRE_RL_pendWait_0_canon,
WILL_FIRE_RL_pendWait_1_canon,
WILL_FIRE_RL_perfReqQ_canonicalize,
WILL_FIRE_RL_perfReqQ_clearReq_canon,
WILL_FIRE_RL_perfReqQ_deqReq_canon,
WILL_FIRE_RL_perfReqQ_enqReq_canon,
WILL_FIRE_RL_respLdQ_canonicalize,
WILL_FIRE_RL_respLdQ_clearReq_canon,
WILL_FIRE_RL_respLdQ_deqReq_canon,
WILL_FIRE_RL_respLdQ_enqReq_canon,
WILL_FIRE_RL_rqFromCQ_data_0_canon,
WILL_FIRE_RL_rqFromCQ_empty_canon,
WILL_FIRE_RL_rqFromCQ_full_canon,
WILL_FIRE_RL_rsToCQ_data_0_canon,
WILL_FIRE_RL_rsToCQ_empty_canon,
WILL_FIRE_RL_rsToCQ_full_canon,
WILL_FIRE_RL_tlb4KB_m_doAddEntry,
WILL_FIRE_RL_tlb4KB_m_doFlush,
WILL_FIRE_RL_tlb4KB_m_pendReq_canon,
WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon,
WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon,
WILL_FIRE_RL_tlb4KB_m_setPendIndex,
WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon,
WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon,
WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon,
WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon,
WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon,
WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon,
WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon,
WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon,
WILL_FIRE_RL_tlbMG_m_doUpdateRep,
WILL_FIRE_RL_tlbMG_m_incRandIdx,
WILL_FIRE_RL_tlbMG_m_lruBit_canon,
WILL_FIRE_RL_tlbMG_m_updRepIdx_canon,
WILL_FIRE_RL_tlbReqQ_empty_canon,
WILL_FIRE_RL_tlbReqQ_full_canon,
WILL_FIRE_RL_transCacheReqQ_empty_canon,
WILL_FIRE_RL_transCacheReqQ_full_canon,
WILL_FIRE_perf_req,
WILL_FIRE_perf_resp,
WILL_FIRE_perf_setStatus,
WILL_FIRE_toChildren_dTlbReqFlush_put,
WILL_FIRE_toChildren_flushDone_get,
WILL_FIRE_toChildren_iTlbReqFlush_put,
WILL_FIRE_toChildren_rqFromC_put,
WILL_FIRE_toChildren_rsToC_deq,
WILL_FIRE_toMem_memReq_deq,
WILL_FIRE_toMem_respLd_enq,
WILL_FIRE_updateVMInfo;
// inputs to muxes for submodule ports
wire [83 : 0] MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1,
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2;
wire [81 : 0] MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1,
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2;
wire [80 : 0] MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1;
wire [65 : 0] MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2;
wire [7 : 0] MUX_tlb4KB_m_flushIdx$write_1__VAL_1,
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1,
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3,
MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1;
wire [3 : 0] MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1,
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2;
wire [2 : 0] MUX_pendWait_0_lat_0$wset_1__VAL_1,
MUX_pendWait_0_lat_0$wset_1__VAL_2,
MUX_pendWait_1_lat_0$wset_1__VAL_1,
MUX_pendWait_1_lat_0$wset_1__VAL_2;
wire MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_1,
MUX_memReqQ_enqReq_lat_0$wset_1__SEL_2,
MUX_pendValid_0_lat_0$wset_1__SEL_1,
MUX_pendValid_0_lat_0$wset_1__SEL_2,
MUX_pendValid_1_lat_0$wset_1__SEL_1,
MUX_pendValid_1_lat_0$wset_1__SEL_2,
MUX_pendWait_0_dummy2_0$write_1__SEL_1,
MUX_pendWait_1_dummy2_0$write_1__SEL_1,
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1,
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_2,
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1,
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1,
MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1,
MUX_tlb4KB_m_state$write_1__SEL_1,
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1,
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1,
MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1,
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1,
MUX_tlbMG_m_updRepIdx_dummy2_1$write_1__SEL_1,
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1,
MUX_tlbMG_m_validVec_0$write_1__SEL_1,
MUX_tlbMG_m_validVec_1$write_1__SEL_1,
MUX_tlbMG_m_validVec_2$write_1__SEL_1,
MUX_tlbMG_m_validVec_3$write_1__SEL_1,
MUX_tlbMG_m_validVec_4$write_1__SEL_1,
MUX_tlbMG_m_validVec_5$write_1__SEL_1,
MUX_tlbMG_m_validVec_6$write_1__SEL_1,
MUX_tlbMG_m_validVec_7$write_1__SEL_1;
// remaining internal signals
reg [63 : 0] CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1,
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876;
reg [43 : 0] CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q16,
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d2016,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1391,
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521,
masked_ppn__h137253;
reg [26 : 0] CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_SEL_ARR__ETC__q3,
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_SEL_ARR__ETC__q4,
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_SEL_ARR__ETC__q7,
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_SEL_ARR__ETC__q9,
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_SEL_ARR__ETC__q11,
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_SEL_ARR__ETC__q13,
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_SEL_ARR__ETC__q14,
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_SEL_ARR__ETC__q15,
CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q17,
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1929,
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138,
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1793,
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1384,
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510,
masked_vpn__h137252;
reg [8 : 0] x__h133729, x__h136754;
reg [1 : 0] CASE_transCacheReqQ_data_0_0_pendReq_0_BITS_28_ETC__q18,
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1378,
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1990,
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671,
walkLevel__h136646,
x__h122416;
reg CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2,
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q5,
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q6,
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q8,
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q10,
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q12,
CASE_tlbReqQ_data_0_0_pendWait_0_dummy2_1_read_ETC__q19,
CASE_v01631_0_pendWait_0_dummy2_1_read__047_AN_ETC__q20,
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133,
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171,
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105,
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788,
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871,
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_838__ETC___d1845,
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_838__ETC___d1970,
SEL_ARR_NOT_respLdQ_data_0_864_BIT_0_865_911_N_ETC___d1914,
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1402,
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1415,
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1424,
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1437,
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1450,
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1463,
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1476,
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666,
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645,
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624,
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603,
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582,
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561,
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540,
SEL_ARR_pendValid_0_dummy2_1_read__29_AND_IF_p_ETC___d1046,
SEL_ARR_pendWait_0_dummy2_0_read__770_AND_pend_ETC___d1834,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1698,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1700,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1702,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1704,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1706,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1708,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1710,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679,
def__h135941;
wire [80 : 0] IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138;
wire [79 : 0] IF_IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_ETC___d1716,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d544,
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136;
wire [63 : 0] baseAddr__h133424,
newPTBase__h136648,
newPTEAddr__h136649,
pteAddr__h133425;
wire [55 : 0] x__h133697, x__h136737;
wire [43 : 0] basePpn__h133693,
rootPPN__h133423,
vm_info_basePPN__h116624,
vm_info_basePPN__h136984;
wire [26 : 0] IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d487,
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130,
vpn__h104314;
wire [7 : 0] IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d286,
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161,
IF_tlbMG_m_lruBit_lat_0_whas__18_THEN_tlbMG_m__ETC___d321,
upd__h144732,
val__h41243,
val__h41244,
x__h41318;
wire [2 : 0] IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1502,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1504,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1506,
IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d342,
IF_tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_ETC___d2207,
IF_tlbMG_m_validVec_4_224_AND_tlbMG_m_validVec_ETC___d2204,
_dfoo52,
_dfoo56,
addIdx__h145990,
addIdx__h147257,
idx__h119391,
v__h143190,
v__h144447,
v__h144923,
value__h119411;
wire [1 : 0] IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1749,
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1750,
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d282,
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d283,
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1093,
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d269,
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d528,
newWalkLevel__h136647,
value__h117443,
vm_info_prv__h116619,
vm_info_prv__h133721,
vm_info_prv__h136979,
w__h117423,
way__h36041;
wire IF_IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy_ETC___d1341,
IF_IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_ETC___d1946,
IF_IF_respForOtherReq_861_BIT_1_862_THEN_NOT_r_ETC___d1919,
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162,
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1239,
IF_NOT_SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_ETC___d1944,
IF_NOT_pendWait_0_dummy2_0_read__770_771_OR_NO_ETC___d1967,
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1326,
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1327,
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328,
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d263,
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d264,
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d265,
IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1329,
IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1345,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1187,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1211,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1236,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1262,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1342,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1309,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1310,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1311,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1312,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1313,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1314,
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315,
IF_NOT_transCacheReqQ_data_0_768_769_OR_NOT_pe_ETC___d1822,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2006,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2056,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2194,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245,
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1922,
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1942,
IF_memReqQ_deqReq_dummy2_2_read__97_AND_IF_mem_ETC___d705,
IF_memReqQ_deqReq_lat_1_whas__68_THEN_memReqQ__ETC___d674,
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648,
IF_pendValid_0_dummy2_1_read__29_AND_IF_pendVa_ETC___d1020,
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573,
IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580,
IF_perfReqQ_enqReq_lat_1_whas__32_THEN_perfReq_ETC___d841,
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1894,
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1895,
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1915,
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d2043,
IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d1977,
IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d2262,
IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d2263,
IF_respLdQ_deqReq_dummy2_2_read__94_AND_IF_res_ETC___d802,
IF_respLdQ_deqReq_lat_1_whas__65_THEN_respLdQ__ETC___d771,
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745,
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d518,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d534,
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125,
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110,
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120,
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147,
IF_tlbMG_m_entryVec_1_152_BITS_1_TO_0_153_EQ_0_ETC___d1170,
IF_tlbMG_m_entryVec_2_177_BITS_1_TO_0_178_EQ_0_ETC___d1194,
IF_tlbMG_m_entryVec_3_201_BITS_1_TO_0_202_EQ_0_ETC___d1219,
IF_tlbMG_m_entryVec_4_226_BITS_1_TO_0_227_EQ_0_ETC___d1245,
IF_tlbMG_m_entryVec_5_252_BITS_1_TO_0_253_EQ_0_ETC___d1272,
IF_tlbMG_m_entryVec_6_278_BITS_1_TO_0_279_EQ_0_ETC___d1287,
IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301,
IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d332,
IF_transCacheReqQ_data_0_768_AND_pendWait_0_du_ETC___d1812,
IF_transCache_RDY_resp__756_AND_transCache_res_ETC___d1781,
NOT_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel__ETC___d2066,
NOT_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel__ETC___d2078,
NOT_flushDoneQ_enqReq_dummy2_2_read__36_51_OR__ETC___d461,
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688,
NOT_memReqQ_enqReq_dummy2_2_read__89_19_OR_IF__ETC___d723,
NOT_perfReqQ_clearReq_dummy2_1_read__76_77_OR__ETC___d881,
NOT_perfReqQ_enqReq_dummy2_2_read__82_97_OR_IF_ETC___d902,
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785,
NOT_respLdQ_enqReq_dummy2_2_read__86_16_OR_IF__ETC___d820,
NOT_rqFromCQ_data_0_dummy2_1_read__003_040_OR__ETC___d1041,
NOT_rqFromCQ_empty_dummy2_1_read__19_20_OR_NOT_ETC___d927,
NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122,
NOT_tlb4KB_m_pendReq_dummy2_1_read__42_08_OR_I_ETC___d943,
NOT_tlb4KB_m_repRam_rdReqQ_empty_dummy2_0_read_ETC___d205,
NOT_tlb4KB_m_repRam_rdReqQ_full_dummy2_1_read__ETC___d989,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1405,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1418,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1427,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1440,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1453,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1466,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1479,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250,
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307,
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1079,
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1321,
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1351,
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165,
NOT_tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1_rea_ETC___d953,
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175,
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d1938,
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d962,
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185,
NOT_tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1_rea_ETC___d971,
NOT_tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0_re_ETC___d195,
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d1024,
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d980,
NOT_tlbMG_m_entryVec_0_125_BITS_79_TO_53_146_E_ETC___d2089,
NOT_tlbMG_m_entryVec_1_152_BITS_79_TO_53_169_E_ETC___d2097,
NOT_tlbMG_m_entryVec_1_152_BITS_79_TO_53_169_E_ETC___d2151,
NOT_tlbMG_m_entryVec_2_177_BITS_79_TO_53_193_E_ETC___d2105,
NOT_tlbMG_m_entryVec_3_201_BITS_79_TO_53_218_E_ETC___d2113,
NOT_tlbMG_m_entryVec_4_226_BITS_79_TO_53_244_E_ETC___d2121,
NOT_tlbMG_m_entryVec_5_252_BITS_79_TO_53_271_E_ETC___d2129,
NOT_tlbMG_m_entryVec_6_278_BITS_79_TO_53_286_E_ETC___d2137,
NOT_tlbMG_m_entryVec_7_292_BITS_79_TO_53_300_E_ETC___d2145,
NOT_tlbMG_m_updRepIdx_dummy2_1_read__50_317_OR_ETC___d1318,
NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1174,
NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1198,
NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1214,
NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1316,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1248,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1543,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1564,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1585,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1606,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1627,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1648,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1669,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1735,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1737,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1754,
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_tlbMG_m__ETC___d2201,
NOT_tlbMG_m_validVec_1_150_151_OR_NOT_tlbMG_m__ETC___d2240,
NOT_tlbMG_m_validVec_3_199_200_OR_NOT_tlbMG_m__ETC___d2238,
NOT_tlbMG_m_validVec_5_250_251_OR_NOT_tlbMG_m__ETC___d2236,
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070,
NOT_transCacheReqQ_data_0_768_769_OR_NOT_pendW_ETC___d1776,
NOT_transCacheReqQ_empty_dummy2_0_read__758_75_ETC___d1767,
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2035,
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2046,
_dfoo13,
_dfoo41,
_dfoo45,
_dfoo57,
_dfoo59,
_dfoo61,
_dfoo63,
_dfoo65,
_dfoo69,
_dfoo73,
_dfoo75,
_dfoo77,
_dfoo79,
_dfoo81,
_dfoo85,
_dfoo9,
_theResult_____2__h82166,
_theResult_____2__h89736,
flushDoneQ_enqReq_dummy2_2_read__36_AND_IF_flu_ETC___d448,
i__h136071,
idx__h135713,
memReqQ_enqReq_dummy2_2_read__89_AND_IF_memReq_ETC___d715,
next_deqP___1__h82485,
next_deqP___1__h90055,
pendValid_0_dummy2_0_read__28_AND_pendValid_0__ETC___d936,
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051,
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056,
pendWait_1_rl_18_BIT_0_30_EQ_SEL_ARR_respLdQ_d_ETC___d1964,
pendWalkAddr_0_786_EQ_0_CONCAT_IF_transCache_r_ETC___d1801,
pendWalkAddr_1_819_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1917,
perfReqQ_enqReq_dummy2_2_read__82_AND_IF_perfR_ETC___d894,
respLdQ_enqReq_dummy2_2_read__86_AND_IF_respLd_ETC___d812,
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1741,
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271,
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287,
tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072,
tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_15_AN_ETC___d1380,
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1075,
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d231,
tlb4KB_m_tlbRam_1_bram_b_read__27_BIT_6_33_EQ__ETC___d234,
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1084,
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d243,
tlb4KB_m_tlbRam_2_bram_b_read__39_BIT_6_45_EQ__ETC___d246,
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088,
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d254,
tlb4KB_m_tlbRam_3_bram_b_read__51_BIT_6_55_EQ__ETC___d256,
tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1495,
tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1497,
tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1499,
tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_1__ETC___d2159,
tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_1__ETC___d2189,
transCache_RDY_deqResp__757_AND_NOT_transCache_ETC___d1827,
transCache_resp__777_BITS_45_TO_44_778_ULT_2___d1779,
v__h101631,
v__h81624,
v__h81907,
v__h89194,
v__h89477;
// action method updateVMInfo
assign RDY_updateVMInfo = 1'd1 ;
assign CAN_FIRE_updateVMInfo = 1'd1 ;
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
// action method toChildren_rqFromC_put
assign RDY_toChildren_rqFromC_put =
!rqFromCQ_full_dummy2_0$Q_OUT || !rqFromCQ_full_dummy2_1$Q_OUT ||
!rqFromCQ_full_dummy2_2$Q_OUT ||
!rqFromCQ_full_rl ;
assign CAN_FIRE_toChildren_rqFromC_put =
!rqFromCQ_full_dummy2_0$Q_OUT || !rqFromCQ_full_dummy2_1$Q_OUT ||
!rqFromCQ_full_dummy2_2$Q_OUT ||
!rqFromCQ_full_rl ;
assign WILL_FIRE_toChildren_rqFromC_put = EN_toChildren_rqFromC_put ;
// value method toChildren_rsToC_notEmpty
assign toChildren_rsToC_notEmpty = RDY_toChildren_rsToC_first ;
assign RDY_toChildren_rsToC_notEmpty = 1'd1 ;
// action method toChildren_rsToC_deq
assign RDY_toChildren_rsToC_deq = RDY_toChildren_rsToC_first ;
assign CAN_FIRE_toChildren_rsToC_deq = RDY_toChildren_rsToC_first ;
assign WILL_FIRE_toChildren_rsToC_deq = EN_toChildren_rsToC_deq ;
// value method toChildren_rsToC_first
assign toChildren_rsToC_first =
{ rsToCQ_data_0_dummy2_1$Q_OUT &&
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d518,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d528,
rsToCQ_data_0_dummy2_1$Q_OUT &&
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d534,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d544 } ;
assign RDY_toChildren_rsToC_first =
!rsToCQ_empty_dummy2_1$Q_OUT || !rsToCQ_empty_dummy2_2$Q_OUT ||
(rsToCQ_empty_dummy_1_0$wget ? !1'd0 : !rsToCQ_empty_rl) ;
// action method toChildren_iTlbReqFlush_put
assign RDY_toChildren_iTlbReqFlush_put = !iFlushReq ;
assign CAN_FIRE_toChildren_iTlbReqFlush_put = !iFlushReq ;
assign WILL_FIRE_toChildren_iTlbReqFlush_put =
EN_toChildren_iTlbReqFlush_put ;
// action method toChildren_dTlbReqFlush_put
assign RDY_toChildren_dTlbReqFlush_put = !dFlushReq ;
assign CAN_FIRE_toChildren_dTlbReqFlush_put = !dFlushReq ;
assign WILL_FIRE_toChildren_dTlbReqFlush_put =
EN_toChildren_dTlbReqFlush_put ;
// action method toChildren_flushDone_get
assign RDY_toChildren_flushDone_get = !flushDoneQ_empty ;
assign CAN_FIRE_toChildren_flushDone_get = !flushDoneQ_empty ;
assign WILL_FIRE_toChildren_flushDone_get = EN_toChildren_flushDone_get ;
// value method toMem_memReq_notEmpty
assign toMem_memReq_notEmpty = !memReqQ_empty ;
assign RDY_toMem_memReq_notEmpty = 1'd1 ;
// action method toMem_memReq_deq
assign RDY_toMem_memReq_deq = !memReqQ_empty ;
assign CAN_FIRE_toMem_memReq_deq = !memReqQ_empty ;
assign WILL_FIRE_toMem_memReq_deq = EN_toMem_memReq_deq ;
// value method toMem_memReq_first
assign toMem_memReq_first =
{ CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1,
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 } ;
assign RDY_toMem_memReq_first = !memReqQ_empty ;
// value method toMem_respLd_notFull
assign toMem_respLd_notFull = !respLdQ_full ;
assign RDY_toMem_respLd_notFull = 1'd1 ;
// action method toMem_respLd_enq
assign RDY_toMem_respLd_enq = !respLdQ_full ;
assign CAN_FIRE_toMem_respLd_enq = !respLdQ_full ;
assign WILL_FIRE_toMem_respLd_enq = EN_toMem_respLd_enq ;
// action method perf_setStatus
assign RDY_perf_setStatus = 1'd1 ;
assign CAN_FIRE_perf_setStatus = 1'd1 ;
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
// action method perf_req
assign RDY_perf_req = !perfReqQ_full ;
assign CAN_FIRE_perf_req = !perfReqQ_full ;
assign WILL_FIRE_perf_req = EN_perf_req ;
// actionvalue method perf_resp
assign perf_resp = { perfReqQ_data_0, 64'd0 } ;
assign RDY_perf_resp = !perfReqQ_empty ;
assign CAN_FIRE_perf_resp = !perfReqQ_empty ;
assign WILL_FIRE_perf_resp = EN_perf_resp ;
// value method perf_respValid
assign perf_respValid = !perfReqQ_empty ;
assign RDY_perf_respValid = 1'd1 ;
// submodule flushDoneQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) flushDoneQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(flushDoneQ_clearReq_dummy2_0$D_IN),
.EN(flushDoneQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule flushDoneQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) flushDoneQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(flushDoneQ_clearReq_dummy2_1$D_IN),
.EN(flushDoneQ_clearReq_dummy2_1$EN),
.Q_OUT(flushDoneQ_clearReq_dummy2_1$Q_OUT));
// submodule flushDoneQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) flushDoneQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(flushDoneQ_deqReq_dummy2_0$D_IN),
.EN(flushDoneQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule flushDoneQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) flushDoneQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(flushDoneQ_deqReq_dummy2_1$D_IN),
.EN(flushDoneQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule flushDoneQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) flushDoneQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(flushDoneQ_deqReq_dummy2_2$D_IN),
.EN(flushDoneQ_deqReq_dummy2_2$EN),
.Q_OUT(flushDoneQ_deqReq_dummy2_2$Q_OUT));
// submodule flushDoneQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) flushDoneQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(flushDoneQ_enqReq_dummy2_0$D_IN),
.EN(flushDoneQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule flushDoneQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) flushDoneQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(flushDoneQ_enqReq_dummy2_1$D_IN),
.EN(flushDoneQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule flushDoneQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) flushDoneQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(flushDoneQ_enqReq_dummy2_2$D_IN),
.EN(flushDoneQ_enqReq_dummy2_2$EN),
.Q_OUT(flushDoneQ_enqReq_dummy2_2$Q_OUT));
// submodule memReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(memReqQ_clearReq_dummy2_0$D_IN),
.EN(memReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule memReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(memReqQ_clearReq_dummy2_1$D_IN),
.EN(memReqQ_clearReq_dummy2_1$EN),
.Q_OUT(memReqQ_clearReq_dummy2_1$Q_OUT));
// submodule memReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(memReqQ_deqReq_dummy2_0$D_IN),
.EN(memReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule memReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(memReqQ_deqReq_dummy2_1$D_IN),
.EN(memReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule memReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(memReqQ_deqReq_dummy2_2$D_IN),
.EN(memReqQ_deqReq_dummy2_2$EN),
.Q_OUT(memReqQ_deqReq_dummy2_2$Q_OUT));
// submodule memReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(memReqQ_enqReq_dummy2_0$D_IN),
.EN(memReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule memReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(memReqQ_enqReq_dummy2_1$D_IN),
.EN(memReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule memReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(memReqQ_enqReq_dummy2_2$D_IN),
.EN(memReqQ_enqReq_dummy2_2$EN),
.Q_OUT(memReqQ_enqReq_dummy2_2$Q_OUT));
// submodule pendValid_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) pendValid_0_dummy2_0(.CLK(CLK),
.D_IN(pendValid_0_dummy2_0$D_IN),
.EN(pendValid_0_dummy2_0$EN),
.Q_OUT(pendValid_0_dummy2_0$Q_OUT));
// submodule pendValid_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) pendValid_0_dummy2_1(.CLK(CLK),
.D_IN(pendValid_0_dummy2_1$D_IN),
.EN(pendValid_0_dummy2_1$EN),
.Q_OUT(pendValid_0_dummy2_1$Q_OUT));
// submodule pendValid_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) pendValid_1_dummy2_0(.CLK(CLK),
.D_IN(pendValid_1_dummy2_0$D_IN),
.EN(pendValid_1_dummy2_0$EN),
.Q_OUT(pendValid_1_dummy2_0$Q_OUT));
// submodule pendValid_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) pendValid_1_dummy2_1(.CLK(CLK),
.D_IN(pendValid_1_dummy2_1$D_IN),
.EN(pendValid_1_dummy2_1$EN),
.Q_OUT(pendValid_1_dummy2_1$Q_OUT));
// submodule pendWait_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) pendWait_0_dummy2_0(.CLK(CLK),
.D_IN(pendWait_0_dummy2_0$D_IN),
.EN(pendWait_0_dummy2_0$EN),
.Q_OUT(pendWait_0_dummy2_0$Q_OUT));
// submodule pendWait_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) pendWait_0_dummy2_1(.CLK(CLK),
.D_IN(pendWait_0_dummy2_1$D_IN),
.EN(pendWait_0_dummy2_1$EN),
.Q_OUT(pendWait_0_dummy2_1$Q_OUT));
// submodule pendWait_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) pendWait_1_dummy2_0(.CLK(CLK),
.D_IN(pendWait_1_dummy2_0$D_IN),
.EN(pendWait_1_dummy2_0$EN),
.Q_OUT(pendWait_1_dummy2_0$Q_OUT));
// submodule pendWait_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) pendWait_1_dummy2_1(.CLK(CLK),
.D_IN(pendWait_1_dummy2_1$D_IN),
.EN(pendWait_1_dummy2_1$EN),
.Q_OUT(pendWait_1_dummy2_1$Q_OUT));
// submodule perfReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) perfReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(perfReqQ_clearReq_dummy2_0$D_IN),
.EN(perfReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule perfReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) perfReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(perfReqQ_clearReq_dummy2_1$D_IN),
.EN(perfReqQ_clearReq_dummy2_1$EN),
.Q_OUT(perfReqQ_clearReq_dummy2_1$Q_OUT));
// submodule perfReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(perfReqQ_deqReq_dummy2_0$D_IN),
.EN(perfReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule perfReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(perfReqQ_deqReq_dummy2_1$D_IN),
.EN(perfReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule perfReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(perfReqQ_deqReq_dummy2_2$D_IN),
.EN(perfReqQ_deqReq_dummy2_2$EN),
.Q_OUT(perfReqQ_deqReq_dummy2_2$Q_OUT));
// submodule perfReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(perfReqQ_enqReq_dummy2_0$D_IN),
.EN(perfReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule perfReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(perfReqQ_enqReq_dummy2_1$D_IN),
.EN(perfReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule perfReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(perfReqQ_enqReq_dummy2_2$D_IN),
.EN(perfReqQ_enqReq_dummy2_2$EN),
.Q_OUT(perfReqQ_enqReq_dummy2_2$Q_OUT));
// submodule respLdQ_clearReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(respLdQ_clearReq_dummy2_0$D_IN),
.EN(respLdQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule respLdQ_clearReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(respLdQ_clearReq_dummy2_1$D_IN),
.EN(respLdQ_clearReq_dummy2_1$EN),
.Q_OUT(respLdQ_clearReq_dummy2_1$Q_OUT));
// submodule respLdQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(respLdQ_deqReq_dummy2_0$D_IN),
.EN(respLdQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule respLdQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(respLdQ_deqReq_dummy2_1$D_IN),
.EN(respLdQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule respLdQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(respLdQ_deqReq_dummy2_2$D_IN),
.EN(respLdQ_deqReq_dummy2_2$EN),
.Q_OUT(respLdQ_deqReq_dummy2_2$Q_OUT));
// submodule respLdQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(respLdQ_enqReq_dummy2_0$D_IN),
.EN(respLdQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule respLdQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(respLdQ_enqReq_dummy2_1$D_IN),
.EN(respLdQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule respLdQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(respLdQ_enqReq_dummy2_2$D_IN),
.EN(respLdQ_enqReq_dummy2_2$EN),
.Q_OUT(respLdQ_enqReq_dummy2_2$Q_OUT));
// submodule rqFromCQ_data_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(rqFromCQ_data_0_dummy2_0$D_IN),
.EN(rqFromCQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule rqFromCQ_data_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(rqFromCQ_data_0_dummy2_1$D_IN),
.EN(rqFromCQ_data_0_dummy2_1$EN),
.Q_OUT(rqFromCQ_data_0_dummy2_1$Q_OUT));
// submodule rqFromCQ_deqP_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(rqFromCQ_deqP_dummy2_0$D_IN),
.EN(rqFromCQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule rqFromCQ_deqP_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(rqFromCQ_deqP_dummy2_1$D_IN),
.EN(rqFromCQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule rqFromCQ_empty_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_empty_dummy2_0(.CLK(CLK),
.D_IN(rqFromCQ_empty_dummy2_0$D_IN),
.EN(rqFromCQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule rqFromCQ_empty_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_empty_dummy2_1(.CLK(CLK),
.D_IN(rqFromCQ_empty_dummy2_1$D_IN),
.EN(rqFromCQ_empty_dummy2_1$EN),
.Q_OUT(rqFromCQ_empty_dummy2_1$Q_OUT));
// submodule rqFromCQ_empty_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_empty_dummy2_2(.CLK(CLK),
.D_IN(rqFromCQ_empty_dummy2_2$D_IN),
.EN(rqFromCQ_empty_dummy2_2$EN),
.Q_OUT(rqFromCQ_empty_dummy2_2$Q_OUT));
// submodule rqFromCQ_enqP_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(rqFromCQ_enqP_dummy2_0$D_IN),
.EN(rqFromCQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule rqFromCQ_enqP_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(rqFromCQ_enqP_dummy2_1$D_IN),
.EN(rqFromCQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule rqFromCQ_full_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_full_dummy2_0(.CLK(CLK),
.D_IN(rqFromCQ_full_dummy2_0$D_IN),
.EN(rqFromCQ_full_dummy2_0$EN),
.Q_OUT(rqFromCQ_full_dummy2_0$Q_OUT));
// submodule rqFromCQ_full_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_full_dummy2_1(.CLK(CLK),
.D_IN(rqFromCQ_full_dummy2_1$D_IN),
.EN(rqFromCQ_full_dummy2_1$EN),
.Q_OUT(rqFromCQ_full_dummy2_1$Q_OUT));
// submodule rqFromCQ_full_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_full_dummy2_2(.CLK(CLK),
.D_IN(rqFromCQ_full_dummy2_2$D_IN),
.EN(rqFromCQ_full_dummy2_2$EN),
.Q_OUT(rqFromCQ_full_dummy2_2$Q_OUT));
// submodule rsToCQ_data_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(rsToCQ_data_0_dummy2_0$D_IN),
.EN(rsToCQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule rsToCQ_data_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(rsToCQ_data_0_dummy2_1$D_IN),
.EN(rsToCQ_data_0_dummy2_1$EN),
.Q_OUT(rsToCQ_data_0_dummy2_1$Q_OUT));
// submodule rsToCQ_deqP_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(rsToCQ_deqP_dummy2_0$D_IN),
.EN(rsToCQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule rsToCQ_deqP_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(rsToCQ_deqP_dummy2_1$D_IN),
.EN(rsToCQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule rsToCQ_empty_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_empty_dummy2_0(.CLK(CLK),
.D_IN(rsToCQ_empty_dummy2_0$D_IN),
.EN(rsToCQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule rsToCQ_empty_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_empty_dummy2_1(.CLK(CLK),
.D_IN(rsToCQ_empty_dummy2_1$D_IN),
.EN(rsToCQ_empty_dummy2_1$EN),
.Q_OUT(rsToCQ_empty_dummy2_1$Q_OUT));
// submodule rsToCQ_empty_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_empty_dummy2_2(.CLK(CLK),
.D_IN(rsToCQ_empty_dummy2_2$D_IN),
.EN(rsToCQ_empty_dummy2_2$EN),
.Q_OUT(rsToCQ_empty_dummy2_2$Q_OUT));
// submodule rsToCQ_enqP_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(rsToCQ_enqP_dummy2_0$D_IN),
.EN(rsToCQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule rsToCQ_enqP_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(rsToCQ_enqP_dummy2_1$D_IN),
.EN(rsToCQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule rsToCQ_full_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_full_dummy2_0(.CLK(CLK),
.D_IN(rsToCQ_full_dummy2_0$D_IN),
.EN(rsToCQ_full_dummy2_0$EN),
.Q_OUT(rsToCQ_full_dummy2_0$Q_OUT));
// submodule rsToCQ_full_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_full_dummy2_1(.CLK(CLK),
.D_IN(rsToCQ_full_dummy2_1$D_IN),
.EN(rsToCQ_full_dummy2_1$EN),
.Q_OUT(rsToCQ_full_dummy2_1$Q_OUT));
// submodule rsToCQ_full_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_full_dummy2_2(.CLK(CLK),
.D_IN(rsToCQ_full_dummy2_2$D_IN),
.EN(rsToCQ_full_dummy2_2$EN),
.Q_OUT(rsToCQ_full_dummy2_2$Q_OUT));
// submodule tlb4KB_m_pendReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) tlb4KB_m_pendReq_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_pendReq_dummy2_0$D_IN),
.EN(tlb4KB_m_pendReq_dummy2_0$EN),
.Q_OUT(tlb4KB_m_pendReq_dummy2_0$Q_OUT));
// submodule tlb4KB_m_pendReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) tlb4KB_m_pendReq_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_pendReq_dummy2_1$D_IN),
.EN(tlb4KB_m_pendReq_dummy2_1$EN),
.Q_OUT(tlb4KB_m_pendReq_dummy2_1$Q_OUT));
// submodule tlb4KB_m_repRam_bram
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd8),
.DATA_WIDTH(32'd8),
.MEMSIZE(9'd256)) tlb4KB_m_repRam_bram(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tlb4KB_m_repRam_bram$ADDRA),
.ADDRB(tlb4KB_m_repRam_bram$ADDRB),
.DIA(tlb4KB_m_repRam_bram$DIA),
.DIB(tlb4KB_m_repRam_bram$DIB),
.WEA(tlb4KB_m_repRam_bram$WEA),
.WEB(tlb4KB_m_repRam_bram$WEB),
.ENA(tlb4KB_m_repRam_bram$ENA),
.ENB(tlb4KB_m_repRam_bram$ENB),
.DOA(),
.DOB(tlb4KB_m_repRam_bram$DOB));
// submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_empty_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$EN),
.Q_OUT(tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$Q_OUT));
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_empty_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$EN),
.Q_OUT(tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$Q_OUT));
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_empty_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$EN),
.Q_OUT(tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$Q_OUT));
// submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_full_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_full_dummy2_0$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_full_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_full_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_full_dummy2_1$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_full_dummy2_1$EN),
.Q_OUT(tlb4KB_m_repRam_rdReqQ_full_dummy2_1$Q_OUT));
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_full_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_repRam_rdReqQ_full_dummy2_2$D_IN),
.EN(tlb4KB_m_repRam_rdReqQ_full_dummy2_2$EN),
.Q_OUT(tlb4KB_m_repRam_rdReqQ_full_dummy2_2$Q_OUT));
// submodule tlb4KB_m_tlbRam_0_bram
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd8),
.DATA_WIDTH(32'd81),
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_0_bram(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tlb4KB_m_tlbRam_0_bram$ADDRA),
.ADDRB(tlb4KB_m_tlbRam_0_bram$ADDRB),
.DIA(tlb4KB_m_tlbRam_0_bram$DIA),
.DIB(tlb4KB_m_tlbRam_0_bram$DIB),
.WEA(tlb4KB_m_tlbRam_0_bram$WEA),
.WEB(tlb4KB_m_tlbRam_0_bram$WEB),
.ENA(tlb4KB_m_tlbRam_0_bram$ENA),
.ENB(tlb4KB_m_tlbRam_0_bram$ENB),
.DOA(),
.DOB(tlb4KB_m_tlbRam_0_bram$DOB));
// submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$EN),
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$Q_OUT));
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$EN),
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$Q_OUT));
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$EN),
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$Q_OUT));
// submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$EN),
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$Q_OUT));
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$D_IN),
.EN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$EN),
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$Q_OUT));
// submodule tlb4KB_m_tlbRam_1_bram
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd8),
.DATA_WIDTH(32'd81),
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_1_bram(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tlb4KB_m_tlbRam_1_bram$ADDRA),
.ADDRB(tlb4KB_m_tlbRam_1_bram$ADDRB),
.DIA(tlb4KB_m_tlbRam_1_bram$DIA),
.DIB(tlb4KB_m_tlbRam_1_bram$DIB),
.WEA(tlb4KB_m_tlbRam_1_bram$WEA),
.WEB(tlb4KB_m_tlbRam_1_bram$WEB),
.ENA(tlb4KB_m_tlbRam_1_bram$ENA),
.ENB(tlb4KB_m_tlbRam_1_bram$ENB),
.DOA(),
.DOB(tlb4KB_m_tlbRam_1_bram$DOB));
// submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$EN),
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$Q_OUT));
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$EN),
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$Q_OUT));
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$EN),
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$Q_OUT));
// submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$EN),
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$Q_OUT));
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$D_IN),
.EN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$EN),
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$Q_OUT));
// submodule tlb4KB_m_tlbRam_2_bram
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd8),
.DATA_WIDTH(32'd81),
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_2_bram(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tlb4KB_m_tlbRam_2_bram$ADDRA),
.ADDRB(tlb4KB_m_tlbRam_2_bram$ADDRB),
.DIA(tlb4KB_m_tlbRam_2_bram$DIA),
.DIB(tlb4KB_m_tlbRam_2_bram$DIB),
.WEA(tlb4KB_m_tlbRam_2_bram$WEA),
.WEB(tlb4KB_m_tlbRam_2_bram$WEB),
.ENA(tlb4KB_m_tlbRam_2_bram$ENA),
.ENB(tlb4KB_m_tlbRam_2_bram$ENB),
.DOA(),
.DOB(tlb4KB_m_tlbRam_2_bram$DOB));
// submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$EN),
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$Q_OUT));
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$EN),
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$Q_OUT));
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$EN),
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$Q_OUT));
// submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$EN),
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$Q_OUT));
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$D_IN),
.EN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$EN),
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$Q_OUT));
// submodule tlb4KB_m_tlbRam_3_bram
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd8),
.DATA_WIDTH(32'd81),
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_3_bram(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(tlb4KB_m_tlbRam_3_bram$ADDRA),
.ADDRB(tlb4KB_m_tlbRam_3_bram$ADDRB),
.DIA(tlb4KB_m_tlbRam_3_bram$DIA),
.DIB(tlb4KB_m_tlbRam_3_bram$DIB),
.WEA(tlb4KB_m_tlbRam_3_bram$WEA),
.WEB(tlb4KB_m_tlbRam_3_bram$WEB),
.ENA(tlb4KB_m_tlbRam_3_bram$ENA),
.ENB(tlb4KB_m_tlbRam_3_bram$ENB),
.DOA(),
.DOB(tlb4KB_m_tlbRam_3_bram$DOB));
// submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$EN),
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$Q_OUT));
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$EN),
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$Q_OUT));
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$EN),
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$Q_OUT));
// submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$EN),
.Q_OUT());
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$EN),
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$Q_OUT));
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2(.CLK(CLK),
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$D_IN),
.EN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$EN),
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$Q_OUT));
// submodule tlbMG_m_lruBit_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) tlbMG_m_lruBit_dummy2_0(.CLK(CLK),
.D_IN(tlbMG_m_lruBit_dummy2_0$D_IN),
.EN(tlbMG_m_lruBit_dummy2_0$EN),
.Q_OUT(tlbMG_m_lruBit_dummy2_0$Q_OUT));
// submodule tlbMG_m_lruBit_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) tlbMG_m_lruBit_dummy2_1(.CLK(CLK),
.D_IN(tlbMG_m_lruBit_dummy2_1$D_IN),
.EN(tlbMG_m_lruBit_dummy2_1$EN),
.Q_OUT(tlbMG_m_lruBit_dummy2_1$Q_OUT));
// submodule tlbMG_m_updRepIdx_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) tlbMG_m_updRepIdx_dummy2_0(.CLK(CLK),
.D_IN(tlbMG_m_updRepIdx_dummy2_0$D_IN),
.EN(tlbMG_m_updRepIdx_dummy2_0$EN),
.Q_OUT(tlbMG_m_updRepIdx_dummy2_0$Q_OUT));
// submodule tlbMG_m_updRepIdx_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) tlbMG_m_updRepIdx_dummy2_1(.CLK(CLK),
.D_IN(tlbMG_m_updRepIdx_dummy2_1$D_IN),
.EN(tlbMG_m_updRepIdx_dummy2_1$EN),
.Q_OUT(tlbMG_m_updRepIdx_dummy2_1$Q_OUT));
// submodule tlbReqQ_deqP_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(tlbReqQ_deqP_dummy2_0$D_IN),
.EN(tlbReqQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule tlbReqQ_deqP_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(tlbReqQ_deqP_dummy2_1$D_IN),
.EN(tlbReqQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule tlbReqQ_empty_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_empty_dummy2_0(.CLK(CLK),
.D_IN(tlbReqQ_empty_dummy2_0$D_IN),
.EN(tlbReqQ_empty_dummy2_0$EN),
.Q_OUT(tlbReqQ_empty_dummy2_0$Q_OUT));
// submodule tlbReqQ_empty_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_empty_dummy2_1(.CLK(CLK),
.D_IN(tlbReqQ_empty_dummy2_1$D_IN),
.EN(tlbReqQ_empty_dummy2_1$EN),
.Q_OUT(tlbReqQ_empty_dummy2_1$Q_OUT));
// submodule tlbReqQ_empty_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_empty_dummy2_2(.CLK(CLK),
.D_IN(tlbReqQ_empty_dummy2_2$D_IN),
.EN(tlbReqQ_empty_dummy2_2$EN),
.Q_OUT(tlbReqQ_empty_dummy2_2$Q_OUT));
// submodule tlbReqQ_enqP_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(tlbReqQ_enqP_dummy2_0$D_IN),
.EN(tlbReqQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule tlbReqQ_enqP_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(tlbReqQ_enqP_dummy2_1$D_IN),
.EN(tlbReqQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule tlbReqQ_full_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_full_dummy2_0(.CLK(CLK),
.D_IN(tlbReqQ_full_dummy2_0$D_IN),
.EN(tlbReqQ_full_dummy2_0$EN),
.Q_OUT());
// submodule tlbReqQ_full_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_full_dummy2_1(.CLK(CLK),
.D_IN(tlbReqQ_full_dummy2_1$D_IN),
.EN(tlbReqQ_full_dummy2_1$EN),
.Q_OUT(tlbReqQ_full_dummy2_1$Q_OUT));
// submodule tlbReqQ_full_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_full_dummy2_2(.CLK(CLK),
.D_IN(tlbReqQ_full_dummy2_2$D_IN),
.EN(tlbReqQ_full_dummy2_2$EN),
.Q_OUT(tlbReqQ_full_dummy2_2$Q_OUT));
// submodule transCache
mkSplitTransCache transCache(.CLK(CLK),
.RST_N(RST_N),
.addEntry_level(transCache$addEntry_level),
.addEntry_ppn(transCache$addEntry_ppn),
.addEntry_vpn(transCache$addEntry_vpn),
.req_vpn(transCache$req_vpn),
.EN_req(transCache$EN_req),
.EN_deqResp(transCache$EN_deqResp),
.EN_addEntry(transCache$EN_addEntry),
.EN_flush(transCache$EN_flush),
.RDY_req(transCache$RDY_req),
.resp(transCache$resp),
.RDY_resp(transCache$RDY_resp),
.RDY_deqResp(transCache$RDY_deqResp),
.RDY_addEntry(transCache$RDY_addEntry),
.RDY_flush(),
.flush_done(transCache$flush_done),
.RDY_flush_done());
// submodule transCacheReqQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(transCacheReqQ_deqP_dummy2_0$D_IN),
.EN(transCacheReqQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule transCacheReqQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(transCacheReqQ_deqP_dummy2_1$D_IN),
.EN(transCacheReqQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule transCacheReqQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_empty_dummy2_0(.CLK(CLK),
.D_IN(transCacheReqQ_empty_dummy2_0$D_IN),
.EN(transCacheReqQ_empty_dummy2_0$EN),
.Q_OUT(transCacheReqQ_empty_dummy2_0$Q_OUT));
// submodule transCacheReqQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_empty_dummy2_1(.CLK(CLK),
.D_IN(transCacheReqQ_empty_dummy2_1$D_IN),
.EN(transCacheReqQ_empty_dummy2_1$EN),
.Q_OUT(transCacheReqQ_empty_dummy2_1$Q_OUT));
// submodule transCacheReqQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_empty_dummy2_2(.CLK(CLK),
.D_IN(transCacheReqQ_empty_dummy2_2$D_IN),
.EN(transCacheReqQ_empty_dummy2_2$EN),
.Q_OUT(transCacheReqQ_empty_dummy2_2$Q_OUT));
// submodule transCacheReqQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(transCacheReqQ_enqP_dummy2_0$D_IN),
.EN(transCacheReqQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule transCacheReqQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(transCacheReqQ_enqP_dummy2_1$D_IN),
.EN(transCacheReqQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule transCacheReqQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_full_dummy2_0(.CLK(CLK),
.D_IN(transCacheReqQ_full_dummy2_0$D_IN),
.EN(transCacheReqQ_full_dummy2_0$EN),
.Q_OUT());
// submodule transCacheReqQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_full_dummy2_1(.CLK(CLK),
.D_IN(transCacheReqQ_full_dummy2_1$D_IN),
.EN(transCacheReqQ_full_dummy2_1$EN),
.Q_OUT(transCacheReqQ_full_dummy2_1$Q_OUT));
// submodule transCacheReqQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) transCacheReqQ_full_dummy2_2(.CLK(CLK),
.D_IN(transCacheReqQ_full_dummy2_2$D_IN),
.EN(transCacheReqQ_full_dummy2_2$EN),
.Q_OUT(transCacheReqQ_full_dummy2_2$Q_OUT));
// rule RL_doStartFlush
assign CAN_FIRE_RL_doStartFlush =
tlb4KB_m_state &&
(!tlb4KB_m_pendReq_dummy2_0$Q_OUT ||
!tlb4KB_m_pendReq_dummy2_1$Q_OUT ||
!tlb4KB_m_pendReq_rl[81]) &&
iFlushReq &&
dFlushReq &&
!waitFlushDone ;
assign WILL_FIRE_RL_doStartFlush = CAN_FIRE_RL_doStartFlush ;
// rule RL_doTranslationCacheResp
assign CAN_FIRE_RL_doTranslationCacheResp =
transCache$RDY_resp &&
transCache_RDY_deqResp__757_AND_NOT_transCache_ETC___d1827 ;
assign WILL_FIRE_RL_doTranslationCacheResp =
CAN_FIRE_RL_doTranslationCacheResp ;
// rule RL_tlb4KB_m_setPendIndex
assign CAN_FIRE_RL_tlb4KB_m_setPendIndex = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_setPendIndex = 1'd1 ;
// rule RL_tlb4KB_m_doAddEntry
assign CAN_FIRE_RL_tlb4KB_m_doAddEntry =
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175 &&
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 &&
NOT_tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0_re_ETC___d195 &&
NOT_tlb4KB_m_repRam_rdReqQ_empty_dummy2_0_read_ETC___d205 &&
tlb4KB_m_state &&
tlb4KB_m_pendReq_dummy2_0$Q_OUT &&
tlb4KB_m_pendReq_dummy2_1$Q_OUT &&
tlb4KB_m_pendReq_rl[81] &&
tlb4KB_m_pendReq_rl[80] ;
assign WILL_FIRE_RL_tlb4KB_m_doAddEntry = CAN_FIRE_RL_tlb4KB_m_doAddEntry ;
// rule RL_tlbMG_m_doUpdateRep
assign CAN_FIRE_RL_tlbMG_m_doUpdateRep =
!CAN_FIRE_RL_doStartFlush && tlbMG_m_updRepIdx_dummy2_0$Q_OUT &&
tlbMG_m_updRepIdx_dummy2_1$Q_OUT &&
tlbMG_m_updRepIdx_rl[3] ;
assign WILL_FIRE_RL_tlbMG_m_doUpdateRep =
CAN_FIRE_RL_tlbMG_m_doUpdateRep && !WILL_FIRE_RL_doStartFlush ;
// rule RL_doTlbResp
assign CAN_FIRE_RL_doTlbResp =
!CAN_FIRE_RL_doStartFlush && tlb4KB_m_state &&
tlb4KB_m_pendReq_dummy2_0$Q_OUT &&
tlb4KB_m_pendReq_dummy2_1$Q_OUT &&
tlb4KB_m_pendReq_rl[81] &&
!tlb4KB_m_pendReq_rl[80] &&
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1351 ;
assign WILL_FIRE_RL_doTlbResp = CAN_FIRE_RL_doTlbResp ;
// rule RL_doPageWalk
assign CAN_FIRE_RL_doPageWalk =
!respLdQ_empty &&
IF_IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_ETC___d1946 &&
tlbReqQ_empty_dummy2_0$Q_OUT &&
tlbReqQ_empty_dummy2_1$Q_OUT &&
tlbReqQ_empty_dummy2_2$Q_OUT &&
tlbReqQ_empty_rl &&
transCacheReqQ_empty_dummy2_0$Q_OUT &&
transCacheReqQ_empty_dummy2_1$Q_OUT &&
transCacheReqQ_empty_dummy2_2$Q_OUT &&
transCacheReqQ_empty_rl ;
assign WILL_FIRE_RL_doPageWalk =
CAN_FIRE_RL_doPageWalk && !WILL_FIRE_RL_doStartFlush ;
// rule RL_doWaitFlush
assign CAN_FIRE_RL_doWaitFlush =
!flushDoneQ_full && iFlushReq && dFlushReq && waitFlushDone &&
tlb4KB_m_state &&
transCache$flush_done ;
assign WILL_FIRE_RL_doWaitFlush = CAN_FIRE_RL_doWaitFlush ;
// rule RL_doTlbReq
assign CAN_FIRE_RL_doTlbReq =
tlb4KB_m_state &&
NOT_tlb4KB_m_pendReq_dummy2_1_read__42_08_OR_I_ETC___d943 &&
NOT_rqFromCQ_empty_dummy2_1_read__19_20_OR_NOT_ETC___d927 &&
NOT_tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1_rea_ETC___d953 &&
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d962 &&
NOT_tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1_rea_ETC___d971 &&
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d1024 &&
(!iFlushReq || !dFlushReq) &&
respLdQ_empty ;
assign WILL_FIRE_RL_doTlbReq = CAN_FIRE_RL_doTlbReq ;
// rule RL_tlb4KB_m_doFlush
assign CAN_FIRE_RL_tlb4KB_m_doFlush = !tlb4KB_m_state ;
assign WILL_FIRE_RL_tlb4KB_m_doFlush = CAN_FIRE_RL_tlb4KB_m_doFlush ;
// rule RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon = 1'd1 ;
// rule RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon = 1'd1 ;
// rule RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon = 1'd1 ;
// rule RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon = 1'd1 ;
// rule RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon = 1'd1 ;
// rule RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon = 1'd1 ;
// rule RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon = 1'd1 ;
// rule RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon = 1'd1 ;
// rule RL_tlb4KB_m_repRam_rdReqQ_empty_canon
assign CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon = 1'd1 ;
// rule RL_tlb4KB_m_repRam_rdReqQ_full_canon
assign CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon = 1'd1 ;
// rule RL_tlb4KB_m_pendReq_canon
assign CAN_FIRE_RL_tlb4KB_m_pendReq_canon = 1'd1 ;
assign WILL_FIRE_RL_tlb4KB_m_pendReq_canon = 1'd1 ;
// rule RL_tlbMG_m_incRandIdx
assign CAN_FIRE_RL_tlbMG_m_incRandIdx = 1'd1 ;
assign WILL_FIRE_RL_tlbMG_m_incRandIdx = 1'd1 ;
// rule RL_tlbMG_m_lruBit_canon
assign CAN_FIRE_RL_tlbMG_m_lruBit_canon = 1'd1 ;
assign WILL_FIRE_RL_tlbMG_m_lruBit_canon = 1'd1 ;
// rule RL_tlbMG_m_updRepIdx_canon
assign CAN_FIRE_RL_tlbMG_m_updRepIdx_canon = 1'd1 ;
assign WILL_FIRE_RL_tlbMG_m_updRepIdx_canon = 1'd1 ;
// rule RL_tlbReqQ_empty_canon
assign CAN_FIRE_RL_tlbReqQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_tlbReqQ_empty_canon = 1'd1 ;
// rule RL_tlbReqQ_full_canon
assign CAN_FIRE_RL_tlbReqQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_tlbReqQ_full_canon = 1'd1 ;
// rule RL_transCacheReqQ_empty_canon
assign CAN_FIRE_RL_transCacheReqQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_transCacheReqQ_empty_canon = 1'd1 ;
// rule RL_transCacheReqQ_full_canon
assign CAN_FIRE_RL_transCacheReqQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_transCacheReqQ_full_canon = 1'd1 ;
// rule RL_flushDoneQ_canonicalize
assign CAN_FIRE_RL_flushDoneQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_flushDoneQ_canonicalize = 1'd1 ;
// rule RL_flushDoneQ_enqReq_canon
assign CAN_FIRE_RL_flushDoneQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_flushDoneQ_enqReq_canon = 1'd1 ;
// rule RL_flushDoneQ_deqReq_canon
assign CAN_FIRE_RL_flushDoneQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_flushDoneQ_deqReq_canon = 1'd1 ;
// rule RL_flushDoneQ_clearReq_canon
assign CAN_FIRE_RL_flushDoneQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_flushDoneQ_clearReq_canon = 1'd1 ;
// rule RL_rqFromCQ_data_0_canon
assign CAN_FIRE_RL_rqFromCQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_rqFromCQ_data_0_canon = 1'd1 ;
// rule RL_rqFromCQ_empty_canon
assign CAN_FIRE_RL_rqFromCQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_rqFromCQ_empty_canon = 1'd1 ;
// rule RL_rqFromCQ_full_canon
assign CAN_FIRE_RL_rqFromCQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_rqFromCQ_full_canon = 1'd1 ;
// rule RL_rsToCQ_data_0_canon
assign CAN_FIRE_RL_rsToCQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_rsToCQ_data_0_canon = 1'd1 ;
// rule RL_rsToCQ_empty_canon
assign CAN_FIRE_RL_rsToCQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_rsToCQ_empty_canon = 1'd1 ;
// rule RL_rsToCQ_full_canon
assign CAN_FIRE_RL_rsToCQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_rsToCQ_full_canon = 1'd1 ;
// rule RL_pendValid_0_canon
assign CAN_FIRE_RL_pendValid_0_canon = 1'd1 ;
assign WILL_FIRE_RL_pendValid_0_canon = 1'd1 ;
// rule RL_pendValid_1_canon
assign CAN_FIRE_RL_pendValid_1_canon = 1'd1 ;
assign WILL_FIRE_RL_pendValid_1_canon = 1'd1 ;
// rule RL_pendWait_0_canon
assign CAN_FIRE_RL_pendWait_0_canon = 1'd1 ;
assign WILL_FIRE_RL_pendWait_0_canon = 1'd1 ;
// rule RL_pendWait_1_canon
assign CAN_FIRE_RL_pendWait_1_canon = 1'd1 ;
assign WILL_FIRE_RL_pendWait_1_canon = 1'd1 ;
// rule RL_memReqQ_canonicalize
assign CAN_FIRE_RL_memReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_memReqQ_canonicalize = 1'd1 ;
// rule RL_memReqQ_enqReq_canon
assign CAN_FIRE_RL_memReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_memReqQ_enqReq_canon = 1'd1 ;
// rule RL_memReqQ_deqReq_canon
assign CAN_FIRE_RL_memReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_memReqQ_deqReq_canon = 1'd1 ;
// rule RL_memReqQ_clearReq_canon
assign CAN_FIRE_RL_memReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_memReqQ_clearReq_canon = 1'd1 ;
// rule RL_respLdQ_canonicalize
assign CAN_FIRE_RL_respLdQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_respLdQ_canonicalize = 1'd1 ;
// rule RL_respLdQ_enqReq_canon
assign CAN_FIRE_RL_respLdQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_respLdQ_enqReq_canon = 1'd1 ;
// rule RL_respLdQ_deqReq_canon
assign CAN_FIRE_RL_respLdQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_respLdQ_deqReq_canon = 1'd1 ;
// rule RL_respLdQ_clearReq_canon
assign CAN_FIRE_RL_respLdQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_respLdQ_clearReq_canon = 1'd1 ;
// rule RL_perfReqQ_canonicalize
assign CAN_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
// rule RL_perfReqQ_enqReq_canon
assign CAN_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
// rule RL_perfReqQ_deqReq_canon
assign CAN_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
// rule RL_perfReqQ_clearReq_canon
assign CAN_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_doTranslationCacheResp &&
!IF_NOT_transCacheReqQ_data_0_768_769_OR_NOT_pe_ETC___d1822 ;
assign MUX_memReqQ_enqReq_lat_0$wset_1__SEL_2 =
WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2046 ;
assign MUX_pendValid_0_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_doTlbResp && _dfoo13 ;
assign MUX_pendValid_0_lat_0$wset_1__SEL_2 =
WILL_FIRE_RL_doPageWalk &&
(idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
_dfoo69) ;
assign MUX_pendValid_1_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_doTlbResp && _dfoo9 ;
assign MUX_pendValid_1_lat_0$wset_1__SEL_2 =
WILL_FIRE_RL_doPageWalk &&
(idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
_dfoo65) ;
assign MUX_pendWait_0_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd0 ;
assign MUX_pendWait_1_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd1 ;
assign MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_doTlbResp &&
(IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112 ||
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 ||
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328) ;
assign MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2006 ;
assign MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2056 ;
assign MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 =
WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1737 ;
assign MUX_tlb4KB_m_state$write_1__SEL_1 =
WILL_FIRE_RL_tlb4KB_m_doFlush && tlb4KB_m_flushIdx == 8'd255 ;
assign MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 =
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd0 &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ;
assign MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 =
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd1 &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ;
assign MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 =
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd2 &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ;
assign MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 =
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd3 &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ;
assign MUX_tlbMG_m_updRepIdx_dummy2_1$write_1__SEL_1 =
WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 ;
assign MUX_tlbMG_m_validVec_0$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign MUX_tlbMG_m_validVec_1$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign MUX_tlbMG_m_validVec_2$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd2 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign MUX_tlbMG_m_validVec_3$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd3 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign MUX_tlbMG_m_validVec_4$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd4 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign MUX_tlbMG_m_validVec_5$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd5 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign MUX_tlbMG_m_validVec_6$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd6 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign MUX_tlbMG_m_validVec_7$write_1__SEL_1 =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd7 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1, pteAddr__h133425, transCacheReqQ_data_0 } ;
assign MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1, newPTEAddr__h136649, idx__h135713 } ;
assign MUX_pendWait_0_lat_0$wset_1__VAL_1 =
(transCacheReqQ_data_0 == 1'd0 &&
IF_NOT_transCacheReqQ_data_0_768_769_OR_NOT_pe_ETC___d1822) ?
{ 2'd2,
NOT_transCacheReqQ_data_0_768_769_OR_NOT_pendW_ETC___d1776 ||
!pendWalkAddr_0_786_EQ_0_CONCAT_IF_transCache_r_ETC___d1801 } :
3'd2 ;
assign MUX_pendWait_0_lat_0$wset_1__VAL_2 =
(idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872) ?
3'd0 :
((idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029) ?
3'd0 :
_dfoo56) ;
assign MUX_pendWait_1_lat_0$wset_1__VAL_1 =
(transCacheReqQ_data_0 == 1'd1 &&
IF_NOT_transCacheReqQ_data_0_768_769_OR_NOT_pe_ETC___d1822) ?
{ 2'd2,
NOT_transCacheReqQ_data_0_768_769_OR_NOT_pendW_ETC___d1776 ||
!pendWalkAddr_0_786_EQ_0_CONCAT_IF_transCache_r_ETC___d1801 } :
3'd2 ;
assign MUX_pendWait_1_lat_0$wset_1__VAL_2 =
(idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872) ?
3'd0 :
((idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029) ?
3'd0 :
_dfoo52) ;
assign MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1 =
{ !SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105,
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1378,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677,
IF_IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_ETC___d1716 } ;
assign MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2 =
{ !SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871,
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1990,
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]),
masked_vpn__h137252,
masked_ppn__h137253,
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[7:1],
walkLevel__h136646 } ;
assign MUX_tlb4KB_m_flushIdx$write_1__VAL_1 = tlb4KB_m_flushIdx + 8'd1 ;
assign MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 =
WILL_FIRE_RL_doTlbResp || WILL_FIRE_RL_tlb4KB_m_doAddEntry ;
assign MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1 =
{ 2'd3,
masked_vpn__h137252,
masked_ppn__h137253,
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[7:1],
walkLevel__h136646 } ;
assign MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2 =
{ 55'h4AAAAAAAAAAAAA, vpn__h104314 } ;
assign MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1 =
{ IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1749,
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1750,
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1741 ?
tlb4KB_m_repRam_bram$DOB[3:2] :
tlb4KB_m_repRam_bram$DOB[1:0],
value__h117443 } ;
assign MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3 =
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d265 ?
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d286 :
{ (!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287 &&
tlb4KB_m_repRam_bram$DOB[3:2] !=
tlb4KB_m_repRam_bram$DOB[7:6] &&
tlb4KB_m_repRam_bram$DOB[5:4] !=
tlb4KB_m_repRam_bram$DOB[7:6]) ?
tlb4KB_m_repRam_bram$DOB[5:4] :
tlb4KB_m_repRam_bram$DOB[7:6],
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287 &&
tlb4KB_m_repRam_bram$DOB[3:2] !=
tlb4KB_m_repRam_bram$DOB[7:6]) ?
tlb4KB_m_repRam_bram$DOB[3:2] :
tlb4KB_m_repRam_bram$DOB[5:4],
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287 ?
tlb4KB_m_repRam_bram$DOB[3:2] :
tlb4KB_m_repRam_bram$DOB[1:0],
tlb4KB_m_repRam_bram$DOB[7:6] } ;
assign MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 =
{ 1'd1, tlb4KB_m_pendReq_rl[79:0] } ;
assign MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1 =
(val__h41244 == 8'd255) ? x__h41318 : val__h41244 ;
assign MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 =
WILL_FIRE_RL_tlbMG_m_doUpdateRep || WILL_FIRE_RL_doStartFlush ;
assign MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1 =
{ 1'd1, value__h119411 } ;
assign MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, v__h143190 } ;
// inlined wires
assign tlb4KB_m_pendReq_lat_1$wget =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1 :
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2 ;
assign tlbMG_m_updRepIdx_lat_1$wget =
MUX_tlbMG_m_updRepIdx_dummy2_1$write_1__SEL_1 ?
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1 :
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2 ;
assign tlbMG_m_updRepIdx_lat_1$whas =
WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 ||
WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ;
assign rsToCQ_data_0_lat_0$wget =
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1 ?
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1 :
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2 ;
assign rsToCQ_data_0_lat_0$whas =
WILL_FIRE_RL_doTlbResp &&
(IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112 ||
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 ||
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328) ||
WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2006 ;
assign rsToCQ_empty_dummy_1_0$wget =
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1 ||
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_2 ;
assign rsToCQ_full_lat_0$whas =
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1 ||
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_2 ;
assign pendValid_0_lat_0$whas =
MUX_pendValid_0_lat_0$wset_1__SEL_1 ||
MUX_pendValid_0_lat_0$wset_1__SEL_2 ;
assign pendValid_0_lat_1$whas =
WILL_FIRE_RL_doTlbReq && v__h101631 == 1'd0 ;
assign pendValid_1_lat_0$whas =
MUX_pendValid_1_lat_0$wset_1__SEL_1 ||
MUX_pendValid_1_lat_0$wset_1__SEL_2 ;
assign pendValid_1_lat_1$whas =
WILL_FIRE_RL_doTlbReq && v__h101631 == 1'd1 ;
assign pendWait_0_lat_0$wget =
MUX_pendWait_0_dummy2_0$write_1__SEL_1 ?
MUX_pendWait_0_lat_0$wset_1__VAL_1 :
MUX_pendWait_0_lat_0$wset_1__VAL_2 ;
assign pendWait_0_lat_0$whas =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd0 ||
WILL_FIRE_RL_doPageWalk && _dfoo79 ;
assign pendWait_1_lat_0$wget =
MUX_pendWait_1_dummy2_0$write_1__SEL_1 ?
MUX_pendWait_1_lat_0$wset_1__VAL_1 :
MUX_pendWait_1_lat_0$wset_1__VAL_2 ;
assign pendWait_1_lat_0$whas =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd1 ||
WILL_FIRE_RL_doPageWalk && _dfoo75 ;
assign memReqQ_enqReq_lat_0$wget =
MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_1 ?
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign memReqQ_enqReq_lat_0$whas =
MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_1 ||
MUX_memReqQ_enqReq_lat_0$wset_1__SEL_2 ;
assign respLdQ_enqReq_lat_0$wget = { 1'd1, toMem_respLd_enq_x } ;
assign respLdQ_deqReq_lat_0$whas =
WILL_FIRE_RL_doPageWalk && i__h136071 &&
(!pendWait_1_dummy2_0$Q_OUT || !pendWait_1_dummy2_1$Q_OUT ||
pendWait_1_rl[2:1] == 2'd0 ||
pendWait_1_rl[2:1] == 2'd1 ||
!pendWait_1_rl_18_BIT_0_30_EQ_SEL_ARR_respLdQ_d_ETC___d1964 ||
IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d1977) ;
assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas =
WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2056 ||
WILL_FIRE_RL_doTlbReq ;
assign transCacheReqQ_enqP_lat_0$whas =
WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1754 ;
assign tlb4KB_m_pendIndex$wget =
{ tlb4KB_m_pendReq_dummy2_0$Q_OUT &&
tlb4KB_m_pendReq_dummy2_1$Q_OUT &&
tlb4KB_m_pendReq_rl[81],
tlb4KB_m_pendReq_rl[80] ?
tlb4KB_m_pendReq_rl[60:53] :
tlb4KB_m_pendReq_rl[7:0] } ;
// register dFlushReq
assign dFlushReq$D_IN = !WILL_FIRE_RL_doWaitFlush ;
assign dFlushReq$EN =
WILL_FIRE_RL_doWaitFlush || EN_toChildren_dTlbReqFlush_put ;
// register flushDoneQ_clearReq_rl
assign flushDoneQ_clearReq_rl$D_IN = 1'd0 ;
assign flushDoneQ_clearReq_rl$EN = 1'd1 ;
// register flushDoneQ_deqReq_rl
assign flushDoneQ_deqReq_rl$D_IN = 1'd0 ;
assign flushDoneQ_deqReq_rl$EN = 1'd1 ;
// register flushDoneQ_empty
assign flushDoneQ_empty$D_IN =
flushDoneQ_clearReq_dummy2_1$Q_OUT && flushDoneQ_clearReq_rl ||
NOT_flushDoneQ_enqReq_dummy2_2_read__36_51_OR__ETC___d461 ;
assign flushDoneQ_empty$EN = 1'd1 ;
// register flushDoneQ_enqReq_rl
assign flushDoneQ_enqReq_rl$D_IN = 1'd0 ;
assign flushDoneQ_enqReq_rl$EN = 1'd1 ;
// register flushDoneQ_full
assign flushDoneQ_full$D_IN =
(!flushDoneQ_clearReq_dummy2_1$Q_OUT ||
!flushDoneQ_clearReq_rl) &&
flushDoneQ_enqReq_dummy2_2_read__36_AND_IF_flu_ETC___d448 ;
assign flushDoneQ_full$EN = 1'd1 ;
// register iFlushReq
assign iFlushReq$D_IN = !WILL_FIRE_RL_doWaitFlush ;
assign iFlushReq$EN =
WILL_FIRE_RL_doWaitFlush || EN_toChildren_iTlbReqFlush_put ;
// register memReqQ_clearReq_rl
assign memReqQ_clearReq_rl$D_IN = 1'd0 ;
assign memReqQ_clearReq_rl$EN = 1'd1 ;
// register memReqQ_data_0
assign memReqQ_data_0$D_IN =
memReqQ_enqReq_lat_0$whas ?
memReqQ_enqReq_lat_0$wget[64:0] :
memReqQ_enqReq_rl[64:0] ;
assign memReqQ_data_0$EN =
memReqQ_enqP == 1'd0 &&
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
memReqQ_enqReq_dummy2_2$Q_OUT &&
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648 ;
// register memReqQ_data_1
assign memReqQ_data_1$D_IN =
memReqQ_enqReq_lat_0$whas ?
memReqQ_enqReq_lat_0$wget[64:0] :
memReqQ_enqReq_rl[64:0] ;
assign memReqQ_data_1$EN =
memReqQ_enqP == 1'd1 &&
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
memReqQ_enqReq_dummy2_2$Q_OUT &&
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648 ;
// register memReqQ_deqP
assign memReqQ_deqP$D_IN =
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
_theResult_____2__h82166 ;
assign memReqQ_deqP$EN = 1'd1 ;
// register memReqQ_deqReq_rl
assign memReqQ_deqReq_rl$D_IN = 1'd0 ;
assign memReqQ_deqReq_rl$EN = 1'd1 ;
// register memReqQ_empty
assign memReqQ_empty$D_IN =
memReqQ_clearReq_dummy2_1$Q_OUT && memReqQ_clearReq_rl ||
IF_memReqQ_deqReq_dummy2_2_read__97_AND_IF_mem_ETC___d705 &&
NOT_memReqQ_enqReq_dummy2_2_read__89_19_OR_IF__ETC___d723 ;
assign memReqQ_empty$EN = 1'd1 ;
// register memReqQ_enqP
assign memReqQ_enqP$D_IN =
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
v__h81624 ;
assign memReqQ_enqP$EN = 1'd1 ;
// register memReqQ_enqReq_rl
assign memReqQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
assign memReqQ_enqReq_rl$EN = 1'd1 ;
// register memReqQ_full
assign memReqQ_full$D_IN =
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
IF_memReqQ_deqReq_dummy2_2_read__97_AND_IF_mem_ETC___d705 &&
memReqQ_enqReq_dummy2_2_read__89_AND_IF_memReq_ETC___d715 ;
assign memReqQ_full$EN = 1'd1 ;
// register pendReq_0
assign pendReq_0$D_IN =
{ rqFromCQ_data_0_dummy2_1$Q_OUT &&
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471,
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481,
vpn__h104314 } ;
assign pendReq_0$EN = pendValid_0_lat_1$whas ;
// register pendReq_1
assign pendReq_1$D_IN =
{ rqFromCQ_data_0_dummy2_1$Q_OUT &&
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471,
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481,
vpn__h104314 } ;
assign pendReq_1$EN = pendValid_1_lat_1$whas ;
// register pendValid_0_rl
assign pendValid_0_rl$D_IN =
pendValid_0_lat_1$whas ||
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573 ;
assign pendValid_0_rl$EN = 1'd1 ;
// register pendValid_1_rl
assign pendValid_1_rl$D_IN =
pendValid_1_lat_1$whas ||
IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580 ;
assign pendValid_1_rl$EN = 1'd1 ;
// register pendWait_0_rl
assign pendWait_0_rl$D_IN =
(pendWait_0_lat_0$whas ?
pendWait_0_lat_0$wget[2:1] == 2'd0 :
pendWait_0_rl[2:1] == 2'd0) ?
3'd0 :
((pendWait_0_lat_0$whas ?
pendWait_0_lat_0$wget[2:1] == 2'd1 :
pendWait_0_rl[2:1] == 2'd1) ?
3'd2 :
{ 2'd2,
pendWait_0_lat_0$whas ?
pendWait_0_lat_0$wget[0] :
pendWait_0_rl[0] }) ;
assign pendWait_0_rl$EN = 1'd1 ;
// register pendWait_1_rl
assign pendWait_1_rl$D_IN =
(pendWait_1_lat_0$whas ?
pendWait_1_lat_0$wget[2:1] == 2'd0 :
pendWait_1_rl[2:1] == 2'd0) ?
3'd0 :
((pendWait_1_lat_0$whas ?
pendWait_1_lat_0$wget[2:1] == 2'd1 :
pendWait_1_rl[2:1] == 2'd1) ?
3'd2 :
{ 2'd2,
pendWait_1_lat_0$whas ?
pendWait_1_lat_0$wget[0] :
pendWait_1_rl[0] }) ;
assign pendWait_1_rl$EN = 1'd1 ;
// register pendWalkAddr_0
assign pendWalkAddr_0$D_IN =
MUX_pendWait_0_dummy2_0$write_1__SEL_1 ?
pteAddr__h133425 :
newPTEAddr__h136649 ;
assign pendWalkAddr_0$EN =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd0 ||
WILL_FIRE_RL_doPageWalk && idx__h135713 == 1'd0 ;
// register pendWalkAddr_1
assign pendWalkAddr_1$D_IN =
MUX_pendWait_1_dummy2_0$write_1__SEL_1 ?
pteAddr__h133425 :
newPTEAddr__h136649 ;
assign pendWalkAddr_1$EN =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd1 ||
WILL_FIRE_RL_doPageWalk && idx__h135713 == 1'd1 ;
// register pendWalkLevel_0
assign pendWalkLevel_0$D_IN =
MUX_pendWait_0_dummy2_0$write_1__SEL_1 ?
transCache$resp[45:44] :
newWalkLevel__h136647 ;
assign pendWalkLevel_0$EN =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd0 ||
WILL_FIRE_RL_doPageWalk && idx__h135713 == 1'd0 ;
// register pendWalkLevel_1
assign pendWalkLevel_1$D_IN =
MUX_pendWait_1_dummy2_0$write_1__SEL_1 ?
transCache$resp[45:44] :
newWalkLevel__h136647 ;
assign pendWalkLevel_1$EN =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd1 ||
WILL_FIRE_RL_doPageWalk && idx__h135713 == 1'd1 ;
// register perfReqQ_clearReq_rl
assign perfReqQ_clearReq_rl$D_IN = 1'd0 ;
assign perfReqQ_clearReq_rl$EN = 1'd1 ;
// register perfReqQ_data_0
assign perfReqQ_data_0$D_IN =
EN_perf_req ?
perfReqQ_enqReq_lat_0$wget[3:0] :
perfReqQ_enqReq_rl[3:0] ;
assign perfReqQ_data_0$EN =
NOT_perfReqQ_clearReq_dummy2_1_read__76_77_OR__ETC___d881 &&
perfReqQ_enqReq_dummy2_2$Q_OUT &&
IF_perfReqQ_enqReq_lat_1_whas__32_THEN_perfReq_ETC___d841 ;
// register perfReqQ_deqReq_rl
assign perfReqQ_deqReq_rl$D_IN = 1'd0 ;
assign perfReqQ_deqReq_rl$EN = 1'd1 ;
// register perfReqQ_empty
assign perfReqQ_empty$D_IN =
perfReqQ_clearReq_dummy2_1$Q_OUT && perfReqQ_clearReq_rl ||
NOT_perfReqQ_enqReq_dummy2_2_read__82_97_OR_IF_ETC___d902 ;
assign perfReqQ_empty$EN = 1'd1 ;
// register perfReqQ_enqReq_rl
assign perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
assign perfReqQ_enqReq_rl$EN = 1'd1 ;
// register perfReqQ_full
assign perfReqQ_full$D_IN =
NOT_perfReqQ_clearReq_dummy2_1_read__76_77_OR__ETC___d881 &&
perfReqQ_enqReq_dummy2_2_read__82_AND_IF_perfR_ETC___d894 ;
assign perfReqQ_full$EN = 1'd1 ;
// register respForOtherReq
assign respForOtherReq$D_IN =
{ IF_NOT_pendWait_0_dummy2_0_read__770_771_OR_NO_ETC___d1967,
i__h136071 } ;
assign respForOtherReq$EN = WILL_FIRE_RL_doPageWalk ;
// register respLdQ_clearReq_rl
assign respLdQ_clearReq_rl$D_IN = 1'd0 ;
assign respLdQ_clearReq_rl$EN = 1'd1 ;
// register respLdQ_data_0
assign respLdQ_data_0$D_IN =
EN_toMem_respLd_enq ?
respLdQ_enqReq_lat_0$wget[64:0] :
respLdQ_enqReq_rl[64:0] ;
assign respLdQ_data_0$EN =
respLdQ_enqP == 1'd0 &&
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
respLdQ_enqReq_dummy2_2$Q_OUT &&
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745 ;
// register respLdQ_data_1
assign respLdQ_data_1$D_IN =
EN_toMem_respLd_enq ?
respLdQ_enqReq_lat_0$wget[64:0] :
respLdQ_enqReq_rl[64:0] ;
assign respLdQ_data_1$EN =
respLdQ_enqP == 1'd1 &&
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
respLdQ_enqReq_dummy2_2$Q_OUT &&
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745 ;
// register respLdQ_deqP
assign respLdQ_deqP$D_IN =
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
_theResult_____2__h89736 ;
assign respLdQ_deqP$EN = 1'd1 ;
// register respLdQ_deqReq_rl
assign respLdQ_deqReq_rl$D_IN = 1'd0 ;
assign respLdQ_deqReq_rl$EN = 1'd1 ;
// register respLdQ_empty
assign respLdQ_empty$D_IN =
respLdQ_clearReq_dummy2_1$Q_OUT && respLdQ_clearReq_rl ||
IF_respLdQ_deqReq_dummy2_2_read__94_AND_IF_res_ETC___d802 &&
NOT_respLdQ_enqReq_dummy2_2_read__86_16_OR_IF__ETC___d820 ;
assign respLdQ_empty$EN = 1'd1 ;
// register respLdQ_enqP
assign respLdQ_enqP$D_IN =
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
v__h89194 ;
assign respLdQ_enqP$EN = 1'd1 ;
// register respLdQ_enqReq_rl
assign respLdQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
assign respLdQ_enqReq_rl$EN = 1'd1 ;
// register respLdQ_full
assign respLdQ_full$D_IN =
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
IF_respLdQ_deqReq_dummy2_2_read__94_AND_IF_res_ETC___d802 &&
respLdQ_enqReq_dummy2_2_read__86_AND_IF_respLd_ETC___d812 ;
assign respLdQ_full$EN = 1'd1 ;
// register rqFromCQ_data_0_rl
assign rqFromCQ_data_0_rl$D_IN =
{ IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471,
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481,
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d487 } ;
assign rqFromCQ_data_0_rl$EN = 1'd1 ;
// register rqFromCQ_empty_rl
assign rqFromCQ_empty_rl$D_IN =
CAN_FIRE_RL_doTlbReq ||
!EN_toChildren_rqFromC_put && rqFromCQ_empty_rl ;
assign rqFromCQ_empty_rl$EN = 1'd1 ;
// register rqFromCQ_full_rl
assign rqFromCQ_full_rl$D_IN =
!CAN_FIRE_RL_doTlbReq &&
(EN_toChildren_rqFromC_put || rqFromCQ_full_rl) ;
assign rqFromCQ_full_rl$EN = 1'd1 ;
// register rsToCQ_data_0_rl
assign rsToCQ_data_0_rl$D_IN =
{ IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d518,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d528,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d534,
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d544 } ;
assign rsToCQ_data_0_rl$EN = 1'd1 ;
// register rsToCQ_empty_rl
assign rsToCQ_empty_rl$D_IN =
EN_toChildren_rsToC_deq ||
(rsToCQ_empty_dummy_1_0$wget ? 1'd0 : rsToCQ_empty_rl) ;
assign rsToCQ_empty_rl$EN = 1'd1 ;
// register rsToCQ_full_rl
assign rsToCQ_full_rl$D_IN =
!EN_toChildren_rsToC_deq &&
(rsToCQ_full_lat_0$whas ? 1'd1 : rsToCQ_full_rl) ;
assign rsToCQ_full_rl$EN = 1'd1 ;
// register tlb4KB_m_flushIdx
assign tlb4KB_m_flushIdx$D_IN =
WILL_FIRE_RL_tlb4KB_m_doFlush ?
MUX_tlb4KB_m_flushIdx$write_1__VAL_1 :
8'd0 ;
assign tlb4KB_m_flushIdx$EN =
WILL_FIRE_RL_tlb4KB_m_doFlush || WILL_FIRE_RL_doStartFlush ;
// register tlb4KB_m_pendReq_rl
assign tlb4KB_m_pendReq_rl$D_IN =
{ IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110,
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138 } ;
assign tlb4KB_m_pendReq_rl$EN = 1'd1 ;
// register tlb4KB_m_repRam_rdReqQ_empty_rl
assign tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd0 :
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
tlb4KB_m_repRam_rdReqQ_empty_rl ;
assign tlb4KB_m_repRam_rdReqQ_empty_rl$EN = 1'd1 ;
// register tlb4KB_m_repRam_rdReqQ_full_rl
assign tlb4KB_m_repRam_rdReqQ_full_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd1 :
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
tlb4KB_m_repRam_rdReqQ_full_rl ;
assign tlb4KB_m_repRam_rdReqQ_full_rl$EN = 1'd1 ;
// register tlb4KB_m_state
assign tlb4KB_m_state$D_IN = MUX_tlb4KB_m_state$write_1__SEL_1 ;
assign tlb4KB_m_state$EN =
WILL_FIRE_RL_tlb4KB_m_doFlush && tlb4KB_m_flushIdx == 8'd255 ||
WILL_FIRE_RL_doStartFlush ;
// register tlb4KB_m_tlbRam_0_rdReqQ_empty_rl
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd0 :
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl ;
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN = 1'd1 ;
// register tlb4KB_m_tlbRam_0_rdReqQ_full_rl
assign tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd1 :
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
tlb4KB_m_tlbRam_0_rdReqQ_full_rl ;
assign tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN = 1'd1 ;
// register tlb4KB_m_tlbRam_1_rdReqQ_empty_rl
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd0 :
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl ;
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN = 1'd1 ;
// register tlb4KB_m_tlbRam_1_rdReqQ_full_rl
assign tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd1 :
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
tlb4KB_m_tlbRam_1_rdReqQ_full_rl ;
assign tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN = 1'd1 ;
// register tlb4KB_m_tlbRam_2_rdReqQ_empty_rl
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd0 :
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl ;
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN = 1'd1 ;
// register tlb4KB_m_tlbRam_2_rdReqQ_full_rl
assign tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd1 :
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
tlb4KB_m_tlbRam_2_rdReqQ_full_rl ;
assign tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN = 1'd1 ;
// register tlb4KB_m_tlbRam_3_rdReqQ_empty_rl
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd0 :
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl ;
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN = 1'd1 ;
// register tlb4KB_m_tlbRam_3_rdReqQ_full_rl
assign tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
1'd1 :
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
tlb4KB_m_tlbRam_3_rdReqQ_full_rl ;
assign tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN = 1'd1 ;
// register tlbMG_m_entryVec_0
assign tlbMG_m_entryVec_0$D_IN = tlbMG_m_entryVec_1$D_IN ;
assign tlbMG_m_entryVec_0$EN = MUX_tlbMG_m_validVec_0$write_1__SEL_1 ;
// register tlbMG_m_entryVec_1
assign tlbMG_m_entryVec_1$D_IN =
{ masked_vpn__h137252,
masked_ppn__h137253,
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[7:1],
walkLevel__h136646 } ;
assign tlbMG_m_entryVec_1$EN = MUX_tlbMG_m_validVec_1$write_1__SEL_1 ;
// register tlbMG_m_entryVec_2
assign tlbMG_m_entryVec_2$D_IN = tlbMG_m_entryVec_1$D_IN ;
assign tlbMG_m_entryVec_2$EN = MUX_tlbMG_m_validVec_2$write_1__SEL_1 ;
// register tlbMG_m_entryVec_3
assign tlbMG_m_entryVec_3$D_IN = tlbMG_m_entryVec_1$D_IN ;
assign tlbMG_m_entryVec_3$EN = MUX_tlbMG_m_validVec_3$write_1__SEL_1 ;
// register tlbMG_m_entryVec_4
assign tlbMG_m_entryVec_4$D_IN = tlbMG_m_entryVec_1$D_IN ;
assign tlbMG_m_entryVec_4$EN = MUX_tlbMG_m_validVec_4$write_1__SEL_1 ;
// register tlbMG_m_entryVec_5
assign tlbMG_m_entryVec_5$D_IN = tlbMG_m_entryVec_1$D_IN ;
assign tlbMG_m_entryVec_5$EN = MUX_tlbMG_m_validVec_5$write_1__SEL_1 ;
// register tlbMG_m_entryVec_6
assign tlbMG_m_entryVec_6$D_IN = tlbMG_m_entryVec_1$D_IN ;
assign tlbMG_m_entryVec_6$EN = MUX_tlbMG_m_validVec_6$write_1__SEL_1 ;
// register tlbMG_m_entryVec_7
assign tlbMG_m_entryVec_7$D_IN = tlbMG_m_entryVec_1$D_IN ;
assign tlbMG_m_entryVec_7$EN = MUX_tlbMG_m_validVec_7$write_1__SEL_1 ;
// register tlbMG_m_lruBit_rl
assign tlbMG_m_lruBit_rl$D_IN =
IF_tlbMG_m_lruBit_lat_0_whas__18_THEN_tlbMG_m__ETC___d321 ;
assign tlbMG_m_lruBit_rl$EN = 1'd1 ;
// register tlbMG_m_randIdx
assign tlbMG_m_randIdx$D_IN = tlbMG_m_randIdx + 3'd1 ;
assign tlbMG_m_randIdx$EN = 1'd1 ;
// register tlbMG_m_updRepIdx_rl
assign tlbMG_m_updRepIdx_rl$D_IN =
{ IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d332,
IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d342 } ;
assign tlbMG_m_updRepIdx_rl$EN = 1'd1 ;
// register tlbMG_m_validVec_0
assign tlbMG_m_validVec_0$D_IN = MUX_tlbMG_m_validVec_0$write_1__SEL_1 ;
assign tlbMG_m_validVec_0$EN =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ||
WILL_FIRE_RL_doStartFlush ;
// register tlbMG_m_validVec_1
assign tlbMG_m_validVec_1$D_IN = MUX_tlbMG_m_validVec_1$write_1__SEL_1 ;
assign tlbMG_m_validVec_1$EN =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ||
WILL_FIRE_RL_doStartFlush ;
// register tlbMG_m_validVec_2
assign tlbMG_m_validVec_2$D_IN = MUX_tlbMG_m_validVec_2$write_1__SEL_1 ;
assign tlbMG_m_validVec_2$EN =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd2 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ||
WILL_FIRE_RL_doStartFlush ;
// register tlbMG_m_validVec_3
assign tlbMG_m_validVec_3$D_IN = MUX_tlbMG_m_validVec_3$write_1__SEL_1 ;
assign tlbMG_m_validVec_3$EN =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd3 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ||
WILL_FIRE_RL_doStartFlush ;
// register tlbMG_m_validVec_4
assign tlbMG_m_validVec_4$D_IN = MUX_tlbMG_m_validVec_4$write_1__SEL_1 ;
assign tlbMG_m_validVec_4$EN =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd4 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ||
WILL_FIRE_RL_doStartFlush ;
// register tlbMG_m_validVec_5
assign tlbMG_m_validVec_5$D_IN = MUX_tlbMG_m_validVec_5$write_1__SEL_1 ;
assign tlbMG_m_validVec_5$EN =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd5 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ||
WILL_FIRE_RL_doStartFlush ;
// register tlbMG_m_validVec_6
assign tlbMG_m_validVec_6$D_IN = MUX_tlbMG_m_validVec_6$write_1__SEL_1 ;
assign tlbMG_m_validVec_6$EN =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd6 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ||
WILL_FIRE_RL_doStartFlush ;
// register tlbMG_m_validVec_7
assign tlbMG_m_validVec_7$D_IN = MUX_tlbMG_m_validVec_7$write_1__SEL_1 ;
assign tlbMG_m_validVec_7$EN =
WILL_FIRE_RL_doPageWalk && v__h143190 == 3'd7 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 ||
WILL_FIRE_RL_doStartFlush ;
// register tlbReqQ_data_0
assign tlbReqQ_data_0$D_IN = v__h101631 ;
assign tlbReqQ_data_0$EN = CAN_FIRE_RL_doTlbReq ;
// register tlbReqQ_empty_rl
assign tlbReqQ_empty_rl$D_IN =
!CAN_FIRE_RL_doTlbReq &&
(CAN_FIRE_RL_doTlbResp || tlbReqQ_empty_rl) ;
assign tlbReqQ_empty_rl$EN = 1'd1 ;
// register tlbReqQ_full_rl
assign tlbReqQ_full_rl$D_IN =
CAN_FIRE_RL_doTlbReq ||
!CAN_FIRE_RL_doTlbResp && tlbReqQ_full_rl ;
assign tlbReqQ_full_rl$EN = 1'd1 ;
// register transCacheReqQ_data_0
assign transCacheReqQ_data_0$D_IN = tlbReqQ_data_0 ;
assign transCacheReqQ_data_0$EN = transCacheReqQ_enqP_lat_0$whas ;
// register transCacheReqQ_empty_rl
assign transCacheReqQ_empty_rl$D_IN =
!transCacheReqQ_enqP_lat_0$whas &&
(CAN_FIRE_RL_doTranslationCacheResp || transCacheReqQ_empty_rl) ;
assign transCacheReqQ_empty_rl$EN = 1'd1 ;
// register transCacheReqQ_full_rl
assign transCacheReqQ_full_rl$D_IN =
transCacheReqQ_enqP_lat_0$whas ||
!CAN_FIRE_RL_doTranslationCacheResp && transCacheReqQ_full_rl ;
assign transCacheReqQ_full_rl$EN = 1'd1 ;
// register vm_info_D
assign vm_info_D$D_IN = updateVMInfo_vmD ;
assign vm_info_D$EN = EN_updateVMInfo ;
// register vm_info_I
assign vm_info_I$D_IN = updateVMInfo_vmI ;
assign vm_info_I$EN = EN_updateVMInfo ;
// register waitFlushDone
assign waitFlushDone$D_IN = !WILL_FIRE_RL_doWaitFlush ;
assign waitFlushDone$EN =
WILL_FIRE_RL_doWaitFlush || WILL_FIRE_RL_doStartFlush ;
// submodule flushDoneQ_clearReq_dummy2_0
assign flushDoneQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign flushDoneQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule flushDoneQ_clearReq_dummy2_1
assign flushDoneQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign flushDoneQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule flushDoneQ_deqReq_dummy2_0
assign flushDoneQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign flushDoneQ_deqReq_dummy2_0$EN = EN_toChildren_flushDone_get ;
// submodule flushDoneQ_deqReq_dummy2_1
assign flushDoneQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign flushDoneQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule flushDoneQ_deqReq_dummy2_2
assign flushDoneQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign flushDoneQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule flushDoneQ_enqReq_dummy2_0
assign flushDoneQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign flushDoneQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_doWaitFlush ;
// submodule flushDoneQ_enqReq_dummy2_1
assign flushDoneQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign flushDoneQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule flushDoneQ_enqReq_dummy2_2
assign flushDoneQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign flushDoneQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule memReqQ_clearReq_dummy2_0
assign memReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign memReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule memReqQ_clearReq_dummy2_1
assign memReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign memReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule memReqQ_deqReq_dummy2_0
assign memReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign memReqQ_deqReq_dummy2_0$EN = EN_toMem_memReq_deq ;
// submodule memReqQ_deqReq_dummy2_1
assign memReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign memReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule memReqQ_deqReq_dummy2_2
assign memReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign memReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule memReqQ_enqReq_dummy2_0
assign memReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign memReqQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_doTranslationCacheResp &&
!IF_NOT_transCacheReqQ_data_0_768_769_OR_NOT_pe_ETC___d1822 ||
WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2046 ;
// submodule memReqQ_enqReq_dummy2_1
assign memReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign memReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule memReqQ_enqReq_dummy2_2
assign memReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign memReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule pendValid_0_dummy2_0
assign pendValid_0_dummy2_0$D_IN = 1'd1 ;
assign pendValid_0_dummy2_0$EN =
WILL_FIRE_RL_doTlbResp && _dfoo13 ||
WILL_FIRE_RL_doPageWalk && _dfoo85 ;
// submodule pendValid_0_dummy2_1
assign pendValid_0_dummy2_1$D_IN = 1'd1 ;
assign pendValid_0_dummy2_1$EN = pendValid_0_lat_1$whas ;
// submodule pendValid_1_dummy2_0
assign pendValid_1_dummy2_0$D_IN = 1'd1 ;
assign pendValid_1_dummy2_0$EN =
WILL_FIRE_RL_doTlbResp && _dfoo9 ||
WILL_FIRE_RL_doPageWalk && _dfoo81 ;
// submodule pendValid_1_dummy2_1
assign pendValid_1_dummy2_1$D_IN = 1'd1 ;
assign pendValid_1_dummy2_1$EN = pendValid_1_lat_1$whas ;
// submodule pendWait_0_dummy2_0
assign pendWait_0_dummy2_0$D_IN = 1'd1 ;
assign pendWait_0_dummy2_0$EN =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd0 ||
WILL_FIRE_RL_doPageWalk && _dfoo77 ;
// submodule pendWait_0_dummy2_1
assign pendWait_0_dummy2_1$D_IN = 1'b0 ;
assign pendWait_0_dummy2_1$EN = 1'b0 ;
// submodule pendWait_1_dummy2_0
assign pendWait_1_dummy2_0$D_IN = 1'd1 ;
assign pendWait_1_dummy2_0$EN =
WILL_FIRE_RL_doTranslationCacheResp &&
transCacheReqQ_data_0 == 1'd1 ||
WILL_FIRE_RL_doPageWalk && _dfoo73 ;
// submodule pendWait_1_dummy2_1
assign pendWait_1_dummy2_1$D_IN = 1'b0 ;
assign pendWait_1_dummy2_1$EN = 1'b0 ;
// submodule perfReqQ_clearReq_dummy2_0
assign perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule perfReqQ_clearReq_dummy2_1
assign perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule perfReqQ_deqReq_dummy2_0
assign perfReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign perfReqQ_deqReq_dummy2_0$EN = EN_perf_resp ;
// submodule perfReqQ_deqReq_dummy2_1
assign perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule perfReqQ_deqReq_dummy2_2
assign perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule perfReqQ_enqReq_dummy2_0
assign perfReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign perfReqQ_enqReq_dummy2_0$EN = EN_perf_req ;
// submodule perfReqQ_enqReq_dummy2_1
assign perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule perfReqQ_enqReq_dummy2_2
assign perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule respLdQ_clearReq_dummy2_0
assign respLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign respLdQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule respLdQ_clearReq_dummy2_1
assign respLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign respLdQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule respLdQ_deqReq_dummy2_0
assign respLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign respLdQ_deqReq_dummy2_0$EN = respLdQ_deqReq_lat_0$whas ;
// submodule respLdQ_deqReq_dummy2_1
assign respLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign respLdQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule respLdQ_deqReq_dummy2_2
assign respLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign respLdQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule respLdQ_enqReq_dummy2_0
assign respLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign respLdQ_enqReq_dummy2_0$EN = EN_toMem_respLd_enq ;
// submodule respLdQ_enqReq_dummy2_1
assign respLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign respLdQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule respLdQ_enqReq_dummy2_2
assign respLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign respLdQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule rqFromCQ_data_0_dummy2_0
assign rqFromCQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign rqFromCQ_data_0_dummy2_0$EN = EN_toChildren_rqFromC_put ;
// submodule rqFromCQ_data_0_dummy2_1
assign rqFromCQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign rqFromCQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule rqFromCQ_deqP_dummy2_0
assign rqFromCQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign rqFromCQ_deqP_dummy2_0$EN = CAN_FIRE_RL_doTlbReq ;
// submodule rqFromCQ_deqP_dummy2_1
assign rqFromCQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign rqFromCQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule rqFromCQ_empty_dummy2_0
assign rqFromCQ_empty_dummy2_0$D_IN = 1'd1 ;
assign rqFromCQ_empty_dummy2_0$EN = EN_toChildren_rqFromC_put ;
// submodule rqFromCQ_empty_dummy2_1
assign rqFromCQ_empty_dummy2_1$D_IN = 1'd1 ;
assign rqFromCQ_empty_dummy2_1$EN = CAN_FIRE_RL_doTlbReq ;
// submodule rqFromCQ_empty_dummy2_2
assign rqFromCQ_empty_dummy2_2$D_IN = 1'b0 ;
assign rqFromCQ_empty_dummy2_2$EN = 1'b0 ;
// submodule rqFromCQ_enqP_dummy2_0
assign rqFromCQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign rqFromCQ_enqP_dummy2_0$EN = EN_toChildren_rqFromC_put ;
// submodule rqFromCQ_enqP_dummy2_1
assign rqFromCQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign rqFromCQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule rqFromCQ_full_dummy2_0
assign rqFromCQ_full_dummy2_0$D_IN = 1'd1 ;
assign rqFromCQ_full_dummy2_0$EN = EN_toChildren_rqFromC_put ;
// submodule rqFromCQ_full_dummy2_1
assign rqFromCQ_full_dummy2_1$D_IN = 1'd1 ;
assign rqFromCQ_full_dummy2_1$EN = CAN_FIRE_RL_doTlbReq ;
// submodule rqFromCQ_full_dummy2_2
assign rqFromCQ_full_dummy2_2$D_IN = 1'b0 ;
assign rqFromCQ_full_dummy2_2$EN = 1'b0 ;
// submodule rsToCQ_data_0_dummy2_0
assign rsToCQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign rsToCQ_data_0_dummy2_0$EN = rsToCQ_data_0_lat_0$whas ;
// submodule rsToCQ_data_0_dummy2_1
assign rsToCQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign rsToCQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule rsToCQ_deqP_dummy2_0
assign rsToCQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign rsToCQ_deqP_dummy2_0$EN = EN_toChildren_rsToC_deq ;
// submodule rsToCQ_deqP_dummy2_1
assign rsToCQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign rsToCQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule rsToCQ_empty_dummy2_0
assign rsToCQ_empty_dummy2_0$D_IN = 1'd1 ;
assign rsToCQ_empty_dummy2_0$EN = rsToCQ_data_0_lat_0$whas ;
// submodule rsToCQ_empty_dummy2_1
assign rsToCQ_empty_dummy2_1$D_IN = 1'd1 ;
assign rsToCQ_empty_dummy2_1$EN = EN_toChildren_rsToC_deq ;
// submodule rsToCQ_empty_dummy2_2
assign rsToCQ_empty_dummy2_2$D_IN = 1'b0 ;
assign rsToCQ_empty_dummy2_2$EN = 1'b0 ;
// submodule rsToCQ_enqP_dummy2_0
assign rsToCQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign rsToCQ_enqP_dummy2_0$EN = rsToCQ_data_0_lat_0$whas ;
// submodule rsToCQ_enqP_dummy2_1
assign rsToCQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign rsToCQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule rsToCQ_full_dummy2_0
assign rsToCQ_full_dummy2_0$D_IN = 1'd1 ;
assign rsToCQ_full_dummy2_0$EN = rsToCQ_data_0_lat_0$whas ;
// submodule rsToCQ_full_dummy2_1
assign rsToCQ_full_dummy2_1$D_IN = 1'd1 ;
assign rsToCQ_full_dummy2_1$EN = EN_toChildren_rsToC_deq ;
// submodule rsToCQ_full_dummy2_2
assign rsToCQ_full_dummy2_2$D_IN = 1'b0 ;
assign rsToCQ_full_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_pendReq_dummy2_0
assign tlb4KB_m_pendReq_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_pendReq_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_pendReq_dummy2_1
assign tlb4KB_m_pendReq_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_pendReq_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_repRam_bram
always@(MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 or
tlb4KB_m_pendReq_rl or
WILL_FIRE_RL_tlb4KB_m_doFlush or
tlb4KB_m_flushIdx or WILL_FIRE_RL_tlb4KB_m_doAddEntry)
begin
case (1'b1) // synopsys parallel_case
MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1:
tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_pendReq_rl[7:0];
WILL_FIRE_RL_tlb4KB_m_doFlush:
tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_flushIdx;
WILL_FIRE_RL_tlb4KB_m_doAddEntry:
tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_pendReq_rl[60:53];
default: tlb4KB_m_repRam_bram$ADDRA =
8'b10101010 /* unspecified value */ ;
endcase
end
assign tlb4KB_m_repRam_bram$ADDRB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
masked_vpn__h137252[7:0] :
vpn__h104314[7:0] ;
always@(MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 or
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1 or
WILL_FIRE_RL_tlb4KB_m_doFlush or
WILL_FIRE_RL_tlb4KB_m_doAddEntry or
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1:
tlb4KB_m_repRam_bram$DIA = MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1;
WILL_FIRE_RL_tlb4KB_m_doFlush: tlb4KB_m_repRam_bram$DIA = 8'd228;
WILL_FIRE_RL_tlb4KB_m_doAddEntry:
tlb4KB_m_repRam_bram$DIA = MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3;
default: tlb4KB_m_repRam_bram$DIA =
8'b10101010 /* unspecified value */ ;
endcase
end
assign tlb4KB_m_repRam_bram$DIB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
8'b10101010 /* unspecified value */ :
8'b10101010 /* unspecified value */ ;
assign tlb4KB_m_repRam_bram$WEA = 1'd1 ;
assign tlb4KB_m_repRam_bram$WEB = 1'd0 ;
assign tlb4KB_m_repRam_bram$ENA =
WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1737 ||
WILL_FIRE_RL_tlb4KB_m_doFlush ||
WILL_FIRE_RL_tlb4KB_m_doAddEntry ;
assign tlb4KB_m_repRam_bram$ENB = tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0
assign tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1
assign tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_0
assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_1
assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_2
assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0
assign tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1
assign tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_0
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_1
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_2
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_0_bram
assign tlb4KB_m_tlbRam_0_bram$ADDRA =
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 ?
tlb4KB_m_pendReq_rl[60:53] :
tlb4KB_m_flushIdx ;
assign tlb4KB_m_tlbRam_0_bram$ADDRB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
masked_vpn__h137252[7:0] :
vpn__h104314[7:0] ;
assign tlb4KB_m_tlbRam_0_bram$DIA =
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 ?
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
81'h0AAAAAAAAAAAAAAAAAAAA ;
assign tlb4KB_m_tlbRam_0_bram$DIB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign tlb4KB_m_tlbRam_0_bram$WEA = 1'd1 ;
assign tlb4KB_m_tlbRam_0_bram$WEB = 1'd0 ;
assign tlb4KB_m_tlbRam_0_bram$ENA =
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd0 &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ||
WILL_FIRE_RL_tlb4KB_m_doFlush ;
assign tlb4KB_m_tlbRam_0_bram$ENB =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_1_bram
assign tlb4KB_m_tlbRam_1_bram$ADDRA =
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 ?
tlb4KB_m_pendReq_rl[60:53] :
tlb4KB_m_flushIdx ;
assign tlb4KB_m_tlbRam_1_bram$ADDRB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
masked_vpn__h137252[7:0] :
vpn__h104314[7:0] ;
assign tlb4KB_m_tlbRam_1_bram$DIA =
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 ?
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
81'h0AAAAAAAAAAAAAAAAAAAA ;
assign tlb4KB_m_tlbRam_1_bram$DIB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign tlb4KB_m_tlbRam_1_bram$WEA = 1'd1 ;
assign tlb4KB_m_tlbRam_1_bram$WEB = 1'd0 ;
assign tlb4KB_m_tlbRam_1_bram$ENA =
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd1 &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ||
WILL_FIRE_RL_tlb4KB_m_doFlush ;
assign tlb4KB_m_tlbRam_1_bram$ENB =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0
assign tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1
assign tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0
assign tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1
assign tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_2_bram
assign tlb4KB_m_tlbRam_2_bram$ADDRA =
MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 ?
tlb4KB_m_pendReq_rl[60:53] :
tlb4KB_m_flushIdx ;
assign tlb4KB_m_tlbRam_2_bram$ADDRB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
masked_vpn__h137252[7:0] :
vpn__h104314[7:0] ;
assign tlb4KB_m_tlbRam_2_bram$DIA =
MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 ?
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
81'h0AAAAAAAAAAAAAAAAAAAA ;
assign tlb4KB_m_tlbRam_2_bram$DIB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign tlb4KB_m_tlbRam_2_bram$WEA = 1'd1 ;
assign tlb4KB_m_tlbRam_2_bram$WEB = 1'd0 ;
assign tlb4KB_m_tlbRam_2_bram$ENA =
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd2 &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ||
WILL_FIRE_RL_tlb4KB_m_doFlush ;
assign tlb4KB_m_tlbRam_2_bram$ENB =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0
assign tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1
assign tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0
assign tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1
assign tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_3_bram
assign tlb4KB_m_tlbRam_3_bram$ADDRA =
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 ?
tlb4KB_m_pendReq_rl[60:53] :
tlb4KB_m_flushIdx ;
assign tlb4KB_m_tlbRam_3_bram$ADDRB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
masked_vpn__h137252[7:0] :
vpn__h104314[7:0] ;
assign tlb4KB_m_tlbRam_3_bram$DIA =
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 ?
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
81'h0AAAAAAAAAAAAAAAAAAAA ;
assign tlb4KB_m_tlbRam_3_bram$DIB =
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign tlb4KB_m_tlbRam_3_bram$WEA = 1'd1 ;
assign tlb4KB_m_tlbRam_3_bram$WEB = 1'd0 ;
assign tlb4KB_m_tlbRam_3_bram$ENA =
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd3 &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ||
WILL_FIRE_RL_tlb4KB_m_doFlush ;
assign tlb4KB_m_tlbRam_3_bram$ENB =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0
assign tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1
assign tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0
assign tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1
assign tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$EN =
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$EN =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$EN = 1'b0 ;
// submodule tlbMG_m_lruBit_dummy2_0
assign tlbMG_m_lruBit_dummy2_0$D_IN = 1'd1 ;
assign tlbMG_m_lruBit_dummy2_0$EN =
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule tlbMG_m_lruBit_dummy2_1
assign tlbMG_m_lruBit_dummy2_1$D_IN = 1'b0 ;
assign tlbMG_m_lruBit_dummy2_1$EN = 1'b0 ;
// submodule tlbMG_m_updRepIdx_dummy2_0
assign tlbMG_m_updRepIdx_dummy2_0$D_IN = 1'd1 ;
assign tlbMG_m_updRepIdx_dummy2_0$EN =
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule tlbMG_m_updRepIdx_dummy2_1
assign tlbMG_m_updRepIdx_dummy2_1$D_IN = 1'd1 ;
assign tlbMG_m_updRepIdx_dummy2_1$EN = tlbMG_m_updRepIdx_lat_1$whas ;
// submodule tlbReqQ_deqP_dummy2_0
assign tlbReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign tlbReqQ_deqP_dummy2_0$EN = CAN_FIRE_RL_doTlbResp ;
// submodule tlbReqQ_deqP_dummy2_1
assign tlbReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign tlbReqQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule tlbReqQ_empty_dummy2_0
assign tlbReqQ_empty_dummy2_0$D_IN = 1'd1 ;
assign tlbReqQ_empty_dummy2_0$EN = CAN_FIRE_RL_doTlbResp ;
// submodule tlbReqQ_empty_dummy2_1
assign tlbReqQ_empty_dummy2_1$D_IN = 1'd1 ;
assign tlbReqQ_empty_dummy2_1$EN = CAN_FIRE_RL_doTlbReq ;
// submodule tlbReqQ_empty_dummy2_2
assign tlbReqQ_empty_dummy2_2$D_IN = 1'b0 ;
assign tlbReqQ_empty_dummy2_2$EN = 1'b0 ;
// submodule tlbReqQ_enqP_dummy2_0
assign tlbReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign tlbReqQ_enqP_dummy2_0$EN = CAN_FIRE_RL_doTlbReq ;
// submodule tlbReqQ_enqP_dummy2_1
assign tlbReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign tlbReqQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule tlbReqQ_full_dummy2_0
assign tlbReqQ_full_dummy2_0$D_IN = 1'd1 ;
assign tlbReqQ_full_dummy2_0$EN = CAN_FIRE_RL_doTlbResp ;
// submodule tlbReqQ_full_dummy2_1
assign tlbReqQ_full_dummy2_1$D_IN = 1'd1 ;
assign tlbReqQ_full_dummy2_1$EN = CAN_FIRE_RL_doTlbReq ;
// submodule tlbReqQ_full_dummy2_2
assign tlbReqQ_full_dummy2_2$D_IN = 1'b0 ;
assign tlbReqQ_full_dummy2_2$EN = 1'b0 ;
// submodule transCache
assign transCache$addEntry_level = walkLevel__h136646 ;
assign transCache$addEntry_ppn =
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[53:10] ;
assign transCache$addEntry_vpn =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899 ;
assign transCache$req_vpn =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138 ;
assign transCache$EN_req =
WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1754 ;
assign transCache$EN_deqResp = CAN_FIRE_RL_doTranslationCacheResp ;
assign transCache$EN_addEntry =
WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2] &&
walkLevel__h136646 != 2'd0 ;
assign transCache$EN_flush = CAN_FIRE_RL_doStartFlush ;
// submodule transCacheReqQ_deqP_dummy2_0
assign transCacheReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign transCacheReqQ_deqP_dummy2_0$EN =
CAN_FIRE_RL_doTranslationCacheResp ;
// submodule transCacheReqQ_deqP_dummy2_1
assign transCacheReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign transCacheReqQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule transCacheReqQ_empty_dummy2_0
assign transCacheReqQ_empty_dummy2_0$D_IN = 1'd1 ;
assign transCacheReqQ_empty_dummy2_0$EN =
CAN_FIRE_RL_doTranslationCacheResp ;
// submodule transCacheReqQ_empty_dummy2_1
assign transCacheReqQ_empty_dummy2_1$D_IN = 1'd1 ;
assign transCacheReqQ_empty_dummy2_1$EN = transCacheReqQ_enqP_lat_0$whas ;
// submodule transCacheReqQ_empty_dummy2_2
assign transCacheReqQ_empty_dummy2_2$D_IN = 1'b0 ;
assign transCacheReqQ_empty_dummy2_2$EN = 1'b0 ;
// submodule transCacheReqQ_enqP_dummy2_0
assign transCacheReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign transCacheReqQ_enqP_dummy2_0$EN = transCacheReqQ_enqP_lat_0$whas ;
// submodule transCacheReqQ_enqP_dummy2_1
assign transCacheReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign transCacheReqQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule transCacheReqQ_full_dummy2_0
assign transCacheReqQ_full_dummy2_0$D_IN = 1'd1 ;
assign transCacheReqQ_full_dummy2_0$EN =
CAN_FIRE_RL_doTranslationCacheResp ;
// submodule transCacheReqQ_full_dummy2_1
assign transCacheReqQ_full_dummy2_1$D_IN = 1'd1 ;
assign transCacheReqQ_full_dummy2_1$EN = transCacheReqQ_enqP_lat_0$whas ;
// submodule transCacheReqQ_full_dummy2_2
assign transCacheReqQ_full_dummy2_2$D_IN = 1'b0 ;
assign transCacheReqQ_full_dummy2_2$EN = 1'b0 ;
// remaining internal signals
assign IF_IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy_ETC___d1341 =
IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1329 ?
NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122 :
(!transCacheReqQ_full_dummy2_1$Q_OUT ||
!transCacheReqQ_full_dummy2_2$Q_OUT ||
CAN_FIRE_RL_doTranslationCacheResp ||
!transCacheReqQ_full_rl) &&
transCache$RDY_req ;
assign IF_IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_ETC___d1716 =
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 ?
{ SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510,
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689,
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691,
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 } :
{ SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1384,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1391,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1698,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1700,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1702,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1704,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1706,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1708,
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1710,
x__h122416 } ;
assign IF_IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_ETC___d1946 =
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ?
NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122 :
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] ?
IF_NOT_SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_ETC___d1944 :
NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122) ;
assign IF_IF_respForOtherReq_861_BIT_1_862_THEN_NOT_r_ETC___d1919 =
(IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1895 ||
pendWalkAddr_0 != newPTEAddr__h136649) ?
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1915 &&
pendWait_1_dummy2_0$Q_OUT &&
pendWait_1_dummy2_1$Q_OUT &&
pendWait_1_rl[2:1] == 2'd1 &&
pendWalkAddr_1_819_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1917 :
idx__h135713 ;
assign IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162 =
(IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133 &&
tlbMG_m_validVec_0 &&
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147) ?
!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133 :
!tlbMG_m_validVec_1 ||
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q5 ;
assign IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1239 =
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1187 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1211 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1236 ;
assign IF_NOT_SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_ETC___d1944 =
(!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]) ?
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1922 :
NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122 &&
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1942 ;
assign IF_NOT_pendWait_0_dummy2_0_read__770_771_OR_NO_ETC___d1967 =
i__h136071 ?
pendWait_1_dummy2_0$Q_OUT && pendWait_1_dummy2_1$Q_OUT &&
pendWait_1_rl[2:1] != 2'd0 &&
pendWait_1_rl[2:1] != 2'd1 &&
pendWait_1_rl_18_BIT_0_30_EQ_SEL_ARR_respLdQ_d_ETC___d1964 &&
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1915 :
idx__h135713 ;
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1749 =
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1741 &&
tlb4KB_m_repRam_bram$DOB[3:2] != value__h117443 &&
tlb4KB_m_repRam_bram$DOB[5:4] != value__h117443) ?
tlb4KB_m_repRam_bram$DOB[5:4] :
tlb4KB_m_repRam_bram$DOB[7:6] ;
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1750 =
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1741 &&
tlb4KB_m_repRam_bram$DOB[3:2] != value__h117443) ?
tlb4KB_m_repRam_bram$DOB[3:2] :
tlb4KB_m_repRam_bram$DOB[5:4] ;
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d282 =
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271 &&
tlb4KB_m_repRam_bram$DOB[3:2] != way__h36041 &&
tlb4KB_m_repRam_bram$DOB[5:4] != way__h36041) ?
tlb4KB_m_repRam_bram$DOB[5:4] :
tlb4KB_m_repRam_bram$DOB[7:6] ;
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d283 =
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271 &&
tlb4KB_m_repRam_bram$DOB[3:2] != way__h36041) ?
tlb4KB_m_repRam_bram$DOB[3:2] :
tlb4KB_m_repRam_bram$DOB[5:4] ;
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d286 =
{ IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d282,
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d283,
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271 ?
tlb4KB_m_repRam_bram$DOB[3:2] :
tlb4KB_m_repRam_bram$DOB[1:0],
way__h36041 } ;
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1093 =
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072) &&
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1075)) ?
2'd2 :
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072) ?
2'd1 :
2'd0) ;
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1326 =
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072) ?
tlb4KB_m_tlbRam_1_bram$DOB[80] &&
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1075 :
tlb4KB_m_tlbRam_0_bram$DOB[80] &&
tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072 ;
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1327 =
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072) &&
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1075)) ?
tlb4KB_m_tlbRam_2_bram$DOB[80] &&
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1084 :
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1326 ;
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 ?
tlb4KB_m_tlbRam_3_bram$DOB[80] &&
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088 :
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1327 ;
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d263 =
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
tlb4KB_m_pendReq_rl[79:53] ||
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) ?
tlb4KB_m_tlbRam_1_bram$DOB[80] &&
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d231 &&
tlb4KB_m_tlbRam_1_bram_b_read__27_BIT_6_33_EQ__ETC___d234 :
tlb4KB_m_tlbRam_0_bram$DOB[80] ;
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d264 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238 ?
tlb4KB_m_tlbRam_2_bram$DOB[80] &&
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d243 &&
tlb4KB_m_tlbRam_2_bram_b_read__39_BIT_6_45_EQ__ETC___d246 :
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d263 ;
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d265 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250 ?
tlb4KB_m_tlbRam_3_bram$DOB[80] &&
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d254 &&
tlb4KB_m_tlbRam_3_bram_b_read__51_BIT_6_55_EQ__ETC___d256 :
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d264 ;
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d269 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238 ?
2'd2 :
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
tlb4KB_m_pendReq_rl[79:53] ||
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) ?
2'd1 :
2'd0) ;
assign IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1329 =
(NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1079 ?
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 :
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1321) &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 ;
assign IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1345 =
(NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1079 ?
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 :
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
tlb4KB_m_tlbRam_0_bram$DOB[80] &&
tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072 ||
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175) &&
1'b1 &&
(IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112 ?
NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1342) ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1187 =
NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1174 ?
!tlbMG_m_validVec_2 ||
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 :
(!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133) &&
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1211 =
NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1198 ?
!tlbMG_m_validVec_3 ||
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q8 :
(!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133) &&
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1187 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1236 =
(NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1214 &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197 &&
(!tlbMG_m_validVec_3 ||
!IF_tlbMG_m_entryVec_3_201_BITS_1_TO_0_202_EQ_0_ETC___d1219)) ?
!tlbMG_m_validVec_4 ||
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q10 :
NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1214 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1262 =
((!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133) &&
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1239 &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1248) ?
!tlbMG_m_validVec_5 ||
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q12 :
(!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133) &&
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1239 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1342 =
NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1316 ?
NOT_tlbMG_m_updRepIdx_dummy2_1_read__50_317_OR_ETC___d1318 &&
NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122 :
IF_IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy_ETC___d1341 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1309 =
(!tlbMG_m_validVec_0 ||
!IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147) ?
tlbMG_m_validVec_1 &&
IF_tlbMG_m_entryVec_1_152_BITS_1_TO_0_153_EQ_0_ETC___d1170 :
tlbMG_m_validVec_0 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1310 =
((!tlbMG_m_validVec_0 ||
!IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147) &&
(!tlbMG_m_validVec_1 ||
!IF_tlbMG_m_entryVec_1_152_BITS_1_TO_0_153_EQ_0_ETC___d1170)) ?
tlbMG_m_validVec_2 &&
IF_tlbMG_m_entryVec_2_177_BITS_1_TO_0_178_EQ_0_ETC___d1194 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1309 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1311 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197 ?
tlbMG_m_validVec_3 &&
IF_tlbMG_m_entryVec_3_201_BITS_1_TO_0_202_EQ_0_ETC___d1219 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1310 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1312 =
(NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197 &&
(!tlbMG_m_validVec_3 ||
!IF_tlbMG_m_entryVec_3_201_BITS_1_TO_0_202_EQ_0_ETC___d1219)) ?
tlbMG_m_validVec_4 &&
IF_tlbMG_m_entryVec_4_226_BITS_1_TO_0_227_EQ_0_ETC___d1245 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1311 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1313 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1248 ?
tlbMG_m_validVec_5 &&
IF_tlbMG_m_entryVec_5_252_BITS_1_TO_0_253_EQ_0_ETC___d1272 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1312 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1314 =
(NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1248 &&
(!tlbMG_m_validVec_5 ||
!IF_tlbMG_m_entryVec_5_252_BITS_1_TO_0_253_EQ_0_ETC___d1272)) ?
tlbMG_m_validVec_6 &&
IF_tlbMG_m_entryVec_6_278_BITS_1_TO_0_279_EQ_0_ETC___d1287 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1313 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 ?
tlbMG_m_validVec_7 &&
IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1314 ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1502 =
((!tlbMG_m_validVec_0 ||
!IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147) &&
(!tlbMG_m_validVec_1 ||
!IF_tlbMG_m_entryVec_1_152_BITS_1_TO_0_153_EQ_0_ETC___d1170)) ?
3'd2 :
((!tlbMG_m_validVec_0 ||
!IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147) ?
3'd1 :
3'd0) ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1504 =
(NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197 &&
(!tlbMG_m_validVec_3 ||
!IF_tlbMG_m_entryVec_3_201_BITS_1_TO_0_202_EQ_0_ETC___d1219)) ?
3'd4 :
(NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197 ?
3'd3 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1502) ;
assign IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1506 =
(NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1248 &&
(!tlbMG_m_validVec_5 ||
!IF_tlbMG_m_entryVec_5_252_BITS_1_TO_0_253_EQ_0_ETC___d1272)) ?
3'd6 :
(NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1248 ?
3'd5 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1504) ;
assign IF_NOT_transCacheReqQ_data_0_768_769_OR_NOT_pe_ETC___d1822 =
(NOT_transCacheReqQ_data_0_768_769_OR_NOT_pendW_ETC___d1776 ||
!pendWalkAddr_0_786_EQ_0_CONCAT_IF_transCache_r_ETC___d1801) ?
!transCacheReqQ_data_0 && pendWait_1_dummy2_0$Q_OUT &&
pendWait_1_dummy2_1$Q_OUT &&
pendWait_1_rl[2:1] == 2'd1 &&
pendWalkAddr_1 == pteAddr__h133425 :
transCacheReqQ_data_0 ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 ?
!vm_info_I[46] :
!vm_info_D[46] ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 ?
vm_info_I[46] :
vm_info_D[46] ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 ?
!vm_info_I[46] :
!vm_info_D[46] ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2006 =
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
walkLevel__h136646 == 2'd0 ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2] ||
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 ?
vm_info_I[46] :
vm_info_D[46] ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029 =
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2] &&
walkLevel__h136646 == 2'd0 ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2056 =
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]) &&
walkLevel__h136646 == 2'd0 ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2194 =
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]) &&
walkLevel__h136646 != 2'd0 &&
NOT_tlbMG_m_entryVec_0_125_BITS_79_TO_53_146_E_ETC___d2089 &&
NOT_tlbMG_m_entryVec_1_152_BITS_79_TO_53_169_E_ETC___d2151 &&
tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_1__ETC___d2189 ;
assign IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2245 =
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]) &&
walkLevel__h136646 != 2'd0 &&
(!tlbMG_m_validVec_0 ||
NOT_tlbMG_m_entryVec_0_125_BITS_79_TO_53_146_E_ETC___d2089) &&
NOT_tlbMG_m_validVec_1_150_151_OR_NOT_tlbMG_m__ETC___d2240 ;
assign IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1922 =
(walkLevel__h136646 == 2'd0) ?
NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122 :
transCache$RDY_addEntry &&
(IF_IF_respForOtherReq_861_BIT_1_862_THEN_NOT_r_ETC___d1919 ||
!memReqQ_full) ;
assign IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1942 =
(walkLevel__h136646 == 2'd0) ?
tlb4KB_m_state &&
NOT_tlb4KB_m_pendReq_dummy2_1_read__42_08_OR_I_ETC___d943 &&
NOT_tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1_rea_ETC___d953 &&
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d1938 :
!CAN_FIRE_RL_doStartFlush &&
NOT_tlbMG_m_updRepIdx_dummy2_1_read__50_317_OR_ETC___d1318 ;
assign IF_memReqQ_deqReq_dummy2_2_read__97_AND_IF_mem_ETC___d705 =
_theResult_____2__h82166 == v__h81624 ;
assign IF_memReqQ_deqReq_lat_1_whas__68_THEN_memReqQ__ETC___d674 =
EN_toMem_memReq_deq || memReqQ_deqReq_rl ;
assign IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648 =
memReqQ_enqReq_lat_0$whas ?
memReqQ_enqReq_lat_0$wget[65] :
memReqQ_enqReq_rl[65] ;
assign IF_pendValid_0_dummy2_1_read__29_AND_IF_pendVa_ETC___d1020 =
(pendValid_0_dummy2_1$Q_OUT &&
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573) ?
!pendValid_1_dummy2_1$Q_OUT ||
(pendValid_1_lat_0$whas ? !1'd0 : !pendValid_1_rl) :
!pendValid_0_dummy2_1$Q_OUT ||
(pendValid_0_lat_0$whas ? !1'd0 : !pendValid_0_rl) ;
assign IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573 =
pendValid_0_lat_0$whas ? 1'd0 : pendValid_0_rl ;
assign IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580 =
pendValid_1_lat_0$whas ? 1'd0 : pendValid_1_rl ;
assign IF_perfReqQ_enqReq_lat_1_whas__32_THEN_perfReq_ETC___d841 =
EN_perf_req ?
perfReqQ_enqReq_lat_0$wget[4] :
perfReqQ_enqReq_rl[4] ;
assign IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1894 =
respForOtherReq[1] ? !respForOtherReq[0] : !def__h135941 ;
assign IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1895 =
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1894 ||
!pendWait_0_dummy2_0$Q_OUT ||
!pendWait_0_dummy2_1$Q_OUT ||
pendWait_0_rl[2:1] != 2'd1 ;
assign IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1915 =
respForOtherReq[1] ?
!respForOtherReq[0] :
SEL_ARR_NOT_respLdQ_data_0_864_BIT_0_865_911_N_ETC___d1914 ;
assign IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d2043 =
(IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1895 ||
pendWalkAddr_0 != newPTEAddr__h136649) &&
(IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d1977 ||
!pendWait_1_dummy2_0$Q_OUT ||
!pendWait_1_dummy2_1$Q_OUT ||
pendWait_1_rl[2:1] != 2'd1 ||
!pendWalkAddr_1_819_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1917) ;
assign IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d1977 =
respForOtherReq[1] ?
respForOtherReq[0] :
!SEL_ARR_NOT_respLdQ_data_0_864_BIT_0_865_911_N_ETC___d1914 ;
assign IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d2262 =
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]) ;
assign IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d2263 =
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]) ;
assign IF_respLdQ_deqReq_dummy2_2_read__94_AND_IF_res_ETC___d802 =
_theResult_____2__h89736 == v__h89194 ;
assign IF_respLdQ_deqReq_lat_1_whas__65_THEN_respLdQ__ETC___d771 =
respLdQ_deqReq_lat_0$whas || respLdQ_deqReq_rl ;
assign IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745 =
EN_toMem_respLd_enq ?
respLdQ_enqReq_lat_0$wget[65] :
respLdQ_enqReq_rl[65] ;
assign IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471 =
EN_toChildren_rqFromC_put ?
toChildren_rqFromC_put[29] :
rqFromCQ_data_0_rl[29] ;
assign IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481 =
EN_toChildren_rqFromC_put ?
toChildren_rqFromC_put[28:27] :
rqFromCQ_data_0_rl[28:27] ;
assign IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d487 =
EN_toChildren_rqFromC_put ?
toChildren_rqFromC_put[26:0] :
rqFromCQ_data_0_rl[26:0] ;
assign IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d518 =
rsToCQ_data_0_lat_0$whas ?
rsToCQ_data_0_lat_0$wget[83] :
rsToCQ_data_0_rl[83] ;
assign IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d528 =
rsToCQ_data_0_lat_0$whas ?
rsToCQ_data_0_lat_0$wget[82:81] :
rsToCQ_data_0_rl[82:81] ;
assign IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d534 =
rsToCQ_data_0_lat_0$whas ?
rsToCQ_data_0_lat_0$wget[80] :
rsToCQ_data_0_rl[80] ;
assign IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d544 =
rsToCQ_data_0_lat_0$whas ?
rsToCQ_data_0_lat_0$wget[79:0] :
rsToCQ_data_0_rl[79:0] ;
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125 =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
!tlb4KB_m_pendReq_lat_1$wget[80] :
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
!tlb4KB_m_pendReq_rl[80] ;
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110 =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
tlb4KB_m_pendReq_lat_1$wget[81] :
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
tlb4KB_m_pendReq_rl[81] ;
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120 =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
tlb4KB_m_pendReq_lat_1$wget[80] :
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
tlb4KB_m_pendReq_rl[80] ;
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130 =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
tlb4KB_m_pendReq_lat_1$wget[26:0] :
(MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ?
27'b010101010101010101010101010 :
tlb4KB_m_pendReq_rl[26:0]) ;
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136 =
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
tlb4KB_m_pendReq_lat_1$wget[79:0] :
(MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ?
80'hAAAAAAAAAAAAAAAAAAAA :
tlb4KB_m_pendReq_rl[79:0]) ;
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138 =
{ IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120,
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125 ?
{ 53'h0AAAAAAAAAAAAA,
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130 } :
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136 } ;
assign IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147 =
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_SEL_ARR__ETC__q3 ==
tlbMG_m_entryVec_0[79:53] ;
assign IF_tlbMG_m_entryVec_1_152_BITS_1_TO_0_153_EQ_0_ETC___d1170 =
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_SEL_ARR__ETC__q4 ==
tlbMG_m_entryVec_1[79:53] ;
assign IF_tlbMG_m_entryVec_2_177_BITS_1_TO_0_178_EQ_0_ETC___d1194 =
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_SEL_ARR__ETC__q7 ==
tlbMG_m_entryVec_2[79:53] ;
assign IF_tlbMG_m_entryVec_3_201_BITS_1_TO_0_202_EQ_0_ETC___d1219 =
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_SEL_ARR__ETC__q9 ==
tlbMG_m_entryVec_3[79:53] ;
assign IF_tlbMG_m_entryVec_4_226_BITS_1_TO_0_227_EQ_0_ETC___d1245 =
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_SEL_ARR__ETC__q11 ==
tlbMG_m_entryVec_4[79:53] ;
assign IF_tlbMG_m_entryVec_5_252_BITS_1_TO_0_253_EQ_0_ETC___d1272 =
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_SEL_ARR__ETC__q13 ==
tlbMG_m_entryVec_5[79:53] ;
assign IF_tlbMG_m_entryVec_6_278_BITS_1_TO_0_279_EQ_0_ETC___d1287 =
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_SEL_ARR__ETC__q14 ==
tlbMG_m_entryVec_6[79:53] ;
assign IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301 =
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_SEL_ARR__ETC__q15 ==
tlbMG_m_entryVec_7[79:53] ;
assign IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161 =
tlbMG_m_lruBit_dummy2_1$Q_OUT ?
~IF_tlbMG_m_lruBit_lat_0_whas__18_THEN_tlbMG_m__ETC___d321 :
8'd255 ;
assign IF_tlbMG_m_lruBit_lat_0_whas__18_THEN_tlbMG_m__ETC___d321 =
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
upd__h144732 :
tlbMG_m_lruBit_rl ;
assign IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d332 =
tlbMG_m_updRepIdx_lat_1$whas ?
tlbMG_m_updRepIdx_lat_1$wget[3] :
!MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 &&
tlbMG_m_updRepIdx_rl[3] ;
assign IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d342 =
tlbMG_m_updRepIdx_lat_1$whas ?
tlbMG_m_updRepIdx_lat_1$wget[2:0] :
(MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
3'b010 :
tlbMG_m_updRepIdx_rl[2:0]) ;
assign IF_tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_ETC___d2207 =
(tlbMG_m_validVec_0 && tlbMG_m_validVec_1) ?
(tlbMG_m_validVec_2 ? 3'd3 : 3'd2) :
(tlbMG_m_validVec_0 ? 3'd1 : 3'd0) ;
assign IF_tlbMG_m_validVec_4_224_AND_tlbMG_m_validVec_ETC___d2204 =
(tlbMG_m_validVec_4 && tlbMG_m_validVec_5) ?
(tlbMG_m_validVec_6 ? 3'd7 : 3'd6) :
(tlbMG_m_validVec_4 ? 3'd5 : 3'd4) ;
assign IF_transCacheReqQ_data_0_768_AND_pendWait_0_du_ETC___d1812 =
(transCacheReqQ_data_0 && pendWait_0_dummy2_0$Q_OUT &&
pendWait_0_dummy2_1$Q_OUT &&
pendWait_0_rl[2:1] == 2'd1 &&
pendWalkAddr_0_786_EQ_0_CONCAT_IF_transCache_r_ETC___d1801) ?
IF_transCache_RDY_resp__756_AND_transCache_res_ETC___d1781 :
transCacheReqQ_data_0 || !pendWait_1_dummy2_0$Q_OUT ||
!pendWait_1_dummy2_1$Q_OUT ||
pendWait_1_rl[2:1] != 2'd1 ||
IF_transCache_RDY_resp__756_AND_transCache_res_ETC___d1781 ;
assign IF_transCache_RDY_resp__756_AND_transCache_res_ETC___d1781 =
(transCache$RDY_resp &&
transCache_resp__777_BITS_45_TO_44_778_ULT_2___d1779) ?
transCache$RDY_resp :
NOT_transCacheReqQ_empty_dummy2_0_read__758_75_ETC___d1767 ;
assign NOT_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel__ETC___d2066 =
walkLevel__h136646 != 2'd0 &&
masked_ppn__h137253 !=
CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q16 ;
assign NOT_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel__ETC___d2078 =
walkLevel__h136646 != 2'd0 &&
masked_vpn__h137252 !=
CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q17 ;
assign NOT_flushDoneQ_enqReq_dummy2_2_read__36_51_OR__ETC___d461 =
(!flushDoneQ_enqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_doWaitFlush && !flushDoneQ_enqReq_rl) &&
(flushDoneQ_deqReq_dummy2_2$Q_OUT &&
(EN_toChildren_flushDone_get || flushDoneQ_deqReq_rl) ||
flushDoneQ_empty) ;
assign NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 =
!memReqQ_clearReq_dummy2_1$Q_OUT || !memReqQ_clearReq_rl ;
assign NOT_memReqQ_enqReq_dummy2_2_read__89_19_OR_IF__ETC___d723 =
(!memReqQ_enqReq_dummy2_2$Q_OUT ||
(memReqQ_enqReq_lat_0$whas ?
!memReqQ_enqReq_lat_0$wget[65] :
!memReqQ_enqReq_rl[65])) &&
(memReqQ_deqReq_dummy2_2$Q_OUT &&
IF_memReqQ_deqReq_lat_1_whas__68_THEN_memReqQ__ETC___d674 ||
memReqQ_empty) ;
assign NOT_perfReqQ_clearReq_dummy2_1_read__76_77_OR__ETC___d881 =
!perfReqQ_clearReq_dummy2_1$Q_OUT || !perfReqQ_clearReq_rl ;
assign NOT_perfReqQ_enqReq_dummy2_2_read__82_97_OR_IF_ETC___d902 =
(!perfReqQ_enqReq_dummy2_2$Q_OUT ||
(EN_perf_req ?
!perfReqQ_enqReq_lat_0$wget[4] :
!perfReqQ_enqReq_rl[4])) &&
(perfReqQ_deqReq_dummy2_2$Q_OUT &&
(EN_perf_resp || perfReqQ_deqReq_rl) ||
perfReqQ_empty) ;
assign NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 =
!respLdQ_clearReq_dummy2_1$Q_OUT || !respLdQ_clearReq_rl ;
assign NOT_respLdQ_enqReq_dummy2_2_read__86_16_OR_IF__ETC___d820 =
(!respLdQ_enqReq_dummy2_2$Q_OUT ||
(EN_toMem_respLd_enq ?
!respLdQ_enqReq_lat_0$wget[65] :
!respLdQ_enqReq_rl[65])) &&
(respLdQ_deqReq_dummy2_2$Q_OUT &&
IF_respLdQ_deqReq_lat_1_whas__65_THEN_respLdQ__ETC___d771 ||
respLdQ_empty) ;
assign NOT_rqFromCQ_data_0_dummy2_1_read__003_040_OR__ETC___d1041 =
!rqFromCQ_data_0_dummy2_1$Q_OUT ||
(EN_toChildren_rqFromC_put ?
!toChildren_rqFromC_put[29] :
!rqFromCQ_data_0_rl[29]) ;
assign NOT_rqFromCQ_empty_dummy2_1_read__19_20_OR_NOT_ETC___d927 =
!rqFromCQ_empty_dummy2_1$Q_OUT ||
!rqFromCQ_empty_dummy2_2$Q_OUT ||
EN_toChildren_rqFromC_put ||
!rqFromCQ_empty_rl ;
assign NOT_rsToCQ_full_dummy2_0_read__113_114_OR_NOT__ETC___d1122 =
!rsToCQ_full_dummy2_0$Q_OUT || !rsToCQ_full_dummy2_1$Q_OUT ||
!rsToCQ_full_dummy2_2$Q_OUT ||
!rsToCQ_full_rl ;
assign NOT_tlb4KB_m_pendReq_dummy2_1_read__42_08_OR_I_ETC___d943 =
!tlb4KB_m_pendReq_dummy2_1$Q_OUT ||
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
!tlb4KB_m_pendReq_rl[81] ;
assign NOT_tlb4KB_m_repRam_rdReqQ_empty_dummy2_0_read_ETC___d205 =
!tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$Q_OUT ||
!tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$Q_OUT ||
!tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$Q_OUT ||
!tlb4KB_m_repRam_rdReqQ_empty_rl ;
assign NOT_tlb4KB_m_repRam_rdReqQ_full_dummy2_1_read__ETC___d989 =
!tlb4KB_m_repRam_rdReqQ_full_dummy2_1$Q_OUT ||
!tlb4KB_m_repRam_rdReqQ_full_dummy2_2$Q_OUT ||
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
!tlb4KB_m_repRam_rdReqQ_full_rl ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 =
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072) &&
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1075) &&
(!tlb4KB_m_tlbRam_2_bram$DOB[80] ||
!tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1084) ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1405 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088) ||
!SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1402 ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1418 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088) ||
!SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1415 ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1427 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088) ||
!SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1424 ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1440 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088) ||
!SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1437 ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1453 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088) ||
!SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1450 ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1466 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088) ||
!SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1463 ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1479 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088) ||
!SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1476 ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238 =
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
tlb4KB_m_pendReq_rl[79:53] ||
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) &&
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d231 ||
!tlb4KB_m_tlbRam_1_bram_b_read__27_BIT_6_33_EQ__ETC___d234) ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238 &&
(!tlb4KB_m_tlbRam_2_bram$DOB[80] ||
!tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d243 ||
!tlb4KB_m_tlbRam_2_bram_b_read__39_BIT_6_45_EQ__ETC___d246) ;
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d254 ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BIT_6_55_EQ__ETC___d256) ;
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1079 =
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175 &&
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072) &&
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1075) ;
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1321 =
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
(tlb4KB_m_tlbRam_0_bram$DOB[80] &&
tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072 ||
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175) ;
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1351 =
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175 &&
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 &&
NOT_tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0_re_ETC___d195 &&
NOT_tlb4KB_m_repRam_rdReqQ_empty_dummy2_0_read_ETC___d205 &&
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070 &&
IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1345 ;
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 =
!tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$Q_OUT ||
!tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$Q_OUT ||
!tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$Q_OUT ||
!tlb4KB_m_tlbRam_0_rdReqQ_empty_rl ;
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1_rea_ETC___d953 =
!tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$Q_OUT ||
!tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$Q_OUT ||
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
!tlb4KB_m_tlbRam_0_rdReqQ_full_rl ;
assign NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175 =
!tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$Q_OUT ||
!tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$Q_OUT ||
!tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$Q_OUT ||
!tlb4KB_m_tlbRam_1_rdReqQ_empty_rl ;
assign NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d1938 =
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d962 &&
NOT_tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1_rea_ETC___d971 &&
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d980 &&
NOT_tlb4KB_m_repRam_rdReqQ_full_dummy2_1_read__ETC___d989 &&
(!tlb4KB_m_pendIndex$wget[8] ||
tlb4KB_m_pendIndex$wget[7:0] != masked_vpn__h137252[7:0]) ;
assign NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d962 =
!tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$Q_OUT ||
!tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$Q_OUT ||
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
!tlb4KB_m_tlbRam_1_rdReqQ_full_rl ;
assign NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 =
!tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$Q_OUT ||
!tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$Q_OUT ||
!tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$Q_OUT ||
!tlb4KB_m_tlbRam_2_rdReqQ_empty_rl ;
assign NOT_tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1_rea_ETC___d971 =
!tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$Q_OUT ||
!tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$Q_OUT ||
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
!tlb4KB_m_tlbRam_2_rdReqQ_full_rl ;
assign NOT_tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0_re_ETC___d195 =
!tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$Q_OUT ||
!tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$Q_OUT ||
!tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$Q_OUT ||
!tlb4KB_m_tlbRam_3_rdReqQ_empty_rl ;
assign NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d1024 =
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d980 &&
NOT_tlb4KB_m_repRam_rdReqQ_full_dummy2_1_read__ETC___d989 &&
(!tlbReqQ_full_dummy2_1$Q_OUT || !tlbReqQ_full_dummy2_2$Q_OUT ||
CAN_FIRE_RL_doTlbResp ||
!tlbReqQ_full_rl) &&
(!tlb4KB_m_pendIndex$wget[8] ||
tlb4KB_m_pendIndex$wget[7:0] != vpn__h104314[7:0]) &&
IF_pendValid_0_dummy2_1_read__29_AND_IF_pendVa_ETC___d1020 ;
assign NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d980 =
!tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$Q_OUT ||
!tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$Q_OUT ||
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
!tlb4KB_m_tlbRam_3_rdReqQ_full_rl ;
assign NOT_tlbMG_m_entryVec_0_125_BITS_79_TO_53_146_E_ETC___d2089 =
tlbMG_m_entryVec_0[79:53] != masked_vpn__h137252 ||
tlbMG_m_entryVec_0[1:0] != walkLevel__h136646 ||
tlbMG_m_entryVec_0[6] !=
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5] ;
assign NOT_tlbMG_m_entryVec_1_152_BITS_79_TO_53_169_E_ETC___d2097 =
tlbMG_m_entryVec_1[79:53] != masked_vpn__h137252 ||
tlbMG_m_entryVec_1[1:0] != walkLevel__h136646 ||
tlbMG_m_entryVec_1[6] !=
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5] ;
assign NOT_tlbMG_m_entryVec_1_152_BITS_79_TO_53_169_E_ETC___d2151 =
NOT_tlbMG_m_entryVec_1_152_BITS_79_TO_53_169_E_ETC___d2097 &&
NOT_tlbMG_m_entryVec_2_177_BITS_79_TO_53_193_E_ETC___d2105 &&
NOT_tlbMG_m_entryVec_3_201_BITS_79_TO_53_218_E_ETC___d2113 &&
NOT_tlbMG_m_entryVec_4_226_BITS_79_TO_53_244_E_ETC___d2121 &&
NOT_tlbMG_m_entryVec_5_252_BITS_79_TO_53_271_E_ETC___d2129 &&
NOT_tlbMG_m_entryVec_6_278_BITS_79_TO_53_286_E_ETC___d2137 &&
NOT_tlbMG_m_entryVec_7_292_BITS_79_TO_53_300_E_ETC___d2145 ;
assign NOT_tlbMG_m_entryVec_2_177_BITS_79_TO_53_193_E_ETC___d2105 =
tlbMG_m_entryVec_2[79:53] != masked_vpn__h137252 ||
tlbMG_m_entryVec_2[1:0] != walkLevel__h136646 ||
tlbMG_m_entryVec_2[6] !=
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5] ;
assign NOT_tlbMG_m_entryVec_3_201_BITS_79_TO_53_218_E_ETC___d2113 =
tlbMG_m_entryVec_3[79:53] != masked_vpn__h137252 ||
tlbMG_m_entryVec_3[1:0] != walkLevel__h136646 ||
tlbMG_m_entryVec_3[6] !=
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5] ;
assign NOT_tlbMG_m_entryVec_4_226_BITS_79_TO_53_244_E_ETC___d2121 =
tlbMG_m_entryVec_4[79:53] != masked_vpn__h137252 ||
tlbMG_m_entryVec_4[1:0] != walkLevel__h136646 ||
tlbMG_m_entryVec_4[6] !=
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5] ;
assign NOT_tlbMG_m_entryVec_5_252_BITS_79_TO_53_271_E_ETC___d2129 =
tlbMG_m_entryVec_5[79:53] != masked_vpn__h137252 ||
tlbMG_m_entryVec_5[1:0] != walkLevel__h136646 ||
tlbMG_m_entryVec_5[6] !=
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5] ;
assign NOT_tlbMG_m_entryVec_6_278_BITS_79_TO_53_286_E_ETC___d2137 =
tlbMG_m_entryVec_6[79:53] != masked_vpn__h137252 ||
tlbMG_m_entryVec_6[1:0] != walkLevel__h136646 ||
tlbMG_m_entryVec_6[6] !=
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5] ;
assign NOT_tlbMG_m_entryVec_7_292_BITS_79_TO_53_300_E_ETC___d2145 =
tlbMG_m_entryVec_7[79:53] != masked_vpn__h137252 ||
tlbMG_m_entryVec_7[1:0] != walkLevel__h136646 ||
tlbMG_m_entryVec_7[6] !=
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5] ;
assign NOT_tlbMG_m_updRepIdx_dummy2_1_read__50_317_OR_ETC___d1318 =
!tlbMG_m_updRepIdx_dummy2_1$Q_OUT ||
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ||
!tlbMG_m_updRepIdx_rl[3] ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1174 =
(!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133) &&
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162 &&
(!tlbMG_m_validVec_0 ||
!IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147) &&
(!tlbMG_m_validVec_1 ||
!IF_tlbMG_m_entryVec_1_152_BITS_1_TO_0_153_EQ_0_ETC___d1170) ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1198 =
(!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133) &&
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1187 &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1214 =
(!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133) &&
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1187 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1211 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG_m_e_ETC___d1316 =
(!tlbMG_m_validVec_0 ||
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133) &&
IF_IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_E_ETC___d1162 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1187 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1211 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1236 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_IF_tlbMG__ETC___d1262 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197 =
(!tlbMG_m_validVec_0 ||
!IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147) &&
(!tlbMG_m_validVec_1 ||
!IF_tlbMG_m_entryVec_1_152_BITS_1_TO_0_153_EQ_0_ETC___d1170) &&
(!tlbMG_m_validVec_2 ||
!IF_tlbMG_m_entryVec_2_177_BITS_1_TO_0_178_EQ_0_ETC___d1194) ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1248 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1197 &&
(!tlbMG_m_validVec_3 ||
!IF_tlbMG_m_entryVec_3_201_BITS_1_TO_0_202_EQ_0_ETC___d1219) &&
(!tlbMG_m_validVec_4 ||
!IF_tlbMG_m_entryVec_4_226_BITS_1_TO_0_227_EQ_0_ETC___d1245) ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1248 &&
(!tlbMG_m_validVec_5 ||
!IF_tlbMG_m_entryVec_5_252_BITS_1_TO_0_253_EQ_0_ETC___d1272) &&
(!tlbMG_m_validVec_6 ||
!IF_tlbMG_m_entryVec_6_278_BITS_1_TO_0_279_EQ_0_ETC___d1287) ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1543 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) ||
!SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1564 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) ||
!SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1585 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) ||
!SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1606 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) ||
!SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1627 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) ||
!SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1648 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) ||
!SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1669 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) ||
!SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1735 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 &&
x__h122416 != 2'd0 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1737 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1754 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301) &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088) ;
assign NOT_tlbMG_m_validVec_0_123_124_OR_NOT_tlbMG_m__ETC___d2201 =
!tlbMG_m_validVec_0 || !tlbMG_m_validVec_1 ||
!tlbMG_m_validVec_2 ||
!tlbMG_m_validVec_3 ||
!tlbMG_m_validVec_4 ||
!tlbMG_m_validVec_5 ||
!tlbMG_m_validVec_6 ||
!tlbMG_m_validVec_7 ;
assign NOT_tlbMG_m_validVec_1_150_151_OR_NOT_tlbMG_m__ETC___d2240 =
(!tlbMG_m_validVec_1 ||
NOT_tlbMG_m_entryVec_1_152_BITS_79_TO_53_169_E_ETC___d2097) &&
(!tlbMG_m_validVec_2 ||
NOT_tlbMG_m_entryVec_2_177_BITS_79_TO_53_193_E_ETC___d2105) &&
NOT_tlbMG_m_validVec_3_199_200_OR_NOT_tlbMG_m__ETC___d2238 ;
assign NOT_tlbMG_m_validVec_3_199_200_OR_NOT_tlbMG_m__ETC___d2238 =
(!tlbMG_m_validVec_3 ||
NOT_tlbMG_m_entryVec_3_201_BITS_79_TO_53_218_E_ETC___d2113) &&
(!tlbMG_m_validVec_4 ||
NOT_tlbMG_m_entryVec_4_226_BITS_79_TO_53_244_E_ETC___d2121) &&
NOT_tlbMG_m_validVec_5_250_251_OR_NOT_tlbMG_m__ETC___d2236 ;
assign NOT_tlbMG_m_validVec_5_250_251_OR_NOT_tlbMG_m__ETC___d2236 =
(!tlbMG_m_validVec_5 ||
NOT_tlbMG_m_entryVec_5_252_BITS_79_TO_53_271_E_ETC___d2129) &&
(!tlbMG_m_validVec_6 ||
NOT_tlbMG_m_entryVec_6_278_BITS_79_TO_53_286_E_ETC___d2137) &&
(!tlbMG_m_validVec_7 ||
NOT_tlbMG_m_entryVec_7_292_BITS_79_TO_53_300_E_ETC___d2145) ;
assign NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070 =
!tlbReqQ_empty_dummy2_0$Q_OUT || !tlbReqQ_empty_dummy2_1$Q_OUT ||
!tlbReqQ_empty_dummy2_2$Q_OUT ||
!tlbReqQ_empty_rl ;
assign NOT_transCacheReqQ_data_0_768_769_OR_NOT_pendW_ETC___d1776 =
!transCacheReqQ_data_0 || !pendWait_0_dummy2_0$Q_OUT ||
!pendWait_0_dummy2_1$Q_OUT ||
pendWait_0_rl[2:1] != 2'd1 ;
assign NOT_transCacheReqQ_empty_dummy2_0_read__758_75_ETC___d1767 =
!transCacheReqQ_empty_dummy2_0$Q_OUT ||
!transCacheReqQ_empty_dummy2_1$Q_OUT ||
!transCacheReqQ_empty_dummy2_2$Q_OUT ||
!transCacheReqQ_empty_rl ;
assign SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2035 =
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2] &&
walkLevel__h136646 != 2'd0 &&
IF_IF_respForOtherReq_861_BIT_1_862_THEN_NOT_r_ETC___d1919 ;
assign SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2046 =
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2] &&
walkLevel__h136646 != 2'd0 &&
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d2043 ;
assign _dfoo13 =
tlbReqQ_data_0 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112 ||
tlbReqQ_data_0 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
(IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 ||
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1737) ;
assign _dfoo41 =
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2046 ||
IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d2263 ||
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] ;
assign _dfoo45 =
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2046 ||
IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d2262 ||
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] ;
assign _dfoo52 =
(idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2035) ?
{ 2'd2,
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1895 ||
pendWalkAddr_0 != newPTEAddr__h136649 } :
((idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2046) ?
3'd2 :
3'd0) ;
assign _dfoo56 =
(idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2035) ?
{ 2'd2,
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1895 ||
pendWalkAddr_0 != newPTEAddr__h136649 } :
((idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2046) ?
3'd2 :
3'd0) ;
assign _dfoo57 =
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029 ||
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2035 ||
_dfoo41 ;
assign _dfoo59 =
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029 ||
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2035 ||
_dfoo41 ;
assign _dfoo61 =
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029 ||
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2035 ||
_dfoo45 ;
assign _dfoo63 =
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029 ||
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d2035 ||
_dfoo45 ;
assign _dfoo65 =
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029 ||
IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d2263 ||
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] ;
assign _dfoo69 =
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2029 ||
IF_respForOtherReq_861_BIT_1_862_THEN_respForO_ETC___d2262 ||
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] ;
assign _dfoo73 =
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
_dfoo57 ;
assign _dfoo75 =
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
_dfoo59 ;
assign _dfoo77 =
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
_dfoo61 ;
assign _dfoo79 =
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
_dfoo63 ;
assign _dfoo81 =
idx__h135713 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
_dfoo65 ;
assign _dfoo85 =
idx__h135713 == 1'd0 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872 ||
_dfoo69 ;
assign _dfoo9 =
tlbReqQ_data_0 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112 ||
tlbReqQ_data_0 == 1'd1 &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
(IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 ||
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1737) ;
assign _theResult_____2__h82166 =
(memReqQ_deqReq_dummy2_2$Q_OUT &&
IF_memReqQ_deqReq_lat_1_whas__68_THEN_memReqQ__ETC___d674) ?
next_deqP___1__h82485 :
memReqQ_deqP ;
assign _theResult_____2__h89736 =
(respLdQ_deqReq_dummy2_2$Q_OUT &&
IF_respLdQ_deqReq_lat_1_whas__65_THEN_respLdQ__ETC___d771) ?
next_deqP___1__h90055 :
respLdQ_deqP ;
assign addIdx__h145990 =
(!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[0] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[1] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[2] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[3]) ?
((!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[4] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[5]) ?
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[6] ?
3'd6 :
3'd7) :
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[4] ?
3'd4 :
3'd5)) :
((!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[0] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[1]) ?
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[2] ?
3'd2 :
3'd3) :
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[0] ?
3'd0 :
3'd1)) ;
assign addIdx__h147257 =
(tlbMG_m_validVec_0 && tlbMG_m_validVec_1 &&
tlbMG_m_validVec_2 &&
tlbMG_m_validVec_3) ?
IF_tlbMG_m_validVec_4_224_AND_tlbMG_m_validVec_ETC___d2204 :
IF_tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_ETC___d2207 ;
assign baseAddr__h133424 = { 8'd0, x__h133697 } ;
assign basePpn__h133693 =
transCache_resp__777_BITS_45_TO_44_778_ULT_2___d1779 ?
transCache$resp[43:0] :
rootPPN__h133423 ;
assign flushDoneQ_enqReq_dummy2_2_read__36_AND_IF_flu_ETC___d448 =
flushDoneQ_enqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_doWaitFlush || flushDoneQ_enqReq_rl) ||
(!flushDoneQ_deqReq_dummy2_2$Q_OUT ||
!EN_toChildren_flushDone_get && !flushDoneQ_deqReq_rl) &&
flushDoneQ_full ;
assign i__h136071 =
!pendWait_0_dummy2_0$Q_OUT || !pendWait_0_dummy2_1$Q_OUT ||
pendWait_0_rl[2:1] == 2'd0 ||
pendWait_0_rl[2:1] == 2'd1 ||
pendWait_0_rl[0] != def__h135941 ||
IF_respForOtherReq_861_BIT_1_862_THEN_NOT_resp_ETC___d1894 ;
assign idx__h119391 = value__h119411 ;
assign idx__h135713 =
respForOtherReq[1] ? respForOtherReq[0] : def__h135941 ;
assign memReqQ_enqReq_dummy2_2_read__89_AND_IF_memReq_ETC___d715 =
memReqQ_enqReq_dummy2_2$Q_OUT &&
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648 ||
(!memReqQ_deqReq_dummy2_2$Q_OUT ||
!EN_toMem_memReq_deq && !memReqQ_deqReq_rl) &&
memReqQ_full ;
assign newPTBase__h136648 = { 8'd0, x__h136737 } ;
assign newPTEAddr__h136649 =
newPTBase__h136648 + { 52'd0, x__h136754, 3'd0 } ;
assign newWalkLevel__h136647 = walkLevel__h136646 - 2'd1 ;
assign next_deqP___1__h82485 = memReqQ_deqP + 1'd1 ;
assign next_deqP___1__h90055 = respLdQ_deqP + 1'd1 ;
assign pendValid_0_dummy2_0_read__28_AND_pendValid_0__ETC___d936 =
pendValid_0_dummy2_0$Q_OUT && pendValid_0_dummy2_1$Q_OUT &&
pendValid_0_rl ||
pendValid_1_dummy2_0$Q_OUT && pendValid_1_dummy2_1$Q_OUT &&
pendValid_1_rl ;
assign pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051 =
pendWait_0_dummy2_1$Q_OUT &&
(pendWait_0_lat_0$whas ?
pendWait_0_lat_0$wget[2:1] != 2'd0 :
pendWait_0_rl[2:1] != 2'd0) ;
assign pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056 =
pendWait_1_dummy2_1$Q_OUT &&
(pendWait_1_lat_0$whas ?
pendWait_1_lat_0$wget[2:1] != 2'd0 :
pendWait_1_rl[2:1] != 2'd0) ;
assign pendWait_1_rl_18_BIT_0_30_EQ_SEL_ARR_respLdQ_d_ETC___d1964 =
pendWait_1_rl[0] == def__h135941 ;
assign pendWalkAddr_0_786_EQ_0_CONCAT_IF_transCache_r_ETC___d1801 =
pendWalkAddr_0 == pteAddr__h133425 ;
assign pendWalkAddr_1_819_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1917 =
pendWalkAddr_1 == newPTEAddr__h136649 ;
assign perfReqQ_enqReq_dummy2_2_read__82_AND_IF_perfR_ETC___d894 =
perfReqQ_enqReq_dummy2_2$Q_OUT &&
IF_perfReqQ_enqReq_lat_1_whas__32_THEN_perfReq_ETC___d841 ||
(!perfReqQ_deqReq_dummy2_2$Q_OUT ||
!EN_perf_resp && !perfReqQ_deqReq_rl) &&
perfReqQ_full ;
assign pteAddr__h133425 = baseAddr__h133424 + { 52'd0, x__h133729, 3'd0 } ;
assign respLdQ_enqReq_dummy2_2_read__86_AND_IF_respLd_ETC___d812 =
respLdQ_enqReq_dummy2_2$Q_OUT &&
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745 ||
(!respLdQ_deqReq_dummy2_2$Q_OUT ||
!respLdQ_deqReq_lat_0$whas && !respLdQ_deqReq_rl) &&
respLdQ_full ;
assign rootPPN__h133423 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 ?
vm_info_I[43:0] :
vm_info_D[43:0] ;
assign tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1741 =
tlb4KB_m_repRam_bram$DOB[1:0] == value__h117443 ;
assign tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271 =
tlb4KB_m_repRam_bram$DOB[1:0] == way__h36041 ;
assign tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287 =
tlb4KB_m_repRam_bram$DOB[1:0] == tlb4KB_m_repRam_bram$DOB[7:6] ;
assign tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072 =
tlb4KB_m_tlbRam_0_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
assign tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_15_AN_ETC___d1380 =
tlb4KB_m_tlbRam_0_bram$DOB[80] &&
tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1072 ||
tlb4KB_m_tlbRam_1_bram$DOB[80] &&
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1075 ||
tlb4KB_m_tlbRam_2_bram$DOB[80] &&
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1084 ;
assign tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1075 =
tlb4KB_m_tlbRam_1_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
assign tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d231 =
tlb4KB_m_tlbRam_1_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
assign tlb4KB_m_tlbRam_1_bram_b_read__27_BIT_6_33_EQ__ETC___d234 =
tlb4KB_m_tlbRam_1_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
assign tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1084 =
tlb4KB_m_tlbRam_2_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
assign tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d243 =
tlb4KB_m_tlbRam_2_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
assign tlb4KB_m_tlbRam_2_bram_b_read__39_BIT_6_45_EQ__ETC___d246 =
tlb4KB_m_tlbRam_2_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
assign tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088 =
tlb4KB_m_tlbRam_3_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
assign tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d254 =
tlb4KB_m_tlbRam_3_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
assign tlb4KB_m_tlbRam_3_bram_b_read__51_BIT_6_55_EQ__ETC___d256 =
tlb4KB_m_tlbRam_3_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
assign tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1495 =
tlbMG_m_validVec_0 &&
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1147 ||
tlbMG_m_validVec_1 &&
IF_tlbMG_m_entryVec_1_152_BITS_1_TO_0_153_EQ_0_ETC___d1170 ||
tlbMG_m_validVec_2 &&
IF_tlbMG_m_entryVec_2_177_BITS_1_TO_0_178_EQ_0_ETC___d1194 ;
assign tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1497 =
tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1495 ||
tlbMG_m_validVec_3 &&
IF_tlbMG_m_entryVec_3_201_BITS_1_TO_0_202_EQ_0_ETC___d1219 ||
tlbMG_m_validVec_4 &&
IF_tlbMG_m_entryVec_4_226_BITS_1_TO_0_227_EQ_0_ETC___d1245 ;
assign tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1499 =
tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1497 ||
tlbMG_m_validVec_5 &&
IF_tlbMG_m_entryVec_5_252_BITS_1_TO_0_253_EQ_0_ETC___d1272 ||
tlbMG_m_validVec_6 &&
IF_tlbMG_m_entryVec_6_278_BITS_1_TO_0_279_EQ_0_ETC___d1287 ;
assign tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_1__ETC___d2159 =
tlbMG_m_validVec_0 && tlbMG_m_validVec_1 && tlbMG_m_validVec_2 &&
tlbMG_m_validVec_3 &&
tlbMG_m_validVec_4 &&
tlbMG_m_validVec_5 &&
tlbMG_m_validVec_6 &&
tlbMG_m_validVec_7 ;
assign tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_1__ETC___d2189 =
tlbMG_m_validVec_0_123_AND_tlbMG_m_validVec_1__ETC___d2159 &&
!SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[0] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[1] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[2] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[3] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[4] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[5] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[6] &&
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[7] ;
assign transCache_RDY_deqResp__757_AND_NOT_transCache_ETC___d1827 =
transCache$RDY_deqResp &&
NOT_transCacheReqQ_empty_dummy2_0_read__758_75_ETC___d1767 &&
((NOT_transCacheReqQ_data_0_768_769_OR_NOT_pendW_ETC___d1776 ||
IF_transCache_RDY_resp__756_AND_transCache_res_ETC___d1781) &&
IF_transCacheReqQ_data_0_768_AND_pendWait_0_du_ETC___d1812 &&
IF_NOT_transCacheReqQ_data_0_768_769_OR_NOT_pe_ETC___d1822 ||
!memReqQ_full) ;
assign transCache_resp__777_BITS_45_TO_44_778_ULT_2___d1779 =
transCache$resp[45:44] < 2'd2 ;
assign upd__h144732 =
WILL_FIRE_RL_tlbMG_m_doUpdateRep ?
MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1 :
8'd0 ;
assign v__h101631 =
pendValid_0_dummy2_1$Q_OUT &&
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573 ;
assign v__h143190 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_tlbMG_m__ETC___d2201 ?
addIdx__h147257 :
v__h144447 ;
assign v__h144447 =
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 ?
tlbMG_m_randIdx :
v__h144923 ;
assign v__h144923 =
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[0] ||
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[1] ||
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[2] ||
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[3] ||
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[4] ||
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[5] ||
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[6] ||
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[7]) ?
addIdx__h145990 :
3'd0 ;
assign v__h81624 =
(memReqQ_enqReq_dummy2_2$Q_OUT &&
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648) ?
v__h81907 :
memReqQ_enqP ;
assign v__h81907 = memReqQ_enqP + 1'd1 ;
assign v__h89194 =
(respLdQ_enqReq_dummy2_2$Q_OUT &&
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745) ?
v__h89477 :
respLdQ_enqP ;
assign v__h89477 = respLdQ_enqP + 1'd1 ;
assign val__h41243 =
(tlbMG_m_lruBit_dummy2_0$Q_OUT &&
tlbMG_m_lruBit_dummy2_1$Q_OUT) ?
tlbMG_m_lruBit_rl :
8'd0 ;
assign val__h41244 = val__h41243 | x__h41318 ;
assign value__h117443 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 ?
2'd3 :
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1093 ;
assign value__h119411 =
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 ?
3'd7 :
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1506 ;
assign vm_info_basePPN__h116624 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 ?
vm_info_I[43:0] :
vm_info_D[43:0] ;
assign vm_info_basePPN__h136984 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 ?
vm_info_I[43:0] :
vm_info_D[43:0] ;
assign vm_info_prv__h116619 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 ?
vm_info_I[48:47] :
vm_info_D[48:47] ;
assign vm_info_prv__h133721 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 ?
vm_info_I[48:47] :
vm_info_D[48:47] ;
assign vm_info_prv__h136979 =
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 ?
vm_info_I[48:47] :
vm_info_D[48:47] ;
assign vpn__h104314 =
rqFromCQ_data_0_dummy2_1$Q_OUT ?
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d487 :
27'd0 ;
assign w__h117423 = value__h117443 ;
assign way__h36041 =
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250 ?
2'd3 :
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d269 ;
assign x__h133697 = { basePpn__h133693, 12'd0 } ;
assign x__h136737 =
{ SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[53:10],
12'd0 } ;
assign x__h41318 = 8'd1 << tlbMG_m_updRepIdx_rl[2:0] ;
always@(memReqQ_deqP or memReqQ_data_0 or memReqQ_data_1)
begin
case (memReqQ_deqP)
1'd0:
CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1 =
memReqQ_data_0[64:1];
1'd1:
CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1 =
memReqQ_data_1[64:1];
endcase
end
always@(memReqQ_deqP or memReqQ_data_0 or memReqQ_data_1)
begin
case (memReqQ_deqP)
1'd0:
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 =
memReqQ_data_0[0];
1'd1:
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 =
memReqQ_data_1[0];
endcase
end
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
begin
case (respLdQ_deqP)
1'd0: def__h135941 = respLdQ_data_0[0];
1'd1: def__h135941 = respLdQ_data_1[0];
endcase
end
always@(idx__h135713 or pendWalkLevel_0 or pendWalkLevel_1)
begin
case (idx__h135713)
1'd0: walkLevel__h136646 = pendWalkLevel_0;
1'd1: walkLevel__h136646 = pendWalkLevel_1;
endcase
end
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
begin
case (tlbReqQ_data_0)
1'd0:
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 =
!pendReq_0[29];
1'd1:
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 =
!pendReq_1[29];
endcase
end
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
begin
case (tlbReqQ_data_0)
1'd0:
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138 =
pendReq_0[26:0];
1'd1:
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138 =
pendReq_1[26:0];
endcase
end
always@(tlbMG_m_entryVec_0 or
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
begin
case (tlbMG_m_entryVec_0[1:0])
2'd0, 2'd1:
IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133 =
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
default: IF_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_EQ_0_ETC___d1133 =
tlbMG_m_entryVec_0[1:0] != 2'd2 ||
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
endcase
end
always@(tlbMG_m_entryVec_0 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138)
begin
case (tlbMG_m_entryVec_0[1:0])
2'd0:
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_SEL_ARR__ETC__q3 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138;
2'd1:
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_SEL_ARR__ETC__q3 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:9],
9'd0 };
2'd2:
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_SEL_ARR__ETC__q3 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:18],
18'd0 };
2'd3: CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_SEL_ARR__ETC__q3 = 27'd0;
endcase
end
always@(tlbMG_m_entryVec_1 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138)
begin
case (tlbMG_m_entryVec_1[1:0])
2'd0:
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_SEL_ARR__ETC__q4 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138;
2'd1:
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_SEL_ARR__ETC__q4 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:9],
9'd0 };
2'd2:
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_SEL_ARR__ETC__q4 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:18],
18'd0 };
2'd3: CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_SEL_ARR__ETC__q4 = 27'd0;
endcase
end
always@(tlbMG_m_entryVec_1 or
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
begin
case (tlbMG_m_entryVec_1[1:0])
2'd0, 2'd1:
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q5 =
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
default: CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q5 =
tlbMG_m_entryVec_1[1:0] != 2'd2 ||
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
endcase
end
always@(tlbMG_m_entryVec_2 or
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
begin
case (tlbMG_m_entryVec_2[1:0])
2'd0, 2'd1:
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 =
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
default: CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 =
tlbMG_m_entryVec_2[1:0] != 2'd2 ||
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
endcase
end
always@(tlbMG_m_entryVec_2 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138)
begin
case (tlbMG_m_entryVec_2[1:0])
2'd0:
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_SEL_ARR__ETC__q7 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138;
2'd1:
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_SEL_ARR__ETC__q7 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:9],
9'd0 };
2'd2:
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_SEL_ARR__ETC__q7 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:18],
18'd0 };
2'd3: CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_SEL_ARR__ETC__q7 = 27'd0;
endcase
end
always@(tlbMG_m_entryVec_3 or
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
begin
case (tlbMG_m_entryVec_3[1:0])
2'd0, 2'd1:
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q8 =
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
default: CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q8 =
tlbMG_m_entryVec_3[1:0] != 2'd2 ||
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
endcase
end
always@(tlbMG_m_entryVec_3 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138)
begin
case (tlbMG_m_entryVec_3[1:0])
2'd0:
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_SEL_ARR__ETC__q9 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138;
2'd1:
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_SEL_ARR__ETC__q9 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:9],
9'd0 };
2'd2:
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_SEL_ARR__ETC__q9 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:18],
18'd0 };
2'd3: CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_SEL_ARR__ETC__q9 = 27'd0;
endcase
end
always@(tlbMG_m_entryVec_4 or
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
begin
case (tlbMG_m_entryVec_4[1:0])
2'd0, 2'd1:
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q10 =
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
default: CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q10 =
tlbMG_m_entryVec_4[1:0] != 2'd2 ||
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
endcase
end
always@(tlbMG_m_entryVec_4 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138)
begin
case (tlbMG_m_entryVec_4[1:0])
2'd0:
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_SEL_ARR__ETC__q11 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138;
2'd1:
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_SEL_ARR__ETC__q11 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:9],
9'd0 };
2'd2:
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_SEL_ARR__ETC__q11 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:18],
18'd0 };
2'd3: CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_SEL_ARR__ETC__q11 = 27'd0;
endcase
end
always@(tlbMG_m_entryVec_5 or
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
begin
case (tlbMG_m_entryVec_5[1:0])
2'd0, 2'd1:
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q12 =
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
default: CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q12 =
tlbMG_m_entryVec_5[1:0] != 2'd2 ||
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
endcase
end
always@(tlbMG_m_entryVec_5 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138)
begin
case (tlbMG_m_entryVec_5[1:0])
2'd0:
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_SEL_ARR__ETC__q13 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138;
2'd1:
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_SEL_ARR__ETC__q13 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:9],
9'd0 };
2'd2:
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_SEL_ARR__ETC__q13 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:18],
18'd0 };
2'd3: CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_SEL_ARR__ETC__q13 = 27'd0;
endcase
end
always@(tlbMG_m_entryVec_6 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138)
begin
case (tlbMG_m_entryVec_6[1:0])
2'd0:
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_SEL_ARR__ETC__q14 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138;
2'd1:
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_SEL_ARR__ETC__q14 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:9],
9'd0 };
2'd2:
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_SEL_ARR__ETC__q14 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:18],
18'd0 };
2'd3: CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_SEL_ARR__ETC__q14 = 27'd0;
endcase
end
always@(tlbMG_m_entryVec_7 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138)
begin
case (tlbMG_m_entryVec_7[1:0])
2'd0:
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_SEL_ARR__ETC__q15 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138;
2'd1:
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_SEL_ARR__ETC__q15 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:9],
9'd0 };
2'd2:
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_SEL_ARR__ETC__q15 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138[26:18],
18'd0 };
2'd3: CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_SEL_ARR__ETC__q15 = 27'd0;
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0: x__h122416 = tlb4KB_m_tlbRam_0_bram$DOB[1:0];
2'd1: x__h122416 = tlb4KB_m_tlbRam_1_bram$DOB[1:0];
2'd2: x__h122416 = tlb4KB_m_tlbRam_2_bram$DOB[1:0];
2'd3: x__h122416 = tlb4KB_m_tlbRam_3_bram$DOB[1:0];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1402 =
!tlb4KB_m_tlbRam_0_bram$DOB[8];
2'd1:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1402 =
!tlb4KB_m_tlbRam_1_bram$DOB[8];
2'd2:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1402 =
!tlb4KB_m_tlbRam_2_bram$DOB[8];
2'd3:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1402 =
!tlb4KB_m_tlbRam_3_bram$DOB[8];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1415 =
!tlb4KB_m_tlbRam_0_bram$DOB[7];
2'd1:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1415 =
!tlb4KB_m_tlbRam_1_bram$DOB[7];
2'd2:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1415 =
!tlb4KB_m_tlbRam_2_bram$DOB[7];
2'd3:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1415 =
!tlb4KB_m_tlbRam_3_bram$DOB[7];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1424 =
!tlb4KB_m_tlbRam_0_bram$DOB[6];
2'd1:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1424 =
!tlb4KB_m_tlbRam_1_bram$DOB[6];
2'd2:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1424 =
!tlb4KB_m_tlbRam_2_bram$DOB[6];
2'd3:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1424 =
!tlb4KB_m_tlbRam_3_bram$DOB[6];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1437 =
!tlb4KB_m_tlbRam_0_bram$DOB[5];
2'd1:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1437 =
!tlb4KB_m_tlbRam_1_bram$DOB[5];
2'd2:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1437 =
!tlb4KB_m_tlbRam_2_bram$DOB[5];
2'd3:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1437 =
!tlb4KB_m_tlbRam_3_bram$DOB[5];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1450 =
!tlb4KB_m_tlbRam_0_bram$DOB[4];
2'd1:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1450 =
!tlb4KB_m_tlbRam_1_bram$DOB[4];
2'd2:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1450 =
!tlb4KB_m_tlbRam_2_bram$DOB[4];
2'd3:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1450 =
!tlb4KB_m_tlbRam_3_bram$DOB[4];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1463 =
!tlb4KB_m_tlbRam_0_bram$DOB[3];
2'd1:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1463 =
!tlb4KB_m_tlbRam_1_bram$DOB[3];
2'd2:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1463 =
!tlb4KB_m_tlbRam_2_bram$DOB[3];
2'd3:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1463 =
!tlb4KB_m_tlbRam_3_bram$DOB[3];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1476 =
!tlb4KB_m_tlbRam_0_bram$DOB[2];
2'd1:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1476 =
!tlb4KB_m_tlbRam_1_bram$DOB[2];
2'd2:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1476 =
!tlb4KB_m_tlbRam_2_bram$DOB[2];
2'd3:
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1476 =
!tlb4KB_m_tlbRam_3_bram$DOB[2];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 =
!tlbMG_m_entryVec_0[8];
3'd1:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 =
!tlbMG_m_entryVec_1[8];
3'd2:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 =
!tlbMG_m_entryVec_2[8];
3'd3:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 =
!tlbMG_m_entryVec_3[8];
3'd4:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 =
!tlbMG_m_entryVec_4[8];
3'd5:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 =
!tlbMG_m_entryVec_5[8];
3'd6:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 =
!tlbMG_m_entryVec_6[8];
3'd7:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540 =
!tlbMG_m_entryVec_7[8];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 =
!tlbMG_m_entryVec_0[7];
3'd1:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 =
!tlbMG_m_entryVec_1[7];
3'd2:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 =
!tlbMG_m_entryVec_2[7];
3'd3:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 =
!tlbMG_m_entryVec_3[7];
3'd4:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 =
!tlbMG_m_entryVec_4[7];
3'd5:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 =
!tlbMG_m_entryVec_5[7];
3'd6:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 =
!tlbMG_m_entryVec_6[7];
3'd7:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561 =
!tlbMG_m_entryVec_7[7];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 =
!tlbMG_m_entryVec_0[6];
3'd1:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 =
!tlbMG_m_entryVec_1[6];
3'd2:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 =
!tlbMG_m_entryVec_2[6];
3'd3:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 =
!tlbMG_m_entryVec_3[6];
3'd4:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 =
!tlbMG_m_entryVec_4[6];
3'd5:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 =
!tlbMG_m_entryVec_5[6];
3'd6:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 =
!tlbMG_m_entryVec_6[6];
3'd7:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582 =
!tlbMG_m_entryVec_7[6];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 =
!tlbMG_m_entryVec_0[5];
3'd1:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 =
!tlbMG_m_entryVec_1[5];
3'd2:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 =
!tlbMG_m_entryVec_2[5];
3'd3:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 =
!tlbMG_m_entryVec_3[5];
3'd4:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 =
!tlbMG_m_entryVec_4[5];
3'd5:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 =
!tlbMG_m_entryVec_5[5];
3'd6:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 =
!tlbMG_m_entryVec_6[5];
3'd7:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603 =
!tlbMG_m_entryVec_7[5];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 =
!tlbMG_m_entryVec_0[3];
3'd1:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 =
!tlbMG_m_entryVec_1[3];
3'd2:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 =
!tlbMG_m_entryVec_2[3];
3'd3:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 =
!tlbMG_m_entryVec_3[3];
3'd4:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 =
!tlbMG_m_entryVec_4[3];
3'd5:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 =
!tlbMG_m_entryVec_5[3];
3'd6:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 =
!tlbMG_m_entryVec_6[3];
3'd7:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645 =
!tlbMG_m_entryVec_7[3];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 =
!tlbMG_m_entryVec_0[4];
3'd1:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 =
!tlbMG_m_entryVec_1[4];
3'd2:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 =
!tlbMG_m_entryVec_2[4];
3'd3:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 =
!tlbMG_m_entryVec_3[4];
3'd4:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 =
!tlbMG_m_entryVec_4[4];
3'd5:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 =
!tlbMG_m_entryVec_5[4];
3'd6:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 =
!tlbMG_m_entryVec_6[4];
3'd7:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624 =
!tlbMG_m_entryVec_7[4];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 =
!tlbMG_m_entryVec_0[2];
3'd1:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 =
!tlbMG_m_entryVec_1[2];
3'd2:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 =
!tlbMG_m_entryVec_2[2];
3'd3:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 =
!tlbMG_m_entryVec_3[2];
3'd4:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 =
!tlbMG_m_entryVec_4[2];
3'd5:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 =
!tlbMG_m_entryVec_5[2];
3'd6:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 =
!tlbMG_m_entryVec_6[2];
3'd7:
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666 =
!tlbMG_m_entryVec_7[2];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685 =
tlbMG_m_entryVec_0[5];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685 =
tlbMG_m_entryVec_1[5];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685 =
tlbMG_m_entryVec_2[5];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685 =
tlbMG_m_entryVec_3[5];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685 =
tlbMG_m_entryVec_4[5];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685 =
tlbMG_m_entryVec_5[5];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685 =
tlbMG_m_entryVec_6[5];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_5_586_tlbMG_ETC___d1685 =
tlbMG_m_entryVec_7[5];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679 =
tlbMG_m_entryVec_0[8];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679 =
tlbMG_m_entryVec_1[8];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679 =
tlbMG_m_entryVec_2[8];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679 =
tlbMG_m_entryVec_3[8];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679 =
tlbMG_m_entryVec_4[8];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679 =
tlbMG_m_entryVec_5[8];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679 =
tlbMG_m_entryVec_6[8];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_8_523_tlbMG_ETC___d1679 =
tlbMG_m_entryVec_7[8];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1708 =
tlb4KB_m_tlbRam_0_bram$DOB[3];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1708 =
tlb4KB_m_tlbRam_1_bram$DOB[3];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1708 =
tlb4KB_m_tlbRam_2_bram$DOB[3];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1708 =
tlb4KB_m_tlbRam_3_bram$DOB[3];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681 =
tlbMG_m_entryVec_0[7];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681 =
tlbMG_m_entryVec_1[7];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681 =
tlbMG_m_entryVec_2[7];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681 =
tlbMG_m_entryVec_3[7];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681 =
tlbMG_m_entryVec_4[7];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681 =
tlbMG_m_entryVec_5[7];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681 =
tlbMG_m_entryVec_6[7];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_7_544_tlbMG_ETC___d1681 =
tlbMG_m_entryVec_7[7];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689 =
tlbMG_m_entryVec_0[3];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689 =
tlbMG_m_entryVec_1[3];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689 =
tlbMG_m_entryVec_2[3];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689 =
tlbMG_m_entryVec_3[3];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689 =
tlbMG_m_entryVec_4[3];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689 =
tlbMG_m_entryVec_5[3];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689 =
tlbMG_m_entryVec_6[3];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_3_628_tlbMG_ETC___d1689 =
tlbMG_m_entryVec_7[3];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1704 =
tlb4KB_m_tlbRam_0_bram$DOB[5];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1704 =
tlb4KB_m_tlbRam_1_bram$DOB[5];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1704 =
tlb4KB_m_tlbRam_2_bram$DOB[5];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1704 =
tlb4KB_m_tlbRam_3_bram$DOB[5];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1700 =
tlb4KB_m_tlbRam_0_bram$DOB[7];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1700 =
tlb4KB_m_tlbRam_1_bram$DOB[7];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1700 =
tlb4KB_m_tlbRam_2_bram$DOB[7];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1700 =
tlb4KB_m_tlbRam_3_bram$DOB[7];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1698 =
tlb4KB_m_tlbRam_0_bram$DOB[8];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1698 =
tlb4KB_m_tlbRam_1_bram$DOB[8];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1698 =
tlb4KB_m_tlbRam_2_bram$DOB[8];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1698 =
tlb4KB_m_tlbRam_3_bram$DOB[8];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1384 =
tlb4KB_m_tlbRam_0_bram$DOB[79:53];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1384 =
tlb4KB_m_tlbRam_1_bram$DOB[79:53];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1384 =
tlb4KB_m_tlbRam_2_bram$DOB[79:53];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1384 =
tlb4KB_m_tlbRam_3_bram$DOB[79:53];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510 =
tlbMG_m_entryVec_0[79:53];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510 =
tlbMG_m_entryVec_1[79:53];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510 =
tlbMG_m_entryVec_2[79:53];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510 =
tlbMG_m_entryVec_3[79:53];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510 =
tlbMG_m_entryVec_4[79:53];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510 =
tlbMG_m_entryVec_5[79:53];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510 =
tlbMG_m_entryVec_6[79:53];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510 =
tlbMG_m_entryVec_7[79:53];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 =
tlbMG_m_entryVec_0[1:0];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 =
tlbMG_m_entryVec_1[1:0];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 =
tlbMG_m_entryVec_2[1:0];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 =
tlbMG_m_entryVec_3[1:0];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 =
tlbMG_m_entryVec_4[1:0];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 =
tlbMG_m_entryVec_5[1:0];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 =
tlbMG_m_entryVec_6[1:0];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 =
tlbMG_m_entryVec_7[1:0];
endcase
end
always@(transCacheReqQ_data_0 or pendReq_0 or pendReq_1)
begin
case (transCacheReqQ_data_0)
1'd0:
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 =
!pendReq_0[29];
1'd1:
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 =
!pendReq_1[29];
endcase
end
always@(transCacheReqQ_data_0 or pendReq_0 or pendReq_1)
begin
case (transCacheReqQ_data_0)
1'd0:
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1793 =
pendReq_0[26:0];
1'd1:
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1793 =
pendReq_1[26:0];
endcase
end
always@(transCache$resp or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1793)
begin
case (transCache$resp[45:44])
2'd0:
x__h133729 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1793[8:0];
2'd1:
x__h133729 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1793[17:9];
2'd2:
x__h133729 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1793[26:18];
2'd3: x__h133729 = 9'b010101010 /* unspecified value */ ;
endcase
end
always@(idx__h135713 or pendReq_0 or pendReq_1)
begin
case (idx__h135713)
1'd0:
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 =
!pendReq_0[29];
1'd1:
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 =
!pendReq_1[29];
endcase
end
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
begin
case (respLdQ_deqP)
1'd0:
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876 =
respLdQ_data_0[64:1];
1'd1:
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876 =
respLdQ_data_1[64:1];
endcase
end
always@(walkLevel__h136646 or
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876)
begin
case (walkLevel__h136646)
2'd0:
masked_ppn__h137253 =
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[53:10];
2'd1:
masked_ppn__h137253 =
{ SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[53:19],
9'd0 };
2'd2:
masked_ppn__h137253 =
{ SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[53:28],
18'd0 };
2'd3: masked_ppn__h137253 = 44'd0;
endcase
end
always@(idx__h135713 or pendReq_0 or pendReq_1)
begin
case (idx__h135713)
1'd0:
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899 =
pendReq_0[26:0];
1'd1:
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899 =
pendReq_1[26:0];
endcase
end
always@(newWalkLevel__h136647 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899)
begin
case (newWalkLevel__h136647)
2'd0:
x__h136754 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899[8:0];
2'd1:
x__h136754 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899[17:9];
2'd2:
x__h136754 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899[26:18];
2'd3: x__h136754 = 9'b010101010 /* unspecified value */ ;
endcase
end
always@(walkLevel__h136646 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899)
begin
case (walkLevel__h136646)
2'd0:
masked_vpn__h137252 =
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899;
2'd1:
masked_vpn__h137252 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899[26:9],
9'd0 };
2'd2:
masked_vpn__h137252 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899[26:18],
18'd0 };
2'd3: masked_vpn__h137252 = 27'd0;
endcase
end
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
begin
case (respLdQ_deqP)
1'd0:
SEL_ARR_NOT_respLdQ_data_0_864_BIT_0_865_911_N_ETC___d1914 =
!respLdQ_data_0[0];
1'd1:
SEL_ARR_NOT_respLdQ_data_0_864_BIT_0_865_911_N_ETC___d1914 =
!respLdQ_data_1[0];
endcase
end
always@(walkLevel__h136646 or
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899)
begin
case (walkLevel__h136646)
2'd1:
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1929 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899[26:9],
9'd0 };
2'd2:
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1929 =
{ SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899[26:18],
18'd0 };
default: IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1929 =
27'd0;
endcase
end
always@(walkLevel__h136646 or
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876)
begin
case (walkLevel__h136646)
2'd1:
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d2016 =
{ SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[53:19],
9'd0 };
2'd2:
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d2016 =
{ SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[53:28],
18'd0 };
default: IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d2016 =
44'd0;
endcase
end
always@(walkLevel__h136646 or
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d2016)
begin
case (walkLevel__h136646)
2'd1:
CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q16 =
{ IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d2016[43:9],
9'd0 };
2'd2:
CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q16 =
{ IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d2016[43:18],
18'd0 };
default: CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q16 =
44'd0;
endcase
end
always@(walkLevel__h136646 or
IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1929)
begin
case (walkLevel__h136646)
2'd1:
CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q17 =
{ IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1929[26:9],
9'd0 };
2'd2:
CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q17 =
{ IF_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel_1_ETC___d1929[26:18],
18'd0 };
default: CASE_walkLevel36646_1_IF_SEL_ARR_pendWalkLevel_ETC__q17 =
27'd0;
endcase
end
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
begin
case (tlbReqQ_data_0)
1'd0:
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1378 =
pendReq_0[28:27];
1'd1:
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1378 =
pendReq_1[28:27];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521 =
tlbMG_m_entryVec_0[52:9];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521 =
tlbMG_m_entryVec_1[52:9];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521 =
tlbMG_m_entryVec_2[52:9];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521 =
tlbMG_m_entryVec_3[52:9];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521 =
tlbMG_m_entryVec_4[52:9];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521 =
tlbMG_m_entryVec_5[52:9];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521 =
tlbMG_m_entryVec_6[52:9];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521 =
tlbMG_m_entryVec_7[52:9];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1391 =
tlb4KB_m_tlbRam_0_bram$DOB[52:9];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1391 =
tlb4KB_m_tlbRam_1_bram$DOB[52:9];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1391 =
tlb4KB_m_tlbRam_2_bram$DOB[52:9];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1391 =
tlb4KB_m_tlbRam_3_bram$DOB[52:9];
endcase
end
always@(idx__h135713 or pendReq_0 or pendReq_1)
begin
case (idx__h135713)
1'd0:
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1990 =
pendReq_0[28:27];
1'd1:
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1990 =
pendReq_1[28:27];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1710 =
tlb4KB_m_tlbRam_0_bram$DOB[2];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1710 =
tlb4KB_m_tlbRam_1_bram$DOB[2];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1710 =
tlb4KB_m_tlbRam_2_bram$DOB[2];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1710 =
tlb4KB_m_tlbRam_3_bram$DOB[2];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691 =
tlbMG_m_entryVec_0[2];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691 =
tlbMG_m_entryVec_1[2];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691 =
tlbMG_m_entryVec_2[2];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691 =
tlbMG_m_entryVec_3[2];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691 =
tlbMG_m_entryVec_4[2];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691 =
tlbMG_m_entryVec_5[2];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691 =
tlbMG_m_entryVec_6[2];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_2_649_tlbMG_ETC___d1691 =
tlbMG_m_entryVec_7[2];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1706 =
tlb4KB_m_tlbRam_0_bram$DOB[4];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1706 =
tlb4KB_m_tlbRam_1_bram$DOB[4];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1706 =
tlb4KB_m_tlbRam_2_bram$DOB[4];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1706 =
tlb4KB_m_tlbRam_3_bram$DOB[4];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687 =
tlbMG_m_entryVec_0[4];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687 =
tlbMG_m_entryVec_1[4];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687 =
tlbMG_m_entryVec_2[4];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687 =
tlbMG_m_entryVec_3[4];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687 =
tlbMG_m_entryVec_4[4];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687 =
tlbMG_m_entryVec_5[4];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687 =
tlbMG_m_entryVec_6[4];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_4_607_tlbMG_ETC___d1687 =
tlbMG_m_entryVec_7[4];
endcase
end
always@(w__h117423 or
tlb4KB_m_tlbRam_0_bram$DOB or
tlb4KB_m_tlbRam_1_bram$DOB or
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
begin
case (w__h117423)
2'd0:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1702 =
tlb4KB_m_tlbRam_0_bram$DOB[6];
2'd1:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1702 =
tlb4KB_m_tlbRam_1_bram$DOB[6];
2'd2:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1702 =
tlb4KB_m_tlbRam_2_bram$DOB[6];
2'd3:
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1702 =
tlb4KB_m_tlbRam_3_bram$DOB[6];
endcase
end
always@(idx__h119391 or
tlbMG_m_entryVec_0 or
tlbMG_m_entryVec_1 or
tlbMG_m_entryVec_2 or
tlbMG_m_entryVec_3 or
tlbMG_m_entryVec_4 or
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
begin
case (idx__h119391)
3'd0:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683 =
tlbMG_m_entryVec_0[6];
3'd1:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683 =
tlbMG_m_entryVec_1[6];
3'd2:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683 =
tlbMG_m_entryVec_2[6];
3'd3:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683 =
tlbMG_m_entryVec_3[6];
3'd4:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683 =
tlbMG_m_entryVec_4[6];
3'd5:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683 =
tlbMG_m_entryVec_5[6];
3'd6:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683 =
tlbMG_m_entryVec_6[6];
3'd7:
SEL_ARR_tlbMG_m_entryVec_0_125_BIT_6_565_tlbMG_ETC___d1683 =
tlbMG_m_entryVec_7[6];
endcase
end
always@(NOT_transCacheReqQ_data_0_768_769_OR_NOT_pendW_ETC___d1776 or
pendWalkAddr_0_786_EQ_0_CONCAT_IF_transCache_r_ETC___d1801 or
pendValid_0_dummy2_0$Q_OUT or
pendValid_0_dummy2_1$Q_OUT or
pendValid_0_rl or
pendValid_1_dummy2_0$Q_OUT or
pendValid_1_dummy2_1$Q_OUT or pendValid_1_rl)
begin
case (NOT_transCacheReqQ_data_0_768_769_OR_NOT_pendW_ETC___d1776 ||
!pendWalkAddr_0_786_EQ_0_CONCAT_IF_transCache_r_ETC___d1801)
1'd0:
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_838__ETC___d1845 =
!pendValid_0_dummy2_0$Q_OUT || !pendValid_0_dummy2_1$Q_OUT ||
!pendValid_0_rl;
1'd1:
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_838__ETC___d1845 =
!pendValid_1_dummy2_0$Q_OUT || !pendValid_1_dummy2_1$Q_OUT ||
!pendValid_1_rl;
endcase
end
always@(i__h136071 or
pendValid_0_dummy2_0$Q_OUT or
pendValid_0_dummy2_1$Q_OUT or
pendValid_0_rl or
pendValid_1_dummy2_0$Q_OUT or
pendValid_1_dummy2_1$Q_OUT or pendValid_1_rl)
begin
case (i__h136071)
1'd0:
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_838__ETC___d1970 =
!pendValid_0_dummy2_0$Q_OUT || !pendValid_0_dummy2_1$Q_OUT ||
!pendValid_0_rl;
1'd1:
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_838__ETC___d1970 =
!pendValid_1_dummy2_0$Q_OUT || !pendValid_1_dummy2_1$Q_OUT ||
!pendValid_1_rl;
endcase
end
always@(transCacheReqQ_data_0 or
pendWait_0_dummy2_0$Q_OUT or
pendWait_0_dummy2_1$Q_OUT or
pendWait_0_rl or
pendWait_1_dummy2_0$Q_OUT or
pendWait_1_dummy2_1$Q_OUT or pendWait_1_rl)
begin
case (transCacheReqQ_data_0)
1'd0:
SEL_ARR_pendWait_0_dummy2_0_read__770_AND_pend_ETC___d1834 =
pendWait_0_dummy2_0$Q_OUT && pendWait_0_dummy2_1$Q_OUT &&
pendWait_0_rl[2:1] != 2'd0;
1'd1:
SEL_ARR_pendWait_0_dummy2_0_read__770_AND_pend_ETC___d1834 =
pendWait_1_dummy2_0$Q_OUT && pendWait_1_dummy2_1$Q_OUT &&
pendWait_1_rl[2:1] != 2'd0;
endcase
end
always@(tlbMG_m_randIdx or
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161)
begin
case (tlbMG_m_randIdx)
3'd0:
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 =
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[0];
3'd1:
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 =
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[1];
3'd2:
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 =
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[2];
3'd3:
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 =
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[3];
3'd4:
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 =
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[4];
3'd5:
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 =
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[5];
3'd6:
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 =
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[6];
3'd7:
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d2171 =
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d2161[7];
endcase
end
always@(v__h101631 or
pendValid_0_dummy2_1$Q_OUT or
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573 or
pendValid_1_dummy2_1$Q_OUT or
IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580)
begin
case (v__h101631)
1'd0:
SEL_ARR_pendValid_0_dummy2_1_read__29_AND_IF_p_ETC___d1046 =
pendValid_0_dummy2_1$Q_OUT &&
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573;
1'd1:
SEL_ARR_pendValid_0_dummy2_1_read__29_AND_IF_p_ETC___d1046 =
pendValid_1_dummy2_1$Q_OUT &&
IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580;
endcase
end
always@(transCacheReqQ_data_0 or pendReq_0 or pendReq_1)
begin
case (transCacheReqQ_data_0)
1'd0:
CASE_transCacheReqQ_data_0_0_pendReq_0_BITS_28_ETC__q18 =
pendReq_0[28:27];
1'd1:
CASE_transCacheReqQ_data_0_0_pendReq_0_BITS_28_ETC__q18 =
pendReq_1[28:27];
endcase
end
always@(tlbReqQ_data_0 or
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051 or
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056)
begin
case (tlbReqQ_data_0)
1'd0:
CASE_tlbReqQ_data_0_0_pendWait_0_dummy2_1_read_ETC__q19 =
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051;
1'd1:
CASE_tlbReqQ_data_0_0_pendWait_0_dummy2_1_read_ETC__q19 =
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056;
endcase
end
always@(v__h101631 or
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051 or
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056)
begin
case (v__h101631)
1'd0:
CASE_v01631_0_pendWait_0_dummy2_1_read__047_AN_ETC__q20 =
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051;
1'd1:
CASE_v01631_0_pendWait_0_dummy2_1_read__047_AN_ETC__q20 =
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
dFlushReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
flushDoneQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
flushDoneQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
flushDoneQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
flushDoneQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
flushDoneQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
iFlushReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
memReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
memReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
memReqQ_data_1 <= `BSV_ASSIGNMENT_DELAY 65'd0;
memReqQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
memReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
memReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
memReqQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
memReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA;
memReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
pendWait_0_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
pendWait_1_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
respForOtherReq <= `BSV_ASSIGNMENT_DELAY 2'd0;
respLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
respLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
respLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 65'd0;
respLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
respLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
respLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
respLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
respLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA;
respLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY 30'h2AAAAAAA;
rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
rsToCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY 84'hAAAAAAAAAAAAAAAAAAAAA;
rsToCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
rsToCQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlb4KB_m_flushIdx <= `BSV_ASSIGNMENT_DELAY 8'd0;
tlb4KB_m_pendReq_rl <= `BSV_ASSIGNMENT_DELAY
82'h0AAAAAAAAAAAAAAAAAAAA;
tlb4KB_m_repRam_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
tlb4KB_m_repRam_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlb4KB_m_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
tlb4KB_m_tlbRam_0_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
tlb4KB_m_tlbRam_1_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
tlb4KB_m_tlbRam_2_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
tlb4KB_m_tlbRam_3_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbMG_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 8'd0;
tlbMG_m_randIdx <= `BSV_ASSIGNMENT_DELAY 3'd0;
tlbMG_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY 4'd2;
tlbMG_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbMG_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbMG_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbMG_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbMG_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbMG_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbMG_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbMG_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlbReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
tlbReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
transCacheReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
transCacheReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
transCacheReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
vm_info_D <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
vm_info_I <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
waitFlushDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (dFlushReq$EN) dFlushReq <= `BSV_ASSIGNMENT_DELAY dFlushReq$D_IN;
if (flushDoneQ_clearReq_rl$EN)
flushDoneQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
flushDoneQ_clearReq_rl$D_IN;
if (flushDoneQ_deqReq_rl$EN)
flushDoneQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
flushDoneQ_deqReq_rl$D_IN;
if (flushDoneQ_empty$EN)
flushDoneQ_empty <= `BSV_ASSIGNMENT_DELAY flushDoneQ_empty$D_IN;
if (flushDoneQ_enqReq_rl$EN)
flushDoneQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
flushDoneQ_enqReq_rl$D_IN;
if (flushDoneQ_full$EN)
flushDoneQ_full <= `BSV_ASSIGNMENT_DELAY flushDoneQ_full$D_IN;
if (iFlushReq$EN) iFlushReq <= `BSV_ASSIGNMENT_DELAY iFlushReq$D_IN;
if (memReqQ_clearReq_rl$EN)
memReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
memReqQ_clearReq_rl$D_IN;
if (memReqQ_data_0$EN)
memReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY memReqQ_data_0$D_IN;
if (memReqQ_data_1$EN)
memReqQ_data_1 <= `BSV_ASSIGNMENT_DELAY memReqQ_data_1$D_IN;
if (memReqQ_deqP$EN)
memReqQ_deqP <= `BSV_ASSIGNMENT_DELAY memReqQ_deqP$D_IN;
if (memReqQ_deqReq_rl$EN)
memReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY memReqQ_deqReq_rl$D_IN;
if (memReqQ_empty$EN)
memReqQ_empty <= `BSV_ASSIGNMENT_DELAY memReqQ_empty$D_IN;
if (memReqQ_enqP$EN)
memReqQ_enqP <= `BSV_ASSIGNMENT_DELAY memReqQ_enqP$D_IN;
if (memReqQ_enqReq_rl$EN)
memReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY memReqQ_enqReq_rl$D_IN;
if (memReqQ_full$EN)
memReqQ_full <= `BSV_ASSIGNMENT_DELAY memReqQ_full$D_IN;
if (pendValid_0_rl$EN)
pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY pendValid_0_rl$D_IN;
if (pendValid_1_rl$EN)
pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY pendValid_1_rl$D_IN;
if (pendWait_0_rl$EN)
pendWait_0_rl <= `BSV_ASSIGNMENT_DELAY pendWait_0_rl$D_IN;
if (pendWait_1_rl$EN)
pendWait_1_rl <= `BSV_ASSIGNMENT_DELAY pendWait_1_rl$D_IN;
if (perfReqQ_clearReq_rl$EN)
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
perfReqQ_clearReq_rl$D_IN;
if (perfReqQ_data_0$EN)
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY perfReqQ_data_0$D_IN;
if (perfReqQ_deqReq_rl$EN)
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_deqReq_rl$D_IN;
if (perfReqQ_empty$EN)
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY perfReqQ_empty$D_IN;
if (perfReqQ_enqReq_rl$EN)
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN;
if (perfReqQ_full$EN)
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN;
if (respForOtherReq$EN)
respForOtherReq <= `BSV_ASSIGNMENT_DELAY respForOtherReq$D_IN;
if (respLdQ_clearReq_rl$EN)
respLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
respLdQ_clearReq_rl$D_IN;
if (respLdQ_data_0$EN)
respLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY respLdQ_data_0$D_IN;
if (respLdQ_data_1$EN)
respLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY respLdQ_data_1$D_IN;
if (respLdQ_deqP$EN)
respLdQ_deqP <= `BSV_ASSIGNMENT_DELAY respLdQ_deqP$D_IN;
if (respLdQ_deqReq_rl$EN)
respLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY respLdQ_deqReq_rl$D_IN;
if (respLdQ_empty$EN)
respLdQ_empty <= `BSV_ASSIGNMENT_DELAY respLdQ_empty$D_IN;
if (respLdQ_enqP$EN)
respLdQ_enqP <= `BSV_ASSIGNMENT_DELAY respLdQ_enqP$D_IN;
if (respLdQ_enqReq_rl$EN)
respLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY respLdQ_enqReq_rl$D_IN;
if (respLdQ_full$EN)
respLdQ_full <= `BSV_ASSIGNMENT_DELAY respLdQ_full$D_IN;
if (rqFromCQ_data_0_rl$EN)
rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_data_0_rl$D_IN;
if (rqFromCQ_empty_rl$EN)
rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_empty_rl$D_IN;
if (rqFromCQ_full_rl$EN)
rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_full_rl$D_IN;
if (rsToCQ_data_0_rl$EN)
rsToCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_data_0_rl$D_IN;
if (rsToCQ_empty_rl$EN)
rsToCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_empty_rl$D_IN;
if (rsToCQ_full_rl$EN)
rsToCQ_full_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_full_rl$D_IN;
if (tlb4KB_m_flushIdx$EN)
tlb4KB_m_flushIdx <= `BSV_ASSIGNMENT_DELAY tlb4KB_m_flushIdx$D_IN;
if (tlb4KB_m_pendReq_rl$EN)
tlb4KB_m_pendReq_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_pendReq_rl$D_IN;
if (tlb4KB_m_repRam_rdReqQ_empty_rl$EN)
tlb4KB_m_repRam_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN;
if (tlb4KB_m_repRam_rdReqQ_full_rl$EN)
tlb4KB_m_repRam_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_repRam_rdReqQ_full_rl$D_IN;
if (tlb4KB_m_state$EN)
tlb4KB_m_state <= `BSV_ASSIGNMENT_DELAY tlb4KB_m_state$D_IN;
if (tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN)
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN;
if (tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN)
tlb4KB_m_tlbRam_0_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN;
if (tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN)
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN;
if (tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN)
tlb4KB_m_tlbRam_1_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN;
if (tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN)
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN;
if (tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN)
tlb4KB_m_tlbRam_2_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN;
if (tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN)
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN;
if (tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN)
tlb4KB_m_tlbRam_3_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN;
if (tlbMG_m_lruBit_rl$EN)
tlbMG_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY tlbMG_m_lruBit_rl$D_IN;
if (tlbMG_m_randIdx$EN)
tlbMG_m_randIdx <= `BSV_ASSIGNMENT_DELAY tlbMG_m_randIdx$D_IN;
if (tlbMG_m_updRepIdx_rl$EN)
tlbMG_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
tlbMG_m_updRepIdx_rl$D_IN;
if (tlbMG_m_validVec_0$EN)
tlbMG_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_0$D_IN;
if (tlbMG_m_validVec_1$EN)
tlbMG_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_1$D_IN;
if (tlbMG_m_validVec_2$EN)
tlbMG_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_2$D_IN;
if (tlbMG_m_validVec_3$EN)
tlbMG_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_3$D_IN;
if (tlbMG_m_validVec_4$EN)
tlbMG_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_4$D_IN;
if (tlbMG_m_validVec_5$EN)
tlbMG_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_5$D_IN;
if (tlbMG_m_validVec_6$EN)
tlbMG_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_6$D_IN;
if (tlbMG_m_validVec_7$EN)
tlbMG_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_7$D_IN;
if (tlbReqQ_data_0$EN)
tlbReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY tlbReqQ_data_0$D_IN;
if (tlbReqQ_empty_rl$EN)
tlbReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY tlbReqQ_empty_rl$D_IN;
if (tlbReqQ_full_rl$EN)
tlbReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY tlbReqQ_full_rl$D_IN;
if (transCacheReqQ_data_0$EN)
transCacheReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
transCacheReqQ_data_0$D_IN;
if (transCacheReqQ_empty_rl$EN)
transCacheReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
transCacheReqQ_empty_rl$D_IN;
if (transCacheReqQ_full_rl$EN)
transCacheReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
transCacheReqQ_full_rl$D_IN;
if (vm_info_D$EN) vm_info_D <= `BSV_ASSIGNMENT_DELAY vm_info_D$D_IN;
if (vm_info_I$EN) vm_info_I <= `BSV_ASSIGNMENT_DELAY vm_info_I$D_IN;
if (waitFlushDone$EN)
waitFlushDone <= `BSV_ASSIGNMENT_DELAY waitFlushDone$D_IN;
end
if (pendReq_0$EN) pendReq_0 <= `BSV_ASSIGNMENT_DELAY pendReq_0$D_IN;
if (pendReq_1$EN) pendReq_1 <= `BSV_ASSIGNMENT_DELAY pendReq_1$D_IN;
if (pendWalkAddr_0$EN)
pendWalkAddr_0 <= `BSV_ASSIGNMENT_DELAY pendWalkAddr_0$D_IN;
if (pendWalkAddr_1$EN)
pendWalkAddr_1 <= `BSV_ASSIGNMENT_DELAY pendWalkAddr_1$D_IN;
if (pendWalkLevel_0$EN)
pendWalkLevel_0 <= `BSV_ASSIGNMENT_DELAY pendWalkLevel_0$D_IN;
if (pendWalkLevel_1$EN)
pendWalkLevel_1 <= `BSV_ASSIGNMENT_DELAY pendWalkLevel_1$D_IN;
if (tlbMG_m_entryVec_0$EN)
tlbMG_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_0$D_IN;
if (tlbMG_m_entryVec_1$EN)
tlbMG_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_1$D_IN;
if (tlbMG_m_entryVec_2$EN)
tlbMG_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_2$D_IN;
if (tlbMG_m_entryVec_3$EN)
tlbMG_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_3$D_IN;
if (tlbMG_m_entryVec_4$EN)
tlbMG_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_4$D_IN;
if (tlbMG_m_entryVec_5$EN)
tlbMG_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_5$D_IN;
if (tlbMG_m_entryVec_6$EN)
tlbMG_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_6$D_IN;
if (tlbMG_m_entryVec_7$EN)
tlbMG_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_7$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
dFlushReq = 1'h0;
flushDoneQ_clearReq_rl = 1'h0;
flushDoneQ_deqReq_rl = 1'h0;
flushDoneQ_empty = 1'h0;
flushDoneQ_enqReq_rl = 1'h0;
flushDoneQ_full = 1'h0;
iFlushReq = 1'h0;
memReqQ_clearReq_rl = 1'h0;
memReqQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
memReqQ_data_1 = 65'h0AAAAAAAAAAAAAAAA;
memReqQ_deqP = 1'h0;
memReqQ_deqReq_rl = 1'h0;
memReqQ_empty = 1'h0;
memReqQ_enqP = 1'h0;
memReqQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
memReqQ_full = 1'h0;
pendReq_0 = 30'h2AAAAAAA;
pendReq_1 = 30'h2AAAAAAA;
pendValid_0_rl = 1'h0;
pendValid_1_rl = 1'h0;
pendWait_0_rl = 3'h2;
pendWait_1_rl = 3'h2;
pendWalkAddr_0 = 64'hAAAAAAAAAAAAAAAA;
pendWalkAddr_1 = 64'hAAAAAAAAAAAAAAAA;
pendWalkLevel_0 = 2'h2;
pendWalkLevel_1 = 2'h2;
perfReqQ_clearReq_rl = 1'h0;
perfReqQ_data_0 = 4'hA;
perfReqQ_deqReq_rl = 1'h0;
perfReqQ_empty = 1'h0;
perfReqQ_enqReq_rl = 5'h0A;
perfReqQ_full = 1'h0;
respForOtherReq = 2'h2;
respLdQ_clearReq_rl = 1'h0;
respLdQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
respLdQ_data_1 = 65'h0AAAAAAAAAAAAAAAA;
respLdQ_deqP = 1'h0;
respLdQ_deqReq_rl = 1'h0;
respLdQ_empty = 1'h0;
respLdQ_enqP = 1'h0;
respLdQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
respLdQ_full = 1'h0;
rqFromCQ_data_0_rl = 30'h2AAAAAAA;
rqFromCQ_empty_rl = 1'h0;
rqFromCQ_full_rl = 1'h0;
rsToCQ_data_0_rl = 84'hAAAAAAAAAAAAAAAAAAAAA;
rsToCQ_empty_rl = 1'h0;
rsToCQ_full_rl = 1'h0;
tlb4KB_m_flushIdx = 8'hAA;
tlb4KB_m_pendReq_rl = 82'h2AAAAAAAAAAAAAAAAAAAA;
tlb4KB_m_repRam_rdReqQ_empty_rl = 1'h0;
tlb4KB_m_repRam_rdReqQ_full_rl = 1'h0;
tlb4KB_m_state = 1'h0;
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl = 1'h0;
tlb4KB_m_tlbRam_0_rdReqQ_full_rl = 1'h0;
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl = 1'h0;
tlb4KB_m_tlbRam_1_rdReqQ_full_rl = 1'h0;
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl = 1'h0;
tlb4KB_m_tlbRam_2_rdReqQ_full_rl = 1'h0;
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl = 1'h0;
tlb4KB_m_tlbRam_3_rdReqQ_full_rl = 1'h0;
tlbMG_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
tlbMG_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
tlbMG_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
tlbMG_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
tlbMG_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
tlbMG_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
tlbMG_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
tlbMG_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
tlbMG_m_lruBit_rl = 8'hAA;
tlbMG_m_randIdx = 3'h2;
tlbMG_m_updRepIdx_rl = 4'hA;
tlbMG_m_validVec_0 = 1'h0;
tlbMG_m_validVec_1 = 1'h0;
tlbMG_m_validVec_2 = 1'h0;
tlbMG_m_validVec_3 = 1'h0;
tlbMG_m_validVec_4 = 1'h0;
tlbMG_m_validVec_5 = 1'h0;
tlbMG_m_validVec_6 = 1'h0;
tlbMG_m_validVec_7 = 1'h0;
tlbReqQ_data_0 = 1'h0;
tlbReqQ_empty_rl = 1'h0;
tlbReqQ_full_rl = 1'h0;
transCacheReqQ_data_0 = 1'h0;
transCacheReqQ_empty_rl = 1'h0;
transCacheReqQ_full_rl = 1'h0;
vm_info_D = 49'h0AAAAAAAAAAAA;
vm_info_I = 49'h0AAAAAAAAAAAA;
waitFlushDone = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doStartFlush &&
NOT_rqFromCQ_empty_dummy2_1_read__19_20_OR_NOT_ETC___d927)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doStartFlush &&
pendValid_0_dummy2_0_read__28_AND_pendValid_0__ETC___d936)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
SEL_ARR_pendWait_0_dummy2_0_read__770_AND_pend_ETC___d1834)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
IF_NOT_transCacheReqQ_data_0_768_769_OR_NOT_pe_ETC___d1822 &&
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_838__ETC___d1845)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("L2TLB start page walk: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("L2TlbRqFromC { ", "child: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788)
$write("tagged I ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
!SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788)
$write("tagged D ",
"'h%h",
CASE_transCacheReqQ_data_0_0_pendReq_0_BITS_28_ETC__q18);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write(", ", "vpn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("'h%h",
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1793,
" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write("; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write("VMInfo { ", "prv: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("'h%h", vm_info_prv__h133721);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write(", ", "asid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write("'h%h", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write(", ", "sv39: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 ?
!vm_info_I[46] :
!vm_info_D[46]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 ?
vm_info_I[46] :
vm_info_D[46]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write(", ", "exeReadable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 ?
!vm_info_I[45] :
!vm_info_D[45]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 ?
vm_info_I[45] :
vm_info_D[45]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write(", ", "userAccessibleByS: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 ?
!vm_info_I[44] :
!vm_info_D[44]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1788 ?
vm_info_I[44] :
vm_info_D[44]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write(", ", "basePPN: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("'h%h", rootPPN__h133423, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write("; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("TranslationCacheResp { ", "startLevel: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("'h%h", transCache$resp[45:44]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write(", ", "ppn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("'h%h", transCache$resp[43:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write("; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("'h%h", transCache$resp[45:44]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write("; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp)
$write("'h%h", pteAddr__h133425);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTranslationCacheResp) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp && iFlushReq && dFlushReq)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
CASE_tlbReqQ_data_0_0_pendWait_0_dummy2_1_read_ETC__q19)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("L2TLB resp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("VMInfo { ", "prv: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("'h%h", vm_info_prv__h116619);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "asid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("'h%h", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "sv39: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
!IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1112)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "exeReadable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 ?
!vm_info_I[45] :
!vm_info_D[45]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 ?
vm_info_I[45] :
vm_info_D[45]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "userAccessibleByS: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 ?
!vm_info_I[44] :
!vm_info_D[44]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105 ?
vm_info_I[44] :
vm_info_D[44]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "basePPN: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp)
$write("'h%h", vm_info_basePPN__h116624, " }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbResp) $write(" ; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("L2TlbRqFromC { ", "child: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105)
$write("tagged I ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
!SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1105)
$write("tagged D ",
"'h%h",
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1378);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "vpn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp)
$write("'h%h",
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1138,
" }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbResp) $write(" ; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("SetAssocTlbResp { ", "hit: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1087 &&
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
(tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_15_AN_ETC___d1380 ||
tlb4KB_m_tlbRam_3_bram$DOB[80] &&
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1088))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "way: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("'h%h", value__h117443);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "entry: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("TlbEntry { ", "vpn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp)
$write("'h%h",
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1384);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "ppn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp)
$write("'h%h",
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1391);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "pteType: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("PTEType { ", "dirty: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 &&
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1402)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1405)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "accessed: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 &&
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1415)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1418)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "global: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 &&
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1424)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1427)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "user: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 &&
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1437)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1440)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "executable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 &&
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1450)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1453)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "writable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 &&
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1463)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1466)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "readable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 &&
SEL_ARR_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14__ETC___d1476)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1479)
$write("True");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbResp) $write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "level: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("'h%h", x__h122416);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "asid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("'h%h", 1'b0, " }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbResp) $write(" }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbResp) $write(" ; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("FullAssocTlbResp { ", "hit: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1290 &&
(!tlbMG_m_validVec_7 ||
!IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
(tlbMG_m_validVec_0_123_AND_IF_tlbMG_m_entryVec_ETC___d1499 ||
tlbMG_m_validVec_7 &&
IF_tlbMG_m_entryVec_7_292_BITS_1_TO_0_293_EQ_0_ETC___d1301))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "index: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("'h%h", value__h119411);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "entry: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("TlbEntry { ", "vpn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp)
$write("'h%h",
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_79_TO_53_1_ETC___d1510);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "ppn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp)
$write("'h%h",
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_52_TO_9_51_ETC___d1521);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "pteType: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("PTEType { ", "dirty: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 &&
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_8_523_5_ETC___d1540)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1543)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "accessed: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 &&
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_7_544_5_ETC___d1561)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1564)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "global: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 &&
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_6_565_5_ETC___d1582)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1585)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "user: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 &&
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_5_586_5_ETC___d1603)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1606)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "executable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 &&
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_4_607_6_ETC___d1624)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1627)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "writable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 &&
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_3_628_6_ETC___d1645)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1648)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "readable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 &&
SEL_ARR_NOT_tlbMG_m_entryVec_0_125_BIT_2_649_6_ETC___d1666)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1669)
$write("True");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbResp) $write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "level: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp)
$write("'h%h",
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write(", ", "asid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp) $write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbResp) $write(" }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbResp) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
IF_NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tl_ETC___d1315 &&
(SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 ==
2'd0 ||
SEL_ARR_tlbMG_m_entryVec_0_125_BITS_1_TO_0_126_ETC___d1671 ==
2'd3))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbResp &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1677 &&
NOT_tlbMG_m_validVec_0_123_124_OR_NOT_IF_tlbMG_ETC___d1735)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk && iFlushReq && dFlushReq)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
IF_NOT_pendWait_0_dummy2_0_read__770_771_OR_NO_ETC___d1967 &&
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_838__ETC___d1970)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("L2TLB page walk: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("VMInfo { ", "prv: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("'h%h", vm_info_prv__h136979);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "asid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("'h%h", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "sv39: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d1872)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "exeReadable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 ?
!vm_info_I[45] :
!vm_info_D[45]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 ?
vm_info_I[45] :
vm_info_D[45]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "userAccessibleByS: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 ?
!vm_info_I[44] :
!vm_info_D[44]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
(SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871 ?
vm_info_I[44] :
vm_info_D[44]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "basePPN: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk)
$write("'h%h", vm_info_basePPN__h136984, " }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doPageWalk) $write(" ; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("'h%h", idx__h135713);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doPageWalk) $write(" ; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("L2TlbRqFromC { ", "child: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871)
$write("tagged I ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NOT_p_ETC___d1871)
$write("tagged D ",
"'h%h",
SEL_ARR_pendReq_0_097_BITS_28_TO_27_375_pendRe_ETC___d1990);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "vpn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk)
$write("'h%h",
SEL_ARR_pendReq_0_097_BITS_26_TO_0_135_pendReq_ETC___d1899,
" }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doPageWalk) $write(" ; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("'h%h", walkLevel__h136646);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doPageWalk) $write(" ; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("PTESv39 { ", "reserved: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk)
$write("'h%h",
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[63:54]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "ppn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk)
$write("'h%h",
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[53:10]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "reserved_sw: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk)
$write("'h%h",
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "pteType: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write("PTEType { ", "dirty: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[7])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[7])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "accessed: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[6])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[6])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "global: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[5])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "user: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[4])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[4])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "executable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "writable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "readable: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1])
$write("False");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doPageWalk) $write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk) $write(", ", "valid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
!SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doPageWalk) $write(" }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doPageWalk) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]) &&
NOT_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel__ETC___d2066)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2008 &&
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[0] &&
(SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[3] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[1] ||
SEL_ARR_respLdQ_data_0_864_BITS_64_TO_1_873_re_ETC___d1876[2]) &&
NOT_SEL_ARR_pendWalkLevel_0_886_pendWalkLevel__ETC___d2078)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doPageWalk &&
IF_SEL_ARR_NOT_pendReq_0_097_BIT_29_098_099_NO_ETC___d2194)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq &&
SEL_ARR_pendValid_0_dummy2_1_read__29_AND_IF_p_ETC___d1046)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq &&
CASE_v01631_0_pendWait_0_dummy2_1_read__047_AN_ETC__q20)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq) $write("L2TLB new req: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq) $write("L2TlbRqFromC { ", "child: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq &&
NOT_rqFromCQ_data_0_dummy2_1_read__003_040_OR__ETC___d1041)
$write("tagged I ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq && rqFromCQ_data_0_dummy2_1$Q_OUT &&
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471)
$write("tagged D ",
"'h%h",
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq) $write(", ", "vpn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq) $write("'h%h", vpn__h104314, " }");
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbReq) $write("; ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doTlbReq) $write("'h%h", v__h101631);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doTlbReq) $write("\n");
end
// synopsys translate_on
endmodule // mkL2Tlb
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