113f888d37
New method 'debug_external_interrupt_req' to support emulation of a debug module starts at P3_Core interface and is plumbed all the way in to the CSR register MIP as interrupt [14]. The corresponding MIE[14] is always 1, so it is never masked. Still todo: should not be masked by MSTATUS interrupt-enables either. Also expanded interrupt-detection logic, mcause etc. to extend up to interrupt 14. Builds in standalone mode, runs ISA tests. Builds in src_SSITH_P3, generating RTL.
87 lines
2.2 KiB
Verilog
87 lines
2.2 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// brAddrCalc O 64
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// brAddrCalc_pc I 64
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// brAddrCalc_val I 64
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// brAddrCalc_iType I 5
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// brAddrCalc_imm I 64
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// brAddrCalc_taken I 1
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//
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// Combinational paths from inputs to outputs:
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// (brAddrCalc_pc,
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// brAddrCalc_val,
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// brAddrCalc_iType,
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// brAddrCalc_imm,
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// brAddrCalc_taken) -> brAddrCalc
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_brAddrCalc(brAddrCalc_pc,
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brAddrCalc_val,
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brAddrCalc_iType,
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brAddrCalc_imm,
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brAddrCalc_taken,
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brAddrCalc);
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// value method brAddrCalc
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input [63 : 0] brAddrCalc_pc;
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input [63 : 0] brAddrCalc_val;
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input [4 : 0] brAddrCalc_iType;
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input [63 : 0] brAddrCalc_imm;
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input brAddrCalc_taken;
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output [63 : 0] brAddrCalc;
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// signals for module outputs
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reg [63 : 0] brAddrCalc;
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// remaining internal signals
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wire [63 : 0] brAddrCalc_pc_PLUS_brAddrCalc_imm___d2,
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brAddrCalc_val_PLUS_brAddrCalc_imm__q1,
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pcPlus4__h27;
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// value method brAddrCalc
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always@(brAddrCalc_iType or
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pcPlus4__h27 or
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brAddrCalc_pc_PLUS_brAddrCalc_imm___d2 or
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brAddrCalc_val_PLUS_brAddrCalc_imm__q1 or brAddrCalc_taken)
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begin
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case (brAddrCalc_iType)
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5'd8: brAddrCalc = brAddrCalc_pc_PLUS_brAddrCalc_imm___d2;
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5'd9:
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brAddrCalc = { brAddrCalc_val_PLUS_brAddrCalc_imm__q1[63:1], 1'b0 };
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5'd10:
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brAddrCalc =
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brAddrCalc_taken ?
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brAddrCalc_pc_PLUS_brAddrCalc_imm___d2 :
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pcPlus4__h27;
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default: brAddrCalc = pcPlus4__h27;
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endcase
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end
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// remaining internal signals
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assign brAddrCalc_pc_PLUS_brAddrCalc_imm___d2 =
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brAddrCalc_pc + brAddrCalc_imm ;
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assign brAddrCalc_val_PLUS_brAddrCalc_imm__q1 =
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brAddrCalc_val + brAddrCalc_imm ;
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assign pcPlus4__h27 = brAddrCalc_pc + 64'd4 ;
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endmodule // module_brAddrCalc
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