113f888d37
New method 'debug_external_interrupt_req' to support emulation of a debug module starts at P3_Core interface and is plumbed all the way in to the CSR register MIP as interrupt [14]. The corresponding MIE[14] is always 1, so it is never masked. Still todo: should not be masked by MSTATUS interrupt-enables either. Also expanded interrupt-detection logic, mcause etc. to extend up to interrupt 14. Builds in standalone mode, runs ISA tests. Builds in src_SSITH_P3, generating RTL.
80 lines
2.2 KiB
Verilog
80 lines
2.2 KiB
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
|
|
//
|
|
//
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// decodeBrPred O 65
|
|
// decodeBrPred_pc I 64
|
|
// decodeBrPred_dInst I 72
|
|
// decodeBrPred_histTaken I 1
|
|
//
|
|
// Combinational paths from inputs to outputs:
|
|
// (decodeBrPred_pc,
|
|
// decodeBrPred_dInst,
|
|
// decodeBrPred_histTaken) -> decodeBrPred
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module module_decodeBrPred(decodeBrPred_pc,
|
|
decodeBrPred_dInst,
|
|
decodeBrPred_histTaken,
|
|
decodeBrPred);
|
|
// value method decodeBrPred
|
|
input [63 : 0] decodeBrPred_pc;
|
|
input [71 : 0] decodeBrPred_dInst;
|
|
input decodeBrPred_histTaken;
|
|
output [64 : 0] decodeBrPred;
|
|
|
|
// signals for module outputs
|
|
wire [64 : 0] decodeBrPred;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2;
|
|
wire [63 : 0] imm_val__h23, jTarget__h43, pcPlus4__h22;
|
|
wire [31 : 0] decodeBrPred_dInst_BITS_31_TO_0__q1;
|
|
|
|
// value method decodeBrPred
|
|
assign decodeBrPred =
|
|
{ decodeBrPred_dInst[71:67] != 5'd9,
|
|
CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 } ;
|
|
|
|
// remaining internal signals
|
|
assign decodeBrPred_dInst_BITS_31_TO_0__q1 = decodeBrPred_dInst[31:0] ;
|
|
assign imm_val__h23 =
|
|
{ {32{decodeBrPred_dInst_BITS_31_TO_0__q1[31]}},
|
|
decodeBrPred_dInst_BITS_31_TO_0__q1 } ;
|
|
assign jTarget__h43 = decodeBrPred_pc + imm_val__h23 ;
|
|
assign pcPlus4__h22 = decodeBrPred_pc + 64'd4 ;
|
|
always@(decodeBrPred_dInst or
|
|
pcPlus4__h22 or jTarget__h43 or decodeBrPred_histTaken)
|
|
begin
|
|
case (decodeBrPred_dInst[71:67])
|
|
5'd8:
|
|
CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
|
|
jTarget__h43;
|
|
5'd10:
|
|
CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
|
|
decodeBrPred_histTaken ? jTarget__h43 : pcPlus4__h22;
|
|
default: CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
|
|
pcPlus4__h22;
|
|
endcase
|
|
end
|
|
endmodule // module_decodeBrPred
|
|
|