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Toooba/src_SSITH_P3/xilinx_ip/hdl/mkMMU_Cache.v
rsnikhil 113f888d37 Added support for 'debug_external_interrupt_req' 
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00

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319 KiB
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//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// valid O 1
// addr O 64 reg
// word64 O 64
// st_amo_val O 64
// exc O 1
// exc_code O 4 reg
// RDY_server_flush_request_put O 1 reg
// RDY_server_flush_response_get O 1
// RDY_tlb_flush O 1 const
// mem_master_awvalid O 1
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1
// mem_master_wid O 4 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1
// mem_master_arvalid O 1
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_op I 2
// req_f3 I 3
// req_amo_funct7 I 7 reg
// req_addr I 64
// req_st_value I 64
// req_priv I 2 reg
// req_sstatus_SUM I 1 reg
// req_mstatus_MXR I 1 reg
// req_satp I 64 reg
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// EN_set_verbosity I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
// EN_server_flush_request_put I 1
// EN_server_flush_response_get I 1
// EN_tlb_flush I 1
//
// Combinational paths from inputs to outputs:
// (mem_master_awready, mem_master_wready) -> valid
// (mem_master_awready, mem_master_wready) -> word64
// (mem_master_awready, mem_master_wready) -> st_amo_val
// (mem_master_awready, mem_master_wready) -> mem_master_bready
// (mem_master_awready,
// mem_master_wready,
// mem_master_arready,
// EN_req) -> mem_master_rready
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMMU_Cache(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_op,
req_f3,
req_amo_funct7,
req_addr,
req_st_value,
req_priv,
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
EN_req,
valid,
addr,
word64,
st_amo_val,
exc,
exc_code,
EN_server_flush_request_put,
RDY_server_flush_request_put,
EN_server_flush_response_get,
RDY_server_flush_response_get,
EN_tlb_flush,
RDY_tlb_flush,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready);
parameter [0 : 0] dmem_not_imem = 1'b0;
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [1 : 0] req_op;
input [2 : 0] req_f3;
input [6 : 0] req_amo_funct7;
input [63 : 0] req_addr;
input [63 : 0] req_st_value;
input [1 : 0] req_priv;
input req_sstatus_SUM;
input req_mstatus_MXR;
input [63 : 0] req_satp;
input EN_req;
// value method valid
output valid;
// value method addr
output [63 : 0] addr;
// value method word64
output [63 : 0] word64;
// value method st_amo_val
output [63 : 0] st_amo_val;
// value method exc
output exc;
// value method exc_code
output [3 : 0] exc_code;
// action method server_flush_request_put
input EN_server_flush_request_put;
output RDY_server_flush_request_put;
// action method server_flush_response_get
input EN_server_flush_response_get;
output RDY_server_flush_response_get;
// action method tlb_flush
input EN_tlb_flush;
output RDY_tlb_flush;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wid
output [3 : 0] mem_master_wid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// signals for module outputs
reg [63 : 0] word64;
wire [63 : 0] addr,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
st_amo_val;
wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb;
wire [3 : 0] exc_code,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion,
mem_master_wid;
wire [2 : 0] mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] mem_master_arburst, mem_master_awburst;
wire RDY_server_flush_request_put,
RDY_server_flush_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_verbosity,
RDY_tlb_flush,
exc,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid,
valid;
// inlined wires
reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1;
wire [10 : 0] crg_sb_to_load_delay$port0__write_1,
crg_sb_to_load_delay$port2__read;
wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1,
ctr_wr_rsps_pending_crg$port2__read,
ctr_wr_rsps_pending_crg$port3__read;
wire crg_sb_to_load_delay$EN_port1__write,
ctr_wr_rsps_pending_crg$EN_port0__write,
ctr_wr_rsps_pending_crg$EN_port2__write,
dw_valid$whas,
master_xactor_crg_rd_addr_full$EN_port0__write,
master_xactor_crg_rd_addr_full$EN_port1__write,
master_xactor_crg_rd_addr_full$EN_port2__write,
master_xactor_crg_rd_addr_full$port1__read,
master_xactor_crg_rd_addr_full$port2__read,
master_xactor_crg_rd_addr_full$port3__read,
master_xactor_crg_rd_data_full$EN_port0__write,
master_xactor_crg_rd_data_full$EN_port1__write,
master_xactor_crg_rd_data_full$EN_port2__write,
master_xactor_crg_rd_data_full$port1__read,
master_xactor_crg_rd_data_full$port2__read,
master_xactor_crg_rd_data_full$port3__read,
master_xactor_crg_wr_addr_full$EN_port0__write,
master_xactor_crg_wr_addr_full$EN_port1__write,
master_xactor_crg_wr_addr_full$EN_port2__write,
master_xactor_crg_wr_addr_full$port1__read,
master_xactor_crg_wr_addr_full$port2__read,
master_xactor_crg_wr_addr_full$port3__read,
master_xactor_crg_wr_data_full$EN_port0__write,
master_xactor_crg_wr_data_full$EN_port1__write,
master_xactor_crg_wr_data_full$EN_port2__write,
master_xactor_crg_wr_data_full$port1__read,
master_xactor_crg_wr_data_full$port2__read,
master_xactor_crg_wr_data_full$port3__read,
master_xactor_crg_wr_resp_full$EN_port0__write,
master_xactor_crg_wr_resp_full$EN_port1__write,
master_xactor_crg_wr_resp_full$EN_port2__write,
master_xactor_crg_wr_resp_full$port1__read,
master_xactor_crg_wr_resp_full$port2__read,
master_xactor_crg_wr_resp_full$port3__read;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register crg_sb_to_load_delay
reg [10 : 0] crg_sb_to_load_delay;
wire [10 : 0] crg_sb_to_load_delay$D_IN;
wire crg_sb_to_load_delay$EN;
// register ctr_wr_rsps_pending_crg
reg [3 : 0] ctr_wr_rsps_pending_crg;
wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
wire ctr_wr_rsps_pending_crg$EN;
// register master_xactor_crg_rd_addr_full
reg master_xactor_crg_rd_addr_full;
wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN;
// register master_xactor_crg_rd_data_full
reg master_xactor_crg_rd_data_full;
wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN;
// register master_xactor_crg_wr_addr_full
reg master_xactor_crg_wr_addr_full;
wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN;
// register master_xactor_crg_wr_data_full
reg master_xactor_crg_wr_data_full;
wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN;
// register master_xactor_crg_wr_resp_full
reg master_xactor_crg_wr_resp_full;
wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN;
// register master_xactor_rg_rd_addr
reg [96 : 0] master_xactor_rg_rd_addr;
reg [96 : 0] master_xactor_rg_rd_addr$D_IN;
wire master_xactor_rg_rd_addr$EN;
// register master_xactor_rg_rd_data
reg [70 : 0] master_xactor_rg_rd_data;
wire [70 : 0] master_xactor_rg_rd_data$D_IN;
wire master_xactor_rg_rd_data$EN;
// register master_xactor_rg_wr_addr
reg [96 : 0] master_xactor_rg_wr_addr;
reg [96 : 0] master_xactor_rg_wr_addr$D_IN;
wire master_xactor_rg_wr_addr$EN;
// register master_xactor_rg_wr_data
reg [76 : 0] master_xactor_rg_wr_data;
reg [76 : 0] master_xactor_rg_wr_data$D_IN;
wire master_xactor_rg_wr_data$EN;
// register master_xactor_rg_wr_resp
reg [5 : 0] master_xactor_rg_wr_resp;
wire [5 : 0] master_xactor_rg_wr_resp$D_IN;
wire master_xactor_rg_wr_resp$EN;
// register rg_addr
reg [63 : 0] rg_addr;
wire [63 : 0] rg_addr$D_IN;
wire rg_addr$EN;
// register rg_amo_funct7
reg [6 : 0] rg_amo_funct7;
wire [6 : 0] rg_amo_funct7$D_IN;
wire rg_amo_funct7$EN;
// register rg_cset_in_cache
reg [5 : 0] rg_cset_in_cache;
wire [5 : 0] rg_cset_in_cache$D_IN;
wire rg_cset_in_cache$EN;
// register rg_error_during_refill
reg rg_error_during_refill;
wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;
// register rg_exc_code
reg [3 : 0] rg_exc_code;
reg [3 : 0] rg_exc_code$D_IN;
wire rg_exc_code$EN;
// register rg_f3
reg [2 : 0] rg_f3;
wire [2 : 0] rg_f3$D_IN;
wire rg_f3$EN;
// register rg_ld_val
reg [63 : 0] rg_ld_val;
reg [63 : 0] rg_ld_val$D_IN;
wire rg_ld_val$EN;
// register rg_lower_word32
reg [31 : 0] rg_lower_word32;
wire [31 : 0] rg_lower_word32$D_IN;
wire rg_lower_word32$EN;
// register rg_lower_word32_full
reg rg_lower_word32_full;
wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;
// register rg_lrsc_pa
reg [63 : 0] rg_lrsc_pa;
wire [63 : 0] rg_lrsc_pa$D_IN;
wire rg_lrsc_pa$EN;
// register rg_lrsc_valid
reg rg_lrsc_valid;
wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;
// register rg_mstatus_MXR
reg rg_mstatus_MXR;
wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;
// register rg_op
reg [1 : 0] rg_op;
wire [1 : 0] rg_op$D_IN;
wire rg_op$EN;
// register rg_pa
reg [63 : 0] rg_pa;
wire [63 : 0] rg_pa$D_IN;
wire rg_pa$EN;
// register rg_priv
reg [1 : 0] rg_priv;
wire [1 : 0] rg_priv$D_IN;
wire rg_priv$EN;
// register rg_pte_pa
reg [63 : 0] rg_pte_pa;
reg [63 : 0] rg_pte_pa$D_IN;
wire rg_pte_pa$EN;
// register rg_req_byte_in_cline
reg [63 : 0] rg_req_byte_in_cline;
wire [63 : 0] rg_req_byte_in_cline$D_IN;
wire rg_req_byte_in_cline$EN;
// register rg_requesting_cline
reg rg_requesting_cline;
reg rg_requesting_cline$D_IN;
wire rg_requesting_cline$EN;
// register rg_satp
reg [63 : 0] rg_satp;
wire [63 : 0] rg_satp$D_IN;
wire rg_satp$EN;
// register rg_sstatus_SUM
reg rg_sstatus_SUM;
wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;
// register rg_st_amo_val
reg [63 : 0] rg_st_amo_val;
wire [63 : 0] rg_st_amo_val$D_IN;
wire rg_st_amo_val$EN;
// register rg_state
reg [4 : 0] rg_state;
reg [4 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_word64_set_in_cache
reg [8 : 0] rg_word64_set_in_cache;
wire [8 : 0] rg_word64_set_in_cache$D_IN;
wire rg_word64_set_in_cache$EN;
// ports of submodule f_pte_writebacks
wire [127 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT;
wire f_pte_writebacks$CLR,
f_pte_writebacks$DEQ,
f_pte_writebacks$EMPTY_N,
f_pte_writebacks$ENQ,
f_pte_writebacks$FULL_N;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule ram_state_and_ctag_cset
wire [52 : 0] ram_state_and_ctag_cset$DIA,
ram_state_and_ctag_cset$DIB,
ram_state_and_ctag_cset$DOB;
wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
wire ram_state_and_ctag_cset$ENA,
ram_state_and_ctag_cset$ENB,
ram_state_and_ctag_cset$WEA,
ram_state_and_ctag_cset$WEB;
// ports of submodule ram_word64_set
reg [63 : 0] ram_word64_set$DIB;
reg [8 : 0] ram_word64_set$ADDRB;
wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB;
wire [8 : 0] ram_word64_set$ADDRA;
wire ram_word64_set$ENA,
ram_word64_set$ENB,
ram_word64_set$WEA,
ram_word64_set$WEB;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
wire soc_map$m_is_mem_addr;
// ports of submodule tlb
reg [1 : 0] tlb$insert_level;
wire [130 : 0] tlb$lookup;
wire [63 : 0] tlb$insert_pte, tlb$insert_pte_pa;
wire [26 : 0] tlb$insert_vpn, tlb$lookup_vpn;
wire [15 : 0] tlb$insert_asid, tlb$lookup_asid;
wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup;
// rule scheduling signals
wire CAN_FIRE_RL_rl_ST_AMO_response,
CAN_FIRE_RL_rl_cache_refill_req_loop,
CAN_FIRE_RL_rl_cache_refill_rsps_loop,
CAN_FIRE_RL_rl_discard_write_rsp,
CAN_FIRE_RL_rl_drive_exception_rsp,
CAN_FIRE_RL_rl_io_AMO_SC_req,
CAN_FIRE_RL_rl_io_AMO_op_req,
CAN_FIRE_RL_rl_io_AMO_read_rsp,
CAN_FIRE_RL_rl_io_read_req,
CAN_FIRE_RL_rl_io_read_rsp,
CAN_FIRE_RL_rl_io_write_req,
CAN_FIRE_RL_rl_maintain_io_read_rsp,
CAN_FIRE_RL_rl_probe_and_immed_rsp,
CAN_FIRE_RL_rl_ptw_level_0,
CAN_FIRE_RL_rl_ptw_level_1,
CAN_FIRE_RL_rl_ptw_level_2,
CAN_FIRE_RL_rl_rereq,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_shift_sb_to_load_delay,
CAN_FIRE_RL_rl_start_cache_refill,
CAN_FIRE_RL_rl_start_reset,
CAN_FIRE_RL_rl_start_tlb_refill,
CAN_FIRE_RL_rl_writeback_updated_PTE,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_req,
CAN_FIRE_server_flush_request_put,
CAN_FIRE_server_flush_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_verbosity,
CAN_FIRE_tlb_flush,
WILL_FIRE_RL_rl_ST_AMO_response,
WILL_FIRE_RL_rl_cache_refill_req_loop,
WILL_FIRE_RL_rl_cache_refill_rsps_loop,
WILL_FIRE_RL_rl_discard_write_rsp,
WILL_FIRE_RL_rl_drive_exception_rsp,
WILL_FIRE_RL_rl_io_AMO_SC_req,
WILL_FIRE_RL_rl_io_AMO_op_req,
WILL_FIRE_RL_rl_io_AMO_read_rsp,
WILL_FIRE_RL_rl_io_read_req,
WILL_FIRE_RL_rl_io_read_rsp,
WILL_FIRE_RL_rl_io_write_req,
WILL_FIRE_RL_rl_maintain_io_read_rsp,
WILL_FIRE_RL_rl_probe_and_immed_rsp,
WILL_FIRE_RL_rl_ptw_level_0,
WILL_FIRE_RL_rl_ptw_level_1,
WILL_FIRE_RL_rl_ptw_level_2,
WILL_FIRE_RL_rl_rereq,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_shift_sb_to_load_delay,
WILL_FIRE_RL_rl_start_cache_refill,
WILL_FIRE_RL_rl_start_reset,
WILL_FIRE_RL_rl_start_tlb_refill,
WILL_FIRE_RL_rl_writeback_updated_PTE,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_req,
WILL_FIRE_server_flush_request_put,
WILL_FIRE_server_flush_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_verbosity,
WILL_FIRE_tlb_flush;
// inputs to muxes for submodule ports
wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1,
MUX_master_xactor_rg_rd_addr$write_1__VAL_2,
MUX_master_xactor_rg_rd_addr$write_1__VAL_3,
MUX_master_xactor_rg_rd_addr$write_1__VAL_4,
MUX_master_xactor_rg_rd_addr$write_1__VAL_5,
MUX_master_xactor_rg_rd_addr$write_1__VAL_6,
MUX_master_xactor_rg_wr_addr$write_1__VAL_1,
MUX_master_xactor_rg_wr_addr$write_1__VAL_2,
MUX_master_xactor_rg_wr_addr$write_1__VAL_4;
wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1,
MUX_master_xactor_rg_wr_data$write_1__VAL_2,
MUX_master_xactor_rg_wr_data$write_1__VAL_3,
MUX_master_xactor_rg_wr_data$write_1__VAL_4;
wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
MUX_ram_word64_set$a_put_3__VAL_2,
MUX_rg_ld_val$write_1__VAL_2,
MUX_rg_req_byte_in_cline$write_1__VAL_1;
wire [52 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2,
MUX_ram_word64_set$b_put_2__VAL_4;
wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
wire [4 : 0] MUX_rg_state$write_1__VAL_10,
MUX_rg_state$write_1__VAL_11,
MUX_rg_state$write_1__VAL_12,
MUX_rg_state$write_1__VAL_13,
MUX_rg_state$write_1__VAL_14,
MUX_rg_state$write_1__VAL_2,
MUX_rg_state$write_1__VAL_6;
wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1,
MUX_rg_exc_code$write_1__VAL_1,
MUX_rg_exc_code$write_1__VAL_6;
wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1,
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2,
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3,
MUX_dw_output_ld_val$wset_1__SEL_1,
MUX_dw_output_ld_val$wset_1__SEL_3,
MUX_dw_output_ld_val$wset_1__SEL_4,
MUX_master_xactor_rg_rd_addr$write_1__PSEL_1,
MUX_master_xactor_rg_rd_addr$write_1__PSEL_2,
MUX_master_xactor_rg_rd_addr$write_1__SEL_1,
MUX_master_xactor_rg_rd_addr$write_1__SEL_2,
MUX_master_xactor_rg_rd_addr$write_1__SEL_3,
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1,
MUX_ram_word64_set$a_put_1__SEL_1,
MUX_ram_word64_set$b_put_1__SEL_2,
MUX_rg_error_during_refill$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_2,
MUX_rg_exc_code$write_1__SEL_3,
MUX_rg_exc_code$write_1__SEL_5,
MUX_rg_exc_code$write_1__SEL_6,
MUX_rg_exc_code$write_1__SEL_7,
MUX_rg_exc_code$write_1__SEL_8,
MUX_rg_ld_val$write_1__SEL_2,
MUX_rg_lrsc_valid$write_1__SEL_2,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_11,
MUX_rg_state$write_1__SEL_18,
MUX_rg_state$write_1__SEL_3,
MUX_tlb$insert_1__SEL_1,
MUX_tlb$insert_1__SEL_2,
MUX_tlb$insert_1__SEL_3,
MUX_tlb$insert_1__SEL_4;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4901;
reg [31 : 0] v__h5002;
reg [31 : 0] v__h31277;
reg [31 : 0] v__h32175;
reg [31 : 0] v__h4532;
reg [31 : 0] v__h24418;
reg [31 : 0] v__h24175;
reg [31 : 0] v__h24729;
reg [31 : 0] v__h24841;
reg [31 : 0] v__h24347;
reg [31 : 0] v__h25475;
reg [31 : 0] v__h25235;
reg [31 : 0] v__h25898;
reg [31 : 0] v__h25786;
reg [31 : 0] v__h25404;
reg [31 : 0] v__h26370;
reg [31 : 0] v__h26441;
reg [31 : 0] v__h26523;
reg [31 : 0] v__h26299;
reg [31 : 0] v__h27433;
reg [31 : 0] v__h5455;
reg [31 : 0] v__h15164;
reg [31 : 0] v__h19383;
reg [31 : 0] v__h18808;
reg [31 : 0] v__h22819;
reg [31 : 0] v__h27770;
reg [31 : 0] v__h27992;
reg [31 : 0] v__h29965;
reg [31 : 0] v__h31065;
reg [31 : 0] v__h31172;
reg [31 : 0] v__h31357;
reg [31 : 0] v__h31879;
reg [31 : 0] v__h32293;
reg [31 : 0] v__h3875;
reg [31 : 0] v__h32611;
reg [31 : 0] v__h32786;
reg [31 : 0] v__h35399;
reg [31 : 0] v__h35651;
reg [31 : 0] v__h32882;
reg [31 : 0] v__h23455;
reg [31 : 0] v__h26650;
reg [31 : 0] v__h29591;
reg [31 : 0] v__h36621;
reg [31 : 0] v__h37775;
reg [31 : 0] v__h36271;
reg [31 : 0] v__h36232;
reg [31 : 0] v__h3869;
reg [31 : 0] v__h4526;
reg [31 : 0] v__h4895;
reg [31 : 0] v__h4996;
reg [31 : 0] v__h5449;
reg [31 : 0] v__h15158;
reg [31 : 0] v__h18802;
reg [31 : 0] v__h19377;
reg [31 : 0] v__h22813;
reg [31 : 0] v__h23449;
reg [31 : 0] v__h24169;
reg [31 : 0] v__h24341;
reg [31 : 0] v__h24412;
reg [31 : 0] v__h24723;
reg [31 : 0] v__h24835;
reg [31 : 0] v__h25229;
reg [31 : 0] v__h25398;
reg [31 : 0] v__h25469;
reg [31 : 0] v__h25780;
reg [31 : 0] v__h25892;
reg [31 : 0] v__h26293;
reg [31 : 0] v__h26364;
reg [31 : 0] v__h26435;
reg [31 : 0] v__h26517;
reg [31 : 0] v__h26644;
reg [31 : 0] v__h27427;
reg [31 : 0] v__h27764;
reg [31 : 0] v__h27986;
reg [31 : 0] v__h29585;
reg [31 : 0] v__h29959;
reg [31 : 0] v__h31059;
reg [31 : 0] v__h31166;
reg [31 : 0] v__h31271;
reg [31 : 0] v__h31351;
reg [31 : 0] v__h31873;
reg [31 : 0] v__h32169;
reg [31 : 0] v__h32287;
reg [31 : 0] v__h32605;
reg [31 : 0] v__h32780;
reg [31 : 0] v__h32876;
reg [31 : 0] v__h35393;
reg [31 : 0] v__h35645;
reg [31 : 0] v__h36226;
reg [31 : 0] v__h36265;
reg [31 : 0] v__h36615;
reg [31 : 0] v__h37769;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result0845_0x4_re_ETC__q34,
CASE_rg_addr_BITS_2_TO_0_0x0_result0910_0x4_re_ETC__q35,
CASE_rg_addr_BITS_2_TO_0_0x0_result4985_0x4_re_ETC__q30,
CASE_rg_addr_BITS_2_TO_0_0x0_result5001_0x4_re_ETC__q50,
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q33,
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q52,
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672,
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681,
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737,
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1174,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1166,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544,
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690,
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755,
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630,
_theResult_____2__h19912,
_theResult_____2__h33206,
_theResult___fst__h6847,
ld_val__h30074,
mem_req_wr_data_wdata__h19184,
mem_req_wr_data_wdata__h22620,
mem_req_wr_data_wdata__h31680,
mem_req_wr_data_wdata__h33184,
new_ld_val__h32912,
new_value__h17899,
new_value__h7872,
w1__h19904,
w1__h33194,
w1__h33198;
reg [7 : 0] mem_req_wr_data_wstrb__h19185, mem_req_wr_data_wstrb__h33185;
reg [2 : 0] value__h32497, value__h35523;
reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29,
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285,
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211,
IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245,
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225,
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297;
wire [63 : 0] IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1309,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563,
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694,
IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787,
_theResult___fst__h19116,
_theResult___fst__h22552,
_theResult___fst__h31612,
_theResult___fst__h33116,
_theResult___snd_fst__h6474,
_theResult___snd_fst__h6545,
_theResult___snd_fst__h7076,
_theResult___snd_snd_fst__h6476,
_theResult___snd_snd_fst__h6547,
cline_addr__h27485,
cline_fabric_addr__h27486,
lev_0_pte_pa__h25507,
lev_0_pte_pa_w64_fa__h25509,
lev_1_PTN_pa__h24448,
lev_1_pte_pa__h24450,
lev_1_pte_pa_w64_fa__h24452,
lev_2_pte_pa__h23508,
lev_2_pte_pa_w64_fa__h23510,
new_st_val__h19634,
new_st_val__h19916,
new_st_val__h20007,
new_st_val__h20987,
new_st_val__h20991,
new_st_val__h20995,
new_st_val__h20999,
new_st_val__h21004,
new_st_val__h21010,
new_st_val__h21015,
new_st_val__h33210,
new_st_val__h33301,
new_st_val__h35161,
new_st_val__h35165,
new_st_val__h35169,
new_st_val__h35173,
new_st_val__h35178,
new_st_val__h35184,
new_st_val__h35189,
pa___1__h6853,
pa___1__h6902,
pa___1__h6971,
pte___1__h7125,
pte___1__h7153,
pte___2__h6845,
result__h14281,
result__h14309,
result__h14337,
result__h14365,
result__h14393,
result__h14421,
result__h14449,
result__h14494,
result__h14522,
result__h14550,
result__h14578,
result__h14606,
result__h14634,
result__h14662,
result__h14690,
result__h14735,
result__h14763,
result__h14791,
result__h14819,
result__h14860,
result__h14888,
result__h14916,
result__h14944,
result__h14985,
result__h15013,
result__h15052,
result__h15080,
result__h30134,
result__h30164,
result__h30191,
result__h30218,
result__h30245,
result__h30272,
result__h30299,
result__h30326,
result__h30370,
result__h30397,
result__h30424,
result__h30451,
result__h30478,
result__h30505,
result__h30532,
result__h30559,
result__h30603,
result__h30630,
result__h30657,
result__h30684,
result__h30724,
result__h30751,
result__h30778,
result__h30805,
result__h30845,
result__h30872,
result__h30910,
result__h30937,
result__h33389,
result__h34297,
result__h34325,
result__h34353,
result__h34381,
result__h34409,
result__h34437,
result__h34465,
result__h34510,
result__h34538,
result__h34566,
result__h34594,
result__h34622,
result__h34650,
result__h34678,
result__h34706,
result__h34751,
result__h34779,
result__h34807,
result__h34835,
result__h34876,
result__h34904,
result__h34932,
result__h34960,
result__h35001,
result__h35029,
result__h35068,
result__h35096,
result__h7925,
satp_pa__h2578,
st_val__h32924,
value__h7170,
vpn_0_pa__h25506,
vpn_1_pa__h24449,
vpn_2_pa__h23507,
w1___1__h19975,
w1___1__h33269,
w2___1__h33270,
w2__h33200,
word64__h7691,
x1_avValue_pa__h6383,
x__h15551,
y__h7961;
wire [55 : 0] x__h24553, x__h5575, x__h6856, x__h6905, x__h6974;
wire [31 : 0] ld_val0074_BITS_31_TO_0__q38,
ld_val0074_BITS_63_TO_32__q45,
master_xactor_rg_rd_data_BITS_34_TO_3__q3,
master_xactor_rg_rd_data_BITS_66_TO_35__q10,
new_value872_BITS_31_TO_0__q32,
rg_st_amo_val_BITS_31_TO_0__q31,
w13194_BITS_31_TO_0__q51,
word64691_BITS_31_TO_0__q17,
word64691_BITS_63_TO_32__q24;
wire [15 : 0] ld_val0074_BITS_15_TO_0__q37,
ld_val0074_BITS_31_TO_16__q41,
ld_val0074_BITS_47_TO_32__q44,
ld_val0074_BITS_63_TO_48__q48,
master_xactor_rg_rd_data_BITS_18_TO_3__q2,
master_xactor_rg_rd_data_BITS_34_TO_19__q7,
master_xactor_rg_rd_data_BITS_50_TO_35__q9,
master_xactor_rg_rd_data_BITS_66_TO_51__q13,
word64691_BITS_15_TO_0__q16,
word64691_BITS_31_TO_16__q20,
word64691_BITS_47_TO_32__q23,
word64691_BITS_63_TO_48__q27;
wire [7 : 0] ld_val0074_BITS_15_TO_8__q39,
ld_val0074_BITS_23_TO_16__q40,
ld_val0074_BITS_31_TO_24__q42,
ld_val0074_BITS_39_TO_32__q43,
ld_val0074_BITS_47_TO_40__q46,
ld_val0074_BITS_55_TO_48__q47,
ld_val0074_BITS_63_TO_56__q49,
ld_val0074_BITS_7_TO_0__q36,
master_xactor_rg_rd_data_BITS_10_TO_3__q1,
master_xactor_rg_rd_data_BITS_18_TO_11__q4,
master_xactor_rg_rd_data_BITS_26_TO_19__q6,
master_xactor_rg_rd_data_BITS_34_TO_27__q5,
master_xactor_rg_rd_data_BITS_42_TO_35__q8,
master_xactor_rg_rd_data_BITS_50_TO_43__q11,
master_xactor_rg_rd_data_BITS_58_TO_51__q12,
master_xactor_rg_rd_data_BITS_66_TO_59__q14,
strobe64__h19115,
strobe64__h19118,
strobe64__h19121,
strobe64__h33115,
strobe64__h33118,
strobe64__h33121,
word64691_BITS_15_TO_8__q18,
word64691_BITS_23_TO_16__q19,
word64691_BITS_31_TO_24__q21,
word64691_BITS_39_TO_32__q22,
word64691_BITS_47_TO_40__q25,
word64691_BITS_55_TO_48__q26,
word64691_BITS_63_TO_56__q28,
word64691_BITS_7_TO_0__q15;
wire [5 : 0] shift_bits__h18980, shift_bits__h32980;
wire [4 : 0] IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399,
IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398,
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401;
wire [3 : 0] access_exc_code__h3321,
b__h23409,
exc_code___1__h6745,
x1_avValue_exc_code__h6384;
wire IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293,
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217,
IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305,
IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304,
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435,
NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284,
NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289,
NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292,
NOT_cfg_verbosity_read__8_ULE_2_060___d1061,
NOT_cfg_verbosity_read__8_ULT_2_05___d406,
NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341,
NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874,
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878,
NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921,
NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984,
NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928,
NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990,
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199,
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437,
NOT_req_f3_BITS_1_TO_0_399_EQ_0b0_400_401_AND__ETC___d1420,
NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294,
NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392,
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446,
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634,
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761,
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853,
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858,
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864,
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872,
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632,
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759,
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819,
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825,
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831,
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837,
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348,
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371,
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409,
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876,
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880,
NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123,
NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139,
cfg_verbosity_read__8_ULE_1___d19,
dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343,
dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100,
lrsc_result__h15541,
master_xactor_crg_rd_data_full_port1__read__96_ETC___d1232,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971,
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975,
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178,
ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438,
req_f3_BITS_1_TO_0_399_EQ_0b0_400_OR_req_f3_BI_ETC___d1429,
rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613,
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234,
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387,
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424,
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449,
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453,
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588,
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607,
rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447,
rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635,
rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762,
rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767,
rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248,
rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117,
rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130,
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126,
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309,
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356,
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378,
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395,
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396,
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414,
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417,
rg_priv_9_ULE_0b1___d60,
rg_state_3_EQ_13_098_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1100,
rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316,
tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106,
tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350,
y__h6671;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas ;
// value method addr
assign addr = rg_addr ;
// value method word64
always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
ld_val__h30074 or
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
new_ld_val__h32912 or
MUX_dw_output_ld_val$wset_1__SEL_3 or
MUX_dw_output_ld_val$wset_1__VAL_3 or
MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h30074;
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
word64 = new_ld_val__h32912;
MUX_dw_output_ld_val$wset_1__SEL_3:
word64 = MUX_dw_output_ld_val$wset_1__VAL_3;
MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val;
default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// value method st_amo_val
assign st_amo_val =
MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ;
// value method exc
assign exc = rg_state == 5'd4 ;
// value method exc_code
assign exc_code = rg_exc_code ;
// action method server_flush_request_put
assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;
// action method server_flush_response_get
assign RDY_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;
// action method tlb_flush
assign RDY_tlb_flush = 1'd1 ;
assign CAN_FIRE_tlb_flush = 1'd1 ;
assign WILL_FIRE_tlb_flush = EN_tlb_flush ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = master_xactor_crg_wr_addr_full$port1__read ;
// value method mem_master_m_awid
assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ;
// value method mem_master_m_awlen
assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ;
// value method mem_master_m_awsize
assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ;
// value method mem_master_m_awburst
assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ;
// value method mem_master_m_awlock
assign mem_master_awlock = master_xactor_rg_wr_addr[15] ;
// value method mem_master_m_awcache
assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ;
// value method mem_master_m_awprot
assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ;
// value method mem_master_m_awqos
assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ;
// value method mem_master_m_awregion
assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = master_xactor_crg_wr_data_full$port1__read ;
// value method mem_master_m_wid
assign mem_master_wid = master_xactor_rg_wr_data[76:73] ;
// value method mem_master_m_wdata
assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ;
// value method mem_master_m_wlast
assign mem_master_wlast = master_xactor_rg_wr_data[0] ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = master_xactor_crg_rd_addr_full$port1__read ;
// value method mem_master_m_arid
assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ;
// value method mem_master_m_araddr
assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ;
// value method mem_master_m_arlen
assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ;
// value method mem_master_m_arsize
assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ;
// value method mem_master_m_arburst
assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ;
// value method mem_master_m_arlock
assign mem_master_arlock = master_xactor_rg_rd_addr[15] ;
// value method mem_master_m_arcache
assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ;
// value method mem_master_m_arprot
assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ;
// value method mem_master_m_arqos
assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ;
// value method mem_master_m_arregion
assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ;
// submodule f_pte_writebacks
FIFO2 #(.width(32'd128), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N),
.CLK(CLK),
.D_IN(f_pte_writebacks$D_IN),
.ENQ(f_pte_writebacks$ENQ),
.DEQ(f_pte_writebacks$DEQ),
.CLR(f_pte_writebacks$CLR),
.D_OUT(f_pte_writebacks$D_OUT),
.FULL_N(f_pte_writebacks$FULL_N),
.EMPTY_N(f_pte_writebacks$EMPTY_N));
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule ram_state_and_ctag_cset
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd6),
.DATA_WIDTH(32'd53),
.MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_state_and_ctag_cset$ADDRA),
.ADDRB(ram_state_and_ctag_cset$ADDRB),
.DIA(ram_state_and_ctag_cset$DIA),
.DIB(ram_state_and_ctag_cset$DIB),
.WEA(ram_state_and_ctag_cset$WEA),
.WEB(ram_state_and_ctag_cset$WEB),
.ENA(ram_state_and_ctag_cset$ENA),
.ENB(ram_state_and_ctag_cset$ENB),
.DOA(),
.DOB(ram_state_and_ctag_cset$DOB));
// submodule ram_word64_set
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd64),
.MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_word64_set$ADDRA),
.ADDRB(ram_word64_set$ADDRB),
.DIA(ram_word64_set$DIA),
.DIB(ram_word64_set$DIB),
.WEA(ram_word64_set$WEA),
.WEB(ram_word64_set$WEB),
.ENA(ram_word64_set$ENA),
.ENB(ram_word64_set$ENB),
.DOA(),
.DOB(ram_word64_set$DOB));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_flash_mem_addr_base(),
.m_flash_mem_addr_size(),
.m_flash_mem_addr_lim(),
.m_ethernet_0_addr_base(),
.m_ethernet_0_addr_size(),
.m_ethernet_0_addr_lim(),
.m_dma_0_addr_base(),
.m_dma_0_addr_size(),
.m_dma_0_addr_lim(),
.m_uart16550_0_addr_base(),
.m_uart16550_0_addr_size(),
.m_uart16550_0_addr_lim(),
.m_gpio_0_addr_base(),
.m_gpio_0_addr_size(),
.m_gpio_0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_ddr4_0_uncached_addr_base(),
.m_ddr4_0_uncached_addr_size(),
.m_ddr4_0_uncached_addr_lim(),
.m_ddr4_0_cached_addr_base(),
.m_ddr4_0_cached_addr_size(),
.m_ddr4_0_cached_addr_lim(),
.m_is_mem_addr(soc_map$m_is_mem_addr),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// submodule tlb
mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK),
.RST_N(RST_N),
.insert_asid(tlb$insert_asid),
.insert_level(tlb$insert_level),
.insert_pte(tlb$insert_pte),
.insert_pte_pa(tlb$insert_pte_pa),
.insert_vpn(tlb$insert_vpn),
.lookup_asid(tlb$lookup_asid),
.lookup_vpn(tlb$lookup_vpn),
.EN_flush(tlb$EN_flush),
.EN_insert(tlb$EN_insert),
.RDY_flush(),
.lookup(tlb$lookup),
.RDY_lookup(tlb$RDY_lookup),
.RDY_insert(tlb$RDY_insert));
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset =
(rg_cset_in_cache != 6'd63 ||
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
rg_state == 5'd1 ;
assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;
// rule RL_rl_shift_sb_to_load_delay
assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ;
assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ;
// rule RL_rl_rereq
assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ;
assign WILL_FIRE_RL_rl_rereq =
CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;
// rule RL_rl_ST_AMO_response
assign CAN_FIRE_RL_rl_ST_AMO_response = WILL_FIRE_RL_rl_ST_AMO_response ;
assign WILL_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ;
// rule RL_rl_maintain_io_read_rsp
assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ;
assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
CAN_FIRE_RL_rl_maintain_io_read_rsp ;
// rule RL_rl_io_AMO_SC_req
assign CAN_FIRE_RL_rl_io_AMO_SC_req =
rg_state == 5'd13 && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_SC_req =
CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_drive_exception_rsp
assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
// rule RL_rl_start_reset
assign CAN_FIRE_RL_rl_start_reset =
f_reset_reqs$EMPTY_N && rg_state != 5'd1 ;
assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ;
// rule RL_rl_ptw_level_2
assign CAN_FIRE_RL_rl_ptw_level_2 =
master_xactor_crg_rd_data_full$port1__read &&
NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921 &&
rg_state == 5'd6 ;
assign WILL_FIRE_RL_rl_ptw_level_2 =
MUX_master_xactor_rg_rd_addr$write_1__PSEL_1 ;
// rule RL_rl_ptw_level_1
assign CAN_FIRE_RL_rl_ptw_level_1 =
master_xactor_crg_rd_data_full$port1__read &&
NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984 &&
rg_state == 5'd7 ;
assign WILL_FIRE_RL_rl_ptw_level_1 =
MUX_master_xactor_rg_rd_addr$write_1__PSEL_2 ;
// rule RL_rl_ptw_level_0
assign CAN_FIRE_RL_rl_ptw_level_0 =
master_xactor_crg_rd_data_full$port1__read &&
(master_xactor_rg_rd_data[2:1] != 2'b0 ||
!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] ||
!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] ||
tlb$RDY_insert) &&
rg_state == 5'd8 ;
assign WILL_FIRE_RL_rl_ptw_level_0 =
CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_cache_refill_req_loop
assign CAN_FIRE_RL_rl_cache_refill_req_loop =
!master_xactor_crg_rd_addr_full$port2__read &&
rg_requesting_cline ;
assign WILL_FIRE_RL_rl_cache_refill_req_loop =
CAN_FIRE_RL_rl_cache_refill_req_loop &&
!WILL_FIRE_RL_rl_ptw_level_1 &&
!WILL_FIRE_RL_rl_ptw_level_2 &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_probe_and_immed_rsp
assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
(cfg_verbosity_read__8_ULE_1___d19 || tlb$RDY_lookup) &&
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup) &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309 &&
rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316 ;
assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
CAN_FIRE_RL_rl_probe_and_immed_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_cache_refill_rsps_loop
assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd10 ;
assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_io_read_rsp
assign CAN_FIRE_RL_rl_io_read_rsp =
master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd14 ;
assign WILL_FIRE_RL_rl_io_read_rsp =
CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_write_req
assign CAN_FIRE_RL_rl_io_write_req =
!master_xactor_crg_wr_addr_full$port2__read &&
!master_xactor_crg_wr_data_full$port2__read &&
rg_state == 5'd13 &&
rg_op == 2'd1 ;
assign WILL_FIRE_RL_rl_io_write_req =
CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_op_req
assign CAN_FIRE_RL_rl_io_AMO_op_req =
!master_xactor_crg_rd_addr_full$port2__read &&
rg_state == 5'd13 &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] != 5'b00010 &&
rg_amo_funct7[6:2] != 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_op_req =
CAN_FIRE_RL_rl_io_AMO_op_req &&
!WILL_FIRE_RL_rl_cache_refill_req_loop &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_writeback_updated_PTE
assign CAN_FIRE_RL_rl_writeback_updated_PTE =
!master_xactor_crg_wr_addr_full$port2__read &&
!master_xactor_crg_wr_data_full$port2__read &&
f_pte_writebacks$EMPTY_N ;
assign WILL_FIRE_RL_rl_writeback_updated_PTE =
CAN_FIRE_RL_rl_writeback_updated_PTE &&
!WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!WILL_FIRE_RL_rl_io_write_req &&
!WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_read_rsp
assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
master_xactor_crg_rd_data_full_port1__read__96_ETC___d1232 &&
rg_state == 5'd16 ;
assign WILL_FIRE_RL_rl_io_AMO_read_rsp =
CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_start_tlb_refill
assign CAN_FIRE_RL_rl_start_tlb_refill =
!master_xactor_crg_rd_addr_full$port2__read &&
rg_state == 5'd5 &&
b__h23409 == 4'd0 ;
assign WILL_FIRE_RL_rl_start_tlb_refill =
CAN_FIRE_RL_rl_start_tlb_refill &&
!WILL_FIRE_RL_rl_cache_refill_req_loop &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_start_cache_refill
assign CAN_FIRE_RL_rl_start_cache_refill =
!master_xactor_crg_rd_addr_full$port2__read &&
rg_state == 5'd9 &&
b__h23409 == 4'd0 ;
assign WILL_FIRE_RL_rl_start_cache_refill =
CAN_FIRE_RL_rl_start_cache_refill &&
!WILL_FIRE_RL_rl_cache_refill_req_loop &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_io_read_req
assign CAN_FIRE_RL_rl_io_read_req =
!master_xactor_crg_rd_addr_full$port2__read &&
rg_state_3_EQ_13_098_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1100 ;
assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_3 ;
// rule RL_rl_discard_write_rsp
assign CAN_FIRE_RL_rl_discard_write_rsp =
b__h23409 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ;
assign WILL_FIRE_RL_rl_discard_write_rsp =
CAN_FIRE_RL_rl_discard_write_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
// inputs to muxes for submodule ports
assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 ;
assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 ;
assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3 =
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_writeback_updated_PTE ;
assign MUX_dw_output_ld_val$wset_1__SEL_1 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_3 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 ;
assign MUX_dw_output_ld_val$wset_1__SEL_4 =
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign MUX_master_xactor_rg_rd_addr$write_1__PSEL_1 =
CAN_FIRE_RL_rl_ptw_level_2 && !WILL_FIRE_RL_rl_start_reset ;
assign MUX_master_xactor_rg_rd_addr$write_1__SEL_1 =
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
!master_xactor_rg_rd_data[5] &&
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4] ;
assign MUX_master_xactor_rg_rd_addr$write_1__PSEL_2 =
CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ;
assign MUX_master_xactor_rg_rd_addr$write_1__SEL_2 =
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
!master_xactor_rg_rd_data[5] &&
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4] ;
assign MUX_master_xactor_rg_rd_addr$write_1__SEL_3 =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 =
EN_req &&
req_f3_BITS_1_TO_0_399_EQ_0b0_400_OR_req_f3_BI_ETC___d1429 ;
assign MUX_ram_word64_set$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_rg_rd_data[2:1] == 2'b0 ;
assign MUX_ram_word64_set$b_put_1__SEL_2 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] != 3'd7 ;
assign MUX_rg_error_during_refill$write_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_rg_rd_data[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_1 =
EN_req &&
NOT_req_f3_BITS_1_TO_0_399_EQ_0b0_400_401_AND__ETC___d1420 ;
assign MUX_rg_exc_code$write_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_3 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_rg_rd_data[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_5 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ;
assign MUX_rg_exc_code$write_1__SEL_6 =
WILL_FIRE_RL_rl_ptw_level_0 &&
(!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] ||
!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] ||
master_xactor_rg_rd_data[2:1] != 2'b0) ;
assign MUX_rg_exc_code$write_1__SEL_7 =
WILL_FIRE_RL_rl_ptw_level_1 &&
NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 ;
assign MUX_rg_exc_code$write_1__SEL_8 =
WILL_FIRE_RL_rl_ptw_level_2 &&
NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 ;
assign MUX_rg_ld_val$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 ;
assign MUX_rg_lrsc_valid$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 ;
assign MUX_rg_state$write_1__SEL_3 =
CAN_FIRE_RL_rl_io_read_req &&
!WILL_FIRE_RL_rl_cache_refill_req_loop &&
!WILL_FIRE_RL_rl_start_reset ;
assign MUX_rg_state$write_1__SEL_10 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd7 ;
assign MUX_rg_state$write_1__SEL_11 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 ;
assign MUX_rg_state$write_1__SEL_18 =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign MUX_tlb$insert_1__SEL_1 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 ;
assign MUX_tlb$insert_1__SEL_2 =
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 ;
assign MUX_tlb$insert_1__SEL_3 =
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 ;
assign MUX_tlb$insert_1__SEL_4 =
WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) ;
assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 =
ctr_wr_rsps_pending_crg + 4'd1 ;
assign MUX_dw_output_ld_val$wset_1__VAL_3 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
new_value__h7872 :
new_value__h17899 ;
assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 =
{ 4'd0, lev_1_pte_pa_w64_fa__h24452, 29'd851968 } ;
assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 =
{ 4'd0, lev_0_pte_pa_w64_fa__h25509, 29'd851968 } ;
assign MUX_master_xactor_rg_rd_addr$write_1__VAL_3 =
{ 4'd0, rg_pa, 8'd0, value__h32497, 18'd65536 } ;
assign MUX_master_xactor_rg_rd_addr$write_1__VAL_4 =
{ 4'd0, lev_2_pte_pa_w64_fa__h23510, 29'd851968 } ;
assign MUX_master_xactor_rg_rd_addr$write_1__VAL_5 =
{ 4'd0, cline_addr__h27485, 29'd851968 } ;
assign MUX_master_xactor_rg_rd_addr$write_1__VAL_6 =
{ 4'd0, cline_fabric_addr__h27486, 29'd851968 } ;
assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 =
{ 4'd0, rg_pa, 8'd0, value__h35523, 18'd65536 } ;
assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 =
{ 4'd0, x1_avValue_pa__h6383, 8'd0, value__h35523, 18'd65536 } ;
assign MUX_master_xactor_rg_wr_addr$write_1__VAL_4 =
{ 4'd0, f_pte_writebacks$D_OUT[127:64], 29'd851968 } ;
assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 =
{ 4'd0,
mem_req_wr_data_wdata__h33184,
mem_req_wr_data_wstrb__h33185,
1'd1 } ;
assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 =
{ 4'd0,
IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787,
mem_req_wr_data_wstrb__h19185,
1'd1 } ;
assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 =
{ 4'd0, f_pte_writebacks$D_OUT[63:0], 9'd511 } ;
assign MUX_master_xactor_rg_wr_data$write_1__VAL_4 =
{ 4'd0,
mem_req_wr_data_wdata__h31680,
mem_req_wr_data_wstrb__h33185,
1'd1 } ;
assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 1'd1, rg_pa[63:12] } ;
assign MUX_ram_word64_set$a_put_3__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 :
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 ;
assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ;
assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ;
assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ;
assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
assign MUX_rg_exc_code$write_1__VAL_6 =
(master_xactor_rg_rd_data[2:1] == 2'b0) ?
exc_code___1__h6745 :
access_exc_code__h3321 ;
assign MUX_rg_ld_val$write_1__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
x__h15551 :
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ;
assign MUX_rg_req_byte_in_cline$write_1__VAL_1 =
rg_req_byte_in_cline + 64'd8 ;
assign MUX_rg_state$write_1__VAL_2 =
NOT_req_f3_BITS_1_TO_0_399_EQ_0b0_400_401_AND__ETC___d1420 ?
5'd4 :
5'd3 ;
assign MUX_rg_state$write_1__VAL_6 =
(master_xactor_rg_rd_data[2:1] == 2'b0) ? 5'd15 : 5'd4 ;
assign MUX_rg_state$write_1__VAL_10 =
(master_xactor_rg_rd_data[2:1] != 2'b0 ||
rg_error_during_refill) ?
5'd4 :
5'd11 ;
assign MUX_rg_state$write_1__VAL_11 =
(rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 &&
!tlb$lookup[130]) ?
5'd5 :
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401 ;
assign MUX_rg_state$write_1__VAL_12 =
(master_xactor_rg_rd_data[2:1] == 2'b0) ?
((!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] &&
master_xactor_rg_rd_data[5] ||
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4]) ?
5'd4 :
5'd11) :
5'd4 ;
assign MUX_rg_state$write_1__VAL_13 =
(master_xactor_rg_rd_data[2:1] == 2'b0) ?
((!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] &&
master_xactor_rg_rd_data[5]) ?
5'd4 :
((!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4]) ?
5'd8 :
((master_xactor_rg_rd_data[21:13] == 9'd0) ?
5'd11 :
5'd4))) :
5'd4 ;
assign MUX_rg_state$write_1__VAL_14 =
(master_xactor_rg_rd_data[2:1] == 2'b0) ?
((!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] &&
master_xactor_rg_rd_data[5]) ?
5'd4 :
((!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4]) ?
5'd7 :
((master_xactor_rg_rd_data[30:22] != 9'd0 ||
master_xactor_rg_rd_data[21:13] != 9'd0) ?
5'd4 :
5'd11))) :
5'd4 ;
// inlined wires
assign dw_valid$whas =
(WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_read_rsp) &&
master_xactor_rg_rd_data[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 ||
WILL_FIRE_RL_rl_drive_exception_rsp ||
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign master_xactor_crg_wr_addr_full$EN_port0__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign master_xactor_crg_wr_addr_full$port1__read =
!master_xactor_crg_wr_addr_full$EN_port0__write &&
master_xactor_crg_wr_addr_full ;
assign master_xactor_crg_wr_addr_full$EN_port1__write =
master_xactor_crg_wr_addr_full$port1__read &&
mem_master_awready ;
assign master_xactor_crg_wr_addr_full$port2__read =
!master_xactor_crg_wr_addr_full$EN_port1__write &&
master_xactor_crg_wr_addr_full$port1__read ;
assign master_xactor_crg_wr_addr_full$EN_port2__write =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_writeback_updated_PTE ;
assign master_xactor_crg_wr_addr_full$port3__read =
master_xactor_crg_wr_addr_full$EN_port2__write ?
1'd1 :
master_xactor_crg_wr_addr_full$port2__read ;
assign master_xactor_crg_wr_data_full$EN_port0__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign master_xactor_crg_wr_data_full$port1__read =
!master_xactor_crg_wr_data_full$EN_port0__write &&
master_xactor_crg_wr_data_full ;
assign master_xactor_crg_wr_data_full$EN_port1__write =
master_xactor_crg_wr_data_full$port1__read && mem_master_wready ;
assign master_xactor_crg_wr_data_full$port2__read =
!master_xactor_crg_wr_data_full$EN_port1__write &&
master_xactor_crg_wr_data_full$port1__read ;
assign master_xactor_crg_wr_data_full$EN_port2__write =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_writeback_updated_PTE ;
assign master_xactor_crg_wr_data_full$port3__read =
master_xactor_crg_wr_data_full$EN_port2__write ?
1'd1 :
master_xactor_crg_wr_data_full$port2__read ;
assign master_xactor_crg_wr_resp_full$EN_port0__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign master_xactor_crg_wr_resp_full$port1__read =
!master_xactor_crg_wr_resp_full$EN_port0__write &&
master_xactor_crg_wr_resp_full ;
assign master_xactor_crg_wr_resp_full$EN_port1__write =
CAN_FIRE_RL_rl_discard_write_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
assign master_xactor_crg_wr_resp_full$port2__read =
!master_xactor_crg_wr_resp_full$EN_port1__write &&
master_xactor_crg_wr_resp_full$port1__read ;
assign master_xactor_crg_wr_resp_full$EN_port2__write =
mem_master_bvalid &&
!master_xactor_crg_wr_resp_full$port2__read ;
assign master_xactor_crg_wr_resp_full$port3__read =
master_xactor_crg_wr_resp_full$EN_port2__write ||
master_xactor_crg_wr_resp_full$port2__read ;
assign master_xactor_crg_rd_addr_full$EN_port0__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign master_xactor_crg_rd_addr_full$port1__read =
!master_xactor_crg_rd_addr_full$EN_port0__write &&
master_xactor_crg_rd_addr_full ;
assign master_xactor_crg_rd_addr_full$EN_port1__write =
master_xactor_crg_rd_addr_full$port1__read &&
mem_master_arready ;
assign master_xactor_crg_rd_addr_full$port2__read =
!master_xactor_crg_rd_addr_full$EN_port1__write &&
master_xactor_crg_rd_addr_full$port1__read ;
assign master_xactor_crg_rd_addr_full$EN_port2__write =
(WILL_FIRE_RL_rl_ptw_level_1 || WILL_FIRE_RL_rl_ptw_level_2) &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
!master_xactor_rg_rd_data[5] &&
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4] ||
WILL_FIRE_RL_rl_io_AMO_op_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_cache_refill_req_loop ||
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_start_tlb_refill ;
assign master_xactor_crg_rd_addr_full$port3__read =
master_xactor_crg_rd_addr_full$EN_port2__write ?
1'd1 :
master_xactor_crg_rd_addr_full$port2__read ;
assign master_xactor_crg_rd_data_full$EN_port0__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign master_xactor_crg_rd_data_full$port1__read =
!master_xactor_crg_rd_data_full$EN_port0__write &&
master_xactor_crg_rd_data_full ;
assign master_xactor_crg_rd_data_full$EN_port1__write =
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop ||
WILL_FIRE_RL_rl_ptw_level_0 ||
WILL_FIRE_RL_rl_ptw_level_1 ||
WILL_FIRE_RL_rl_ptw_level_2 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp ;
assign master_xactor_crg_rd_data_full$port2__read =
!master_xactor_crg_rd_data_full$EN_port1__write &&
master_xactor_crg_rd_data_full$port1__read ;
assign master_xactor_crg_rd_data_full$EN_port2__write =
mem_master_rvalid &&
!master_xactor_crg_rd_data_full$port2__read ;
assign master_xactor_crg_rd_data_full$port3__read =
master_xactor_crg_rd_data_full$EN_port2__write ||
master_xactor_crg_rd_data_full$port2__read ;
assign ctr_wr_rsps_pending_crg$EN_port0__write =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_writeback_updated_PTE ;
always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
ctr_wr_rsps_pending_crg$port0__write_1 =
MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1;
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2:
ctr_wr_rsps_pending_crg$port0__write_1 =
MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1;
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3:
ctr_wr_rsps_pending_crg$port0__write_1 =
MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1;
default: ctr_wr_rsps_pending_crg$port0__write_1 =
4'b1010 /* unspecified value */ ;
endcase
end
assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h23409 - 4'd1 ;
assign ctr_wr_rsps_pending_crg$port2__read =
WILL_FIRE_RL_rl_discard_write_rsp ?
ctr_wr_rsps_pending_crg$port1__write_1 :
b__h23409 ;
assign ctr_wr_rsps_pending_crg$EN_port2__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign ctr_wr_rsps_pending_crg$port3__read =
ctr_wr_rsps_pending_crg$EN_port2__write ?
4'd0 :
ctr_wr_rsps_pending_crg$port2__read ;
assign crg_sb_to_load_delay$port0__write_1 =
{ 1'd0, crg_sb_to_load_delay[10:1] } ;
assign crg_sb_to_load_delay$EN_port1__write =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766 ;
assign crg_sb_to_load_delay$port2__read =
crg_sb_to_load_delay$EN_port1__write ?
11'd2047 :
crg_sb_to_load_delay$port0__write_1 ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register crg_sb_to_load_delay
assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ;
assign crg_sb_to_load_delay$EN = 1'b1 ;
// register ctr_wr_rsps_pending_crg
assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register master_xactor_crg_rd_addr_full
assign master_xactor_crg_rd_addr_full$D_IN =
master_xactor_crg_rd_addr_full$port3__read ;
assign master_xactor_crg_rd_addr_full$EN = 1'b1 ;
// register master_xactor_crg_rd_data_full
assign master_xactor_crg_rd_data_full$D_IN =
master_xactor_crg_rd_data_full$port3__read ;
assign master_xactor_crg_rd_data_full$EN = 1'b1 ;
// register master_xactor_crg_wr_addr_full
assign master_xactor_crg_wr_addr_full$D_IN =
master_xactor_crg_wr_addr_full$port3__read ;
assign master_xactor_crg_wr_addr_full$EN = 1'b1 ;
// register master_xactor_crg_wr_data_full
assign master_xactor_crg_wr_data_full$D_IN =
master_xactor_crg_wr_data_full$port3__read ;
assign master_xactor_crg_wr_data_full$EN = 1'b1 ;
// register master_xactor_crg_wr_resp_full
assign master_xactor_crg_wr_resp_full$D_IN =
master_xactor_crg_wr_resp_full$port3__read ;
assign master_xactor_crg_wr_resp_full$EN = 1'b1 ;
// register master_xactor_rg_rd_addr
always@(MUX_master_xactor_rg_rd_addr$write_1__SEL_1 or
MUX_master_xactor_rg_rd_addr$write_1__VAL_1 or
MUX_master_xactor_rg_rd_addr$write_1__SEL_2 or
MUX_master_xactor_rg_rd_addr$write_1__VAL_2 or
MUX_master_xactor_rg_rd_addr$write_1__SEL_3 or
MUX_master_xactor_rg_rd_addr$write_1__VAL_3 or
WILL_FIRE_RL_rl_start_tlb_refill or
MUX_master_xactor_rg_rd_addr$write_1__VAL_4 or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_master_xactor_rg_rd_addr$write_1__VAL_5 or
WILL_FIRE_RL_rl_cache_refill_req_loop or
MUX_master_xactor_rg_rd_addr$write_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_master_xactor_rg_rd_addr$write_1__SEL_1:
master_xactor_rg_rd_addr$D_IN =
MUX_master_xactor_rg_rd_addr$write_1__VAL_1;
MUX_master_xactor_rg_rd_addr$write_1__SEL_2:
master_xactor_rg_rd_addr$D_IN =
MUX_master_xactor_rg_rd_addr$write_1__VAL_2;
MUX_master_xactor_rg_rd_addr$write_1__SEL_3:
master_xactor_rg_rd_addr$D_IN =
MUX_master_xactor_rg_rd_addr$write_1__VAL_3;
WILL_FIRE_RL_rl_start_tlb_refill:
master_xactor_rg_rd_addr$D_IN =
MUX_master_xactor_rg_rd_addr$write_1__VAL_4;
WILL_FIRE_RL_rl_start_cache_refill:
master_xactor_rg_rd_addr$D_IN =
MUX_master_xactor_rg_rd_addr$write_1__VAL_5;
WILL_FIRE_RL_rl_cache_refill_req_loop:
master_xactor_rg_rd_addr$D_IN =
MUX_master_xactor_rg_rd_addr$write_1__VAL_6;
default: master_xactor_rg_rd_addr$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign master_xactor_rg_rd_addr$EN =
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
!master_xactor_rg_rd_data[5] &&
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4] ||
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
!master_xactor_rg_rd_data[5] &&
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4] ||
WILL_FIRE_RL_rl_io_AMO_op_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_start_tlb_refill ||
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_cache_refill_req_loop ;
// register master_xactor_rg_rd_data
assign master_xactor_rg_rd_data$D_IN =
{ mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast } ;
assign master_xactor_rg_rd_data$EN = 1'd1 ;
// register master_xactor_rg_wr_addr
always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or
MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or
WILL_FIRE_RL_rl_io_write_req or
WILL_FIRE_RL_rl_writeback_updated_PTE or
MUX_master_xactor_rg_wr_addr$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
master_xactor_rg_wr_addr$D_IN =
MUX_master_xactor_rg_wr_addr$write_1__VAL_1;
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2:
master_xactor_rg_wr_addr$D_IN =
MUX_master_xactor_rg_wr_addr$write_1__VAL_2;
WILL_FIRE_RL_rl_io_write_req:
master_xactor_rg_wr_addr$D_IN =
MUX_master_xactor_rg_wr_addr$write_1__VAL_1;
WILL_FIRE_RL_rl_writeback_updated_PTE:
master_xactor_rg_wr_addr$D_IN =
MUX_master_xactor_rg_wr_addr$write_1__VAL_4;
default: master_xactor_rg_wr_addr$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign master_xactor_rg_wr_addr$EN =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_writeback_updated_PTE ;
// register master_xactor_rg_wr_data
always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
MUX_master_xactor_rg_wr_data$write_1__VAL_1 or
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or
MUX_master_xactor_rg_wr_data$write_1__VAL_2 or
WILL_FIRE_RL_rl_writeback_updated_PTE or
MUX_master_xactor_rg_wr_data$write_1__VAL_3 or
WILL_FIRE_RL_rl_io_write_req or
MUX_master_xactor_rg_wr_data$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
master_xactor_rg_wr_data$D_IN =
MUX_master_xactor_rg_wr_data$write_1__VAL_1;
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2:
master_xactor_rg_wr_data$D_IN =
MUX_master_xactor_rg_wr_data$write_1__VAL_2;
WILL_FIRE_RL_rl_writeback_updated_PTE:
master_xactor_rg_wr_data$D_IN =
MUX_master_xactor_rg_wr_data$write_1__VAL_3;
WILL_FIRE_RL_rl_io_write_req:
master_xactor_rg_wr_data$D_IN =
MUX_master_xactor_rg_wr_data$write_1__VAL_4;
default: master_xactor_rg_wr_data$D_IN =
77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign master_xactor_rg_wr_data$EN =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 ||
WILL_FIRE_RL_rl_writeback_updated_PTE ||
WILL_FIRE_RL_rl_io_write_req ;
// register master_xactor_rg_wr_resp
assign master_xactor_rg_wr_resp$D_IN =
{ mem_master_bid, mem_master_bresp } ;
assign master_xactor_rg_wr_resp$EN =
mem_master_bvalid &&
!master_xactor_crg_wr_resp_full$port2__read ;
// register rg_addr
assign rg_addr$D_IN = req_addr ;
assign rg_addr$EN = EN_req ;
// register rg_amo_funct7
assign rg_amo_funct7$D_IN = req_amo_funct7 ;
assign rg_amo_funct7$EN = EN_req ;
// register rg_cset_in_cache
assign rg_cset_in_cache$D_IN =
WILL_FIRE_RL_rl_reset ?
MUX_rg_cset_in_cache$write_1__VAL_1 :
6'd0 ;
assign rg_cset_in_cache$EN =
WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;
// register rg_error_during_refill
assign rg_error_during_refill$D_IN =
MUX_rg_error_during_refill$write_1__SEL_1 ;
assign rg_error_during_refill$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_rg_rd_data[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_exc_code
always@(MUX_rg_exc_code$write_1__SEL_1 or
MUX_rg_exc_code$write_1__VAL_1 or
MUX_rg_exc_code$write_1__SEL_2 or
MUX_rg_exc_code$write_1__SEL_3 or
MUX_rg_error_during_refill$write_1__SEL_1 or
access_exc_code__h3321 or
MUX_rg_exc_code$write_1__SEL_5 or
x1_avValue_exc_code__h6384 or
MUX_rg_exc_code$write_1__SEL_6 or
MUX_rg_exc_code$write_1__VAL_6 or
MUX_rg_exc_code$write_1__SEL_7 or MUX_rg_exc_code$write_1__SEL_8)
case (1'b1)
MUX_rg_exc_code$write_1__SEL_1:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
MUX_rg_error_during_refill$write_1__SEL_1:
rg_exc_code$D_IN = access_exc_code__h3321;
MUX_rg_exc_code$write_1__SEL_5:
rg_exc_code$D_IN = x1_avValue_exc_code__h6384;
MUX_rg_exc_code$write_1__SEL_6:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6;
MUX_rg_exc_code$write_1__SEL_7:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6;
MUX_rg_exc_code$write_1__SEL_8:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6;
default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign rg_exc_code$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_rg_rd_data[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_rg_rd_data[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] != 2'b0 ||
EN_req &&
NOT_req_f3_BITS_1_TO_0_399_EQ_0b0_400_401_AND__ETC___d1420 ||
WILL_FIRE_RL_rl_ptw_level_2 &&
NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 ||
WILL_FIRE_RL_rl_ptw_level_1 &&
NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 ||
WILL_FIRE_RL_rl_ptw_level_0 &&
(!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] ||
!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] ||
master_xactor_rg_rd_data[2:1] != 2'b0) ;
// register rg_f3
assign rg_f3$D_IN = req_f3 ;
assign rg_f3$EN = EN_req ;
// register rg_ld_val
always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or
new_ld_val__h32912 or
MUX_rg_ld_val$write_1__SEL_2 or
MUX_rg_ld_val$write_1__VAL_2 or
WILL_FIRE_RL_rl_io_read_rsp or
ld_val__h30074 or WILL_FIRE_RL_rl_io_AMO_SC_req)
begin
case (1'b1) // synopsys parallel_case
MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1:
rg_ld_val$D_IN = new_ld_val__h32912;
MUX_rg_ld_val$write_1__SEL_2:
rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h30074;
WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_ld_val$EN =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 ||
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_SC_req ;
// register rg_lower_word32
assign rg_lower_word32$D_IN = 32'h0 ;
assign rg_lower_word32$EN = 1'b0 ;
// register rg_lower_word32_full
assign rg_lower_word32_full$D_IN = 1'd0 ;
assign rg_lower_word32_full$EN =
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_lrsc_pa
assign rg_lrsc_pa$D_IN = soc_map$m_is_mem_addr_addr ;
assign rg_lrsc_pa$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597 ;
// register rg_lrsc_valid
assign rg_lrsc_valid$D_IN =
MUX_rg_lrsc_valid$write_1__SEL_2 &&
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 ;
assign rg_lrsc_valid$EN =
WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_mstatus_MXR
assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ;
assign rg_mstatus_MXR$EN = EN_req ;
// register rg_op
assign rg_op$D_IN = req_op ;
assign rg_op$EN = EN_req ;
// register rg_pa
assign rg_pa$D_IN = EN_req ? req_addr : soc_map$m_is_mem_addr_addr ;
assign rg_pa$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421 ||
EN_req ;
// register rg_priv
assign rg_priv$D_IN = req_priv ;
assign rg_priv$EN = EN_req ;
// register rg_pte_pa
always@(MUX_master_xactor_rg_rd_addr$write_1__SEL_1 or
lev_1_pte_pa__h24450 or
MUX_master_xactor_rg_rd_addr$write_1__SEL_2 or
lev_0_pte_pa__h25507 or
WILL_FIRE_RL_rl_start_tlb_refill or lev_2_pte_pa__h23508)
begin
case (1'b1) // synopsys parallel_case
MUX_master_xactor_rg_rd_addr$write_1__SEL_1:
rg_pte_pa$D_IN = lev_1_pte_pa__h24450;
MUX_master_xactor_rg_rd_addr$write_1__SEL_2:
rg_pte_pa$D_IN = lev_0_pte_pa__h25507;
WILL_FIRE_RL_rl_start_tlb_refill: rg_pte_pa$D_IN = lev_2_pte_pa__h23508;
default: rg_pte_pa$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_pte_pa$EN =
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
!master_xactor_rg_rd_data[5] &&
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4] ||
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
!master_xactor_rg_rd_data[5] &&
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4] ||
WILL_FIRE_RL_rl_start_tlb_refill ;
// register rg_req_byte_in_cline
assign rg_req_byte_in_cline$D_IN =
WILL_FIRE_RL_rl_cache_refill_req_loop ?
MUX_rg_req_byte_in_cline$write_1__VAL_1 :
64'd8 ;
assign rg_req_byte_in_cline$EN =
WILL_FIRE_RL_rl_cache_refill_req_loop ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_requesting_cline
always@(WILL_FIRE_RL_rl_cache_refill_req_loop or
rg_req_byte_in_cline or
WILL_FIRE_RL_rl_start_reset or WILL_FIRE_RL_rl_start_cache_refill)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_cache_refill_req_loop:
rg_requesting_cline$D_IN = rg_req_byte_in_cline != 64'd56;
WILL_FIRE_RL_rl_start_reset: rg_requesting_cline$D_IN = 1'd0;
WILL_FIRE_RL_rl_start_cache_refill: rg_requesting_cline$D_IN = 1'd1;
default: rg_requesting_cline$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign rg_requesting_cline$EN =
WILL_FIRE_RL_rl_cache_refill_req_loop ||
WILL_FIRE_RL_rl_start_reset ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_satp
assign rg_satp$D_IN = req_satp ;
assign rg_satp$EN = EN_req ;
// register rg_sstatus_SUM
assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ;
assign rg_sstatus_SUM$EN = EN_req ;
// register rg_st_amo_val
assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h19634 ;
assign rg_st_amo_val$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880 ||
EN_req ;
// register rg_state
always@(EN_tlb_flush or
EN_req or
MUX_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_rl_io_read_req or
WILL_FIRE_RL_rl_start_cache_refill or
WILL_FIRE_RL_rl_start_tlb_refill or
WILL_FIRE_RL_rl_io_AMO_read_rsp or
MUX_rg_state$write_1__VAL_6 or
WILL_FIRE_RL_rl_io_AMO_op_req or
WILL_FIRE_RL_rl_io_write_req or
WILL_FIRE_RL_rl_io_read_rsp or
MUX_rg_state$write_1__SEL_10 or
MUX_rg_state$write_1__VAL_10 or
MUX_rg_state$write_1__SEL_11 or
MUX_rg_state$write_1__VAL_11 or
WILL_FIRE_RL_rl_ptw_level_0 or
MUX_rg_state$write_1__VAL_12 or
WILL_FIRE_RL_rl_ptw_level_1 or
MUX_rg_state$write_1__VAL_13 or
WILL_FIRE_RL_rl_ptw_level_2 or
MUX_rg_state$write_1__VAL_14 or
WILL_FIRE_RL_rl_start_reset or
WILL_FIRE_RL_rl_io_AMO_SC_req or
WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_18)
case (1'b1)
EN_tlb_flush: rg_state$D_IN = 5'd2;
EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14;
WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10;
WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 5'd6;
WILL_FIRE_RL_rl_io_AMO_read_rsp:
rg_state$D_IN = MUX_rg_state$write_1__VAL_6;
WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16;
WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 5'd12;
WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_6;
MUX_rg_state$write_1__SEL_10:
rg_state$D_IN = MUX_rg_state$write_1__VAL_10;
MUX_rg_state$write_1__SEL_11:
rg_state$D_IN = MUX_rg_state$write_1__VAL_11;
WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_12;
WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_13;
WILL_FIRE_RL_rl_ptw_level_2: rg_state$D_IN = MUX_rg_state$write_1__VAL_14;
WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1;
WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 5'd12;
WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3;
MUX_rg_state$write_1__SEL_18: rg_state$D_IN = 5'd2;
default: rg_state$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign rg_state$EN =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd7 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 ||
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_ptw_level_2 ||
WILL_FIRE_RL_rl_ptw_level_1 ||
WILL_FIRE_RL_rl_ptw_level_0 ||
EN_req ||
WILL_FIRE_RL_rl_start_reset ||
EN_tlb_flush ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_tlb_refill ||
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_io_AMO_SC_req ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_io_AMO_op_req ;
// register rg_word64_set_in_cache
assign rg_word64_set_in_cache$D_IN =
MUX_ram_word64_set$b_put_1__SEL_2 ?
MUX_ram_word64_set$b_put_2__VAL_2 :
MUX_ram_word64_set$b_put_2__VAL_4 ;
assign rg_word64_set_in_cache$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] != 3'd7 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule f_pte_writebacks
assign f_pte_writebacks$D_IN = { tlb$lookup[63:0], value__h7170 } ;
assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ;
assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ;
assign f_pte_writebacks$CLR = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
assign f_reset_reqs$ENQ =
EN_server_reset_request_put || EN_server_flush_request_put ;
assign f_reset_reqs$DEQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
assign f_reset_rsps$ENQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign f_reset_rsps$DEQ =
EN_server_flush_response_get || EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule ram_state_and_ctag_cset
assign ram_state_and_ctag_cset$ADDRA =
WILL_FIRE_RL_rl_start_cache_refill ?
rg_addr[11:6] :
rg_cset_in_cache ;
assign ram_state_and_ctag_cset$ADDRB =
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
req_addr[11:6] :
rg_addr[11:6] ;
assign ram_state_and_ctag_cset$DIA =
WILL_FIRE_RL_rl_start_cache_refill ?
MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
53'h0AAAAAAAAAAAAA ;
assign ram_state_and_ctag_cset$DIB =
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
53'h0AAAAAAAAAAAAA /* unspecified value */ :
53'h0AAAAAAAAAAAAA /* unspecified value */ ;
assign ram_state_and_ctag_cset$WEA = 1'd1 ;
assign ram_state_and_ctag_cset$WEB = 1'd0 ;
assign ram_state_and_ctag_cset$ENA =
WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ;
assign ram_state_and_ctag_cset$ENB =
EN_req &&
req_f3_BITS_1_TO_0_399_EQ_0b0_400_OR_req_f3_BI_ETC___d1429 ||
WILL_FIRE_RL_rl_rereq ;
// submodule ram_word64_set
assign ram_word64_set$ADDRA =
MUX_ram_word64_set$a_put_1__SEL_1 ?
rg_word64_set_in_cache :
rg_addr[11:3] ;
always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
req_addr or
MUX_ram_word64_set$b_put_1__SEL_2 or
MUX_ram_word64_set$b_put_2__VAL_2 or
WILL_FIRE_RL_rl_rereq or
rg_addr or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_ram_word64_set$b_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
ram_word64_set$ADDRB = req_addr[11:3];
MUX_ram_word64_set$b_put_1__SEL_2:
ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2;
WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3];
WILL_FIRE_RL_rl_start_cache_refill:
ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4;
default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ;
endcase
end
assign ram_word64_set$DIA =
MUX_ram_word64_set$a_put_1__SEL_1 ?
master_xactor_rg_rd_data[66:3] :
MUX_ram_word64_set$a_put_3__VAL_2 ;
always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
MUX_ram_word64_set$b_put_1__SEL_2 or
WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
MUX_ram_word64_set$b_put_1__SEL_2:
ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_rereq:
ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_start_cache_refill:
ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
default: ram_word64_set$DIB =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign ram_word64_set$WEA = 1'd1 ;
assign ram_word64_set$WEB = 1'd0 ;
assign ram_word64_set$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_rg_rd_data[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639 ;
assign ram_word64_set$ENB =
EN_req &&
req_f3_BITS_1_TO_0_399_EQ_0b0_400_OR_req_f3_BI_ETC___d1429 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] != 3'd7 ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr =
(rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8) ?
_theResult___snd_fst__h6474 :
rg_addr ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// submodule tlb
assign tlb$insert_asid = rg_satp[59:44] ;
always@(MUX_tlb$insert_1__SEL_1 or
tlb$lookup or
MUX_tlb$insert_1__SEL_2 or
MUX_tlb$insert_1__SEL_3 or MUX_tlb$insert_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[65:64];
MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd2;
MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd1;
MUX_tlb$insert_1__SEL_4: tlb$insert_level = 2'd0;
default: tlb$insert_level = 2'b10 /* unspecified value */ ;
endcase
end
assign tlb$insert_pte =
(MUX_tlb$insert_1__SEL_2 || MUX_tlb$insert_1__SEL_3 ||
MUX_tlb$insert_1__SEL_4) ?
master_xactor_rg_rd_data[66:3] :
value__h7170 ;
assign tlb$insert_pte_pa =
MUX_tlb$insert_1__SEL_1 ? tlb$lookup[63:0] : rg_pte_pa ;
assign tlb$insert_vpn = rg_addr[38:12] ;
assign tlb$lookup_asid = rg_satp[59:44] ;
assign tlb$lookup_vpn = rg_addr[38:12] ;
assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ;
assign tlb$EN_insert =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 ||
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 ||
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 ||
WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) ;
// remaining internal signals
assign IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293 =
(x1_avValue_pa__h6383[2:0] == 3'h0) ?
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 :
NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292 ;
assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577 =
(rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1309 =
(rg_addr[2:0] == 3'h0) ? ld_val__h30074 : 64'd0 ;
assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217 =
(rg_addr[2:0] == 3'h0) ?
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 :
rg_addr[2:0] != 3'h4 ||
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 ;
assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 =
(rg_addr[2:0] == 3'h0) ? word64__h7691 : 64'd0 ;
assign IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 =
(rg_f3 == 3'b010) ?
{ {32{rg_st_amo_val_BITS_31_TO_0__q31[31]}},
rg_st_amo_val_BITS_31_TO_0__q31 } :
rg_st_amo_val ;
assign IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ||
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 :
IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304 ;
assign IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
5'd9 :
IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398 ;
assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248 :
!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ||
!master_xactor_crg_wr_addr_full$port2__read &&
!master_xactor_crg_wr_data_full$port2__read &&
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 &&
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 &&
IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ;
assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
5'd12 :
((!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ?
5'd9 :
5'd12) ;
assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
mem_req_wr_data_wdata__h19184 :
mem_req_wr_data_wdata__h22620 ;
assign IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401 =
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ?
5'd4 :
((dmem_not_imem && !soc_map$m_is_mem_addr) ?
5'd13 :
IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399) ;
assign IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 =
x1_avValue_pa__h6383 == rg_lrsc_pa ;
assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284 =
x1_avValue_pa__h6383[2:0] != 3'h7 ||
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ;
assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289 =
x1_avValue_pa__h6383[2:0] != 3'h6 ||
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ;
assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292 =
x1_avValue_pa__h6383[2:0] != 3'h4 ||
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ;
assign NOT_cfg_verbosity_read__8_ULE_2_060___d1061 = cfg_verbosity > 4'd2 ;
assign NOT_cfg_verbosity_read__8_ULT_2_05___d406 = cfg_verbosity >= 4'd2 ;
assign NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341 =
!dmem_not_imem &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
tlb$lookup[69] ;
assign NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108 =
!dmem_not_imem ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
!tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872 ;
assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 ;
assign NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921 =
master_xactor_rg_rd_data[2:1] != 2'b0 ||
!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] ||
((!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4]) ?
!master_xactor_crg_rd_addr_full$port2__read :
master_xactor_rg_rd_data[30:22] != 9'd0 ||
master_xactor_rg_rd_data[21:13] != 9'd0 ||
tlb$RDY_insert) ;
assign NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984 =
master_xactor_rg_rd_data[2:1] != 2'b0 ||
!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] ||
((!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4]) ?
!master_xactor_crg_rd_addr_full$port2__read :
master_xactor_rg_rd_data[21:13] != 9'd0 || tlb$RDY_insert) ;
assign NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 =
!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] ||
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
(master_xactor_rg_rd_data[30:22] != 9'd0 ||
master_xactor_rg_rd_data[21:13] != 9'd0) ||
master_xactor_rg_rd_data[2:1] != 2'b0 ;
assign NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 =
!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] ||
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
master_xactor_rg_rd_data[21:13] != 9'd0 ||
master_xactor_rg_rd_data[2:1] != 2'b0 ;
assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 =
!ram_state_and_ctag_cset$DOB[52] || !rg_priv_9_ULE_0b1___d60 ||
rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup ;
assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 ;
assign NOT_req_f3_BITS_1_TO_0_399_EQ_0b0_400_401_AND__ETC___d1420 =
req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
(req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
(req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
assign NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294 =
rg_f3 != 3'b011 ||
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ;
assign NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) ;
assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 ;
assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ;
assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
(rg_f3 == 3'b0 || rg_f3 == 3'b001) ;
assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
ctr_wr_rsps_pending_crg == 4'd15 ;
assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ;
assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
(rg_f3 == 3'b0 || rg_f3 == 3'b001) ;
assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) &&
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) &&
ctr_wr_rsps_pending_crg == 4'd15 ;
assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 =
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
(NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341 ||
dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343 ||
dmem_not_imem && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
tlb$lookup[68]) ;
assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 =
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
dmem_not_imem &&
tlb$lookup[68] ;
assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409 =
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
tlb$lookup[72] &&
!pte___2__h6845[7] &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583 =
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
(!dmem_not_imem && tlb$lookup[69] ||
dmem_not_imem &&
tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106) ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142 =
!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 ||
NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307 =
(NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142 ||
tlb$RDY_insert && tlb$RDY_lookup && f_pte_writebacks$FULL_N) &&
(dmem_not_imem && !soc_map$m_is_mem_addr ||
IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305) ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353 =
!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130] &&
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 &&
tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368 =
!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 ||
NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 =
!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 &&
tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428 =
!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424 &&
tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428 &&
dmem_not_imem &&
!soc_map$m_is_mem_addr &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h15541) ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 =
!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583 &&
tlb$lookup[72] ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 =
!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 &&
tlb$lookup[72] &&
tlb$lookup[73] ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767 ||
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634) ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
rg_lrsc_valid &&
!rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
!rg_lrsc_valid &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849 =
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h15541 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874 ;
assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880 =
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 &&
NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878 ;
assign NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123 =
!tlb$lookup[72] ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
!tlb$lookup[73] ;
assign NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 =
!tlb$lookup[72] || !tlb$lookup[73] || pte___2__h6845[7] ||
rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ;
assign _theResult___fst__h19116 = rg_st_amo_val << shift_bits__h18980 ;
assign _theResult___fst__h22552 = new_st_val__h19634 << shift_bits__h18980 ;
assign _theResult___fst__h31612 = rg_st_amo_val << shift_bits__h32980 ;
assign _theResult___fst__h33116 = st_val__h32924 << shift_bits__h32980 ;
assign _theResult___snd_fst__h6474 =
tlb$lookup[130] ? _theResult___snd_fst__h6545 : rg_addr ;
assign _theResult___snd_fst__h6545 =
(rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 ||
NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ?
rg_addr :
_theResult___fst__h6847 ;
assign _theResult___snd_fst__h7076 =
(!pte___2__h6845[7] && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ?
pte___1__h7153 :
pte___2__h6845 ;
assign _theResult___snd_snd_fst__h6476 =
tlb$lookup[130] ?
_theResult___snd_snd_fst__h6547 :
tlb$lookup[129:66] ;
assign _theResult___snd_snd_fst__h6547 =
(rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 ||
NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ?
tlb$lookup[129:66] :
_theResult___snd_fst__h7076 ;
assign access_exc_code__h3321 =
dmem_not_imem ?
((rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd5 :
4'd7) :
4'd1 ;
assign b__h23409 =
ctr_wr_rsps_pending_crg$EN_port0__write ?
ctr_wr_rsps_pending_crg$port0__write_1 :
ctr_wr_rsps_pending_crg ;
assign cfg_verbosity_read__8_ULE_1___d19 = cfg_verbosity <= 4'd1 ;
assign cline_addr__h27485 = { rg_pa[63:6], 6'd0 } ;
assign cline_fabric_addr__h27486 =
cline_addr__h27485 | rg_req_byte_in_cline ;
assign dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343 =
dmem_not_imem &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 ;
assign dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100 =
dmem_not_imem ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
!tlb$lookup[69] ;
assign exc_code___1__h6745 = x1_avValue_exc_code__h6384 ;
assign ld_val0074_BITS_15_TO_0__q37 = ld_val__h30074[15:0] ;
assign ld_val0074_BITS_15_TO_8__q39 = ld_val__h30074[15:8] ;
assign ld_val0074_BITS_23_TO_16__q40 = ld_val__h30074[23:16] ;
assign ld_val0074_BITS_31_TO_0__q38 = ld_val__h30074[31:0] ;
assign ld_val0074_BITS_31_TO_16__q41 = ld_val__h30074[31:16] ;
assign ld_val0074_BITS_31_TO_24__q42 = ld_val__h30074[31:24] ;
assign ld_val0074_BITS_39_TO_32__q43 = ld_val__h30074[39:32] ;
assign ld_val0074_BITS_47_TO_32__q44 = ld_val__h30074[47:32] ;
assign ld_val0074_BITS_47_TO_40__q46 = ld_val__h30074[47:40] ;
assign ld_val0074_BITS_55_TO_48__q47 = ld_val__h30074[55:48] ;
assign ld_val0074_BITS_63_TO_32__q45 = ld_val__h30074[63:32] ;
assign ld_val0074_BITS_63_TO_48__q48 = ld_val__h30074[63:48] ;
assign ld_val0074_BITS_63_TO_56__q49 = ld_val__h30074[63:56] ;
assign ld_val0074_BITS_7_TO_0__q36 = ld_val__h30074[7:0] ;
assign lev_0_pte_pa__h25507 = lev_1_PTN_pa__h24448 + vpn_0_pa__h25506 ;
assign lev_0_pte_pa_w64_fa__h25509 = { lev_0_pte_pa__h25507[63:3], 3'b0 } ;
assign lev_1_PTN_pa__h24448 = { 8'd0, x__h24553 } ;
assign lev_1_pte_pa__h24450 = lev_1_PTN_pa__h24448 + vpn_1_pa__h24449 ;
assign lev_1_pte_pa_w64_fa__h24452 = { lev_1_pte_pa__h24450[63:3], 3'b0 } ;
assign lev_2_pte_pa__h23508 = satp_pa__h2578 + vpn_2_pa__h23507 ;
assign lev_2_pte_pa_w64_fa__h23510 = { lev_2_pte_pa__h23508[63:3], 3'b0 } ;
assign lrsc_result__h15541 =
!rg_lrsc_valid ||
!rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 ;
assign master_xactor_crg_rd_data_full_port1__read__96_ETC___d1232 =
master_xactor_crg_rd_data_full$port1__read &&
(master_xactor_rg_rd_data[2:1] != 2'b0 ||
!master_xactor_crg_wr_addr_full$port2__read &&
!master_xactor_crg_wr_data_full$port2__read) ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
master_xactor_rg_rd_data[21:13] == 9'd0 ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
master_xactor_rg_rd_data[21:13] == 9'd0 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
master_xactor_rg_rd_data[21:13] != 9'd0 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
(!master_xactor_rg_rd_data[3] ||
!master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5]) &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
!master_xactor_rg_rd_data[5] &&
!master_xactor_rg_rd_data[6] &&
!master_xactor_rg_rd_data[4] &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
(master_xactor_rg_rd_data[30:22] != 9'd0 ||
master_xactor_rg_rd_data[21:13] != 9'd0) &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
master_xactor_rg_rd_data[30:22] == 9'd0 &&
master_xactor_rg_rd_data[21:13] == 9'd0 ;
assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975 =
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
master_xactor_rg_rd_data[30:22] == 9'd0 &&
master_xactor_rg_rd_data[21:13] == 9'd0 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 =
master_xactor_rg_rd_data[10:3] ;
assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 =
master_xactor_rg_rd_data[18:11] ;
assign master_xactor_rg_rd_data_BITS_18_TO_3__q2 =
master_xactor_rg_rd_data[18:3] ;
assign master_xactor_rg_rd_data_BITS_26_TO_19__q6 =
master_xactor_rg_rd_data[26:19] ;
assign master_xactor_rg_rd_data_BITS_34_TO_19__q7 =
master_xactor_rg_rd_data[34:19] ;
assign master_xactor_rg_rd_data_BITS_34_TO_27__q5 =
master_xactor_rg_rd_data[34:27] ;
assign master_xactor_rg_rd_data_BITS_34_TO_3__q3 =
master_xactor_rg_rd_data[34:3] ;
assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 =
master_xactor_rg_rd_data[42:35] ;
assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 =
master_xactor_rg_rd_data[50:35] ;
assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 =
master_xactor_rg_rd_data[50:43] ;
assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 =
master_xactor_rg_rd_data[58:51] ;
assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 =
master_xactor_rg_rd_data[66:35] ;
assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 =
master_xactor_rg_rd_data[66:51] ;
assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 =
master_xactor_rg_rd_data[66:59] ;
assign new_st_val__h19634 =
(rg_f3 == 3'b010) ?
new_st_val__h19916 :
_theResult_____2__h19912 ;
assign new_st_val__h19916 = { 32'd0, _theResult_____2__h19912[31:0] } ;
assign new_st_val__h20007 =
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 +
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ;
assign new_st_val__h20987 = w1__h19904 ^ w2__h33200 ;
assign new_st_val__h20991 = w1__h19904 & w2__h33200 ;
assign new_st_val__h20995 = w1__h19904 | w2__h33200 ;
assign new_st_val__h20999 =
(w1__h19904 < w2__h33200) ? w1__h19904 : w2__h33200 ;
assign new_st_val__h21004 =
(w1__h19904 <= w2__h33200) ? w2__h33200 : w1__h19904 ;
assign new_st_val__h21010 =
((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ^
64'h8000000000000000) <
(IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^
64'h8000000000000000)) ?
w1__h19904 :
w2__h33200 ;
assign new_st_val__h21015 =
((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ^
64'h8000000000000000) <=
(IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^
64'h8000000000000000)) ?
w2__h33200 :
w1__h19904 ;
assign new_st_val__h33210 = { 32'd0, _theResult_____2__h33206[31:0] } ;
assign new_st_val__h33301 =
new_ld_val__h32912 +
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ;
assign new_st_val__h35161 = w1__h33198 ^ w2__h33200 ;
assign new_st_val__h35165 = w1__h33198 & w2__h33200 ;
assign new_st_val__h35169 = w1__h33198 | w2__h33200 ;
assign new_st_val__h35173 =
(w1__h33198 < w2__h33200) ? w1__h33198 : w2__h33200 ;
assign new_st_val__h35178 =
(w1__h33198 <= w2__h33200) ? w2__h33200 : w1__h33198 ;
assign new_st_val__h35184 =
((new_ld_val__h32912 ^ 64'h8000000000000000) <
(IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^
64'h8000000000000000)) ?
w1__h33198 :
w2__h33200 ;
assign new_st_val__h35189 =
((new_ld_val__h32912 ^ 64'h8000000000000000) <=
(IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^
64'h8000000000000000)) ?
w2__h33200 :
w1__h33198 ;
assign new_value872_BITS_31_TO_0__q32 = new_value__h7872[31:0] ;
assign pa___1__h6853 = { 8'd0, x__h6856 } ;
assign pa___1__h6902 = { 8'd0, x__h6905 } ;
assign pa___1__h6971 = { 8'd0, x__h6974 } ;
assign pte___1__h7125 = { tlb$lookup[129:73], 1'd1, tlb$lookup[71:66] } ;
assign pte___1__h7153 =
{ pte___2__h6845[63:8], 1'd1, pte___2__h6845[6:0] } ;
assign pte___2__h6845 =
tlb$lookup[72] ? tlb$lookup[129:66] : pte___1__h7125 ;
assign ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 =
ram_state_and_ctag_cset$DOB[51:0] ==
x1_avValue_pa__h6383[63:12] ;
assign ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438 =
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ||
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437 ;
assign req_f3_BITS_1_TO_0_399_EQ_0b0_400_OR_req_f3_BI_ETC___d1429 =
req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
assign result__h14281 =
{ {56{word64691_BITS_15_TO_8__q18[7]}},
word64691_BITS_15_TO_8__q18 } ;
assign result__h14309 =
{ {56{word64691_BITS_23_TO_16__q19[7]}},
word64691_BITS_23_TO_16__q19 } ;
assign result__h14337 =
{ {56{word64691_BITS_31_TO_24__q21[7]}},
word64691_BITS_31_TO_24__q21 } ;
assign result__h14365 =
{ {56{word64691_BITS_39_TO_32__q22[7]}},
word64691_BITS_39_TO_32__q22 } ;
assign result__h14393 =
{ {56{word64691_BITS_47_TO_40__q25[7]}},
word64691_BITS_47_TO_40__q25 } ;
assign result__h14421 =
{ {56{word64691_BITS_55_TO_48__q26[7]}},
word64691_BITS_55_TO_48__q26 } ;
assign result__h14449 =
{ {56{word64691_BITS_63_TO_56__q28[7]}},
word64691_BITS_63_TO_56__q28 } ;
assign result__h14494 = { 56'd0, word64__h7691[7:0] } ;
assign result__h14522 = { 56'd0, word64__h7691[15:8] } ;
assign result__h14550 = { 56'd0, word64__h7691[23:16] } ;
assign result__h14578 = { 56'd0, word64__h7691[31:24] } ;
assign result__h14606 = { 56'd0, word64__h7691[39:32] } ;
assign result__h14634 = { 56'd0, word64__h7691[47:40] } ;
assign result__h14662 = { 56'd0, word64__h7691[55:48] } ;
assign result__h14690 = { 56'd0, word64__h7691[63:56] } ;
assign result__h14735 =
{ {48{word64691_BITS_15_TO_0__q16[15]}},
word64691_BITS_15_TO_0__q16 } ;
assign result__h14763 =
{ {48{word64691_BITS_31_TO_16__q20[15]}},
word64691_BITS_31_TO_16__q20 } ;
assign result__h14791 =
{ {48{word64691_BITS_47_TO_32__q23[15]}},
word64691_BITS_47_TO_32__q23 } ;
assign result__h14819 =
{ {48{word64691_BITS_63_TO_48__q27[15]}},
word64691_BITS_63_TO_48__q27 } ;
assign result__h14860 = { 48'd0, word64__h7691[15:0] } ;
assign result__h14888 = { 48'd0, word64__h7691[31:16] } ;
assign result__h14916 = { 48'd0, word64__h7691[47:32] } ;
assign result__h14944 = { 48'd0, word64__h7691[63:48] } ;
assign result__h14985 =
{ {32{word64691_BITS_31_TO_0__q17[31]}},
word64691_BITS_31_TO_0__q17 } ;
assign result__h15013 =
{ {32{word64691_BITS_63_TO_32__q24[31]}},
word64691_BITS_63_TO_32__q24 } ;
assign result__h15052 = { 32'd0, word64__h7691[31:0] } ;
assign result__h15080 = { 32'd0, word64__h7691[63:32] } ;
assign result__h30134 =
{ {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}},
master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ;
assign result__h30164 =
{ {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}},
master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ;
assign result__h30191 =
{ {56{master_xactor_rg_rd_data_BITS_26_TO_19__q6[7]}},
master_xactor_rg_rd_data_BITS_26_TO_19__q6 } ;
assign result__h30218 =
{ {56{master_xactor_rg_rd_data_BITS_34_TO_27__q5[7]}},
master_xactor_rg_rd_data_BITS_34_TO_27__q5 } ;
assign result__h30245 =
{ {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}},
master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ;
assign result__h30272 =
{ {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}},
master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ;
assign result__h30299 =
{ {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}},
master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ;
assign result__h30326 =
{ {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}},
master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ;
assign result__h30370 = { 56'd0, master_xactor_rg_rd_data[10:3] } ;
assign result__h30397 = { 56'd0, master_xactor_rg_rd_data[18:11] } ;
assign result__h30424 = { 56'd0, master_xactor_rg_rd_data[26:19] } ;
assign result__h30451 = { 56'd0, master_xactor_rg_rd_data[34:27] } ;
assign result__h30478 = { 56'd0, master_xactor_rg_rd_data[42:35] } ;
assign result__h30505 = { 56'd0, master_xactor_rg_rd_data[50:43] } ;
assign result__h30532 = { 56'd0, master_xactor_rg_rd_data[58:51] } ;
assign result__h30559 = { 56'd0, master_xactor_rg_rd_data[66:59] } ;
assign result__h30603 =
{ {48{master_xactor_rg_rd_data_BITS_18_TO_3__q2[15]}},
master_xactor_rg_rd_data_BITS_18_TO_3__q2 } ;
assign result__h30630 =
{ {48{master_xactor_rg_rd_data_BITS_34_TO_19__q7[15]}},
master_xactor_rg_rd_data_BITS_34_TO_19__q7 } ;
assign result__h30657 =
{ {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}},
master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ;
assign result__h30684 =
{ {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}},
master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ;
assign result__h30724 = { 48'd0, master_xactor_rg_rd_data[18:3] } ;
assign result__h30751 = { 48'd0, master_xactor_rg_rd_data[34:19] } ;
assign result__h30778 = { 48'd0, master_xactor_rg_rd_data[50:35] } ;
assign result__h30805 = { 48'd0, master_xactor_rg_rd_data[66:51] } ;
assign result__h30845 =
{ {32{master_xactor_rg_rd_data_BITS_34_TO_3__q3[31]}},
master_xactor_rg_rd_data_BITS_34_TO_3__q3 } ;
assign result__h30872 =
{ {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}},
master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ;
assign result__h30910 = { 32'd0, master_xactor_rg_rd_data[34:3] } ;
assign result__h30937 = { 32'd0, master_xactor_rg_rd_data[66:35] } ;
assign result__h33389 =
{ {56{ld_val0074_BITS_7_TO_0__q36[7]}},
ld_val0074_BITS_7_TO_0__q36 } ;
assign result__h34297 =
{ {56{ld_val0074_BITS_15_TO_8__q39[7]}},
ld_val0074_BITS_15_TO_8__q39 } ;
assign result__h34325 =
{ {56{ld_val0074_BITS_23_TO_16__q40[7]}},
ld_val0074_BITS_23_TO_16__q40 } ;
assign result__h34353 =
{ {56{ld_val0074_BITS_31_TO_24__q42[7]}},
ld_val0074_BITS_31_TO_24__q42 } ;
assign result__h34381 =
{ {56{ld_val0074_BITS_39_TO_32__q43[7]}},
ld_val0074_BITS_39_TO_32__q43 } ;
assign result__h34409 =
{ {56{ld_val0074_BITS_47_TO_40__q46[7]}},
ld_val0074_BITS_47_TO_40__q46 } ;
assign result__h34437 =
{ {56{ld_val0074_BITS_55_TO_48__q47[7]}},
ld_val0074_BITS_55_TO_48__q47 } ;
assign result__h34465 =
{ {56{ld_val0074_BITS_63_TO_56__q49[7]}},
ld_val0074_BITS_63_TO_56__q49 } ;
assign result__h34510 = { 56'd0, ld_val__h30074[7:0] } ;
assign result__h34538 = { 56'd0, ld_val__h30074[15:8] } ;
assign result__h34566 = { 56'd0, ld_val__h30074[23:16] } ;
assign result__h34594 = { 56'd0, ld_val__h30074[31:24] } ;
assign result__h34622 = { 56'd0, ld_val__h30074[39:32] } ;
assign result__h34650 = { 56'd0, ld_val__h30074[47:40] } ;
assign result__h34678 = { 56'd0, ld_val__h30074[55:48] } ;
assign result__h34706 = { 56'd0, ld_val__h30074[63:56] } ;
assign result__h34751 =
{ {48{ld_val0074_BITS_15_TO_0__q37[15]}},
ld_val0074_BITS_15_TO_0__q37 } ;
assign result__h34779 =
{ {48{ld_val0074_BITS_31_TO_16__q41[15]}},
ld_val0074_BITS_31_TO_16__q41 } ;
assign result__h34807 =
{ {48{ld_val0074_BITS_47_TO_32__q44[15]}},
ld_val0074_BITS_47_TO_32__q44 } ;
assign result__h34835 =
{ {48{ld_val0074_BITS_63_TO_48__q48[15]}},
ld_val0074_BITS_63_TO_48__q48 } ;
assign result__h34876 = { 48'd0, ld_val__h30074[15:0] } ;
assign result__h34904 = { 48'd0, ld_val__h30074[31:16] } ;
assign result__h34932 = { 48'd0, ld_val__h30074[47:32] } ;
assign result__h34960 = { 48'd0, ld_val__h30074[63:48] } ;
assign result__h35001 =
{ {32{ld_val0074_BITS_31_TO_0__q38[31]}},
ld_val0074_BITS_31_TO_0__q38 } ;
assign result__h35029 =
{ {32{ld_val0074_BITS_63_TO_32__q45[31]}},
ld_val0074_BITS_63_TO_32__q45 } ;
assign result__h35068 = { 32'd0, ld_val__h30074[31:0] } ;
assign result__h35096 = { 32'd0, ld_val__h30074[63:32] } ;
assign result__h7925 =
{ {56{word64691_BITS_7_TO_0__q15[7]}},
word64691_BITS_7_TO_0__q15 } ;
assign rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613 =
rg_amo_funct7[6:2] == 5'b00010 &&
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) &&
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 =
rg_lrsc_pa == x1_avValue_pa__h6383 ;
assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ;
assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
tlb$lookup[68] ;
assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438 ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447 ;
assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ;
assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) &&
!cfg_verbosity_read__8_ULE_1___d19 ;
assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447 =
rg_op == 2'd1 &&
IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446 ;
assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632 ||
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 ;
assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759 ||
NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761 ;
assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) ;
assign rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248 =
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h15541 ||
!master_xactor_crg_wr_addr_full$port2__read &&
!master_xactor_crg_wr_data_full$port2__read &&
IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ;
assign rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 =
rg_priv == 2'b0 && !tlb$lookup[70] ||
rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM ||
dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100 &&
NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108 &&
(!dmem_not_imem || rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
!tlb$lookup[68]) ;
assign rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 =
rg_priv == 2'b0 && !tlb$lookup[70] ||
rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM ||
!dmem_not_imem ||
!tlb$lookup[68] ;
assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 =
rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 &&
tlb$lookup[130] &&
(rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 ||
NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ;
assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309 =
rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 &&
!tlb$lookup[130] ||
(rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ?
tlb$RDY_lookup :
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307) ;
assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356 =
rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 &&
(rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 ||
NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) &&
tlb$lookup[130] ;
assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 =
rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 &&
tlb$lookup[130] &&
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 &&
tlb$lookup[72] &&
tlb$lookup[73] &&
!pte___2__h6845[7] &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395 =
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ||
dmem_not_imem && !soc_map$m_is_mem_addr ||
rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387 ||
NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392 ;
assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 =
rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 &&
!tlb$lookup[130] ||
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395 ;
assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414 =
rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 &&
tlb$lookup[130] &&
NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406 &&
dmem_not_imem &&
tlb$lookup[68] &&
tlb$lookup[73] ;
assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417 =
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406 &&
(!dmem_not_imem || !tlb$lookup[68] || !tlb$lookup[73]) ;
assign rg_priv_9_ULE_0b1___d60 = rg_priv <= 2'b01 ;
assign rg_st_amo_val_BITS_31_TO_0__q31 = rg_st_amo_val[31:0] ;
assign rg_state_3_EQ_13_098_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1100 =
rg_state == 5'd13 &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
b__h23409 == 4'd0 ;
assign rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316 =
rg_state == 5'd3 &&
(rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
crg_sb_to_load_delay$port0__write_1 == 11'd0) ;
assign satp_pa__h2578 = { 8'd0, x__h5575 } ;
assign shift_bits__h18980 = { x1_avValue_pa__h6383[2:0], 3'b0 } ;
assign shift_bits__h32980 = { rg_pa[2:0], 3'b0 } ;
assign st_val__h32924 =
(rg_f3 == 3'b010) ?
new_st_val__h33210 :
_theResult_____2__h33206 ;
assign strobe64__h19115 = 8'b00000001 << x1_avValue_pa__h6383[2:0] ;
assign strobe64__h19118 = 8'b00000011 << x1_avValue_pa__h6383[2:0] ;
assign strobe64__h19121 = 8'b00001111 << x1_avValue_pa__h6383[2:0] ;
assign strobe64__h33115 = 8'b00000001 << rg_pa[2:0] ;
assign strobe64__h33118 = 8'b00000011 << rg_pa[2:0] ;
assign strobe64__h33121 = 8'b00001111 << rg_pa[2:0] ;
assign tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 =
tlb$lookup[67] | y__h6671 ;
assign tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 =
tlb$lookup[72] &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
tlb$lookup[73]) ;
assign value__h7170 =
(rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8) ?
_theResult___snd_snd_fst__h6476 :
tlb$lookup[129:66] ;
assign vpn_0_pa__h25506 = { 52'd0, rg_addr[20:12], 3'd0 } ;
assign vpn_1_pa__h24449 = { 52'd0, rg_addr[29:21], 3'd0 } ;
assign vpn_2_pa__h23507 = { 52'd0, rg_addr[38:30], 3'd0 } ;
assign w13194_BITS_31_TO_0__q51 = w1__h33194[31:0] ;
assign w1___1__h19975 = { 32'd0, new_value__h7872[31:0] } ;
assign w1___1__h33269 = { 32'd0, w1__h33194[31:0] } ;
assign w2___1__h33270 = { 32'd0, rg_st_amo_val[31:0] } ;
assign w2__h33200 = (rg_f3 == 3'b010) ? w2___1__h33270 : rg_st_amo_val ;
assign word64691_BITS_15_TO_0__q16 = word64__h7691[15:0] ;
assign word64691_BITS_15_TO_8__q18 = word64__h7691[15:8] ;
assign word64691_BITS_23_TO_16__q19 = word64__h7691[23:16] ;
assign word64691_BITS_31_TO_0__q17 = word64__h7691[31:0] ;
assign word64691_BITS_31_TO_16__q20 = word64__h7691[31:16] ;
assign word64691_BITS_31_TO_24__q21 = word64__h7691[31:24] ;
assign word64691_BITS_39_TO_32__q22 = word64__h7691[39:32] ;
assign word64691_BITS_47_TO_32__q23 = word64__h7691[47:32] ;
assign word64691_BITS_47_TO_40__q25 = word64__h7691[47:40] ;
assign word64691_BITS_55_TO_48__q26 = word64__h7691[55:48] ;
assign word64691_BITS_63_TO_32__q24 = word64__h7691[63:32] ;
assign word64691_BITS_63_TO_48__q27 = word64__h7691[63:48] ;
assign word64691_BITS_63_TO_56__q28 = word64__h7691[63:56] ;
assign word64691_BITS_7_TO_0__q15 = word64__h7691[7:0] ;
assign word64__h7691 = ram_word64_set$DOB & y__h7961 ;
assign x1_avValue_exc_code__h6384 =
dmem_not_imem ?
((rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd13 :
4'd15) :
4'd12 ;
assign x1_avValue_pa__h6383 = soc_map$m_is_mem_addr_addr ;
assign x__h15551 = { 63'd0, lrsc_result__h15541 } ;
assign x__h24553 = { master_xactor_rg_rd_data[56:13], 12'b0 } ;
assign x__h5575 = { rg_satp[43:0], 12'b0 } ;
assign x__h6856 = { tlb$lookup[119:76], rg_addr[11:0] } ;
assign x__h6905 = { tlb$lookup[119:85], rg_addr[20:0] } ;
assign x__h6974 = { tlb$lookup[119:94], rg_addr[29:0] } ;
assign y__h6671 = rg_mstatus_MXR & tlb$lookup[69] ;
assign y__h7961 =
{64{ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178}} ;
always@(rg_f3)
begin
case (rg_f3[1:0])
2'b0: value__h32497 = 3'b0;
2'b01: value__h32497 = 3'b001;
2'b10: value__h32497 = 3'b010;
2'd3: value__h32497 = 3'b011;
endcase
end
always@(rg_f3)
begin
case (rg_f3[1:0])
2'b0: value__h35523 = 3'b0;
2'b01: value__h35523 = 3'b001;
2'b10: value__h35523 = 3'b010;
2'b11: value__h35523 = 3'b011;
endcase
end
always@(tlb$lookup or
rg_addr or pa___1__h6853 or pa___1__h6902 or pa___1__h6971)
begin
case (tlb$lookup[65:64])
2'd0: _theResult___fst__h6847 = pa___1__h6853;
2'd1: _theResult___fst__h6847 = pa___1__h6902;
2'd2: _theResult___fst__h6847 = pa___1__h6971;
2'd3: _theResult___fst__h6847 = rg_addr;
endcase
end
always@(rg_f3 or strobe64__h33115 or strobe64__h33118 or strobe64__h33121)
begin
case (rg_f3[1:0])
2'b0: mem_req_wr_data_wstrb__h33185 = strobe64__h33115;
2'b01: mem_req_wr_data_wstrb__h33185 = strobe64__h33118;
2'b10: mem_req_wr_data_wstrb__h33185 = strobe64__h33121;
2'b11: mem_req_wr_data_wstrb__h33185 = 8'b11111111;
endcase
end
always@(rg_f3 or rg_st_amo_val or _theResult___fst__h31612)
begin
case (rg_f3[1:0])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h31680 = _theResult___fst__h31612;
2'd3: mem_req_wr_data_wdata__h31680 = rg_st_amo_val;
endcase
end
always@(rg_f3 or strobe64__h19115 or strobe64__h19118 or strobe64__h19121)
begin
case (rg_f3[1:0])
2'b0: mem_req_wr_data_wstrb__h19185 = strobe64__h19115;
2'b01: mem_req_wr_data_wstrb__h19185 = strobe64__h19118;
2'b10: mem_req_wr_data_wstrb__h19185 = strobe64__h19121;
2'b11: mem_req_wr_data_wstrb__h19185 = 8'b11111111;
endcase
end
always@(rg_f3 or rg_st_amo_val or _theResult___fst__h19116)
begin
case (rg_f3[1:0])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h19184 = _theResult___fst__h19116;
2'd3: mem_req_wr_data_wdata__h19184 = rg_st_amo_val;
endcase
end
always@(rg_f3 or rg_priv_9_ULE_0b1___d60 or rg_satp or tlb$RDY_lookup)
begin
case (rg_f3[1:0])
2'b0, 2'b01:
IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 =
!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup;
default: IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 =
rg_f3[1:0] != 2'b10 || !rg_priv_9_ULE_0b1___d60 ||
rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup;
endcase
end
always@(rg_addr or
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199)
begin
case (rg_addr[2:0])
3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 =
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199;
3'd7:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 =
rg_addr[2:0] != 3'h7 ||
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199;
endcase
end
always@(rg_addr or
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199)
begin
case (rg_addr[2:0])
3'h0, 3'h2, 3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 =
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 =
rg_addr[2:0] != 3'h6 ||
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199;
endcase
end
always@(rg_f3 or
rg_addr or
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217)
begin
case (rg_f3)
3'b0, 3'b100:
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203;
3'b001, 3'b101:
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211;
3'b010, 3'b110:
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217;
default: IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 =
rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 ||
NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199;
endcase
end
always@(rg_amo_funct7 or
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225)
begin
case (rg_amo_funct7[6:2])
5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100:
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 =
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225;
default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 =
rg_amo_funct7[6:2] != 5'b10100 ||
IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225;
endcase
end
always@(x1_avValue_pa__h6383 or
NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284 or
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29)
begin
case (x1_avValue_pa__h6383[2:0])
3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 =
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29;
3'd7:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 =
NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284;
endcase
end
always@(x1_avValue_pa__h6383 or
NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289 or
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29)
begin
case (x1_avValue_pa__h6383[2:0])
3'h0, 3'h2, 3'h4:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 =
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29;
default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 =
NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289;
endcase
end
always@(rg_f3 or
NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294 or
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 or
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 or
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293)
begin
case (rg_f3)
3'b0:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 =
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285;
3'b001:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 =
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290;
3'b010:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 =
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293;
default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 =
NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294;
endcase
end
always@(rg_addr or
result__h7925 or
result__h14281 or
result__h14309 or
result__h14337 or
result__h14365 or
result__h14393 or result__h14421 or result__h14449)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 =
result__h7925;
3'h1:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 =
result__h14281;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 =
result__h14309;
3'h3:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 =
result__h14337;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 =
result__h14365;
3'h5:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 =
result__h14393;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 =
result__h14421;
3'h7:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 =
result__h14449;
endcase
end
always@(rg_addr or
result__h14494 or
result__h14522 or
result__h14550 or
result__h14578 or
result__h14606 or
result__h14634 or result__h14662 or result__h14690)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 =
result__h14494;
3'h1:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 =
result__h14522;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 =
result__h14550;
3'h3:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 =
result__h14578;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 =
result__h14606;
3'h5:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 =
result__h14634;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 =
result__h14662;
3'h7:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 =
result__h14690;
endcase
end
always@(rg_addr or
result__h14735 or
result__h14763 or result__h14791 or result__h14819)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 =
result__h14735;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 =
result__h14763;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 =
result__h14791;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 =
result__h14819;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 =
64'd0;
endcase
end
always@(rg_addr or
result__h14860 or
result__h14888 or result__h14916 or result__h14944)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 =
result__h14860;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 =
result__h14888;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 =
result__h14916;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 =
result__h14944;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 =
64'd0;
endcase
end
always@(rg_addr or result__h15052 or result__h15080)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 =
result__h15052;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 =
result__h15080;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 =
64'd0;
endcase
end
always@(rg_addr or result__h14985 or result__h15013)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result4985_0x4_re_ETC__q30 =
result__h14985;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result4985_0x4_re_ETC__q30 =
result__h15013;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result4985_0x4_re_ETC__q30 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or
CASE_rg_addr_BITS_2_TO_0_0x0_result4985_0x4_re_ETC__q30 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562)
begin
case (rg_f3)
3'b0:
new_value__h7872 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516;
3'b001:
new_value__h7872 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544;
3'b010:
new_value__h7872 =
CASE_rg_addr_BITS_2_TO_0_0x0_result4985_0x4_re_ETC__q30;
3'b011:
new_value__h7872 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563;
3'b100:
new_value__h7872 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532;
3'b101:
new_value__h7872 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552;
3'b110:
new_value__h7872 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562;
3'd7: new_value__h7872 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or
w1___1__h19975 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562)
begin
case (rg_f3)
3'b0:
w1__h19904 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516;
3'b001:
w1__h19904 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544;
3'b010: w1__h19904 = w1___1__h19975;
3'b011:
w1__h19904 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563;
3'b100:
w1__h19904 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532;
3'b101:
w1__h19904 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552;
3'b110:
w1__h19904 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562;
3'd7: w1__h19904 = 64'd0;
endcase
end
always@(x1_avValue_pa__h6383 or ram_word64_set$DOB or rg_st_amo_val)
begin
case (x1_avValue_pa__h6383[2:0])
3'h0:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 =
{ ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] };
3'h2:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 =
{ ram_word64_set$DOB[63:32],
rg_st_amo_val[15:0],
ram_word64_set$DOB[15:0] };
3'h4:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 =
{ ram_word64_set$DOB[63:48],
rg_st_amo_val[15:0],
ram_word64_set$DOB[31:0] };
3'h6:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 =
{ rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] };
default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 =
ram_word64_set$DOB;
endcase
end
always@(x1_avValue_pa__h6383 or ram_word64_set$DOB or rg_st_amo_val)
begin
case (x1_avValue_pa__h6383[2:0])
3'h0:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 =
{ ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] };
3'h1:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 =
{ ram_word64_set$DOB[63:16],
rg_st_amo_val[7:0],
ram_word64_set$DOB[7:0] };
3'h2:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 =
{ ram_word64_set$DOB[63:24],
rg_st_amo_val[7:0],
ram_word64_set$DOB[15:0] };
3'h3:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 =
{ ram_word64_set$DOB[63:32],
rg_st_amo_val[7:0],
ram_word64_set$DOB[23:0] };
3'h4:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 =
{ ram_word64_set$DOB[63:40],
rg_st_amo_val[7:0],
ram_word64_set$DOB[31:0] };
3'h5:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 =
{ ram_word64_set$DOB[63:48],
rg_st_amo_val[7:0],
ram_word64_set$DOB[39:0] };
3'h6:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 =
{ ram_word64_set$DOB[63:56],
rg_st_amo_val[7:0],
ram_word64_set$DOB[47:0] };
3'h7:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 =
{ rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] };
endcase
end
always@(rg_f3 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or
new_value872_BITS_31_TO_0__q32 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562)
begin
case (rg_f3)
3'b0:
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516;
3'b001:
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544;
3'b010:
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 =
{ {32{new_value872_BITS_31_TO_0__q32[31]}},
new_value872_BITS_31_TO_0__q32 };
3'b011:
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563;
3'b100:
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532;
3'b101:
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552;
3'b110:
IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562;
3'd7: IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h21015 or
new_st_val__h20007 or
w2__h33200 or
new_st_val__h20987 or
new_st_val__h20995 or
new_st_val__h20991 or
new_st_val__h21010 or new_st_val__h20999 or new_st_val__h21004)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h19912 = new_st_val__h20007;
5'b00001: _theResult_____2__h19912 = w2__h33200;
5'b00100: _theResult_____2__h19912 = new_st_val__h20987;
5'b01000: _theResult_____2__h19912 = new_st_val__h20995;
5'b01100: _theResult_____2__h19912 = new_st_val__h20991;
5'b10000: _theResult_____2__h19912 = new_st_val__h21010;
5'b11000: _theResult_____2__h19912 = new_st_val__h20999;
5'b11100: _theResult_____2__h19912 = new_st_val__h21004;
default: _theResult_____2__h19912 = new_st_val__h21015;
endcase
end
always@(rg_f3 or new_st_val__h19634 or _theResult___fst__h22552)
begin
case (rg_f3[1:0])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h22620 = _theResult___fst__h22552;
2'd3: mem_req_wr_data_wdata__h22620 = new_st_val__h19634;
endcase
end
always@(x1_avValue_pa__h6383 or ram_word64_set$DOB or new_st_val__h19634)
begin
case (x1_avValue_pa__h6383[2:0])
3'h0:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 =
{ ram_word64_set$DOB[63:16], new_st_val__h19634[15:0] };
3'h2:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 =
{ ram_word64_set$DOB[63:32],
new_st_val__h19634[15:0],
ram_word64_set$DOB[15:0] };
3'h4:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 =
{ ram_word64_set$DOB[63:48],
new_st_val__h19634[15:0],
ram_word64_set$DOB[31:0] };
3'h6:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 =
{ new_st_val__h19634[15:0], ram_word64_set$DOB[47:0] };
default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 =
ram_word64_set$DOB;
endcase
end
always@(x1_avValue_pa__h6383 or ram_word64_set$DOB or new_st_val__h19634)
begin
case (x1_avValue_pa__h6383[2:0])
3'h0:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 =
{ ram_word64_set$DOB[63:8], new_st_val__h19634[7:0] };
3'h1:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 =
{ ram_word64_set$DOB[63:16],
new_st_val__h19634[7:0],
ram_word64_set$DOB[7:0] };
3'h2:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 =
{ ram_word64_set$DOB[63:24],
new_st_val__h19634[7:0],
ram_word64_set$DOB[15:0] };
3'h3:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 =
{ ram_word64_set$DOB[63:32],
new_st_val__h19634[7:0],
ram_word64_set$DOB[23:0] };
3'h4:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 =
{ ram_word64_set$DOB[63:40],
new_st_val__h19634[7:0],
ram_word64_set$DOB[31:0] };
3'h5:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 =
{ ram_word64_set$DOB[63:48],
new_st_val__h19634[7:0],
ram_word64_set$DOB[39:0] };
3'h6:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 =
{ ram_word64_set$DOB[63:56],
new_st_val__h19634[7:0],
ram_word64_set$DOB[47:0] };
3'h7:
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 =
{ new_st_val__h19634[7:0], ram_word64_set$DOB[55:0] };
endcase
end
always@(x1_avValue_pa__h6383 or ram_word64_set$DOB or rg_st_amo_val)
begin
case (x1_avValue_pa__h6383[2:0])
3'h0:
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q33 =
{ ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] };
3'h4:
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q33 =
{ rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] };
default: CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q33 =
ram_word64_set$DOB;
endcase
end
always@(rg_f3 or
ram_word64_set$DOB or
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 or
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 or
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q33 or
rg_st_amo_val)
begin
case (rg_f3)
3'b0:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 =
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672;
3'b001:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 =
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681;
3'b010:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 =
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q33;
3'b011:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 =
rg_st_amo_val;
default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 =
ram_word64_set$DOB;
endcase
end
always@(rg_addr or
result__h30724 or
result__h30751 or result__h30778 or result__h30805)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1174 =
result__h30724;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1174 =
result__h30751;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1174 =
result__h30778;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1174 =
result__h30805;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1174 =
64'd0;
endcase
end
always@(rg_addr or
result__h30603 or
result__h30630 or result__h30657 or result__h30684)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1166 =
result__h30603;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1166 =
result__h30630;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1166 =
result__h30657;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1166 =
result__h30684;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1166 =
64'd0;
endcase
end
always@(rg_addr or
result__h30370 or
result__h30397 or
result__h30424 or
result__h30451 or
result__h30478 or
result__h30505 or result__h30532 or result__h30559)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 =
result__h30370;
3'h1:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 =
result__h30397;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 =
result__h30424;
3'h3:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 =
result__h30451;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 =
result__h30478;
3'h5:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 =
result__h30505;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 =
result__h30532;
3'h7:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 =
result__h30559;
endcase
end
always@(rg_addr or
result__h30134 or
result__h30164 or
result__h30191 or
result__h30218 or
result__h30245 or
result__h30272 or result__h30299 or result__h30326)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 =
result__h30134;
3'h1:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 =
result__h30164;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 =
result__h30191;
3'h3:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 =
result__h30218;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 =
result__h30245;
3'h5:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 =
result__h30272;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 =
result__h30299;
3'h7:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 =
result__h30326;
endcase
end
always@(rg_addr or result__h30845 or result__h30872)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result0845_0x4_re_ETC__q34 =
result__h30845;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result0845_0x4_re_ETC__q34 =
result__h30872;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result0845_0x4_re_ETC__q34 =
64'd0;
endcase
end
always@(rg_addr or result__h30910 or result__h30937)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result0910_0x4_re_ETC__q35 =
result__h30910;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result0910_0x4_re_ETC__q35 =
result__h30937;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result0910_0x4_re_ETC__q35 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1166 or
CASE_rg_addr_BITS_2_TO_0_0x0_result0845_0x4_re_ETC__q34 or
rg_addr or
master_xactor_rg_rd_data or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1174 or
CASE_rg_addr_BITS_2_TO_0_0x0_result0910_0x4_re_ETC__q35)
begin
case (rg_f3)
3'b0:
ld_val__h30074 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1138;
3'b001:
ld_val__h30074 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1166;
3'b010:
ld_val__h30074 =
CASE_rg_addr_BITS_2_TO_0_0x0_result0845_0x4_re_ETC__q34;
3'b011:
ld_val__h30074 =
(rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0;
3'b100:
ld_val__h30074 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1154;
3'b101:
ld_val__h30074 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1174;
3'b110:
ld_val__h30074 =
CASE_rg_addr_BITS_2_TO_0_0x0_result0910_0x4_re_ETC__q35;
3'd7: ld_val__h30074 = 64'd0;
endcase
end
always@(rg_addr or result__h35068 or result__h35096)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308 =
result__h35068;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308 =
result__h35096;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308 =
64'd0;
endcase
end
always@(rg_addr or
result__h34876 or
result__h34904 or result__h34932 or result__h34960)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 =
result__h34876;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 =
result__h34904;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 =
result__h34932;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 =
result__h34960;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 =
64'd0;
endcase
end
always@(rg_addr or
result__h34751 or
result__h34779 or result__h34807 or result__h34835)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290 =
result__h34751;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290 =
result__h34779;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290 =
result__h34807;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290 =
result__h34835;
default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290 =
64'd0;
endcase
end
always@(rg_addr or
result__h34510 or
result__h34538 or
result__h34566 or
result__h34594 or
result__h34622 or
result__h34650 or result__h34678 or result__h34706)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 =
result__h34510;
3'h1:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 =
result__h34538;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 =
result__h34566;
3'h3:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 =
result__h34594;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 =
result__h34622;
3'h5:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 =
result__h34650;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 =
result__h34678;
3'h7:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 =
result__h34706;
endcase
end
always@(rg_addr or
result__h33389 or
result__h34297 or
result__h34325 or
result__h34353 or
result__h34381 or
result__h34409 or result__h34437 or result__h34465)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 =
result__h33389;
3'h1:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 =
result__h34297;
3'h2:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 =
result__h34325;
3'h3:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 =
result__h34353;
3'h4:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 =
result__h34381;
3'h5:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 =
result__h34409;
3'h6:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 =
result__h34437;
3'h7:
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 =
result__h34465;
endcase
end
always@(rg_addr or result__h35001 or result__h35029)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result5001_0x4_re_ETC__q50 =
result__h35001;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result5001_0x4_re_ETC__q50 =
result__h35029;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result5001_0x4_re_ETC__q50 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290 or
CASE_rg_addr_BITS_2_TO_0_0x0_result5001_0x4_re_ETC__q50 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1309 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308)
begin
case (rg_f3)
3'b0:
w1__h33194 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262;
3'b001:
w1__h33194 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290;
3'b010:
w1__h33194 =
CASE_rg_addr_BITS_2_TO_0_0x0_result5001_0x4_re_ETC__q50;
3'b011:
w1__h33194 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1309;
3'b100:
w1__h33194 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278;
3'b101:
w1__h33194 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298;
3'b110:
w1__h33194 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308;
3'd7: w1__h33194 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290 or
w1___1__h33269 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1309 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308)
begin
case (rg_f3)
3'b0:
w1__h33198 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262;
3'b001:
w1__h33198 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290;
3'b010: w1__h33198 = w1___1__h33269;
3'b011:
w1__h33198 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1309;
3'b100:
w1__h33198 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278;
3'b101:
w1__h33198 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298;
3'b110:
w1__h33198 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308;
3'd7: w1__h33198 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290 or
w13194_BITS_31_TO_0__q51 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1309 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 or
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308)
begin
case (rg_f3)
3'b0:
new_ld_val__h32912 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1262;
3'b001:
new_ld_val__h32912 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1290;
3'b010:
new_ld_val__h32912 =
{ {32{w13194_BITS_31_TO_0__q51[31]}},
w13194_BITS_31_TO_0__q51 };
3'b011:
new_ld_val__h32912 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1309;
3'b100:
new_ld_val__h32912 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1278;
3'b101:
new_ld_val__h32912 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298;
3'b110:
new_ld_val__h32912 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1308;
3'd7: new_ld_val__h32912 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h35189 or
new_st_val__h33301 or
w2__h33200 or
new_st_val__h35161 or
new_st_val__h35169 or
new_st_val__h35165 or
new_st_val__h35184 or new_st_val__h35173 or new_st_val__h35178)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h33206 = new_st_val__h33301;
5'b00001: _theResult_____2__h33206 = w2__h33200;
5'b00100: _theResult_____2__h33206 = new_st_val__h35161;
5'b01000: _theResult_____2__h33206 = new_st_val__h35169;
5'b01100: _theResult_____2__h33206 = new_st_val__h35165;
5'b10000: _theResult_____2__h33206 = new_st_val__h35184;
5'b11000: _theResult_____2__h33206 = new_st_val__h35173;
5'b11100: _theResult_____2__h33206 = new_st_val__h35178;
default: _theResult_____2__h33206 = new_st_val__h35189;
endcase
end
always@(rg_f3 or st_val__h32924 or _theResult___fst__h33116)
begin
case (rg_f3[1:0])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h33184 = _theResult___fst__h33116;
2'd3: mem_req_wr_data_wdata__h33184 = st_val__h32924;
endcase
end
always@(x1_avValue_pa__h6383 or ram_word64_set$DOB or new_st_val__h19634)
begin
case (x1_avValue_pa__h6383[2:0])
3'h0:
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q52 =
{ ram_word64_set$DOB[63:32], new_st_val__h19634[31:0] };
3'h4:
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q52 =
{ new_st_val__h19634[31:0], ram_word64_set$DOB[31:0] };
default: CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q52 =
ram_word64_set$DOB;
endcase
end
always@(rg_f3 or
ram_word64_set$DOB or
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 or
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 or
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q52 or
new_st_val__h19634)
begin
case (rg_f3)
3'b0:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 =
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737;
3'b001:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 =
IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746;
3'b010:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 =
CASE_x1_avValue_pa383_BITS_2_TO_0_0x0_ram_word_ETC__q52;
3'b011:
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 =
new_st_val__h19634;
default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 =
ram_word64_set$DOB;
endcase
end
always@(rg_f3 or IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577)
begin
case (rg_f3)
3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
new_value__h17899 =
IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577;
3'd7: new_value__h17899 = 64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0;
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0;
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_requesting_cline <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (crg_sb_to_load_delay$EN)
crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY
crg_sb_to_load_delay$D_IN;
if (ctr_wr_rsps_pending_crg$EN)
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
ctr_wr_rsps_pending_crg$D_IN;
if (master_xactor_crg_rd_addr_full$EN)
master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
master_xactor_crg_rd_addr_full$D_IN;
if (master_xactor_crg_rd_data_full$EN)
master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
master_xactor_crg_rd_data_full$D_IN;
if (master_xactor_crg_wr_addr_full$EN)
master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
master_xactor_crg_wr_addr_full$D_IN;
if (master_xactor_crg_wr_data_full$EN)
master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
master_xactor_crg_wr_data_full$D_IN;
if (master_xactor_crg_wr_resp_full$EN)
master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
master_xactor_crg_wr_resp_full$D_IN;
if (rg_cset_in_cache$EN)
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
if (rg_lower_word32_full$EN)
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
rg_lower_word32_full$D_IN;
if (rg_lrsc_valid$EN)
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
if (rg_requesting_cline$EN)
rg_requesting_cline <= `BSV_ASSIGNMENT_DELAY
rg_requesting_cline$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (master_xactor_rg_rd_addr$EN)
master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
master_xactor_rg_rd_addr$D_IN;
if (master_xactor_rg_rd_data$EN)
master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
master_xactor_rg_rd_data$D_IN;
if (master_xactor_rg_wr_addr$EN)
master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
master_xactor_rg_wr_addr$D_IN;
if (master_xactor_rg_wr_data$EN)
master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
master_xactor_rg_wr_data$D_IN;
if (master_xactor_rg_wr_resp$EN)
master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
master_xactor_rg_wr_resp$D_IN;
if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
if (rg_amo_funct7$EN)
rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
if (rg_error_during_refill$EN)
rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
rg_error_during_refill$D_IN;
if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
if (rg_lower_word32$EN)
rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
if (rg_mstatus_MXR$EN)
rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN;
if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
if (rg_req_byte_in_cline$EN)
rg_req_byte_in_cline <= `BSV_ASSIGNMENT_DELAY rg_req_byte_in_cline$D_IN;
if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN;
if (rg_sstatus_SUM$EN)
rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
if (rg_st_amo_val$EN)
rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
if (rg_word64_set_in_cache$EN)
rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY
rg_word64_set_in_cache$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
crg_sb_to_load_delay = 11'h2AA;
ctr_wr_rsps_pending_crg = 4'hA;
master_xactor_crg_rd_addr_full = 1'h0;
master_xactor_crg_rd_data_full = 1'h0;
master_xactor_crg_wr_addr_full = 1'h0;
master_xactor_crg_wr_data_full = 1'h0;
master_xactor_crg_wr_resp_full = 1'h0;
master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA;
master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA;
master_xactor_rg_wr_resp = 6'h2A;
rg_addr = 64'hAAAAAAAAAAAAAAAA;
rg_amo_funct7 = 7'h2A;
rg_cset_in_cache = 6'h2A;
rg_error_during_refill = 1'h0;
rg_exc_code = 4'hA;
rg_f3 = 3'h2;
rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
rg_lower_word32 = 32'hAAAAAAAA;
rg_lower_word32_full = 1'h0;
rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA;
rg_lrsc_valid = 1'h0;
rg_mstatus_MXR = 1'h0;
rg_op = 2'h2;
rg_pa = 64'hAAAAAAAAAAAAAAAA;
rg_priv = 2'h2;
rg_pte_pa = 64'hAAAAAAAAAAAAAAAA;
rg_req_byte_in_cline = 64'hAAAAAAAAAAAAAAAA;
rg_requesting_cline = 1'h0;
rg_satp = 64'hAAAAAAAAAAAAAAAA;
rg_sstatus_SUM = 1'h0;
rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
rg_state = 5'h0A;
rg_word64_set_in_cache = 9'h0AA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
begin
v__h4901 = $stime;
#0;
end
v__h4895 = v__h4901 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4895,
"D_MMU_Cache",
$signed(32'd64),
$signed(32'd1));
else
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4895,
"I_MMU_Cache",
$signed(32'd64),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
!cfg_verbosity_read__8_ULE_1___d19 &&
f_reset_reqs$D_OUT)
begin
v__h5002 = $stime;
#0;
end
v__h4996 = v__h5002 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
!cfg_verbosity_read__8_ULE_1___d19 &&
f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: Flushed", v__h4996, "D_MMU_Cache");
else
$display("%0d: %s.rl_reset: Flushed", v__h4996, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__8_ULE_1___d19)
$display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
rg_addr[11:6],
rg_addr[11:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h31277 = $stime;
#0;
end
v__h31271 = v__h31277 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31271,
"D_MMU_Cache",
rg_addr,
rg_ld_val);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31271,
"I_MMU_Cache",
rg_addr,
rg_ld_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19)
begin
v__h32175 = $stime;
#0;
end
v__h32169 = v__h32175 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32169,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32169,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19)
$display(" FAIL due to I/O address.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__8_ULE_1___d19)
begin
v__h4532 = $stime;
#0;
end
v__h4526 = v__h4532 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_start_reset", v__h4526, "D_MMU_Cache");
else
$display("%0d: %s.rl_start_reset", v__h4526, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937)
begin
v__h24418 = $stime;
#0;
end
v__h24412 = v__h24418 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h24412,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa,
exc_code___1__h6745);
else
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h24412,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa,
exc_code___1__h6745);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
begin
v__h24175 = $stime;
#0;
end
v__h24169 = v__h24175 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
if (dmem_not_imem)
$display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1",
v__h24169,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1",
v__h24169,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$display(" Req for level 1 PTE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", lev_1_pte_pa_w64_fa__h24452);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963)
begin
v__h24729 = $stime;
#0;
end
v__h24723 = v__h24729 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h",
v__h24723,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h",
v__h24723,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
(master_xactor_rg_rd_data[30:22] != 9'd0 ||
master_xactor_rg_rd_data[21:13] != 9'd0))
$display(" Invalid PTE: PPN[1] or PPN[0] is not zero; page fault %0d",
exc_code___1__h6745);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975)
begin
v__h24841 = $stime;
#0;
end
v__h24835 = v__h24841 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage",
v__h24835,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage",
v__h24835,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975)
$display(" Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h24448);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h24347 = $stime;
#0;
end
v__h24341 = v__h24347 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h24341,
"D_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h3321);
else
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h24341,
"I_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h3321);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937)
begin
v__h25475 = $stime;
#0;
end
v__h25469 = v__h25475 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h25469,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa,
exc_code___1__h6745);
else
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h25469,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa,
exc_code___1__h6745);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
begin
v__h25235 = $stime;
#0;
end
v__h25229 = v__h25235 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
if (dmem_not_imem)
$display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
v__h25229,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
v__h25229,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$display(" Req for level 0 PTE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", lev_0_pte_pa_w64_fa__h25509);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010)
begin
v__h25898 = $stime;
#0;
end
v__h25892 = v__h25898 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
v__h25892,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
v__h25892,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010)
$display(" Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h24448);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016)
begin
v__h25786 = $stime;
#0;
end
v__h25780 = v__h25786 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
v__h25780,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
v__h25780,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
master_xactor_rg_rd_data[3] &&
(master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) &&
(master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) &&
master_xactor_rg_rd_data[21:13] != 9'd0)
$display(" Invalid PTE: PPN [0] is not zero; page fault %0d",
exc_code___1__h6745);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h25404 = $stime;
#0;
end
v__h25398 = v__h25404 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h25398,
"D_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h3321);
else
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h25398,
"I_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h3321);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937)
begin
v__h26370 = $stime;
#0;
end
v__h26364 = v__h26370 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h26364,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa,
exc_code___1__h6745);
else
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h26364,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa,
exc_code___1__h6745);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
begin
v__h26441 = $stime;
#0;
end
v__h26435 = v__h26441 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
v__h26435,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa,
exc_code___1__h6745);
else
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
v__h26435,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa,
exc_code___1__h6745);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041)
begin
v__h26523 = $stime;
#0;
end
v__h26517 = v__h26523 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
v__h26517,
"D_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
v__h26517,
"I_MMU_Cache",
rg_addr,
master_xactor_rg_rd_data[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041)
$display(" Addr Space page pa: 0x%0h", lev_1_PTN_pa__h24448);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h26299 = $stime;
#0;
end
v__h26293 = v__h26299 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h26293,
"D_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h3321);
else
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h26293,
"I_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h3321);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
begin
v__h27433 = $stime;
#0;
end
v__h27427 = v__h27433 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_req_loop",
v__h27427,
"D_MMU_Cache");
else
$display("%0d: %s.rl_cache_refill_req_loop",
v__h27427,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", cline_fabric_addr__h27486);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_req_loop &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h5455 = $stime;
#0;
end
v__h5449 = v__h5455 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h5449,
"D_MMU_Cache",
rg_addr);
else
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h5449,
"I_MMU_Cache",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
rg_satp[63:60] != 4'd0)
$display(" Priv:%0d SATP:{mode %0d asid %0h pa %0h} VA:%0h.%0h.%0h",
rg_priv,
rg_satp[63:60],
rg_satp[59:44],
satp_pa__h2578,
rg_addr[29:21],
rg_addr[20:12],
rg_addr[11:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}",
rg_addr[63:12],
rg_addr[11:6],
rg_addr[5:3],
rg_addr[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" CSet 0x%0x: (state, tag):", rg_addr[11:6]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
ram_state_and_ctag_cset$DOB[52])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
!ram_state_and_ctag_cset$DOB[52])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
ram_state_and_ctag_cset$DOB[52])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
!ram_state_and_ctag_cset$DOB[52])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" 0x%0x", ram_word64_set$DOB);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" TLB result: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("VM_Xlate_Result { ", "outcome: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353)
$write("VM_XLATE_OK");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356)
$write("VM_XLATE_EXCEPTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
rg_priv_9_ULE_0b1___d60 &&
rg_satp[63:60] == 4'd8 &&
!tlb$lookup[130])
$write("VM_XLATE_TLB_MISS");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", x1_avValue_exc_code__h6384);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "pte_modified: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "pte: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", value__h7170, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$display(" fa_record_pte_A_D_updates:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("TLB_Lookup_Result { ", "hit: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(", ", "pte: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("'h%h", tlb$lookup[129:66]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(", ", "pte_level: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("'h%h", tlb$lookup[65:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(", ", "pte_pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("'h%h", tlb$lookup[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("VM_Xlate_Result { ", "outcome: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414)
$write("VM_XLATE_OK");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417)
$write("VM_XLATE_EXCEPTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(", ", "pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("'h%h", x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("'h%h", x1_avValue_exc_code__h6384);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(", ", "pte_modified: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write(", ", "pte: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("'h%h", value__h7170, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 &&
NOT_cfg_verbosity_read__8_ULT_2_05___d406)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431)
$display(" => IO_REQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591)
begin
v__h15164 = $stime;
#0;
end
v__h15158 = v__h15164 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h15158,
"D_MMU_Cache",
rg_addr,
word64__h7691,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h15158,
"I_MMU_Cache",
rg_addr,
word64__h7691,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604)
$display(" AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591)
$display(" Read-hit: addr 0x%0h word64 0x%0h",
rg_addr,
word64__h7691);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610)
$display(" Read Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616)
$display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
rg_lrsc_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800)
$display(" ST: cancelling LR/SC reservation for PA",
x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806)
$display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
rg_lrsc_pa,
x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812)
$display(" AMO SC: fail due to invalid LR/SC reservation");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818)
$display(" AMO SC result = %0d", lrsc_result__h15541);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824)
$display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h",
x1_avValue_pa__h6383,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824)
$write(" 0x%0x",
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829)
$display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h",
x1_avValue_pa__h6383,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842)
begin
v__h19383 = $stime;
#0;
end
v__h19377 = v__h19383 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842)
$display("%0d: ERROR: CreditCounter: overflow", v__h19377);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", value__h35523);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("AXI4_Wr_Data { ", "wid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", mem_req_wr_data_wdata__h19184);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", mem_req_wr_data_wstrb__h19185);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836)
$display(" => rl_write_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850)
begin
v__h18808 = $stime;
#0;
end
v__h18802 = v__h18808 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h18802,
"D_MMU_Cache",
rg_addr,
64'd1,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h18802,
"I_MMU_Cache",
rg_addr,
64'd1,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850)
$display(" AMO SC: Fail response for addr 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857)
$display(" AMO Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
rg_addr,
rg_amo_funct7,
rg_f3,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$display(" PA 0x%0h ", x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$display(" Cache word64 0x%0h, load-result 0x%0h",
word64__h7691,
word64__h7691);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$display(" 0x%0h op 0x%0h -> 0x%0h",
word64__h7691,
word64__h7691,
new_st_val__h19634);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(" 0x%0x",
IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868)
begin
v__h22819 = $stime;
#0;
end
v__h22813 = v__h22819 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868)
$display("%0d: ERROR: CreditCounter: overflow", v__h22813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", value__h35523);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("AXI4_Wr_Data { ", "wid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", mem_req_wr_data_wdata__h22620);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", mem_req_wr_data_wstrb__h19185);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876)
$display(" AMO_op: cancelling LR/SC reservation for PA",
x1_avValue_pa__h6383);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
begin
v__h27770 = $stime;
#0;
end
v__h27764 = v__h27770 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27764,
"D_MMU_Cache");
else
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27764,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write("'h%h", master_xactor_rg_rd_data[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write("'h%h", master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write("'h%h", master_xactor_rg_rd_data[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061 &&
master_xactor_rg_rd_data[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061 &&
!master_xactor_rg_rd_data[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h27992 = $stime;
#0;
end
v__h27986 = v__h27992 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27986,
"D_MMU_Cache",
access_exc_code__h3321);
else
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27986,
"I_MMU_Cache",
access_exc_code__h3321);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd7 &&
(master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) &&
!cfg_verbosity_read__8_ULE_1___d19)
$display(" => MODULE_EXCEPTION_RSP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd7 &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!rg_error_during_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$display(" => CACHE_REREQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new",
rg_word64_set_in_cache,
rg_word64_set_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_word64_set_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(" 0x%0x", ram_word64_set$DOB);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_word64_set_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write(" 0x%0x", master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__8_ULE_2_060___d1061)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
begin
v__h29965 = $stime;
#0;
end
v__h29959 = v__h29965 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h29959,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h29959,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", master_xactor_rg_rd_data[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", master_xactor_rg_rd_data[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19 &&
master_xactor_rg_rd_data[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19 &&
!master_xactor_rg_rd_data[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h31065 = $stime;
#0;
end
v__h31059 = v__h31065 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31059,
"D_MMU_Cache",
rg_addr,
ld_val__h30074);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31059,
"I_MMU_Cache",
rg_addr,
ld_val__h30074);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h31172 = $stime;
#0;
end
v__h31166 = v__h31172 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31166,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31166,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
begin
v__h31357 = $stime;
#0;
end
v__h31351 = v__h31357 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31351,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31351,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15)
begin
v__h31879 = $stime;
#0;
end
v__h31873 = v__h31879 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15)
$display("%0d: ERROR: CreditCounter: overflow", v__h31873);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", value__h35523);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Wr_Data { ", "wid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", mem_req_wr_data_wdata__h31680);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", mem_req_wr_data_wstrb__h33185);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
begin
v__h32293 = $stime;
#0;
end
v__h32287 = v__h32293 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32287,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32287,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", value__h32497);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
ctr_wr_rsps_pending_crg == 4'd15)
begin
v__h3875 = $stime;
#0;
end
v__h3869 = v__h3875 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
ctr_wr_rsps_pending_crg == 4'd15)
$display("%0d: ERROR: CreditCounter: overflow", v__h3869);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
ctr_wr_rsps_pending_crg == 4'd15)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", f_pte_writebacks$D_OUT[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Wr_Data { ", "wid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", f_pte_writebacks$D_OUT[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd255);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_updated_PTE &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h32611 = $stime;
#0;
end
v__h32605 = v__h32611 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32605,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32605,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", master_xactor_rg_rd_data[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", master_xactor_rg_rd_data[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
master_xactor_rg_rd_data[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19 &&
!master_xactor_rg_rd_data[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h32786 = $stime;
#0;
end
v__h32780 = v__h32786 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32780,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32780,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
ctr_wr_rsps_pending_crg == 4'd15)
begin
v__h35399 = $stime;
#0;
end
v__h35393 = v__h35399 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
ctr_wr_rsps_pending_crg == 4'd15)
$display("%0d: ERROR: CreditCounter: overflow", v__h35393);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
ctr_wr_rsps_pending_crg == 4'd15)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", value__h35523);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Wr_Data { ", "wid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", mem_req_wr_data_wdata__h33184);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", mem_req_wr_data_wstrb__h33185);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h35651 = $stime;
#0;
end
v__h35645 = v__h35651 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h35645,
"D_MMU_Cache",
rg_addr,
new_ld_val__h32912);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h35645,
"I_MMU_Cache",
rg_addr,
new_ld_val__h32912);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h32882 = $stime;
#0;
end
v__h32876 = v__h32882 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_rg_rd_data[2:1] != 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32876,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32876,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h23455 = $stime;
#0;
end
v__h23449 = v__h23455 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE",
v__h23449,
"D_MMU_Cache",
rg_addr);
else
$display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE",
v__h23449,
"I_MMU_Cache",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", lev_2_pte_pa_w64_fa__h23510);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h26650 = $stime;
#0;
end
v__h26644 = v__h26650 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_start_cache_refill: ",
v__h26644,
"D_MMU_Cache");
else
$display("%0d: %s.rl_start_cache_refill: ",
v__h26644,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", cline_addr__h27485);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__8_ULE_1___d19)
$display(" Victim way %0d; => CACHE_REFILL", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
begin
v__h29591 = $stime;
#0;
end
v__h29585 = v__h29591 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h29585,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h29585,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", value__h32497);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19)
begin
v__h36621 = $stime;
#0;
end
v__h36615 = v__h36621 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$write("%0d: %s.req: op:", v__h36615, "D_MMU_Cache");
else
$write("%0d: %s.req: op:", v__h36615, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op == 2'd0)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op == 2'd1)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op != 2'd0 &&
req_op != 2'd1)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(" f3:%0d addr:0x%0h st_value:0x%0h priv:",
req_f3,
req_addr,
req_st_value);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b0)
$write("U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b01)
$write("S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b11)
$write("M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv != 2'b0 &&
req_priv != 2'b01 &&
req_priv != 2'b11)
$write("RESERVED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__8_ULE_1___d19)
$display(" amo_funct7 = 0x%0h", req_amo_funct7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req &&
req_f3_BITS_1_TO_0_399_EQ_0b0_400_OR_req_f3_BI_ETC___d1429 &&
!cfg_verbosity_read__8_ULE_1___d19)
$display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
req_addr[11:6],
req_addr[11:3]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_tlb_flush && !cfg_verbosity_read__8_ULE_1___d19)
begin
v__h37775 = $stime;
#0;
end
v__h37769 = v__h37775 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_tlb_flush && !cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$display("%0d: %s.tlb_flush", v__h37769, "D_MMU_Cache");
else
$display("%0d: %s.tlb_flush", v__h37769, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
begin
v__h36271 = $stime;
#0;
end
v__h36265 = v__h36271 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
if (dmem_not_imem)
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h36265,
"D_MMU_Cache",
$unsigned(b__h23409));
else
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h36265,
"I_MMU_Cache",
$unsigned(b__h23409));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", master_xactor_rg_wr_resp[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", master_xactor_rg_wr_resp[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] == 2'b0 &&
!cfg_verbosity_read__8_ULE_1___d19)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
begin
v__h36232 = $stime;
#0;
end
v__h36226 = v__h36232 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
if (dmem_not_imem)
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h36226,
"D_MMU_Cache");
else
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h36226,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", master_xactor_rg_wr_resp[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", master_xactor_rg_wr_resp[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("\n");
end
// synopsys translate_on
endmodule // mkMMU_Cache
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