113f888d37
New method 'debug_external_interrupt_req' to support emulation of a debug module starts at P3_Core interface and is plumbed all the way in to the CSR register MIP as interrupt [14]. The corresponding MIE[14] is always 1, so it is never masked. Still todo: should not be masked by MSTATUS interrupt-enables either. Also expanded interrupt-detection logic, mcause etc. to extend up to interrupt 14. Builds in standalone mode, runs ISA tests. Builds in src_SSITH_P3, generating RTL.
618 lines
21 KiB
Verilog
618 lines
21 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_flush O 1 const
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// lookup O 131
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// RDY_lookup O 1
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// RDY_insert O 1
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// CLK I 1 clock
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// RST_N I 1 reset
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// lookup_asid I 16
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// lookup_vpn I 27
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// insert_asid I 16 reg
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// insert_vpn I 27
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// insert_pte I 64 reg
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// insert_level I 2
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// insert_pte_pa I 64 reg
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// EN_flush I 1
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// EN_insert I 1
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//
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// Combinational paths from inputs to outputs:
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// (lookup_asid, lookup_vpn) -> lookup
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkTLB(CLK,
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RST_N,
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EN_flush,
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RDY_flush,
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lookup_asid,
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lookup_vpn,
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lookup,
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RDY_lookup,
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insert_asid,
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insert_vpn,
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insert_pte,
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insert_level,
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insert_pte_pa,
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EN_insert,
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RDY_insert);
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parameter [0 : 0] dmem_not_imem = 1'b0;
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input CLK;
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input RST_N;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method lookup
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input [15 : 0] lookup_asid;
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input [26 : 0] lookup_vpn;
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output [130 : 0] lookup;
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output RDY_lookup;
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// action method insert
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input [15 : 0] insert_asid;
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input [26 : 0] insert_vpn;
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input [63 : 0] insert_pte;
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input [1 : 0] insert_level;
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input [63 : 0] insert_pte_pa;
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input EN_insert;
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output RDY_insert;
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// signals for module outputs
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wire [130 : 0] lookup;
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wire RDY_flush, RDY_insert, RDY_lookup;
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// register rg_flushing
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reg rg_flushing;
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wire rg_flushing$D_IN, rg_flushing$EN;
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// register tlb0_valids_0
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reg tlb0_valids_0;
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wire tlb0_valids_0$D_IN, tlb0_valids_0$EN;
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// register tlb0_valids_1
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reg tlb0_valids_1;
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wire tlb0_valids_1$D_IN, tlb0_valids_1$EN;
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// register tlb0_valids_2
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reg tlb0_valids_2;
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wire tlb0_valids_2$D_IN, tlb0_valids_2$EN;
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// register tlb0_valids_3
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reg tlb0_valids_3;
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wire tlb0_valids_3$D_IN, tlb0_valids_3$EN;
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// register tlb1_valids_0
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reg tlb1_valids_0;
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wire tlb1_valids_0$D_IN, tlb1_valids_0$EN;
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// register tlb1_valids_1
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reg tlb1_valids_1;
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wire tlb1_valids_1$D_IN, tlb1_valids_1$EN;
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// register tlb1_valids_2
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reg tlb1_valids_2;
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wire tlb1_valids_2$D_IN, tlb1_valids_2$EN;
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// register tlb1_valids_3
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reg tlb1_valids_3;
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wire tlb1_valids_3$D_IN, tlb1_valids_3$EN;
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// register tlb2_valids_0
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reg tlb2_valids_0;
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wire tlb2_valids_0$D_IN, tlb2_valids_0$EN;
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// register tlb2_valids_1
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reg tlb2_valids_1;
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wire tlb2_valids_1$D_IN, tlb2_valids_1$EN;
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// register tlb2_valids_2
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reg tlb2_valids_2;
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wire tlb2_valids_2$D_IN, tlb2_valids_2$EN;
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// register tlb2_valids_3
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reg tlb2_valids_3;
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wire tlb2_valids_3$D_IN, tlb2_valids_3$EN;
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// ports of submodule tlb0_entries
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wire [168 : 0] tlb0_entries$D_IN, tlb0_entries$D_OUT_1;
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wire [1 : 0] tlb0_entries$ADDR_1,
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tlb0_entries$ADDR_2,
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tlb0_entries$ADDR_3,
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tlb0_entries$ADDR_4,
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tlb0_entries$ADDR_5,
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tlb0_entries$ADDR_IN;
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wire tlb0_entries$WE;
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// ports of submodule tlb1_entries
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wire [159 : 0] tlb1_entries$D_IN, tlb1_entries$D_OUT_1;
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wire [1 : 0] tlb1_entries$ADDR_1,
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tlb1_entries$ADDR_2,
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tlb1_entries$ADDR_3,
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tlb1_entries$ADDR_4,
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tlb1_entries$ADDR_5,
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tlb1_entries$ADDR_IN;
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wire tlb1_entries$WE;
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// ports of submodule tlb2_entries
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wire [150 : 0] tlb2_entries$D_IN, tlb2_entries$D_OUT_1;
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wire [1 : 0] tlb2_entries$ADDR_1,
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tlb2_entries$ADDR_2,
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tlb2_entries$ADDR_3,
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tlb2_entries$ADDR_4,
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tlb2_entries$ADDR_5,
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tlb2_entries$ADDR_IN;
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wire tlb2_entries$WE;
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// rule scheduling signals
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wire CAN_FIRE_RL_rl_initialize,
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CAN_FIRE_flush,
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CAN_FIRE_insert,
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WILL_FIRE_RL_rl_initialize,
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WILL_FIRE_flush,
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WILL_FIRE_insert;
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// inputs to muxes for submodule ports
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wire MUX_tlb0_valids_0$write_1__SEL_1,
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MUX_tlb0_valids_1$write_1__SEL_1,
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MUX_tlb0_valids_2$write_1__SEL_1,
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MUX_tlb0_valids_3$write_1__SEL_1,
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MUX_tlb1_valids_0$write_1__SEL_1,
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MUX_tlb1_valids_1$write_1__SEL_1,
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MUX_tlb1_valids_2$write_1__SEL_1,
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MUX_tlb1_valids_3$write_1__SEL_1,
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MUX_tlb2_valids_0$write_1__SEL_1,
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MUX_tlb2_valids_1$write_1__SEL_1,
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MUX_tlb2_valids_2$write_1__SEL_1,
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MUX_tlb2_valids_3$write_1__SEL_1;
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// remaining internal signals
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reg SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51,
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SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29,
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SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8;
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wire [129 : 0] IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92,
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IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93;
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wire NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73,
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NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43,
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NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22,
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NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80,
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SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61,
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SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65,
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tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54,
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tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60,
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tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33,
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tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41,
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tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12,
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tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20;
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// action method flush
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assign RDY_flush = 1'd1 ;
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assign CAN_FIRE_flush = 1'd1 ;
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assign WILL_FIRE_flush = EN_flush ;
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// value method lookup
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assign lookup =
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{ NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 &&
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NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 &&
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SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61 ||
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NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80,
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IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93 } ;
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assign RDY_lookup = !rg_flushing ;
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// action method insert
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assign RDY_insert = !rg_flushing ;
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assign CAN_FIRE_insert = !rg_flushing ;
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assign WILL_FIRE_insert = EN_insert ;
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// submodule tlb0_entries
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RegFile #(.addr_width(32'd2),
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.data_width(32'd169),
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.lo(2'h0),
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.hi(2'd3)) tlb0_entries(.CLK(CLK),
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.ADDR_1(tlb0_entries$ADDR_1),
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.ADDR_2(tlb0_entries$ADDR_2),
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.ADDR_3(tlb0_entries$ADDR_3),
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.ADDR_4(tlb0_entries$ADDR_4),
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.ADDR_5(tlb0_entries$ADDR_5),
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.ADDR_IN(tlb0_entries$ADDR_IN),
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.D_IN(tlb0_entries$D_IN),
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.WE(tlb0_entries$WE),
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.D_OUT_1(tlb0_entries$D_OUT_1),
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.D_OUT_2(),
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.D_OUT_3(),
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.D_OUT_4(),
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.D_OUT_5());
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// submodule tlb1_entries
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RegFile #(.addr_width(32'd2),
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.data_width(32'd160),
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.lo(2'h0),
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.hi(2'd3)) tlb1_entries(.CLK(CLK),
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.ADDR_1(tlb1_entries$ADDR_1),
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.ADDR_2(tlb1_entries$ADDR_2),
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.ADDR_3(tlb1_entries$ADDR_3),
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.ADDR_4(tlb1_entries$ADDR_4),
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.ADDR_5(tlb1_entries$ADDR_5),
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.ADDR_IN(tlb1_entries$ADDR_IN),
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.D_IN(tlb1_entries$D_IN),
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.WE(tlb1_entries$WE),
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.D_OUT_1(tlb1_entries$D_OUT_1),
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.D_OUT_2(),
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.D_OUT_3(),
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.D_OUT_4(),
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.D_OUT_5());
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// submodule tlb2_entries
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RegFile #(.addr_width(32'd2),
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.data_width(32'd151),
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.lo(2'h0),
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.hi(2'd3)) tlb2_entries(.CLK(CLK),
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.ADDR_1(tlb2_entries$ADDR_1),
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.ADDR_2(tlb2_entries$ADDR_2),
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.ADDR_3(tlb2_entries$ADDR_3),
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.ADDR_4(tlb2_entries$ADDR_4),
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.ADDR_5(tlb2_entries$ADDR_5),
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.ADDR_IN(tlb2_entries$ADDR_IN),
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.D_IN(tlb2_entries$D_IN),
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.WE(tlb2_entries$WE),
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.D_OUT_1(tlb2_entries$D_OUT_1),
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.D_OUT_2(),
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.D_OUT_3(),
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.D_OUT_4(),
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.D_OUT_5());
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// rule RL_rl_initialize
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assign CAN_FIRE_RL_rl_initialize = rg_flushing ;
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assign WILL_FIRE_RL_rl_initialize = rg_flushing ;
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// inputs to muxes for submodule ports
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assign MUX_tlb0_valids_0$write_1__SEL_1 =
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EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 ;
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assign MUX_tlb0_valids_1$write_1__SEL_1 =
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EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 ;
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assign MUX_tlb0_valids_2$write_1__SEL_1 =
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EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 ;
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assign MUX_tlb0_valids_3$write_1__SEL_1 =
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EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 ;
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assign MUX_tlb1_valids_0$write_1__SEL_1 =
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EN_insert && insert_vpn[10:9] == 2'd0 && insert_level == 2'd1 ;
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assign MUX_tlb1_valids_1$write_1__SEL_1 =
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EN_insert && insert_vpn[10:9] == 2'd1 && insert_level == 2'd1 ;
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assign MUX_tlb1_valids_2$write_1__SEL_1 =
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EN_insert && insert_vpn[10:9] == 2'd2 && insert_level == 2'd1 ;
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assign MUX_tlb1_valids_3$write_1__SEL_1 =
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EN_insert && insert_vpn[10:9] == 2'd3 && insert_level == 2'd1 ;
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assign MUX_tlb2_valids_0$write_1__SEL_1 =
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EN_insert && insert_vpn[19:18] == 2'd0 && insert_level != 2'd0 &&
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insert_level != 2'd1 ;
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assign MUX_tlb2_valids_1$write_1__SEL_1 =
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EN_insert && insert_vpn[19:18] == 2'd1 && insert_level != 2'd0 &&
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insert_level != 2'd1 ;
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assign MUX_tlb2_valids_2$write_1__SEL_1 =
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EN_insert && insert_vpn[19:18] == 2'd2 && insert_level != 2'd0 &&
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insert_level != 2'd1 ;
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assign MUX_tlb2_valids_3$write_1__SEL_1 =
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EN_insert && insert_vpn[19:18] == 2'd3 && insert_level != 2'd0 &&
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insert_level != 2'd1 ;
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// register rg_flushing
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assign rg_flushing$D_IN = EN_flush ;
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assign rg_flushing$EN = rg_flushing || EN_flush ;
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// register tlb0_valids_0
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assign tlb0_valids_0$D_IN = MUX_tlb0_valids_0$write_1__SEL_1 ;
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assign tlb0_valids_0$EN =
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EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 ||
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rg_flushing ;
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// register tlb0_valids_1
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assign tlb0_valids_1$D_IN = MUX_tlb0_valids_1$write_1__SEL_1 ;
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assign tlb0_valids_1$EN =
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EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 ||
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rg_flushing ;
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// register tlb0_valids_2
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assign tlb0_valids_2$D_IN = MUX_tlb0_valids_2$write_1__SEL_1 ;
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assign tlb0_valids_2$EN =
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EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 ||
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rg_flushing ;
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// register tlb0_valids_3
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assign tlb0_valids_3$D_IN = MUX_tlb0_valids_3$write_1__SEL_1 ;
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assign tlb0_valids_3$EN =
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EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 ||
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rg_flushing ;
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// register tlb1_valids_0
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assign tlb1_valids_0$D_IN = MUX_tlb1_valids_0$write_1__SEL_1 ;
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assign tlb1_valids_0$EN =
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EN_insert && insert_vpn[10:9] == 2'd0 && insert_level == 2'd1 ||
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rg_flushing ;
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// register tlb1_valids_1
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assign tlb1_valids_1$D_IN = MUX_tlb1_valids_1$write_1__SEL_1 ;
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assign tlb1_valids_1$EN =
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EN_insert && insert_vpn[10:9] == 2'd1 && insert_level == 2'd1 ||
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rg_flushing ;
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// register tlb1_valids_2
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assign tlb1_valids_2$D_IN = MUX_tlb1_valids_2$write_1__SEL_1 ;
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assign tlb1_valids_2$EN =
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EN_insert && insert_vpn[10:9] == 2'd2 && insert_level == 2'd1 ||
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rg_flushing ;
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// register tlb1_valids_3
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assign tlb1_valids_3$D_IN = MUX_tlb1_valids_3$write_1__SEL_1 ;
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assign tlb1_valids_3$EN =
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EN_insert && insert_vpn[10:9] == 2'd3 && insert_level == 2'd1 ||
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rg_flushing ;
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// register tlb2_valids_0
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assign tlb2_valids_0$D_IN = MUX_tlb2_valids_0$write_1__SEL_1 ;
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assign tlb2_valids_0$EN =
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EN_insert && insert_vpn[19:18] == 2'd0 && insert_level != 2'd0 &&
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insert_level != 2'd1 ||
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rg_flushing ;
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// register tlb2_valids_1
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assign tlb2_valids_1$D_IN = MUX_tlb2_valids_1$write_1__SEL_1 ;
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assign tlb2_valids_1$EN =
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EN_insert && insert_vpn[19:18] == 2'd1 && insert_level != 2'd0 &&
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insert_level != 2'd1 ||
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rg_flushing ;
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// register tlb2_valids_2
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assign tlb2_valids_2$D_IN = MUX_tlb2_valids_2$write_1__SEL_1 ;
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assign tlb2_valids_2$EN =
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EN_insert && insert_vpn[19:18] == 2'd2 && insert_level != 2'd0 &&
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insert_level != 2'd1 ||
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rg_flushing ;
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// register tlb2_valids_3
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assign tlb2_valids_3$D_IN = MUX_tlb2_valids_3$write_1__SEL_1 ;
|
|
assign tlb2_valids_3$EN =
|
|
EN_insert && insert_vpn[19:18] == 2'd3 && insert_level != 2'd0 &&
|
|
insert_level != 2'd1 ||
|
|
rg_flushing ;
|
|
|
|
// submodule tlb0_entries
|
|
assign tlb0_entries$ADDR_1 = lookup_vpn[1:0] ;
|
|
assign tlb0_entries$ADDR_2 = 2'h0 ;
|
|
assign tlb0_entries$ADDR_3 = 2'h0 ;
|
|
assign tlb0_entries$ADDR_4 = 2'h0 ;
|
|
assign tlb0_entries$ADDR_5 = 2'h0 ;
|
|
assign tlb0_entries$ADDR_IN = insert_vpn[1:0] ;
|
|
assign tlb0_entries$D_IN =
|
|
{ insert_asid, insert_vpn[26:2], insert_pte, insert_pte_pa } ;
|
|
assign tlb0_entries$WE = EN_insert && insert_level == 2'd0 ;
|
|
|
|
// submodule tlb1_entries
|
|
assign tlb1_entries$ADDR_1 = lookup_vpn[10:9] ;
|
|
assign tlb1_entries$ADDR_2 = 2'h0 ;
|
|
assign tlb1_entries$ADDR_3 = 2'h0 ;
|
|
assign tlb1_entries$ADDR_4 = 2'h0 ;
|
|
assign tlb1_entries$ADDR_5 = 2'h0 ;
|
|
assign tlb1_entries$ADDR_IN = insert_vpn[10:9] ;
|
|
assign tlb1_entries$D_IN =
|
|
{ insert_asid, insert_vpn[26:11], insert_pte, insert_pte_pa } ;
|
|
assign tlb1_entries$WE = EN_insert && insert_level == 2'd1 ;
|
|
|
|
// submodule tlb2_entries
|
|
assign tlb2_entries$ADDR_1 = lookup_vpn[19:18] ;
|
|
assign tlb2_entries$ADDR_2 = 2'h0 ;
|
|
assign tlb2_entries$ADDR_3 = 2'h0 ;
|
|
assign tlb2_entries$ADDR_4 = 2'h0 ;
|
|
assign tlb2_entries$ADDR_5 = 2'h0 ;
|
|
assign tlb2_entries$ADDR_IN = insert_vpn[19:18] ;
|
|
assign tlb2_entries$D_IN =
|
|
{ insert_asid, insert_vpn[26:20], insert_pte, insert_pte_pa } ;
|
|
assign tlb2_entries$WE =
|
|
EN_insert && insert_level != 2'd0 && insert_level != 2'd1 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92 =
|
|
(NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 &&
|
|
SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 &&
|
|
NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73) ?
|
|
{ tlb1_entries$D_OUT_1[127:64],
|
|
2'd1,
|
|
tlb1_entries$D_OUT_1[63:0] } :
|
|
{ tlb2_entries$D_OUT_1[127:64],
|
|
2'd2,
|
|
tlb2_entries$D_OUT_1[63:0] } ;
|
|
assign IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93 =
|
|
(NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 &&
|
|
NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 &&
|
|
SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61) ?
|
|
{ tlb0_entries$D_OUT_1[127:64],
|
|
2'd0,
|
|
tlb0_entries$D_OUT_1[63:0] } :
|
|
IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92 ;
|
|
assign NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 =
|
|
!SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 ||
|
|
!tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 &&
|
|
!tlb0_entries$D_OUT_1[69] ||
|
|
!tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 ;
|
|
assign NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 =
|
|
!SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 ||
|
|
!tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 &&
|
|
!tlb1_entries$D_OUT_1[69] ||
|
|
!tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 ;
|
|
assign NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 =
|
|
!SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 ||
|
|
!tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 &&
|
|
!tlb2_entries$D_OUT_1[69] ||
|
|
!tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 ;
|
|
assign NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80 =
|
|
NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 &&
|
|
SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 &&
|
|
NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 ||
|
|
SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 &&
|
|
(tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 ||
|
|
tlb2_entries$D_OUT_1[69]) &&
|
|
tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 &&
|
|
NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 &&
|
|
NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 ;
|
|
assign SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61 =
|
|
SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 &&
|
|
(tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 ||
|
|
tlb0_entries$D_OUT_1[69]) &&
|
|
tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 ;
|
|
assign SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 =
|
|
SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 &&
|
|
(tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 ||
|
|
tlb1_entries$D_OUT_1[69]) &&
|
|
tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 ;
|
|
assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 =
|
|
tlb0_entries$D_OUT_1[168:153] == lookup_asid ;
|
|
assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 =
|
|
tlb0_entries$D_OUT_1[152:128] == lookup_vpn[26:2] ;
|
|
assign tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 =
|
|
tlb1_entries$D_OUT_1[159:144] == lookup_asid ;
|
|
assign tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 =
|
|
tlb1_entries$D_OUT_1[143:128] == lookup_vpn[26:11] ;
|
|
assign tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 =
|
|
tlb2_entries$D_OUT_1[150:135] == lookup_asid ;
|
|
assign tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 =
|
|
tlb2_entries$D_OUT_1[134:128] == lookup_vpn[26:20] ;
|
|
always@(lookup_vpn or
|
|
tlb2_valids_0 or tlb2_valids_1 or tlb2_valids_2 or tlb2_valids_3)
|
|
begin
|
|
case (lookup_vpn[19:18])
|
|
2'd0:
|
|
SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 =
|
|
tlb2_valids_0;
|
|
2'd1:
|
|
SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 =
|
|
tlb2_valids_1;
|
|
2'd2:
|
|
SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 =
|
|
tlb2_valids_2;
|
|
2'd3:
|
|
SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 =
|
|
tlb2_valids_3;
|
|
endcase
|
|
end
|
|
always@(lookup_vpn or
|
|
tlb1_valids_0 or tlb1_valids_1 or tlb1_valids_2 or tlb1_valids_3)
|
|
begin
|
|
case (lookup_vpn[10:9])
|
|
2'd0:
|
|
SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 =
|
|
tlb1_valids_0;
|
|
2'd1:
|
|
SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 =
|
|
tlb1_valids_1;
|
|
2'd2:
|
|
SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 =
|
|
tlb1_valids_2;
|
|
2'd3:
|
|
SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 =
|
|
tlb1_valids_3;
|
|
endcase
|
|
end
|
|
always@(lookup_vpn or
|
|
tlb0_valids_0 or tlb0_valids_1 or tlb0_valids_2 or tlb0_valids_3)
|
|
begin
|
|
case (lookup_vpn[1:0])
|
|
2'd0:
|
|
SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 =
|
|
tlb0_valids_0;
|
|
2'd1:
|
|
SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 =
|
|
tlb0_valids_1;
|
|
2'd2:
|
|
SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 =
|
|
tlb0_valids_2;
|
|
2'd3:
|
|
SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 =
|
|
tlb0_valids_3;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
rg_flushing <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
end
|
|
else
|
|
begin
|
|
if (rg_flushing$EN)
|
|
rg_flushing <= `BSV_ASSIGNMENT_DELAY rg_flushing$D_IN;
|
|
end
|
|
if (tlb0_valids_0$EN)
|
|
tlb0_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_0$D_IN;
|
|
if (tlb0_valids_1$EN)
|
|
tlb0_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_1$D_IN;
|
|
if (tlb0_valids_2$EN)
|
|
tlb0_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_2$D_IN;
|
|
if (tlb0_valids_3$EN)
|
|
tlb0_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_3$D_IN;
|
|
if (tlb1_valids_0$EN)
|
|
tlb1_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_0$D_IN;
|
|
if (tlb1_valids_1$EN)
|
|
tlb1_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_1$D_IN;
|
|
if (tlb1_valids_2$EN)
|
|
tlb1_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_2$D_IN;
|
|
if (tlb1_valids_3$EN)
|
|
tlb1_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_3$D_IN;
|
|
if (tlb2_valids_0$EN)
|
|
tlb2_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_0$D_IN;
|
|
if (tlb2_valids_1$EN)
|
|
tlb2_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_1$D_IN;
|
|
if (tlb2_valids_2$EN)
|
|
tlb2_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_2$D_IN;
|
|
if (tlb2_valids_3$EN)
|
|
tlb2_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_3$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
rg_flushing = 1'h0;
|
|
tlb0_valids_0 = 1'h0;
|
|
tlb0_valids_1 = 1'h0;
|
|
tlb0_valids_2 = 1'h0;
|
|
tlb0_valids_3 = 1'h0;
|
|
tlb1_valids_0 = 1'h0;
|
|
tlb1_valids_1 = 1'h0;
|
|
tlb1_valids_2 = 1'h0;
|
|
tlb1_valids_3 = 1'h0;
|
|
tlb2_valids_0 = 1'h0;
|
|
tlb2_valids_1 = 1'h0;
|
|
tlb2_valids_2 = 1'h0;
|
|
tlb2_valids_3 = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkTLB
|
|
|