3230 lines
131 KiB
Verilog
3230 lines
131 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_set_verbosity O 1 const
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// RDY_set_htif_addrs O 1 const
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// RDY_cpu_reset_server_request_put O 1 reg
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// RDY_cpu_reset_server_response_get O 1 reg
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// cpu_imem_master_awvalid O 1
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// cpu_imem_master_awid O 4 reg
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// cpu_imem_master_awaddr O 64 reg
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// cpu_imem_master_awlen O 8 reg
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// cpu_imem_master_awsize O 3 reg
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// cpu_imem_master_awburst O 2 reg
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// cpu_imem_master_awlock O 1 reg
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// cpu_imem_master_awcache O 4 reg
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// cpu_imem_master_awprot O 3 reg
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// cpu_imem_master_awqos O 4 reg
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// cpu_imem_master_awregion O 4 reg
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// cpu_imem_master_wvalid O 1
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// cpu_imem_master_wid O 4 reg
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// cpu_imem_master_wdata O 64 reg
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// cpu_imem_master_wstrb O 8 reg
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// cpu_imem_master_wlast O 1 reg
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// cpu_imem_master_bready O 1
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// cpu_imem_master_arvalid O 1
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// cpu_imem_master_arid O 4 reg
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// cpu_imem_master_araddr O 64 reg
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// cpu_imem_master_arlen O 8 reg
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// cpu_imem_master_arsize O 3 reg
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// cpu_imem_master_arburst O 2 reg
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// cpu_imem_master_arlock O 1 reg
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// cpu_imem_master_arcache O 4 reg
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// cpu_imem_master_arprot O 3 reg
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// cpu_imem_master_arqos O 4 reg
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// cpu_imem_master_arregion O 4 reg
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// cpu_imem_master_rready O 1
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// cpu_dmem_master_awvalid O 1 reg
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// cpu_dmem_master_awid O 4 reg
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// cpu_dmem_master_awaddr O 64 reg
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// cpu_dmem_master_awlen O 8 reg
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// cpu_dmem_master_awsize O 3 reg
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// cpu_dmem_master_awburst O 2 reg
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// cpu_dmem_master_awlock O 1 reg
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// cpu_dmem_master_awcache O 4 reg
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// cpu_dmem_master_awprot O 3 reg
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// cpu_dmem_master_awqos O 4 reg
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// cpu_dmem_master_awregion O 4 reg
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// cpu_dmem_master_wvalid O 1 reg
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// cpu_dmem_master_wid O 4 reg
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// cpu_dmem_master_wdata O 64 reg
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// cpu_dmem_master_wstrb O 8 reg
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// cpu_dmem_master_wlast O 1 reg
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// cpu_dmem_master_bready O 1 reg
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// cpu_dmem_master_arvalid O 1 reg
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// cpu_dmem_master_arid O 4 reg
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// cpu_dmem_master_araddr O 64 reg
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// cpu_dmem_master_arlen O 8 reg
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// cpu_dmem_master_arsize O 3 reg
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// cpu_dmem_master_arburst O 2 reg
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// cpu_dmem_master_arlock O 1 reg
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// cpu_dmem_master_arcache O 4 reg
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// cpu_dmem_master_arprot O 3 reg
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// cpu_dmem_master_arqos O 4 reg
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// cpu_dmem_master_arregion O 4 reg
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// cpu_dmem_master_rready O 1 reg
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// tv_verifier_info_get_get O 608 reg
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// RDY_tv_verifier_info_get_get O 1 reg
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// RDY_dm_dmi_read_addr O 1
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// dm_dmi_read_data O 32
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// RDY_dm_dmi_read_data O 1
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// RDY_dm_dmi_write O 1
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// RDY_dm_ndm_reset_req_get_get O 1 reg
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// CLK I 1 clock
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// RST_N I 1 reset
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// set_verbosity_verbosity I 4 reg
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// set_verbosity_logdelay I 64 unused
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// set_htif_addrs_tohost_addr I 64 reg
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// set_htif_addrs_fromhost_addr I 64 reg
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// cpu_imem_master_awready I 1
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// cpu_imem_master_wready I 1
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// cpu_imem_master_bvalid I 1
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// cpu_imem_master_bid I 4 reg
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// cpu_imem_master_bresp I 2 reg
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// cpu_imem_master_arready I 1
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// cpu_imem_master_rvalid I 1
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// cpu_imem_master_rid I 4 reg
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// cpu_imem_master_rdata I 64 reg
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// cpu_imem_master_rresp I 2 reg
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// cpu_imem_master_rlast I 1 reg
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// cpu_dmem_master_awready I 1
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// cpu_dmem_master_wready I 1
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// cpu_dmem_master_bvalid I 1
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// cpu_dmem_master_bid I 4 reg
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// cpu_dmem_master_bresp I 2 reg
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// cpu_dmem_master_arready I 1
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// cpu_dmem_master_rvalid I 1
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// cpu_dmem_master_rid I 4 reg
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// cpu_dmem_master_rdata I 64 reg
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// cpu_dmem_master_rresp I 2 reg
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// cpu_dmem_master_rlast I 1 reg
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// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1
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// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1
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// debug_external_interrupt_req_set_not_clear I 1
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// dm_dmi_read_addr_dm_addr I 7
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// dm_dmi_write_dm_addr I 7
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// dm_dmi_write_dm_word I 32
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// EN_set_verbosity I 1
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// EN_set_htif_addrs I 1
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// EN_cpu_reset_server_request_put I 1
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// EN_cpu_reset_server_response_get I 1
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// EN_dm_dmi_read_addr I 1
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// EN_dm_dmi_write I 1
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// EN_dm_ndm_reset_req_get_get I 1
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// EN_tv_verifier_info_get_get I 1
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// EN_dm_dmi_read_data I 1
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//
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// Combinational paths from inputs to outputs:
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// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready
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// (dm_dmi_read_addr_dm_addr, EN_dm_dmi_read_addr) -> RDY_dm_dmi_read_data
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// (dm_dmi_read_addr_dm_addr,
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// EN_dm_dmi_read_addr,
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// EN_dm_dmi_read_data) -> dm_dmi_read_data
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkCoreW(CLK,
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RST_N,
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set_verbosity_verbosity,
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set_verbosity_logdelay,
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EN_set_verbosity,
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RDY_set_verbosity,
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set_htif_addrs_tohost_addr,
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set_htif_addrs_fromhost_addr,
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EN_set_htif_addrs,
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RDY_set_htif_addrs,
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EN_cpu_reset_server_request_put,
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RDY_cpu_reset_server_request_put,
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EN_cpu_reset_server_response_get,
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RDY_cpu_reset_server_response_get,
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cpu_imem_master_awvalid,
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cpu_imem_master_awid,
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cpu_imem_master_awaddr,
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cpu_imem_master_awlen,
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cpu_imem_master_awsize,
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cpu_imem_master_awburst,
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cpu_imem_master_awlock,
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cpu_imem_master_awcache,
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cpu_imem_master_awprot,
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cpu_imem_master_awqos,
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cpu_imem_master_awregion,
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cpu_imem_master_awready,
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cpu_imem_master_wvalid,
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cpu_imem_master_wid,
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cpu_imem_master_wdata,
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cpu_imem_master_wstrb,
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cpu_imem_master_wlast,
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cpu_imem_master_wready,
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cpu_imem_master_bvalid,
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cpu_imem_master_bid,
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cpu_imem_master_bresp,
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cpu_imem_master_bready,
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cpu_imem_master_arvalid,
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cpu_imem_master_arid,
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cpu_imem_master_araddr,
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cpu_imem_master_arlen,
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cpu_imem_master_arsize,
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cpu_imem_master_arburst,
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cpu_imem_master_arlock,
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cpu_imem_master_arcache,
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cpu_imem_master_arprot,
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cpu_imem_master_arqos,
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cpu_imem_master_arregion,
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cpu_imem_master_arready,
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cpu_imem_master_rvalid,
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cpu_imem_master_rid,
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cpu_imem_master_rdata,
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cpu_imem_master_rresp,
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cpu_imem_master_rlast,
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cpu_imem_master_rready,
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cpu_dmem_master_awvalid,
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cpu_dmem_master_awid,
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cpu_dmem_master_awaddr,
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cpu_dmem_master_awlen,
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cpu_dmem_master_awsize,
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cpu_dmem_master_awburst,
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cpu_dmem_master_awlock,
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cpu_dmem_master_awcache,
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cpu_dmem_master_awprot,
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cpu_dmem_master_awqos,
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cpu_dmem_master_awregion,
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cpu_dmem_master_awready,
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cpu_dmem_master_wvalid,
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cpu_dmem_master_wid,
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cpu_dmem_master_wdata,
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cpu_dmem_master_wstrb,
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cpu_dmem_master_wlast,
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cpu_dmem_master_wready,
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cpu_dmem_master_bvalid,
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cpu_dmem_master_bid,
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cpu_dmem_master_bresp,
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cpu_dmem_master_bready,
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cpu_dmem_master_arvalid,
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cpu_dmem_master_arid,
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cpu_dmem_master_araddr,
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cpu_dmem_master_arlen,
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cpu_dmem_master_arsize,
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cpu_dmem_master_arburst,
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cpu_dmem_master_arlock,
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cpu_dmem_master_arcache,
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cpu_dmem_master_arprot,
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cpu_dmem_master_arqos,
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cpu_dmem_master_arregion,
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cpu_dmem_master_arready,
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cpu_dmem_master_rvalid,
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cpu_dmem_master_rid,
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cpu_dmem_master_rdata,
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cpu_dmem_master_rresp,
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cpu_dmem_master_rlast,
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cpu_dmem_master_rready,
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core_external_interrupt_sources_0_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_1_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_2_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_3_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_4_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_5_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_6_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_7_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_8_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_9_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_10_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_11_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_12_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_13_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_14_m_interrupt_req_set_not_clear,
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core_external_interrupt_sources_15_m_interrupt_req_set_not_clear,
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debug_external_interrupt_req_set_not_clear,
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EN_tv_verifier_info_get_get,
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tv_verifier_info_get_get,
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RDY_tv_verifier_info_get_get,
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dm_dmi_read_addr_dm_addr,
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EN_dm_dmi_read_addr,
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RDY_dm_dmi_read_addr,
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EN_dm_dmi_read_data,
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dm_dmi_read_data,
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RDY_dm_dmi_read_data,
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dm_dmi_write_dm_addr,
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dm_dmi_write_dm_word,
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EN_dm_dmi_write,
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RDY_dm_dmi_write,
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EN_dm_ndm_reset_req_get_get,
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RDY_dm_ndm_reset_req_get_get);
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input CLK;
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input RST_N;
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// action method set_verbosity
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input [3 : 0] set_verbosity_verbosity;
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input [63 : 0] set_verbosity_logdelay;
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input EN_set_verbosity;
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output RDY_set_verbosity;
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// action method set_htif_addrs
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input [63 : 0] set_htif_addrs_tohost_addr;
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input [63 : 0] set_htif_addrs_fromhost_addr;
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input EN_set_htif_addrs;
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output RDY_set_htif_addrs;
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// action method cpu_reset_server_request_put
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input EN_cpu_reset_server_request_put;
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output RDY_cpu_reset_server_request_put;
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// action method cpu_reset_server_response_get
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input EN_cpu_reset_server_response_get;
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output RDY_cpu_reset_server_response_get;
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// value method cpu_imem_master_m_awvalid
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output cpu_imem_master_awvalid;
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// value method cpu_imem_master_m_awid
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output [3 : 0] cpu_imem_master_awid;
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// value method cpu_imem_master_m_awaddr
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output [63 : 0] cpu_imem_master_awaddr;
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// value method cpu_imem_master_m_awlen
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output [7 : 0] cpu_imem_master_awlen;
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// value method cpu_imem_master_m_awsize
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output [2 : 0] cpu_imem_master_awsize;
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// value method cpu_imem_master_m_awburst
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output [1 : 0] cpu_imem_master_awburst;
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// value method cpu_imem_master_m_awlock
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output cpu_imem_master_awlock;
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// value method cpu_imem_master_m_awcache
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output [3 : 0] cpu_imem_master_awcache;
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// value method cpu_imem_master_m_awprot
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output [2 : 0] cpu_imem_master_awprot;
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// value method cpu_imem_master_m_awqos
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output [3 : 0] cpu_imem_master_awqos;
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// value method cpu_imem_master_m_awregion
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output [3 : 0] cpu_imem_master_awregion;
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// value method cpu_imem_master_m_awuser
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// action method cpu_imem_master_m_awready
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input cpu_imem_master_awready;
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// value method cpu_imem_master_m_wvalid
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output cpu_imem_master_wvalid;
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// value method cpu_imem_master_m_wid
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output [3 : 0] cpu_imem_master_wid;
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// value method cpu_imem_master_m_wdata
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output [63 : 0] cpu_imem_master_wdata;
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// value method cpu_imem_master_m_wstrb
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output [7 : 0] cpu_imem_master_wstrb;
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// value method cpu_imem_master_m_wlast
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output cpu_imem_master_wlast;
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// value method cpu_imem_master_m_wuser
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// action method cpu_imem_master_m_wready
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input cpu_imem_master_wready;
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// action method cpu_imem_master_m_bvalid
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input cpu_imem_master_bvalid;
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input [3 : 0] cpu_imem_master_bid;
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input [1 : 0] cpu_imem_master_bresp;
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// value method cpu_imem_master_m_bready
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output cpu_imem_master_bready;
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// value method cpu_imem_master_m_arvalid
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output cpu_imem_master_arvalid;
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// value method cpu_imem_master_m_arid
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output [3 : 0] cpu_imem_master_arid;
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// value method cpu_imem_master_m_araddr
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output [63 : 0] cpu_imem_master_araddr;
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// value method cpu_imem_master_m_arlen
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output [7 : 0] cpu_imem_master_arlen;
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// value method cpu_imem_master_m_arsize
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output [2 : 0] cpu_imem_master_arsize;
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// value method cpu_imem_master_m_arburst
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output [1 : 0] cpu_imem_master_arburst;
|
|
|
|
// value method cpu_imem_master_m_arlock
|
|
output cpu_imem_master_arlock;
|
|
|
|
// value method cpu_imem_master_m_arcache
|
|
output [3 : 0] cpu_imem_master_arcache;
|
|
|
|
// value method cpu_imem_master_m_arprot
|
|
output [2 : 0] cpu_imem_master_arprot;
|
|
|
|
// value method cpu_imem_master_m_arqos
|
|
output [3 : 0] cpu_imem_master_arqos;
|
|
|
|
// value method cpu_imem_master_m_arregion
|
|
output [3 : 0] cpu_imem_master_arregion;
|
|
|
|
// value method cpu_imem_master_m_aruser
|
|
|
|
// action method cpu_imem_master_m_arready
|
|
input cpu_imem_master_arready;
|
|
|
|
// action method cpu_imem_master_m_rvalid
|
|
input cpu_imem_master_rvalid;
|
|
input [3 : 0] cpu_imem_master_rid;
|
|
input [63 : 0] cpu_imem_master_rdata;
|
|
input [1 : 0] cpu_imem_master_rresp;
|
|
input cpu_imem_master_rlast;
|
|
|
|
// value method cpu_imem_master_m_rready
|
|
output cpu_imem_master_rready;
|
|
|
|
// value method cpu_dmem_master_m_awvalid
|
|
output cpu_dmem_master_awvalid;
|
|
|
|
// value method cpu_dmem_master_m_awid
|
|
output [3 : 0] cpu_dmem_master_awid;
|
|
|
|
// value method cpu_dmem_master_m_awaddr
|
|
output [63 : 0] cpu_dmem_master_awaddr;
|
|
|
|
// value method cpu_dmem_master_m_awlen
|
|
output [7 : 0] cpu_dmem_master_awlen;
|
|
|
|
// value method cpu_dmem_master_m_awsize
|
|
output [2 : 0] cpu_dmem_master_awsize;
|
|
|
|
// value method cpu_dmem_master_m_awburst
|
|
output [1 : 0] cpu_dmem_master_awburst;
|
|
|
|
// value method cpu_dmem_master_m_awlock
|
|
output cpu_dmem_master_awlock;
|
|
|
|
// value method cpu_dmem_master_m_awcache
|
|
output [3 : 0] cpu_dmem_master_awcache;
|
|
|
|
// value method cpu_dmem_master_m_awprot
|
|
output [2 : 0] cpu_dmem_master_awprot;
|
|
|
|
// value method cpu_dmem_master_m_awqos
|
|
output [3 : 0] cpu_dmem_master_awqos;
|
|
|
|
// value method cpu_dmem_master_m_awregion
|
|
output [3 : 0] cpu_dmem_master_awregion;
|
|
|
|
// value method cpu_dmem_master_m_awuser
|
|
|
|
// action method cpu_dmem_master_m_awready
|
|
input cpu_dmem_master_awready;
|
|
|
|
// value method cpu_dmem_master_m_wvalid
|
|
output cpu_dmem_master_wvalid;
|
|
|
|
// value method cpu_dmem_master_m_wid
|
|
output [3 : 0] cpu_dmem_master_wid;
|
|
|
|
// value method cpu_dmem_master_m_wdata
|
|
output [63 : 0] cpu_dmem_master_wdata;
|
|
|
|
// value method cpu_dmem_master_m_wstrb
|
|
output [7 : 0] cpu_dmem_master_wstrb;
|
|
|
|
// value method cpu_dmem_master_m_wlast
|
|
output cpu_dmem_master_wlast;
|
|
|
|
// value method cpu_dmem_master_m_wuser
|
|
|
|
// action method cpu_dmem_master_m_wready
|
|
input cpu_dmem_master_wready;
|
|
|
|
// action method cpu_dmem_master_m_bvalid
|
|
input cpu_dmem_master_bvalid;
|
|
input [3 : 0] cpu_dmem_master_bid;
|
|
input [1 : 0] cpu_dmem_master_bresp;
|
|
|
|
// value method cpu_dmem_master_m_bready
|
|
output cpu_dmem_master_bready;
|
|
|
|
// value method cpu_dmem_master_m_arvalid
|
|
output cpu_dmem_master_arvalid;
|
|
|
|
// value method cpu_dmem_master_m_arid
|
|
output [3 : 0] cpu_dmem_master_arid;
|
|
|
|
// value method cpu_dmem_master_m_araddr
|
|
output [63 : 0] cpu_dmem_master_araddr;
|
|
|
|
// value method cpu_dmem_master_m_arlen
|
|
output [7 : 0] cpu_dmem_master_arlen;
|
|
|
|
// value method cpu_dmem_master_m_arsize
|
|
output [2 : 0] cpu_dmem_master_arsize;
|
|
|
|
// value method cpu_dmem_master_m_arburst
|
|
output [1 : 0] cpu_dmem_master_arburst;
|
|
|
|
// value method cpu_dmem_master_m_arlock
|
|
output cpu_dmem_master_arlock;
|
|
|
|
// value method cpu_dmem_master_m_arcache
|
|
output [3 : 0] cpu_dmem_master_arcache;
|
|
|
|
// value method cpu_dmem_master_m_arprot
|
|
output [2 : 0] cpu_dmem_master_arprot;
|
|
|
|
// value method cpu_dmem_master_m_arqos
|
|
output [3 : 0] cpu_dmem_master_arqos;
|
|
|
|
// value method cpu_dmem_master_m_arregion
|
|
output [3 : 0] cpu_dmem_master_arregion;
|
|
|
|
// value method cpu_dmem_master_m_aruser
|
|
|
|
// action method cpu_dmem_master_m_arready
|
|
input cpu_dmem_master_arready;
|
|
|
|
// action method cpu_dmem_master_m_rvalid
|
|
input cpu_dmem_master_rvalid;
|
|
input [3 : 0] cpu_dmem_master_rid;
|
|
input [63 : 0] cpu_dmem_master_rdata;
|
|
input [1 : 0] cpu_dmem_master_rresp;
|
|
input cpu_dmem_master_rlast;
|
|
|
|
// value method cpu_dmem_master_m_rready
|
|
output cpu_dmem_master_rready;
|
|
|
|
// action method core_external_interrupt_sources_0_m_interrupt_req
|
|
input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_1_m_interrupt_req
|
|
input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_2_m_interrupt_req
|
|
input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_3_m_interrupt_req
|
|
input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_4_m_interrupt_req
|
|
input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_5_m_interrupt_req
|
|
input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_6_m_interrupt_req
|
|
input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_7_m_interrupt_req
|
|
input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_8_m_interrupt_req
|
|
input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_9_m_interrupt_req
|
|
input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_10_m_interrupt_req
|
|
input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_11_m_interrupt_req
|
|
input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_12_m_interrupt_req
|
|
input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_13_m_interrupt_req
|
|
input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_14_m_interrupt_req
|
|
input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear;
|
|
|
|
// action method core_external_interrupt_sources_15_m_interrupt_req
|
|
input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear;
|
|
|
|
// action method debug_external_interrupt_req
|
|
input debug_external_interrupt_req_set_not_clear;
|
|
|
|
// actionvalue method tv_verifier_info_get_get
|
|
input EN_tv_verifier_info_get_get;
|
|
output [607 : 0] tv_verifier_info_get_get;
|
|
output RDY_tv_verifier_info_get_get;
|
|
|
|
// action method dm_dmi_read_addr
|
|
input [6 : 0] dm_dmi_read_addr_dm_addr;
|
|
input EN_dm_dmi_read_addr;
|
|
output RDY_dm_dmi_read_addr;
|
|
|
|
// actionvalue method dm_dmi_read_data
|
|
input EN_dm_dmi_read_data;
|
|
output [31 : 0] dm_dmi_read_data;
|
|
output RDY_dm_dmi_read_data;
|
|
|
|
// action method dm_dmi_write
|
|
input [6 : 0] dm_dmi_write_dm_addr;
|
|
input [31 : 0] dm_dmi_write_dm_word;
|
|
input EN_dm_dmi_write;
|
|
output RDY_dm_dmi_write;
|
|
|
|
// action method dm_ndm_reset_req_get_get
|
|
input EN_dm_ndm_reset_req_get_get;
|
|
output RDY_dm_ndm_reset_req_get_get;
|
|
|
|
// signals for module outputs
|
|
wire [607 : 0] tv_verifier_info_get_get;
|
|
wire [63 : 0] cpu_dmem_master_araddr,
|
|
cpu_dmem_master_awaddr,
|
|
cpu_dmem_master_wdata,
|
|
cpu_imem_master_araddr,
|
|
cpu_imem_master_awaddr,
|
|
cpu_imem_master_wdata;
|
|
wire [31 : 0] dm_dmi_read_data;
|
|
wire [7 : 0] cpu_dmem_master_arlen,
|
|
cpu_dmem_master_awlen,
|
|
cpu_dmem_master_wstrb,
|
|
cpu_imem_master_arlen,
|
|
cpu_imem_master_awlen,
|
|
cpu_imem_master_wstrb;
|
|
wire [3 : 0] cpu_dmem_master_arcache,
|
|
cpu_dmem_master_arid,
|
|
cpu_dmem_master_arqos,
|
|
cpu_dmem_master_arregion,
|
|
cpu_dmem_master_awcache,
|
|
cpu_dmem_master_awid,
|
|
cpu_dmem_master_awqos,
|
|
cpu_dmem_master_awregion,
|
|
cpu_dmem_master_wid,
|
|
cpu_imem_master_arcache,
|
|
cpu_imem_master_arid,
|
|
cpu_imem_master_arqos,
|
|
cpu_imem_master_arregion,
|
|
cpu_imem_master_awcache,
|
|
cpu_imem_master_awid,
|
|
cpu_imem_master_awqos,
|
|
cpu_imem_master_awregion,
|
|
cpu_imem_master_wid;
|
|
wire [2 : 0] cpu_dmem_master_arprot,
|
|
cpu_dmem_master_arsize,
|
|
cpu_dmem_master_awprot,
|
|
cpu_dmem_master_awsize,
|
|
cpu_imem_master_arprot,
|
|
cpu_imem_master_arsize,
|
|
cpu_imem_master_awprot,
|
|
cpu_imem_master_awsize;
|
|
wire [1 : 0] cpu_dmem_master_arburst,
|
|
cpu_dmem_master_awburst,
|
|
cpu_imem_master_arburst,
|
|
cpu_imem_master_awburst;
|
|
wire RDY_cpu_reset_server_request_put,
|
|
RDY_cpu_reset_server_response_get,
|
|
RDY_dm_dmi_read_addr,
|
|
RDY_dm_dmi_read_data,
|
|
RDY_dm_dmi_write,
|
|
RDY_dm_ndm_reset_req_get_get,
|
|
RDY_set_htif_addrs,
|
|
RDY_set_verbosity,
|
|
RDY_tv_verifier_info_get_get,
|
|
cpu_dmem_master_arlock,
|
|
cpu_dmem_master_arvalid,
|
|
cpu_dmem_master_awlock,
|
|
cpu_dmem_master_awvalid,
|
|
cpu_dmem_master_bready,
|
|
cpu_dmem_master_rready,
|
|
cpu_dmem_master_wlast,
|
|
cpu_dmem_master_wvalid,
|
|
cpu_imem_master_arlock,
|
|
cpu_imem_master_arvalid,
|
|
cpu_imem_master_awlock,
|
|
cpu_imem_master_awvalid,
|
|
cpu_imem_master_bready,
|
|
cpu_imem_master_rready,
|
|
cpu_imem_master_wlast,
|
|
cpu_imem_master_wvalid;
|
|
|
|
// register hart0_halt
|
|
reg hart0_halt;
|
|
wire hart0_halt$D_IN, hart0_halt$EN;
|
|
|
|
// register once
|
|
reg once;
|
|
wire once$D_IN, once$EN;
|
|
|
|
// register rg_fromhost_addr
|
|
reg [63 : 0] rg_fromhost_addr;
|
|
wire [63 : 0] rg_fromhost_addr$D_IN;
|
|
wire rg_fromhost_addr$EN;
|
|
|
|
// register rg_tohost_addr
|
|
reg [63 : 0] rg_tohost_addr;
|
|
wire [63 : 0] rg_tohost_addr$D_IN;
|
|
wire rg_tohost_addr$EN;
|
|
|
|
// ports of submodule cpu_halt
|
|
wire cpu_halt$ASSERT_IN, cpu_halt$ASSERT_OUT, cpu_halt$OUT_RST;
|
|
|
|
// ports of submodule cpu_reset
|
|
wire cpu_reset$ASSERT_IN, cpu_reset$ASSERT_OUT, cpu_reset$OUT_RST;
|
|
|
|
// ports of submodule cpu_reset_either
|
|
wire cpu_reset_either$RST_OUT;
|
|
|
|
// ports of submodule debug_module
|
|
wire [64 : 0] debug_module$hart0_csr_mem_client_response_put,
|
|
debug_module$hart0_fpr_mem_client_response_put,
|
|
debug_module$hart0_gpr_mem_client_response_put;
|
|
wire [63 : 0] debug_module$master_araddr,
|
|
debug_module$master_awaddr,
|
|
debug_module$master_rdata,
|
|
debug_module$master_wdata;
|
|
wire [31 : 0] debug_module$dmi_read_data, debug_module$dmi_write_dm_word;
|
|
wire [7 : 0] debug_module$master_arlen,
|
|
debug_module$master_awlen,
|
|
debug_module$master_wstrb;
|
|
wire [6 : 0] debug_module$dmi_read_addr_dm_addr,
|
|
debug_module$dmi_write_dm_addr;
|
|
wire [3 : 0] debug_module$master_arcache,
|
|
debug_module$master_arid,
|
|
debug_module$master_arqos,
|
|
debug_module$master_arregion,
|
|
debug_module$master_awcache,
|
|
debug_module$master_awid,
|
|
debug_module$master_awqos,
|
|
debug_module$master_awregion,
|
|
debug_module$master_bid,
|
|
debug_module$master_rid,
|
|
debug_module$master_wid;
|
|
wire [2 : 0] debug_module$master_arprot,
|
|
debug_module$master_arsize,
|
|
debug_module$master_awprot,
|
|
debug_module$master_awsize;
|
|
wire [1 : 0] debug_module$master_arburst,
|
|
debug_module$master_awburst,
|
|
debug_module$master_bresp,
|
|
debug_module$master_rresp;
|
|
wire debug_module$EN_dmi_read_addr,
|
|
debug_module$EN_dmi_read_data,
|
|
debug_module$EN_dmi_write,
|
|
debug_module$EN_get_ndm_reset_req_get,
|
|
debug_module$EN_hart0_client_run_halt_request_get,
|
|
debug_module$EN_hart0_client_run_halt_response_put,
|
|
debug_module$EN_hart0_csr_mem_client_request_get,
|
|
debug_module$EN_hart0_csr_mem_client_response_put,
|
|
debug_module$EN_hart0_fpr_mem_client_request_get,
|
|
debug_module$EN_hart0_fpr_mem_client_response_put,
|
|
debug_module$EN_hart0_get_other_req_get,
|
|
debug_module$EN_hart0_get_reset_req_get,
|
|
debug_module$EN_hart0_gpr_mem_client_request_get,
|
|
debug_module$EN_hart0_gpr_mem_client_response_put,
|
|
debug_module$RDY_dmi_read_addr,
|
|
debug_module$RDY_dmi_read_data,
|
|
debug_module$RDY_dmi_write,
|
|
debug_module$RDY_get_ndm_reset_req_get,
|
|
debug_module$RDY_hart0_client_run_halt_request_get,
|
|
debug_module$RDY_hart0_client_run_halt_response_put,
|
|
debug_module$RDY_hart0_csr_mem_client_request_get,
|
|
debug_module$RDY_hart0_csr_mem_client_response_put,
|
|
debug_module$RDY_hart0_fpr_mem_client_request_get,
|
|
debug_module$RDY_hart0_fpr_mem_client_response_put,
|
|
debug_module$RDY_hart0_get_reset_req_get,
|
|
debug_module$RDY_hart0_gpr_mem_client_request_get,
|
|
debug_module$RDY_hart0_gpr_mem_client_response_put,
|
|
debug_module$hart0_client_run_halt_request_get,
|
|
debug_module$hart0_client_run_halt_response_put,
|
|
debug_module$master_arlock,
|
|
debug_module$master_arready,
|
|
debug_module$master_arvalid,
|
|
debug_module$master_awlock,
|
|
debug_module$master_awready,
|
|
debug_module$master_awvalid,
|
|
debug_module$master_bready,
|
|
debug_module$master_bvalid,
|
|
debug_module$master_rlast,
|
|
debug_module$master_rready,
|
|
debug_module$master_rvalid,
|
|
debug_module$master_wlast,
|
|
debug_module$master_wready,
|
|
debug_module$master_wvalid;
|
|
|
|
// ports of submodule dm_mem_tap
|
|
wire [361 : 0] dm_mem_tap$trace_data_out_get;
|
|
wire [63 : 0] dm_mem_tap$master_araddr,
|
|
dm_mem_tap$master_awaddr,
|
|
dm_mem_tap$master_rdata,
|
|
dm_mem_tap$master_wdata,
|
|
dm_mem_tap$slave_araddr,
|
|
dm_mem_tap$slave_awaddr,
|
|
dm_mem_tap$slave_rdata,
|
|
dm_mem_tap$slave_wdata;
|
|
wire [7 : 0] dm_mem_tap$master_arlen,
|
|
dm_mem_tap$master_awlen,
|
|
dm_mem_tap$master_wstrb,
|
|
dm_mem_tap$slave_arlen,
|
|
dm_mem_tap$slave_awlen,
|
|
dm_mem_tap$slave_wstrb;
|
|
wire [3 : 0] dm_mem_tap$master_arcache,
|
|
dm_mem_tap$master_arid,
|
|
dm_mem_tap$master_arqos,
|
|
dm_mem_tap$master_arregion,
|
|
dm_mem_tap$master_awcache,
|
|
dm_mem_tap$master_awid,
|
|
dm_mem_tap$master_awqos,
|
|
dm_mem_tap$master_awregion,
|
|
dm_mem_tap$master_bid,
|
|
dm_mem_tap$master_rid,
|
|
dm_mem_tap$master_wid,
|
|
dm_mem_tap$slave_arcache,
|
|
dm_mem_tap$slave_arid,
|
|
dm_mem_tap$slave_arqos,
|
|
dm_mem_tap$slave_arregion,
|
|
dm_mem_tap$slave_awcache,
|
|
dm_mem_tap$slave_awid,
|
|
dm_mem_tap$slave_awqos,
|
|
dm_mem_tap$slave_awregion,
|
|
dm_mem_tap$slave_bid,
|
|
dm_mem_tap$slave_rid,
|
|
dm_mem_tap$slave_wid;
|
|
wire [2 : 0] dm_mem_tap$master_arprot,
|
|
dm_mem_tap$master_arsize,
|
|
dm_mem_tap$master_awprot,
|
|
dm_mem_tap$master_awsize,
|
|
dm_mem_tap$slave_arprot,
|
|
dm_mem_tap$slave_arsize,
|
|
dm_mem_tap$slave_awprot,
|
|
dm_mem_tap$slave_awsize;
|
|
wire [1 : 0] dm_mem_tap$master_arburst,
|
|
dm_mem_tap$master_awburst,
|
|
dm_mem_tap$master_bresp,
|
|
dm_mem_tap$master_rresp,
|
|
dm_mem_tap$slave_arburst,
|
|
dm_mem_tap$slave_awburst,
|
|
dm_mem_tap$slave_bresp,
|
|
dm_mem_tap$slave_rresp;
|
|
wire dm_mem_tap$EN_trace_data_out_get,
|
|
dm_mem_tap$RDY_trace_data_out_get,
|
|
dm_mem_tap$master_arlock,
|
|
dm_mem_tap$master_arready,
|
|
dm_mem_tap$master_arvalid,
|
|
dm_mem_tap$master_awlock,
|
|
dm_mem_tap$master_awready,
|
|
dm_mem_tap$master_awvalid,
|
|
dm_mem_tap$master_bready,
|
|
dm_mem_tap$master_bvalid,
|
|
dm_mem_tap$master_rlast,
|
|
dm_mem_tap$master_rready,
|
|
dm_mem_tap$master_rvalid,
|
|
dm_mem_tap$master_wlast,
|
|
dm_mem_tap$master_wready,
|
|
dm_mem_tap$master_wvalid,
|
|
dm_mem_tap$slave_arlock,
|
|
dm_mem_tap$slave_arready,
|
|
dm_mem_tap$slave_arvalid,
|
|
dm_mem_tap$slave_awlock,
|
|
dm_mem_tap$slave_awready,
|
|
dm_mem_tap$slave_awvalid,
|
|
dm_mem_tap$slave_bready,
|
|
dm_mem_tap$slave_bvalid,
|
|
dm_mem_tap$slave_rlast,
|
|
dm_mem_tap$slave_rready,
|
|
dm_mem_tap$slave_rvalid,
|
|
dm_mem_tap$slave_wlast,
|
|
dm_mem_tap$slave_wready,
|
|
dm_mem_tap$slave_wvalid;
|
|
|
|
// ports of submodule f_reset_reqs
|
|
wire f_reset_reqs$CLR,
|
|
f_reset_reqs$DEQ,
|
|
f_reset_reqs$EMPTY_N,
|
|
f_reset_reqs$ENQ,
|
|
f_reset_reqs$FULL_N;
|
|
|
|
// ports of submodule f_reset_requestor
|
|
wire f_reset_requestor$CLR,
|
|
f_reset_requestor$DEQ,
|
|
f_reset_requestor$D_IN,
|
|
f_reset_requestor$D_OUT,
|
|
f_reset_requestor$EMPTY_N,
|
|
f_reset_requestor$ENQ,
|
|
f_reset_requestor$FULL_N;
|
|
|
|
// ports of submodule f_reset_rsps
|
|
wire f_reset_rsps$CLR,
|
|
f_reset_rsps$DEQ,
|
|
f_reset_rsps$EMPTY_N,
|
|
f_reset_rsps$ENQ,
|
|
f_reset_rsps$FULL_N;
|
|
|
|
// ports of submodule f_trace_data_merged
|
|
wire [361 : 0] f_trace_data_merged$D_IN, f_trace_data_merged$D_OUT;
|
|
wire f_trace_data_merged$CLR,
|
|
f_trace_data_merged$DEQ,
|
|
f_trace_data_merged$EMPTY_N,
|
|
f_trace_data_merged$ENQ,
|
|
f_trace_data_merged$FULL_N;
|
|
|
|
// ports of submodule fabric_2x3
|
|
wire [63 : 0] fabric_2x3$v_from_masters_0_araddr,
|
|
fabric_2x3$v_from_masters_0_awaddr,
|
|
fabric_2x3$v_from_masters_0_rdata,
|
|
fabric_2x3$v_from_masters_0_wdata,
|
|
fabric_2x3$v_from_masters_1_araddr,
|
|
fabric_2x3$v_from_masters_1_awaddr,
|
|
fabric_2x3$v_from_masters_1_rdata,
|
|
fabric_2x3$v_from_masters_1_wdata,
|
|
fabric_2x3$v_to_slaves_0_araddr,
|
|
fabric_2x3$v_to_slaves_0_awaddr,
|
|
fabric_2x3$v_to_slaves_0_rdata,
|
|
fabric_2x3$v_to_slaves_0_wdata,
|
|
fabric_2x3$v_to_slaves_1_araddr,
|
|
fabric_2x3$v_to_slaves_1_awaddr,
|
|
fabric_2x3$v_to_slaves_1_rdata,
|
|
fabric_2x3$v_to_slaves_1_wdata,
|
|
fabric_2x3$v_to_slaves_2_rdata;
|
|
wire [7 : 0] fabric_2x3$v_from_masters_0_arlen,
|
|
fabric_2x3$v_from_masters_0_awlen,
|
|
fabric_2x3$v_from_masters_0_wstrb,
|
|
fabric_2x3$v_from_masters_1_arlen,
|
|
fabric_2x3$v_from_masters_1_awlen,
|
|
fabric_2x3$v_from_masters_1_wstrb,
|
|
fabric_2x3$v_to_slaves_0_arlen,
|
|
fabric_2x3$v_to_slaves_0_awlen,
|
|
fabric_2x3$v_to_slaves_0_wstrb,
|
|
fabric_2x3$v_to_slaves_1_arlen,
|
|
fabric_2x3$v_to_slaves_1_awlen,
|
|
fabric_2x3$v_to_slaves_1_wstrb;
|
|
wire [3 : 0] fabric_2x3$set_verbosity_verbosity,
|
|
fabric_2x3$v_from_masters_0_arcache,
|
|
fabric_2x3$v_from_masters_0_arid,
|
|
fabric_2x3$v_from_masters_0_arqos,
|
|
fabric_2x3$v_from_masters_0_arregion,
|
|
fabric_2x3$v_from_masters_0_awcache,
|
|
fabric_2x3$v_from_masters_0_awid,
|
|
fabric_2x3$v_from_masters_0_awqos,
|
|
fabric_2x3$v_from_masters_0_awregion,
|
|
fabric_2x3$v_from_masters_0_bid,
|
|
fabric_2x3$v_from_masters_0_rid,
|
|
fabric_2x3$v_from_masters_0_wid,
|
|
fabric_2x3$v_from_masters_1_arcache,
|
|
fabric_2x3$v_from_masters_1_arid,
|
|
fabric_2x3$v_from_masters_1_arqos,
|
|
fabric_2x3$v_from_masters_1_arregion,
|
|
fabric_2x3$v_from_masters_1_awcache,
|
|
fabric_2x3$v_from_masters_1_awid,
|
|
fabric_2x3$v_from_masters_1_awqos,
|
|
fabric_2x3$v_from_masters_1_awregion,
|
|
fabric_2x3$v_from_masters_1_bid,
|
|
fabric_2x3$v_from_masters_1_rid,
|
|
fabric_2x3$v_from_masters_1_wid,
|
|
fabric_2x3$v_to_slaves_0_arcache,
|
|
fabric_2x3$v_to_slaves_0_arid,
|
|
fabric_2x3$v_to_slaves_0_arqos,
|
|
fabric_2x3$v_to_slaves_0_arregion,
|
|
fabric_2x3$v_to_slaves_0_awcache,
|
|
fabric_2x3$v_to_slaves_0_awid,
|
|
fabric_2x3$v_to_slaves_0_awqos,
|
|
fabric_2x3$v_to_slaves_0_awregion,
|
|
fabric_2x3$v_to_slaves_0_bid,
|
|
fabric_2x3$v_to_slaves_0_rid,
|
|
fabric_2x3$v_to_slaves_0_wid,
|
|
fabric_2x3$v_to_slaves_1_arcache,
|
|
fabric_2x3$v_to_slaves_1_arid,
|
|
fabric_2x3$v_to_slaves_1_arqos,
|
|
fabric_2x3$v_to_slaves_1_arregion,
|
|
fabric_2x3$v_to_slaves_1_awcache,
|
|
fabric_2x3$v_to_slaves_1_awid,
|
|
fabric_2x3$v_to_slaves_1_awqos,
|
|
fabric_2x3$v_to_slaves_1_awregion,
|
|
fabric_2x3$v_to_slaves_1_bid,
|
|
fabric_2x3$v_to_slaves_1_rid,
|
|
fabric_2x3$v_to_slaves_1_wid,
|
|
fabric_2x3$v_to_slaves_2_bid,
|
|
fabric_2x3$v_to_slaves_2_rid;
|
|
wire [2 : 0] fabric_2x3$v_from_masters_0_arprot,
|
|
fabric_2x3$v_from_masters_0_arsize,
|
|
fabric_2x3$v_from_masters_0_awprot,
|
|
fabric_2x3$v_from_masters_0_awsize,
|
|
fabric_2x3$v_from_masters_1_arprot,
|
|
fabric_2x3$v_from_masters_1_arsize,
|
|
fabric_2x3$v_from_masters_1_awprot,
|
|
fabric_2x3$v_from_masters_1_awsize,
|
|
fabric_2x3$v_to_slaves_0_arprot,
|
|
fabric_2x3$v_to_slaves_0_arsize,
|
|
fabric_2x3$v_to_slaves_0_awprot,
|
|
fabric_2x3$v_to_slaves_0_awsize,
|
|
fabric_2x3$v_to_slaves_1_arprot,
|
|
fabric_2x3$v_to_slaves_1_arsize,
|
|
fabric_2x3$v_to_slaves_1_awprot,
|
|
fabric_2x3$v_to_slaves_1_awsize;
|
|
wire [1 : 0] fabric_2x3$v_from_masters_0_arburst,
|
|
fabric_2x3$v_from_masters_0_awburst,
|
|
fabric_2x3$v_from_masters_0_bresp,
|
|
fabric_2x3$v_from_masters_0_rresp,
|
|
fabric_2x3$v_from_masters_1_arburst,
|
|
fabric_2x3$v_from_masters_1_awburst,
|
|
fabric_2x3$v_from_masters_1_bresp,
|
|
fabric_2x3$v_from_masters_1_rresp,
|
|
fabric_2x3$v_to_slaves_0_arburst,
|
|
fabric_2x3$v_to_slaves_0_awburst,
|
|
fabric_2x3$v_to_slaves_0_bresp,
|
|
fabric_2x3$v_to_slaves_0_rresp,
|
|
fabric_2x3$v_to_slaves_1_arburst,
|
|
fabric_2x3$v_to_slaves_1_awburst,
|
|
fabric_2x3$v_to_slaves_1_bresp,
|
|
fabric_2x3$v_to_slaves_1_rresp,
|
|
fabric_2x3$v_to_slaves_2_bresp,
|
|
fabric_2x3$v_to_slaves_2_rresp;
|
|
wire fabric_2x3$EN_reset,
|
|
fabric_2x3$EN_set_verbosity,
|
|
fabric_2x3$RDY_reset,
|
|
fabric_2x3$v_from_masters_0_arlock,
|
|
fabric_2x3$v_from_masters_0_arready,
|
|
fabric_2x3$v_from_masters_0_arvalid,
|
|
fabric_2x3$v_from_masters_0_awlock,
|
|
fabric_2x3$v_from_masters_0_awready,
|
|
fabric_2x3$v_from_masters_0_awvalid,
|
|
fabric_2x3$v_from_masters_0_bready,
|
|
fabric_2x3$v_from_masters_0_bvalid,
|
|
fabric_2x3$v_from_masters_0_rlast,
|
|
fabric_2x3$v_from_masters_0_rready,
|
|
fabric_2x3$v_from_masters_0_rvalid,
|
|
fabric_2x3$v_from_masters_0_wlast,
|
|
fabric_2x3$v_from_masters_0_wready,
|
|
fabric_2x3$v_from_masters_0_wvalid,
|
|
fabric_2x3$v_from_masters_1_arlock,
|
|
fabric_2x3$v_from_masters_1_arready,
|
|
fabric_2x3$v_from_masters_1_arvalid,
|
|
fabric_2x3$v_from_masters_1_awlock,
|
|
fabric_2x3$v_from_masters_1_awready,
|
|
fabric_2x3$v_from_masters_1_awvalid,
|
|
fabric_2x3$v_from_masters_1_bready,
|
|
fabric_2x3$v_from_masters_1_bvalid,
|
|
fabric_2x3$v_from_masters_1_rlast,
|
|
fabric_2x3$v_from_masters_1_rready,
|
|
fabric_2x3$v_from_masters_1_rvalid,
|
|
fabric_2x3$v_from_masters_1_wlast,
|
|
fabric_2x3$v_from_masters_1_wready,
|
|
fabric_2x3$v_from_masters_1_wvalid,
|
|
fabric_2x3$v_to_slaves_0_arlock,
|
|
fabric_2x3$v_to_slaves_0_arready,
|
|
fabric_2x3$v_to_slaves_0_arvalid,
|
|
fabric_2x3$v_to_slaves_0_awlock,
|
|
fabric_2x3$v_to_slaves_0_awready,
|
|
fabric_2x3$v_to_slaves_0_awvalid,
|
|
fabric_2x3$v_to_slaves_0_bready,
|
|
fabric_2x3$v_to_slaves_0_bvalid,
|
|
fabric_2x3$v_to_slaves_0_rlast,
|
|
fabric_2x3$v_to_slaves_0_rready,
|
|
fabric_2x3$v_to_slaves_0_rvalid,
|
|
fabric_2x3$v_to_slaves_0_wlast,
|
|
fabric_2x3$v_to_slaves_0_wready,
|
|
fabric_2x3$v_to_slaves_0_wvalid,
|
|
fabric_2x3$v_to_slaves_1_arlock,
|
|
fabric_2x3$v_to_slaves_1_arready,
|
|
fabric_2x3$v_to_slaves_1_arvalid,
|
|
fabric_2x3$v_to_slaves_1_awlock,
|
|
fabric_2x3$v_to_slaves_1_awready,
|
|
fabric_2x3$v_to_slaves_1_awvalid,
|
|
fabric_2x3$v_to_slaves_1_bready,
|
|
fabric_2x3$v_to_slaves_1_bvalid,
|
|
fabric_2x3$v_to_slaves_1_rlast,
|
|
fabric_2x3$v_to_slaves_1_rready,
|
|
fabric_2x3$v_to_slaves_1_rvalid,
|
|
fabric_2x3$v_to_slaves_1_wlast,
|
|
fabric_2x3$v_to_slaves_1_wready,
|
|
fabric_2x3$v_to_slaves_1_wvalid,
|
|
fabric_2x3$v_to_slaves_2_arready,
|
|
fabric_2x3$v_to_slaves_2_awready,
|
|
fabric_2x3$v_to_slaves_2_bvalid,
|
|
fabric_2x3$v_to_slaves_2_rlast,
|
|
fabric_2x3$v_to_slaves_2_rvalid,
|
|
fabric_2x3$v_to_slaves_2_wready;
|
|
|
|
// ports of submodule plic
|
|
wire [63 : 0] plic$axi4_slave_araddr,
|
|
plic$axi4_slave_awaddr,
|
|
plic$axi4_slave_rdata,
|
|
plic$axi4_slave_wdata,
|
|
plic$set_addr_map_addr_base,
|
|
plic$set_addr_map_addr_lim;
|
|
wire [7 : 0] plic$axi4_slave_arlen,
|
|
plic$axi4_slave_awlen,
|
|
plic$axi4_slave_wstrb;
|
|
wire [3 : 0] plic$axi4_slave_arcache,
|
|
plic$axi4_slave_arid,
|
|
plic$axi4_slave_arqos,
|
|
plic$axi4_slave_arregion,
|
|
plic$axi4_slave_awcache,
|
|
plic$axi4_slave_awid,
|
|
plic$axi4_slave_awqos,
|
|
plic$axi4_slave_awregion,
|
|
plic$axi4_slave_bid,
|
|
plic$axi4_slave_rid,
|
|
plic$axi4_slave_wid,
|
|
plic$set_verbosity_verbosity;
|
|
wire [2 : 0] plic$axi4_slave_arprot,
|
|
plic$axi4_slave_arsize,
|
|
plic$axi4_slave_awprot,
|
|
plic$axi4_slave_awsize;
|
|
wire [1 : 0] plic$axi4_slave_arburst,
|
|
plic$axi4_slave_awburst,
|
|
plic$axi4_slave_bresp,
|
|
plic$axi4_slave_rresp;
|
|
wire plic$EN_server_reset_request_put,
|
|
plic$EN_server_reset_response_get,
|
|
plic$EN_set_addr_map,
|
|
plic$EN_set_verbosity,
|
|
plic$EN_show_PLIC_state,
|
|
plic$RDY_server_reset_request_put,
|
|
plic$RDY_server_reset_response_get,
|
|
plic$axi4_slave_arlock,
|
|
plic$axi4_slave_arready,
|
|
plic$axi4_slave_arvalid,
|
|
plic$axi4_slave_awlock,
|
|
plic$axi4_slave_awready,
|
|
plic$axi4_slave_awvalid,
|
|
plic$axi4_slave_bready,
|
|
plic$axi4_slave_bvalid,
|
|
plic$axi4_slave_rlast,
|
|
plic$axi4_slave_rready,
|
|
plic$axi4_slave_rvalid,
|
|
plic$axi4_slave_wlast,
|
|
plic$axi4_slave_wready,
|
|
plic$axi4_slave_wvalid,
|
|
plic$v_sources_0_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_10_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_11_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_12_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_13_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_14_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_15_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_1_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_2_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_3_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_4_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_5_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_6_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_7_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_8_m_interrupt_req_set_not_clear,
|
|
plic$v_sources_9_m_interrupt_req_set_not_clear,
|
|
plic$v_targets_0_m_eip,
|
|
plic$v_targets_1_m_eip;
|
|
|
|
// ports of submodule proc
|
|
wire [361 : 0] proc$trace_data_out_get;
|
|
wire [76 : 0] proc$hart0_csr_mem_server_request_put;
|
|
wire [69 : 0] proc$hart0_fpr_mem_server_request_put,
|
|
proc$hart0_gpr_mem_server_request_put;
|
|
wire [63 : 0] proc$master0_araddr,
|
|
proc$master0_awaddr,
|
|
proc$master0_rdata,
|
|
proc$master0_wdata,
|
|
proc$master1_araddr,
|
|
proc$master1_awaddr,
|
|
proc$master1_rdata,
|
|
proc$master1_wdata,
|
|
proc$start_fromhostAddr,
|
|
proc$start_startpc,
|
|
proc$start_tohostAddr;
|
|
wire [7 : 0] proc$master0_arlen,
|
|
proc$master0_awlen,
|
|
proc$master0_wstrb,
|
|
proc$master1_arlen,
|
|
proc$master1_awlen,
|
|
proc$master1_wstrb;
|
|
wire [3 : 0] proc$hart0_put_other_req_put,
|
|
proc$master0_arcache,
|
|
proc$master0_arid,
|
|
proc$master0_arqos,
|
|
proc$master0_arregion,
|
|
proc$master0_awcache,
|
|
proc$master0_awid,
|
|
proc$master0_awqos,
|
|
proc$master0_awregion,
|
|
proc$master0_bid,
|
|
proc$master0_rid,
|
|
proc$master0_wid,
|
|
proc$master1_arcache,
|
|
proc$master1_arid,
|
|
proc$master1_arqos,
|
|
proc$master1_arregion,
|
|
proc$master1_awcache,
|
|
proc$master1_awid,
|
|
proc$master1_awqos,
|
|
proc$master1_awregion,
|
|
proc$master1_bid,
|
|
proc$master1_rid,
|
|
proc$master1_wid,
|
|
proc$set_verbosity_verbosity;
|
|
wire [2 : 0] proc$master0_arprot,
|
|
proc$master0_arsize,
|
|
proc$master0_awprot,
|
|
proc$master0_awsize,
|
|
proc$master1_arprot,
|
|
proc$master1_arsize,
|
|
proc$master1_awprot,
|
|
proc$master1_awsize;
|
|
wire [1 : 0] proc$master0_arburst,
|
|
proc$master0_awburst,
|
|
proc$master0_bresp,
|
|
proc$master0_rresp,
|
|
proc$master1_arburst,
|
|
proc$master1_awburst,
|
|
proc$master1_bresp,
|
|
proc$master1_rresp;
|
|
wire proc$EN_hart0_csr_mem_server_request_put,
|
|
proc$EN_hart0_csr_mem_server_response_get,
|
|
proc$EN_hart0_fpr_mem_server_request_put,
|
|
proc$EN_hart0_fpr_mem_server_response_get,
|
|
proc$EN_hart0_gpr_mem_server_request_put,
|
|
proc$EN_hart0_gpr_mem_server_response_get,
|
|
proc$EN_hart0_put_other_req_put,
|
|
proc$EN_hart0_server_reset_request_put,
|
|
proc$EN_hart0_server_reset_response_get,
|
|
proc$EN_hart0_server_run_halt_request_put,
|
|
proc$EN_hart0_server_run_halt_response_get,
|
|
proc$EN_set_verbosity,
|
|
proc$EN_start,
|
|
proc$EN_trace_data_out_get,
|
|
proc$RDY_hart0_server_reset_request_put,
|
|
proc$RDY_hart0_server_reset_response_get,
|
|
proc$RDY_start,
|
|
proc$RDY_trace_data_out_get,
|
|
proc$debug_external_interrupt_req_set_not_clear,
|
|
proc$hart0_server_run_halt_request_put,
|
|
proc$m_external_interrupt_req_set_not_clear,
|
|
proc$master0_arlock,
|
|
proc$master0_arready,
|
|
proc$master0_arvalid,
|
|
proc$master0_awlock,
|
|
proc$master0_awready,
|
|
proc$master0_awvalid,
|
|
proc$master0_bready,
|
|
proc$master0_bvalid,
|
|
proc$master0_rlast,
|
|
proc$master0_rready,
|
|
proc$master0_rvalid,
|
|
proc$master0_wlast,
|
|
proc$master0_wready,
|
|
proc$master0_wvalid,
|
|
proc$master1_arlock,
|
|
proc$master1_arready,
|
|
proc$master1_arvalid,
|
|
proc$master1_awlock,
|
|
proc$master1_awready,
|
|
proc$master1_awvalid,
|
|
proc$master1_bready,
|
|
proc$master1_bvalid,
|
|
proc$master1_rlast,
|
|
proc$master1_rready,
|
|
proc$master1_rvalid,
|
|
proc$master1_wlast,
|
|
proc$master1_wready,
|
|
proc$master1_wvalid,
|
|
proc$non_maskable_interrupt_req_set_not_clear,
|
|
proc$s_external_interrupt_req_set_not_clear;
|
|
|
|
// ports of submodule soc_map
|
|
wire [63 : 0] soc_map$m_is_IO_addr_addr,
|
|
soc_map$m_is_mem_addr_addr,
|
|
soc_map$m_is_near_mem_IO_addr_addr,
|
|
soc_map$m_plic_addr_base,
|
|
soc_map$m_plic_addr_lim;
|
|
|
|
// ports of submodule tv_encode
|
|
wire [607 : 0] tv_encode$tv_vb_out_get;
|
|
wire [361 : 0] tv_encode$trace_data_in_put;
|
|
wire tv_encode$EN_reset,
|
|
tv_encode$EN_trace_data_in_put,
|
|
tv_encode$EN_tv_vb_out_get,
|
|
tv_encode$RDY_trace_data_in_put,
|
|
tv_encode$RDY_tv_vb_out_get;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_merge_cpu_trace_data,
|
|
CAN_FIRE_RL_merge_dm_mem_trace_data,
|
|
CAN_FIRE_RL_mkConnectionGetPut,
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_complete,
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete,
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start,
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
|
|
CAN_FIRE_RL_rl_csr,
|
|
CAN_FIRE_RL_rl_fpr,
|
|
CAN_FIRE_RL_rl_gpr,
|
|
CAN_FIRE_RL_rl_halt,
|
|
CAN_FIRE_RL_rl_halt_reset,
|
|
CAN_FIRE_RL_rl_hart0_server_reset,
|
|
CAN_FIRE_RL_rl_hart0_server_run_halt,
|
|
CAN_FIRE_RL_rl_once,
|
|
CAN_FIRE_RL_rl_rd_addr_channel,
|
|
CAN_FIRE_RL_rl_rd_addr_channel_1,
|
|
CAN_FIRE_RL_rl_rd_addr_channel_2,
|
|
CAN_FIRE_RL_rl_rd_addr_channel_3,
|
|
CAN_FIRE_RL_rl_rd_addr_channel_4,
|
|
CAN_FIRE_RL_rl_rd_data_channel,
|
|
CAN_FIRE_RL_rl_rd_data_channel_1,
|
|
CAN_FIRE_RL_rl_rd_data_channel_2,
|
|
CAN_FIRE_RL_rl_rd_data_channel_3,
|
|
CAN_FIRE_RL_rl_rd_data_channel_4,
|
|
CAN_FIRE_RL_rl_relay_external_interrupts,
|
|
CAN_FIRE_RL_rl_relay_non_maskable_interrupt,
|
|
CAN_FIRE_RL_rl_wr_addr_channel,
|
|
CAN_FIRE_RL_rl_wr_addr_channel_1,
|
|
CAN_FIRE_RL_rl_wr_addr_channel_2,
|
|
CAN_FIRE_RL_rl_wr_addr_channel_3,
|
|
CAN_FIRE_RL_rl_wr_addr_channel_4,
|
|
CAN_FIRE_RL_rl_wr_data_channel,
|
|
CAN_FIRE_RL_rl_wr_data_channel_1,
|
|
CAN_FIRE_RL_rl_wr_data_channel_2,
|
|
CAN_FIRE_RL_rl_wr_data_channel_3,
|
|
CAN_FIRE_RL_rl_wr_data_channel_4,
|
|
CAN_FIRE_RL_rl_wr_response_channel,
|
|
CAN_FIRE_RL_rl_wr_response_channel_1,
|
|
CAN_FIRE_RL_rl_wr_response_channel_2,
|
|
CAN_FIRE_RL_rl_wr_response_channel_3,
|
|
CAN_FIRE_RL_rl_wr_response_channel_4,
|
|
CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
|
|
CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
|
|
CAN_FIRE_cpu_dmem_master_m_arready,
|
|
CAN_FIRE_cpu_dmem_master_m_awready,
|
|
CAN_FIRE_cpu_dmem_master_m_bvalid,
|
|
CAN_FIRE_cpu_dmem_master_m_rvalid,
|
|
CAN_FIRE_cpu_dmem_master_m_wready,
|
|
CAN_FIRE_cpu_imem_master_m_arready,
|
|
CAN_FIRE_cpu_imem_master_m_awready,
|
|
CAN_FIRE_cpu_imem_master_m_bvalid,
|
|
CAN_FIRE_cpu_imem_master_m_rvalid,
|
|
CAN_FIRE_cpu_imem_master_m_wready,
|
|
CAN_FIRE_cpu_reset_server_request_put,
|
|
CAN_FIRE_cpu_reset_server_response_get,
|
|
CAN_FIRE_debug_external_interrupt_req,
|
|
CAN_FIRE_dm_dmi_read_addr,
|
|
CAN_FIRE_dm_dmi_read_data,
|
|
CAN_FIRE_dm_dmi_write,
|
|
CAN_FIRE_dm_ndm_reset_req_get_get,
|
|
CAN_FIRE_set_htif_addrs,
|
|
CAN_FIRE_set_verbosity,
|
|
CAN_FIRE_tv_verifier_info_get_get,
|
|
WILL_FIRE_RL_merge_cpu_trace_data,
|
|
WILL_FIRE_RL_merge_dm_mem_trace_data,
|
|
WILL_FIRE_RL_mkConnectionGetPut,
|
|
WILL_FIRE_RL_rl_cpu_hart0_reset_complete,
|
|
WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete,
|
|
WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start,
|
|
WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
|
|
WILL_FIRE_RL_rl_csr,
|
|
WILL_FIRE_RL_rl_fpr,
|
|
WILL_FIRE_RL_rl_gpr,
|
|
WILL_FIRE_RL_rl_halt,
|
|
WILL_FIRE_RL_rl_halt_reset,
|
|
WILL_FIRE_RL_rl_hart0_server_reset,
|
|
WILL_FIRE_RL_rl_hart0_server_run_halt,
|
|
WILL_FIRE_RL_rl_once,
|
|
WILL_FIRE_RL_rl_rd_addr_channel,
|
|
WILL_FIRE_RL_rl_rd_addr_channel_1,
|
|
WILL_FIRE_RL_rl_rd_addr_channel_2,
|
|
WILL_FIRE_RL_rl_rd_addr_channel_3,
|
|
WILL_FIRE_RL_rl_rd_addr_channel_4,
|
|
WILL_FIRE_RL_rl_rd_data_channel,
|
|
WILL_FIRE_RL_rl_rd_data_channel_1,
|
|
WILL_FIRE_RL_rl_rd_data_channel_2,
|
|
WILL_FIRE_RL_rl_rd_data_channel_3,
|
|
WILL_FIRE_RL_rl_rd_data_channel_4,
|
|
WILL_FIRE_RL_rl_relay_external_interrupts,
|
|
WILL_FIRE_RL_rl_relay_non_maskable_interrupt,
|
|
WILL_FIRE_RL_rl_wr_addr_channel,
|
|
WILL_FIRE_RL_rl_wr_addr_channel_1,
|
|
WILL_FIRE_RL_rl_wr_addr_channel_2,
|
|
WILL_FIRE_RL_rl_wr_addr_channel_3,
|
|
WILL_FIRE_RL_rl_wr_addr_channel_4,
|
|
WILL_FIRE_RL_rl_wr_data_channel,
|
|
WILL_FIRE_RL_rl_wr_data_channel_1,
|
|
WILL_FIRE_RL_rl_wr_data_channel_2,
|
|
WILL_FIRE_RL_rl_wr_data_channel_3,
|
|
WILL_FIRE_RL_rl_wr_data_channel_4,
|
|
WILL_FIRE_RL_rl_wr_response_channel,
|
|
WILL_FIRE_RL_rl_wr_response_channel_1,
|
|
WILL_FIRE_RL_rl_wr_response_channel_2,
|
|
WILL_FIRE_RL_rl_wr_response_channel_3,
|
|
WILL_FIRE_RL_rl_wr_response_channel_4,
|
|
WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
|
|
WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
|
|
WILL_FIRE_cpu_dmem_master_m_arready,
|
|
WILL_FIRE_cpu_dmem_master_m_awready,
|
|
WILL_FIRE_cpu_dmem_master_m_bvalid,
|
|
WILL_FIRE_cpu_dmem_master_m_rvalid,
|
|
WILL_FIRE_cpu_dmem_master_m_wready,
|
|
WILL_FIRE_cpu_imem_master_m_arready,
|
|
WILL_FIRE_cpu_imem_master_m_awready,
|
|
WILL_FIRE_cpu_imem_master_m_bvalid,
|
|
WILL_FIRE_cpu_imem_master_m_rvalid,
|
|
WILL_FIRE_cpu_imem_master_m_wready,
|
|
WILL_FIRE_cpu_reset_server_request_put,
|
|
WILL_FIRE_cpu_reset_server_response_get,
|
|
WILL_FIRE_debug_external_interrupt_req,
|
|
WILL_FIRE_dm_dmi_read_addr,
|
|
WILL_FIRE_dm_dmi_read_data,
|
|
WILL_FIRE_dm_dmi_write,
|
|
WILL_FIRE_dm_ndm_reset_req_get_get,
|
|
WILL_FIRE_set_htif_addrs,
|
|
WILL_FIRE_set_verbosity,
|
|
WILL_FIRE_tv_verifier_info_get_get;
|
|
|
|
// declarations used by system tasks
|
|
// synopsys translate_off
|
|
reg [31 : 0] v__h5014;
|
|
reg [31 : 0] v__h4855;
|
|
reg [31 : 0] v__h4849;
|
|
reg [31 : 0] v__h5008;
|
|
// synopsys translate_on
|
|
|
|
// action method set_verbosity
|
|
assign RDY_set_verbosity = 1'd1 ;
|
|
assign CAN_FIRE_set_verbosity = 1'd1 ;
|
|
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
|
|
|
|
// action method set_htif_addrs
|
|
assign RDY_set_htif_addrs = 1'd1 ;
|
|
assign CAN_FIRE_set_htif_addrs = 1'd1 ;
|
|
assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ;
|
|
|
|
// action method cpu_reset_server_request_put
|
|
assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
|
|
assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
|
|
assign WILL_FIRE_cpu_reset_server_request_put =
|
|
EN_cpu_reset_server_request_put ;
|
|
|
|
// action method cpu_reset_server_response_get
|
|
assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
|
|
assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
|
|
assign WILL_FIRE_cpu_reset_server_response_get =
|
|
EN_cpu_reset_server_response_get ;
|
|
|
|
// value method cpu_imem_master_m_awvalid
|
|
assign cpu_imem_master_awvalid = proc$master0_awvalid ;
|
|
|
|
// value method cpu_imem_master_m_awid
|
|
assign cpu_imem_master_awid = proc$master0_awid ;
|
|
|
|
// value method cpu_imem_master_m_awaddr
|
|
assign cpu_imem_master_awaddr = proc$master0_awaddr ;
|
|
|
|
// value method cpu_imem_master_m_awlen
|
|
assign cpu_imem_master_awlen = proc$master0_awlen ;
|
|
|
|
// value method cpu_imem_master_m_awsize
|
|
assign cpu_imem_master_awsize = proc$master0_awsize ;
|
|
|
|
// value method cpu_imem_master_m_awburst
|
|
assign cpu_imem_master_awburst = proc$master0_awburst ;
|
|
|
|
// value method cpu_imem_master_m_awlock
|
|
assign cpu_imem_master_awlock = proc$master0_awlock ;
|
|
|
|
// value method cpu_imem_master_m_awcache
|
|
assign cpu_imem_master_awcache = proc$master0_awcache ;
|
|
|
|
// value method cpu_imem_master_m_awprot
|
|
assign cpu_imem_master_awprot = proc$master0_awprot ;
|
|
|
|
// value method cpu_imem_master_m_awqos
|
|
assign cpu_imem_master_awqos = proc$master0_awqos ;
|
|
|
|
// value method cpu_imem_master_m_awregion
|
|
assign cpu_imem_master_awregion = proc$master0_awregion ;
|
|
|
|
// action method cpu_imem_master_m_awready
|
|
assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ;
|
|
assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ;
|
|
|
|
// value method cpu_imem_master_m_wvalid
|
|
assign cpu_imem_master_wvalid = proc$master0_wvalid ;
|
|
|
|
// value method cpu_imem_master_m_wid
|
|
assign cpu_imem_master_wid = proc$master0_wid ;
|
|
|
|
// value method cpu_imem_master_m_wdata
|
|
assign cpu_imem_master_wdata = proc$master0_wdata ;
|
|
|
|
// value method cpu_imem_master_m_wstrb
|
|
assign cpu_imem_master_wstrb = proc$master0_wstrb ;
|
|
|
|
// value method cpu_imem_master_m_wlast
|
|
assign cpu_imem_master_wlast = proc$master0_wlast ;
|
|
|
|
// action method cpu_imem_master_m_wready
|
|
assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ;
|
|
assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ;
|
|
|
|
// action method cpu_imem_master_m_bvalid
|
|
assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
|
|
assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
|
|
|
|
// value method cpu_imem_master_m_bready
|
|
assign cpu_imem_master_bready = proc$master0_bready ;
|
|
|
|
// value method cpu_imem_master_m_arvalid
|
|
assign cpu_imem_master_arvalid = proc$master0_arvalid ;
|
|
|
|
// value method cpu_imem_master_m_arid
|
|
assign cpu_imem_master_arid = proc$master0_arid ;
|
|
|
|
// value method cpu_imem_master_m_araddr
|
|
assign cpu_imem_master_araddr = proc$master0_araddr ;
|
|
|
|
// value method cpu_imem_master_m_arlen
|
|
assign cpu_imem_master_arlen = proc$master0_arlen ;
|
|
|
|
// value method cpu_imem_master_m_arsize
|
|
assign cpu_imem_master_arsize = proc$master0_arsize ;
|
|
|
|
// value method cpu_imem_master_m_arburst
|
|
assign cpu_imem_master_arburst = proc$master0_arburst ;
|
|
|
|
// value method cpu_imem_master_m_arlock
|
|
assign cpu_imem_master_arlock = proc$master0_arlock ;
|
|
|
|
// value method cpu_imem_master_m_arcache
|
|
assign cpu_imem_master_arcache = proc$master0_arcache ;
|
|
|
|
// value method cpu_imem_master_m_arprot
|
|
assign cpu_imem_master_arprot = proc$master0_arprot ;
|
|
|
|
// value method cpu_imem_master_m_arqos
|
|
assign cpu_imem_master_arqos = proc$master0_arqos ;
|
|
|
|
// value method cpu_imem_master_m_arregion
|
|
assign cpu_imem_master_arregion = proc$master0_arregion ;
|
|
|
|
// action method cpu_imem_master_m_arready
|
|
assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ;
|
|
assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ;
|
|
|
|
// action method cpu_imem_master_m_rvalid
|
|
assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
|
|
assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
|
|
|
|
// value method cpu_imem_master_m_rready
|
|
assign cpu_imem_master_rready = proc$master0_rready ;
|
|
|
|
// value method cpu_dmem_master_m_awvalid
|
|
assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ;
|
|
|
|
// value method cpu_dmem_master_m_awid
|
|
assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ;
|
|
|
|
// value method cpu_dmem_master_m_awaddr
|
|
assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ;
|
|
|
|
// value method cpu_dmem_master_m_awlen
|
|
assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ;
|
|
|
|
// value method cpu_dmem_master_m_awsize
|
|
assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ;
|
|
|
|
// value method cpu_dmem_master_m_awburst
|
|
assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ;
|
|
|
|
// value method cpu_dmem_master_m_awlock
|
|
assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ;
|
|
|
|
// value method cpu_dmem_master_m_awcache
|
|
assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ;
|
|
|
|
// value method cpu_dmem_master_m_awprot
|
|
assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ;
|
|
|
|
// value method cpu_dmem_master_m_awqos
|
|
assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ;
|
|
|
|
// value method cpu_dmem_master_m_awregion
|
|
assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ;
|
|
|
|
// action method cpu_dmem_master_m_awready
|
|
assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ;
|
|
assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ;
|
|
|
|
// value method cpu_dmem_master_m_wvalid
|
|
assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ;
|
|
|
|
// value method cpu_dmem_master_m_wid
|
|
assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ;
|
|
|
|
// value method cpu_dmem_master_m_wdata
|
|
assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ;
|
|
|
|
// value method cpu_dmem_master_m_wstrb
|
|
assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ;
|
|
|
|
// value method cpu_dmem_master_m_wlast
|
|
assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ;
|
|
|
|
// action method cpu_dmem_master_m_wready
|
|
assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ;
|
|
assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ;
|
|
|
|
// action method cpu_dmem_master_m_bvalid
|
|
assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ;
|
|
assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ;
|
|
|
|
// value method cpu_dmem_master_m_bready
|
|
assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ;
|
|
|
|
// value method cpu_dmem_master_m_arvalid
|
|
assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ;
|
|
|
|
// value method cpu_dmem_master_m_arid
|
|
assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ;
|
|
|
|
// value method cpu_dmem_master_m_araddr
|
|
assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ;
|
|
|
|
// value method cpu_dmem_master_m_arlen
|
|
assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ;
|
|
|
|
// value method cpu_dmem_master_m_arsize
|
|
assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ;
|
|
|
|
// value method cpu_dmem_master_m_arburst
|
|
assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ;
|
|
|
|
// value method cpu_dmem_master_m_arlock
|
|
assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ;
|
|
|
|
// value method cpu_dmem_master_m_arcache
|
|
assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ;
|
|
|
|
// value method cpu_dmem_master_m_arprot
|
|
assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ;
|
|
|
|
// value method cpu_dmem_master_m_arqos
|
|
assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ;
|
|
|
|
// value method cpu_dmem_master_m_arregion
|
|
assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ;
|
|
|
|
// action method cpu_dmem_master_m_arready
|
|
assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ;
|
|
assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ;
|
|
|
|
// action method cpu_dmem_master_m_rvalid
|
|
assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ;
|
|
assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ;
|
|
|
|
// value method cpu_dmem_master_m_rready
|
|
assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ;
|
|
|
|
// action method core_external_interrupt_sources_0_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_1_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_2_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_3_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_4_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_5_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_6_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_7_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_8_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_9_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_10_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_11_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_12_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_13_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_14_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method core_external_interrupt_sources_15_m_interrupt_req
|
|
assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
|
|
|
|
// action method debug_external_interrupt_req
|
|
assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ;
|
|
assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ;
|
|
|
|
// actionvalue method tv_verifier_info_get_get
|
|
assign tv_verifier_info_get_get = tv_encode$tv_vb_out_get ;
|
|
assign RDY_tv_verifier_info_get_get = tv_encode$RDY_tv_vb_out_get ;
|
|
assign CAN_FIRE_tv_verifier_info_get_get = tv_encode$RDY_tv_vb_out_get ;
|
|
assign WILL_FIRE_tv_verifier_info_get_get = EN_tv_verifier_info_get_get ;
|
|
|
|
// action method dm_dmi_read_addr
|
|
assign RDY_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ;
|
|
assign CAN_FIRE_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ;
|
|
assign WILL_FIRE_dm_dmi_read_addr = EN_dm_dmi_read_addr ;
|
|
|
|
// actionvalue method dm_dmi_read_data
|
|
assign dm_dmi_read_data = debug_module$dmi_read_data ;
|
|
assign RDY_dm_dmi_read_data = debug_module$RDY_dmi_read_data ;
|
|
assign CAN_FIRE_dm_dmi_read_data = debug_module$RDY_dmi_read_data ;
|
|
assign WILL_FIRE_dm_dmi_read_data = EN_dm_dmi_read_data ;
|
|
|
|
// action method dm_dmi_write
|
|
assign RDY_dm_dmi_write = debug_module$RDY_dmi_write ;
|
|
assign CAN_FIRE_dm_dmi_write = debug_module$RDY_dmi_write ;
|
|
assign WILL_FIRE_dm_dmi_write = EN_dm_dmi_write ;
|
|
|
|
// action method dm_ndm_reset_req_get_get
|
|
assign RDY_dm_ndm_reset_req_get_get =
|
|
debug_module$RDY_get_ndm_reset_req_get ;
|
|
assign CAN_FIRE_dm_ndm_reset_req_get_get =
|
|
debug_module$RDY_get_ndm_reset_req_get ;
|
|
assign WILL_FIRE_dm_ndm_reset_req_get_get = EN_dm_ndm_reset_req_get_get ;
|
|
|
|
// submodule cpu_halt
|
|
MakeResetA #(.RSTDELAY(32'd50), .init(1'd0)) cpu_halt(.CLK(CLK),
|
|
.RST(RST_N),
|
|
.DST_CLK(CLK),
|
|
.ASSERT_IN(cpu_halt$ASSERT_IN),
|
|
.ASSERT_OUT(cpu_halt$ASSERT_OUT),
|
|
.OUT_RST(cpu_halt$OUT_RST));
|
|
|
|
// submodule cpu_reset
|
|
MakeResetA #(.RSTDELAY(32'd50), .init(1'd0)) cpu_reset(.CLK(CLK),
|
|
.RST(RST_N),
|
|
.DST_CLK(CLK),
|
|
.ASSERT_IN(cpu_reset$ASSERT_IN),
|
|
.ASSERT_OUT(cpu_reset$ASSERT_OUT),
|
|
.OUT_RST(cpu_reset$OUT_RST));
|
|
|
|
// submodule cpu_reset_either
|
|
ResetEither cpu_reset_either(.A_RST(cpu_reset$OUT_RST),
|
|
.B_RST(cpu_halt$OUT_RST),
|
|
.RST_OUT(cpu_reset_either$RST_OUT));
|
|
|
|
// submodule debug_module
|
|
mkDebug_Module debug_module(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.dmi_read_addr_dm_addr(debug_module$dmi_read_addr_dm_addr),
|
|
.dmi_write_dm_addr(debug_module$dmi_write_dm_addr),
|
|
.dmi_write_dm_word(debug_module$dmi_write_dm_word),
|
|
.hart0_client_run_halt_response_put(debug_module$hart0_client_run_halt_response_put),
|
|
.hart0_csr_mem_client_response_put(debug_module$hart0_csr_mem_client_response_put),
|
|
.hart0_fpr_mem_client_response_put(debug_module$hart0_fpr_mem_client_response_put),
|
|
.hart0_gpr_mem_client_response_put(debug_module$hart0_gpr_mem_client_response_put),
|
|
.master_arready(debug_module$master_arready),
|
|
.master_awready(debug_module$master_awready),
|
|
.master_bid(debug_module$master_bid),
|
|
.master_bresp(debug_module$master_bresp),
|
|
.master_bvalid(debug_module$master_bvalid),
|
|
.master_rdata(debug_module$master_rdata),
|
|
.master_rid(debug_module$master_rid),
|
|
.master_rlast(debug_module$master_rlast),
|
|
.master_rresp(debug_module$master_rresp),
|
|
.master_rvalid(debug_module$master_rvalid),
|
|
.master_wready(debug_module$master_wready),
|
|
.EN_dmi_read_addr(debug_module$EN_dmi_read_addr),
|
|
.EN_dmi_read_data(debug_module$EN_dmi_read_data),
|
|
.EN_dmi_write(debug_module$EN_dmi_write),
|
|
.EN_hart0_get_reset_req_get(debug_module$EN_hart0_get_reset_req_get),
|
|
.EN_hart0_client_run_halt_request_get(debug_module$EN_hart0_client_run_halt_request_get),
|
|
.EN_hart0_client_run_halt_response_put(debug_module$EN_hart0_client_run_halt_response_put),
|
|
.EN_hart0_get_other_req_get(debug_module$EN_hart0_get_other_req_get),
|
|
.EN_hart0_gpr_mem_client_request_get(debug_module$EN_hart0_gpr_mem_client_request_get),
|
|
.EN_hart0_gpr_mem_client_response_put(debug_module$EN_hart0_gpr_mem_client_response_put),
|
|
.EN_hart0_fpr_mem_client_request_get(debug_module$EN_hart0_fpr_mem_client_request_get),
|
|
.EN_hart0_fpr_mem_client_response_put(debug_module$EN_hart0_fpr_mem_client_response_put),
|
|
.EN_hart0_csr_mem_client_request_get(debug_module$EN_hart0_csr_mem_client_request_get),
|
|
.EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put),
|
|
.EN_get_ndm_reset_req_get(debug_module$EN_get_ndm_reset_req_get),
|
|
.RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr),
|
|
.dmi_read_data(debug_module$dmi_read_data),
|
|
.RDY_dmi_read_data(debug_module$RDY_dmi_read_data),
|
|
.RDY_dmi_write(debug_module$RDY_dmi_write),
|
|
.RDY_hart0_get_reset_req_get(debug_module$RDY_hart0_get_reset_req_get),
|
|
.hart0_client_run_halt_request_get(debug_module$hart0_client_run_halt_request_get),
|
|
.RDY_hart0_client_run_halt_request_get(debug_module$RDY_hart0_client_run_halt_request_get),
|
|
.RDY_hart0_client_run_halt_response_put(debug_module$RDY_hart0_client_run_halt_response_put),
|
|
.hart0_get_other_req_get(),
|
|
.RDY_hart0_get_other_req_get(),
|
|
.hart0_gpr_mem_client_request_get(),
|
|
.RDY_hart0_gpr_mem_client_request_get(debug_module$RDY_hart0_gpr_mem_client_request_get),
|
|
.RDY_hart0_gpr_mem_client_response_put(debug_module$RDY_hart0_gpr_mem_client_response_put),
|
|
.hart0_fpr_mem_client_request_get(),
|
|
.RDY_hart0_fpr_mem_client_request_get(debug_module$RDY_hart0_fpr_mem_client_request_get),
|
|
.RDY_hart0_fpr_mem_client_response_put(debug_module$RDY_hart0_fpr_mem_client_response_put),
|
|
.hart0_csr_mem_client_request_get(),
|
|
.RDY_hart0_csr_mem_client_request_get(debug_module$RDY_hart0_csr_mem_client_request_get),
|
|
.RDY_hart0_csr_mem_client_response_put(debug_module$RDY_hart0_csr_mem_client_response_put),
|
|
.RDY_get_ndm_reset_req_get(debug_module$RDY_get_ndm_reset_req_get),
|
|
.master_awvalid(debug_module$master_awvalid),
|
|
.master_awid(debug_module$master_awid),
|
|
.master_awaddr(debug_module$master_awaddr),
|
|
.master_awlen(debug_module$master_awlen),
|
|
.master_awsize(debug_module$master_awsize),
|
|
.master_awburst(debug_module$master_awburst),
|
|
.master_awlock(debug_module$master_awlock),
|
|
.master_awcache(debug_module$master_awcache),
|
|
.master_awprot(debug_module$master_awprot),
|
|
.master_awqos(debug_module$master_awqos),
|
|
.master_awregion(debug_module$master_awregion),
|
|
.master_wvalid(debug_module$master_wvalid),
|
|
.master_wid(debug_module$master_wid),
|
|
.master_wdata(debug_module$master_wdata),
|
|
.master_wstrb(debug_module$master_wstrb),
|
|
.master_wlast(debug_module$master_wlast),
|
|
.master_bready(debug_module$master_bready),
|
|
.master_arvalid(debug_module$master_arvalid),
|
|
.master_arid(debug_module$master_arid),
|
|
.master_araddr(debug_module$master_araddr),
|
|
.master_arlen(debug_module$master_arlen),
|
|
.master_arsize(debug_module$master_arsize),
|
|
.master_arburst(debug_module$master_arburst),
|
|
.master_arlock(debug_module$master_arlock),
|
|
.master_arcache(debug_module$master_arcache),
|
|
.master_arprot(debug_module$master_arprot),
|
|
.master_arqos(debug_module$master_arqos),
|
|
.master_arregion(debug_module$master_arregion),
|
|
.master_rready(debug_module$master_rready));
|
|
|
|
// submodule dm_mem_tap
|
|
mkDM_Mem_Tap dm_mem_tap(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.master_arready(dm_mem_tap$master_arready),
|
|
.master_awready(dm_mem_tap$master_awready),
|
|
.master_bid(dm_mem_tap$master_bid),
|
|
.master_bresp(dm_mem_tap$master_bresp),
|
|
.master_bvalid(dm_mem_tap$master_bvalid),
|
|
.master_rdata(dm_mem_tap$master_rdata),
|
|
.master_rid(dm_mem_tap$master_rid),
|
|
.master_rlast(dm_mem_tap$master_rlast),
|
|
.master_rresp(dm_mem_tap$master_rresp),
|
|
.master_rvalid(dm_mem_tap$master_rvalid),
|
|
.master_wready(dm_mem_tap$master_wready),
|
|
.slave_araddr(dm_mem_tap$slave_araddr),
|
|
.slave_arburst(dm_mem_tap$slave_arburst),
|
|
.slave_arcache(dm_mem_tap$slave_arcache),
|
|
.slave_arid(dm_mem_tap$slave_arid),
|
|
.slave_arlen(dm_mem_tap$slave_arlen),
|
|
.slave_arlock(dm_mem_tap$slave_arlock),
|
|
.slave_arprot(dm_mem_tap$slave_arprot),
|
|
.slave_arqos(dm_mem_tap$slave_arqos),
|
|
.slave_arregion(dm_mem_tap$slave_arregion),
|
|
.slave_arsize(dm_mem_tap$slave_arsize),
|
|
.slave_arvalid(dm_mem_tap$slave_arvalid),
|
|
.slave_awaddr(dm_mem_tap$slave_awaddr),
|
|
.slave_awburst(dm_mem_tap$slave_awburst),
|
|
.slave_awcache(dm_mem_tap$slave_awcache),
|
|
.slave_awid(dm_mem_tap$slave_awid),
|
|
.slave_awlen(dm_mem_tap$slave_awlen),
|
|
.slave_awlock(dm_mem_tap$slave_awlock),
|
|
.slave_awprot(dm_mem_tap$slave_awprot),
|
|
.slave_awqos(dm_mem_tap$slave_awqos),
|
|
.slave_awregion(dm_mem_tap$slave_awregion),
|
|
.slave_awsize(dm_mem_tap$slave_awsize),
|
|
.slave_awvalid(dm_mem_tap$slave_awvalid),
|
|
.slave_bready(dm_mem_tap$slave_bready),
|
|
.slave_rready(dm_mem_tap$slave_rready),
|
|
.slave_wdata(dm_mem_tap$slave_wdata),
|
|
.slave_wid(dm_mem_tap$slave_wid),
|
|
.slave_wlast(dm_mem_tap$slave_wlast),
|
|
.slave_wstrb(dm_mem_tap$slave_wstrb),
|
|
.slave_wvalid(dm_mem_tap$slave_wvalid),
|
|
.EN_trace_data_out_get(dm_mem_tap$EN_trace_data_out_get),
|
|
.slave_awready(dm_mem_tap$slave_awready),
|
|
.slave_wready(dm_mem_tap$slave_wready),
|
|
.slave_bvalid(dm_mem_tap$slave_bvalid),
|
|
.slave_bid(dm_mem_tap$slave_bid),
|
|
.slave_bresp(dm_mem_tap$slave_bresp),
|
|
.slave_arready(dm_mem_tap$slave_arready),
|
|
.slave_rvalid(dm_mem_tap$slave_rvalid),
|
|
.slave_rid(dm_mem_tap$slave_rid),
|
|
.slave_rdata(dm_mem_tap$slave_rdata),
|
|
.slave_rresp(dm_mem_tap$slave_rresp),
|
|
.slave_rlast(dm_mem_tap$slave_rlast),
|
|
.master_awvalid(dm_mem_tap$master_awvalid),
|
|
.master_awid(dm_mem_tap$master_awid),
|
|
.master_awaddr(dm_mem_tap$master_awaddr),
|
|
.master_awlen(dm_mem_tap$master_awlen),
|
|
.master_awsize(dm_mem_tap$master_awsize),
|
|
.master_awburst(dm_mem_tap$master_awburst),
|
|
.master_awlock(dm_mem_tap$master_awlock),
|
|
.master_awcache(dm_mem_tap$master_awcache),
|
|
.master_awprot(dm_mem_tap$master_awprot),
|
|
.master_awqos(dm_mem_tap$master_awqos),
|
|
.master_awregion(dm_mem_tap$master_awregion),
|
|
.master_wvalid(dm_mem_tap$master_wvalid),
|
|
.master_wid(dm_mem_tap$master_wid),
|
|
.master_wdata(dm_mem_tap$master_wdata),
|
|
.master_wstrb(dm_mem_tap$master_wstrb),
|
|
.master_wlast(dm_mem_tap$master_wlast),
|
|
.master_bready(dm_mem_tap$master_bready),
|
|
.master_arvalid(dm_mem_tap$master_arvalid),
|
|
.master_arid(dm_mem_tap$master_arid),
|
|
.master_araddr(dm_mem_tap$master_araddr),
|
|
.master_arlen(dm_mem_tap$master_arlen),
|
|
.master_arsize(dm_mem_tap$master_arsize),
|
|
.master_arburst(dm_mem_tap$master_arburst),
|
|
.master_arlock(dm_mem_tap$master_arlock),
|
|
.master_arcache(dm_mem_tap$master_arcache),
|
|
.master_arprot(dm_mem_tap$master_arprot),
|
|
.master_arqos(dm_mem_tap$master_arqos),
|
|
.master_arregion(dm_mem_tap$master_arregion),
|
|
.master_rready(dm_mem_tap$master_rready),
|
|
.trace_data_out_get(dm_mem_tap$trace_data_out_get),
|
|
.RDY_trace_data_out_get(dm_mem_tap$RDY_trace_data_out_get));
|
|
|
|
// submodule f_reset_reqs
|
|
FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.ENQ(f_reset_reqs$ENQ),
|
|
.DEQ(f_reset_reqs$DEQ),
|
|
.CLR(f_reset_reqs$CLR),
|
|
.FULL_N(f_reset_reqs$FULL_N),
|
|
.EMPTY_N(f_reset_reqs$EMPTY_N));
|
|
|
|
// submodule f_reset_requestor
|
|
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_requestor(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(f_reset_requestor$D_IN),
|
|
.ENQ(f_reset_requestor$ENQ),
|
|
.DEQ(f_reset_requestor$DEQ),
|
|
.CLR(f_reset_requestor$CLR),
|
|
.D_OUT(f_reset_requestor$D_OUT),
|
|
.FULL_N(f_reset_requestor$FULL_N),
|
|
.EMPTY_N(f_reset_requestor$EMPTY_N));
|
|
|
|
// submodule f_reset_rsps
|
|
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.ENQ(f_reset_rsps$ENQ),
|
|
.DEQ(f_reset_rsps$DEQ),
|
|
.CLR(f_reset_rsps$CLR),
|
|
.FULL_N(f_reset_rsps$FULL_N),
|
|
.EMPTY_N(f_reset_rsps$EMPTY_N));
|
|
|
|
// submodule f_trace_data_merged
|
|
FIFO2 #(.width(32'd362), .guarded(32'd1)) f_trace_data_merged(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(f_trace_data_merged$D_IN),
|
|
.ENQ(f_trace_data_merged$ENQ),
|
|
.DEQ(f_trace_data_merged$DEQ),
|
|
.CLR(f_trace_data_merged$CLR),
|
|
.D_OUT(f_trace_data_merged$D_OUT),
|
|
.FULL_N(f_trace_data_merged$FULL_N),
|
|
.EMPTY_N(f_trace_data_merged$EMPTY_N));
|
|
|
|
// submodule fabric_2x3
|
|
mkFabric_2x3 fabric_2x3(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity),
|
|
.v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr),
|
|
.v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst),
|
|
.v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache),
|
|
.v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid),
|
|
.v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen),
|
|
.v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock),
|
|
.v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot),
|
|
.v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos),
|
|
.v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion),
|
|
.v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize),
|
|
.v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid),
|
|
.v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr),
|
|
.v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst),
|
|
.v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache),
|
|
.v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid),
|
|
.v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen),
|
|
.v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock),
|
|
.v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot),
|
|
.v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos),
|
|
.v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion),
|
|
.v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize),
|
|
.v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid),
|
|
.v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready),
|
|
.v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready),
|
|
.v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata),
|
|
.v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid),
|
|
.v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast),
|
|
.v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb),
|
|
.v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid),
|
|
.v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr),
|
|
.v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst),
|
|
.v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache),
|
|
.v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid),
|
|
.v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen),
|
|
.v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock),
|
|
.v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot),
|
|
.v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos),
|
|
.v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion),
|
|
.v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize),
|
|
.v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid),
|
|
.v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr),
|
|
.v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst),
|
|
.v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache),
|
|
.v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid),
|
|
.v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen),
|
|
.v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock),
|
|
.v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot),
|
|
.v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos),
|
|
.v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion),
|
|
.v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize),
|
|
.v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid),
|
|
.v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready),
|
|
.v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready),
|
|
.v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata),
|
|
.v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid),
|
|
.v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast),
|
|
.v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb),
|
|
.v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid),
|
|
.v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready),
|
|
.v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready),
|
|
.v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid),
|
|
.v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp),
|
|
.v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid),
|
|
.v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata),
|
|
.v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid),
|
|
.v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast),
|
|
.v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp),
|
|
.v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid),
|
|
.v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready),
|
|
.v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready),
|
|
.v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready),
|
|
.v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid),
|
|
.v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp),
|
|
.v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid),
|
|
.v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata),
|
|
.v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid),
|
|
.v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast),
|
|
.v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp),
|
|
.v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid),
|
|
.v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready),
|
|
.v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready),
|
|
.v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready),
|
|
.v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid),
|
|
.v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp),
|
|
.v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid),
|
|
.v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata),
|
|
.v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid),
|
|
.v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast),
|
|
.v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp),
|
|
.v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid),
|
|
.v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready),
|
|
.EN_reset(fabric_2x3$EN_reset),
|
|
.EN_set_verbosity(fabric_2x3$EN_set_verbosity),
|
|
.RDY_reset(fabric_2x3$RDY_reset),
|
|
.RDY_set_verbosity(),
|
|
.v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready),
|
|
.v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready),
|
|
.v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid),
|
|
.v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid),
|
|
.v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp),
|
|
.v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready),
|
|
.v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid),
|
|
.v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid),
|
|
.v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata),
|
|
.v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp),
|
|
.v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast),
|
|
.v_from_masters_1_awready(fabric_2x3$v_from_masters_1_awready),
|
|
.v_from_masters_1_wready(fabric_2x3$v_from_masters_1_wready),
|
|
.v_from_masters_1_bvalid(fabric_2x3$v_from_masters_1_bvalid),
|
|
.v_from_masters_1_bid(fabric_2x3$v_from_masters_1_bid),
|
|
.v_from_masters_1_bresp(fabric_2x3$v_from_masters_1_bresp),
|
|
.v_from_masters_1_arready(fabric_2x3$v_from_masters_1_arready),
|
|
.v_from_masters_1_rvalid(fabric_2x3$v_from_masters_1_rvalid),
|
|
.v_from_masters_1_rid(fabric_2x3$v_from_masters_1_rid),
|
|
.v_from_masters_1_rdata(fabric_2x3$v_from_masters_1_rdata),
|
|
.v_from_masters_1_rresp(fabric_2x3$v_from_masters_1_rresp),
|
|
.v_from_masters_1_rlast(fabric_2x3$v_from_masters_1_rlast),
|
|
.v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid),
|
|
.v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid),
|
|
.v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr),
|
|
.v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen),
|
|
.v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize),
|
|
.v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst),
|
|
.v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock),
|
|
.v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache),
|
|
.v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot),
|
|
.v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos),
|
|
.v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion),
|
|
.v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid),
|
|
.v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid),
|
|
.v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata),
|
|
.v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb),
|
|
.v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast),
|
|
.v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready),
|
|
.v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid),
|
|
.v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid),
|
|
.v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr),
|
|
.v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen),
|
|
.v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize),
|
|
.v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst),
|
|
.v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock),
|
|
.v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache),
|
|
.v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot),
|
|
.v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos),
|
|
.v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion),
|
|
.v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready),
|
|
.v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid),
|
|
.v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid),
|
|
.v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr),
|
|
.v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen),
|
|
.v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize),
|
|
.v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst),
|
|
.v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock),
|
|
.v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache),
|
|
.v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot),
|
|
.v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos),
|
|
.v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion),
|
|
.v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid),
|
|
.v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid),
|
|
.v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata),
|
|
.v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb),
|
|
.v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast),
|
|
.v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready),
|
|
.v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid),
|
|
.v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid),
|
|
.v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr),
|
|
.v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen),
|
|
.v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize),
|
|
.v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst),
|
|
.v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock),
|
|
.v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache),
|
|
.v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot),
|
|
.v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos),
|
|
.v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion),
|
|
.v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready),
|
|
.v_to_slaves_2_awvalid(),
|
|
.v_to_slaves_2_awid(),
|
|
.v_to_slaves_2_awaddr(),
|
|
.v_to_slaves_2_awlen(),
|
|
.v_to_slaves_2_awsize(),
|
|
.v_to_slaves_2_awburst(),
|
|
.v_to_slaves_2_awlock(),
|
|
.v_to_slaves_2_awcache(),
|
|
.v_to_slaves_2_awprot(),
|
|
.v_to_slaves_2_awqos(),
|
|
.v_to_slaves_2_awregion(),
|
|
.v_to_slaves_2_wvalid(),
|
|
.v_to_slaves_2_wid(),
|
|
.v_to_slaves_2_wdata(),
|
|
.v_to_slaves_2_wstrb(),
|
|
.v_to_slaves_2_wlast(),
|
|
.v_to_slaves_2_bready(),
|
|
.v_to_slaves_2_arvalid(),
|
|
.v_to_slaves_2_arid(),
|
|
.v_to_slaves_2_araddr(),
|
|
.v_to_slaves_2_arlen(),
|
|
.v_to_slaves_2_arsize(),
|
|
.v_to_slaves_2_arburst(),
|
|
.v_to_slaves_2_arlock(),
|
|
.v_to_slaves_2_arcache(),
|
|
.v_to_slaves_2_arprot(),
|
|
.v_to_slaves_2_arqos(),
|
|
.v_to_slaves_2_arregion(),
|
|
.v_to_slaves_2_rready());
|
|
|
|
// submodule plic
|
|
mkPLIC_16_2_7 plic(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.axi4_slave_araddr(plic$axi4_slave_araddr),
|
|
.axi4_slave_arburst(plic$axi4_slave_arburst),
|
|
.axi4_slave_arcache(plic$axi4_slave_arcache),
|
|
.axi4_slave_arid(plic$axi4_slave_arid),
|
|
.axi4_slave_arlen(plic$axi4_slave_arlen),
|
|
.axi4_slave_arlock(plic$axi4_slave_arlock),
|
|
.axi4_slave_arprot(plic$axi4_slave_arprot),
|
|
.axi4_slave_arqos(plic$axi4_slave_arqos),
|
|
.axi4_slave_arregion(plic$axi4_slave_arregion),
|
|
.axi4_slave_arsize(plic$axi4_slave_arsize),
|
|
.axi4_slave_arvalid(plic$axi4_slave_arvalid),
|
|
.axi4_slave_awaddr(plic$axi4_slave_awaddr),
|
|
.axi4_slave_awburst(plic$axi4_slave_awburst),
|
|
.axi4_slave_awcache(plic$axi4_slave_awcache),
|
|
.axi4_slave_awid(plic$axi4_slave_awid),
|
|
.axi4_slave_awlen(plic$axi4_slave_awlen),
|
|
.axi4_slave_awlock(plic$axi4_slave_awlock),
|
|
.axi4_slave_awprot(plic$axi4_slave_awprot),
|
|
.axi4_slave_awqos(plic$axi4_slave_awqos),
|
|
.axi4_slave_awregion(plic$axi4_slave_awregion),
|
|
.axi4_slave_awsize(plic$axi4_slave_awsize),
|
|
.axi4_slave_awvalid(plic$axi4_slave_awvalid),
|
|
.axi4_slave_bready(plic$axi4_slave_bready),
|
|
.axi4_slave_rready(plic$axi4_slave_rready),
|
|
.axi4_slave_wdata(plic$axi4_slave_wdata),
|
|
.axi4_slave_wid(plic$axi4_slave_wid),
|
|
.axi4_slave_wlast(plic$axi4_slave_wlast),
|
|
.axi4_slave_wstrb(plic$axi4_slave_wstrb),
|
|
.axi4_slave_wvalid(plic$axi4_slave_wvalid),
|
|
.set_addr_map_addr_base(plic$set_addr_map_addr_base),
|
|
.set_addr_map_addr_lim(plic$set_addr_map_addr_lim),
|
|
.set_verbosity_verbosity(plic$set_verbosity_verbosity),
|
|
.v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear),
|
|
.v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear),
|
|
.v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear),
|
|
.v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear),
|
|
.v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear),
|
|
.v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear),
|
|
.v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear),
|
|
.v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear),
|
|
.v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear),
|
|
.v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear),
|
|
.v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear),
|
|
.v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear),
|
|
.v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear),
|
|
.v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear),
|
|
.v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear),
|
|
.v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear),
|
|
.EN_set_verbosity(plic$EN_set_verbosity),
|
|
.EN_show_PLIC_state(plic$EN_show_PLIC_state),
|
|
.EN_server_reset_request_put(plic$EN_server_reset_request_put),
|
|
.EN_server_reset_response_get(plic$EN_server_reset_response_get),
|
|
.EN_set_addr_map(plic$EN_set_addr_map),
|
|
.RDY_set_verbosity(),
|
|
.RDY_show_PLIC_state(),
|
|
.RDY_server_reset_request_put(plic$RDY_server_reset_request_put),
|
|
.RDY_server_reset_response_get(plic$RDY_server_reset_response_get),
|
|
.RDY_set_addr_map(),
|
|
.axi4_slave_awready(plic$axi4_slave_awready),
|
|
.axi4_slave_wready(plic$axi4_slave_wready),
|
|
.axi4_slave_bvalid(plic$axi4_slave_bvalid),
|
|
.axi4_slave_bid(plic$axi4_slave_bid),
|
|
.axi4_slave_bresp(plic$axi4_slave_bresp),
|
|
.axi4_slave_arready(plic$axi4_slave_arready),
|
|
.axi4_slave_rvalid(plic$axi4_slave_rvalid),
|
|
.axi4_slave_rid(plic$axi4_slave_rid),
|
|
.axi4_slave_rdata(plic$axi4_slave_rdata),
|
|
.axi4_slave_rresp(plic$axi4_slave_rresp),
|
|
.axi4_slave_rlast(plic$axi4_slave_rlast),
|
|
.v_targets_0_m_eip(plic$v_targets_0_m_eip),
|
|
.v_targets_1_m_eip(plic$v_targets_1_m_eip));
|
|
|
|
// submodule proc
|
|
mkProc proc(.CLK(CLK),
|
|
.RST_N(cpu_reset_either$RST_OUT),
|
|
.debug_external_interrupt_req_set_not_clear(proc$debug_external_interrupt_req_set_not_clear),
|
|
.hart0_csr_mem_server_request_put(proc$hart0_csr_mem_server_request_put),
|
|
.hart0_fpr_mem_server_request_put(proc$hart0_fpr_mem_server_request_put),
|
|
.hart0_gpr_mem_server_request_put(proc$hart0_gpr_mem_server_request_put),
|
|
.hart0_put_other_req_put(proc$hart0_put_other_req_put),
|
|
.hart0_server_run_halt_request_put(proc$hart0_server_run_halt_request_put),
|
|
.m_external_interrupt_req_set_not_clear(proc$m_external_interrupt_req_set_not_clear),
|
|
.master0_arready(proc$master0_arready),
|
|
.master0_awready(proc$master0_awready),
|
|
.master0_bid(proc$master0_bid),
|
|
.master0_bresp(proc$master0_bresp),
|
|
.master0_bvalid(proc$master0_bvalid),
|
|
.master0_rdata(proc$master0_rdata),
|
|
.master0_rid(proc$master0_rid),
|
|
.master0_rlast(proc$master0_rlast),
|
|
.master0_rresp(proc$master0_rresp),
|
|
.master0_rvalid(proc$master0_rvalid),
|
|
.master0_wready(proc$master0_wready),
|
|
.master1_arready(proc$master1_arready),
|
|
.master1_awready(proc$master1_awready),
|
|
.master1_bid(proc$master1_bid),
|
|
.master1_bresp(proc$master1_bresp),
|
|
.master1_bvalid(proc$master1_bvalid),
|
|
.master1_rdata(proc$master1_rdata),
|
|
.master1_rid(proc$master1_rid),
|
|
.master1_rlast(proc$master1_rlast),
|
|
.master1_rresp(proc$master1_rresp),
|
|
.master1_rvalid(proc$master1_rvalid),
|
|
.master1_wready(proc$master1_wready),
|
|
.non_maskable_interrupt_req_set_not_clear(proc$non_maskable_interrupt_req_set_not_clear),
|
|
.s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear),
|
|
.set_verbosity_verbosity(proc$set_verbosity_verbosity),
|
|
.start_fromhostAddr(proc$start_fromhostAddr),
|
|
.start_startpc(proc$start_startpc),
|
|
.start_tohostAddr(proc$start_tohostAddr),
|
|
.EN_hart0_server_reset_request_put(proc$EN_hart0_server_reset_request_put),
|
|
.EN_hart0_server_reset_response_get(proc$EN_hart0_server_reset_response_get),
|
|
.EN_start(proc$EN_start),
|
|
.EN_set_verbosity(proc$EN_set_verbosity),
|
|
.EN_trace_data_out_get(proc$EN_trace_data_out_get),
|
|
.EN_hart0_server_run_halt_request_put(proc$EN_hart0_server_run_halt_request_put),
|
|
.EN_hart0_server_run_halt_response_get(proc$EN_hart0_server_run_halt_response_get),
|
|
.EN_hart0_put_other_req_put(proc$EN_hart0_put_other_req_put),
|
|
.EN_hart0_gpr_mem_server_request_put(proc$EN_hart0_gpr_mem_server_request_put),
|
|
.EN_hart0_gpr_mem_server_response_get(proc$EN_hart0_gpr_mem_server_response_get),
|
|
.EN_hart0_fpr_mem_server_request_put(proc$EN_hart0_fpr_mem_server_request_put),
|
|
.EN_hart0_fpr_mem_server_response_get(proc$EN_hart0_fpr_mem_server_response_get),
|
|
.EN_hart0_csr_mem_server_request_put(proc$EN_hart0_csr_mem_server_request_put),
|
|
.EN_hart0_csr_mem_server_response_get(proc$EN_hart0_csr_mem_server_response_get),
|
|
.RDY_hart0_server_reset_request_put(proc$RDY_hart0_server_reset_request_put),
|
|
.RDY_hart0_server_reset_response_get(proc$RDY_hart0_server_reset_response_get),
|
|
.RDY_start(proc$RDY_start),
|
|
.master0_awvalid(proc$master0_awvalid),
|
|
.master0_awid(proc$master0_awid),
|
|
.master0_awaddr(proc$master0_awaddr),
|
|
.master0_awlen(proc$master0_awlen),
|
|
.master0_awsize(proc$master0_awsize),
|
|
.master0_awburst(proc$master0_awburst),
|
|
.master0_awlock(proc$master0_awlock),
|
|
.master0_awcache(proc$master0_awcache),
|
|
.master0_awprot(proc$master0_awprot),
|
|
.master0_awqos(proc$master0_awqos),
|
|
.master0_awregion(proc$master0_awregion),
|
|
.master0_wvalid(proc$master0_wvalid),
|
|
.master0_wid(proc$master0_wid),
|
|
.master0_wdata(proc$master0_wdata),
|
|
.master0_wstrb(proc$master0_wstrb),
|
|
.master0_wlast(proc$master0_wlast),
|
|
.master0_bready(proc$master0_bready),
|
|
.master0_arvalid(proc$master0_arvalid),
|
|
.master0_arid(proc$master0_arid),
|
|
.master0_araddr(proc$master0_araddr),
|
|
.master0_arlen(proc$master0_arlen),
|
|
.master0_arsize(proc$master0_arsize),
|
|
.master0_arburst(proc$master0_arburst),
|
|
.master0_arlock(proc$master0_arlock),
|
|
.master0_arcache(proc$master0_arcache),
|
|
.master0_arprot(proc$master0_arprot),
|
|
.master0_arqos(proc$master0_arqos),
|
|
.master0_arregion(proc$master0_arregion),
|
|
.master0_rready(proc$master0_rready),
|
|
.master1_awvalid(proc$master1_awvalid),
|
|
.master1_awid(proc$master1_awid),
|
|
.master1_awaddr(proc$master1_awaddr),
|
|
.master1_awlen(proc$master1_awlen),
|
|
.master1_awsize(proc$master1_awsize),
|
|
.master1_awburst(proc$master1_awburst),
|
|
.master1_awlock(proc$master1_awlock),
|
|
.master1_awcache(proc$master1_awcache),
|
|
.master1_awprot(proc$master1_awprot),
|
|
.master1_awqos(proc$master1_awqos),
|
|
.master1_awregion(proc$master1_awregion),
|
|
.master1_wvalid(proc$master1_wvalid),
|
|
.master1_wid(proc$master1_wid),
|
|
.master1_wdata(proc$master1_wdata),
|
|
.master1_wstrb(proc$master1_wstrb),
|
|
.master1_wlast(proc$master1_wlast),
|
|
.master1_bready(proc$master1_bready),
|
|
.master1_arvalid(proc$master1_arvalid),
|
|
.master1_arid(proc$master1_arid),
|
|
.master1_araddr(proc$master1_araddr),
|
|
.master1_arlen(proc$master1_arlen),
|
|
.master1_arsize(proc$master1_arsize),
|
|
.master1_arburst(proc$master1_arburst),
|
|
.master1_arlock(proc$master1_arlock),
|
|
.master1_arcache(proc$master1_arcache),
|
|
.master1_arprot(proc$master1_arprot),
|
|
.master1_arqos(proc$master1_arqos),
|
|
.master1_arregion(proc$master1_arregion),
|
|
.master1_rready(proc$master1_rready),
|
|
.RDY_set_verbosity(),
|
|
.trace_data_out_get(proc$trace_data_out_get),
|
|
.RDY_trace_data_out_get(proc$RDY_trace_data_out_get),
|
|
.RDY_hart0_server_run_halt_request_put(),
|
|
.hart0_server_run_halt_response_get(),
|
|
.RDY_hart0_server_run_halt_response_get(),
|
|
.RDY_hart0_put_other_req_put(),
|
|
.RDY_hart0_gpr_mem_server_request_put(),
|
|
.hart0_gpr_mem_server_response_get(),
|
|
.RDY_hart0_gpr_mem_server_response_get(),
|
|
.RDY_hart0_fpr_mem_server_request_put(),
|
|
.hart0_fpr_mem_server_response_get(),
|
|
.RDY_hart0_fpr_mem_server_response_get(),
|
|
.RDY_hart0_csr_mem_server_request_put(),
|
|
.hart0_csr_mem_server_response_get(),
|
|
.RDY_hart0_csr_mem_server_response_get());
|
|
|
|
// submodule soc_map
|
|
mkSoC_Map soc_map(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
|
|
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
|
|
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
|
|
.m_plic_addr_base(soc_map$m_plic_addr_base),
|
|
.m_plic_addr_size(),
|
|
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
|
|
.m_near_mem_io_addr_base(),
|
|
.m_near_mem_io_addr_size(),
|
|
.m_near_mem_io_addr_lim(),
|
|
.m_flash_mem_addr_base(),
|
|
.m_flash_mem_addr_size(),
|
|
.m_flash_mem_addr_lim(),
|
|
.m_ethernet_0_addr_base(),
|
|
.m_ethernet_0_addr_size(),
|
|
.m_ethernet_0_addr_lim(),
|
|
.m_dma_0_addr_base(),
|
|
.m_dma_0_addr_size(),
|
|
.m_dma_0_addr_lim(),
|
|
.m_uart16550_0_addr_base(),
|
|
.m_uart16550_0_addr_size(),
|
|
.m_uart16550_0_addr_lim(),
|
|
.m_gpio_0_addr_base(),
|
|
.m_gpio_0_addr_size(),
|
|
.m_gpio_0_addr_lim(),
|
|
.m_boot_rom_addr_base(),
|
|
.m_boot_rom_addr_size(),
|
|
.m_boot_rom_addr_lim(),
|
|
.m_ddr4_0_uncached_addr_base(),
|
|
.m_ddr4_0_uncached_addr_size(),
|
|
.m_ddr4_0_uncached_addr_lim(),
|
|
.m_ddr4_0_cached_addr_base(),
|
|
.m_ddr4_0_cached_addr_size(),
|
|
.m_ddr4_0_cached_addr_lim(),
|
|
.m_is_mem_addr(),
|
|
.m_is_IO_addr(),
|
|
.m_is_near_mem_IO_addr(),
|
|
.m_pc_reset_value(),
|
|
.m_mtvec_reset_value(),
|
|
.m_nmivec_reset_value());
|
|
|
|
// submodule tv_encode
|
|
mkTV_Encode tv_encode(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.trace_data_in_put(tv_encode$trace_data_in_put),
|
|
.EN_reset(tv_encode$EN_reset),
|
|
.EN_trace_data_in_put(tv_encode$EN_trace_data_in_put),
|
|
.EN_tv_vb_out_get(tv_encode$EN_tv_vb_out_get),
|
|
.RDY_reset(),
|
|
.RDY_trace_data_in_put(tv_encode$RDY_trace_data_in_put),
|
|
.tv_vb_out_get(tv_encode$tv_vb_out_get),
|
|
.RDY_tv_vb_out_get(tv_encode$RDY_tv_vb_out_get));
|
|
|
|
// rule RL_rl_once
|
|
assign CAN_FIRE_RL_rl_once =
|
|
proc$RDY_hart0_server_reset_request_put && !once &&
|
|
!cpu_reset$ASSERT_OUT &&
|
|
!cpu_halt$ASSERT_OUT ;
|
|
assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ;
|
|
|
|
// rule RL_rl_hart0_server_reset
|
|
assign CAN_FIRE_RL_rl_hart0_server_reset =
|
|
proc$RDY_start && proc$RDY_hart0_server_reset_response_get ;
|
|
assign WILL_FIRE_RL_rl_hart0_server_reset =
|
|
CAN_FIRE_RL_rl_hart0_server_reset ;
|
|
|
|
// rule RL_rl_hart0_server_run_halt
|
|
assign CAN_FIRE_RL_rl_hart0_server_run_halt = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_hart0_server_run_halt = 1'd1 ;
|
|
|
|
// rule RL_rl_halt_reset
|
|
assign CAN_FIRE_RL_rl_halt_reset = hart0_halt ;
|
|
assign WILL_FIRE_RL_rl_halt_reset = hart0_halt ;
|
|
|
|
// rule RL_rl_halt
|
|
assign CAN_FIRE_RL_rl_halt =
|
|
debug_module$RDY_hart0_client_run_halt_response_put &&
|
|
debug_module$RDY_hart0_client_run_halt_request_get ;
|
|
assign WILL_FIRE_RL_rl_halt = CAN_FIRE_RL_rl_halt ;
|
|
|
|
// rule RL_rl_gpr
|
|
assign CAN_FIRE_RL_rl_gpr =
|
|
debug_module$RDY_hart0_gpr_mem_client_response_put &&
|
|
debug_module$RDY_hart0_gpr_mem_client_request_get ;
|
|
assign WILL_FIRE_RL_rl_gpr = CAN_FIRE_RL_rl_gpr ;
|
|
|
|
// rule RL_rl_fpr
|
|
assign CAN_FIRE_RL_rl_fpr =
|
|
debug_module$RDY_hart0_fpr_mem_client_response_put &&
|
|
debug_module$RDY_hart0_fpr_mem_client_request_get ;
|
|
assign WILL_FIRE_RL_rl_fpr = CAN_FIRE_RL_rl_fpr ;
|
|
|
|
// rule RL_rl_csr
|
|
assign CAN_FIRE_RL_rl_csr =
|
|
debug_module$RDY_hart0_csr_mem_client_response_put &&
|
|
debug_module$RDY_hart0_csr_mem_client_request_get ;
|
|
assign WILL_FIRE_RL_rl_csr = CAN_FIRE_RL_rl_csr ;
|
|
|
|
// rule RL_rl_cpu_hart0_reset_from_dm_complete
|
|
assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete =
|
|
f_reset_requestor$EMPTY_N && !f_reset_requestor$D_OUT &&
|
|
!cpu_reset$ASSERT_OUT ;
|
|
assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete =
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete ;
|
|
|
|
// rule RL_mkConnectionGetPut
|
|
assign CAN_FIRE_RL_mkConnectionGetPut =
|
|
tv_encode$RDY_trace_data_in_put && f_trace_data_merged$EMPTY_N ;
|
|
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
|
|
|
|
// rule RL_merge_cpu_trace_data
|
|
assign CAN_FIRE_RL_merge_cpu_trace_data =
|
|
proc$RDY_trace_data_out_get && f_trace_data_merged$FULL_N ;
|
|
assign WILL_FIRE_RL_merge_cpu_trace_data =
|
|
CAN_FIRE_RL_merge_cpu_trace_data ;
|
|
|
|
// rule RL_rl_wr_addr_channel
|
|
assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_data_channel
|
|
assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_addr_channel
|
|
assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_data_channel
|
|
assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ;
|
|
|
|
// rule RL_merge_dm_mem_trace_data
|
|
assign CAN_FIRE_RL_merge_dm_mem_trace_data =
|
|
dm_mem_tap$RDY_trace_data_out_get && f_trace_data_merged$FULL_N ;
|
|
assign WILL_FIRE_RL_merge_dm_mem_trace_data =
|
|
CAN_FIRE_RL_merge_dm_mem_trace_data &&
|
|
!WILL_FIRE_RL_merge_cpu_trace_data ;
|
|
|
|
// rule RL_rl_wr_addr_channel_1
|
|
assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_data_channel_1
|
|
assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_response_channel_1
|
|
assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_addr_channel_1
|
|
assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_data_channel_1
|
|
assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_addr_channel_2
|
|
assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_data_channel_2
|
|
assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_response_channel_2
|
|
assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_addr_channel_2
|
|
assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_data_channel_2
|
|
assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_addr_channel_3
|
|
assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_data_channel_3
|
|
assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_response_channel_3
|
|
assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_addr_channel_3
|
|
assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_data_channel_3
|
|
assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_addr_channel_4
|
|
assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_data_channel_4
|
|
assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ;
|
|
|
|
// rule RL_rl_wr_response_channel_4
|
|
assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_addr_channel_4
|
|
assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ;
|
|
|
|
// rule RL_rl_rd_data_channel_4
|
|
assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ;
|
|
|
|
// rule RL_rl_relay_external_interrupts
|
|
assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
|
|
|
|
// rule RL_rl_cpu_hart0_reset_complete
|
|
assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete =
|
|
plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N &&
|
|
!cpu_reset$ASSERT_OUT ;
|
|
assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete =
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
|
|
|
|
// rule RL_rl_cpu_hart0_reset_from_soc_start
|
|
assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
|
|
plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset &&
|
|
f_reset_reqs$EMPTY_N ;
|
|
assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
|
|
|
|
// rule RL_rl_cpu_hart0_reset_from_dm_start
|
|
assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start =
|
|
debug_module$RDY_hart0_get_reset_req_get &&
|
|
f_reset_requestor$FULL_N ;
|
|
assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start =
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start &&
|
|
!WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
|
|
|
|
// rule RL_rl_wr_response_channel
|
|
assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ;
|
|
|
|
// rule RL_rl_relay_non_maskable_interrupt
|
|
assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ;
|
|
assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ;
|
|
|
|
// register hart0_halt
|
|
assign hart0_halt$D_IN = !debug_module$hart0_client_run_halt_request_get ;
|
|
assign hart0_halt$EN = CAN_FIRE_RL_rl_halt ;
|
|
|
|
// register once
|
|
assign once$D_IN = 1'd1 ;
|
|
assign once$EN = CAN_FIRE_RL_rl_once ;
|
|
|
|
// register rg_fromhost_addr
|
|
assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ;
|
|
assign rg_fromhost_addr$EN = EN_set_htif_addrs ;
|
|
|
|
// register rg_tohost_addr
|
|
assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ;
|
|
assign rg_tohost_addr$EN = EN_set_htif_addrs ;
|
|
|
|
// submodule cpu_halt
|
|
assign cpu_halt$ASSERT_IN = hart0_halt ;
|
|
|
|
// submodule cpu_reset
|
|
assign cpu_reset$ASSERT_IN =
|
|
WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ||
|
|
WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
|
|
|
|
// submodule debug_module
|
|
assign debug_module$dmi_read_addr_dm_addr = dm_dmi_read_addr_dm_addr ;
|
|
assign debug_module$dmi_write_dm_addr = dm_dmi_write_dm_addr ;
|
|
assign debug_module$dmi_write_dm_word = dm_dmi_write_dm_word ;
|
|
assign debug_module$hart0_client_run_halt_response_put =
|
|
debug_module$hart0_client_run_halt_request_get ;
|
|
assign debug_module$hart0_csr_mem_client_response_put =
|
|
65'h10000000000000000 ;
|
|
assign debug_module$hart0_fpr_mem_client_response_put =
|
|
65'h10000000000000000 ;
|
|
assign debug_module$hart0_gpr_mem_client_response_put =
|
|
65'h10000000000000000 ;
|
|
assign debug_module$master_arready = dm_mem_tap$slave_arready ;
|
|
assign debug_module$master_awready = dm_mem_tap$slave_awready ;
|
|
assign debug_module$master_bid = dm_mem_tap$slave_bid ;
|
|
assign debug_module$master_bresp = dm_mem_tap$slave_bresp ;
|
|
assign debug_module$master_bvalid = dm_mem_tap$slave_bvalid ;
|
|
assign debug_module$master_rdata = dm_mem_tap$slave_rdata ;
|
|
assign debug_module$master_rid = dm_mem_tap$slave_rid ;
|
|
assign debug_module$master_rlast = dm_mem_tap$slave_rlast ;
|
|
assign debug_module$master_rresp = dm_mem_tap$slave_rresp ;
|
|
assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ;
|
|
assign debug_module$master_wready = dm_mem_tap$slave_wready ;
|
|
assign debug_module$EN_dmi_read_addr = EN_dm_dmi_read_addr ;
|
|
assign debug_module$EN_dmi_read_data = EN_dm_dmi_read_data ;
|
|
assign debug_module$EN_dmi_write = EN_dm_dmi_write ;
|
|
assign debug_module$EN_hart0_get_reset_req_get =
|
|
WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ;
|
|
assign debug_module$EN_hart0_client_run_halt_request_get =
|
|
CAN_FIRE_RL_rl_halt ;
|
|
assign debug_module$EN_hart0_client_run_halt_response_put =
|
|
CAN_FIRE_RL_rl_halt ;
|
|
assign debug_module$EN_hart0_get_other_req_get = 1'b0 ;
|
|
assign debug_module$EN_hart0_gpr_mem_client_request_get =
|
|
CAN_FIRE_RL_rl_gpr ;
|
|
assign debug_module$EN_hart0_gpr_mem_client_response_put =
|
|
CAN_FIRE_RL_rl_gpr ;
|
|
assign debug_module$EN_hart0_fpr_mem_client_request_get =
|
|
CAN_FIRE_RL_rl_fpr ;
|
|
assign debug_module$EN_hart0_fpr_mem_client_response_put =
|
|
CAN_FIRE_RL_rl_fpr ;
|
|
assign debug_module$EN_hart0_csr_mem_client_request_get =
|
|
CAN_FIRE_RL_rl_csr ;
|
|
assign debug_module$EN_hart0_csr_mem_client_response_put =
|
|
CAN_FIRE_RL_rl_csr ;
|
|
assign debug_module$EN_get_ndm_reset_req_get = EN_dm_ndm_reset_req_get_get ;
|
|
|
|
// submodule dm_mem_tap
|
|
assign dm_mem_tap$master_arready = fabric_2x3$v_from_masters_1_arready ;
|
|
assign dm_mem_tap$master_awready = fabric_2x3$v_from_masters_1_awready ;
|
|
assign dm_mem_tap$master_bid = fabric_2x3$v_from_masters_1_bid ;
|
|
assign dm_mem_tap$master_bresp = fabric_2x3$v_from_masters_1_bresp ;
|
|
assign dm_mem_tap$master_bvalid = fabric_2x3$v_from_masters_1_bvalid ;
|
|
assign dm_mem_tap$master_rdata = fabric_2x3$v_from_masters_1_rdata ;
|
|
assign dm_mem_tap$master_rid = fabric_2x3$v_from_masters_1_rid ;
|
|
assign dm_mem_tap$master_rlast = fabric_2x3$v_from_masters_1_rlast ;
|
|
assign dm_mem_tap$master_rresp = fabric_2x3$v_from_masters_1_rresp ;
|
|
assign dm_mem_tap$master_rvalid = fabric_2x3$v_from_masters_1_rvalid ;
|
|
assign dm_mem_tap$master_wready = fabric_2x3$v_from_masters_1_wready ;
|
|
assign dm_mem_tap$slave_araddr = debug_module$master_araddr ;
|
|
assign dm_mem_tap$slave_arburst = debug_module$master_arburst ;
|
|
assign dm_mem_tap$slave_arcache = debug_module$master_arcache ;
|
|
assign dm_mem_tap$slave_arid = debug_module$master_arid ;
|
|
assign dm_mem_tap$slave_arlen = debug_module$master_arlen ;
|
|
assign dm_mem_tap$slave_arlock = debug_module$master_arlock ;
|
|
assign dm_mem_tap$slave_arprot = debug_module$master_arprot ;
|
|
assign dm_mem_tap$slave_arqos = debug_module$master_arqos ;
|
|
assign dm_mem_tap$slave_arregion = debug_module$master_arregion ;
|
|
assign dm_mem_tap$slave_arsize = debug_module$master_arsize ;
|
|
assign dm_mem_tap$slave_arvalid = debug_module$master_arvalid ;
|
|
assign dm_mem_tap$slave_awaddr = debug_module$master_awaddr ;
|
|
assign dm_mem_tap$slave_awburst = debug_module$master_awburst ;
|
|
assign dm_mem_tap$slave_awcache = debug_module$master_awcache ;
|
|
assign dm_mem_tap$slave_awid = debug_module$master_awid ;
|
|
assign dm_mem_tap$slave_awlen = debug_module$master_awlen ;
|
|
assign dm_mem_tap$slave_awlock = debug_module$master_awlock ;
|
|
assign dm_mem_tap$slave_awprot = debug_module$master_awprot ;
|
|
assign dm_mem_tap$slave_awqos = debug_module$master_awqos ;
|
|
assign dm_mem_tap$slave_awregion = debug_module$master_awregion ;
|
|
assign dm_mem_tap$slave_awsize = debug_module$master_awsize ;
|
|
assign dm_mem_tap$slave_awvalid = debug_module$master_awvalid ;
|
|
assign dm_mem_tap$slave_bready = debug_module$master_bready ;
|
|
assign dm_mem_tap$slave_rready = debug_module$master_rready ;
|
|
assign dm_mem_tap$slave_wdata = debug_module$master_wdata ;
|
|
assign dm_mem_tap$slave_wid = debug_module$master_wid ;
|
|
assign dm_mem_tap$slave_wlast = debug_module$master_wlast ;
|
|
assign dm_mem_tap$slave_wstrb = debug_module$master_wstrb ;
|
|
assign dm_mem_tap$slave_wvalid = debug_module$master_wvalid ;
|
|
assign dm_mem_tap$EN_trace_data_out_get =
|
|
WILL_FIRE_RL_merge_dm_mem_trace_data ;
|
|
|
|
// submodule f_reset_reqs
|
|
assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ;
|
|
assign f_reset_reqs$DEQ =
|
|
plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset &&
|
|
f_reset_reqs$EMPTY_N ;
|
|
assign f_reset_reqs$CLR = 1'b0 ;
|
|
|
|
// submodule f_reset_requestor
|
|
assign f_reset_requestor$D_IN = 1'd0 ;
|
|
assign f_reset_requestor$ENQ =
|
|
WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ;
|
|
assign f_reset_requestor$DEQ =
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_complete ;
|
|
assign f_reset_requestor$CLR = 1'b0 ;
|
|
|
|
// submodule f_reset_rsps
|
|
assign f_reset_rsps$ENQ =
|
|
plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N &&
|
|
!cpu_reset$ASSERT_OUT ;
|
|
assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ;
|
|
assign f_reset_rsps$CLR = 1'b0 ;
|
|
|
|
// submodule f_trace_data_merged
|
|
assign f_trace_data_merged$D_IN =
|
|
WILL_FIRE_RL_merge_cpu_trace_data ?
|
|
proc$trace_data_out_get :
|
|
dm_mem_tap$trace_data_out_get ;
|
|
assign f_trace_data_merged$ENQ =
|
|
WILL_FIRE_RL_merge_cpu_trace_data ||
|
|
WILL_FIRE_RL_merge_dm_mem_trace_data ;
|
|
assign f_trace_data_merged$DEQ = CAN_FIRE_RL_mkConnectionGetPut ;
|
|
assign f_trace_data_merged$CLR = 1'b0 ;
|
|
|
|
// submodule fabric_2x3
|
|
assign fabric_2x3$set_verbosity_verbosity = 4'h0 ;
|
|
assign fabric_2x3$v_from_masters_0_araddr = proc$master1_araddr ;
|
|
assign fabric_2x3$v_from_masters_0_arburst = proc$master1_arburst ;
|
|
assign fabric_2x3$v_from_masters_0_arcache = proc$master1_arcache ;
|
|
assign fabric_2x3$v_from_masters_0_arid = proc$master1_arid ;
|
|
assign fabric_2x3$v_from_masters_0_arlen = proc$master1_arlen ;
|
|
assign fabric_2x3$v_from_masters_0_arlock = proc$master1_arlock ;
|
|
assign fabric_2x3$v_from_masters_0_arprot = proc$master1_arprot ;
|
|
assign fabric_2x3$v_from_masters_0_arqos = proc$master1_arqos ;
|
|
assign fabric_2x3$v_from_masters_0_arregion = proc$master1_arregion ;
|
|
assign fabric_2x3$v_from_masters_0_arsize = proc$master1_arsize ;
|
|
assign fabric_2x3$v_from_masters_0_arvalid = proc$master1_arvalid ;
|
|
assign fabric_2x3$v_from_masters_0_awaddr = proc$master1_awaddr ;
|
|
assign fabric_2x3$v_from_masters_0_awburst = proc$master1_awburst ;
|
|
assign fabric_2x3$v_from_masters_0_awcache = proc$master1_awcache ;
|
|
assign fabric_2x3$v_from_masters_0_awid = proc$master1_awid ;
|
|
assign fabric_2x3$v_from_masters_0_awlen = proc$master1_awlen ;
|
|
assign fabric_2x3$v_from_masters_0_awlock = proc$master1_awlock ;
|
|
assign fabric_2x3$v_from_masters_0_awprot = proc$master1_awprot ;
|
|
assign fabric_2x3$v_from_masters_0_awqos = proc$master1_awqos ;
|
|
assign fabric_2x3$v_from_masters_0_awregion = proc$master1_awregion ;
|
|
assign fabric_2x3$v_from_masters_0_awsize = proc$master1_awsize ;
|
|
assign fabric_2x3$v_from_masters_0_awvalid = proc$master1_awvalid ;
|
|
assign fabric_2x3$v_from_masters_0_bready = proc$master1_bready ;
|
|
assign fabric_2x3$v_from_masters_0_rready = proc$master1_rready ;
|
|
assign fabric_2x3$v_from_masters_0_wdata = proc$master1_wdata ;
|
|
assign fabric_2x3$v_from_masters_0_wid = proc$master1_wid ;
|
|
assign fabric_2x3$v_from_masters_0_wlast = proc$master1_wlast ;
|
|
assign fabric_2x3$v_from_masters_0_wstrb = proc$master1_wstrb ;
|
|
assign fabric_2x3$v_from_masters_0_wvalid = proc$master1_wvalid ;
|
|
assign fabric_2x3$v_from_masters_1_araddr = dm_mem_tap$master_araddr ;
|
|
assign fabric_2x3$v_from_masters_1_arburst = dm_mem_tap$master_arburst ;
|
|
assign fabric_2x3$v_from_masters_1_arcache = dm_mem_tap$master_arcache ;
|
|
assign fabric_2x3$v_from_masters_1_arid = dm_mem_tap$master_arid ;
|
|
assign fabric_2x3$v_from_masters_1_arlen = dm_mem_tap$master_arlen ;
|
|
assign fabric_2x3$v_from_masters_1_arlock = dm_mem_tap$master_arlock ;
|
|
assign fabric_2x3$v_from_masters_1_arprot = dm_mem_tap$master_arprot ;
|
|
assign fabric_2x3$v_from_masters_1_arqos = dm_mem_tap$master_arqos ;
|
|
assign fabric_2x3$v_from_masters_1_arregion = dm_mem_tap$master_arregion ;
|
|
assign fabric_2x3$v_from_masters_1_arsize = dm_mem_tap$master_arsize ;
|
|
assign fabric_2x3$v_from_masters_1_arvalid = dm_mem_tap$master_arvalid ;
|
|
assign fabric_2x3$v_from_masters_1_awaddr = dm_mem_tap$master_awaddr ;
|
|
assign fabric_2x3$v_from_masters_1_awburst = dm_mem_tap$master_awburst ;
|
|
assign fabric_2x3$v_from_masters_1_awcache = dm_mem_tap$master_awcache ;
|
|
assign fabric_2x3$v_from_masters_1_awid = dm_mem_tap$master_awid ;
|
|
assign fabric_2x3$v_from_masters_1_awlen = dm_mem_tap$master_awlen ;
|
|
assign fabric_2x3$v_from_masters_1_awlock = dm_mem_tap$master_awlock ;
|
|
assign fabric_2x3$v_from_masters_1_awprot = dm_mem_tap$master_awprot ;
|
|
assign fabric_2x3$v_from_masters_1_awqos = dm_mem_tap$master_awqos ;
|
|
assign fabric_2x3$v_from_masters_1_awregion = dm_mem_tap$master_awregion ;
|
|
assign fabric_2x3$v_from_masters_1_awsize = dm_mem_tap$master_awsize ;
|
|
assign fabric_2x3$v_from_masters_1_awvalid = dm_mem_tap$master_awvalid ;
|
|
assign fabric_2x3$v_from_masters_1_bready = dm_mem_tap$master_bready ;
|
|
assign fabric_2x3$v_from_masters_1_rready = dm_mem_tap$master_rready ;
|
|
assign fabric_2x3$v_from_masters_1_wdata = dm_mem_tap$master_wdata ;
|
|
assign fabric_2x3$v_from_masters_1_wid = dm_mem_tap$master_wid ;
|
|
assign fabric_2x3$v_from_masters_1_wlast = dm_mem_tap$master_wlast ;
|
|
assign fabric_2x3$v_from_masters_1_wstrb = dm_mem_tap$master_wstrb ;
|
|
assign fabric_2x3$v_from_masters_1_wvalid = dm_mem_tap$master_wvalid ;
|
|
assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ;
|
|
assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ;
|
|
assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ;
|
|
assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ;
|
|
assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ;
|
|
assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ;
|
|
assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ;
|
|
assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ;
|
|
assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ;
|
|
assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ;
|
|
assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ;
|
|
assign fabric_2x3$v_to_slaves_1_arready = plic$axi4_slave_arready ;
|
|
assign fabric_2x3$v_to_slaves_1_awready = plic$axi4_slave_awready ;
|
|
assign fabric_2x3$v_to_slaves_1_bid = plic$axi4_slave_bid ;
|
|
assign fabric_2x3$v_to_slaves_1_bresp = plic$axi4_slave_bresp ;
|
|
assign fabric_2x3$v_to_slaves_1_bvalid = plic$axi4_slave_bvalid ;
|
|
assign fabric_2x3$v_to_slaves_1_rdata = plic$axi4_slave_rdata ;
|
|
assign fabric_2x3$v_to_slaves_1_rid = plic$axi4_slave_rid ;
|
|
assign fabric_2x3$v_to_slaves_1_rlast = plic$axi4_slave_rlast ;
|
|
assign fabric_2x3$v_to_slaves_1_rresp = plic$axi4_slave_rresp ;
|
|
assign fabric_2x3$v_to_slaves_1_rvalid = plic$axi4_slave_rvalid ;
|
|
assign fabric_2x3$v_to_slaves_1_wready = plic$axi4_slave_wready ;
|
|
assign fabric_2x3$v_to_slaves_2_arready = 1'd0 ;
|
|
assign fabric_2x3$v_to_slaves_2_awready = 1'd0 ;
|
|
assign fabric_2x3$v_to_slaves_2_bid = 4'b1010 /* unspecified value */ ;
|
|
assign fabric_2x3$v_to_slaves_2_bresp = 2'd0 ;
|
|
assign fabric_2x3$v_to_slaves_2_bvalid = 1'd0 ;
|
|
assign fabric_2x3$v_to_slaves_2_rdata = 64'd0 ;
|
|
assign fabric_2x3$v_to_slaves_2_rid = 4'd0 ;
|
|
assign fabric_2x3$v_to_slaves_2_rlast = 1'd1 ;
|
|
assign fabric_2x3$v_to_slaves_2_rresp = 2'd0 ;
|
|
assign fabric_2x3$v_to_slaves_2_rvalid = 1'd0 ;
|
|
assign fabric_2x3$v_to_slaves_2_wready = 1'd0 ;
|
|
assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
|
|
assign fabric_2x3$EN_set_verbosity = 1'b0 ;
|
|
|
|
// submodule plic
|
|
assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ;
|
|
assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ;
|
|
assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ;
|
|
assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ;
|
|
assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ;
|
|
assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ;
|
|
assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ;
|
|
assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ;
|
|
assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ;
|
|
assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ;
|
|
assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ;
|
|
assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ;
|
|
assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ;
|
|
assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ;
|
|
assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ;
|
|
assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ;
|
|
assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ;
|
|
assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ;
|
|
assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ;
|
|
assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ;
|
|
assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ;
|
|
assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ;
|
|
assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ;
|
|
assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ;
|
|
assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ;
|
|
assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ;
|
|
assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ;
|
|
assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ;
|
|
assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ;
|
|
assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ;
|
|
assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ;
|
|
assign plic$set_verbosity_verbosity = 4'h0 ;
|
|
assign plic$v_sources_0_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_10_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_11_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_12_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_13_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_14_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_15_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_1_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_2_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_3_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_4_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_5_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_6_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_7_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_8_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ;
|
|
assign plic$v_sources_9_m_interrupt_req_set_not_clear =
|
|
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ;
|
|
assign plic$EN_set_verbosity = 1'b0 ;
|
|
assign plic$EN_show_PLIC_state = 1'b0 ;
|
|
assign plic$EN_server_reset_request_put =
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
|
|
assign plic$EN_server_reset_response_get =
|
|
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
|
|
assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
|
|
|
|
// submodule proc
|
|
assign proc$debug_external_interrupt_req_set_not_clear =
|
|
debug_external_interrupt_req_set_not_clear ;
|
|
assign proc$hart0_csr_mem_server_request_put = 77'h0 ;
|
|
assign proc$hart0_fpr_mem_server_request_put = 70'h0 ;
|
|
assign proc$hart0_gpr_mem_server_request_put = 70'h0 ;
|
|
assign proc$hart0_put_other_req_put = 4'h0 ;
|
|
assign proc$hart0_server_run_halt_request_put = 1'b0 ;
|
|
assign proc$m_external_interrupt_req_set_not_clear =
|
|
plic$v_targets_0_m_eip ;
|
|
assign proc$master0_arready = cpu_imem_master_arready ;
|
|
assign proc$master0_awready = cpu_imem_master_awready ;
|
|
assign proc$master0_bid = cpu_imem_master_bid ;
|
|
assign proc$master0_bresp = cpu_imem_master_bresp ;
|
|
assign proc$master0_bvalid = cpu_imem_master_bvalid ;
|
|
assign proc$master0_rdata = cpu_imem_master_rdata ;
|
|
assign proc$master0_rid = cpu_imem_master_rid ;
|
|
assign proc$master0_rlast = cpu_imem_master_rlast ;
|
|
assign proc$master0_rresp = cpu_imem_master_rresp ;
|
|
assign proc$master0_rvalid = cpu_imem_master_rvalid ;
|
|
assign proc$master0_wready = cpu_imem_master_wready ;
|
|
assign proc$master1_arready = fabric_2x3$v_from_masters_0_arready ;
|
|
assign proc$master1_awready = fabric_2x3$v_from_masters_0_awready ;
|
|
assign proc$master1_bid = fabric_2x3$v_from_masters_0_bid ;
|
|
assign proc$master1_bresp = fabric_2x3$v_from_masters_0_bresp ;
|
|
assign proc$master1_bvalid = fabric_2x3$v_from_masters_0_bvalid ;
|
|
assign proc$master1_rdata = fabric_2x3$v_from_masters_0_rdata ;
|
|
assign proc$master1_rid = fabric_2x3$v_from_masters_0_rid ;
|
|
assign proc$master1_rlast = fabric_2x3$v_from_masters_0_rlast ;
|
|
assign proc$master1_rresp = fabric_2x3$v_from_masters_0_rresp ;
|
|
assign proc$master1_rvalid = fabric_2x3$v_from_masters_0_rvalid ;
|
|
assign proc$master1_wready = fabric_2x3$v_from_masters_0_wready ;
|
|
assign proc$non_maskable_interrupt_req_set_not_clear = 1'd0 ;
|
|
assign proc$s_external_interrupt_req_set_not_clear =
|
|
plic$v_targets_1_m_eip ;
|
|
assign proc$set_verbosity_verbosity = set_verbosity_verbosity ;
|
|
assign proc$start_fromhostAddr = rg_fromhost_addr ;
|
|
assign proc$start_startpc = 64'h0000000070000000 ;
|
|
assign proc$start_tohostAddr = rg_tohost_addr ;
|
|
assign proc$EN_hart0_server_reset_request_put = CAN_FIRE_RL_rl_once ;
|
|
assign proc$EN_hart0_server_reset_response_get =
|
|
CAN_FIRE_RL_rl_hart0_server_reset ;
|
|
assign proc$EN_start = CAN_FIRE_RL_rl_hart0_server_reset ;
|
|
assign proc$EN_set_verbosity = EN_set_verbosity ;
|
|
assign proc$EN_trace_data_out_get = CAN_FIRE_RL_merge_cpu_trace_data ;
|
|
assign proc$EN_hart0_server_run_halt_request_put = 1'b0 ;
|
|
assign proc$EN_hart0_server_run_halt_response_get = 1'd1 ;
|
|
assign proc$EN_hart0_put_other_req_put = 1'b0 ;
|
|
assign proc$EN_hart0_gpr_mem_server_request_put = 1'b0 ;
|
|
assign proc$EN_hart0_gpr_mem_server_response_get = 1'b0 ;
|
|
assign proc$EN_hart0_fpr_mem_server_request_put = 1'b0 ;
|
|
assign proc$EN_hart0_fpr_mem_server_response_get = 1'b0 ;
|
|
assign proc$EN_hart0_csr_mem_server_request_put = 1'b0 ;
|
|
assign proc$EN_hart0_csr_mem_server_response_get = 1'b0 ;
|
|
|
|
// submodule soc_map
|
|
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
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assign soc_map$m_is_mem_addr_addr = 64'h0 ;
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assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
|
|
|
|
// submodule tv_encode
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assign tv_encode$trace_data_in_put = f_trace_data_merged$D_OUT ;
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assign tv_encode$EN_reset = 1'b0 ;
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|
assign tv_encode$EN_trace_data_in_put = CAN_FIRE_RL_mkConnectionGetPut ;
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assign tv_encode$EN_tv_vb_out_get = EN_tv_verifier_info_get_get ;
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
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|
begin
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|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
hart0_halt <= `BSV_ASSIGNMENT_DELAY 1'd0;
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|
rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0;
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|
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0;
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|
end
|
|
else
|
|
begin
|
|
if (hart0_halt$EN)
|
|
hart0_halt <= `BSV_ASSIGNMENT_DELAY hart0_halt$D_IN;
|
|
if (rg_fromhost_addr$EN)
|
|
rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN;
|
|
if (rg_tohost_addr$EN)
|
|
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN;
|
|
end
|
|
if (cpu_reset_either$RST_OUT == `BSV_RESET_VALUE)
|
|
begin
|
|
once <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (once$EN) once <= `BSV_ASSIGNMENT_DELAY once$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
hart0_halt = 1'h0;
|
|
once = 1'h0;
|
|
rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA;
|
|
rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
|
|
begin
|
|
v__h5014 = $stime;
|
|
#0;
|
|
end
|
|
v__h5008 = v__h5014 / 32'd10;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
|
|
$display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc",
|
|
v__h5008);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
|
|
begin
|
|
v__h4855 = $stime;
|
|
#0;
|
|
end
|
|
v__h4849 = v__h4855 / 32'd10;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
|
|
$display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4849);
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkCoreW
|
|
|