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Toooba/src_bsc_lib_RTL
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Darius Rad 4d1030df47 Add support for external debug module.
2019-04-09 14:08:36 -04:00
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BRAM2.v
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FIFO1.v
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FIFO2.v
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FIFO10.v
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FIFO20.v
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FIFOL1.v
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main.v
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MakeClock.v
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MakeResetA.v
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README.txt
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RegFile.v
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RegFileLoad.v
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ResetEither.v
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RevertReg.v
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SizedFIFO0.v
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SizedFIFO.v
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SyncFIFOLevel.v
Add support for external debug module.
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SyncHandshake.v
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SyncResetA.v
Add support for external debug module.
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README.txt 

These are copies of a few of the Verilog files that are found in any
standard Bluespec bsc distribution at $(BLUESPECDIR)/Verilog
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