23 lines
262 B
Plaintext
23 lines
262 B
Plaintext
*~
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README.html
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build_dir
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*.bo
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*.ba
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*.o
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obj_dir
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elf_to_hex
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Mem.hex
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exe*
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*.log
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Tests/Logs
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*_edited.v
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*.trace_mem_load
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AA_*
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symbol_table.txt
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vpi_wrapper_*
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builds/RV*/build_dir
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builds/RV*/Verilog_RTL
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.depends.mk
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src_SSITH_P3/Verilog_RTL
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src_SSITH_P3/Verilog_RTL_sim
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