Cheri-research/Toooba
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Toooba/src_SSITH_P3/Verilog_RTL/mkCore.v

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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_coreReq_start O 1 const
// RDY_coreReq_perfReq O 1 reg
// coreIndInv_perfResp O 73
// RDY_coreIndInv_perfResp O 1 reg
// RDY_coreIndInv_terminate O 1 reg
// dCacheToParent_rsToP_notEmpty O 1
// RDY_dCacheToParent_rsToP_notEmpty O 1 const
// RDY_dCacheToParent_rsToP_deq O 1
// dCacheToParent_rsToP_first O 579
// RDY_dCacheToParent_rsToP_first O 1
// dCacheToParent_rqToP_notEmpty O 1
// RDY_dCacheToParent_rqToP_notEmpty O 1 const
// RDY_dCacheToParent_rqToP_deq O 1
// dCacheToParent_rqToP_first O 72
// RDY_dCacheToParent_rqToP_first O 1
// dCacheToParent_fromP_notFull O 1
// RDY_dCacheToParent_fromP_notFull O 1 const
// RDY_dCacheToParent_fromP_enq O 1
// iCacheToParent_rsToP_notEmpty O 1
// RDY_iCacheToParent_rsToP_notEmpty O 1 const
// RDY_iCacheToParent_rsToP_deq O 1
// iCacheToParent_rsToP_first O 579
// RDY_iCacheToParent_rsToP_first O 1
// iCacheToParent_rqToP_notEmpty O 1
// RDY_iCacheToParent_rqToP_notEmpty O 1 const
// RDY_iCacheToParent_rqToP_deq O 1
// iCacheToParent_rqToP_first O 72
// RDY_iCacheToParent_rqToP_first O 1
// iCacheToParent_fromP_notFull O 1
// RDY_iCacheToParent_fromP_notFull O 1 const
// RDY_iCacheToParent_fromP_enq O 1
// tlbToMem_memReq_notEmpty O 1
// RDY_tlbToMem_memReq_notEmpty O 1 const
// RDY_tlbToMem_memReq_deq O 1
// tlbToMem_memReq_first O 65
// RDY_tlbToMem_memReq_first O 1
// tlbToMem_respLd_notFull O 1
// RDY_tlbToMem_respLd_notFull O 1 const
// RDY_tlbToMem_respLd_enq O 1
// mmioToPlatform_cRq_notEmpty O 1
// RDY_mmioToPlatform_cRq_notEmpty O 1 const
// RDY_mmioToPlatform_cRq_deq O 1
// mmioToPlatform_cRq_first O 142
// RDY_mmioToPlatform_cRq_first O 1
// mmioToPlatform_pRs_notFull O 1
// RDY_mmioToPlatform_pRs_notFull O 1 const
// RDY_mmioToPlatform_pRs_enq O 1
// mmioToPlatform_pRq_notFull O 1
// RDY_mmioToPlatform_pRq_notFull O 1 const
// RDY_mmioToPlatform_pRq_enq O 1
// mmioToPlatform_cRs_notEmpty O 1
// RDY_mmioToPlatform_cRs_notEmpty O 1 const
// RDY_mmioToPlatform_cRs_deq O 1
// mmioToPlatform_cRs_first O 1 reg
// RDY_mmioToPlatform_cRs_first O 1
// RDY_mmioToPlatform_setTime O 1 const
// sendDoStats O 1 reg
// RDY_sendDoStats O 1 reg
// RDY_recvDoStats O 1 const
// deadlock_dCacheCRqStuck_get O 73 const
// RDY_deadlock_dCacheCRqStuck_get O 1 const
// deadlock_dCachePRqStuck_get O 68 const
// RDY_deadlock_dCachePRqStuck_get O 1 const
// deadlock_iCacheCRqStuck_get O 68 const
// RDY_deadlock_iCacheCRqStuck_get O 1 const
// deadlock_iCachePRqStuck_get O 68 const
// RDY_deadlock_iCachePRqStuck_get O 1 const
// deadlock_renameInstStuck_get O 78 const
// RDY_deadlock_renameInstStuck_get O 1 const
// deadlock_renameCorrectPathStuck_get O 78 const
// RDY_deadlock_renameCorrectPathStuck_get O 1 const
// deadlock_commitInstStuck_get O 163 const
// RDY_deadlock_commitInstStuck_get O 1 const
// deadlock_commitUserInstStuck_get O 163 const
// RDY_deadlock_commitUserInstStuck_get O 1 const
// RDY_deadlock_checkStarted_get O 1 const
// renameDebug_renameErr_get O 89 const
// RDY_renameDebug_renameErr_get O 1 const
// RDY_setMEIP O 1 const
// RDY_setSEIP O 1 const
// RDY_hart0_run_halt_server_request_put O 1 reg
// hart0_run_halt_server_response_get O 1 reg
// RDY_hart0_run_halt_server_response_get O 1 reg
// RDY_hart0_gpr_mem_server_request_put O 1 reg
// hart0_gpr_mem_server_response_get O 65 reg
// RDY_hart0_gpr_mem_server_response_get O 1 reg
// RDY_hart0_fpr_mem_server_request_put O 1 reg
// hart0_fpr_mem_server_response_get O 65 reg
// RDY_hart0_fpr_mem_server_response_get O 1 reg
// RDY_hart0_csr_mem_server_request_put O 1 reg
// hart0_csr_mem_server_response_get O 65 reg
// RDY_hart0_csr_mem_server_response_get O 1 reg
// v_to_TV_0_get O 713
// RDY_v_to_TV_0_get O 1 reg
// v_to_TV_1_get O 713
// RDY_v_to_TV_1_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// coreReq_start_startpc I 64
// coreReq_start_toHostAddr I 64 reg
// coreReq_start_fromHostAddr I 64 reg
// coreReq_perfReq_loc I 4 reg
// coreReq_perfReq_t I 5 reg
// dCacheToParent_fromP_enq_x I 583
// iCacheToParent_fromP_enq_x I 583
// tlbToMem_respLd_enq_x I 65
// mmioToPlatform_pRs_enq_x I 67
// mmioToPlatform_pRq_enq_x I 39
// mmioToPlatform_setTime_t I 64 reg
// recvDoStats_x I 1 reg
// setMEIP_v I 1
// setSEIP_v I 1
// hart0_run_halt_server_request_put I 1 reg
// hart0_gpr_mem_server_request_put I 70 reg
// hart0_fpr_mem_server_request_put I 70 reg
// hart0_csr_mem_server_request_put I 77 reg
// EN_coreReq_start I 1
// EN_coreReq_perfReq I 1
// EN_coreIndInv_terminate I 1
// EN_dCacheToParent_rsToP_deq I 1
// EN_dCacheToParent_rqToP_deq I 1
// EN_dCacheToParent_fromP_enq I 1
// EN_iCacheToParent_rsToP_deq I 1
// EN_iCacheToParent_rqToP_deq I 1
// EN_iCacheToParent_fromP_enq I 1
// EN_tlbToMem_memReq_deq I 1
// EN_tlbToMem_respLd_enq I 1
// EN_mmioToPlatform_cRq_deq I 1
// EN_mmioToPlatform_pRs_enq I 1
// EN_mmioToPlatform_pRq_enq I 1
// EN_mmioToPlatform_cRs_deq I 1
// EN_mmioToPlatform_setTime I 1
// EN_recvDoStats I 1
// EN_deadlock_checkStarted_get I 1 unused
// EN_setMEIP I 1
// EN_setSEIP I 1
// EN_hart0_run_halt_server_request_put I 1
// EN_hart0_gpr_mem_server_request_put I 1
// EN_hart0_fpr_mem_server_request_put I 1
// EN_hart0_csr_mem_server_request_put I 1
// EN_coreIndInv_perfResp I 1
// EN_sendDoStats I 1
// EN_deadlock_dCacheCRqStuck_get I 1 unused
// EN_deadlock_dCachePRqStuck_get I 1 unused
// EN_deadlock_iCacheCRqStuck_get I 1 unused
// EN_deadlock_iCachePRqStuck_get I 1 unused
// EN_deadlock_renameInstStuck_get I 1 unused
// EN_deadlock_renameCorrectPathStuck_get I 1 unused
// EN_deadlock_commitInstStuck_get I 1 unused
// EN_deadlock_commitUserInstStuck_get I 1 unused
// EN_renameDebug_renameErr_get I 1 unused
// EN_hart0_run_halt_server_response_get I 1
// EN_hart0_gpr_mem_server_response_get I 1
// EN_hart0_fpr_mem_server_response_get I 1
// EN_hart0_csr_mem_server_response_get I 1
// EN_v_to_TV_0_get I 1
// EN_v_to_TV_1_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCore(CLK,
RST_N,
coreReq_start_startpc,
coreReq_start_toHostAddr,
coreReq_start_fromHostAddr,
EN_coreReq_start,
RDY_coreReq_start,
coreReq_perfReq_loc,
coreReq_perfReq_t,
EN_coreReq_perfReq,
RDY_coreReq_perfReq,
EN_coreIndInv_perfResp,
coreIndInv_perfResp,
RDY_coreIndInv_perfResp,
EN_coreIndInv_terminate,
RDY_coreIndInv_terminate,
dCacheToParent_rsToP_notEmpty,
RDY_dCacheToParent_rsToP_notEmpty,
EN_dCacheToParent_rsToP_deq,
RDY_dCacheToParent_rsToP_deq,
dCacheToParent_rsToP_first,
RDY_dCacheToParent_rsToP_first,
dCacheToParent_rqToP_notEmpty,
RDY_dCacheToParent_rqToP_notEmpty,
EN_dCacheToParent_rqToP_deq,
RDY_dCacheToParent_rqToP_deq,
dCacheToParent_rqToP_first,
RDY_dCacheToParent_rqToP_first,
dCacheToParent_fromP_notFull,
RDY_dCacheToParent_fromP_notFull,
dCacheToParent_fromP_enq_x,
EN_dCacheToParent_fromP_enq,
RDY_dCacheToParent_fromP_enq,
iCacheToParent_rsToP_notEmpty,
RDY_iCacheToParent_rsToP_notEmpty,
EN_iCacheToParent_rsToP_deq,
RDY_iCacheToParent_rsToP_deq,
iCacheToParent_rsToP_first,
RDY_iCacheToParent_rsToP_first,
iCacheToParent_rqToP_notEmpty,
RDY_iCacheToParent_rqToP_notEmpty,
EN_iCacheToParent_rqToP_deq,
RDY_iCacheToParent_rqToP_deq,
iCacheToParent_rqToP_first,
RDY_iCacheToParent_rqToP_first,
iCacheToParent_fromP_notFull,
RDY_iCacheToParent_fromP_notFull,
iCacheToParent_fromP_enq_x,
EN_iCacheToParent_fromP_enq,
RDY_iCacheToParent_fromP_enq,
tlbToMem_memReq_notEmpty,
RDY_tlbToMem_memReq_notEmpty,
EN_tlbToMem_memReq_deq,
RDY_tlbToMem_memReq_deq,
tlbToMem_memReq_first,
RDY_tlbToMem_memReq_first,
tlbToMem_respLd_notFull,
RDY_tlbToMem_respLd_notFull,
tlbToMem_respLd_enq_x,
EN_tlbToMem_respLd_enq,
RDY_tlbToMem_respLd_enq,
mmioToPlatform_cRq_notEmpty,
RDY_mmioToPlatform_cRq_notEmpty,
EN_mmioToPlatform_cRq_deq,
RDY_mmioToPlatform_cRq_deq,
mmioToPlatform_cRq_first,
RDY_mmioToPlatform_cRq_first,
mmioToPlatform_pRs_notFull,
RDY_mmioToPlatform_pRs_notFull,
mmioToPlatform_pRs_enq_x,
EN_mmioToPlatform_pRs_enq,
RDY_mmioToPlatform_pRs_enq,
mmioToPlatform_pRq_notFull,
RDY_mmioToPlatform_pRq_notFull,
mmioToPlatform_pRq_enq_x,
EN_mmioToPlatform_pRq_enq,
RDY_mmioToPlatform_pRq_enq,
mmioToPlatform_cRs_notEmpty,
RDY_mmioToPlatform_cRs_notEmpty,
EN_mmioToPlatform_cRs_deq,
RDY_mmioToPlatform_cRs_deq,
mmioToPlatform_cRs_first,
RDY_mmioToPlatform_cRs_first,
mmioToPlatform_setTime_t,
EN_mmioToPlatform_setTime,
RDY_mmioToPlatform_setTime,
EN_sendDoStats,
sendDoStats,
RDY_sendDoStats,
recvDoStats_x,
EN_recvDoStats,
RDY_recvDoStats,
EN_deadlock_dCacheCRqStuck_get,
deadlock_dCacheCRqStuck_get,
RDY_deadlock_dCacheCRqStuck_get,
EN_deadlock_dCachePRqStuck_get,
deadlock_dCachePRqStuck_get,
RDY_deadlock_dCachePRqStuck_get,
EN_deadlock_iCacheCRqStuck_get,
deadlock_iCacheCRqStuck_get,
RDY_deadlock_iCacheCRqStuck_get,
EN_deadlock_iCachePRqStuck_get,
deadlock_iCachePRqStuck_get,
RDY_deadlock_iCachePRqStuck_get,
EN_deadlock_renameInstStuck_get,
deadlock_renameInstStuck_get,
RDY_deadlock_renameInstStuck_get,
EN_deadlock_renameCorrectPathStuck_get,
deadlock_renameCorrectPathStuck_get,
RDY_deadlock_renameCorrectPathStuck_get,
EN_deadlock_commitInstStuck_get,
deadlock_commitInstStuck_get,
RDY_deadlock_commitInstStuck_get,
EN_deadlock_commitUserInstStuck_get,
deadlock_commitUserInstStuck_get,
RDY_deadlock_commitUserInstStuck_get,
EN_deadlock_checkStarted_get,
RDY_deadlock_checkStarted_get,
EN_renameDebug_renameErr_get,
renameDebug_renameErr_get,
RDY_renameDebug_renameErr_get,
setMEIP_v,
EN_setMEIP,
RDY_setMEIP,
setSEIP_v,
EN_setSEIP,
RDY_setSEIP,
hart0_run_halt_server_request_put,
EN_hart0_run_halt_server_request_put,
RDY_hart0_run_halt_server_request_put,
EN_hart0_run_halt_server_response_get,
hart0_run_halt_server_response_get,
RDY_hart0_run_halt_server_response_get,
hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_response_get,
hart0_gpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_response_get,
hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
RDY_hart0_fpr_mem_server_response_get,
hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_response_get,
hart0_csr_mem_server_response_get,
RDY_hart0_csr_mem_server_response_get,
EN_v_to_TV_0_get,
v_to_TV_0_get,
RDY_v_to_TV_0_get,
EN_v_to_TV_1_get,
v_to_TV_1_get,
RDY_v_to_TV_1_get);
input CLK;
input RST_N;
// action method coreReq_start
input [63 : 0] coreReq_start_startpc;
input [63 : 0] coreReq_start_toHostAddr;
input [63 : 0] coreReq_start_fromHostAddr;
input EN_coreReq_start;
output RDY_coreReq_start;
// action method coreReq_perfReq
input [3 : 0] coreReq_perfReq_loc;
input [4 : 0] coreReq_perfReq_t;
input EN_coreReq_perfReq;
output RDY_coreReq_perfReq;
// actionvalue method coreIndInv_perfResp
input EN_coreIndInv_perfResp;
output [72 : 0] coreIndInv_perfResp;
output RDY_coreIndInv_perfResp;
// action method coreIndInv_terminate
input EN_coreIndInv_terminate;
output RDY_coreIndInv_terminate;
// value method dCacheToParent_rsToP_notEmpty
output dCacheToParent_rsToP_notEmpty;
output RDY_dCacheToParent_rsToP_notEmpty;
// action method dCacheToParent_rsToP_deq
input EN_dCacheToParent_rsToP_deq;
output RDY_dCacheToParent_rsToP_deq;
// value method dCacheToParent_rsToP_first
output [578 : 0] dCacheToParent_rsToP_first;
output RDY_dCacheToParent_rsToP_first;
// value method dCacheToParent_rqToP_notEmpty
output dCacheToParent_rqToP_notEmpty;
output RDY_dCacheToParent_rqToP_notEmpty;
// action method dCacheToParent_rqToP_deq
input EN_dCacheToParent_rqToP_deq;
output RDY_dCacheToParent_rqToP_deq;
// value method dCacheToParent_rqToP_first
output [71 : 0] dCacheToParent_rqToP_first;
output RDY_dCacheToParent_rqToP_first;
// value method dCacheToParent_fromP_notFull
output dCacheToParent_fromP_notFull;
output RDY_dCacheToParent_fromP_notFull;
// action method dCacheToParent_fromP_enq
input [582 : 0] dCacheToParent_fromP_enq_x;
input EN_dCacheToParent_fromP_enq;
output RDY_dCacheToParent_fromP_enq;
// value method iCacheToParent_rsToP_notEmpty
output iCacheToParent_rsToP_notEmpty;
output RDY_iCacheToParent_rsToP_notEmpty;
// action method iCacheToParent_rsToP_deq
input EN_iCacheToParent_rsToP_deq;
output RDY_iCacheToParent_rsToP_deq;
// value method iCacheToParent_rsToP_first
output [578 : 0] iCacheToParent_rsToP_first;
output RDY_iCacheToParent_rsToP_first;
// value method iCacheToParent_rqToP_notEmpty
output iCacheToParent_rqToP_notEmpty;
output RDY_iCacheToParent_rqToP_notEmpty;
// action method iCacheToParent_rqToP_deq
input EN_iCacheToParent_rqToP_deq;
output RDY_iCacheToParent_rqToP_deq;
// value method iCacheToParent_rqToP_first
output [71 : 0] iCacheToParent_rqToP_first;
output RDY_iCacheToParent_rqToP_first;
// value method iCacheToParent_fromP_notFull
output iCacheToParent_fromP_notFull;
output RDY_iCacheToParent_fromP_notFull;
// action method iCacheToParent_fromP_enq
input [582 : 0] iCacheToParent_fromP_enq_x;
input EN_iCacheToParent_fromP_enq;
output RDY_iCacheToParent_fromP_enq;
// value method tlbToMem_memReq_notEmpty
output tlbToMem_memReq_notEmpty;
output RDY_tlbToMem_memReq_notEmpty;
// action method tlbToMem_memReq_deq
input EN_tlbToMem_memReq_deq;
output RDY_tlbToMem_memReq_deq;
// value method tlbToMem_memReq_first
output [64 : 0] tlbToMem_memReq_first;
output RDY_tlbToMem_memReq_first;
// value method tlbToMem_respLd_notFull
output tlbToMem_respLd_notFull;
output RDY_tlbToMem_respLd_notFull;
// action method tlbToMem_respLd_enq
input [64 : 0] tlbToMem_respLd_enq_x;
input EN_tlbToMem_respLd_enq;
output RDY_tlbToMem_respLd_enq;
// value method mmioToPlatform_cRq_notEmpty
output mmioToPlatform_cRq_notEmpty;
output RDY_mmioToPlatform_cRq_notEmpty;
// action method mmioToPlatform_cRq_deq
input EN_mmioToPlatform_cRq_deq;
output RDY_mmioToPlatform_cRq_deq;
// value method mmioToPlatform_cRq_first
output [141 : 0] mmioToPlatform_cRq_first;
output RDY_mmioToPlatform_cRq_first;
// value method mmioToPlatform_pRs_notFull
output mmioToPlatform_pRs_notFull;
output RDY_mmioToPlatform_pRs_notFull;
// action method mmioToPlatform_pRs_enq
input [66 : 0] mmioToPlatform_pRs_enq_x;
input EN_mmioToPlatform_pRs_enq;
output RDY_mmioToPlatform_pRs_enq;
// value method mmioToPlatform_pRq_notFull
output mmioToPlatform_pRq_notFull;
output RDY_mmioToPlatform_pRq_notFull;
// action method mmioToPlatform_pRq_enq
input [38 : 0] mmioToPlatform_pRq_enq_x;
input EN_mmioToPlatform_pRq_enq;
output RDY_mmioToPlatform_pRq_enq;
// value method mmioToPlatform_cRs_notEmpty
output mmioToPlatform_cRs_notEmpty;
output RDY_mmioToPlatform_cRs_notEmpty;
// action method mmioToPlatform_cRs_deq
input EN_mmioToPlatform_cRs_deq;
output RDY_mmioToPlatform_cRs_deq;
// value method mmioToPlatform_cRs_first
output mmioToPlatform_cRs_first;
output RDY_mmioToPlatform_cRs_first;
// action method mmioToPlatform_setTime
input [63 : 0] mmioToPlatform_setTime_t;
input EN_mmioToPlatform_setTime;
output RDY_mmioToPlatform_setTime;
// actionvalue method sendDoStats
input EN_sendDoStats;
output sendDoStats;
output RDY_sendDoStats;
// action method recvDoStats
input recvDoStats_x;
input EN_recvDoStats;
output RDY_recvDoStats;
// actionvalue method deadlock_dCacheCRqStuck_get
input EN_deadlock_dCacheCRqStuck_get;
output [72 : 0] deadlock_dCacheCRqStuck_get;
output RDY_deadlock_dCacheCRqStuck_get;
// actionvalue method deadlock_dCachePRqStuck_get
input EN_deadlock_dCachePRqStuck_get;
output [67 : 0] deadlock_dCachePRqStuck_get;
output RDY_deadlock_dCachePRqStuck_get;
// actionvalue method deadlock_iCacheCRqStuck_get
input EN_deadlock_iCacheCRqStuck_get;
output [67 : 0] deadlock_iCacheCRqStuck_get;
output RDY_deadlock_iCacheCRqStuck_get;
// actionvalue method deadlock_iCachePRqStuck_get
input EN_deadlock_iCachePRqStuck_get;
output [67 : 0] deadlock_iCachePRqStuck_get;
output RDY_deadlock_iCachePRqStuck_get;
// actionvalue method deadlock_renameInstStuck_get
input EN_deadlock_renameInstStuck_get;
output [77 : 0] deadlock_renameInstStuck_get;
output RDY_deadlock_renameInstStuck_get;
// actionvalue method deadlock_renameCorrectPathStuck_get
input EN_deadlock_renameCorrectPathStuck_get;
output [77 : 0] deadlock_renameCorrectPathStuck_get;
output RDY_deadlock_renameCorrectPathStuck_get;
// actionvalue method deadlock_commitInstStuck_get
input EN_deadlock_commitInstStuck_get;
output [162 : 0] deadlock_commitInstStuck_get;
output RDY_deadlock_commitInstStuck_get;
// actionvalue method deadlock_commitUserInstStuck_get
input EN_deadlock_commitUserInstStuck_get;
output [162 : 0] deadlock_commitUserInstStuck_get;
output RDY_deadlock_commitUserInstStuck_get;
// action method deadlock_checkStarted_get
input EN_deadlock_checkStarted_get;
output RDY_deadlock_checkStarted_get;
// actionvalue method renameDebug_renameErr_get
input EN_renameDebug_renameErr_get;
output [88 : 0] renameDebug_renameErr_get;
output RDY_renameDebug_renameErr_get;
// action method setMEIP
input setMEIP_v;
input EN_setMEIP;
output RDY_setMEIP;
// action method setSEIP
input setSEIP_v;
input EN_setSEIP;
output RDY_setSEIP;
// action method hart0_run_halt_server_request_put
input hart0_run_halt_server_request_put;
input EN_hart0_run_halt_server_request_put;
output RDY_hart0_run_halt_server_request_put;
// actionvalue method hart0_run_halt_server_response_get
input EN_hart0_run_halt_server_response_get;
output hart0_run_halt_server_response_get;
output RDY_hart0_run_halt_server_response_get;
// action method hart0_gpr_mem_server_request_put
input [69 : 0] hart0_gpr_mem_server_request_put;
input EN_hart0_gpr_mem_server_request_put;
output RDY_hart0_gpr_mem_server_request_put;
// actionvalue method hart0_gpr_mem_server_response_get
input EN_hart0_gpr_mem_server_response_get;
output [64 : 0] hart0_gpr_mem_server_response_get;
output RDY_hart0_gpr_mem_server_response_get;
// action method hart0_fpr_mem_server_request_put
input [69 : 0] hart0_fpr_mem_server_request_put;
input EN_hart0_fpr_mem_server_request_put;
output RDY_hart0_fpr_mem_server_request_put;
// actionvalue method hart0_fpr_mem_server_response_get
input EN_hart0_fpr_mem_server_response_get;
output [64 : 0] hart0_fpr_mem_server_response_get;
output RDY_hart0_fpr_mem_server_response_get;
// action method hart0_csr_mem_server_request_put
input [76 : 0] hart0_csr_mem_server_request_put;
input EN_hart0_csr_mem_server_request_put;
output RDY_hart0_csr_mem_server_request_put;
// actionvalue method hart0_csr_mem_server_response_get
input EN_hart0_csr_mem_server_response_get;
output [64 : 0] hart0_csr_mem_server_response_get;
output RDY_hart0_csr_mem_server_response_get;
// actionvalue method v_to_TV_0_get
input EN_v_to_TV_0_get;
output [712 : 0] v_to_TV_0_get;
output RDY_v_to_TV_0_get;
// actionvalue method v_to_TV_1_get
input EN_v_to_TV_1_get;
output [712 : 0] v_to_TV_1_get;
output RDY_v_to_TV_1_get;
// signals for module outputs
wire [712 : 0] v_to_TV_0_get, v_to_TV_1_get;
wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first;
wire [162 : 0] deadlock_commitInstStuck_get,
deadlock_commitUserInstStuck_get;
wire [141 : 0] mmioToPlatform_cRq_first;
wire [88 : 0] renameDebug_renameErr_get;
wire [77 : 0] deadlock_renameCorrectPathStuck_get,
deadlock_renameInstStuck_get;
wire [72 : 0] coreIndInv_perfResp, deadlock_dCacheCRqStuck_get;
wire [71 : 0] dCacheToParent_rqToP_first, iCacheToParent_rqToP_first;
wire [67 : 0] deadlock_dCachePRqStuck_get,
deadlock_iCacheCRqStuck_get,
deadlock_iCachePRqStuck_get;
wire [64 : 0] hart0_csr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
hart0_gpr_mem_server_response_get,
tlbToMem_memReq_first;
wire RDY_coreIndInv_perfResp,
RDY_coreIndInv_terminate,
RDY_coreReq_perfReq,
RDY_coreReq_start,
RDY_dCacheToParent_fromP_enq,
RDY_dCacheToParent_fromP_notFull,
RDY_dCacheToParent_rqToP_deq,
RDY_dCacheToParent_rqToP_first,
RDY_dCacheToParent_rqToP_notEmpty,
RDY_dCacheToParent_rsToP_deq,
RDY_dCacheToParent_rsToP_first,
RDY_dCacheToParent_rsToP_notEmpty,
RDY_deadlock_checkStarted_get,
RDY_deadlock_commitInstStuck_get,
RDY_deadlock_commitUserInstStuck_get,
RDY_deadlock_dCacheCRqStuck_get,
RDY_deadlock_dCachePRqStuck_get,
RDY_deadlock_iCacheCRqStuck_get,
RDY_deadlock_iCachePRqStuck_get,
RDY_deadlock_renameCorrectPathStuck_get,
RDY_deadlock_renameInstStuck_get,
RDY_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_response_get,
RDY_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_response_get,
RDY_hart0_run_halt_server_request_put,
RDY_hart0_run_halt_server_response_get,
RDY_iCacheToParent_fromP_enq,
RDY_iCacheToParent_fromP_notFull,
RDY_iCacheToParent_rqToP_deq,
RDY_iCacheToParent_rqToP_first,
RDY_iCacheToParent_rqToP_notEmpty,
RDY_iCacheToParent_rsToP_deq,
RDY_iCacheToParent_rsToP_first,
RDY_iCacheToParent_rsToP_notEmpty,
RDY_mmioToPlatform_cRq_deq,
RDY_mmioToPlatform_cRq_first,
RDY_mmioToPlatform_cRq_notEmpty,
RDY_mmioToPlatform_cRs_deq,
RDY_mmioToPlatform_cRs_first,
RDY_mmioToPlatform_cRs_notEmpty,
RDY_mmioToPlatform_pRq_enq,
RDY_mmioToPlatform_pRq_notFull,
RDY_mmioToPlatform_pRs_enq,
RDY_mmioToPlatform_pRs_notFull,
RDY_mmioToPlatform_setTime,
RDY_recvDoStats,
RDY_renameDebug_renameErr_get,
RDY_sendDoStats,
RDY_setMEIP,
RDY_setSEIP,
RDY_tlbToMem_memReq_deq,
RDY_tlbToMem_memReq_first,
RDY_tlbToMem_memReq_notEmpty,
RDY_tlbToMem_respLd_enq,
RDY_tlbToMem_respLd_notFull,
RDY_v_to_TV_0_get,
RDY_v_to_TV_1_get,
dCacheToParent_fromP_notFull,
dCacheToParent_rqToP_notEmpty,
dCacheToParent_rsToP_notEmpty,
hart0_run_halt_server_response_get,
iCacheToParent_fromP_notFull,
iCacheToParent_rqToP_notEmpty,
iCacheToParent_rsToP_notEmpty,
mmioToPlatform_cRq_notEmpty,
mmioToPlatform_cRs_first,
mmioToPlatform_cRs_notEmpty,
mmioToPlatform_pRq_notFull,
mmioToPlatform_pRs_notFull,
sendDoStats,
tlbToMem_memReq_notEmpty,
tlbToMem_respLd_notFull;
// inlined wires
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget;
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget;
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget;
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget;
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget;
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget;
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget;
wire [142 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget;
wire [76 : 0] coreFix_memExe_issueLd$wget;
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget;
wire [70 : 0] coreFix_aluExe_0_bypassWire_0$wget,
coreFix_aluExe_0_bypassWire_1$wget,
coreFix_aluExe_0_bypassWire_2$wget,
coreFix_aluExe_0_bypassWire_3$wget;
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget,
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget;
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_lat_0$wget;
wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget;
wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget,
mmio_dataRespQ_enqReq_lat_0$wget;
wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget;
wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget;
wire coreFix_aluExe_0_bypassWire_0$whas,
coreFix_aluExe_0_bypassWire_1$whas,
coreFix_aluExe_0_bypassWire_2$whas,
coreFix_aluExe_0_bypassWire_3$whas,
coreFix_aluExe_1_bypassWire_2$whas,
coreFix_aluExe_1_bypassWire_3$whas,
coreFix_fpuMulDivExe_0_bypassWire_2$whas,
coreFix_fpuMulDivExe_0_bypassWire_3$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
coreFix_globalSpecUpdate_correctSpecTag_0$whas,
coreFix_globalSpecUpdate_correctSpecTag_1$whas,
coreFix_memExe_bypassWire_2$whas,
coreFix_memExe_bypassWire_3$whas,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas,
coreFix_memExe_forwardQ_enqReq_lat_0$whas,
coreFix_memExe_issueLd$whas,
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas,
coreFix_memExe_reqLdQ_data_0_lat_0$whas,
coreFix_memExe_reqLdQ_empty_lat_0$whas,
coreFix_memExe_reqLdQ_full_lat_0$whas,
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas,
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas,
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas,
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas,
csrInstOrInterruptInflight_lat_1$whas,
csrf_mcycle_ehr_data_lat_0$whas,
csrf_minstret_ehr_data_dummy_1_0$whas,
csrf_minstret_ehr_data_lat_0$whas,
csrf_minstret_ehr_data_lat_1$whas,
mmio_cRqQ_enqReq_lat_0$whas,
mmio_dataPendQ_enqReq_lat_0$whas,
mmio_dataReqQ_enqReq_lat_0$whas,
mmio_dataRespQ_deqReq_lat_0$whas,
mmio_pRsQ_deqReq_lat_0$whas;
// register commitStage_commitTrap
reg [133 : 0] commitStage_commitTrap;
wire [133 : 0] commitStage_commitTrap$D_IN;
wire commitStage_commitTrap$EN;
// register commitStage_rg_just_after_reset
reg commitStage_rg_just_after_reset;
wire commitStage_rg_just_after_reset$D_IN,
commitStage_rg_just_after_reset$EN;
// register commitStage_rg_run_state
reg commitStage_rg_run_state;
wire commitStage_rg_run_state$D_IN, commitStage_rg_run_state$EN;
// register commitStage_rg_serial_num
reg [63 : 0] commitStage_rg_serial_num;
reg [63 : 0] commitStage_rg_serial_num$D_IN;
wire commitStage_rg_serial_num$EN;
// register coreFix_doStatsReg
reg coreFix_doStatsReg;
wire coreFix_doStatsReg$D_IN, coreFix_doStatsReg$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt;
wire [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready
reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit;
wire [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0;
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1;
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0;
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1;
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl;
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl;
wire [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo;
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl;
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0;
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1;
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
reg [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl;
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
reg [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl;
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN;
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
reg coreFix_memExe_dMem_perfReqQ_clearReq_rl;
wire coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_data_0
reg [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0;
wire [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
wire coreFix_memExe_dMem_perfReqQ_data_0$EN;
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
reg coreFix_memExe_dMem_perfReqQ_deqReq_rl;
wire coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_empty
reg coreFix_memExe_dMem_perfReqQ_empty;
wire coreFix_memExe_dMem_perfReqQ_empty$D_IN,
coreFix_memExe_dMem_perfReqQ_empty$EN;
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
reg [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl;
wire [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_full
reg coreFix_memExe_dMem_perfReqQ_full;
wire coreFix_memExe_dMem_perfReqQ_full$D_IN,
coreFix_memExe_dMem_perfReqQ_full$EN;
// register coreFix_memExe_forwardQ_clearReq_rl
reg coreFix_memExe_forwardQ_clearReq_rl;
wire coreFix_memExe_forwardQ_clearReq_rl$D_IN,
coreFix_memExe_forwardQ_clearReq_rl$EN;
// register coreFix_memExe_forwardQ_data_0
reg [68 : 0] coreFix_memExe_forwardQ_data_0;
wire [68 : 0] coreFix_memExe_forwardQ_data_0$D_IN;
wire coreFix_memExe_forwardQ_data_0$EN;
// register coreFix_memExe_forwardQ_data_1
reg [68 : 0] coreFix_memExe_forwardQ_data_1;
wire [68 : 0] coreFix_memExe_forwardQ_data_1$D_IN;
wire coreFix_memExe_forwardQ_data_1$EN;
// register coreFix_memExe_forwardQ_deqP
reg coreFix_memExe_forwardQ_deqP;
wire coreFix_memExe_forwardQ_deqP$D_IN, coreFix_memExe_forwardQ_deqP$EN;
// register coreFix_memExe_forwardQ_deqReq_rl
reg coreFix_memExe_forwardQ_deqReq_rl;
wire coreFix_memExe_forwardQ_deqReq_rl$D_IN,
coreFix_memExe_forwardQ_deqReq_rl$EN;
// register coreFix_memExe_forwardQ_empty
reg coreFix_memExe_forwardQ_empty;
wire coreFix_memExe_forwardQ_empty$D_IN, coreFix_memExe_forwardQ_empty$EN;
// register coreFix_memExe_forwardQ_enqP
reg coreFix_memExe_forwardQ_enqP;
wire coreFix_memExe_forwardQ_enqP$D_IN, coreFix_memExe_forwardQ_enqP$EN;
// register coreFix_memExe_forwardQ_enqReq_rl
reg [69 : 0] coreFix_memExe_forwardQ_enqReq_rl;
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN;
wire coreFix_memExe_forwardQ_enqReq_rl$EN;
// register coreFix_memExe_forwardQ_full
reg coreFix_memExe_forwardQ_full;
wire coreFix_memExe_forwardQ_full$D_IN, coreFix_memExe_forwardQ_full$EN;
// register coreFix_memExe_memRespLdQ_clearReq_rl
reg coreFix_memExe_memRespLdQ_clearReq_rl;
wire coreFix_memExe_memRespLdQ_clearReq_rl$D_IN,
coreFix_memExe_memRespLdQ_clearReq_rl$EN;
// register coreFix_memExe_memRespLdQ_data_0
reg [68 : 0] coreFix_memExe_memRespLdQ_data_0;
wire [68 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN;
wire coreFix_memExe_memRespLdQ_data_0$EN;
// register coreFix_memExe_memRespLdQ_data_1
reg [68 : 0] coreFix_memExe_memRespLdQ_data_1;
wire [68 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN;
wire coreFix_memExe_memRespLdQ_data_1$EN;
// register coreFix_memExe_memRespLdQ_deqP
reg coreFix_memExe_memRespLdQ_deqP;
wire coreFix_memExe_memRespLdQ_deqP$D_IN, coreFix_memExe_memRespLdQ_deqP$EN;
// register coreFix_memExe_memRespLdQ_deqReq_rl
reg coreFix_memExe_memRespLdQ_deqReq_rl;
wire coreFix_memExe_memRespLdQ_deqReq_rl$D_IN,
coreFix_memExe_memRespLdQ_deqReq_rl$EN;
// register coreFix_memExe_memRespLdQ_empty
reg coreFix_memExe_memRespLdQ_empty;
wire coreFix_memExe_memRespLdQ_empty$D_IN,
coreFix_memExe_memRespLdQ_empty$EN;
// register coreFix_memExe_memRespLdQ_enqP
reg coreFix_memExe_memRespLdQ_enqP;
wire coreFix_memExe_memRespLdQ_enqP$D_IN, coreFix_memExe_memRespLdQ_enqP$EN;
// register coreFix_memExe_memRespLdQ_enqReq_rl
reg [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl;
wire [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
wire coreFix_memExe_memRespLdQ_enqReq_rl$EN;
// register coreFix_memExe_memRespLdQ_full
reg coreFix_memExe_memRespLdQ_full;
wire coreFix_memExe_memRespLdQ_full$D_IN, coreFix_memExe_memRespLdQ_full$EN;
// register coreFix_memExe_reqLdQ_data_0_rl
reg [68 : 0] coreFix_memExe_reqLdQ_data_0_rl;
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_rl$D_IN;
wire coreFix_memExe_reqLdQ_data_0_rl$EN;
// register coreFix_memExe_reqLdQ_empty_rl
reg coreFix_memExe_reqLdQ_empty_rl;
wire coreFix_memExe_reqLdQ_empty_rl$D_IN, coreFix_memExe_reqLdQ_empty_rl$EN;
// register coreFix_memExe_reqLdQ_full_rl
reg coreFix_memExe_reqLdQ_full_rl;
wire coreFix_memExe_reqLdQ_full_rl$D_IN, coreFix_memExe_reqLdQ_full_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
reg [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl;
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
wire coreFix_memExe_reqLrScAmoQ_data_0_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_empty_rl
reg coreFix_memExe_reqLrScAmoQ_empty_rl;
wire coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_full_rl
reg coreFix_memExe_reqLrScAmoQ_full_rl;
wire coreFix_memExe_reqLrScAmoQ_full_rl$D_IN,
coreFix_memExe_reqLrScAmoQ_full_rl$EN;
// register coreFix_memExe_reqStQ_data_0_rl
reg [65 : 0] coreFix_memExe_reqStQ_data_0_rl;
wire [65 : 0] coreFix_memExe_reqStQ_data_0_rl$D_IN;
wire coreFix_memExe_reqStQ_data_0_rl$EN;
// register coreFix_memExe_reqStQ_empty_rl
reg coreFix_memExe_reqStQ_empty_rl;
wire coreFix_memExe_reqStQ_empty_rl$D_IN, coreFix_memExe_reqStQ_empty_rl$EN;
// register coreFix_memExe_reqStQ_full_rl
reg coreFix_memExe_reqStQ_full_rl;
wire coreFix_memExe_reqStQ_full_rl$D_IN, coreFix_memExe_reqStQ_full_rl$EN;
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
reg coreFix_memExe_respLrScAmoQ_clearReq_rl;
wire coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_data_0
reg [63 : 0] coreFix_memExe_respLrScAmoQ_data_0;
wire [63 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN;
wire coreFix_memExe_respLrScAmoQ_data_0$EN;
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
reg coreFix_memExe_respLrScAmoQ_deqReq_rl;
wire coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_empty
reg coreFix_memExe_respLrScAmoQ_empty;
wire coreFix_memExe_respLrScAmoQ_empty$D_IN,
coreFix_memExe_respLrScAmoQ_empty$EN;
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl;
wire [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
wire coreFix_memExe_respLrScAmoQ_enqReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_full
reg coreFix_memExe_respLrScAmoQ_full;
wire coreFix_memExe_respLrScAmoQ_full$D_IN,
coreFix_memExe_respLrScAmoQ_full$EN;
// register coreFix_memExe_waitLrScAmoMMIOResp
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp;
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
wire coreFix_memExe_waitLrScAmoMMIOResp$EN;
// register csrInstOrInterruptInflight_rl
reg csrInstOrInterruptInflight_rl;
wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN;
// register csrf_external_int_en_vec_0
reg csrf_external_int_en_vec_0;
wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN;
// register csrf_external_int_en_vec_1
reg csrf_external_int_en_vec_1;
wire csrf_external_int_en_vec_1$D_IN, csrf_external_int_en_vec_1$EN;
// register csrf_external_int_en_vec_3
reg csrf_external_int_en_vec_3;
wire csrf_external_int_en_vec_3$D_IN, csrf_external_int_en_vec_3$EN;
// register csrf_external_int_pend_vec_0
reg csrf_external_int_pend_vec_0;
wire csrf_external_int_pend_vec_0$D_IN, csrf_external_int_pend_vec_0$EN;
// register csrf_external_int_pend_vec_1
reg csrf_external_int_pend_vec_1;
reg csrf_external_int_pend_vec_1$D_IN;
wire csrf_external_int_pend_vec_1$EN;
// register csrf_external_int_pend_vec_3
reg csrf_external_int_pend_vec_3;
reg csrf_external_int_pend_vec_3$D_IN;
wire csrf_external_int_pend_vec_3$EN;
// register csrf_fflags_reg
reg [4 : 0] csrf_fflags_reg;
reg [4 : 0] csrf_fflags_reg$D_IN;
wire csrf_fflags_reg$EN;
// register csrf_frm_reg
reg [2 : 0] csrf_frm_reg;
wire [2 : 0] csrf_frm_reg$D_IN;
wire csrf_frm_reg$EN;
// register csrf_fs_reg
reg [1 : 0] csrf_fs_reg;
reg [1 : 0] csrf_fs_reg$D_IN;
wire csrf_fs_reg$EN;
// register csrf_ie_vec_0
reg csrf_ie_vec_0;
wire csrf_ie_vec_0$D_IN, csrf_ie_vec_0$EN;
// register csrf_ie_vec_1
reg csrf_ie_vec_1;
reg csrf_ie_vec_1$D_IN;
wire csrf_ie_vec_1$EN;
// register csrf_ie_vec_3
reg csrf_ie_vec_3;
reg csrf_ie_vec_3$D_IN;
wire csrf_ie_vec_3$EN;
// register csrf_mcause_code_reg
reg [3 : 0] csrf_mcause_code_reg;
reg [3 : 0] csrf_mcause_code_reg$D_IN;
wire csrf_mcause_code_reg$EN;
// register csrf_mcause_interrupt_reg
reg csrf_mcause_interrupt_reg;
reg csrf_mcause_interrupt_reg$D_IN;
wire csrf_mcause_interrupt_reg$EN;
// register csrf_mcounteren_cy_reg
reg csrf_mcounteren_cy_reg;
wire csrf_mcounteren_cy_reg$D_IN, csrf_mcounteren_cy_reg$EN;
// register csrf_mcounteren_ir_reg
reg csrf_mcounteren_ir_reg;
wire csrf_mcounteren_ir_reg$D_IN, csrf_mcounteren_ir_reg$EN;
// register csrf_mcounteren_tm_reg
reg csrf_mcounteren_tm_reg;
wire csrf_mcounteren_tm_reg$D_IN, csrf_mcounteren_tm_reg$EN;
// register csrf_mcycle_ehr_data_rl
reg [63 : 0] csrf_mcycle_ehr_data_rl;
wire [63 : 0] csrf_mcycle_ehr_data_rl$D_IN;
wire csrf_mcycle_ehr_data_rl$EN;
// register csrf_medeleg_13_11_reg
reg [2 : 0] csrf_medeleg_13_11_reg;
wire [2 : 0] csrf_medeleg_13_11_reg$D_IN;
wire csrf_medeleg_13_11_reg$EN;
// register csrf_medeleg_15_reg
reg csrf_medeleg_15_reg;
wire csrf_medeleg_15_reg$D_IN, csrf_medeleg_15_reg$EN;
// register csrf_medeleg_9_0_reg
reg [9 : 0] csrf_medeleg_9_0_reg;
wire [9 : 0] csrf_medeleg_9_0_reg$D_IN;
wire csrf_medeleg_9_0_reg$EN;
// register csrf_mepc_csr
reg [63 : 0] csrf_mepc_csr;
reg [63 : 0] csrf_mepc_csr$D_IN;
wire csrf_mepc_csr$EN;
// register csrf_mideleg_11_reg
reg csrf_mideleg_11_reg;
wire csrf_mideleg_11_reg$D_IN, csrf_mideleg_11_reg$EN;
// register csrf_mideleg_1_0_reg
reg [1 : 0] csrf_mideleg_1_0_reg;
wire [1 : 0] csrf_mideleg_1_0_reg$D_IN;
wire csrf_mideleg_1_0_reg$EN;
// register csrf_mideleg_5_3_reg
reg [2 : 0] csrf_mideleg_5_3_reg;
wire [2 : 0] csrf_mideleg_5_3_reg$D_IN;
wire csrf_mideleg_5_3_reg$EN;
// register csrf_mideleg_9_7_reg
reg [2 : 0] csrf_mideleg_9_7_reg;
wire [2 : 0] csrf_mideleg_9_7_reg$D_IN;
wire csrf_mideleg_9_7_reg$EN;
// register csrf_minstret_ehr_data_rl
reg [63 : 0] csrf_minstret_ehr_data_rl;
wire [63 : 0] csrf_minstret_ehr_data_rl$D_IN;
wire csrf_minstret_ehr_data_rl$EN;
// register csrf_mpp_reg
reg [1 : 0] csrf_mpp_reg;
reg [1 : 0] csrf_mpp_reg$D_IN;
wire csrf_mpp_reg$EN;
// register csrf_mprv_reg
reg csrf_mprv_reg;
wire csrf_mprv_reg$D_IN, csrf_mprv_reg$EN;
// register csrf_mscratch_csr
reg [63 : 0] csrf_mscratch_csr;
wire [63 : 0] csrf_mscratch_csr$D_IN;
wire csrf_mscratch_csr$EN;
// register csrf_mtval_csr
reg [63 : 0] csrf_mtval_csr;
reg [63 : 0] csrf_mtval_csr$D_IN;
wire csrf_mtval_csr$EN;
// register csrf_mtvec_base_hi_reg
reg [61 : 0] csrf_mtvec_base_hi_reg;
wire [61 : 0] csrf_mtvec_base_hi_reg$D_IN;
wire csrf_mtvec_base_hi_reg$EN;
// register csrf_mtvec_mode_low_reg
reg csrf_mtvec_mode_low_reg;
wire csrf_mtvec_mode_low_reg$D_IN, csrf_mtvec_mode_low_reg$EN;
// register csrf_mxr_reg
reg csrf_mxr_reg;
wire csrf_mxr_reg$D_IN, csrf_mxr_reg$EN;
// register csrf_ppn_reg
reg [43 : 0] csrf_ppn_reg;
wire [43 : 0] csrf_ppn_reg$D_IN;
wire csrf_ppn_reg$EN;
// register csrf_prev_ie_vec_0
reg csrf_prev_ie_vec_0;
wire csrf_prev_ie_vec_0$D_IN, csrf_prev_ie_vec_0$EN;
// register csrf_prev_ie_vec_1
reg csrf_prev_ie_vec_1;
reg csrf_prev_ie_vec_1$D_IN;
wire csrf_prev_ie_vec_1$EN;
// register csrf_prev_ie_vec_3
reg csrf_prev_ie_vec_3;
reg csrf_prev_ie_vec_3$D_IN;
wire csrf_prev_ie_vec_3$EN;
// register csrf_prv_reg
reg [1 : 0] csrf_prv_reg;
reg [1 : 0] csrf_prv_reg$D_IN;
wire csrf_prv_reg$EN;
// register csrf_rg_dcsr
reg [63 : 0] csrf_rg_dcsr;
reg [63 : 0] csrf_rg_dcsr$D_IN;
wire csrf_rg_dcsr$EN;
// register csrf_rg_dpc
reg [63 : 0] csrf_rg_dpc;
reg [63 : 0] csrf_rg_dpc$D_IN;
wire csrf_rg_dpc$EN;
// register csrf_rg_dscratch0
reg [63 : 0] csrf_rg_dscratch0;
wire [63 : 0] csrf_rg_dscratch0$D_IN;
wire csrf_rg_dscratch0$EN;
// register csrf_rg_dscratch1
reg [63 : 0] csrf_rg_dscratch1;
wire [63 : 0] csrf_rg_dscratch1$D_IN;
wire csrf_rg_dscratch1$EN;
// register csrf_scause_code_reg
reg [3 : 0] csrf_scause_code_reg;
reg [3 : 0] csrf_scause_code_reg$D_IN;
wire csrf_scause_code_reg$EN;
// register csrf_scause_interrupt_reg
reg csrf_scause_interrupt_reg;
reg csrf_scause_interrupt_reg$D_IN;
wire csrf_scause_interrupt_reg$EN;
// register csrf_scounteren_cy_reg
reg csrf_scounteren_cy_reg;
wire csrf_scounteren_cy_reg$D_IN, csrf_scounteren_cy_reg$EN;
// register csrf_scounteren_ir_reg
reg csrf_scounteren_ir_reg;
wire csrf_scounteren_ir_reg$D_IN, csrf_scounteren_ir_reg$EN;
// register csrf_scounteren_tm_reg
reg csrf_scounteren_tm_reg;
wire csrf_scounteren_tm_reg$D_IN, csrf_scounteren_tm_reg$EN;
// register csrf_sepc_csr
reg [63 : 0] csrf_sepc_csr;
reg [63 : 0] csrf_sepc_csr$D_IN;
wire csrf_sepc_csr$EN;
// register csrf_software_int_en_vec_0
reg csrf_software_int_en_vec_0;
wire csrf_software_int_en_vec_0$D_IN, csrf_software_int_en_vec_0$EN;
// register csrf_software_int_en_vec_1
reg csrf_software_int_en_vec_1;
wire csrf_software_int_en_vec_1$D_IN, csrf_software_int_en_vec_1$EN;
// register csrf_software_int_en_vec_3
reg csrf_software_int_en_vec_3;
wire csrf_software_int_en_vec_3$D_IN, csrf_software_int_en_vec_3$EN;
// register csrf_software_int_pend_vec_0
reg csrf_software_int_pend_vec_0;
wire csrf_software_int_pend_vec_0$D_IN, csrf_software_int_pend_vec_0$EN;
// register csrf_software_int_pend_vec_1
reg csrf_software_int_pend_vec_1;
wire csrf_software_int_pend_vec_1$D_IN, csrf_software_int_pend_vec_1$EN;
// register csrf_software_int_pend_vec_3
reg csrf_software_int_pend_vec_3;
reg csrf_software_int_pend_vec_3$D_IN;
wire csrf_software_int_pend_vec_3$EN;
// register csrf_spp_reg
reg csrf_spp_reg;
reg csrf_spp_reg$D_IN;
wire csrf_spp_reg$EN;
// register csrf_sscratch_csr
reg [63 : 0] csrf_sscratch_csr;
wire [63 : 0] csrf_sscratch_csr$D_IN;
wire csrf_sscratch_csr$EN;
// register csrf_stats_module_doStats
reg csrf_stats_module_doStats;
wire csrf_stats_module_doStats$D_IN, csrf_stats_module_doStats$EN;
// register csrf_stval_csr
reg [63 : 0] csrf_stval_csr;
reg [63 : 0] csrf_stval_csr$D_IN;
wire csrf_stval_csr$EN;
// register csrf_stvec_base_hi_reg
reg [61 : 0] csrf_stvec_base_hi_reg;
wire [61 : 0] csrf_stvec_base_hi_reg$D_IN;
wire csrf_stvec_base_hi_reg$EN;
// register csrf_stvec_mode_low_reg
reg csrf_stvec_mode_low_reg;
wire csrf_stvec_mode_low_reg$D_IN, csrf_stvec_mode_low_reg$EN;
// register csrf_sum_reg
reg csrf_sum_reg;
wire csrf_sum_reg$D_IN, csrf_sum_reg$EN;
// register csrf_time_reg
reg [63 : 0] csrf_time_reg;
wire [63 : 0] csrf_time_reg$D_IN;
wire csrf_time_reg$EN;
// register csrf_timer_int_en_vec_0
reg csrf_timer_int_en_vec_0;
wire csrf_timer_int_en_vec_0$D_IN, csrf_timer_int_en_vec_0$EN;
// register csrf_timer_int_en_vec_1
reg csrf_timer_int_en_vec_1;
wire csrf_timer_int_en_vec_1$D_IN, csrf_timer_int_en_vec_1$EN;
// register csrf_timer_int_en_vec_3
reg csrf_timer_int_en_vec_3;
wire csrf_timer_int_en_vec_3$D_IN, csrf_timer_int_en_vec_3$EN;
// register csrf_timer_int_pend_vec_0
reg csrf_timer_int_pend_vec_0;
wire csrf_timer_int_pend_vec_0$D_IN, csrf_timer_int_pend_vec_0$EN;
// register csrf_timer_int_pend_vec_1
reg csrf_timer_int_pend_vec_1;
wire csrf_timer_int_pend_vec_1$D_IN, csrf_timer_int_pend_vec_1$EN;
// register csrf_timer_int_pend_vec_3
reg csrf_timer_int_pend_vec_3;
wire csrf_timer_int_pend_vec_3$D_IN, csrf_timer_int_pend_vec_3$EN;
// register csrf_tsr_reg
reg csrf_tsr_reg;
wire csrf_tsr_reg$D_IN, csrf_tsr_reg$EN;
// register csrf_tvm_reg
reg csrf_tvm_reg;
wire csrf_tvm_reg$D_IN, csrf_tvm_reg$EN;
// register csrf_tw_reg
reg csrf_tw_reg;
wire csrf_tw_reg$D_IN, csrf_tw_reg$EN;
// register csrf_vm_mode_sv39_reg
reg csrf_vm_mode_sv39_reg;
wire csrf_vm_mode_sv39_reg$D_IN, csrf_vm_mode_sv39_reg$EN;
// register flush_brpred
reg flush_brpred;
wire flush_brpred$D_IN, flush_brpred$EN;
// register flush_caches
reg flush_caches;
wire flush_caches$D_IN, flush_caches$EN;
// register flush_reservation
reg flush_reservation;
wire flush_reservation$D_IN, flush_reservation$EN;
// register flush_tlbs
reg flush_tlbs;
wire flush_tlbs$D_IN, flush_tlbs$EN;
// register mmio_cRqQ_clearReq_rl
reg mmio_cRqQ_clearReq_rl;
wire mmio_cRqQ_clearReq_rl$D_IN, mmio_cRqQ_clearReq_rl$EN;
// register mmio_cRqQ_data_0
reg [141 : 0] mmio_cRqQ_data_0;
wire [141 : 0] mmio_cRqQ_data_0$D_IN;
wire mmio_cRqQ_data_0$EN;
// register mmio_cRqQ_deqReq_rl
reg mmio_cRqQ_deqReq_rl;
wire mmio_cRqQ_deqReq_rl$D_IN, mmio_cRqQ_deqReq_rl$EN;
// register mmio_cRqQ_empty
reg mmio_cRqQ_empty;
wire mmio_cRqQ_empty$D_IN, mmio_cRqQ_empty$EN;
// register mmio_cRqQ_enqReq_rl
reg [142 : 0] mmio_cRqQ_enqReq_rl;
wire [142 : 0] mmio_cRqQ_enqReq_rl$D_IN;
wire mmio_cRqQ_enqReq_rl$EN;
// register mmio_cRqQ_full
reg mmio_cRqQ_full;
wire mmio_cRqQ_full$D_IN, mmio_cRqQ_full$EN;
// register mmio_cRsQ_clearReq_rl
reg mmio_cRsQ_clearReq_rl;
wire mmio_cRsQ_clearReq_rl$D_IN, mmio_cRsQ_clearReq_rl$EN;
// register mmio_cRsQ_data_0
reg mmio_cRsQ_data_0;
wire mmio_cRsQ_data_0$D_IN, mmio_cRsQ_data_0$EN;
// register mmio_cRsQ_deqReq_rl
reg mmio_cRsQ_deqReq_rl;
wire mmio_cRsQ_deqReq_rl$D_IN, mmio_cRsQ_deqReq_rl$EN;
// register mmio_cRsQ_empty
reg mmio_cRsQ_empty;
wire mmio_cRsQ_empty$D_IN, mmio_cRsQ_empty$EN;
// register mmio_cRsQ_enqReq_rl
reg [1 : 0] mmio_cRsQ_enqReq_rl;
wire [1 : 0] mmio_cRsQ_enqReq_rl$D_IN;
wire mmio_cRsQ_enqReq_rl$EN;
// register mmio_cRsQ_full
reg mmio_cRsQ_full;
wire mmio_cRsQ_full$D_IN, mmio_cRsQ_full$EN;
// register mmio_dataPendQ_clearReq_rl
reg mmio_dataPendQ_clearReq_rl;
wire mmio_dataPendQ_clearReq_rl$D_IN, mmio_dataPendQ_clearReq_rl$EN;
// register mmio_dataPendQ_deqReq_rl
reg mmio_dataPendQ_deqReq_rl;
wire mmio_dataPendQ_deqReq_rl$D_IN, mmio_dataPendQ_deqReq_rl$EN;
// register mmio_dataPendQ_empty
reg mmio_dataPendQ_empty;
wire mmio_dataPendQ_empty$D_IN, mmio_dataPendQ_empty$EN;
// register mmio_dataPendQ_enqReq_rl
reg mmio_dataPendQ_enqReq_rl;
wire mmio_dataPendQ_enqReq_rl$D_IN, mmio_dataPendQ_enqReq_rl$EN;
// register mmio_dataPendQ_full
reg mmio_dataPendQ_full;
wire mmio_dataPendQ_full$D_IN, mmio_dataPendQ_full$EN;
// register mmio_dataReqQ_clearReq_rl
reg mmio_dataReqQ_clearReq_rl;
wire mmio_dataReqQ_clearReq_rl$D_IN, mmio_dataReqQ_clearReq_rl$EN;
// register mmio_dataReqQ_data_0
reg [141 : 0] mmio_dataReqQ_data_0;
wire [141 : 0] mmio_dataReqQ_data_0$D_IN;
wire mmio_dataReqQ_data_0$EN;
// register mmio_dataReqQ_deqReq_rl
reg mmio_dataReqQ_deqReq_rl;
wire mmio_dataReqQ_deqReq_rl$D_IN, mmio_dataReqQ_deqReq_rl$EN;
// register mmio_dataReqQ_empty
reg mmio_dataReqQ_empty;
wire mmio_dataReqQ_empty$D_IN, mmio_dataReqQ_empty$EN;
// register mmio_dataReqQ_enqReq_rl
reg [142 : 0] mmio_dataReqQ_enqReq_rl;
wire [142 : 0] mmio_dataReqQ_enqReq_rl$D_IN;
wire mmio_dataReqQ_enqReq_rl$EN;
// register mmio_dataReqQ_full
reg mmio_dataReqQ_full;
wire mmio_dataReqQ_full$D_IN, mmio_dataReqQ_full$EN;
// register mmio_dataRespQ_clearReq_rl
reg mmio_dataRespQ_clearReq_rl;
wire mmio_dataRespQ_clearReq_rl$D_IN, mmio_dataRespQ_clearReq_rl$EN;
// register mmio_dataRespQ_data_0
reg [64 : 0] mmio_dataRespQ_data_0;
wire [64 : 0] mmio_dataRespQ_data_0$D_IN;
wire mmio_dataRespQ_data_0$EN;
// register mmio_dataRespQ_deqReq_rl
reg mmio_dataRespQ_deqReq_rl;
wire mmio_dataRespQ_deqReq_rl$D_IN, mmio_dataRespQ_deqReq_rl$EN;
// register mmio_dataRespQ_empty
reg mmio_dataRespQ_empty;
wire mmio_dataRespQ_empty$D_IN, mmio_dataRespQ_empty$EN;
// register mmio_dataRespQ_enqReq_rl
reg [65 : 0] mmio_dataRespQ_enqReq_rl;
wire [65 : 0] mmio_dataRespQ_enqReq_rl$D_IN;
wire mmio_dataRespQ_enqReq_rl$EN;
// register mmio_dataRespQ_full
reg mmio_dataRespQ_full;
wire mmio_dataRespQ_full$D_IN, mmio_dataRespQ_full$EN;
// register mmio_fromHostAddr
reg [60 : 0] mmio_fromHostAddr;
wire [60 : 0] mmio_fromHostAddr$D_IN;
wire mmio_fromHostAddr$EN;
// register mmio_pRqQ_clearReq_rl
reg mmio_pRqQ_clearReq_rl;
wire mmio_pRqQ_clearReq_rl$D_IN, mmio_pRqQ_clearReq_rl$EN;
// register mmio_pRqQ_data_0
reg [38 : 0] mmio_pRqQ_data_0;
wire [38 : 0] mmio_pRqQ_data_0$D_IN;
wire mmio_pRqQ_data_0$EN;
// register mmio_pRqQ_deqReq_rl
reg mmio_pRqQ_deqReq_rl;
wire mmio_pRqQ_deqReq_rl$D_IN, mmio_pRqQ_deqReq_rl$EN;
// register mmio_pRqQ_empty
reg mmio_pRqQ_empty;
wire mmio_pRqQ_empty$D_IN, mmio_pRqQ_empty$EN;
// register mmio_pRqQ_enqReq_rl
reg [39 : 0] mmio_pRqQ_enqReq_rl;
wire [39 : 0] mmio_pRqQ_enqReq_rl$D_IN;
wire mmio_pRqQ_enqReq_rl$EN;
// register mmio_pRqQ_full
reg mmio_pRqQ_full;
wire mmio_pRqQ_full$D_IN, mmio_pRqQ_full$EN;
// register mmio_pRsQ_clearReq_rl
reg mmio_pRsQ_clearReq_rl;
wire mmio_pRsQ_clearReq_rl$D_IN, mmio_pRsQ_clearReq_rl$EN;
// register mmio_pRsQ_data_0
reg [66 : 0] mmio_pRsQ_data_0;
wire [66 : 0] mmio_pRsQ_data_0$D_IN;
wire mmio_pRsQ_data_0$EN;
// register mmio_pRsQ_deqReq_rl
reg mmio_pRsQ_deqReq_rl;
wire mmio_pRsQ_deqReq_rl$D_IN, mmio_pRsQ_deqReq_rl$EN;
// register mmio_pRsQ_empty
reg mmio_pRsQ_empty;
wire mmio_pRsQ_empty$D_IN, mmio_pRsQ_empty$EN;
// register mmio_pRsQ_enqReq_rl
reg [67 : 0] mmio_pRsQ_enqReq_rl;
wire [67 : 0] mmio_pRsQ_enqReq_rl$D_IN;
wire mmio_pRsQ_enqReq_rl$EN;
// register mmio_pRsQ_full
reg mmio_pRsQ_full;
wire mmio_pRsQ_full$D_IN, mmio_pRsQ_full$EN;
// register mmio_toHostAddr
reg [60 : 0] mmio_toHostAddr;
wire [60 : 0] mmio_toHostAddr$D_IN;
wire mmio_toHostAddr$EN;
// register outOfReset
reg outOfReset;
wire outOfReset$D_IN, outOfReset$EN;
// register renameStage_rg_m_halt_req
reg [4 : 0] renameStage_rg_m_halt_req;
reg [4 : 0] renameStage_rg_m_halt_req$D_IN;
wire renameStage_rg_m_halt_req$EN;
// register rg_core_run_state
reg [1 : 0] rg_core_run_state;
reg [1 : 0] rg_core_run_state$D_IN;
wire rg_core_run_state$EN;
// register started
reg started;
wire started$D_IN, started$EN;
// register update_vm_info
reg update_vm_info;
wire update_vm_info$D_IN, update_vm_info$EN;
// ports of submodule commitStage_f_rob_data
wire [353 : 0] commitStage_f_rob_data$D_IN, commitStage_f_rob_data$D_OUT;
wire commitStage_f_rob_data$CLR,
commitStage_f_rob_data$DEQ,
commitStage_f_rob_data$EMPTY_N,
commitStage_f_rob_data$ENQ,
commitStage_f_rob_data$FULL_N;
// ports of submodule coreFix_aluExe_0_dispToRegQ
reg [3 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [157 : 0] coreFix_aluExe_0_dispToRegQ$enq_x,
coreFix_aluExe_0_dispToRegQ$first;
wire [11 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_dispToRegQ$EN_deq,
coreFix_aluExe_0_dispToRegQ$EN_enq,
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_dispToRegQ$RDY_deq,
coreFix_aluExe_0_dispToRegQ$RDY_enq,
coreFix_aluExe_0_dispToRegQ$RDY_first,
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_exeToFinQ
reg [3 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
wire [326 : 0] coreFix_aluExe_0_exeToFinQ$enq_x,
coreFix_aluExe_0_exeToFinQ$first;
wire [11 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_exeToFinQ$EN_deq,
coreFix_aluExe_0_exeToFinQ$EN_enq,
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_exeToFinQ$RDY_deq,
coreFix_aluExe_0_exeToFinQ$RDY_enq,
coreFix_aluExe_0_exeToFinQ$RDY_first,
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_regToExeQ
reg [3 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [421 : 0] coreFix_aluExe_0_regToExeQ$enq_x,
coreFix_aluExe_0_regToExeQ$first;
wire [11 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_regToExeQ$EN_deq,
coreFix_aluExe_0_regToExeQ$EN_enq,
coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_regToExeQ$RDY_deq,
coreFix_aluExe_0_regToExeQ$RDY_enq,
coreFix_aluExe_0_regToExeQ$RDY_first,
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_rsAlu
reg [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_2_put,
coreFix_aluExe_0_rsAlu$setRegReady_4_put;
reg [3 : 0] coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
wire [161 : 0] coreFix_aluExe_0_rsAlu$dispatchData,
coreFix_aluExe_0_rsAlu$enq_x;
wire [11 : 0] coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_0_put,
coreFix_aluExe_0_rsAlu$setRegReady_1_put,
coreFix_aluExe_0_rsAlu$setRegReady_3_put;
wire [5 : 0] coreFix_aluExe_0_rsAlu$setRobEnqTime_t;
wire [4 : 0] coreFix_aluExe_0_rsAlu$approximateCount;
wire coreFix_aluExe_0_rsAlu$EN_doDispatch,
coreFix_aluExe_0_rsAlu$EN_enq,
coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put,
coreFix_aluExe_0_rsAlu$EN_setRobEnqTime,
coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_rsAlu$RDY_dispatchData,
coreFix_aluExe_0_rsAlu$RDY_doDispatch,
coreFix_aluExe_0_rsAlu$RDY_enq,
coreFix_aluExe_0_rsAlu$canEnq,
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_dispToRegQ
reg [3 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [157 : 0] coreFix_aluExe_1_dispToRegQ$enq_x,
coreFix_aluExe_1_dispToRegQ$first;
wire [11 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_dispToRegQ$EN_deq,
coreFix_aluExe_1_dispToRegQ$EN_enq,
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_dispToRegQ$RDY_deq,
coreFix_aluExe_1_dispToRegQ$RDY_enq,
coreFix_aluExe_1_dispToRegQ$RDY_first,
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_exeToFinQ
reg [3 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
wire [326 : 0] coreFix_aluExe_1_exeToFinQ$enq_x,
coreFix_aluExe_1_exeToFinQ$first;
wire [11 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_exeToFinQ$EN_deq,
coreFix_aluExe_1_exeToFinQ$EN_enq,
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_exeToFinQ$RDY_deq,
coreFix_aluExe_1_exeToFinQ$RDY_enq,
coreFix_aluExe_1_exeToFinQ$RDY_first,
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_regToExeQ
reg [3 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [421 : 0] coreFix_aluExe_1_regToExeQ$enq_x,
coreFix_aluExe_1_regToExeQ$first;
wire [11 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_regToExeQ$EN_deq,
coreFix_aluExe_1_regToExeQ$EN_enq,
coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_regToExeQ$RDY_deq,
coreFix_aluExe_1_regToExeQ$RDY_enq,
coreFix_aluExe_1_regToExeQ$RDY_first,
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_rsAlu
reg [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_2_put,
coreFix_aluExe_1_rsAlu$setRegReady_4_put;
reg [3 : 0] coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
wire [161 : 0] coreFix_aluExe_1_rsAlu$dispatchData,
coreFix_aluExe_1_rsAlu$enq_x;
wire [11 : 0] coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_0_put,
coreFix_aluExe_1_rsAlu$setRegReady_1_put,
coreFix_aluExe_1_rsAlu$setRegReady_3_put;
wire [5 : 0] coreFix_aluExe_1_rsAlu$setRobEnqTime_t;
wire [4 : 0] coreFix_aluExe_1_rsAlu$approximateCount;
wire coreFix_aluExe_1_rsAlu$EN_doDispatch,
coreFix_aluExe_1_rsAlu$EN_enq,
coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put,
coreFix_aluExe_1_rsAlu$EN_setRobEnqTime,
coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_rsAlu$RDY_dispatchData,
coreFix_aluExe_1_rsAlu$RDY_doDispatch,
coreFix_aluExe_1_rsAlu$RDY_enq,
coreFix_aluExe_1_rsAlu$canEnq,
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_dispToRegQ
reg [3 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [77 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x,
coreFix_fpuMulDivExe_0_dispToRegQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first,
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
wire [130 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put;
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get;
wire coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
wire [195 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put;
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get;
wire coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get;
wire [66 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put;
wire coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag;
wire [101 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
wire [139 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
wire [203 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag;
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
reg [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN;
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ;
// ports of submodule coreFix_fpuMulDivExe_0_regToExeQ
reg [3 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [245 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x,
coreFix_fpuMulDivExe_0_regToExeQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_regToExeQ$EN_deq,
coreFix_fpuMulDivExe_0_regToExeQ$EN_enq,
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first,
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
reg [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put;
reg [3 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag;
wire [86 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x;
wire [11 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put;
wire [5 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t;
wire coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n;
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData;
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq;
wire [63 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr;
wire [57 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData;
wire [65 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq;
wire [1 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n;
wire coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r;
reg [569 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam;
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq;
reg coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first;
wire coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dTlb
reg [3 : 0] coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag;
wire [174 : 0] coreFix_memExe_dTlb$procResp;
wire [105 : 0] coreFix_memExe_dTlb$procReq_req;
wire [82 : 0] coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x;
wire [48 : 0] coreFix_memExe_dTlb$updateVMInfo_vm;
wire [28 : 0] coreFix_memExe_dTlb$toParent_rqToP_first;
wire [11 : 0] coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask;
wire [2 : 0] coreFix_memExe_dTlb$perf_req_r;
wire coreFix_memExe_dTlb$EN_deqProcResp,
coreFix_memExe_dTlb$EN_flush,
coreFix_memExe_dTlb$EN_perf_req,
coreFix_memExe_dTlb$EN_perf_resp,
coreFix_memExe_dTlb$EN_perf_setStatus,
coreFix_memExe_dTlb$EN_procReq,
coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation,
coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_dTlb$EN_toParent_flush_request_get,
coreFix_memExe_dTlb$EN_toParent_flush_response_put,
coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq,
coreFix_memExe_dTlb$EN_toParent_rqToP_deq,
coreFix_memExe_dTlb$EN_updateVMInfo,
coreFix_memExe_dTlb$RDY_deqProcResp,
coreFix_memExe_dTlb$RDY_flush,
coreFix_memExe_dTlb$RDY_procReq,
coreFix_memExe_dTlb$RDY_procResp,
coreFix_memExe_dTlb$RDY_toParent_flush_request_get,
coreFix_memExe_dTlb$RDY_toParent_flush_response_put,
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq,
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq,
coreFix_memExe_dTlb$RDY_toParent_rqToP_first,
coreFix_memExe_dTlb$flush_done,
coreFix_memExe_dTlb$noPendingReq,
coreFix_memExe_dTlb$perf_setStatus_doStats,
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_dispToRegQ
reg [3 : 0] coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [97 : 0] coreFix_memExe_dispToRegQ$enq_x,
coreFix_memExe_dispToRegQ$first;
wire [11 : 0] coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_memExe_dispToRegQ$EN_deq,
coreFix_memExe_dispToRegQ$EN_enq,
coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_dispToRegQ$RDY_deq,
coreFix_memExe_dispToRegQ$RDY_enq,
coreFix_memExe_dispToRegQ$RDY_first,
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
wire coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
wire coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_clearReq_dummy2_1$EN,
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
wire coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
wire coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
wire coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_2$EN,
coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
wire coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
wire coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
wire coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_2$EN,
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_lsq
reg [3 : 0] coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag;
wire [170 : 0] coreFix_memExe_lsq$firstSt;
wire [113 : 0] coreFix_memExe_lsq$firstLd;
wire [85 : 0] coreFix_memExe_lsq$respLd;
wire [76 : 0] coreFix_memExe_lsq$getIssueLd;
wire [74 : 0] coreFix_memExe_lsq$issueLd;
wire [67 : 0] coreFix_memExe_lsq$issueLd_sbRes;
wire [63 : 0] coreFix_memExe_lsq$issueLd_paddr,
coreFix_memExe_lsq$respLd_alignedData,
coreFix_memExe_lsq$updateAddr_paddr,
coreFix_memExe_lsq$updateData_d;
wire [17 : 0] coreFix_memExe_lsq$enqLd_mem_inst,
coreFix_memExe_lsq$enqSt_mem_inst;
wire [11 : 0] coreFix_memExe_lsq$enqLd_inst_tag,
coreFix_memExe_lsq$enqLd_spec_bits,
coreFix_memExe_lsq$enqSt_inst_tag,
coreFix_memExe_lsq$enqSt_spec_bits,
coreFix_memExe_lsq$specUpdate_correctSpeculation_mask;
wire [9 : 0] coreFix_memExe_lsq$getHit;
wire [8 : 0] coreFix_memExe_lsq$enqLd_dst, coreFix_memExe_lsq$enqSt_dst;
wire [7 : 0] coreFix_memExe_lsq$getOrigBE,
coreFix_memExe_lsq$issueLd_shiftedBE,
coreFix_memExe_lsq$updateAddr_shiftedBE;
wire [6 : 0] coreFix_memExe_lsq$enqLdTag, coreFix_memExe_lsq$enqStTag;
wire [5 : 0] coreFix_memExe_lsq$getHit_t,
coreFix_memExe_lsq$getOrigBE_t,
coreFix_memExe_lsq$setAtCommit_0_put,
coreFix_memExe_lsq$setAtCommit_1_put,
coreFix_memExe_lsq$updateAddr_lsqTag;
wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag,
coreFix_memExe_lsq$respLd_t,
coreFix_memExe_lsq$updateAddr_fault;
wire [3 : 0] coreFix_memExe_lsq$updateData_t;
wire [1 : 0] coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx;
wire coreFix_memExe_lsq$EN_deqLd,
coreFix_memExe_lsq$EN_deqSt,
coreFix_memExe_lsq$EN_enqLd,
coreFix_memExe_lsq$EN_enqSt,
coreFix_memExe_lsq$EN_getHit,
coreFix_memExe_lsq$EN_getIssueLd,
coreFix_memExe_lsq$EN_issueLd,
coreFix_memExe_lsq$EN_respLd,
coreFix_memExe_lsq$EN_setAtCommit_0_put,
coreFix_memExe_lsq$EN_setAtCommit_1_put,
coreFix_memExe_lsq$EN_specUpdate_correctSpeculation,
coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_lsq$EN_updateAddr,
coreFix_memExe_lsq$EN_updateData,
coreFix_memExe_lsq$EN_wakeupLdStalledBySB,
coreFix_memExe_lsq$RDY_deqLd,
coreFix_memExe_lsq$RDY_deqSt,
coreFix_memExe_lsq$RDY_enqLd,
coreFix_memExe_lsq$RDY_enqSt,
coreFix_memExe_lsq$RDY_firstLd,
coreFix_memExe_lsq$RDY_firstSt,
coreFix_memExe_lsq$RDY_getIssueLd,
coreFix_memExe_lsq$noWrongPathLoads,
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all,
coreFix_memExe_lsq$stqEmpty,
coreFix_memExe_lsq$updateAddr,
coreFix_memExe_lsq$updateAddr_isMMIO;
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_regToExeQ
reg [3 : 0] coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [192 : 0] coreFix_memExe_regToExeQ$enq_x,
coreFix_memExe_regToExeQ$first;
wire [11 : 0] coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_memExe_regToExeQ$EN_deq,
coreFix_memExe_regToExeQ$EN_enq,
coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_regToExeQ$RDY_deq,
coreFix_memExe_regToExeQ$RDY_enq,
coreFix_memExe_regToExeQ$RDY_first,
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
wire coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
wire coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_data_0_dummy2_1$EN,
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
wire coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
wire coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_0
wire coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_1
wire coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_1$EN,
coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_2
wire coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_2$EN,
coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
wire coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
wire coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_0
wire coreFix_memExe_reqLdQ_full_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_0$EN,
coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_1
wire coreFix_memExe_reqLdQ_full_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_1$EN,
coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_2
wire coreFix_memExe_reqLdQ_full_dummy2_2$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_2$EN,
coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_0
wire coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqStQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_1
wire coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqStQ_data_0_dummy2_1$EN,
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_0
wire coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqStQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_1
wire coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqStQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_0
wire coreFix_memExe_reqStQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_1
wire coreFix_memExe_reqStQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_1$EN,
coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_2
wire coreFix_memExe_reqStQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_2$EN,
coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_0
wire coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqStQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_1
wire coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqStQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_0
wire coreFix_memExe_reqStQ_full_dummy2_0$D_IN,
coreFix_memExe_reqStQ_full_dummy2_0$EN,
coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_1
wire coreFix_memExe_reqStQ_full_dummy2_1$D_IN,
coreFix_memExe_reqStQ_full_dummy2_1$EN,
coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_2
wire coreFix_memExe_reqStQ_full_dummy2_2$D_IN,
coreFix_memExe_reqStQ_full_dummy2_2$EN,
coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_rsMem
reg [7 : 0] coreFix_memExe_rsMem$setRegReady_2_put,
coreFix_memExe_rsMem$setRegReady_4_put;
reg [3 : 0] coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag;
wire [106 : 0] coreFix_memExe_rsMem$dispatchData,
coreFix_memExe_rsMem$enq_x;
wire [11 : 0] coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_memExe_rsMem$setRegReady_0_put,
coreFix_memExe_rsMem$setRegReady_1_put,
coreFix_memExe_rsMem$setRegReady_3_put;
wire [5 : 0] coreFix_memExe_rsMem$setRobEnqTime_t;
wire coreFix_memExe_rsMem$EN_doDispatch,
coreFix_memExe_rsMem$EN_enq,
coreFix_memExe_rsMem$EN_setRegReady_0_put,
coreFix_memExe_rsMem$EN_setRegReady_1_put,
coreFix_memExe_rsMem$EN_setRegReady_2_put,
coreFix_memExe_rsMem$EN_setRegReady_3_put,
coreFix_memExe_rsMem$EN_setRegReady_4_put,
coreFix_memExe_rsMem$EN_setRobEnqTime,
coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation,
coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_rsMem$RDY_dispatchData,
coreFix_memExe_rsMem$RDY_doDispatch,
coreFix_memExe_rsMem$RDY_enq,
coreFix_memExe_rsMem$canEnq,
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_stb
wire [635 : 0] coreFix_memExe_stb$issue;
wire [633 : 0] coreFix_memExe_stb$deq;
wire [67 : 0] coreFix_memExe_stb$search;
wire [63 : 0] coreFix_memExe_stb$enq_data,
coreFix_memExe_stb$enq_paddr,
coreFix_memExe_stb$getEnqIndex_paddr,
coreFix_memExe_stb$noMatchLdQ_paddr,
coreFix_memExe_stb$noMatchStQ_paddr,
coreFix_memExe_stb$search_paddr;
wire [7 : 0] coreFix_memExe_stb$enq_be,
coreFix_memExe_stb$noMatchLdQ_be,
coreFix_memExe_stb$noMatchStQ_be,
coreFix_memExe_stb$search_be;
wire [2 : 0] coreFix_memExe_stb$getEnqIndex;
wire [1 : 0] coreFix_memExe_stb$deq_idx, coreFix_memExe_stb$enq_idx;
wire coreFix_memExe_stb$EN_deq,
coreFix_memExe_stb$EN_enq,
coreFix_memExe_stb$EN_issue,
coreFix_memExe_stb$RDY_deq,
coreFix_memExe_stb$RDY_enq,
coreFix_memExe_stb$RDY_issue,
coreFix_memExe_stb$isEmpty,
coreFix_memExe_stb$noMatchLdQ,
coreFix_memExe_stb$noMatchStQ;
// ports of submodule coreFix_trainBPQ_0
wire [159 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT;
wire coreFix_trainBPQ_0$CLR,
coreFix_trainBPQ_0$DEQ,
coreFix_trainBPQ_0$EMPTY_N,
coreFix_trainBPQ_0$ENQ,
coreFix_trainBPQ_0$FULL_N;
// ports of submodule coreFix_trainBPQ_1
wire [159 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT;
wire coreFix_trainBPQ_1$CLR,
coreFix_trainBPQ_1$DEQ,
coreFix_trainBPQ_1$EMPTY_N,
coreFix_trainBPQ_1$ENQ,
coreFix_trainBPQ_1$FULL_N;
// ports of submodule csrInstOrInterruptInflight_dummy2_0
wire csrInstOrInterruptInflight_dummy2_0$D_IN,
csrInstOrInterruptInflight_dummy2_0$EN,
csrInstOrInterruptInflight_dummy2_0$Q_OUT;
// ports of submodule csrInstOrInterruptInflight_dummy2_1
wire csrInstOrInterruptInflight_dummy2_1$D_IN,
csrInstOrInterruptInflight_dummy2_1$EN,
csrInstOrInterruptInflight_dummy2_1$Q_OUT;
// ports of submodule csrf_mcycle_ehr_data_dummy2_0
wire csrf_mcycle_ehr_data_dummy2_0$D_IN,
csrf_mcycle_ehr_data_dummy2_0$EN,
csrf_mcycle_ehr_data_dummy2_0$Q_OUT;
// ports of submodule csrf_mcycle_ehr_data_dummy2_1
wire csrf_mcycle_ehr_data_dummy2_1$D_IN,
csrf_mcycle_ehr_data_dummy2_1$EN,
csrf_mcycle_ehr_data_dummy2_1$Q_OUT;
// ports of submodule csrf_minstret_ehr_data_dummy2_0
wire csrf_minstret_ehr_data_dummy2_0$D_IN,
csrf_minstret_ehr_data_dummy2_0$EN,
csrf_minstret_ehr_data_dummy2_0$Q_OUT;
// ports of submodule csrf_minstret_ehr_data_dummy2_1
wire csrf_minstret_ehr_data_dummy2_1$D_IN,
csrf_minstret_ehr_data_dummy2_1$EN,
csrf_minstret_ehr_data_dummy2_1$Q_OUT;
// ports of submodule csrf_stats_module_writeQ
wire csrf_stats_module_writeQ$CLR,
csrf_stats_module_writeQ$DEQ,
csrf_stats_module_writeQ$D_IN,
csrf_stats_module_writeQ$D_OUT,
csrf_stats_module_writeQ$EMPTY_N,
csrf_stats_module_writeQ$ENQ,
csrf_stats_module_writeQ$FULL_N;
// ports of submodule csrf_terminate_module_terminateQ
wire csrf_terminate_module_terminateQ$CLR,
csrf_terminate_module_terminateQ$DEQ,
csrf_terminate_module_terminateQ$EMPTY_N,
csrf_terminate_module_terminateQ$ENQ,
csrf_terminate_module_terminateQ$FULL_N;
// ports of submodule epochManager
wire [3 : 0] epochManager$checkEpoch_0_check_e,
epochManager$checkEpoch_1_check_e,
epochManager$updatePrevEpoch_0_update_e,
epochManager$updatePrevEpoch_1_update_e;
wire epochManager$EN_incrementEpoch,
epochManager$EN_updatePrevEpoch_0_update,
epochManager$EN_updatePrevEpoch_1_update,
epochManager$RDY_incrementEpoch,
epochManager$checkEpoch_0_check,
epochManager$checkEpoch_1_check;
// ports of submodule f_csr_reqs
wire [76 : 0] f_csr_reqs$D_IN, f_csr_reqs$D_OUT;
wire f_csr_reqs$CLR,
f_csr_reqs$DEQ,
f_csr_reqs$EMPTY_N,
f_csr_reqs$ENQ,
f_csr_reqs$FULL_N;
// ports of submodule f_csr_rsps
reg [64 : 0] f_csr_rsps$D_IN;
wire [64 : 0] f_csr_rsps$D_OUT;
wire f_csr_rsps$CLR,
f_csr_rsps$DEQ,
f_csr_rsps$EMPTY_N,
f_csr_rsps$ENQ,
f_csr_rsps$FULL_N;
// ports of submodule f_fpr_reqs
wire [69 : 0] f_fpr_reqs$D_IN, f_fpr_reqs$D_OUT;
wire f_fpr_reqs$CLR,
f_fpr_reqs$DEQ,
f_fpr_reqs$EMPTY_N,
f_fpr_reqs$ENQ,
f_fpr_reqs$FULL_N;
// ports of submodule f_fpr_rsps
reg [64 : 0] f_fpr_rsps$D_IN;
wire [64 : 0] f_fpr_rsps$D_OUT;
wire f_fpr_rsps$CLR,
f_fpr_rsps$DEQ,
f_fpr_rsps$EMPTY_N,
f_fpr_rsps$ENQ,
f_fpr_rsps$FULL_N;
// ports of submodule f_gpr_reqs
wire [69 : 0] f_gpr_reqs$D_IN, f_gpr_reqs$D_OUT;
wire f_gpr_reqs$CLR,
f_gpr_reqs$DEQ,
f_gpr_reqs$EMPTY_N,
f_gpr_reqs$ENQ,
f_gpr_reqs$FULL_N;
// ports of submodule f_gpr_rsps
reg [64 : 0] f_gpr_rsps$D_IN;
wire [64 : 0] f_gpr_rsps$D_OUT;
wire f_gpr_rsps$CLR,
f_gpr_rsps$DEQ,
f_gpr_rsps$EMPTY_N,
f_gpr_rsps$ENQ,
f_gpr_rsps$FULL_N;
// ports of submodule f_run_halt_reqs
wire f_run_halt_reqs$CLR,
f_run_halt_reqs$DEQ,
f_run_halt_reqs$D_IN,
f_run_halt_reqs$D_OUT,
f_run_halt_reqs$EMPTY_N,
f_run_halt_reqs$ENQ,
f_run_halt_reqs$FULL_N;
// ports of submodule f_run_halt_rsps
wire f_run_halt_rsps$CLR,
f_run_halt_rsps$DEQ,
f_run_halt_rsps$D_IN,
f_run_halt_rsps$D_OUT,
f_run_halt_rsps$EMPTY_N,
f_run_halt_rsps$ENQ,
f_run_halt_rsps$FULL_N;
// ports of submodule fetchStage
reg [63 : 0] fetchStage$redirect_pc;
wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x;
wire [578 : 0] fetchStage$iMemIfc_to_parent_rsToP_first;
wire [387 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first;
wire [80 : 0] fetchStage$iTlbIfc_toParent_rsFromP_enq_x;
wire [71 : 0] fetchStage$iMemIfc_to_parent_rqToP_first;
wire [67 : 0] fetchStage$iMemIfc_cRqStuck_get,
fetchStage$iMemIfc_pRqStuck_get;
wire [65 : 0] fetchStage$mmioIfc_instResp_enq_x;
wire [63 : 0] fetchStage$iMemIfc_to_proc_request_put,
fetchStage$iTlbIfc_to_proc_request_put,
fetchStage$mmioIfc_instReq_first_fst,
fetchStage$mmioIfc_setHtifAddrs_fromHost,
fetchStage$mmioIfc_setHtifAddrs_toHost,
fetchStage$start_pc,
fetchStage$train_predictors_next_pc,
fetchStage$train_predictors_pc;
wire [48 : 0] fetchStage$iTlbIfc_updateVMInfo_vm;
wire [26 : 0] fetchStage$iTlbIfc_toParent_rqToP_first;
wire [23 : 0] fetchStage$train_predictors_dpTrain;
wire [4 : 0] fetchStage$train_predictors_iType;
wire [2 : 0] fetchStage$iTlbIfc_perf_req_r;
wire [1 : 0] fetchStage$iMemIfc_perf_req_r, fetchStage$perf_req_r;
wire fetchStage$EN_done_flushing,
fetchStage$EN_flush_predictors,
fetchStage$EN_iMemIfc_cRqStuck_get,
fetchStage$EN_iMemIfc_flush,
fetchStage$EN_iMemIfc_pRqStuck_get,
fetchStage$EN_iMemIfc_perf_req,
fetchStage$EN_iMemIfc_perf_resp,
fetchStage$EN_iMemIfc_perf_setStatus,
fetchStage$EN_iMemIfc_to_parent_fromP_enq,
fetchStage$EN_iMemIfc_to_parent_rqToP_deq,
fetchStage$EN_iMemIfc_to_parent_rsToP_deq,
fetchStage$EN_iMemIfc_to_proc_request_put,
fetchStage$EN_iMemIfc_to_proc_response_get,
fetchStage$EN_iTlbIfc_flush,
fetchStage$EN_iTlbIfc_perf_req,
fetchStage$EN_iTlbIfc_perf_resp,
fetchStage$EN_iTlbIfc_perf_setStatus,
fetchStage$EN_iTlbIfc_toParent_flush_request_get,
fetchStage$EN_iTlbIfc_toParent_flush_response_put,
fetchStage$EN_iTlbIfc_toParent_rqToP_deq,
fetchStage$EN_iTlbIfc_toParent_rsFromP_enq,
fetchStage$EN_iTlbIfc_to_proc_request_put,
fetchStage$EN_iTlbIfc_to_proc_response_get,
fetchStage$EN_iTlbIfc_updateVMInfo,
fetchStage$EN_mmioIfc_instReq_deq,
fetchStage$EN_mmioIfc_instResp_enq,
fetchStage$EN_mmioIfc_setHtifAddrs,
fetchStage$EN_perf_req,
fetchStage$EN_perf_resp,
fetchStage$EN_perf_setStatus,
fetchStage$EN_pipelines_0_deq,
fetchStage$EN_pipelines_1_deq,
fetchStage$EN_redirect,
fetchStage$EN_setWaitFlush,
fetchStage$EN_setWaitRedirect,
fetchStage$EN_start,
fetchStage$EN_stop,
fetchStage$EN_train_predictors,
fetchStage$RDY_done_flushing,
fetchStage$RDY_iMemIfc_cRqStuck_get,
fetchStage$RDY_iMemIfc_pRqStuck_get,
fetchStage$RDY_iMemIfc_to_parent_fromP_enq,
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq,
fetchStage$RDY_iMemIfc_to_parent_rqToP_first,
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq,
fetchStage$RDY_iMemIfc_to_parent_rsToP_first,
fetchStage$RDY_iTlbIfc_flush,
fetchStage$RDY_iTlbIfc_toParent_flush_request_get,
fetchStage$RDY_iTlbIfc_toParent_flush_response_put,
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq,
fetchStage$RDY_iTlbIfc_toParent_rqToP_first,
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq,
fetchStage$RDY_mmioIfc_instReq_deq,
fetchStage$RDY_mmioIfc_instReq_first_fst,
fetchStage$RDY_mmioIfc_instReq_first_snd,
fetchStage$RDY_mmioIfc_instResp_enq,
fetchStage$RDY_pipelines_0_deq,
fetchStage$RDY_pipelines_0_first,
fetchStage$RDY_pipelines_1_deq,
fetchStage$RDY_pipelines_1_first,
fetchStage$emptyForFlush,
fetchStage$flush_predictors_done,
fetchStage$iMemIfc_flush_done,
fetchStage$iMemIfc_perf_setStatus_doStats,
fetchStage$iMemIfc_to_parent_fromP_notFull,
fetchStage$iMemIfc_to_parent_rqToP_notEmpty,
fetchStage$iMemIfc_to_parent_rsToP_notEmpty,
fetchStage$iTlbIfc_flush_done,
fetchStage$iTlbIfc_noPendingReq,
fetchStage$iTlbIfc_perf_setStatus_doStats,
fetchStage$mmioIfc_instReq_first_snd,
fetchStage$perf_setStatus_doStats,
fetchStage$pipelines_0_canDeq,
fetchStage$pipelines_1_canDeq,
fetchStage$train_predictors_isCompressed,
fetchStage$train_predictors_mispred,
fetchStage$train_predictors_taken;
// ports of submodule l2Tlb
wire [83 : 0] l2Tlb$toChildren_rsToC_first;
wire [64 : 0] l2Tlb$toMem_memReq_first, l2Tlb$toMem_respLd_enq_x;
wire [48 : 0] l2Tlb$updateVMInfo_vmD, l2Tlb$updateVMInfo_vmI;
wire [29 : 0] l2Tlb$toChildren_rqFromC_put;
wire [3 : 0] l2Tlb$perf_req_r;
wire l2Tlb$EN_perf_req,
l2Tlb$EN_perf_resp,
l2Tlb$EN_perf_setStatus,
l2Tlb$EN_toChildren_dTlbReqFlush_put,
l2Tlb$EN_toChildren_flushDone_get,
l2Tlb$EN_toChildren_iTlbReqFlush_put,
l2Tlb$EN_toChildren_rqFromC_put,
l2Tlb$EN_toChildren_rsToC_deq,
l2Tlb$EN_toMem_memReq_deq,
l2Tlb$EN_toMem_respLd_enq,
l2Tlb$EN_updateVMInfo,
l2Tlb$RDY_toChildren_dTlbReqFlush_put,
l2Tlb$RDY_toChildren_flushDone_get,
l2Tlb$RDY_toChildren_iTlbReqFlush_put,
l2Tlb$RDY_toChildren_rqFromC_put,
l2Tlb$RDY_toChildren_rsToC_deq,
l2Tlb$RDY_toChildren_rsToC_first,
l2Tlb$RDY_toMem_memReq_deq,
l2Tlb$RDY_toMem_memReq_first,
l2Tlb$RDY_toMem_respLd_enq,
l2Tlb$perf_setStatus_doStats,
l2Tlb$toMem_memReq_notEmpty,
l2Tlb$toMem_respLd_notFull;
// ports of submodule mmio_cRqQ_clearReq_dummy2_0
wire mmio_cRqQ_clearReq_dummy2_0$D_IN, mmio_cRqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_clearReq_dummy2_1
wire mmio_cRqQ_clearReq_dummy2_1$D_IN,
mmio_cRqQ_clearReq_dummy2_1$EN,
mmio_cRqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_cRqQ_deqReq_dummy2_0
wire mmio_cRqQ_deqReq_dummy2_0$D_IN, mmio_cRqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_deqReq_dummy2_1
wire mmio_cRqQ_deqReq_dummy2_1$D_IN, mmio_cRqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_cRqQ_deqReq_dummy2_2
wire mmio_cRqQ_deqReq_dummy2_2$D_IN,
mmio_cRqQ_deqReq_dummy2_2$EN,
mmio_cRqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRqQ_enqReq_dummy2_0
wire mmio_cRqQ_enqReq_dummy2_0$D_IN, mmio_cRqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_enqReq_dummy2_1
wire mmio_cRqQ_enqReq_dummy2_1$D_IN, mmio_cRqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_cRqQ_enqReq_dummy2_2
wire mmio_cRqQ_enqReq_dummy2_2$D_IN,
mmio_cRqQ_enqReq_dummy2_2$EN,
mmio_cRqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRsQ_clearReq_dummy2_0
wire mmio_cRsQ_clearReq_dummy2_0$D_IN, mmio_cRsQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_clearReq_dummy2_1
wire mmio_cRsQ_clearReq_dummy2_1$D_IN,
mmio_cRsQ_clearReq_dummy2_1$EN,
mmio_cRsQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_cRsQ_deqReq_dummy2_0
wire mmio_cRsQ_deqReq_dummy2_0$D_IN, mmio_cRsQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_deqReq_dummy2_1
wire mmio_cRsQ_deqReq_dummy2_1$D_IN, mmio_cRsQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_cRsQ_deqReq_dummy2_2
wire mmio_cRsQ_deqReq_dummy2_2$D_IN,
mmio_cRsQ_deqReq_dummy2_2$EN,
mmio_cRsQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRsQ_enqReq_dummy2_0
wire mmio_cRsQ_enqReq_dummy2_0$D_IN, mmio_cRsQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_enqReq_dummy2_1
wire mmio_cRsQ_enqReq_dummy2_1$D_IN, mmio_cRsQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_cRsQ_enqReq_dummy2_2
wire mmio_cRsQ_enqReq_dummy2_2$D_IN,
mmio_cRsQ_enqReq_dummy2_2$EN,
mmio_cRsQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataPendQ_clearReq_dummy2_0
wire mmio_dataPendQ_clearReq_dummy2_0$D_IN,
mmio_dataPendQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_clearReq_dummy2_1
wire mmio_dataPendQ_clearReq_dummy2_1$D_IN,
mmio_dataPendQ_clearReq_dummy2_1$EN,
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_0
wire mmio_dataPendQ_deqReq_dummy2_0$D_IN, mmio_dataPendQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_1
wire mmio_dataPendQ_deqReq_dummy2_1$D_IN, mmio_dataPendQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_2
wire mmio_dataPendQ_deqReq_dummy2_2$D_IN,
mmio_dataPendQ_deqReq_dummy2_2$EN,
mmio_dataPendQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_0
wire mmio_dataPendQ_enqReq_dummy2_0$D_IN, mmio_dataPendQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_1
wire mmio_dataPendQ_enqReq_dummy2_1$D_IN, mmio_dataPendQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_2
wire mmio_dataPendQ_enqReq_dummy2_2$D_IN,
mmio_dataPendQ_enqReq_dummy2_2$EN,
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataReqQ_clearReq_dummy2_0
wire mmio_dataReqQ_clearReq_dummy2_0$D_IN,
mmio_dataReqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_clearReq_dummy2_1
wire mmio_dataReqQ_clearReq_dummy2_1$D_IN,
mmio_dataReqQ_clearReq_dummy2_1$EN,
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_0
wire mmio_dataReqQ_deqReq_dummy2_0$D_IN, mmio_dataReqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_1
wire mmio_dataReqQ_deqReq_dummy2_1$D_IN, mmio_dataReqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_2
wire mmio_dataReqQ_deqReq_dummy2_2$D_IN,
mmio_dataReqQ_deqReq_dummy2_2$EN,
mmio_dataReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_0
wire mmio_dataReqQ_enqReq_dummy2_0$D_IN, mmio_dataReqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_1
wire mmio_dataReqQ_enqReq_dummy2_1$D_IN, mmio_dataReqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_2
wire mmio_dataReqQ_enqReq_dummy2_2$D_IN,
mmio_dataReqQ_enqReq_dummy2_2$EN,
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataRespQ_clearReq_dummy2_0
wire mmio_dataRespQ_clearReq_dummy2_0$D_IN,
mmio_dataRespQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_clearReq_dummy2_1
wire mmio_dataRespQ_clearReq_dummy2_1$D_IN,
mmio_dataRespQ_clearReq_dummy2_1$EN,
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_0
wire mmio_dataRespQ_deqReq_dummy2_0$D_IN, mmio_dataRespQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_1
wire mmio_dataRespQ_deqReq_dummy2_1$D_IN, mmio_dataRespQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_2
wire mmio_dataRespQ_deqReq_dummy2_2$D_IN,
mmio_dataRespQ_deqReq_dummy2_2$EN,
mmio_dataRespQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_0
wire mmio_dataRespQ_enqReq_dummy2_0$D_IN, mmio_dataRespQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_1
wire mmio_dataRespQ_enqReq_dummy2_1$D_IN, mmio_dataRespQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_2
wire mmio_dataRespQ_enqReq_dummy2_2$D_IN,
mmio_dataRespQ_enqReq_dummy2_2$EN,
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRqQ_clearReq_dummy2_0
wire mmio_pRqQ_clearReq_dummy2_0$D_IN, mmio_pRqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_clearReq_dummy2_1
wire mmio_pRqQ_clearReq_dummy2_1$D_IN,
mmio_pRqQ_clearReq_dummy2_1$EN,
mmio_pRqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_pRqQ_deqReq_dummy2_0
wire mmio_pRqQ_deqReq_dummy2_0$D_IN, mmio_pRqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_deqReq_dummy2_1
wire mmio_pRqQ_deqReq_dummy2_1$D_IN, mmio_pRqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_pRqQ_deqReq_dummy2_2
wire mmio_pRqQ_deqReq_dummy2_2$D_IN,
mmio_pRqQ_deqReq_dummy2_2$EN,
mmio_pRqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRqQ_enqReq_dummy2_0
wire mmio_pRqQ_enqReq_dummy2_0$D_IN, mmio_pRqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_enqReq_dummy2_1
wire mmio_pRqQ_enqReq_dummy2_1$D_IN, mmio_pRqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_pRqQ_enqReq_dummy2_2
wire mmio_pRqQ_enqReq_dummy2_2$D_IN,
mmio_pRqQ_enqReq_dummy2_2$EN,
mmio_pRqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRsQ_clearReq_dummy2_0
wire mmio_pRsQ_clearReq_dummy2_0$D_IN, mmio_pRsQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_clearReq_dummy2_1
wire mmio_pRsQ_clearReq_dummy2_1$D_IN,
mmio_pRsQ_clearReq_dummy2_1$EN,
mmio_pRsQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_pRsQ_deqReq_dummy2_0
wire mmio_pRsQ_deqReq_dummy2_0$D_IN, mmio_pRsQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_deqReq_dummy2_1
wire mmio_pRsQ_deqReq_dummy2_1$D_IN, mmio_pRsQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_pRsQ_deqReq_dummy2_2
wire mmio_pRsQ_deqReq_dummy2_2$D_IN,
mmio_pRsQ_deqReq_dummy2_2$EN,
mmio_pRsQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRsQ_enqReq_dummy2_0
wire mmio_pRsQ_enqReq_dummy2_0$D_IN, mmio_pRsQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_enqReq_dummy2_1
wire mmio_pRsQ_enqReq_dummy2_1$D_IN, mmio_pRsQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_pRsQ_enqReq_dummy2_2
wire mmio_pRsQ_enqReq_dummy2_2$D_IN,
mmio_pRsQ_enqReq_dummy2_2$EN,
mmio_pRsQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule perfReqQ
wire [8 : 0] perfReqQ$D_IN, perfReqQ$D_OUT;
wire perfReqQ$CLR,
perfReqQ$DEQ,
perfReqQ$EMPTY_N,
perfReqQ$ENQ,
perfReqQ$FULL_N;
// ports of submodule regRenamingTable
reg [26 : 0] regRenamingTable$rename_0_getRename_r;
reg [3 : 0] regRenamingTable$specUpdate_incorrectSpeculation_kill_tag;
wire [32 : 0] regRenamingTable$rename_0_getRename,
regRenamingTable$rename_1_getRename;
wire [26 : 0] regRenamingTable$rename_0_claimRename_r,
regRenamingTable$rename_1_claimRename_r,
regRenamingTable$rename_1_getRename_r;
wire [11 : 0] regRenamingTable$rename_0_claimRename_sb,
regRenamingTable$rename_1_claimRename_sb,
regRenamingTable$specUpdate_correctSpeculation_mask;
wire regRenamingTable$EN_commit_0_commit,
regRenamingTable$EN_commit_1_commit,
regRenamingTable$EN_rename_0_claimRename,
regRenamingTable$EN_rename_1_claimRename,
regRenamingTable$EN_specUpdate_correctSpeculation,
regRenamingTable$EN_specUpdate_incorrectSpeculation,
regRenamingTable$RDY_commit_0_commit,
regRenamingTable$RDY_commit_1_commit,
regRenamingTable$RDY_rename_0_claimRename,
regRenamingTable$RDY_rename_0_getRename,
regRenamingTable$RDY_rename_1_claimRename,
regRenamingTable$RDY_rename_1_getRename,
regRenamingTable$rename_0_canRename,
regRenamingTable$rename_1_canRename,
regRenamingTable$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule rf
reg [63 : 0] rf$write_2_wr_data, rf$write_3_wr_data;
reg [6 : 0] rf$write_2_wr_rindx, rf$write_3_wr_rindx;
wire [63 : 0] rf$read_0_rd1,
rf$read_0_rd2,
rf$read_1_rd1,
rf$read_1_rd2,
rf$read_2_rd1,
rf$read_2_rd2,
rf$read_2_rd3,
rf$read_3_rd1,
rf$read_3_rd2,
rf$read_4_rd1,
rf$write_0_wr_data,
rf$write_1_wr_data,
rf$write_4_wr_data;
wire [6 : 0] rf$read_0_rd1_rindx,
rf$read_0_rd2_rindx,
rf$read_0_rd3_rindx,
rf$read_1_rd1_rindx,
rf$read_1_rd2_rindx,
rf$read_1_rd3_rindx,
rf$read_2_rd1_rindx,
rf$read_2_rd2_rindx,
rf$read_2_rd3_rindx,
rf$read_3_rd1_rindx,
rf$read_3_rd2_rindx,
rf$read_3_rd3_rindx,
rf$read_4_rd1_rindx,
rf$read_4_rd2_rindx,
rf$read_4_rd3_rindx,
rf$write_0_wr_rindx,
rf$write_1_wr_rindx,
rf$write_4_wr_rindx;
wire rf$EN_write_0_wr,
rf$EN_write_1_wr,
rf$EN_write_2_wr,
rf$EN_write_3_wr,
rf$EN_write_4_wr;
// ports of submodule rob
reg [353 : 0] rob$enqPort_0_enq_x;
reg [63 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data,
rob$setExecuted_doFinishMem_RegData_dst_data;
reg [11 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_x,
rob$setExecuted_doFinishMem_RegData_x,
rob$specUpdate_incorrectSpeculation_inst_tag;
reg [4 : 0] rob$setExecuted_deqLSQ_cause,
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags;
reg [3 : 0] rob$specUpdate_incorrectSpeculation_spec_tag;
wire [353 : 0] rob$deqPort_0_deq_data,
rob$deqPort_1_deq_data,
rob$enqPort_1_enq_x;
wire [129 : 0] rob$setExecuted_doFinishAlu_0_set_cf,
rob$setExecuted_doFinishAlu_1_set_cf;
wire [64 : 0] rob$setExecuted_doFinishAlu_0_set_csrData,
rob$setExecuted_doFinishAlu_1_set_csrData;
wire [63 : 0] rob$getOrigPC_0_get,
rob$getOrigPC_1_get,
rob$getOrigPredPC_0_get,
rob$getOrigPredPC_1_get,
rob$setExecuted_doFinishAlu_0_set_dst_data,
rob$setExecuted_doFinishAlu_1_set_dst_data,
rob$setExecuted_doFinishMem_vaddr;
wire [31 : 0] rob$getOrig_Inst_0_get, rob$getOrig_Inst_1_get;
wire [11 : 0] rob$deqPort_0_getDeqInstTag,
rob$enqPort_0_getEnqInstTag,
rob$enqPort_1_getEnqInstTag,
rob$getOrigPC_0_get_x,
rob$getOrigPC_1_get_x,
rob$getOrigPC_2_get_x,
rob$getOrigPredPC_0_get_x,
rob$getOrigPredPC_1_get_x,
rob$getOrig_Inst_0_get_x,
rob$getOrig_Inst_1_get_x,
rob$setExecuted_deqLSQ_x,
rob$setExecuted_doFinishAlu_0_set_x,
rob$setExecuted_doFinishAlu_1_set_x,
rob$setExecuted_doFinishMem_x,
rob$setLSQAtCommitNotified_x,
rob$specUpdate_correctSpeculation_mask;
wire [5 : 0] rob$getEnqTime;
wire [2 : 0] rob$setExecuted_deqLSQ_ld_killed;
wire rob$EN_deqPort_0_deq,
rob$EN_deqPort_1_deq,
rob$EN_enqPort_0_enq,
rob$EN_enqPort_1_enq,
rob$EN_setExecuted_deqLSQ,
rob$EN_setExecuted_doFinishAlu_0_set,
rob$EN_setExecuted_doFinishAlu_1_set,
rob$EN_setExecuted_doFinishFpuMulDiv_0_set,
rob$EN_setExecuted_doFinishMem,
rob$EN_setExecuted_doFinishMem_RegData,
rob$EN_setLSQAtCommitNotified,
rob$EN_specUpdate_correctSpeculation,
rob$EN_specUpdate_incorrectSpeculation,
rob$RDY_deqPort_0_deq,
rob$RDY_deqPort_0_deq_data,
rob$RDY_deqPort_1_deq,
rob$RDY_deqPort_1_deq_data,
rob$RDY_enqPort_0_enq,
rob$RDY_enqPort_1_enq,
rob$RDY_setExecuted_deqLSQ,
rob$RDY_setExecuted_doFinishAlu_0_set,
rob$RDY_setExecuted_doFinishAlu_1_set,
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set,
rob$RDY_setExecuted_doFinishMem,
rob$RDY_setLSQAtCommitNotified,
rob$deqPort_0_canDeq,
rob$deqPort_1_canDeq,
rob$enqPort_0_canEnq,
rob$enqPort_1_canEnq,
rob$isEmpty,
rob$setExecuted_doFinishMem_access_at_commit,
rob$setExecuted_doFinishMem_non_mmio_st_done,
rob$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule sbAggr
reg [6 : 0] sbAggr$setReady_2_put, sbAggr$setReady_4_put;
wire [32 : 0] sbAggr$eagerLookup_0_get_r, sbAggr$eagerLookup_1_get_r;
wire [8 : 0] sbAggr$setBusy_0_set_dst, sbAggr$setBusy_1_set_dst;
wire [6 : 0] sbAggr$setReady_0_put,
sbAggr$setReady_1_put,
sbAggr$setReady_3_put;
wire [3 : 0] sbAggr$eagerLookup_0_get, sbAggr$eagerLookup_1_get;
wire sbAggr$EN_setBusy_0_set,
sbAggr$EN_setBusy_1_set,
sbAggr$EN_setReady_0_put,
sbAggr$EN_setReady_1_put,
sbAggr$EN_setReady_2_put,
sbAggr$EN_setReady_3_put,
sbAggr$EN_setReady_4_put;
// ports of submodule sbCons
reg [6 : 0] sbCons$setReady_2_put, sbCons$setReady_3_put;
wire [32 : 0] sbCons$eagerLookup_0_get_r,
sbCons$eagerLookup_1_get_r,
sbCons$lazyLookup_0_get_r,
sbCons$lazyLookup_1_get_r,
sbCons$lazyLookup_2_get_r,
sbCons$lazyLookup_3_get_r,
sbCons$lazyLookup_4_get_r;
wire [8 : 0] sbCons$setBusy_0_set_dst, sbCons$setBusy_1_set_dst;
wire [6 : 0] sbCons$setReady_0_put,
sbCons$setReady_1_put,
sbCons$setReady_4_put;
wire [3 : 0] sbCons$lazyLookup_0_get,
sbCons$lazyLookup_1_get,
sbCons$lazyLookup_2_get,
sbCons$lazyLookup_3_get;
wire sbCons$EN_setBusy_0_set,
sbCons$EN_setBusy_1_set,
sbCons$EN_setReady_0_put,
sbCons$EN_setReady_1_put,
sbCons$EN_setReady_2_put,
sbCons$EN_setReady_3_put,
sbCons$EN_setReady_4_put;
// ports of submodule specTagManager
reg [3 : 0] specTagManager$specUpdate_incorrectSpeculation_kill_tag;
wire [11 : 0] specTagManager$currentSpecBits,
specTagManager$specUpdate_correctSpeculation_mask;
wire [3 : 0] specTagManager$nextSpecTag;
wire specTagManager$EN_claimSpecTag,
specTagManager$EN_specUpdate_correctSpeculation,
specTagManager$EN_specUpdate_incorrectSpeculation,
specTagManager$RDY_claimSpecTag,
specTagManager$RDY_nextSpecTag,
specTagManager$canClaim,
specTagManager$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule v_f_to_TV_0
reg [712 : 0] v_f_to_TV_0$D_IN;
wire [712 : 0] v_f_to_TV_0$D_OUT;
wire v_f_to_TV_0$CLR,
v_f_to_TV_0$DEQ,
v_f_to_TV_0$EMPTY_N,
v_f_to_TV_0$ENQ,
v_f_to_TV_0$FULL_N;
// ports of submodule v_f_to_TV_1
wire [712 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT;
wire v_f_to_TV_1$CLR,
v_f_to_TV_1$DEQ,
v_f_to_TV_1$EMPTY_N,
v_f_to_TV_1$ENQ,
v_f_to_TV_1$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_commitStage_doCommitKilledLd,
CAN_FIRE_RL_commitStage_doCommitNormalInst,
CAN_FIRE_RL_commitStage_doCommitSystemInst,
CAN_FIRE_RL_commitStage_doCommitTrap_flush,
CAN_FIRE_RL_commitStage_doCommitTrap_handle,
CAN_FIRE_RL_commitStage_doSetLSQAtCommit,
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1,
CAN_FIRE_RL_commitStage_notifyLSQCommit,
CAN_FIRE_RL_commitStage_rl_send_tv_reset,
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu,
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
CAN_FIRE_RL_coreFix_doFetchTrainBP,
CAN_FIRE_RL_coreFix_doFetchTrainBP_1,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon,
CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
CAN_FIRE_RL_coreFix_memExe_doDispatchMem,
CAN_FIRE_RL_coreFix_memExe_doExeMem,
CAN_FIRE_RL_coreFix_memExe_doFinishMem,
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
CAN_FIRE_RL_coreFix_memExe_doIssueSB,
CAN_FIRE_RL_coreFix_memExe_doRegReadMem,
CAN_FIRE_RL_coreFix_memExe_doRespLdForward,
CAN_FIRE_RL_coreFix_memExe_doRespLdMem,
CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_sendLdToMem,
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
CAN_FIRE_RL_coreFix_memExe_sendStToMem,
CAN_FIRE_RL_csrInstOrInterruptInflight_canon,
CAN_FIRE_RL_csrf_incCycle,
CAN_FIRE_RL_csrf_mcycle_ehr_data_canon,
CAN_FIRE_RL_csrf_mcycle_ehr_setRead,
CAN_FIRE_RL_csrf_minstret_ehr_data_canon,
CAN_FIRE_RL_csrf_minstret_ehr_setRead,
CAN_FIRE_RL_flushBrPred,
CAN_FIRE_RL_flushCaches,
CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_mkConnectionGetPut_1,
CAN_FIRE_RL_mmio_cRqQ_canonicalize,
CAN_FIRE_RL_mmio_cRqQ_clearReq_canon,
CAN_FIRE_RL_mmio_cRqQ_deqReq_canon,
CAN_FIRE_RL_mmio_cRqQ_enqReq_canon,
CAN_FIRE_RL_mmio_cRsQ_canonicalize,
CAN_FIRE_RL_mmio_cRsQ_clearReq_canon,
CAN_FIRE_RL_mmio_cRsQ_deqReq_canon,
CAN_FIRE_RL_mmio_cRsQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_canonicalize,
CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_canonicalize,
CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_canonicalize,
CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon,
CAN_FIRE_RL_mmio_handlePRq,
CAN_FIRE_RL_mmio_pRqQ_canonicalize,
CAN_FIRE_RL_mmio_pRqQ_clearReq_canon,
CAN_FIRE_RL_mmio_pRqQ_deqReq_canon,
CAN_FIRE_RL_mmio_pRqQ_enqReq_canon,
CAN_FIRE_RL_mmio_pRsQ_canonicalize,
CAN_FIRE_RL_mmio_pRsQ_clearReq_canon,
CAN_FIRE_RL_mmio_pRsQ_deqReq_canon,
CAN_FIRE_RL_mmio_pRsQ_enqReq_canon,
CAN_FIRE_RL_mmio_sendDataReq,
CAN_FIRE_RL_mmio_sendDataResp,
CAN_FIRE_RL_mmio_sendInstReq,
CAN_FIRE_RL_mmio_sendInstResp,
CAN_FIRE_RL_prepareCachesAndTlbs,
CAN_FIRE_RL_readyToFetch,
CAN_FIRE_RL_renameStage_doRenaming,
CAN_FIRE_RL_renameStage_doRenaming_SystemInst,
CAN_FIRE_RL_renameStage_doRenaming_Trap,
CAN_FIRE_RL_renameStage_doRenaming_wrongPath,
CAN_FIRE_RL_rl_debug_csr_access_busy,
CAN_FIRE_RL_rl_debug_csr_read,
CAN_FIRE_RL_rl_debug_csr_write,
CAN_FIRE_RL_rl_debug_fpr_access_busy,
CAN_FIRE_RL_rl_debug_fpr_read,
CAN_FIRE_RL_rl_debug_fpr_write,
CAN_FIRE_RL_rl_debug_gpr_access_busy,
CAN_FIRE_RL_rl_debug_gpr_read,
CAN_FIRE_RL_rl_debug_gpr_write,
CAN_FIRE_RL_rl_debug_halt_req,
CAN_FIRE_RL_rl_debug_halt_req_already_halted,
CAN_FIRE_RL_rl_debug_halted,
CAN_FIRE_RL_rl_debug_resume,
CAN_FIRE_RL_rl_debug_run_redundant,
CAN_FIRE_RL_rl_outOfReset,
CAN_FIRE_RL_sendDTlbReq,
CAN_FIRE_RL_sendFlushDone,
CAN_FIRE_RL_sendITlbReq,
CAN_FIRE_RL_sendRobEnqTime,
CAN_FIRE_RL_sendRsToDTlb,
CAN_FIRE_RL_sendRsToITlb,
CAN_FIRE_RL_setDoFlushBrPred,
CAN_FIRE_RL_setDoFlushCaches,
CAN_FIRE_coreIndInv_perfResp,
CAN_FIRE_coreIndInv_terminate,
CAN_FIRE_coreReq_perfReq,
CAN_FIRE_coreReq_start,
CAN_FIRE_dCacheToParent_fromP_enq,
CAN_FIRE_dCacheToParent_rqToP_deq,
CAN_FIRE_dCacheToParent_rsToP_deq,
CAN_FIRE_deadlock_checkStarted_get,
CAN_FIRE_deadlock_commitInstStuck_get,
CAN_FIRE_deadlock_commitUserInstStuck_get,
CAN_FIRE_deadlock_dCacheCRqStuck_get,
CAN_FIRE_deadlock_dCachePRqStuck_get,
CAN_FIRE_deadlock_iCacheCRqStuck_get,
CAN_FIRE_deadlock_iCachePRqStuck_get,
CAN_FIRE_deadlock_renameCorrectPathStuck_get,
CAN_FIRE_deadlock_renameInstStuck_get,
CAN_FIRE_hart0_csr_mem_server_request_put,
CAN_FIRE_hart0_csr_mem_server_response_get,
CAN_FIRE_hart0_fpr_mem_server_request_put,
CAN_FIRE_hart0_fpr_mem_server_response_get,
CAN_FIRE_hart0_gpr_mem_server_request_put,
CAN_FIRE_hart0_gpr_mem_server_response_get,
CAN_FIRE_hart0_run_halt_server_request_put,
CAN_FIRE_hart0_run_halt_server_response_get,
CAN_FIRE_iCacheToParent_fromP_enq,
CAN_FIRE_iCacheToParent_rqToP_deq,
CAN_FIRE_iCacheToParent_rsToP_deq,
CAN_FIRE_mmioToPlatform_cRq_deq,
CAN_FIRE_mmioToPlatform_cRs_deq,
CAN_FIRE_mmioToPlatform_pRq_enq,
CAN_FIRE_mmioToPlatform_pRs_enq,
CAN_FIRE_mmioToPlatform_setTime,
CAN_FIRE_recvDoStats,
CAN_FIRE_renameDebug_renameErr_get,
CAN_FIRE_sendDoStats,
CAN_FIRE_setMEIP,
CAN_FIRE_setSEIP,
CAN_FIRE_tlbToMem_memReq_deq,
CAN_FIRE_tlbToMem_respLd_enq,
CAN_FIRE_v_to_TV_0_get,
CAN_FIRE_v_to_TV_1_get,
WILL_FIRE_RL_commitStage_doCommitKilledLd,
WILL_FIRE_RL_commitStage_doCommitNormalInst,
WILL_FIRE_RL_commitStage_doCommitSystemInst,
WILL_FIRE_RL_commitStage_doCommitTrap_flush,
WILL_FIRE_RL_commitStage_doCommitTrap_handle,
WILL_FIRE_RL_commitStage_doSetLSQAtCommit,
WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1,
WILL_FIRE_RL_commitStage_notifyLSQCommit,
WILL_FIRE_RL_commitStage_rl_send_tv_reset,
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu,
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
WILL_FIRE_RL_coreFix_doFetchTrainBP,
WILL_FIRE_RL_coreFix_doFetchTrainBP_1,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon,
WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
WILL_FIRE_RL_coreFix_memExe_doDispatchMem,
WILL_FIRE_RL_coreFix_memExe_doExeMem,
WILL_FIRE_RL_coreFix_memExe_doFinishMem,
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
WILL_FIRE_RL_coreFix_memExe_doIssueSB,
WILL_FIRE_RL_coreFix_memExe_doRegReadMem,
WILL_FIRE_RL_coreFix_memExe_doRespLdForward,
WILL_FIRE_RL_coreFix_memExe_doRespLdMem,
WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_sendLdToMem,
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
WILL_FIRE_RL_coreFix_memExe_sendStToMem,
WILL_FIRE_RL_csrInstOrInterruptInflight_canon,
WILL_FIRE_RL_csrf_incCycle,
WILL_FIRE_RL_csrf_mcycle_ehr_data_canon,
WILL_FIRE_RL_csrf_mcycle_ehr_setRead,
WILL_FIRE_RL_csrf_minstret_ehr_data_canon,
WILL_FIRE_RL_csrf_minstret_ehr_setRead,
WILL_FIRE_RL_flushBrPred,
WILL_FIRE_RL_flushCaches,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_mkConnectionGetPut_1,
WILL_FIRE_RL_mmio_cRqQ_canonicalize,
WILL_FIRE_RL_mmio_cRqQ_clearReq_canon,
WILL_FIRE_RL_mmio_cRqQ_deqReq_canon,
WILL_FIRE_RL_mmio_cRqQ_enqReq_canon,
WILL_FIRE_RL_mmio_cRsQ_canonicalize,
WILL_FIRE_RL_mmio_cRsQ_clearReq_canon,
WILL_FIRE_RL_mmio_cRsQ_deqReq_canon,
WILL_FIRE_RL_mmio_cRsQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_canonicalize,
WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_canonicalize,
WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_canonicalize,
WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon,
WILL_FIRE_RL_mmio_handlePRq,
WILL_FIRE_RL_mmio_pRqQ_canonicalize,
WILL_FIRE_RL_mmio_pRqQ_clearReq_canon,
WILL_FIRE_RL_mmio_pRqQ_deqReq_canon,
WILL_FIRE_RL_mmio_pRqQ_enqReq_canon,
WILL_FIRE_RL_mmio_pRsQ_canonicalize,
WILL_FIRE_RL_mmio_pRsQ_clearReq_canon,
WILL_FIRE_RL_mmio_pRsQ_deqReq_canon,
WILL_FIRE_RL_mmio_pRsQ_enqReq_canon,
WILL_FIRE_RL_mmio_sendDataReq,
WILL_FIRE_RL_mmio_sendDataResp,
WILL_FIRE_RL_mmio_sendInstReq,
WILL_FIRE_RL_mmio_sendInstResp,
WILL_FIRE_RL_prepareCachesAndTlbs,
WILL_FIRE_RL_readyToFetch,
WILL_FIRE_RL_renameStage_doRenaming,
WILL_FIRE_RL_renameStage_doRenaming_SystemInst,
WILL_FIRE_RL_renameStage_doRenaming_Trap,
WILL_FIRE_RL_renameStage_doRenaming_wrongPath,
WILL_FIRE_RL_rl_debug_csr_access_busy,
WILL_FIRE_RL_rl_debug_csr_read,
WILL_FIRE_RL_rl_debug_csr_write,
WILL_FIRE_RL_rl_debug_fpr_access_busy,
WILL_FIRE_RL_rl_debug_fpr_read,
WILL_FIRE_RL_rl_debug_fpr_write,
WILL_FIRE_RL_rl_debug_gpr_access_busy,
WILL_FIRE_RL_rl_debug_gpr_read,
WILL_FIRE_RL_rl_debug_gpr_write,
WILL_FIRE_RL_rl_debug_halt_req,
WILL_FIRE_RL_rl_debug_halt_req_already_halted,
WILL_FIRE_RL_rl_debug_halted,
WILL_FIRE_RL_rl_debug_resume,
WILL_FIRE_RL_rl_debug_run_redundant,
WILL_FIRE_RL_rl_outOfReset,
WILL_FIRE_RL_sendDTlbReq,
WILL_FIRE_RL_sendFlushDone,
WILL_FIRE_RL_sendITlbReq,
WILL_FIRE_RL_sendRobEnqTime,
WILL_FIRE_RL_sendRsToDTlb,
WILL_FIRE_RL_sendRsToITlb,
WILL_FIRE_RL_setDoFlushBrPred,
WILL_FIRE_RL_setDoFlushCaches,
WILL_FIRE_coreIndInv_perfResp,
WILL_FIRE_coreIndInv_terminate,
WILL_FIRE_coreReq_perfReq,
WILL_FIRE_coreReq_start,
WILL_FIRE_dCacheToParent_fromP_enq,
WILL_FIRE_dCacheToParent_rqToP_deq,
WILL_FIRE_dCacheToParent_rsToP_deq,
WILL_FIRE_deadlock_checkStarted_get,
WILL_FIRE_deadlock_commitInstStuck_get,
WILL_FIRE_deadlock_commitUserInstStuck_get,
WILL_FIRE_deadlock_dCacheCRqStuck_get,
WILL_FIRE_deadlock_dCachePRqStuck_get,
WILL_FIRE_deadlock_iCacheCRqStuck_get,
WILL_FIRE_deadlock_iCachePRqStuck_get,
WILL_FIRE_deadlock_renameCorrectPathStuck_get,
WILL_FIRE_deadlock_renameInstStuck_get,
WILL_FIRE_hart0_csr_mem_server_request_put,
WILL_FIRE_hart0_csr_mem_server_response_get,
WILL_FIRE_hart0_fpr_mem_server_request_put,
WILL_FIRE_hart0_fpr_mem_server_response_get,
WILL_FIRE_hart0_gpr_mem_server_request_put,
WILL_FIRE_hart0_gpr_mem_server_response_get,
WILL_FIRE_hart0_run_halt_server_request_put,
WILL_FIRE_hart0_run_halt_server_response_get,
WILL_FIRE_iCacheToParent_fromP_enq,
WILL_FIRE_iCacheToParent_rqToP_deq,
WILL_FIRE_iCacheToParent_rsToP_deq,
WILL_FIRE_mmioToPlatform_cRq_deq,
WILL_FIRE_mmioToPlatform_cRs_deq,
WILL_FIRE_mmioToPlatform_pRq_enq,
WILL_FIRE_mmioToPlatform_pRs_enq,
WILL_FIRE_mmioToPlatform_setTime,
WILL_FIRE_recvDoStats,
WILL_FIRE_renameDebug_renameErr_get,
WILL_FIRE_sendDoStats,
WILL_FIRE_setMEIP,
WILL_FIRE_setSEIP,
WILL_FIRE_tlbToMem_memReq_deq,
WILL_FIRE_tlbToMem_respLd_enq,
WILL_FIRE_v_to_TV_0_get,
WILL_FIRE_v_to_TV_1_get;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1,
MUX_coreFix_memExe_lsq$respLd_2__VAL_2,
MUX_fetchStage$redirect_1__VAL_6;
reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1,
MUX_coreFix_memExe_lsq$respLd_1__VAL_2;
reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2, MUX_csrf_fs_reg$write_1__VAL_3;
wire [712 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1,
MUX_v_f_to_TV_0$enq_1__VAL_2,
MUX_v_f_to_TV_0$enq_1__VAL_3,
MUX_v_f_to_TV_0$enq_1__VAL_4;
wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
wire [579 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
wire [569 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
wire [353 : 0] MUX_rob$enqPort_0_enq_1__VAL_1,
MUX_rob$enqPort_0_enq_1__VAL_2,
MUX_rob$enqPort_0_enq_1__VAL_3;
wire [161 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2;
wire [160 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
wire [159 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1,
MUX_coreFix_trainBPQ_0$enq_1__VAL_2,
MUX_coreFix_trainBPQ_1$enq_1__VAL_1,
MUX_coreFix_trainBPQ_1$enq_1__VAL_2;
wire [152 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3,
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2;
wire [142 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2,
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2;
wire [133 : 0] MUX_commitStage_commitTrap$write_1__VAL_2;
wire [69 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1;
wire [67 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1;
wire [64 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3,
MUX_f_csr_rsps$enq_1__VAL_3,
MUX_f_fpr_rsps$enq_1__VAL_3;
wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_1,
MUX_commitStage_rg_serial_num$write_1__VAL_3,
MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2,
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1,
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2,
MUX_csrf_mtval_csr$write_1__VAL_1,
MUX_csrf_mtval_csr$write_1__VAL_2,
MUX_csrf_rg_dcsr$write_1__VAL_2,
MUX_csrf_sepc_csr$write_1__VAL_1,
MUX_csrf_stval_csr$write_1__VAL_1,
MUX_rf$write_2_wr_2__VAL_2,
MUX_rf$write_2_wr_2__VAL_3,
MUX_rf$write_2_wr_2__VAL_4,
MUX_rf$write_2_wr_2__VAL_5,
MUX_rf$write_2_wr_2__VAL_6,
MUX_rf$write_3_wr_2__VAL_4,
MUX_rf$write_3_wr_2__VAL_5;
wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1,
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_2;
wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1,
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2;
wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2,
MUX_regRenamingTable$rename_0_getRename_1__VAL_3;
wire [7 : 0] MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1;
wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1,
MUX_rob$setExecuted_deqLSQ_2__VAL_2,
MUX_rob$setExecuted_deqLSQ_2__VAL_6,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4;
wire [3 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2;
wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1,
MUX_csrf_frm_reg$write_1__VAL_1,
MUX_csrf_frm_reg$write_1__VAL_2;
wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__VAL_1;
wire MUX_commitStage_rg_run_state$write_1__SEL_1,
MUX_commitStage_rg_serial_num$write_1__SEL_1,
MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1,
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4,
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1,
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2,
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1,
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2,
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2,
MUX_coreFix_memExe_lsq$getHit_1__SEL_1,
MUX_coreFix_memExe_lsq$getHit_1__SEL_2,
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1,
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1,
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1,
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2,
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1,
MUX_coreFix_trainBPQ_0$enq_1__SEL_1,
MUX_coreFix_trainBPQ_1$enq_1__SEL_1,
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1,
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2,
MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1,
MUX_csrf_external_int_en_vec_0$write_1__SEL_1,
MUX_csrf_external_int_en_vec_3$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_0$write_1__SEL_2,
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2,
MUX_csrf_fflags_reg$write_1__SEL_1,
MUX_csrf_fflags_reg$write_1__SEL_2,
MUX_csrf_fflags_reg$write_1__SEL_3,
MUX_csrf_frm_reg$write_1__SEL_1,
MUX_csrf_fs_reg$write_1__SEL_2,
MUX_csrf_fs_reg$write_1__SEL_3,
MUX_csrf_ie_vec_0$write_1__SEL_1,
MUX_csrf_ie_vec_0$write_1__SEL_2,
MUX_csrf_ie_vec_1$write_1__SEL_1,
MUX_csrf_ie_vec_1$write_1__SEL_2,
MUX_csrf_ie_vec_1$write_1__VAL_1,
MUX_csrf_ie_vec_3$write_1__SEL_1,
MUX_csrf_ie_vec_3$write_1__SEL_2,
MUX_csrf_ie_vec_3$write_1__SEL_3,
MUX_csrf_ie_vec_3$write_1__VAL_1,
MUX_csrf_mcause_code_reg$write_1__SEL_1,
MUX_csrf_mcause_code_reg$write_1__SEL_3,
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1,
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1,
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2,
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1,
MUX_csrf_mepc_csr$write_1__SEL_1,
MUX_csrf_mepc_csr$write_1__SEL_3,
MUX_csrf_mideleg_11_reg$write_1__SEL_1,
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1,
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2,
MUX_csrf_mpp_reg$write_1__SEL_1,
MUX_csrf_mscratch_csr$write_1__SEL_1,
MUX_csrf_mtval_csr$write_1__SEL_1,
MUX_csrf_mtval_csr$write_1__SEL_3,
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1,
MUX_csrf_ppn_reg$write_1__SEL_1,
MUX_csrf_prev_ie_vec_1$write_1__SEL_1,
MUX_csrf_prev_ie_vec_1$write_1__VAL_1,
MUX_csrf_prev_ie_vec_3$write_1__SEL_1,
MUX_csrf_prev_ie_vec_3$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__SEL_1,
MUX_csrf_prv_reg$write_1__SEL_3,
MUX_csrf_rg_dcsr$write_1__SEL_1,
MUX_csrf_rg_dpc$write_1__SEL_1,
MUX_csrf_rg_dpc$write_1__SEL_3,
MUX_csrf_rg_dscratch0$write_1__SEL_1,
MUX_csrf_rg_dscratch1$write_1__SEL_1,
MUX_csrf_scause_code_reg$write_1__SEL_1,
MUX_csrf_scause_code_reg$write_1__SEL_3,
MUX_csrf_scounteren_cy_reg$write_1__SEL_1,
MUX_csrf_sepc_csr$write_1__SEL_1,
MUX_csrf_sepc_csr$write_1__SEL_3,
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2,
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2,
MUX_csrf_spp_reg$write_1__SEL_1,
MUX_csrf_spp_reg$write_1__VAL_1,
MUX_csrf_sscratch_csr$write_1__SEL_1,
MUX_csrf_stats_module_writeQ$enq_1__SEL_1,
MUX_csrf_stval_csr$write_1__SEL_1,
MUX_csrf_stval_csr$write_1__SEL_3,
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1,
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2,
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2,
MUX_flush_reservation$write_1__SEL_2,
MUX_flush_tlbs$write_1__SEL_1,
MUX_regRenamingTable$rename_0_getRename_1__SEL_1,
MUX_regRenamingTable$rename_0_getRename_1__SEL_2,
MUX_regRenamingTable$rename_0_getRename_1__SEL_3,
MUX_renameStage_rg_m_halt_req$write_1__PSEL_1,
MUX_renameStage_rg_m_halt_req$write_1__SEL_1,
MUX_renameStage_rg_m_halt_req$write_1__SEL_2,
MUX_rf$write_3_wr_1__PSEL_1,
MUX_rf$write_3_wr_1__SEL_1,
MUX_rf$write_3_wr_1__SEL_2,
MUX_rf$write_3_wr_1__SEL_3,
MUX_rf$write_3_wr_1__SEL_4,
MUX_rf$write_3_wr_1__SEL_5,
MUX_rf$write_3_wr_2__SEL_1,
MUX_rg_core_run_state$write_1__SEL_4,
MUX_rob$setExecuted_deqLSQ_1__SEL_1,
MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_1,
MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_1,
MUX_sbAggr$setReady_4_put_1__SEL_1,
MUX_sbAggr$setReady_4_put_1__SEL_2,
MUX_sbCons$setReady_3_put_1__SEL_1,
MUX_sbCons$setReady_3_put_1__SEL_2,
MUX_sbCons$setReady_3_put_1__SEL_3,
MUX_started$write_1__SEL_1,
MUX_v_f_to_TV_0$enq_1__SEL_2;
// remaining internal signals
reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2529;
reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q297,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q252,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10056,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2969,
addr__h292526,
curData__h193958,
data_out__h733205,
data_warl_xformed__h720256,
rVal1__h613461,
rVal1__h638104,
trap_val__h709367,
x__h198698;
reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20,
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q217,
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q218,
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q219,
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q220,
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q205,
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q206,
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q207,
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q208,
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q209,
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q210,
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q221,
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q222,
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q223,
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q224,
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q225,
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q226,
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q215,
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q216,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10711,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10737,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10756,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9231,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9258,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9277,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9941,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9967,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9986;
reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356,
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408;
reg [22 : 0] CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q83,
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q84,
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q87,
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q88,
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q89,
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q90,
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q120,
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q121,
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q50,
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q51,
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q118,
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q119,
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q48,
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q49,
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q122,
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q123,
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q52,
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q53,
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q124,
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q125,
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q54,
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q55,
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q85,
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q86,
_theResult___fst_sfd__h348594,
_theResult___fst_sfd__h357317,
_theResult___fst_sfd__h365899,
_theResult___fst_sfd__h375083,
_theResult___fst_sfd__h383719,
_theResult___fst_sfd__h394293,
_theResult___fst_sfd__h403014,
_theResult___fst_sfd__h411596,
_theResult___fst_sfd__h420780,
_theResult___fst_sfd__h429416,
_theResult___fst_sfd__h439988,
_theResult___fst_sfd__h448709,
_theResult___fst_sfd__h457291,
_theResult___fst_sfd__h466475,
_theResult___fst_sfd__h475111;
reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q286,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q292,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289,
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299,
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q295,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061,
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d13758;
reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367,
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417;
reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q278,
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q287,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q284,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q293,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q290,
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235,
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q247,
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q301,
CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5,
CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1,
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143;
reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18,
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q211,
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q212,
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q213,
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q214,
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q183,
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q184,
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q185,
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q186,
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q187,
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q188,
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q160,
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q161,
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q189,
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q190,
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q191,
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q192,
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q143,
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q144,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10616,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10654,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10685,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9131,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9174,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9205,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9846,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9884,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9915;
reg [7 : 0] CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q68,
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q69,
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q76,
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q77,
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q81,
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q82,
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q105,
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q106,
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q35,
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q36,
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q103,
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q104,
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q33,
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q34,
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q111,
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q112,
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q41,
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q42,
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q116,
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q117,
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q46,
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q47,
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q70,
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q71,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381,
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430,
_theResult___fst_exp__h348593,
_theResult___fst_exp__h357316,
_theResult___fst_exp__h365898,
_theResult___fst_exp__h375082,
_theResult___fst_exp__h383718,
_theResult___fst_exp__h394292,
_theResult___fst_exp__h403013,
_theResult___fst_exp__h411595,
_theResult___fst_exp__h420779,
_theResult___fst_exp__h429415,
_theResult___fst_exp__h439987,
_theResult___fst_exp__h448708,
_theResult___fst_exp__h457290,
_theResult___fst_exp__h466474,
_theResult___fst_exp__h475110;
reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q281,
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9,
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q275,
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189;
reg [4 : 0] IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14311,
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14476;
reg [3 : 0] CASE_checkForException_3178_BITS_3_TO_0_0_chec_ETC__q234,
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279,
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q280,
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q21,
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22,
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q277,
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276,
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248,
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q249,
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6,
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7,
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2,
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3,
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14314,
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298,
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14477,
i__h708343,
i__h708503;
reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q285,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q291,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288,
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q256,
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270,
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233,
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829,
x__h288305,
x__h294075;
reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263,
CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q246,
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q302,
CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8,
CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4;
reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q267,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264,
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243,
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244,
CASE_fetchStage_pipelines_0_canDeq__2930_AND_N_ETC__q241,
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242,
CASE_guard03027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94,
CASE_guard03027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93,
CASE_guard05914_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147,
CASE_guard11957_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96,
CASE_guard11957_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95,
CASE_guard14983_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149,
CASE_guard20793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98,
CASE_guard20793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97,
CASE_guard35455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203,
CASE_guard35455_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193,
CASE_guard40015_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127,
CASE_guard40015_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126,
CASE_guard44767_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199,
CASE_guard44767_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195,
CASE_guard48621_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57,
CASE_guard48621_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56,
CASE_guard48722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129,
CASE_guard48722_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128,
CASE_guard53836_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201,
CASE_guard53836_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197,
CASE_guard57330_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59,
CASE_guard57330_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58,
CASE_guard57652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131,
CASE_guard57652_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130,
CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61,
CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60,
CASE_guard66488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133,
CASE_guard66488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132,
CASE_guard74759_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172,
CASE_guard74759_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162,
CASE_guard75096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63,
CASE_guard75096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62,
CASE_guard84071_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168,
CASE_guard84071_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164,
CASE_guard93140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170,
CASE_guard93140_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166,
CASE_guard94320_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92,
CASE_guard94320_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91,
CASE_guard96602_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145,
CASE_k72122_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6543,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6556,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6560,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6573,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6586,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6599,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6606,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6616,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6623,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5151,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5164,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5168,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5181,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5194,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5207,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5214,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5224,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5231,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7935,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7948,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7952,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7965,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7978,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7991,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7998,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8008,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8015,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10966,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11002,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11050,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11092,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11134,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8508,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8521,
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635,
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693,
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14305,
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14308,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13639,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13698,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14016,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14038,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14056,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14111,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14113,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14127,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14134,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14210,
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14222,
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14474,
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14475,
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068,
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14207,
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14234,
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656,
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14168,
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623,
SEL_ARR_fetchStage_pipelines_0_canDeq__2930_AN_ETC___d13938;
wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3344;
wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2539,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2552,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2551;
wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3039;
wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2237,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3032,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16215;
wire [457 : 0] commitStage_f_rob_data_first__4972_BITS_161_TO_ETC___d15136,
rob_deqPort_0_deq_data__4560_BITS_161_TO_98_45_ETC___d15481;
wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2034;
wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2232,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3023,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16206;
wire [321 : 0] basicExec___d12105, basicExec___d12779;
wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2029;
wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2227,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3014,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16197,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11188,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11201,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11194;
wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2024;
wire [127 : 0] b__h606169, b__h606245, b__h606346, b__h606358, x__h607170;
wire [68 : 0] execFpuSimple___d11168;
wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627,
IF_rob_deqPort_0_deq_data__4560_BITS_97_TO_96__ETC___d14724;
wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2599;
wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9285,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12620,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12621,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12629,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12630,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11946,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11947,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11955,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11956,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8455,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8463,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8471,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1679,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1680,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1687,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1688,
IF_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_d_ETC___d11256,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10052,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10766,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9286,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9996,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2596,
IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1385,
IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434,
IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386,
IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435,
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8,
_theResult___fst__h606569,
_theResult___snd__h606570,
a___1__h606183,
a___1__h606574,
a__h606021,
amoExec___d882,
b___1__h606184,
b___1__h606635,
b__h606022,
base__h711168,
base__h711188,
commitStage_rg_serial_num_4736_PLUS_IF_rob_deq_ETC___d15627,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11258,
data___1__h477611,
data___1__h478505,
data__h477099,
data__h477993,
fallthrough_pc__h668411,
fallthrough_pc__h683886,
fcsr_csr__read__h613763,
fflags_csr__read__h613738,
frm_csr__read__h613749,
mcause_csr__read__h615403,
mcounteren_csr__read__h615148,
medeleg_csr__read__h614755,
mideleg_csr__read__h614850,
mie_csr__read__h614974,
mip_csr__read__h615636,
mstatus_csr__read__h614607,
mtvec_csr__read__h615056,
n___1__h200101,
n__h195496,
n__read__h615740,
n__read__h615931,
n__read__h6607,
n__read__h724080,
next_pc__h720279,
pc__h711152,
q___1__h478580,
rVal1__h484791,
rVal2__h484792,
r___1__h478607,
res_data__h340395,
res_data__h340400,
res_data__h386097,
res_data__h386102,
res_data__h431792,
res_data__h431797,
resp_addr__h294503,
rob_deqPort_0_deq_data__4560_BITS_353_TO_290_4_ETC___d15379,
robdeqPort_0_deq_data_BITS_95_TO_32__q245,
satp_csr__read__h614464,
scause_csr__read__h614262,
scounteren_csr__read__h614124,
shiftData__h184291,
sie_csr__read__h614028,
sip_csr__read__h614401,
sstatus_csr__read__h613959,
stvec_csr__read__h614071,
upd__h3994,
upd__h5311,
upd__h6721,
upd__h724191,
v__h612270,
v__h637067,
vaddr__h184286,
x__h155119,
x__h158666,
x__h161480,
x__h163328,
x__h18215,
x__h184198,
x__h184199,
x__h20753,
x__h289750,
x__h291604,
x__h46122,
x__h484697,
x__h484698,
x__h484699,
x__h48658,
x__h606558,
x__h621197,
x__h621198,
x__h643562,
x__h643563,
x__h702237,
x__h712324,
x__h712515,
x__h723610,
x_addr__h316600,
x_quotient__h477795,
x_reg_ifc__read__h613868,
x_remainder__h477796,
y__h623923,
y__h645995,
y__h727463,
y__h729146,
y_avValue__h183364,
y_avValue__h184045,
y_avValue__h481835,
y_avValue__h482519,
y_avValue__h483196,
y_avValue__h613404,
y_avValue__h619207,
y_avValue__h638049,
y_avValue__h641582,
y_avValue_new_pc__h710944,
y_avValue_new_pc__h711130,
y_avValue_snd_snd_snd_snd_snd__h727478,
y_avValue_snd_snd_snd_snd_snd__h729195,
y_avValue_snd_snd_snd_snd_snd__h729224;
wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10764,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9994,
IF_csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_c_ETC___d15130,
IF_rob_deqPort_0_deq_data__4560_BITS_257_TO_25_ETC___d15475,
r1__read__h616908,
r1__read__h617312,
r1__read__h617842,
r1__read__h617847,
r1__read__h617866,
r1__read__h618119,
r1__read__h618285,
r1__read__h618396,
r1__read__h618401,
r1__read__h618420;
wire [61 : 0] r1__read__h616910,
r1__read__h617314,
r1__read__h617849,
r1__read__h617868,
r1__read__h618121,
r1__read__h618261,
r1__read__h618287,
r1__read__h618403,
r1__read__h618422;
wire [60 : 0] r1__read__h618123,
r1__read__h618263,
r1__read__h618289,
r1__read__h618424;
wire [59 : 0] r1__read__h616912,
r1__read__h617316,
r1__read__h617860,
r1__read__h617870,
r1__read__h618125,
r1__read__h618291,
r1__read__h618414,
r1__read__h618426;
wire [58 : 0] r1__read__h616914,
r1__read__h617318,
r1__read__h617872,
r1__read__h618127,
r1__read__h618293,
r1__read__h618428;
wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2579,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3109,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2788,
r1__read__h616916,
r1__read__h617320,
r1__read__h617874,
r1__read__h618129,
r1__read__h618265,
r1__read__h618295,
r1__read__h618430,
y__h256656;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29,
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64,
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10250,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8765,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9480,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4655,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6047,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7439,
_theResult____h348611,
_theResult____h366250,
_theResult____h394310,
_theResult____h411947,
_theResult____h440005,
_theResult____h457642,
_theResult____h505904,
_theResult____h544757,
_theResult____h584061,
_theResult___snd__h356733,
_theResult___snd__h356744,
_theResult___snd__h356746,
_theResult___snd__h356756,
_theResult___snd__h356762,
_theResult___snd__h356785,
_theResult___snd__h365329,
_theResult___snd__h365331,
_theResult___snd__h365338,
_theResult___snd__h365344,
_theResult___snd__h365367,
_theResult___snd__h374499,
_theResult___snd__h374510,
_theResult___snd__h374512,
_theResult___snd__h374522,
_theResult___snd__h374528,
_theResult___snd__h374551,
_theResult___snd__h383119,
_theResult___snd__h383133,
_theResult___snd__h383139,
_theResult___snd__h383157,
_theResult___snd__h402430,
_theResult___snd__h402441,
_theResult___snd__h402443,
_theResult___snd__h402453,
_theResult___snd__h402459,
_theResult___snd__h402482,
_theResult___snd__h411026,
_theResult___snd__h411028,
_theResult___snd__h411035,
_theResult___snd__h411041,
_theResult___snd__h411064,
_theResult___snd__h420196,
_theResult___snd__h420207,
_theResult___snd__h420209,
_theResult___snd__h420219,
_theResult___snd__h420225,
_theResult___snd__h420248,
_theResult___snd__h428816,
_theResult___snd__h428830,
_theResult___snd__h428836,
_theResult___snd__h428854,
_theResult___snd__h448125,
_theResult___snd__h448136,
_theResult___snd__h448138,
_theResult___snd__h448148,
_theResult___snd__h448154,
_theResult___snd__h448177,
_theResult___snd__h456721,
_theResult___snd__h456723,
_theResult___snd__h456730,
_theResult___snd__h456736,
_theResult___snd__h456759,
_theResult___snd__h465891,
_theResult___snd__h465902,
_theResult___snd__h465904,
_theResult___snd__h465914,
_theResult___snd__h465920,
_theResult___snd__h465943,
_theResult___snd__h474511,
_theResult___snd__h474525,
_theResult___snd__h474531,
_theResult___snd__h474549,
_theResult___snd__h504514,
_theResult___snd__h504516,
_theResult___snd__h504523,
_theResult___snd__h504529,
_theResult___snd__h504552,
_theResult___snd__h514151,
_theResult___snd__h514162,
_theResult___snd__h514164,
_theResult___snd__h514174,
_theResult___snd__h514180,
_theResult___snd__h514203,
_theResult___snd__h522919,
_theResult___snd__h522933,
_theResult___snd__h522939,
_theResult___snd__h522957,
_theResult___snd__h543367,
_theResult___snd__h543369,
_theResult___snd__h543376,
_theResult___snd__h543382,
_theResult___snd__h543405,
_theResult___snd__h553004,
_theResult___snd__h553015,
_theResult___snd__h553017,
_theResult___snd__h553027,
_theResult___snd__h553033,
_theResult___snd__h553056,
_theResult___snd__h561772,
_theResult___snd__h561786,
_theResult___snd__h561792,
_theResult___snd__h561810,
_theResult___snd__h582671,
_theResult___snd__h582673,
_theResult___snd__h582680,
_theResult___snd__h582686,
_theResult___snd__h582709,
_theResult___snd__h592308,
_theResult___snd__h592319,
_theResult___snd__h592321,
_theResult___snd__h592331,
_theResult___snd__h592337,
_theResult___snd__h592360,
_theResult___snd__h601076,
_theResult___snd__h601090,
_theResult___snd__h601096,
_theResult___snd__h601114,
r1__read__h618131,
r1__read__h618267,
r1__read__h618297,
r1__read__h618432,
result__h366863,
result__h412560,
result__h458255,
result__h506517,
result__h545370,
result__h584674,
sfd__h341006,
sfd__h386708,
sfd__h432403,
sfd__h485537,
sfd__h524531,
sfd__h563835,
sfdin__h356716,
sfdin__h374482,
sfdin__h402413,
sfdin__h420179,
sfdin__h448108,
sfdin__h465874,
sfdin__h514134,
sfdin__h552987,
sfdin__h592291,
x__h366960,
x__h412657,
x__h458352,
x__h506612,
x__h545465,
x__h584769;
wire [55 : 0] r1__read__h616918,
r1__read__h617322,
r1__read__h617876,
r1__read__h618133,
r1__read__h618299,
r1__read__h618434;
wire [54 : 0] r1__read__h616920,
r1__read__h617324,
r1__read__h617878,
r1__read__h618135,
r1__read__h618301,
r1__read__h618436;
wire [53 : 0] r1__read__h618244,
r1__read__h618269,
r1__read__h618303,
r1__read__h618438,
sfd__h504581,
sfd__h514232,
sfd__h522992,
sfd__h543434,
sfd__h553085,
sfd__h561845,
sfd__h582738,
sfd__h592389,
sfd__h601149,
value__h349233,
value__h394930,
value__h440625;
wire [52 : 0] r1__read__h618137,
r1__read__h618246,
r1__read__h618271,
r1__read__h618305,
r1__read__h618440;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10731,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10733,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9252,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9254,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9961,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9963,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10705,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10707,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10750,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10752,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9225,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9227,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9271,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9273,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9935,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9937,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9980,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9982,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993,
_theResult___fst_sfd__h489491,
_theResult___fst_sfd__h505319,
_theResult___fst_sfd__h505322,
_theResult___fst_sfd__h514970,
_theResult___fst_sfd__h514973,
_theResult___fst_sfd__h523754,
_theResult___fst_sfd__h523757,
_theResult___fst_sfd__h523766,
_theResult___fst_sfd__h523772,
_theResult___fst_sfd__h528344,
_theResult___fst_sfd__h544172,
_theResult___fst_sfd__h544175,
_theResult___fst_sfd__h553823,
_theResult___fst_sfd__h553826,
_theResult___fst_sfd__h562607,
_theResult___fst_sfd__h562610,
_theResult___fst_sfd__h562619,
_theResult___fst_sfd__h562625,
_theResult___fst_sfd__h567648,
_theResult___fst_sfd__h583476,
_theResult___fst_sfd__h583479,
_theResult___fst_sfd__h593127,
_theResult___fst_sfd__h593130,
_theResult___fst_sfd__h601911,
_theResult___fst_sfd__h601914,
_theResult___fst_sfd__h601923,
_theResult___fst_sfd__h601929,
_theResult___sfd__h505219,
_theResult___sfd__h514870,
_theResult___sfd__h523654,
_theResult___sfd__h544072,
_theResult___sfd__h553723,
_theResult___sfd__h562507,
_theResult___sfd__h583376,
_theResult___sfd__h593027,
_theResult___sfd__h601811,
_theResult___snd_fst_sfd__h485491,
_theResult___snd_fst_sfd__h505325,
_theResult___snd_fst_sfd__h523760,
_theResult___snd_fst_sfd__h524485,
_theResult___snd_fst_sfd__h544178,
_theResult___snd_fst_sfd__h562613,
_theResult___snd_fst_sfd__h563789,
_theResult___snd_fst_sfd__h583482,
_theResult___snd_fst_sfd__h601917,
out___1_sfd__h485239,
out___1_sfd__h524233,
out___1_sfd__h563537,
out_sfd__h505222,
out_sfd__h514873,
out_sfd__h523657,
out_sfd__h544075,
out_sfd__h553726,
out_sfd__h562510,
out_sfd__h583379,
out_sfd__h593030,
out_sfd__h601814;
wire [50 : 0] r1__read__h616922, r1__read__h618139;
wire [49 : 0] r1__read__h618248;
wire [48 : 0] r1__read__h616924, r1__read__h618141, r1__read__h618250;
wire [46 : 0] r1__read__h616926, r1__read__h618143;
wire [45 : 0] r1__read__h616928, r1__read__h618145;
wire [44 : 0] r1__read__h616930, r1__read__h618147;
wire [43 : 0] r1__read__h616932, r1__read__h618149;
wire [42 : 0] r1__read__h618151;
wire [41 : 0] r1__read__h618153;
wire [40 : 0] r1__read__h618155;
wire [37 : 0] IF_fetchStage_pipelines_0_first__2932_BIT_160__ETC___d14317,
IF_fetchStage_pipelines_1_first__2941_BIT_160__ETC___d14480;
wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11,
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q13,
data77099_BITS_31_TO_0__q10,
data77993_BITS_31_TO_0__q14,
imm__h659436,
r1__read__h616934,
r1__read__h618157,
x__h194721,
x__h340410,
x__h386112,
x__h431807,
x__h76067,
x_data__h65916,
x_data_imm__h679352,
x_data_imm__h694985;
wire [29 : 0] r1__read__h616936, r1__read__h618159;
wire [27 : 0] r1__read__h618161;
wire [24 : 0] NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14363,
sfd__h356814,
sfd__h365396,
sfd__h374580,
sfd__h383192,
sfd__h402511,
sfd__h411093,
sfd__h420277,
sfd__h428889,
sfd__h448206,
sfd__h456788,
sfd__h465972,
sfd__h474584,
value__h490120,
value__h528973,
value__h568277;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5054,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5056,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6446,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6448,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7838,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7840,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5100,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5102,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6492,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6494,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7884,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7886,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5073,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5075,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5119,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5121,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6465,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6467,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6511,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6513,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7857,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7859,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7903,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7905,
_theResult___fst_sfd__h357320,
_theResult___fst_sfd__h365902,
_theResult___fst_sfd__h375086,
_theResult___fst_sfd__h383722,
_theResult___fst_sfd__h383731,
_theResult___fst_sfd__h383737,
_theResult___fst_sfd__h403017,
_theResult___fst_sfd__h411599,
_theResult___fst_sfd__h420783,
_theResult___fst_sfd__h429419,
_theResult___fst_sfd__h429428,
_theResult___fst_sfd__h429434,
_theResult___fst_sfd__h448712,
_theResult___fst_sfd__h457294,
_theResult___fst_sfd__h466478,
_theResult___fst_sfd__h475114,
_theResult___fst_sfd__h475123,
_theResult___fst_sfd__h475129,
_theResult___sfd__h357239,
_theResult___sfd__h365821,
_theResult___sfd__h375005,
_theResult___sfd__h383641,
_theResult___sfd__h383743,
_theResult___sfd__h402936,
_theResult___sfd__h411518,
_theResult___sfd__h420702,
_theResult___sfd__h429338,
_theResult___sfd__h429440,
_theResult___sfd__h448631,
_theResult___sfd__h457213,
_theResult___sfd__h466397,
_theResult___sfd__h475033,
_theResult___sfd__h475135,
_theResult___snd_fst_sfd__h340956,
_theResult___snd_fst_sfd__h365905,
_theResult___snd_fst_sfd__h383725,
_theResult___snd_fst_sfd__h386658,
_theResult___snd_fst_sfd__h411602,
_theResult___snd_fst_sfd__h429422,
_theResult___snd_fst_sfd__h432353,
_theResult___snd_fst_sfd__h457297,
_theResult___snd_fst_sfd__h475117,
f1_sfd__h485176,
f2_sfd__h524170,
f3_sfd__h563474,
out_f_sfd__h384020,
out_f_sfd__h429717,
out_f_sfd__h475412,
out_sfd__h357242,
out_sfd__h365824,
out_sfd__h375008,
out_sfd__h383644,
out_sfd__h402939,
out_sfd__h411521,
out_sfd__h420705,
out_sfd__h429341,
out_sfd__h448634,
out_sfd__h457216,
out_sfd__h466400,
out_sfd__h475036;
wire [19 : 0] r1__read__h618096;
wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002,
_theResult____h655256,
enabled_ints___1__h655781,
enabled_ints__h655828,
pend_ints__h655254,
y__h655793;
wire [13 : 0] r1__read_BITS_13_TO_0___h655804;
wire [12 : 0] fetchStage_pipelines_1_first__2941_BIT_173_375_ETC___d13842,
rob_deqPort_0_deq_data__4560_BIT_181_4634_CONC_ETC___d14717;
wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10543,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9058,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9773,
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873,
IF_fetchStage_pipelines_0_first__2932_BIT_173__ETC___d13205,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108,
_0_CONCAT_csrf_external_int_en_vec_3_read__1851_ETC___d12975,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10246,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8761,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9476,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4651,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6043,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7435,
renaming_spec_bits__h687315,
result__h650833,
result__h650884,
spec_bits__h690442,
w__h650828,
x__h366993,
x__h412690,
x__h458385,
x__h506645,
x__h545498,
x__h584802,
x__h650832,
x__h650883,
y__h650862,
y__h690455,
y_avValue_fst__h683715,
y_avValue_fst__h683744,
y_avValue_fst__h683778;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10648,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10650,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9168,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9170,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9878,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9880,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10610,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10612,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10679,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10681,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9125,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9127,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9199,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9201,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9840,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9842,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9909,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9911,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180,
_theResult___exp__h505218,
_theResult___exp__h514869,
_theResult___exp__h523653,
_theResult___exp__h544071,
_theResult___exp__h553722,
_theResult___exp__h562506,
_theResult___exp__h583375,
_theResult___exp__h593026,
_theResult___exp__h601810,
_theResult___fst_exp__h489490,
_theResult___fst_exp__h504554,
_theResult___fst_exp__h504560,
_theResult___fst_exp__h504563,
_theResult___fst_exp__h505318,
_theResult___fst_exp__h505321,
_theResult___fst_exp__h514140,
_theResult___fst_exp__h514205,
_theResult___fst_exp__h514211,
_theResult___fst_exp__h514214,
_theResult___fst_exp__h514969,
_theResult___fst_exp__h514972,
_theResult___fst_exp__h522925,
_theResult___fst_exp__h522964,
_theResult___fst_exp__h522970,
_theResult___fst_exp__h522973,
_theResult___fst_exp__h523753,
_theResult___fst_exp__h523756,
_theResult___fst_exp__h523765,
_theResult___fst_exp__h523768,
_theResult___fst_exp__h528343,
_theResult___fst_exp__h543407,
_theResult___fst_exp__h543413,
_theResult___fst_exp__h543416,
_theResult___fst_exp__h544171,
_theResult___fst_exp__h544174,
_theResult___fst_exp__h552993,
_theResult___fst_exp__h553058,
_theResult___fst_exp__h553064,
_theResult___fst_exp__h553067,
_theResult___fst_exp__h553822,
_theResult___fst_exp__h553825,
_theResult___fst_exp__h561778,
_theResult___fst_exp__h561817,
_theResult___fst_exp__h561823,
_theResult___fst_exp__h561826,
_theResult___fst_exp__h562606,
_theResult___fst_exp__h562609,
_theResult___fst_exp__h562618,
_theResult___fst_exp__h562621,
_theResult___fst_exp__h567647,
_theResult___fst_exp__h582711,
_theResult___fst_exp__h582717,
_theResult___fst_exp__h582720,
_theResult___fst_exp__h583475,
_theResult___fst_exp__h583478,
_theResult___fst_exp__h592297,
_theResult___fst_exp__h592362,
_theResult___fst_exp__h592368,
_theResult___fst_exp__h592371,
_theResult___fst_exp__h593126,
_theResult___fst_exp__h593129,
_theResult___fst_exp__h601082,
_theResult___fst_exp__h601121,
_theResult___fst_exp__h601127,
_theResult___fst_exp__h601130,
_theResult___fst_exp__h601910,
_theResult___fst_exp__h601913,
_theResult___fst_exp__h601922,
_theResult___fst_exp__h601925,
_theResult___snd_fst_exp__h505324,
_theResult___snd_fst_exp__h523759,
_theResult___snd_fst_exp__h544177,
_theResult___snd_fst_exp__h562612,
_theResult___snd_fst_exp__h583481,
_theResult___snd_fst_exp__h601916,
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72,
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107,
din_inc___2_exp__h523813,
din_inc___2_exp__h523848,
din_inc___2_exp__h523874,
din_inc___2_exp__h562666,
din_inc___2_exp__h562701,
din_inc___2_exp__h562727,
din_inc___2_exp__h601970,
din_inc___2_exp__h602005,
din_inc___2_exp__h602031,
out_exp__h505221,
out_exp__h514872,
out_exp__h523656,
out_exp__h544074,
out_exp__h553725,
out_exp__h562509,
out_exp__h583378,
out_exp__h593029,
out_exp__h601813;
wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4969,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6361,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7753;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4407,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5799,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7191,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4954,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4956,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6346,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6348,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7738,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7740,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4629,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4631,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5023,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5025,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6021,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6023,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6415,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6417,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7413,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7415,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7807,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7809,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113,
_0_CONCAT_csrf_external_int_en_vec_3_read__1851_ETC___d12970,
_theResult___exp__h357238,
_theResult___exp__h365820,
_theResult___exp__h375004,
_theResult___exp__h383640,
_theResult___exp__h383742,
_theResult___exp__h402935,
_theResult___exp__h411517,
_theResult___exp__h420701,
_theResult___exp__h429337,
_theResult___exp__h429439,
_theResult___exp__h448630,
_theResult___exp__h457212,
_theResult___exp__h466396,
_theResult___exp__h475032,
_theResult___exp__h475134,
_theResult___fst_exp__h356722,
_theResult___fst_exp__h356787,
_theResult___fst_exp__h356793,
_theResult___fst_exp__h356796,
_theResult___fst_exp__h357319,
_theResult___fst_exp__h365369,
_theResult___fst_exp__h365375,
_theResult___fst_exp__h365378,
_theResult___fst_exp__h365901,
_theResult___fst_exp__h374488,
_theResult___fst_exp__h374553,
_theResult___fst_exp__h374559,
_theResult___fst_exp__h374562,
_theResult___fst_exp__h375085,
_theResult___fst_exp__h383125,
_theResult___fst_exp__h383164,
_theResult___fst_exp__h383170,
_theResult___fst_exp__h383173,
_theResult___fst_exp__h383721,
_theResult___fst_exp__h383730,
_theResult___fst_exp__h383733,
_theResult___fst_exp__h402419,
_theResult___fst_exp__h402484,
_theResult___fst_exp__h402490,
_theResult___fst_exp__h402493,
_theResult___fst_exp__h403016,
_theResult___fst_exp__h411066,
_theResult___fst_exp__h411072,
_theResult___fst_exp__h411075,
_theResult___fst_exp__h411598,
_theResult___fst_exp__h420185,
_theResult___fst_exp__h420250,
_theResult___fst_exp__h420256,
_theResult___fst_exp__h420259,
_theResult___fst_exp__h420782,
_theResult___fst_exp__h428822,
_theResult___fst_exp__h428861,
_theResult___fst_exp__h428867,
_theResult___fst_exp__h428870,
_theResult___fst_exp__h429418,
_theResult___fst_exp__h429427,
_theResult___fst_exp__h429430,
_theResult___fst_exp__h448114,
_theResult___fst_exp__h448179,
_theResult___fst_exp__h448185,
_theResult___fst_exp__h448188,
_theResult___fst_exp__h448711,
_theResult___fst_exp__h456761,
_theResult___fst_exp__h456767,
_theResult___fst_exp__h456770,
_theResult___fst_exp__h457293,
_theResult___fst_exp__h465880,
_theResult___fst_exp__h465945,
_theResult___fst_exp__h465951,
_theResult___fst_exp__h465954,
_theResult___fst_exp__h466477,
_theResult___fst_exp__h474517,
_theResult___fst_exp__h474556,
_theResult___fst_exp__h474562,
_theResult___fst_exp__h474565,
_theResult___fst_exp__h475113,
_theResult___fst_exp__h475122,
_theResult___fst_exp__h475125,
_theResult___snd_fst_exp__h365904,
_theResult___snd_fst_exp__h383724,
_theResult___snd_fst_exp__h411601,
_theResult___snd_fst_exp__h429421,
_theResult___snd_fst_exp__h457296,
_theResult___snd_fst_exp__h475116,
din_inc___2_exp__h383755,
din_inc___2_exp__h383779,
din_inc___2_exp__h383809,
din_inc___2_exp__h383833,
din_inc___2_exp__h429452,
din_inc___2_exp__h429476,
din_inc___2_exp__h429506,
din_inc___2_exp__h429530,
din_inc___2_exp__h475147,
din_inc___2_exp__h475171,
din_inc___2_exp__h475201,
din_inc___2_exp__h475225,
f1_exp85175_MINUS_127__q136,
f1_exp__h485175,
f2_exp24169_MINUS_127__q176,
f2_exp__h524169,
f3_exp63473_MINUS_127__q153,
f3_exp__h563473,
out_exp__h357241,
out_exp__h365823,
out_exp__h375007,
out_exp__h383643,
out_exp__h402938,
out_exp__h411520,
out_exp__h420704,
out_exp__h429340,
out_exp__h448633,
out_exp__h457215,
out_exp__h466399,
out_exp__h475035,
out_f_exp__h384019,
out_f_exp__h429716,
out_f_exp__h475411,
x__h616893;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4344,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5736,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7128,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10492,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9007,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9722,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4895,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6287,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7679,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10195,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8695,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9425,
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5967,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4575,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7359,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2173,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16241,
x__h184420,
x__h711183;
wire [4 : 0] IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14533,
IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15817,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5266,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6658,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8050,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10870,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10911,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10955,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5295,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6687,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8079,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10853,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10894,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10938,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5278,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6670,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8062,
checkForException___d13178,
checkForException___d13864,
fflags__h729123,
res_fflags__h340396,
res_fflags__h386098,
res_fflags__h431793,
rob_deqPort_0_deq_data__4560_BIT_166_4576_CONC_ETC___d14625,
rs1__h659435,
x__h155113,
x__h158660,
x__h161476,
x__h289738,
y_avValue_fst__h727013,
y_avValue_fst__h729038,
y_avValue_fst__h729066;
wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1876,
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1878,
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1880,
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1882,
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1884,
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1886,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13366,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13367,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13368,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13369,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13370,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13371,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13372,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13373,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13374,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13375,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13376,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13377,
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13378,
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411,
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820,
IF_NOT_renameStage_rg_m_halt_req_2959_BIT_4_29_ETC___d13451,
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2930,
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263,
cause_code__h708328,
vm_mode_reg__read__h618102;
wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2568,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2887,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220,
_theResult_____2__h299047,
dcsr_cause__h707848,
next_deqP___1__h299326,
v__h298467,
v__h298698,
x__h304677,
x_decodeInfo_frm__h659119;
wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2883,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216,
IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15838,
IF_sfdin02413_BIT_33_THEN_2_ELSE_0__q65,
IF_sfdin14134_BIT_4_THEN_2_ELSE_0__q139,
IF_sfdin20179_BIT_33_THEN_2_ELSE_0__q75,
IF_sfdin48108_BIT_33_THEN_2_ELSE_0__q100,
IF_sfdin52987_BIT_4_THEN_2_ELSE_0__q179,
IF_sfdin56716_BIT_33_THEN_2_ELSE_0__q30,
IF_sfdin65874_BIT_33_THEN_2_ELSE_0__q110,
IF_sfdin74482_BIT_33_THEN_2_ELSE_0__q40,
IF_sfdin92291_BIT_4_THEN_2_ELSE_0__q156,
IF_theResult___snd01076_BIT_4_THEN_2_ELSE_0__q159,
IF_theResult___snd04514_BIT_4_THEN_2_ELSE_0__q135,
IF_theResult___snd11026_BIT_33_THEN_2_ELSE_0__q67,
IF_theResult___snd22919_BIT_4_THEN_2_ELSE_0__q142,
IF_theResult___snd28816_BIT_33_THEN_2_ELSE_0__q80,
IF_theResult___snd43367_BIT_4_THEN_2_ELSE_0__q175,
IF_theResult___snd56721_BIT_33_THEN_2_ELSE_0__q102,
IF_theResult___snd61772_BIT_4_THEN_2_ELSE_0__q182,
IF_theResult___snd65329_BIT_33_THEN_2_ELSE_0__q32,
IF_theResult___snd74511_BIT_33_THEN_2_ELSE_0__q115,
IF_theResult___snd82671_BIT_4_THEN_2_ELSE_0__q152,
IF_theResult___snd83119_BIT_33_THEN_2_ELSE_0__q45,
guard__h348621,
guard__h357330,
guard__h366260,
guard__h375096,
guard__h394320,
guard__h403027,
guard__h411957,
guard__h420793,
guard__h440015,
guard__h448722,
guard__h457652,
guard__h466488,
guard__h496602,
guard__h505914,
guard__h514983,
guard__h535455,
guard__h544767,
guard__h553836,
guard__h574759,
guard__h584071,
guard__h593140,
prv__h730760,
prv__h730804,
r1__read_BITS_13_TO_12___h659304,
sbIdx__h158539,
v__h607240,
v__h607250,
v__h608281,
x__h720450,
x__h729365,
x_prv__h711252,
x_prv__h720900,
y_avValue_snd_snd_snd_fst__h727472,
y_avValue_snd_snd_snd_fst__h729189,
y_avValue_snd_snd_snd_fst__h729218;
wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5166,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5216,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6558,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6608,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7950,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d8000,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10034,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10536,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10803,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9051,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9766,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10019,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10046,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10582,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10788,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10815,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9097,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812,
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13220,
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13922,
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13959,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10050,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10586,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10819,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10874,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10915,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10959,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10974,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10984,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10995,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11014,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11028,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11043,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11060,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11072,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11085,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11102,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11114,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11127,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9101,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9816,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10241,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8756,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9471,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12405,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12406,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12407,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12432,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12433,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12434,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11546,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11547,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11548,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11573,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11574,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11575,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8338,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8362,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8363,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8364,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8388,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8389,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8390,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1620,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1621,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1622,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1646,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1647,
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1648,
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2115,
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2132,
IF_NOT_fetchStage_pipelines_0_canDeq__2930_293_ETC___d14074,
IF_NOT_fetchStage_pipelines_0_canDeq__2930_293_ETC___d14082,
IF_NOT_fetchStage_pipelines_1_first__2941_BITS_ETC___d13997,
IF_NOT_fetchStage_pipelines_1_first__2941_BITS_ETC___d14081,
IF_NOT_rob_deqPort_1_deq_data__5517_BIT_25_551_ETC___d15829,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10048,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10584,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10817,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11012,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11026,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11041,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11058,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11070,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11083,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11100,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11112,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11125,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9099,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9814,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5196,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5233,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5324,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5337,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5350,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6588,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6625,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6716,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6729,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6742,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7980,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8017,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8108,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8121,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8134,
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2348_ETC___d12381,
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2348_ETC___d12417,
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1489_ETC___d11522,
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1489_ETC___d11558,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8312,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8347,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8373,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6629,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6627,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6691,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6702,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6718,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6731,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6744,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5235,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5299,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5310,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5326,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5339,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5352,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8019,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8083,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8094,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8110,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8123,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8136,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5237,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8021,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10021,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10790,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8542,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2113,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2133,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2136,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3143,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3155,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3235,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3250,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3257,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3277,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3101,
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_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6673,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6698,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6725,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8065,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8090,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354,
_dfoo12,
_dfoo16,
_dfoo18,
_dfoo2,
_dfoo20,
_dfoo24,
_dfoo26,
_dfoo32,
_dfoo7,
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset,
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset,
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset,
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset,
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset,
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset,
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
_dor1coreFix_memExe_bypassWire_2$EN_wset,
_dor1coreFix_memExe_bypassWire_3$EN_wset,
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset,
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset,
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put,
_dor1rf$EN_write_0_wr,
_dor1rf$EN_write_1_wr,
_dor1sbAggr$EN_setReady_3_put,
_dor1sbCons$EN_setReady_0_put,
_dor1sbCons$EN_setReady_1_put,
_theResult_____2__h307043,
_theResult_____2__h313037,
_theResult_____2__h320891,
_theResult_____2__h331235,
_theResult_____2__h334460,
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873,
coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12373,
coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12414,
coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12386,
coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12420,
coreFix_aluExe_0_bypassWire_2_wget__2392_BITS__ETC___d12394,
coreFix_aluExe_0_bypassWire_2_wget__2392_BITS__ETC___d12424,
coreFix_aluExe_0_bypassWire_3_wget__2399_BITS__ETC___d12401,
coreFix_aluExe_0_bypassWire_3_wget__2399_BITS__ETC___d12428,
coreFix_aluExe_0_dispToRegQ_RDY_first__2348_AN_ETC___d12439,
coreFix_aluExe_0_exeToFinQ_RDY_first__2815_AND_ETC___d12855,
coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619,
coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11514,
coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11555,
coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11527,
coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11561,
coreFix_aluExe_1_bypassWire_2_wget__1533_BITS__ETC___d11535,
coreFix_aluExe_1_bypassWire_2_wget__1533_BITS__ETC___d11565,
coreFix_aluExe_1_bypassWire_3_wget__1540_BITS__ETC___d11542,
coreFix_aluExe_1_bypassWire_3_wget__1540_BITS__ETC___d11569,
coreFix_aluExe_1_dispToRegQ_RDY_first__1489_AN_ETC___d11580,
coreFix_aluExe_1_exeToFinQ_RDY_first__2141_AND_ETC___d12182,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8304,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8344,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8370,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8317,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8350,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8376,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8325,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8354,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8380,
coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8332,
coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8358,
coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8384,
coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first__2_ETC___d8396,
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5369,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3977,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6761,
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8539,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8153,
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d10964,
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11000,
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11048,
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11090,
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11132,
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14193,
coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588,
coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628,
coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1601,
coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1634,
coreFix_memExe_bypassWire_2_wget__607_BITS_70__ETC___d1609,
coreFix_memExe_bypassWire_2_wget__607_BITS_70__ETC___d1638,
coreFix_memExe_bypassWire_3_wget__614_BITS_70__ETC___d1616,
coreFix_memExe_bypassWire_3_wget__614_BITS_70__ETC___d1642,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2606,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3164,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3267,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2099,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2822,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2589,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2594,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2611,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2628,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2648,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2672,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2678,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2680,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2715,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2727,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2738,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2758,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2891,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2895,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2899,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2904,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2908,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2913,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2917,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2922,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2934,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2938,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2942,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3438,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3534,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1937,
coreFix_memExe_dTlb_procResp__741_BITS_105_TO__ETC___d1895,
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1751,
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1752,
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1756,
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1759,
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760,
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3856,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3762,
coreFix_memExe_regToExeQ_RDY_enq__564_AND_core_ETC___d1654,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1228,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1232,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1237,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1241,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3671,
coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14875,
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13213,
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13676,
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13957,
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936,
csrf_prv_reg_read__2962_ULE_1___d14914,
csrf_prv_reg_read__2962_ULT_IF_fetchStage_pipe_ETC___d13210,
csrf_rg_dcsr_read__1900_BIT_2_3230_OR_NOT_fetc_ETC___d13672,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13900,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14042,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14060,
f_csr_rsps_i_notFull__5945_AND_f_csr_reqs_firs_ETC___d16040,
fetchStage_RDY_pipelines_1_deq__2944_AND_NOT_f_ETC___d14244,
fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14184,
fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14266,
fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14372,
fetchStage_pipelines_0_canDeq__2930_AND_fetchS_ETC___d14254,
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14190,
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14197,
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14219,
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14231,
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14523,
fetchStage_pipelines_0_canDeq__2930_AND_specTa_ETC___d14349,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d13208,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d13911,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14010,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14122,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14128,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14145,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14157,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14164,
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14180,
fetchStage_pipelines_0_first__2932_BITS_199_TO_ETC___d13683,
fetchStage_pipelines_0_first__2932_BIT_68_2961_ETC___d14001,
fetchStage_pipelines_1_first__2941_BITS_194_TO_ETC___d14139,
fetchStage_pipelines_1_first__2941_BITS_199_TO_ETC___d14151,
guard__h366858,
guard__h412555,
guard__h458250,
guard__h506512,
guard__h545365,
guard__h584669,
idx__h687446,
k__h672122,
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444,
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836,
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312,
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153,
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13223,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13512,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13530,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14258,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14260,
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747,
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606,
msip__h75952,
next_deqP___1__h307322,
next_deqP___1__h313603,
next_deqP___1__h321457,
next_deqP___1__h331514,
next_deqP___1__h334739,
r1__read_BIT_20___h659964,
regRenamingTable_RDY_rename_0_getRename__3468__ETC___d14107,
regRenamingTable_RDY_rename_1_getRename__4170__ETC___d14188,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13989,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14136,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14278,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14291,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14296,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14301,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14321,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14325,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14331,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14335,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14343,
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14521,
regRenamingTable_rename_1_canRename__3704_AND__ETC___d13904,
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14046,
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14064,
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400,
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_N_ETC___d13236,
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_N_ETC___d13466,
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d13925,
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d13965,
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14006,
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14086,
rg_core_run_state_read__3226_EQ_2_3227_AND_NOT_ETC___d15884,
rob_RDY_deqPort_0_deq_data__4557_AND_rob_RDY_d_ETC___d15204,
rob_RDY_enqPort_0_enq__2954_AND_regRenamingTab_ETC___d13476,
tsr_val__h723699,
tvm_val__h723701,
v__h301812,
v__h302330,
v__h312326,
v__h312557,
v__h316202,
v__h316433,
v__h330803,
v__h331034,
v__h334028,
v__h334259,
x__h606584;
// action method coreReq_start
assign RDY_coreReq_start = 1'd1 ;
assign CAN_FIRE_coreReq_start = 1'd1 ;
assign WILL_FIRE_coreReq_start = EN_coreReq_start ;
// action method coreReq_perfReq
assign RDY_coreReq_perfReq = perfReqQ$FULL_N ;
assign CAN_FIRE_coreReq_perfReq = perfReqQ$FULL_N ;
assign WILL_FIRE_coreReq_perfReq = EN_coreReq_perfReq ;
// actionvalue method coreIndInv_perfResp
assign coreIndInv_perfResp = { perfReqQ$D_OUT, 64'd0 } ;
assign RDY_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
assign CAN_FIRE_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
assign WILL_FIRE_coreIndInv_perfResp = EN_coreIndInv_perfResp ;
// action method coreIndInv_terminate
assign RDY_coreIndInv_terminate = csrf_terminate_module_terminateQ$EMPTY_N ;
assign CAN_FIRE_coreIndInv_terminate =
csrf_terminate_module_terminateQ$EMPTY_N ;
assign WILL_FIRE_coreIndInv_terminate = EN_coreIndInv_terminate ;
// value method dCacheToParent_rsToP_notEmpty
assign dCacheToParent_rsToP_notEmpty =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign RDY_dCacheToParent_rsToP_notEmpty = 1'd1 ;
// action method dCacheToParent_rsToP_deq
assign RDY_dCacheToParent_rsToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign CAN_FIRE_dCacheToParent_rsToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign WILL_FIRE_dCacheToParent_rsToP_deq = EN_dCacheToParent_rsToP_deq ;
// value method dCacheToParent_rsToP_first
assign dCacheToParent_rsToP_first =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263,
!CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16215 } ;
assign RDY_dCacheToParent_rsToP_first =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
// value method dCacheToParent_rqToP_notEmpty
assign dCacheToParent_rqToP_notEmpty =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign RDY_dCacheToParent_rqToP_notEmpty = 1'd1 ;
// action method dCacheToParent_rqToP_deq
assign RDY_dCacheToParent_rqToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign CAN_FIRE_dCacheToParent_rqToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign WILL_FIRE_dCacheToParent_rqToP_deq = EN_dCacheToParent_rqToP_deq ;
// value method dCacheToParent_rqToP_first
assign dCacheToParent_rqToP_first =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16241 } ;
assign RDY_dCacheToParent_rqToP_first =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
// value method dCacheToParent_fromP_notFull
assign dCacheToParent_fromP_notFull =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign RDY_dCacheToParent_fromP_notFull = 1'd1 ;
// action method dCacheToParent_fromP_enq
assign RDY_dCacheToParent_fromP_enq =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign CAN_FIRE_dCacheToParent_fromP_enq =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign WILL_FIRE_dCacheToParent_fromP_enq = EN_dCacheToParent_fromP_enq ;
// value method iCacheToParent_rsToP_notEmpty
assign iCacheToParent_rsToP_notEmpty =
fetchStage$iMemIfc_to_parent_rsToP_notEmpty ;
assign RDY_iCacheToParent_rsToP_notEmpty = 1'd1 ;
// action method iCacheToParent_rsToP_deq
assign RDY_iCacheToParent_rsToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
assign CAN_FIRE_iCacheToParent_rsToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
assign WILL_FIRE_iCacheToParent_rsToP_deq = EN_iCacheToParent_rsToP_deq ;
// value method iCacheToParent_rsToP_first
assign iCacheToParent_rsToP_first =
fetchStage$iMemIfc_to_parent_rsToP_first ;
assign RDY_iCacheToParent_rsToP_first =
fetchStage$RDY_iMemIfc_to_parent_rsToP_first ;
// value method iCacheToParent_rqToP_notEmpty
assign iCacheToParent_rqToP_notEmpty =
fetchStage$iMemIfc_to_parent_rqToP_notEmpty ;
assign RDY_iCacheToParent_rqToP_notEmpty = 1'd1 ;
// action method iCacheToParent_rqToP_deq
assign RDY_iCacheToParent_rqToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
assign CAN_FIRE_iCacheToParent_rqToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
assign WILL_FIRE_iCacheToParent_rqToP_deq = EN_iCacheToParent_rqToP_deq ;
// value method iCacheToParent_rqToP_first
assign iCacheToParent_rqToP_first =
fetchStage$iMemIfc_to_parent_rqToP_first ;
assign RDY_iCacheToParent_rqToP_first =
fetchStage$RDY_iMemIfc_to_parent_rqToP_first ;
// value method iCacheToParent_fromP_notFull
assign iCacheToParent_fromP_notFull =
fetchStage$iMemIfc_to_parent_fromP_notFull ;
assign RDY_iCacheToParent_fromP_notFull = 1'd1 ;
// action method iCacheToParent_fromP_enq
assign RDY_iCacheToParent_fromP_enq =
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
assign CAN_FIRE_iCacheToParent_fromP_enq =
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
assign WILL_FIRE_iCacheToParent_fromP_enq = EN_iCacheToParent_fromP_enq ;
// value method tlbToMem_memReq_notEmpty
assign tlbToMem_memReq_notEmpty = l2Tlb$toMem_memReq_notEmpty ;
assign RDY_tlbToMem_memReq_notEmpty = 1'd1 ;
// action method tlbToMem_memReq_deq
assign RDY_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
assign CAN_FIRE_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
assign WILL_FIRE_tlbToMem_memReq_deq = EN_tlbToMem_memReq_deq ;
// value method tlbToMem_memReq_first
assign tlbToMem_memReq_first = l2Tlb$toMem_memReq_first ;
assign RDY_tlbToMem_memReq_first = l2Tlb$RDY_toMem_memReq_first ;
// value method tlbToMem_respLd_notFull
assign tlbToMem_respLd_notFull = l2Tlb$toMem_respLd_notFull ;
assign RDY_tlbToMem_respLd_notFull = 1'd1 ;
// action method tlbToMem_respLd_enq
assign RDY_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
assign CAN_FIRE_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
assign WILL_FIRE_tlbToMem_respLd_enq = EN_tlbToMem_respLd_enq ;
// value method mmioToPlatform_cRq_notEmpty
assign mmioToPlatform_cRq_notEmpty = !mmio_cRqQ_empty ;
assign RDY_mmioToPlatform_cRq_notEmpty = 1'd1 ;
// action method mmioToPlatform_cRq_deq
assign RDY_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
assign CAN_FIRE_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
assign WILL_FIRE_mmioToPlatform_cRq_deq = EN_mmioToPlatform_cRq_deq ;
// value method mmioToPlatform_cRq_first
assign mmioToPlatform_cRq_first =
{ mmio_cRqQ_data_0[141:78],
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9,
mmio_cRqQ_data_0[71:0] } ;
assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ;
// value method mmioToPlatform_pRs_notFull
assign mmioToPlatform_pRs_notFull = !mmio_pRsQ_full ;
assign RDY_mmioToPlatform_pRs_notFull = 1'd1 ;
// action method mmioToPlatform_pRs_enq
assign RDY_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
assign CAN_FIRE_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
assign WILL_FIRE_mmioToPlatform_pRs_enq = EN_mmioToPlatform_pRs_enq ;
// value method mmioToPlatform_pRq_notFull
assign mmioToPlatform_pRq_notFull = !mmio_pRqQ_full ;
assign RDY_mmioToPlatform_pRq_notFull = 1'd1 ;
// action method mmioToPlatform_pRq_enq
assign RDY_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
assign CAN_FIRE_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
assign WILL_FIRE_mmioToPlatform_pRq_enq = EN_mmioToPlatform_pRq_enq ;
// value method mmioToPlatform_cRs_notEmpty
assign mmioToPlatform_cRs_notEmpty = !mmio_cRsQ_empty ;
assign RDY_mmioToPlatform_cRs_notEmpty = 1'd1 ;
// action method mmioToPlatform_cRs_deq
assign RDY_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
assign CAN_FIRE_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
assign WILL_FIRE_mmioToPlatform_cRs_deq = EN_mmioToPlatform_cRs_deq ;
// value method mmioToPlatform_cRs_first
assign mmioToPlatform_cRs_first = mmio_cRsQ_data_0 ;
assign RDY_mmioToPlatform_cRs_first = !mmio_cRsQ_empty ;
// action method mmioToPlatform_setTime
assign RDY_mmioToPlatform_setTime = 1'd1 ;
assign CAN_FIRE_mmioToPlatform_setTime = 1'd1 ;
assign WILL_FIRE_mmioToPlatform_setTime = EN_mmioToPlatform_setTime ;
// actionvalue method sendDoStats
assign sendDoStats = csrf_stats_module_writeQ$D_OUT ;
assign RDY_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
assign CAN_FIRE_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
assign WILL_FIRE_sendDoStats = EN_sendDoStats ;
// action method recvDoStats
assign RDY_recvDoStats = 1'd1 ;
assign CAN_FIRE_recvDoStats = 1'd1 ;
assign WILL_FIRE_recvDoStats = EN_recvDoStats ;
// actionvalue method deadlock_dCacheCRqStuck_get
assign deadlock_dCacheCRqStuck_get = 73'h0AAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_dCacheCRqStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_dCacheCRqStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_dCacheCRqStuck_get =
EN_deadlock_dCacheCRqStuck_get ;
// actionvalue method deadlock_dCachePRqStuck_get
assign deadlock_dCachePRqStuck_get = 68'hAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_dCachePRqStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_dCachePRqStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_dCachePRqStuck_get =
EN_deadlock_dCachePRqStuck_get ;
// actionvalue method deadlock_iCacheCRqStuck_get
assign deadlock_iCacheCRqStuck_get = fetchStage$iMemIfc_cRqStuck_get ;
assign RDY_deadlock_iCacheCRqStuck_get =
fetchStage$RDY_iMemIfc_cRqStuck_get ;
assign CAN_FIRE_deadlock_iCacheCRqStuck_get =
fetchStage$RDY_iMemIfc_cRqStuck_get ;
assign WILL_FIRE_deadlock_iCacheCRqStuck_get =
EN_deadlock_iCacheCRqStuck_get ;
// actionvalue method deadlock_iCachePRqStuck_get
assign deadlock_iCachePRqStuck_get = fetchStage$iMemIfc_pRqStuck_get ;
assign RDY_deadlock_iCachePRqStuck_get =
fetchStage$RDY_iMemIfc_pRqStuck_get ;
assign CAN_FIRE_deadlock_iCachePRqStuck_get =
fetchStage$RDY_iMemIfc_pRqStuck_get ;
assign WILL_FIRE_deadlock_iCachePRqStuck_get =
EN_deadlock_iCachePRqStuck_get ;
// actionvalue method deadlock_renameInstStuck_get
assign deadlock_renameInstStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_renameInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_renameInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_renameInstStuck_get =
EN_deadlock_renameInstStuck_get ;
// actionvalue method deadlock_renameCorrectPathStuck_get
assign deadlock_renameCorrectPathStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_renameCorrectPathStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_renameCorrectPathStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_renameCorrectPathStuck_get =
EN_deadlock_renameCorrectPathStuck_get ;
// actionvalue method deadlock_commitInstStuck_get
assign deadlock_commitInstStuck_get =
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_commitInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_commitInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_commitInstStuck_get =
EN_deadlock_commitInstStuck_get ;
// actionvalue method deadlock_commitUserInstStuck_get
assign deadlock_commitUserInstStuck_get =
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_commitUserInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_commitUserInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_commitUserInstStuck_get =
EN_deadlock_commitUserInstStuck_get ;
// action method deadlock_checkStarted_get
assign RDY_deadlock_checkStarted_get = 1'd0 ;
assign CAN_FIRE_deadlock_checkStarted_get = 1'd0 ;
assign WILL_FIRE_deadlock_checkStarted_get = EN_deadlock_checkStarted_get ;
// actionvalue method renameDebug_renameErr_get
assign renameDebug_renameErr_get = 89'h0AAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_renameDebug_renameErr_get = 1'd0 ;
assign CAN_FIRE_renameDebug_renameErr_get = 1'd0 ;
assign WILL_FIRE_renameDebug_renameErr_get = EN_renameDebug_renameErr_get ;
// action method setMEIP
assign RDY_setMEIP = 1'd1 ;
assign CAN_FIRE_setMEIP = 1'd1 ;
assign WILL_FIRE_setMEIP = EN_setMEIP ;
// action method setSEIP
assign RDY_setSEIP = 1'd1 ;
assign CAN_FIRE_setSEIP = 1'd1 ;
assign WILL_FIRE_setSEIP = EN_setSEIP ;
// action method hart0_run_halt_server_request_put
assign RDY_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ;
assign CAN_FIRE_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ;
assign WILL_FIRE_hart0_run_halt_server_request_put =
EN_hart0_run_halt_server_request_put ;
// actionvalue method hart0_run_halt_server_response_get
assign hart0_run_halt_server_response_get = f_run_halt_rsps$D_OUT ;
assign RDY_hart0_run_halt_server_response_get = f_run_halt_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_run_halt_server_response_get =
f_run_halt_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_run_halt_server_response_get =
EN_hart0_run_halt_server_response_get ;
// action method hart0_gpr_mem_server_request_put
assign RDY_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
assign CAN_FIRE_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
assign WILL_FIRE_hart0_gpr_mem_server_request_put =
EN_hart0_gpr_mem_server_request_put ;
// actionvalue method hart0_gpr_mem_server_response_get
assign hart0_gpr_mem_server_response_get = f_gpr_rsps$D_OUT ;
assign RDY_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_gpr_mem_server_response_get =
EN_hart0_gpr_mem_server_response_get ;
// action method hart0_fpr_mem_server_request_put
assign RDY_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
assign CAN_FIRE_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
assign WILL_FIRE_hart0_fpr_mem_server_request_put =
EN_hart0_fpr_mem_server_request_put ;
// actionvalue method hart0_fpr_mem_server_response_get
assign hart0_fpr_mem_server_response_get = f_fpr_rsps$D_OUT ;
assign RDY_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_fpr_mem_server_response_get =
EN_hart0_fpr_mem_server_response_get ;
// action method hart0_csr_mem_server_request_put
assign RDY_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
assign CAN_FIRE_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
assign WILL_FIRE_hart0_csr_mem_server_request_put =
EN_hart0_csr_mem_server_request_put ;
// actionvalue method hart0_csr_mem_server_response_get
assign hart0_csr_mem_server_response_get = f_csr_rsps$D_OUT ;
assign RDY_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_csr_mem_server_response_get =
EN_hart0_csr_mem_server_response_get ;
// actionvalue method v_to_TV_0_get
assign v_to_TV_0_get =
{ v_f_to_TV_0$D_OUT[712:476],
CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5,
v_f_to_TV_0$D_OUT[463:462],
v_f_to_TV_0$D_OUT[462] ?
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 :
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7,
v_f_to_TV_0$D_OUT[457:394],
CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8,
v_f_to_TV_0$D_OUT[391:0] } ;
assign RDY_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ;
assign CAN_FIRE_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ;
assign WILL_FIRE_v_to_TV_0_get = EN_v_to_TV_0_get ;
// actionvalue method v_to_TV_1_get
assign v_to_TV_1_get =
{ v_f_to_TV_1$D_OUT[712:476],
CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1,
v_f_to_TV_1$D_OUT[463:462],
v_f_to_TV_1$D_OUT[462] ?
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 :
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3,
v_f_to_TV_1$D_OUT[457:394],
CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4,
v_f_to_TV_1$D_OUT[391:0] } ;
assign RDY_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ;
assign CAN_FIRE_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ;
assign WILL_FIRE_v_to_TV_1_get = EN_v_to_TV_1_get ;
// submodule commitStage_f_rob_data
FIFO2 #(.width(32'd354),
.guarded(32'd1)) commitStage_f_rob_data(.RST(RST_N),
.CLK(CLK),
.D_IN(commitStage_f_rob_data$D_IN),
.ENQ(commitStage_f_rob_data$ENQ),
.DEQ(commitStage_f_rob_data$DEQ),
.CLR(commitStage_f_rob_data$CLR),
.D_OUT(commitStage_f_rob_data$D_OUT),
.FULL_N(commitStage_f_rob_data$FULL_N),
.EMPTY_N(commitStage_f_rob_data$EMPTY_N));
// submodule coreFix_aluExe_0_dispToRegQ
mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_dispToRegQ$EN_enq),
.EN_deq(coreFix_aluExe_0_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_dispToRegQ$RDY_deq),
.first(coreFix_aluExe_0_dispToRegQ$first),
.RDY_first(coreFix_aluExe_0_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_exeToFinQ
mkAluExeToFinFifo coreFix_aluExe_0_exeToFinQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_exeToFinQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_exeToFinQ$EN_enq),
.EN_deq(coreFix_aluExe_0_exeToFinQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_exeToFinQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_exeToFinQ$RDY_deq),
.first(coreFix_aluExe_0_exeToFinQ$first),
.RDY_first(coreFix_aluExe_0_exeToFinQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_regToExeQ
mkAluRegToExeFifo coreFix_aluExe_0_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_regToExeQ$EN_enq),
.EN_deq(coreFix_aluExe_0_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_regToExeQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_regToExeQ$RDY_deq),
.first(coreFix_aluExe_0_regToExeQ$first),
.RDY_first(coreFix_aluExe_0_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_rsAlu
mkReservationStationAlu coreFix_aluExe_0_rsAlu(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_rsAlu$enq_x),
.setRegReady_0_put(coreFix_aluExe_0_rsAlu$setRegReady_0_put),
.setRegReady_1_put(coreFix_aluExe_0_rsAlu$setRegReady_1_put),
.setRegReady_2_put(coreFix_aluExe_0_rsAlu$setRegReady_2_put),
.setRegReady_3_put(coreFix_aluExe_0_rsAlu$setRegReady_3_put),
.setRegReady_4_put(coreFix_aluExe_0_rsAlu$setRegReady_4_put),
.setRobEnqTime_t(coreFix_aluExe_0_rsAlu$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_rsAlu$EN_enq),
.EN_setRobEnqTime(coreFix_aluExe_0_rsAlu$EN_setRobEnqTime),
.EN_doDispatch(coreFix_aluExe_0_rsAlu$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_rsAlu$RDY_enq),
.canEnq(coreFix_aluExe_0_rsAlu$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_aluExe_0_rsAlu$dispatchData),
.RDY_dispatchData(coreFix_aluExe_0_rsAlu$RDY_dispatchData),
.RDY_doDispatch(coreFix_aluExe_0_rsAlu$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(coreFix_aluExe_0_rsAlu$approximateCount),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_dispToRegQ
mkAluDispToRegFifo coreFix_aluExe_1_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_dispToRegQ$EN_enq),
.EN_deq(coreFix_aluExe_1_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_dispToRegQ$RDY_deq),
.first(coreFix_aluExe_1_dispToRegQ$first),
.RDY_first(coreFix_aluExe_1_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_exeToFinQ
mkAluExeToFinFifo coreFix_aluExe_1_exeToFinQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_exeToFinQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_exeToFinQ$EN_enq),
.EN_deq(coreFix_aluExe_1_exeToFinQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_exeToFinQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_exeToFinQ$RDY_deq),
.first(coreFix_aluExe_1_exeToFinQ$first),
.RDY_first(coreFix_aluExe_1_exeToFinQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_regToExeQ
mkAluRegToExeFifo coreFix_aluExe_1_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_regToExeQ$EN_enq),
.EN_deq(coreFix_aluExe_1_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_regToExeQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_regToExeQ$RDY_deq),
.first(coreFix_aluExe_1_regToExeQ$first),
.RDY_first(coreFix_aluExe_1_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_rsAlu
mkReservationStationAlu coreFix_aluExe_1_rsAlu(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_rsAlu$enq_x),
.setRegReady_0_put(coreFix_aluExe_1_rsAlu$setRegReady_0_put),
.setRegReady_1_put(coreFix_aluExe_1_rsAlu$setRegReady_1_put),
.setRegReady_2_put(coreFix_aluExe_1_rsAlu$setRegReady_2_put),
.setRegReady_3_put(coreFix_aluExe_1_rsAlu$setRegReady_3_put),
.setRegReady_4_put(coreFix_aluExe_1_rsAlu$setRegReady_4_put),
.setRobEnqTime_t(coreFix_aluExe_1_rsAlu$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_rsAlu$EN_enq),
.EN_setRobEnqTime(coreFix_aluExe_1_rsAlu$EN_setRobEnqTime),
.EN_doDispatch(coreFix_aluExe_1_rsAlu$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_rsAlu$RDY_enq),
.canEnq(coreFix_aluExe_1_rsAlu$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_aluExe_1_rsAlu$dispatchData),
.RDY_dispatchData(coreFix_aluExe_1_rsAlu$RDY_dispatchData),
.RDY_doDispatch(coreFix_aluExe_1_rsAlu$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(coreFix_aluExe_1_rsAlu$approximateCount),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
mkFpuMulDivDispToRegFifo coreFix_fpuMulDivExe_0_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_dispToRegQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_divQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
mkDoubleDiv coreFix_fpuMulDivExe_0_fpuExec_double_div(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
mkDoubleFMA coreFix_fpuMulDivExe_0_fpuExec_double_fma(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
mkDoubleSqrt coreFix_fpuMulDivExe_0_fpuExec_double_sqrt(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
mkFmaExecQ coreFix_fpuMulDivExe_0_fpuExec_fmaQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
mkSimpleRespQ coreFix_fpuMulDivExe_0_fpuExec_simpleQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_sqrtQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
mkDivExecQ coreFix_fpuMulDivExe_0_mulDivExec_divQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
FIFO2 #(.width(32'd140),
.guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT),
.FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
FIFO2 #(.width(32'd64),
.guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT),
.FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
FIFO2 #(.width(32'd204),
.guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT),
.FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
mkMulExecQ coreFix_fpuMulDivExe_0_mulDivExec_mulQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd0)) coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT),
.FULL_N(),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_regToExeQ
mkFpuMulDivRegToExeFifo coreFix_fpuMulDivExe_0_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_regToExeQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_regToExeQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
mkReservationStationFpuMulDiv coreFix_fpuMulDivExe_0_rsFpuMulDiv(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x),
.setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put),
.setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put),
.setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put),
.setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put),
.setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put),
.setRobEnqTime_t(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq),
.EN_setRobEnqTime(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime),
.EN_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq),
.canEnq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData),
.RDY_dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData),
.RDY_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
mkDCRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_cRqMshr(.CLK(CLK),
.RST_N(RST_N),
.cRqTransfer_getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r),
.cRqTransfer_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n),
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n),
.pipelineResp_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n),
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n),
.pipelineResp_getSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n),
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n),
.pipelineResp_searchEndOfChain_addr(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr),
.pipelineResp_setData_d(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d),
.pipelineResp_setData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n),
.pipelineResp_setStateSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n),
.pipelineResp_setStateSlot_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot),
.pipelineResp_setStateSlot_state(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state),
.pipelineResp_setSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n),
.pipelineResp_setSucc_succ(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ),
.sendRqToP_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n),
.sendRqToP_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n),
.sendRsToP_cRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n),
.sendRsToP_cRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n),
.sendRsToP_cRq_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n),
.sendRsToP_cRq_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n),
.sendRsToP_cRq_setWaitSt_setSlot_clearData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n),
.sendRsToP_cRq_setWaitSt_setSlot_clearData_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot),
.EN_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit),
.EN_sendRsToP_cRq_setWaitSt_setSlot_clearData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData),
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry),
.EN_pipelineResp_setData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData),
.EN_pipelineResp_setStateSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot),
.EN_pipelineResp_setSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc),
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get),
.cRqTransfer_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq),
.RDY_cRqTransfer_getRq(),
.cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit),
.RDY_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit),
.sendRsToP_cRq_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState),
.RDY_sendRsToP_cRq_getState(),
.sendRsToP_cRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq),
.RDY_sendRsToP_cRq_getRq(),
.sendRsToP_cRq_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot),
.RDY_sendRsToP_cRq_getSlot(),
.sendRsToP_cRq_getData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData),
.RDY_sendRsToP_cRq_getData(),
.RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData(),
.sendRqToP_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq),
.RDY_sendRqToP_getRq(),
.sendRqToP_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot),
.RDY_sendRqToP_getSlot(),
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry),
.pipelineResp_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState),
.RDY_pipelineResp_getState(),
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot),
.RDY_pipelineResp_getSlot(),
.RDY_pipelineResp_setData(),
.RDY_pipelineResp_setStateSlot(),
.pipelineResp_getSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc),
.RDY_pipelineResp_getSucc(),
.RDY_pipelineResp_setSucc(),
.pipelineResp_searchEndOfChain(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain),
.RDY_pipelineResp_searchEndOfChain(),
.emptyForFlush(),
.RDY_emptyForFlush(),
.stuck_get(),
.RDY_stuck_get());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
mkDPRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_pRqMshr(.CLK(CLK),
.RST_N(RST_N),
.getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r),
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n),
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n),
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n),
.pipelineResp_setDone_setData_d(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d),
.pipelineResp_setDone_setData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n),
.sendRsToP_pRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n),
.sendRsToP_pRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n),
.sendRsToP_pRq_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n),
.EN_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit),
.EN_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry),
.EN_pipelineResp_setDone_setData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData),
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get),
.getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit),
.RDY_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit),
.sendRsToP_pRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq),
.RDY_sendRsToP_pRq_getRq(),
.sendRsToP_pRq_getData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData),
.RDY_sendRsToP_pRq_getData(),
.RDY_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getState(),
.RDY_pipelineResp_getState(),
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry),
.RDY_pipelineResp_setDone_setData(),
.stuck_get(),
.RDY_stuck_get());
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
mkDPipeline coreFix_memExe_dMem_cache_m_banks_0_pipeline(.CLK(CLK),
.RST_N(RST_N),
.deqWrite_swapRq(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq),
.deqWrite_updateRep(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep),
.deqWrite_wrRam(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam),
.send_r(coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r),
.EN_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send),
.EN_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite),
.RDY_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send),
.first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first),
.RDY_first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first),
.RDY_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
SizedFIFO #(.p1width(32'd3),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
FIFO2 #(.width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
FIFO2 #(.width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd12),
.p3cntr_width(32'd4),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dTlb
mkDTlbSynth coreFix_memExe_dTlb(.CLK(CLK),
.RST_N(RST_N),
.perf_req_r(coreFix_memExe_dTlb$perf_req_r),
.perf_setStatus_doStats(coreFix_memExe_dTlb$perf_setStatus_doStats),
.procReq_req(coreFix_memExe_dTlb$procReq_req),
.specUpdate_correctSpeculation_mask(coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag),
.toParent_ldTransRsFromP_enq_x(coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x),
.updateVMInfo_vm(coreFix_memExe_dTlb$updateVMInfo_vm),
.EN_flush(coreFix_memExe_dTlb$EN_flush),
.EN_updateVMInfo(coreFix_memExe_dTlb$EN_updateVMInfo),
.EN_procReq(coreFix_memExe_dTlb$EN_procReq),
.EN_deqProcResp(coreFix_memExe_dTlb$EN_deqProcResp),
.EN_toParent_rqToP_deq(coreFix_memExe_dTlb$EN_toParent_rqToP_deq),
.EN_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq),
.EN_toParent_flush_request_get(coreFix_memExe_dTlb$EN_toParent_flush_request_get),
.EN_toParent_flush_response_put(coreFix_memExe_dTlb$EN_toParent_flush_response_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation),
.EN_perf_setStatus(coreFix_memExe_dTlb$EN_perf_setStatus),
.EN_perf_req(coreFix_memExe_dTlb$EN_perf_req),
.EN_perf_resp(coreFix_memExe_dTlb$EN_perf_resp),
.flush_done(coreFix_memExe_dTlb$flush_done),
.RDY_flush_done(),
.RDY_flush(coreFix_memExe_dTlb$RDY_flush),
.RDY_updateVMInfo(),
.noPendingReq(coreFix_memExe_dTlb$noPendingReq),
.RDY_noPendingReq(),
.RDY_procReq(coreFix_memExe_dTlb$RDY_procReq),
.procResp(coreFix_memExe_dTlb$procResp),
.RDY_procResp(coreFix_memExe_dTlb$RDY_procResp),
.RDY_deqProcResp(coreFix_memExe_dTlb$RDY_deqProcResp),
.toParent_rqToP_notEmpty(),
.RDY_toParent_rqToP_notEmpty(),
.RDY_toParent_rqToP_deq(coreFix_memExe_dTlb$RDY_toParent_rqToP_deq),
.toParent_rqToP_first(coreFix_memExe_dTlb$toParent_rqToP_first),
.RDY_toParent_rqToP_first(coreFix_memExe_dTlb$RDY_toParent_rqToP_first),
.toParent_ldTransRsFromP_notFull(),
.RDY_toParent_ldTransRsFromP_notFull(),
.RDY_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq),
.RDY_toParent_flush_request_get(coreFix_memExe_dTlb$RDY_toParent_flush_request_get),
.RDY_toParent_flush_response_put(coreFix_memExe_dTlb$RDY_toParent_flush_response_put),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule coreFix_memExe_dispToRegQ
mkMemDispToRegFifo coreFix_memExe_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_dispToRegQ$EN_enq),
.EN_deq(coreFix_memExe_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_memExe_dispToRegQ$RDY_deq),
.first(coreFix_memExe_dispToRegQ$first),
.RDY_first(coreFix_memExe_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_lsq
mkSplitLSQ coreFix_memExe_lsq(.CLK(CLK),
.RST_N(RST_N),
.enqLd_dst(coreFix_memExe_lsq$enqLd_dst),
.enqLd_inst_tag(coreFix_memExe_lsq$enqLd_inst_tag),
.enqLd_mem_inst(coreFix_memExe_lsq$enqLd_mem_inst),
.enqLd_spec_bits(coreFix_memExe_lsq$enqLd_spec_bits),
.enqSt_dst(coreFix_memExe_lsq$enqSt_dst),
.enqSt_inst_tag(coreFix_memExe_lsq$enqSt_inst_tag),
.enqSt_mem_inst(coreFix_memExe_lsq$enqSt_mem_inst),
.enqSt_spec_bits(coreFix_memExe_lsq$enqSt_spec_bits),
.getHit_t(coreFix_memExe_lsq$getHit_t),
.getOrigBE_t(coreFix_memExe_lsq$getOrigBE_t),
.issueLd_lsqTag(coreFix_memExe_lsq$issueLd_lsqTag),
.issueLd_paddr(coreFix_memExe_lsq$issueLd_paddr),
.issueLd_sbRes(coreFix_memExe_lsq$issueLd_sbRes),
.issueLd_shiftedBE(coreFix_memExe_lsq$issueLd_shiftedBE),
.respLd_alignedData(coreFix_memExe_lsq$respLd_alignedData),
.respLd_t(coreFix_memExe_lsq$respLd_t),
.setAtCommit_0_put(coreFix_memExe_lsq$setAtCommit_0_put),
.setAtCommit_1_put(coreFix_memExe_lsq$setAtCommit_1_put),
.specUpdate_correctSpeculation_mask(coreFix_memExe_lsq$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag),
.updateAddr_fault(coreFix_memExe_lsq$updateAddr_fault),
.updateAddr_isMMIO(coreFix_memExe_lsq$updateAddr_isMMIO),
.updateAddr_lsqTag(coreFix_memExe_lsq$updateAddr_lsqTag),
.updateAddr_paddr(coreFix_memExe_lsq$updateAddr_paddr),
.updateAddr_shiftedBE(coreFix_memExe_lsq$updateAddr_shiftedBE),
.updateData_d(coreFix_memExe_lsq$updateData_d),
.updateData_t(coreFix_memExe_lsq$updateData_t),
.wakeupLdStalledBySB_sbIdx(coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx),
.EN_enqLd(coreFix_memExe_lsq$EN_enqLd),
.EN_enqSt(coreFix_memExe_lsq$EN_enqSt),
.EN_getHit(coreFix_memExe_lsq$EN_getHit),
.EN_updateData(coreFix_memExe_lsq$EN_updateData),
.EN_updateAddr(coreFix_memExe_lsq$EN_updateAddr),
.EN_issueLd(coreFix_memExe_lsq$EN_issueLd),
.EN_getIssueLd(coreFix_memExe_lsq$EN_getIssueLd),
.EN_respLd(coreFix_memExe_lsq$EN_respLd),
.EN_deqLd(coreFix_memExe_lsq$EN_deqLd),
.EN_deqSt(coreFix_memExe_lsq$EN_deqSt),
.EN_wakeupLdStalledBySB(coreFix_memExe_lsq$EN_wakeupLdStalledBySB),
.EN_setAtCommit_0_put(coreFix_memExe_lsq$EN_setAtCommit_0_put),
.EN_setAtCommit_1_put(coreFix_memExe_lsq$EN_setAtCommit_1_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_lsq$EN_specUpdate_correctSpeculation),
.enqLdTag(coreFix_memExe_lsq$enqLdTag),
.RDY_enqLdTag(),
.enqStTag(coreFix_memExe_lsq$enqStTag),
.RDY_enqStTag(),
.RDY_enqLd(coreFix_memExe_lsq$RDY_enqLd),
.RDY_enqSt(coreFix_memExe_lsq$RDY_enqSt),
.getOrigBE(coreFix_memExe_lsq$getOrigBE),
.RDY_getOrigBE(),
.getHit(coreFix_memExe_lsq$getHit),
.RDY_getHit(),
.RDY_updateData(),
.updateAddr(coreFix_memExe_lsq$updateAddr),
.RDY_updateAddr(),
.issueLd(coreFix_memExe_lsq$issueLd),
.RDY_issueLd(),
.getIssueLd(coreFix_memExe_lsq$getIssueLd),
.RDY_getIssueLd(coreFix_memExe_lsq$RDY_getIssueLd),
.respLd(coreFix_memExe_lsq$respLd),
.RDY_respLd(),
.firstLd(coreFix_memExe_lsq$firstLd),
.RDY_firstLd(coreFix_memExe_lsq$RDY_firstLd),
.RDY_deqLd(coreFix_memExe_lsq$RDY_deqLd),
.firstSt(coreFix_memExe_lsq$firstSt),
.RDY_firstSt(coreFix_memExe_lsq$RDY_firstSt),
.RDY_deqSt(coreFix_memExe_lsq$RDY_deqSt),
.RDY_wakeupLdStalledBySB(),
.stqEmpty(coreFix_memExe_lsq$stqEmpty),
.RDY_stqEmpty(),
.RDY_setAtCommit_0_put(),
.RDY_setAtCommit_1_put(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.stqFull_ehrPort0(),
.RDY_stqFull_ehrPort0(),
.ldqFull_ehrPort0(),
.RDY_ldqFull_ehrPort0(),
.noWrongPathLoads(coreFix_memExe_lsq$noWrongPathLoads),
.RDY_noWrongPathLoads());
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_regToExeQ
mkMemRegToExeFifo coreFix_memExe_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_regToExeQ$EN_enq),
.EN_deq(coreFix_memExe_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_regToExeQ$RDY_enq),
.RDY_deq(coreFix_memExe_regToExeQ$RDY_deq),
.first(coreFix_memExe_regToExeQ$first),
.RDY_first(coreFix_memExe_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqStQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_rsMem
mkReservationStationMem coreFix_memExe_rsMem(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_rsMem$enq_x),
.setRegReady_0_put(coreFix_memExe_rsMem$setRegReady_0_put),
.setRegReady_1_put(coreFix_memExe_rsMem$setRegReady_1_put),
.setRegReady_2_put(coreFix_memExe_rsMem$setRegReady_2_put),
.setRegReady_3_put(coreFix_memExe_rsMem$setRegReady_3_put),
.setRegReady_4_put(coreFix_memExe_rsMem$setRegReady_4_put),
.setRobEnqTime_t(coreFix_memExe_rsMem$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_rsMem$EN_enq),
.EN_setRobEnqTime(coreFix_memExe_rsMem$EN_setRobEnqTime),
.EN_doDispatch(coreFix_memExe_rsMem$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_memExe_rsMem$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_memExe_rsMem$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_memExe_rsMem$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_memExe_rsMem$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_memExe_rsMem$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_rsMem$RDY_enq),
.canEnq(coreFix_memExe_rsMem$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_memExe_rsMem$dispatchData),
.RDY_dispatchData(coreFix_memExe_rsMem$RDY_dispatchData),
.RDY_doDispatch(coreFix_memExe_rsMem$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_stb
mkStoreBufferEhr coreFix_memExe_stb(.CLK(CLK),
.RST_N(RST_N),
.deq_idx(coreFix_memExe_stb$deq_idx),
.enq_be(coreFix_memExe_stb$enq_be),
.enq_data(coreFix_memExe_stb$enq_data),
.enq_idx(coreFix_memExe_stb$enq_idx),
.enq_paddr(coreFix_memExe_stb$enq_paddr),
.getEnqIndex_paddr(coreFix_memExe_stb$getEnqIndex_paddr),
.noMatchLdQ_be(coreFix_memExe_stb$noMatchLdQ_be),
.noMatchLdQ_paddr(coreFix_memExe_stb$noMatchLdQ_paddr),
.noMatchStQ_be(coreFix_memExe_stb$noMatchStQ_be),
.noMatchStQ_paddr(coreFix_memExe_stb$noMatchStQ_paddr),
.search_be(coreFix_memExe_stb$search_be),
.search_paddr(coreFix_memExe_stb$search_paddr),
.EN_enq(coreFix_memExe_stb$EN_enq),
.EN_deq(coreFix_memExe_stb$EN_deq),
.EN_issue(coreFix_memExe_stb$EN_issue),
.isEmpty(coreFix_memExe_stb$isEmpty),
.RDY_isEmpty(),
.getEnqIndex(coreFix_memExe_stb$getEnqIndex),
.RDY_getEnqIndex(),
.RDY_enq(coreFix_memExe_stb$RDY_enq),
.deq(coreFix_memExe_stb$deq),
.RDY_deq(coreFix_memExe_stb$RDY_deq),
.issue(coreFix_memExe_stb$issue),
.RDY_issue(coreFix_memExe_stb$RDY_issue),
.search(coreFix_memExe_stb$search),
.RDY_search(),
.noMatchLdQ(coreFix_memExe_stb$noMatchLdQ),
.RDY_noMatchLdQ(),
.noMatchStQ(coreFix_memExe_stb$noMatchStQ),
.RDY_noMatchStQ());
// submodule coreFix_trainBPQ_0
FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_trainBPQ_0$D_IN),
.ENQ(coreFix_trainBPQ_0$ENQ),
.DEQ(coreFix_trainBPQ_0$DEQ),
.CLR(coreFix_trainBPQ_0$CLR),
.D_OUT(coreFix_trainBPQ_0$D_OUT),
.FULL_N(coreFix_trainBPQ_0$FULL_N),
.EMPTY_N(coreFix_trainBPQ_0$EMPTY_N));
// submodule coreFix_trainBPQ_1
FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_trainBPQ_1$D_IN),
.ENQ(coreFix_trainBPQ_1$ENQ),
.DEQ(coreFix_trainBPQ_1$DEQ),
.CLR(coreFix_trainBPQ_1$CLR),
.D_OUT(coreFix_trainBPQ_1$D_OUT),
.FULL_N(coreFix_trainBPQ_1$FULL_N),
.EMPTY_N(coreFix_trainBPQ_1$EMPTY_N));
// submodule csrInstOrInterruptInflight_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrInstOrInterruptInflight_dummy2_0(.CLK(CLK),
.D_IN(csrInstOrInterruptInflight_dummy2_0$D_IN),
.EN(csrInstOrInterruptInflight_dummy2_0$EN),
.Q_OUT(csrInstOrInterruptInflight_dummy2_0$Q_OUT));
// submodule csrInstOrInterruptInflight_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrInstOrInterruptInflight_dummy2_1(.CLK(CLK),
.D_IN(csrInstOrInterruptInflight_dummy2_1$D_IN),
.EN(csrInstOrInterruptInflight_dummy2_1$EN),
.Q_OUT(csrInstOrInterruptInflight_dummy2_1$Q_OUT));
// submodule csrf_mcycle_ehr_data_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_0(.CLK(CLK),
.D_IN(csrf_mcycle_ehr_data_dummy2_0$D_IN),
.EN(csrf_mcycle_ehr_data_dummy2_0$EN),
.Q_OUT(csrf_mcycle_ehr_data_dummy2_0$Q_OUT));
// submodule csrf_mcycle_ehr_data_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_1(.CLK(CLK),
.D_IN(csrf_mcycle_ehr_data_dummy2_1$D_IN),
.EN(csrf_mcycle_ehr_data_dummy2_1$EN),
.Q_OUT(csrf_mcycle_ehr_data_dummy2_1$Q_OUT));
// submodule csrf_minstret_ehr_data_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_minstret_ehr_data_dummy2_0(.CLK(CLK),
.D_IN(csrf_minstret_ehr_data_dummy2_0$D_IN),
.EN(csrf_minstret_ehr_data_dummy2_0$EN),
.Q_OUT(csrf_minstret_ehr_data_dummy2_0$Q_OUT));
// submodule csrf_minstret_ehr_data_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_minstret_ehr_data_dummy2_1(.CLK(CLK),
.D_IN(csrf_minstret_ehr_data_dummy2_1$D_IN),
.EN(csrf_minstret_ehr_data_dummy2_1$EN),
.Q_OUT(csrf_minstret_ehr_data_dummy2_1$Q_OUT));
// submodule csrf_stats_module_writeQ
FIFO1 #(.width(32'd1),
.guarded(32'd1)) csrf_stats_module_writeQ(.RST(RST_N),
.CLK(CLK),
.D_IN(csrf_stats_module_writeQ$D_IN),
.ENQ(csrf_stats_module_writeQ$ENQ),
.DEQ(csrf_stats_module_writeQ$DEQ),
.CLR(csrf_stats_module_writeQ$CLR),
.D_OUT(csrf_stats_module_writeQ$D_OUT),
.FULL_N(csrf_stats_module_writeQ$FULL_N),
.EMPTY_N(csrf_stats_module_writeQ$EMPTY_N));
// submodule csrf_terminate_module_terminateQ
FIFO10 #(.guarded(32'd1)) csrf_terminate_module_terminateQ(.RST(RST_N),
.CLK(CLK),
.ENQ(csrf_terminate_module_terminateQ$ENQ),
.DEQ(csrf_terminate_module_terminateQ$DEQ),
.CLR(csrf_terminate_module_terminateQ$CLR),
.FULL_N(csrf_terminate_module_terminateQ$FULL_N),
.EMPTY_N(csrf_terminate_module_terminateQ$EMPTY_N));
// submodule epochManager
mkEpochManager epochManager(.CLK(CLK),
.RST_N(RST_N),
.checkEpoch_0_check_e(epochManager$checkEpoch_0_check_e),
.checkEpoch_1_check_e(epochManager$checkEpoch_1_check_e),
.updatePrevEpoch_0_update_e(epochManager$updatePrevEpoch_0_update_e),
.updatePrevEpoch_1_update_e(epochManager$updatePrevEpoch_1_update_e),
.EN_updatePrevEpoch_0_update(epochManager$EN_updatePrevEpoch_0_update),
.EN_updatePrevEpoch_1_update(epochManager$EN_updatePrevEpoch_1_update),
.EN_incrementEpoch(epochManager$EN_incrementEpoch),
.checkEpoch_0_check(epochManager$checkEpoch_0_check),
.RDY_checkEpoch_0_check(),
.checkEpoch_1_check(epochManager$checkEpoch_1_check),
.RDY_checkEpoch_1_check(),
.RDY_updatePrevEpoch_0_update(),
.RDY_updatePrevEpoch_1_update(),
.getEpoch(),
.RDY_getEpoch(),
.RDY_incrementEpoch(epochManager$RDY_incrementEpoch),
.getEpochState(),
.RDY_getEpochState(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0());
// submodule f_csr_reqs
FIFO1 #(.width(32'd77), .guarded(32'd1)) f_csr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_csr_reqs$D_IN),
.ENQ(f_csr_reqs$ENQ),
.DEQ(f_csr_reqs$DEQ),
.CLR(f_csr_reqs$CLR),
.D_OUT(f_csr_reqs$D_OUT),
.FULL_N(f_csr_reqs$FULL_N),
.EMPTY_N(f_csr_reqs$EMPTY_N));
// submodule f_csr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_csr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_csr_rsps$D_IN),
.ENQ(f_csr_rsps$ENQ),
.DEQ(f_csr_rsps$DEQ),
.CLR(f_csr_rsps$CLR),
.D_OUT(f_csr_rsps$D_OUT),
.FULL_N(f_csr_rsps$FULL_N),
.EMPTY_N(f_csr_rsps$EMPTY_N));
// submodule f_fpr_reqs
FIFO1 #(.width(32'd70), .guarded(32'd1)) f_fpr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fpr_reqs$D_IN),
.ENQ(f_fpr_reqs$ENQ),
.DEQ(f_fpr_reqs$DEQ),
.CLR(f_fpr_reqs$CLR),
.D_OUT(f_fpr_reqs$D_OUT),
.FULL_N(f_fpr_reqs$FULL_N),
.EMPTY_N(f_fpr_reqs$EMPTY_N));
// submodule f_fpr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_fpr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fpr_rsps$D_IN),
.ENQ(f_fpr_rsps$ENQ),
.DEQ(f_fpr_rsps$DEQ),
.CLR(f_fpr_rsps$CLR),
.D_OUT(f_fpr_rsps$D_OUT),
.FULL_N(f_fpr_rsps$FULL_N),
.EMPTY_N(f_fpr_rsps$EMPTY_N));
// submodule f_gpr_reqs
FIFO1 #(.width(32'd70), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_gpr_reqs$D_IN),
.ENQ(f_gpr_reqs$ENQ),
.DEQ(f_gpr_reqs$DEQ),
.CLR(f_gpr_reqs$CLR),
.D_OUT(f_gpr_reqs$D_OUT),
.FULL_N(f_gpr_reqs$FULL_N),
.EMPTY_N(f_gpr_reqs$EMPTY_N));
// submodule f_gpr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_gpr_rsps$D_IN),
.ENQ(f_gpr_rsps$ENQ),
.DEQ(f_gpr_rsps$DEQ),
.CLR(f_gpr_rsps$CLR),
.D_OUT(f_gpr_rsps$D_OUT),
.FULL_N(f_gpr_rsps$FULL_N),
.EMPTY_N(f_gpr_rsps$EMPTY_N));
// submodule f_run_halt_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_run_halt_reqs$D_IN),
.ENQ(f_run_halt_reqs$ENQ),
.DEQ(f_run_halt_reqs$DEQ),
.CLR(f_run_halt_reqs$CLR),
.D_OUT(f_run_halt_reqs$D_OUT),
.FULL_N(f_run_halt_reqs$FULL_N),
.EMPTY_N(f_run_halt_reqs$EMPTY_N));
// submodule f_run_halt_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_run_halt_rsps$D_IN),
.ENQ(f_run_halt_rsps$ENQ),
.DEQ(f_run_halt_rsps$DEQ),
.CLR(f_run_halt_rsps$CLR),
.D_OUT(f_run_halt_rsps$D_OUT),
.FULL_N(f_run_halt_rsps$FULL_N),
.EMPTY_N(f_run_halt_rsps$EMPTY_N));
// submodule fetchStage
mkFetchStage fetchStage(.CLK(CLK),
.RST_N(RST_N),
.iMemIfc_perf_req_r(fetchStage$iMemIfc_perf_req_r),
.iMemIfc_perf_setStatus_doStats(fetchStage$iMemIfc_perf_setStatus_doStats),
.iMemIfc_to_parent_fromP_enq_x(fetchStage$iMemIfc_to_parent_fromP_enq_x),
.iMemIfc_to_proc_request_put(fetchStage$iMemIfc_to_proc_request_put),
.iTlbIfc_perf_req_r(fetchStage$iTlbIfc_perf_req_r),
.iTlbIfc_perf_setStatus_doStats(fetchStage$iTlbIfc_perf_setStatus_doStats),
.iTlbIfc_toParent_rsFromP_enq_x(fetchStage$iTlbIfc_toParent_rsFromP_enq_x),
.iTlbIfc_to_proc_request_put(fetchStage$iTlbIfc_to_proc_request_put),
.iTlbIfc_updateVMInfo_vm(fetchStage$iTlbIfc_updateVMInfo_vm),
.mmioIfc_instResp_enq_x(fetchStage$mmioIfc_instResp_enq_x),
.mmioIfc_setHtifAddrs_fromHost(fetchStage$mmioIfc_setHtifAddrs_fromHost),
.mmioIfc_setHtifAddrs_toHost(fetchStage$mmioIfc_setHtifAddrs_toHost),
.perf_req_r(fetchStage$perf_req_r),
.perf_setStatus_doStats(fetchStage$perf_setStatus_doStats),
.redirect_pc(fetchStage$redirect_pc),
.start_pc(fetchStage$start_pc),
.train_predictors_dpTrain(fetchStage$train_predictors_dpTrain),
.train_predictors_iType(fetchStage$train_predictors_iType),
.train_predictors_isCompressed(fetchStage$train_predictors_isCompressed),
.train_predictors_mispred(fetchStage$train_predictors_mispred),
.train_predictors_next_pc(fetchStage$train_predictors_next_pc),
.train_predictors_pc(fetchStage$train_predictors_pc),
.train_predictors_taken(fetchStage$train_predictors_taken),
.EN_pipelines_0_deq(fetchStage$EN_pipelines_0_deq),
.EN_pipelines_1_deq(fetchStage$EN_pipelines_1_deq),
.EN_iTlbIfc_flush(fetchStage$EN_iTlbIfc_flush),
.EN_iTlbIfc_updateVMInfo(fetchStage$EN_iTlbIfc_updateVMInfo),
.EN_iTlbIfc_to_proc_request_put(fetchStage$EN_iTlbIfc_to_proc_request_put),
.EN_iTlbIfc_to_proc_response_get(fetchStage$EN_iTlbIfc_to_proc_response_get),
.EN_iTlbIfc_toParent_rqToP_deq(fetchStage$EN_iTlbIfc_toParent_rqToP_deq),
.EN_iTlbIfc_toParent_rsFromP_enq(fetchStage$EN_iTlbIfc_toParent_rsFromP_enq),
.EN_iTlbIfc_toParent_flush_request_get(fetchStage$EN_iTlbIfc_toParent_flush_request_get),
.EN_iTlbIfc_toParent_flush_response_put(fetchStage$EN_iTlbIfc_toParent_flush_response_put),
.EN_iTlbIfc_perf_setStatus(fetchStage$EN_iTlbIfc_perf_setStatus),
.EN_iTlbIfc_perf_req(fetchStage$EN_iTlbIfc_perf_req),
.EN_iTlbIfc_perf_resp(fetchStage$EN_iTlbIfc_perf_resp),
.EN_iMemIfc_to_proc_request_put(fetchStage$EN_iMemIfc_to_proc_request_put),
.EN_iMemIfc_to_proc_response_get(fetchStage$EN_iMemIfc_to_proc_response_get),
.EN_iMemIfc_flush(fetchStage$EN_iMemIfc_flush),
.EN_iMemIfc_perf_setStatus(fetchStage$EN_iMemIfc_perf_setStatus),
.EN_iMemIfc_perf_req(fetchStage$EN_iMemIfc_perf_req),
.EN_iMemIfc_perf_resp(fetchStage$EN_iMemIfc_perf_resp),
.EN_iMemIfc_to_parent_rsToP_deq(fetchStage$EN_iMemIfc_to_parent_rsToP_deq),
.EN_iMemIfc_to_parent_rqToP_deq(fetchStage$EN_iMemIfc_to_parent_rqToP_deq),
.EN_iMemIfc_to_parent_fromP_enq(fetchStage$EN_iMemIfc_to_parent_fromP_enq),
.EN_iMemIfc_cRqStuck_get(fetchStage$EN_iMemIfc_cRqStuck_get),
.EN_iMemIfc_pRqStuck_get(fetchStage$EN_iMemIfc_pRqStuck_get),
.EN_mmioIfc_instReq_deq(fetchStage$EN_mmioIfc_instReq_deq),
.EN_mmioIfc_instResp_enq(fetchStage$EN_mmioIfc_instResp_enq),
.EN_mmioIfc_setHtifAddrs(fetchStage$EN_mmioIfc_setHtifAddrs),
.EN_start(fetchStage$EN_start),
.EN_stop(fetchStage$EN_stop),
.EN_setWaitRedirect(fetchStage$EN_setWaitRedirect),
.EN_redirect(fetchStage$EN_redirect),
.EN_setWaitFlush(fetchStage$EN_setWaitFlush),
.EN_done_flushing(fetchStage$EN_done_flushing),
.EN_train_predictors(fetchStage$EN_train_predictors),
.EN_flush_predictors(fetchStage$EN_flush_predictors),
.EN_perf_setStatus(fetchStage$EN_perf_setStatus),
.EN_perf_req(fetchStage$EN_perf_req),
.EN_perf_resp(fetchStage$EN_perf_resp),
.pipelines_0_canDeq(fetchStage$pipelines_0_canDeq),
.RDY_pipelines_0_canDeq(),
.RDY_pipelines_0_deq(fetchStage$RDY_pipelines_0_deq),
.pipelines_0_first(fetchStage$pipelines_0_first),
.RDY_pipelines_0_first(fetchStage$RDY_pipelines_0_first),
.pipelines_1_canDeq(fetchStage$pipelines_1_canDeq),
.RDY_pipelines_1_canDeq(),
.RDY_pipelines_1_deq(fetchStage$RDY_pipelines_1_deq),
.pipelines_1_first(fetchStage$pipelines_1_first),
.RDY_pipelines_1_first(fetchStage$RDY_pipelines_1_first),
.iTlbIfc_flush_done(fetchStage$iTlbIfc_flush_done),
.RDY_iTlbIfc_flush_done(),
.RDY_iTlbIfc_flush(fetchStage$RDY_iTlbIfc_flush),
.RDY_iTlbIfc_updateVMInfo(),
.iTlbIfc_noPendingReq(fetchStage$iTlbIfc_noPendingReq),
.RDY_iTlbIfc_noPendingReq(),
.RDY_iTlbIfc_to_proc_request_put(),
.iTlbIfc_to_proc_response_get(),
.RDY_iTlbIfc_to_proc_response_get(),
.iTlbIfc_toParent_rqToP_notEmpty(),
.RDY_iTlbIfc_toParent_rqToP_notEmpty(),
.RDY_iTlbIfc_toParent_rqToP_deq(fetchStage$RDY_iTlbIfc_toParent_rqToP_deq),
.iTlbIfc_toParent_rqToP_first(fetchStage$iTlbIfc_toParent_rqToP_first),
.RDY_iTlbIfc_toParent_rqToP_first(fetchStage$RDY_iTlbIfc_toParent_rqToP_first),
.iTlbIfc_toParent_rsFromP_notFull(),
.RDY_iTlbIfc_toParent_rsFromP_notFull(),
.RDY_iTlbIfc_toParent_rsFromP_enq(fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq),
.RDY_iTlbIfc_toParent_flush_request_get(fetchStage$RDY_iTlbIfc_toParent_flush_request_get),
.RDY_iTlbIfc_toParent_flush_response_put(fetchStage$RDY_iTlbIfc_toParent_flush_response_put),
.RDY_iTlbIfc_perf_setStatus(),
.RDY_iTlbIfc_perf_req(),
.iTlbIfc_perf_resp(),
.RDY_iTlbIfc_perf_resp(),
.iTlbIfc_perf_respValid(),
.RDY_iTlbIfc_perf_respValid(),
.RDY_iMemIfc_to_proc_request_put(),
.iMemIfc_to_proc_response_get(),
.RDY_iMemIfc_to_proc_response_get(),
.RDY_iMemIfc_flush(),
.iMemIfc_flush_done(fetchStage$iMemIfc_flush_done),
.RDY_iMemIfc_flush_done(),
.RDY_iMemIfc_perf_setStatus(),
.RDY_iMemIfc_perf_req(),
.iMemIfc_perf_resp(),
.RDY_iMemIfc_perf_resp(),
.iMemIfc_perf_respValid(),
.RDY_iMemIfc_perf_respValid(),
.iMemIfc_to_parent_rsToP_notEmpty(fetchStage$iMemIfc_to_parent_rsToP_notEmpty),
.RDY_iMemIfc_to_parent_rsToP_notEmpty(),
.RDY_iMemIfc_to_parent_rsToP_deq(fetchStage$RDY_iMemIfc_to_parent_rsToP_deq),
.iMemIfc_to_parent_rsToP_first(fetchStage$iMemIfc_to_parent_rsToP_first),
.RDY_iMemIfc_to_parent_rsToP_first(fetchStage$RDY_iMemIfc_to_parent_rsToP_first),
.iMemIfc_to_parent_rqToP_notEmpty(fetchStage$iMemIfc_to_parent_rqToP_notEmpty),
.RDY_iMemIfc_to_parent_rqToP_notEmpty(),
.RDY_iMemIfc_to_parent_rqToP_deq(fetchStage$RDY_iMemIfc_to_parent_rqToP_deq),
.iMemIfc_to_parent_rqToP_first(fetchStage$iMemIfc_to_parent_rqToP_first),
.RDY_iMemIfc_to_parent_rqToP_first(fetchStage$RDY_iMemIfc_to_parent_rqToP_first),
.iMemIfc_to_parent_fromP_notFull(fetchStage$iMemIfc_to_parent_fromP_notFull),
.RDY_iMemIfc_to_parent_fromP_notFull(),
.RDY_iMemIfc_to_parent_fromP_enq(fetchStage$RDY_iMemIfc_to_parent_fromP_enq),
.iMemIfc_cRqStuck_get(fetchStage$iMemIfc_cRqStuck_get),
.RDY_iMemIfc_cRqStuck_get(fetchStage$RDY_iMemIfc_cRqStuck_get),
.iMemIfc_pRqStuck_get(fetchStage$iMemIfc_pRqStuck_get),
.RDY_iMemIfc_pRqStuck_get(fetchStage$RDY_iMemIfc_pRqStuck_get),
.mmioIfc_instReq_notEmpty(),
.RDY_mmioIfc_instReq_notEmpty(),
.RDY_mmioIfc_instReq_deq(fetchStage$RDY_mmioIfc_instReq_deq),
.mmioIfc_instReq_first_fst(fetchStage$mmioIfc_instReq_first_fst),
.RDY_mmioIfc_instReq_first_fst(fetchStage$RDY_mmioIfc_instReq_first_fst),
.mmioIfc_instReq_first_snd(fetchStage$mmioIfc_instReq_first_snd),
.RDY_mmioIfc_instReq_first_snd(fetchStage$RDY_mmioIfc_instReq_first_snd),
.mmioIfc_instResp_notFull(),
.RDY_mmioIfc_instResp_notFull(),
.RDY_mmioIfc_instResp_enq(fetchStage$RDY_mmioIfc_instResp_enq),
.RDY_mmioIfc_setHtifAddrs(),
.RDY_start(),
.RDY_stop(),
.RDY_setWaitRedirect(),
.RDY_redirect(),
.RDY_setWaitFlush(),
.RDY_done_flushing(fetchStage$RDY_done_flushing),
.RDY_train_predictors(),
.emptyForFlush(fetchStage$emptyForFlush),
.RDY_emptyForFlush(),
.RDY_flush_predictors(),
.flush_predictors_done(fetchStage$flush_predictors_done),
.RDY_flush_predictors_done(),
.getFetchState(),
.RDY_getFetchState(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule l2Tlb
mkL2Tlb l2Tlb(.CLK(CLK),
.RST_N(RST_N),
.perf_req_r(l2Tlb$perf_req_r),
.perf_setStatus_doStats(l2Tlb$perf_setStatus_doStats),
.toChildren_rqFromC_put(l2Tlb$toChildren_rqFromC_put),
.toMem_respLd_enq_x(l2Tlb$toMem_respLd_enq_x),
.updateVMInfo_vmD(l2Tlb$updateVMInfo_vmD),
.updateVMInfo_vmI(l2Tlb$updateVMInfo_vmI),
.EN_updateVMInfo(l2Tlb$EN_updateVMInfo),
.EN_toChildren_rqFromC_put(l2Tlb$EN_toChildren_rqFromC_put),
.EN_toChildren_rsToC_deq(l2Tlb$EN_toChildren_rsToC_deq),
.EN_toChildren_iTlbReqFlush_put(l2Tlb$EN_toChildren_iTlbReqFlush_put),
.EN_toChildren_dTlbReqFlush_put(l2Tlb$EN_toChildren_dTlbReqFlush_put),
.EN_toChildren_flushDone_get(l2Tlb$EN_toChildren_flushDone_get),
.EN_toMem_memReq_deq(l2Tlb$EN_toMem_memReq_deq),
.EN_toMem_respLd_enq(l2Tlb$EN_toMem_respLd_enq),
.EN_perf_setStatus(l2Tlb$EN_perf_setStatus),
.EN_perf_req(l2Tlb$EN_perf_req),
.EN_perf_resp(l2Tlb$EN_perf_resp),
.RDY_updateVMInfo(),
.RDY_toChildren_rqFromC_put(l2Tlb$RDY_toChildren_rqFromC_put),
.toChildren_rsToC_notEmpty(),
.RDY_toChildren_rsToC_notEmpty(),
.RDY_toChildren_rsToC_deq(l2Tlb$RDY_toChildren_rsToC_deq),
.toChildren_rsToC_first(l2Tlb$toChildren_rsToC_first),
.RDY_toChildren_rsToC_first(l2Tlb$RDY_toChildren_rsToC_first),
.RDY_toChildren_iTlbReqFlush_put(l2Tlb$RDY_toChildren_iTlbReqFlush_put),
.RDY_toChildren_dTlbReqFlush_put(l2Tlb$RDY_toChildren_dTlbReqFlush_put),
.RDY_toChildren_flushDone_get(l2Tlb$RDY_toChildren_flushDone_get),
.toMem_memReq_notEmpty(l2Tlb$toMem_memReq_notEmpty),
.RDY_toMem_memReq_notEmpty(),
.RDY_toMem_memReq_deq(l2Tlb$RDY_toMem_memReq_deq),
.toMem_memReq_first(l2Tlb$toMem_memReq_first),
.RDY_toMem_memReq_first(l2Tlb$RDY_toMem_memReq_first),
.toMem_respLd_notFull(l2Tlb$toMem_respLd_notFull),
.RDY_toMem_respLd_notFull(),
.RDY_toMem_respLd_enq(l2Tlb$RDY_toMem_respLd_enq),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule mmio_cRqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_cRqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_cRqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_cRqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_cRqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_cRqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_cRsQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_clearReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_clearReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_cRsQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_cRsQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRsQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_2$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_cRsQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_cRsQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRsQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_2$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_cRsQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataPendQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataPendQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataPendQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataPendQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataPendQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataPendQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataPendQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataReqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataReqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataRespQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataRespQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataRespQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataRespQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataRespQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataRespQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataRespQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_pRqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_pRqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_pRqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_pRqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_pRqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_pRqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_pRsQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRsQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_clearReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRsQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_clearReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_pRsQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_pRsQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRsQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_2$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_pRsQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_pRsQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRsQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_2$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_pRsQ_enqReq_dummy2_2$Q_OUT));
// submodule perfReqQ
FIFO1 #(.width(32'd9), .guarded(32'd1)) perfReqQ(.RST(RST_N),
.CLK(CLK),
.D_IN(perfReqQ$D_IN),
.ENQ(perfReqQ$ENQ),
.DEQ(perfReqQ$DEQ),
.CLR(perfReqQ$CLR),
.D_OUT(perfReqQ$D_OUT),
.FULL_N(perfReqQ$FULL_N),
.EMPTY_N(perfReqQ$EMPTY_N));
// submodule regRenamingTable
mkRegRenamingTable regRenamingTable(.CLK(CLK),
.RST_N(RST_N),
.rename_0_claimRename_r(regRenamingTable$rename_0_claimRename_r),
.rename_0_claimRename_sb(regRenamingTable$rename_0_claimRename_sb),
.rename_0_getRename_r(regRenamingTable$rename_0_getRename_r),
.rename_1_claimRename_r(regRenamingTable$rename_1_claimRename_r),
.rename_1_claimRename_sb(regRenamingTable$rename_1_claimRename_sb),
.rename_1_getRename_r(regRenamingTable$rename_1_getRename_r),
.specUpdate_correctSpeculation_mask(regRenamingTable$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(regRenamingTable$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(regRenamingTable$specUpdate_incorrectSpeculation_kill_tag),
.EN_rename_0_claimRename(regRenamingTable$EN_rename_0_claimRename),
.EN_rename_1_claimRename(regRenamingTable$EN_rename_1_claimRename),
.EN_commit_0_commit(regRenamingTable$EN_commit_0_commit),
.EN_commit_1_commit(regRenamingTable$EN_commit_1_commit),
.EN_specUpdate_incorrectSpeculation(regRenamingTable$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(regRenamingTable$EN_specUpdate_correctSpeculation),
.rename_0_getRename(regRenamingTable$rename_0_getRename),
.RDY_rename_0_getRename(regRenamingTable$RDY_rename_0_getRename),
.RDY_rename_0_claimRename(regRenamingTable$RDY_rename_0_claimRename),
.rename_0_canRename(regRenamingTable$rename_0_canRename),
.RDY_rename_0_canRename(),
.rename_1_getRename(regRenamingTable$rename_1_getRename),
.RDY_rename_1_getRename(regRenamingTable$RDY_rename_1_getRename),
.RDY_rename_1_claimRename(regRenamingTable$RDY_rename_1_claimRename),
.rename_1_canRename(regRenamingTable$rename_1_canRename),
.RDY_rename_1_canRename(),
.RDY_commit_0_commit(regRenamingTable$RDY_commit_0_commit),
.commit_0_canCommit(),
.RDY_commit_0_canCommit(),
.RDY_commit_1_commit(regRenamingTable$RDY_commit_1_commit),
.commit_1_canCommit(),
.RDY_commit_1_canCommit(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule rf
mkRFileSynth rf(.CLK(CLK),
.RST_N(RST_N),
.read_0_rd1_rindx(rf$read_0_rd1_rindx),
.read_0_rd2_rindx(rf$read_0_rd2_rindx),
.read_0_rd3_rindx(rf$read_0_rd3_rindx),
.read_1_rd1_rindx(rf$read_1_rd1_rindx),
.read_1_rd2_rindx(rf$read_1_rd2_rindx),
.read_1_rd3_rindx(rf$read_1_rd3_rindx),
.read_2_rd1_rindx(rf$read_2_rd1_rindx),
.read_2_rd2_rindx(rf$read_2_rd2_rindx),
.read_2_rd3_rindx(rf$read_2_rd3_rindx),
.read_3_rd1_rindx(rf$read_3_rd1_rindx),
.read_3_rd2_rindx(rf$read_3_rd2_rindx),
.read_3_rd3_rindx(rf$read_3_rd3_rindx),
.read_4_rd1_rindx(rf$read_4_rd1_rindx),
.read_4_rd2_rindx(rf$read_4_rd2_rindx),
.read_4_rd3_rindx(rf$read_4_rd3_rindx),
.write_0_wr_data(rf$write_0_wr_data),
.write_0_wr_rindx(rf$write_0_wr_rindx),
.write_1_wr_data(rf$write_1_wr_data),
.write_1_wr_rindx(rf$write_1_wr_rindx),
.write_2_wr_data(rf$write_2_wr_data),
.write_2_wr_rindx(rf$write_2_wr_rindx),
.write_3_wr_data(rf$write_3_wr_data),
.write_3_wr_rindx(rf$write_3_wr_rindx),
.write_4_wr_data(rf$write_4_wr_data),
.write_4_wr_rindx(rf$write_4_wr_rindx),
.EN_write_0_wr(rf$EN_write_0_wr),
.EN_write_1_wr(rf$EN_write_1_wr),
.EN_write_2_wr(rf$EN_write_2_wr),
.EN_write_3_wr(rf$EN_write_3_wr),
.EN_write_4_wr(rf$EN_write_4_wr),
.RDY_write_0_wr(),
.RDY_write_1_wr(),
.RDY_write_2_wr(),
.RDY_write_3_wr(),
.RDY_write_4_wr(),
.read_0_rd1(rf$read_0_rd1),
.RDY_read_0_rd1(),
.read_0_rd2(rf$read_0_rd2),
.RDY_read_0_rd2(),
.read_0_rd3(),
.RDY_read_0_rd3(),
.read_1_rd1(rf$read_1_rd1),
.RDY_read_1_rd1(),
.read_1_rd2(rf$read_1_rd2),
.RDY_read_1_rd2(),
.read_1_rd3(),
.RDY_read_1_rd3(),
.read_2_rd1(rf$read_2_rd1),
.RDY_read_2_rd1(),
.read_2_rd2(rf$read_2_rd2),
.RDY_read_2_rd2(),
.read_2_rd3(rf$read_2_rd3),
.RDY_read_2_rd3(),
.read_3_rd1(rf$read_3_rd1),
.RDY_read_3_rd1(),
.read_3_rd2(rf$read_3_rd2),
.RDY_read_3_rd2(),
.read_3_rd3(),
.RDY_read_3_rd3(),
.read_4_rd1(rf$read_4_rd1),
.RDY_read_4_rd1(),
.read_4_rd2(),
.RDY_read_4_rd2(),
.read_4_rd3(),
.RDY_read_4_rd3());
// submodule rob
mkReorderBufferSynth rob(.CLK(CLK),
.RST_N(RST_N),
.enqPort_0_enq_x(rob$enqPort_0_enq_x),
.enqPort_1_enq_x(rob$enqPort_1_enq_x),
.getOrigPC_0_get_x(rob$getOrigPC_0_get_x),
.getOrigPC_1_get_x(rob$getOrigPC_1_get_x),
.getOrigPC_2_get_x(rob$getOrigPC_2_get_x),
.getOrigPredPC_0_get_x(rob$getOrigPredPC_0_get_x),
.getOrigPredPC_1_get_x(rob$getOrigPredPC_1_get_x),
.getOrig_Inst_0_get_x(rob$getOrig_Inst_0_get_x),
.getOrig_Inst_1_get_x(rob$getOrig_Inst_1_get_x),
.setExecuted_deqLSQ_cause(rob$setExecuted_deqLSQ_cause),
.setExecuted_deqLSQ_ld_killed(rob$setExecuted_deqLSQ_ld_killed),
.setExecuted_deqLSQ_x(rob$setExecuted_deqLSQ_x),
.setExecuted_doFinishAlu_0_set_cf(rob$setExecuted_doFinishAlu_0_set_cf),
.setExecuted_doFinishAlu_0_set_csrData(rob$setExecuted_doFinishAlu_0_set_csrData),
.setExecuted_doFinishAlu_0_set_dst_data(rob$setExecuted_doFinishAlu_0_set_dst_data),
.setExecuted_doFinishAlu_0_set_x(rob$setExecuted_doFinishAlu_0_set_x),
.setExecuted_doFinishAlu_1_set_cf(rob$setExecuted_doFinishAlu_1_set_cf),
.setExecuted_doFinishAlu_1_set_csrData(rob$setExecuted_doFinishAlu_1_set_csrData),
.setExecuted_doFinishAlu_1_set_dst_data(rob$setExecuted_doFinishAlu_1_set_dst_data),
.setExecuted_doFinishAlu_1_set_x(rob$setExecuted_doFinishAlu_1_set_x),
.setExecuted_doFinishFpuMulDiv_0_set_dst_data(rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data),
.setExecuted_doFinishFpuMulDiv_0_set_fflags(rob$setExecuted_doFinishFpuMulDiv_0_set_fflags),
.setExecuted_doFinishFpuMulDiv_0_set_x(rob$setExecuted_doFinishFpuMulDiv_0_set_x),
.setExecuted_doFinishMem_RegData_dst_data(rob$setExecuted_doFinishMem_RegData_dst_data),
.setExecuted_doFinishMem_RegData_x(rob$setExecuted_doFinishMem_RegData_x),
.setExecuted_doFinishMem_access_at_commit(rob$setExecuted_doFinishMem_access_at_commit),
.setExecuted_doFinishMem_non_mmio_st_done(rob$setExecuted_doFinishMem_non_mmio_st_done),
.setExecuted_doFinishMem_vaddr(rob$setExecuted_doFinishMem_vaddr),
.setExecuted_doFinishMem_x(rob$setExecuted_doFinishMem_x),
.setLSQAtCommitNotified_x(rob$setLSQAtCommitNotified_x),
.specUpdate_correctSpeculation_mask(rob$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_inst_tag(rob$specUpdate_incorrectSpeculation_inst_tag),
.specUpdate_incorrectSpeculation_kill_all(rob$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_spec_tag(rob$specUpdate_incorrectSpeculation_spec_tag),
.EN_enqPort_0_enq(rob$EN_enqPort_0_enq),
.EN_enqPort_1_enq(rob$EN_enqPort_1_enq),
.EN_deqPort_0_deq(rob$EN_deqPort_0_deq),
.EN_deqPort_1_deq(rob$EN_deqPort_1_deq),
.EN_setLSQAtCommitNotified(rob$EN_setLSQAtCommitNotified),
.EN_setExecuted_deqLSQ(rob$EN_setExecuted_deqLSQ),
.EN_setExecuted_doFinishAlu_0_set(rob$EN_setExecuted_doFinishAlu_0_set),
.EN_setExecuted_doFinishAlu_1_set(rob$EN_setExecuted_doFinishAlu_1_set),
.EN_setExecuted_doFinishFpuMulDiv_0_set(rob$EN_setExecuted_doFinishFpuMulDiv_0_set),
.EN_setExecuted_doFinishMem(rob$EN_setExecuted_doFinishMem),
.EN_setExecuted_doFinishMem_RegData(rob$EN_setExecuted_doFinishMem_RegData),
.EN_specUpdate_incorrectSpeculation(rob$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(rob$EN_specUpdate_correctSpeculation),
.enqPort_0_canEnq(rob$enqPort_0_canEnq),
.RDY_enqPort_0_canEnq(),
.RDY_enqPort_0_enq(rob$RDY_enqPort_0_enq),
.enqPort_0_getEnqInstTag(rob$enqPort_0_getEnqInstTag),
.RDY_enqPort_0_getEnqInstTag(),
.enqPort_1_canEnq(rob$enqPort_1_canEnq),
.RDY_enqPort_1_canEnq(),
.RDY_enqPort_1_enq(rob$RDY_enqPort_1_enq),
.enqPort_1_getEnqInstTag(rob$enqPort_1_getEnqInstTag),
.RDY_enqPort_1_getEnqInstTag(),
.isEmpty(rob$isEmpty),
.RDY_isEmpty(),
.deqPort_0_canDeq(rob$deqPort_0_canDeq),
.RDY_deqPort_0_canDeq(),
.RDY_deqPort_0_deq(rob$RDY_deqPort_0_deq),
.deqPort_0_getDeqInstTag(rob$deqPort_0_getDeqInstTag),
.RDY_deqPort_0_getDeqInstTag(),
.deqPort_0_deq_data(rob$deqPort_0_deq_data),
.RDY_deqPort_0_deq_data(rob$RDY_deqPort_0_deq_data),
.deqPort_1_canDeq(rob$deqPort_1_canDeq),
.RDY_deqPort_1_canDeq(),
.RDY_deqPort_1_deq(rob$RDY_deqPort_1_deq),
.deqPort_1_getDeqInstTag(),
.RDY_deqPort_1_getDeqInstTag(),
.deqPort_1_deq_data(rob$deqPort_1_deq_data),
.RDY_deqPort_1_deq_data(rob$RDY_deqPort_1_deq_data),
.RDY_setLSQAtCommitNotified(rob$RDY_setLSQAtCommitNotified),
.RDY_setExecuted_deqLSQ(rob$RDY_setExecuted_deqLSQ),
.RDY_setExecuted_doFinishAlu_0_set(rob$RDY_setExecuted_doFinishAlu_0_set),
.RDY_setExecuted_doFinishAlu_1_set(rob$RDY_setExecuted_doFinishAlu_1_set),
.RDY_setExecuted_doFinishFpuMulDiv_0_set(rob$RDY_setExecuted_doFinishFpuMulDiv_0_set),
.RDY_setExecuted_doFinishMem(rob$RDY_setExecuted_doFinishMem),
.RDY_setExecuted_doFinishMem_RegData(),
.getOrigPC_0_get(rob$getOrigPC_0_get),
.RDY_getOrigPC_0_get(),
.getOrigPC_1_get(rob$getOrigPC_1_get),
.RDY_getOrigPC_1_get(),
.getOrigPC_2_get(),
.RDY_getOrigPC_2_get(),
.getOrigPredPC_0_get(rob$getOrigPredPC_0_get),
.RDY_getOrigPredPC_0_get(),
.getOrigPredPC_1_get(rob$getOrigPredPC_1_get),
.RDY_getOrigPredPC_1_get(),
.getOrig_Inst_0_get(rob$getOrig_Inst_0_get),
.RDY_getOrig_Inst_0_get(),
.getOrig_Inst_1_get(rob$getOrig_Inst_1_get),
.RDY_getOrig_Inst_1_get(),
.getEnqTime(rob$getEnqTime),
.RDY_getEnqTime(),
.isEmpty_ehrPort0(),
.RDY_isEmpty_ehrPort0(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule sbAggr
mkScoreboardAggr sbAggr(.CLK(CLK),
.RST_N(RST_N),
.eagerLookup_0_get_r(sbAggr$eagerLookup_0_get_r),
.eagerLookup_1_get_r(sbAggr$eagerLookup_1_get_r),
.setBusy_0_set_dst(sbAggr$setBusy_0_set_dst),
.setBusy_1_set_dst(sbAggr$setBusy_1_set_dst),
.setReady_0_put(sbAggr$setReady_0_put),
.setReady_1_put(sbAggr$setReady_1_put),
.setReady_2_put(sbAggr$setReady_2_put),
.setReady_3_put(sbAggr$setReady_3_put),
.setReady_4_put(sbAggr$setReady_4_put),
.EN_setBusy_0_set(sbAggr$EN_setBusy_0_set),
.EN_setBusy_1_set(sbAggr$EN_setBusy_1_set),
.EN_setReady_0_put(sbAggr$EN_setReady_0_put),
.EN_setReady_1_put(sbAggr$EN_setReady_1_put),
.EN_setReady_2_put(sbAggr$EN_setReady_2_put),
.EN_setReady_3_put(sbAggr$EN_setReady_3_put),
.EN_setReady_4_put(sbAggr$EN_setReady_4_put),
.eagerLookup_0_get(sbAggr$eagerLookup_0_get),
.RDY_eagerLookup_0_get(),
.eagerLookup_1_get(sbAggr$eagerLookup_1_get),
.RDY_eagerLookup_1_get(),
.RDY_setBusy_0_set(),
.RDY_setBusy_1_set(),
.RDY_setReady_0_put(),
.RDY_setReady_1_put(),
.RDY_setReady_2_put(),
.RDY_setReady_3_put(),
.RDY_setReady_4_put());
// submodule sbCons
mkScoreboardCons sbCons(.CLK(CLK),
.RST_N(RST_N),
.eagerLookup_0_get_r(sbCons$eagerLookup_0_get_r),
.eagerLookup_1_get_r(sbCons$eagerLookup_1_get_r),
.lazyLookup_0_get_r(sbCons$lazyLookup_0_get_r),
.lazyLookup_1_get_r(sbCons$lazyLookup_1_get_r),
.lazyLookup_2_get_r(sbCons$lazyLookup_2_get_r),
.lazyLookup_3_get_r(sbCons$lazyLookup_3_get_r),
.lazyLookup_4_get_r(sbCons$lazyLookup_4_get_r),
.setBusy_0_set_dst(sbCons$setBusy_0_set_dst),
.setBusy_1_set_dst(sbCons$setBusy_1_set_dst),
.setReady_0_put(sbCons$setReady_0_put),
.setReady_1_put(sbCons$setReady_1_put),
.setReady_2_put(sbCons$setReady_2_put),
.setReady_3_put(sbCons$setReady_3_put),
.setReady_4_put(sbCons$setReady_4_put),
.EN_setBusy_0_set(sbCons$EN_setBusy_0_set),
.EN_setBusy_1_set(sbCons$EN_setBusy_1_set),
.EN_setReady_0_put(sbCons$EN_setReady_0_put),
.EN_setReady_1_put(sbCons$EN_setReady_1_put),
.EN_setReady_2_put(sbCons$EN_setReady_2_put),
.EN_setReady_3_put(sbCons$EN_setReady_3_put),
.EN_setReady_4_put(sbCons$EN_setReady_4_put),
.eagerLookup_0_get(),
.RDY_eagerLookup_0_get(),
.eagerLookup_1_get(),
.RDY_eagerLookup_1_get(),
.RDY_setBusy_0_set(),
.RDY_setBusy_1_set(),
.RDY_setReady_0_put(),
.RDY_setReady_1_put(),
.RDY_setReady_2_put(),
.RDY_setReady_3_put(),
.RDY_setReady_4_put(),
.lazyLookup_0_get(sbCons$lazyLookup_0_get),
.RDY_lazyLookup_0_get(),
.lazyLookup_1_get(sbCons$lazyLookup_1_get),
.RDY_lazyLookup_1_get(),
.lazyLookup_2_get(sbCons$lazyLookup_2_get),
.RDY_lazyLookup_2_get(),
.lazyLookup_3_get(sbCons$lazyLookup_3_get),
.RDY_lazyLookup_3_get(),
.lazyLookup_4_get(),
.RDY_lazyLookup_4_get());
// submodule specTagManager
mkSpecTagManager specTagManager(.CLK(CLK),
.RST_N(RST_N),
.specUpdate_correctSpeculation_mask(specTagManager$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(specTagManager$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(specTagManager$specUpdate_incorrectSpeculation_kill_tag),
.EN_claimSpecTag(specTagManager$EN_claimSpecTag),
.EN_specUpdate_incorrectSpeculation(specTagManager$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(specTagManager$EN_specUpdate_correctSpeculation),
.currentSpecBits(specTagManager$currentSpecBits),
.RDY_currentSpecBits(),
.nextSpecTag(specTagManager$nextSpecTag),
.RDY_nextSpecTag(specTagManager$RDY_nextSpecTag),
.RDY_claimSpecTag(specTagManager$RDY_claimSpecTag),
.canClaim(specTagManager$canClaim),
.RDY_canClaim(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0());
// submodule v_f_to_TV_0
FIFO2 #(.width(32'd713), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N),
.CLK(CLK),
.D_IN(v_f_to_TV_0$D_IN),
.ENQ(v_f_to_TV_0$ENQ),
.DEQ(v_f_to_TV_0$DEQ),
.CLR(v_f_to_TV_0$CLR),
.D_OUT(v_f_to_TV_0$D_OUT),
.FULL_N(v_f_to_TV_0$FULL_N),
.EMPTY_N(v_f_to_TV_0$EMPTY_N));
// submodule v_f_to_TV_1
FIFO2 #(.width(32'd713), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N),
.CLK(CLK),
.D_IN(v_f_to_TV_1$D_IN),
.ENQ(v_f_to_TV_1$ENQ),
.DEQ(v_f_to_TV_1$DEQ),
.CLR(v_f_to_TV_1$CLR),
.D_OUT(v_f_to_TV_1$D_OUT),
.FULL_N(v_f_to_TV_1$FULL_N),
.EMPTY_N(v_f_to_TV_1$EMPTY_N));
// rule RL_rl_outOfReset
assign CAN_FIRE_RL_rl_outOfReset = !outOfReset ;
assign WILL_FIRE_RL_rl_outOfReset = CAN_FIRE_RL_rl_outOfReset ;
// rule RL_sendDTlbReq
assign CAN_FIRE_RL_sendDTlbReq =
coreFix_memExe_dTlb$RDY_toParent_rqToP_first &&
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq &&
l2Tlb$RDY_toChildren_rqFromC_put ;
assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ;
// rule RL_sendITlbReq
assign CAN_FIRE_RL_sendITlbReq =
l2Tlb$RDY_toChildren_rqFromC_put &&
fetchStage$RDY_iTlbIfc_toParent_rqToP_first &&
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ;
assign WILL_FIRE_RL_sendITlbReq =
CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ;
// rule RL_sendRsToDTlb
assign CAN_FIRE_RL_sendRsToDTlb =
l2Tlb$RDY_toChildren_rsToC_first &&
l2Tlb$RDY_toChildren_rsToC_deq &&
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq &&
l2Tlb$toChildren_rsToC_first[83] ;
assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ;
// rule RL_sendRsToITlb
assign CAN_FIRE_RL_sendRsToITlb =
l2Tlb$RDY_toChildren_rsToC_first &&
l2Tlb$RDY_toChildren_rsToC_deq &&
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq &&
!l2Tlb$toChildren_rsToC_first[83] ;
assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ;
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
coreFix_memExe_dTlb$RDY_toParent_flush_request_get &&
l2Tlb$RDY_toChildren_dTlbReqFlush_put ;
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
// rule RL_mkConnectionGetPut_1
assign CAN_FIRE_RL_mkConnectionGetPut_1 =
l2Tlb$RDY_toChildren_iTlbReqFlush_put &&
fetchStage$RDY_iTlbIfc_toParent_flush_request_get ;
assign WILL_FIRE_RL_mkConnectionGetPut_1 =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
// rule RL_sendFlushDone
assign CAN_FIRE_RL_sendFlushDone =
coreFix_memExe_dTlb$RDY_toParent_flush_response_put &&
l2Tlb$RDY_toChildren_flushDone_get &&
fetchStage$RDY_iTlbIfc_toParent_flush_response_put ;
assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ;
// rule RL_sendRobEnqTime
assign CAN_FIRE_RL_sendRobEnqTime = 1'd1 ;
assign WILL_FIRE_RL_sendRobEnqTime = 1'd1 ;
// rule RL_setDoFlushCaches
assign CAN_FIRE_RL_setDoFlushCaches =
flush_caches && fetchStage$emptyForFlush &&
coreFix_memExe_lsq$noWrongPathLoads ;
assign WILL_FIRE_RL_setDoFlushCaches = CAN_FIRE_RL_setDoFlushCaches ;
// rule RL_setDoFlushBrPred
assign CAN_FIRE_RL_setDoFlushBrPred =
flush_brpred && fetchStage$emptyForFlush ;
assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
// rule RL_readyToFetch
assign CAN_FIRE_RL_readyToFetch =
fetchStage$RDY_done_flushing &&
rg_core_run_state_read__3226_EQ_2_3227_AND_NOT_ETC___d15884 &&
!flush_brpred &&
fetchStage$iMemIfc_flush_done &&
fetchStage$flush_predictors_done ;
assign WILL_FIRE_RL_readyToFetch = CAN_FIRE_RL_readyToFetch ;
// rule RL_flushCaches
assign CAN_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ;
assign WILL_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ;
// rule RL_flushBrPred
assign CAN_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
// rule RL_rl_debug_gpr_read
assign CAN_FIRE_RL_rl_debug_gpr_read =
regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N &&
f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_gpr_read = CAN_FIRE_RL_rl_debug_gpr_read ;
// rule RL_rl_debug_gpr_access_busy
assign CAN_FIRE_RL_rl_debug_gpr_access_busy =
f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_gpr_access_busy =
CAN_FIRE_RL_rl_debug_gpr_access_busy ;
// rule RL_rl_debug_fpr_read
assign CAN_FIRE_RL_rl_debug_fpr_read =
regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N &&
f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$EMPTY_N &&
!f_fpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_fpr_read = CAN_FIRE_RL_rl_debug_fpr_read ;
// rule RL_rl_debug_fpr_access_busy
assign CAN_FIRE_RL_rl_debug_fpr_access_busy =
f_fpr_reqs$EMPTY_N && f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_fpr_access_busy =
CAN_FIRE_RL_rl_debug_fpr_access_busy ;
// rule RL_rl_debug_csr_access_busy
assign CAN_FIRE_RL_rl_debug_csr_access_busy =
f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_csr_access_busy =
CAN_FIRE_RL_rl_debug_csr_access_busy ;
// rule RL_rl_debug_halt_req
assign CAN_FIRE_RL_rl_debug_halt_req =
f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] &&
rg_core_run_state == 2'd2 &&
!f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ;
// rule RL_rl_debug_halt_req_already_halted
assign CAN_FIRE_RL_rl_debug_halt_req_already_halted =
f_run_halt_reqs$EMPTY_N && rg_core_run_state != 2'd2 &&
!f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_halt_req_already_halted =
CAN_FIRE_RL_rl_debug_halt_req_already_halted ;
// rule RL_rl_debug_halted
assign CAN_FIRE_RL_rl_debug_halted =
f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd0 ;
assign WILL_FIRE_RL_rl_debug_halted = CAN_FIRE_RL_rl_debug_halted ;
// rule RL_rl_debug_run_redundant
assign CAN_FIRE_RL_rl_debug_run_redundant =
f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N &&
rg_core_run_state == 2'd2 &&
f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_run_redundant =
CAN_FIRE_RL_rl_debug_run_redundant ;
// rule RL_csrf_minstret_ehr_setRead
assign CAN_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
assign WILL_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
// rule RL_csrf_mcycle_ehr_setRead
assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
// rule RL_rl_debug_csr_read
assign CAN_FIRE_RL_rl_debug_csr_read =
f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_csr_reqs$D_OUT[76] ;
assign WILL_FIRE_RL_rl_debug_csr_read = CAN_FIRE_RL_rl_debug_csr_read ;
// rule RL_rl_debug_csr_write
assign CAN_FIRE_RL_rl_debug_csr_write =
f_csr_reqs$EMPTY_N &&
f_csr_rsps_i_notFull__5945_AND_f_csr_reqs_firs_ETC___d16040 &&
rg_core_run_state == 2'd1 &&
f_csr_reqs$D_OUT[76] ;
assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ;
// rule RL_mmio_handlePRq
assign CAN_FIRE_RL_mmio_handlePRq =
!mmio_pRqQ_empty && !mmio_cRsQ_full &&
(!csrInstOrInterruptInflight_dummy2_0$Q_OUT ||
!csrInstOrInterruptInflight_dummy2_1$Q_OUT ||
!csrInstOrInterruptInflight_rl) ;
assign WILL_FIRE_RL_mmio_handlePRq = CAN_FIRE_RL_mmio_handlePRq ;
// rule RL_mmio_sendDataReq
assign CAN_FIRE_RL_mmio_sendDataReq =
!mmio_dataReqQ_empty && !mmio_cRqQ_full ;
assign WILL_FIRE_RL_mmio_sendDataReq = CAN_FIRE_RL_mmio_sendDataReq ;
// rule RL_mmio_sendInstReq
assign CAN_FIRE_RL_mmio_sendInstReq =
!mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd &&
fetchStage$RDY_mmioIfc_instReq_first_fst &&
fetchStage$RDY_mmioIfc_instReq_deq ;
assign WILL_FIRE_RL_mmio_sendInstReq =
CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ;
// rule RL_mmio_sendDataResp
assign CAN_FIRE_RL_mmio_sendDataResp =
!mmio_dataRespQ_full && !mmio_pRsQ_empty &&
mmio_pRsQ_data_0[66] ;
assign WILL_FIRE_RL_mmio_sendDataResp = CAN_FIRE_RL_mmio_sendDataResp ;
// rule RL_mmio_sendInstResp
assign CAN_FIRE_RL_mmio_sendInstResp =
!mmio_pRsQ_empty && fetchStage$RDY_mmioIfc_instResp_enq &&
!mmio_pRsQ_data_0[66] ;
assign WILL_FIRE_RL_mmio_sendInstResp = CAN_FIRE_RL_mmio_sendInstResp ;
// rule RL_mmio_cRqQ_canonicalize
assign CAN_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
// rule RL_mmio_cRqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_cRqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_cRqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_canonicalize
assign CAN_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
// rule RL_mmio_pRsQ_enqReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_deqReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_clearReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_canonicalize
assign CAN_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
// rule RL_mmio_cRsQ_enqReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_deqReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_clearReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_doFetchTrainBP
assign CAN_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
// rule RL_coreFix_doFetchTrainBP_1
assign CAN_FIRE_RL_coreFix_doFetchTrainBP_1 = coreFix_trainBPQ_0$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_doFetchTrainBP_1 =
coreFix_trainBPQ_0$EMPTY_N && !coreFix_trainBPQ_1$EMPTY_N ;
// rule RL_coreFix_memExe_doIssueSB
assign CAN_FIRE_RL_coreFix_memExe_doIssueSB =
(!coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqStQ_full_rl) &&
coreFix_memExe_stb$RDY_issue ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueSB =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// rule RL_coreFix_memExe_doDeqLdQ_Lr_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1026 &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
!coreFix_memExe_lsq$firstLd[16] &&
coreFix_memExe_lsq$firstLd[101] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
coreFix_memExe_stb$noMatchLdQ &&
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
coreFix_memExe_lsq$firstLd[16] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
// rule RL_coreFix_memExe_dMem_perfReqQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N &&
!coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
!coreFix_memExe_respLrScAmoQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2779 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
// rule RL_renameStage_doRenaming_wrongPath
assign CAN_FIRE_RL_renameStage_doRenaming_wrongPath =
fetchStage$RDY_pipelines_0_first &&
(!fetchStage$pipelines_0_canDeq ||
epochManager$checkEpoch_0_check ||
fetchStage$RDY_pipelines_0_deq) &&
NOT_fetchStage_pipelines_1_canDeq__2938_2939_O_ETC___d12947 &&
!epochManager$checkEpoch_0_check ;
assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath =
CAN_FIRE_RL_renameStage_doRenaming_wrongPath ;
// rule RL_commitStage_doCommitTrap_flush
assign CAN_FIRE_RL_commitStage_doCommitTrap_flush =
rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq &&
commitStage_f_rob_data$FULL_N &&
(rob$deqPort_0_deq_data[12] ||
epochManager$RDY_incrementEpoch) &&
!commitStage_rg_run_state &&
!commitStage_commitTrap[133] &&
rob$deqPort_0_deq_data[167] ;
assign WILL_FIRE_RL_commitStage_doCommitTrap_flush =
CAN_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_commitStage_rl_send_tv_reset
assign CAN_FIRE_RL_commitStage_rl_send_tv_reset =
v_f_to_TV_0$FULL_N && commitStage_rg_just_after_reset ;
assign WILL_FIRE_RL_commitStage_rl_send_tv_reset =
CAN_FIRE_RL_commitStage_rl_send_tv_reset ;
// rule RL_commitStage_doCommitTrap_handle
assign CAN_FIRE_RL_commitStage_doCommitTrap_handle =
commitStage_f_rob_data$EMPTY_N &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14850 &&
(commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14875) &&
!commitStage_rg_run_state &&
commitStage_commitTrap[133] ;
assign WILL_FIRE_RL_commitStage_doCommitTrap_handle =
CAN_FIRE_RL_commitStage_doCommitTrap_handle &&
!WILL_FIRE_RL_commitStage_rl_send_tv_reset &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_commitStage_doCommitKilledLd
assign CAN_FIRE_RL_commitStage_doCommitKilledLd =
epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data &&
rob$RDY_deqPort_0_deq &&
!commitStage_rg_run_state &&
!commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
rob$deqPort_0_deq_data[18] ;
assign WILL_FIRE_RL_commitStage_doCommitKilledLd =
CAN_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_commitStage_doCommitSystemInst
assign CAN_FIRE_RL_commitStage_doCommitSystemInst =
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
rob_RDY_deqPort_0_deq_data__4557_AND_rob_RDY_d_ETC___d15204 &&
NOT_commitStage_rg_run_state_4566_4567_AND_NOT_ETC___d15210 &&
(rob$deqPort_0_deq_data[257:253] == 5'd0 ||
rob$deqPort_0_deq_data[257:253] == 5'd21 ||
rob$deqPort_0_deq_data[257:253] == 5'd17 ||
rob$deqPort_0_deq_data[257:253] == 5'd18 ||
rob$deqPort_0_deq_data[257:253] == 5'd13 ||
rob$deqPort_0_deq_data[257:253] == 5'd16 ||
rob$deqPort_0_deq_data[257:253] == 5'd15 ||
rob$deqPort_0_deq_data[257:253] == 5'd19 ||
rob$deqPort_0_deq_data[257:253] == 5'd20) ;
assign WILL_FIRE_RL_commitStage_doCommitSystemInst =
CAN_FIRE_RL_commitStage_doCommitSystemInst &&
!WILL_FIRE_RL_commitStage_rl_send_tv_reset &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_csr_write &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_csrf_incCycle
assign CAN_FIRE_RL_csrf_incCycle = 1'd1 ;
assign WILL_FIRE_RL_csrf_incCycle = 1'd1 ;
// rule RL_csrf_mcycle_ehr_data_canon
assign CAN_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
assign WILL_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
// rule RL_commitStage_notifyLSQCommit
assign CAN_FIRE_RL_commitStage_notifyLSQCommit =
rob$RDY_setLSQAtCommitNotified && rob$RDY_deqPort_0_deq_data &&
!commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
!rob$deqPort_0_deq_data[25] &&
rob$deqPort_0_deq_data[15] &&
!rob$deqPort_0_deq_data[14] ;
assign WILL_FIRE_RL_commitStage_notifyLSQCommit =
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
// rule RL_commitStage_doCommitNormalInst
assign CAN_FIRE_RL_commitStage_doCommitNormalInst =
rob$RDY_deqPort_0_deq_data &&
NOT_rob_deqPort_0_canDeq__5509_5510_OR_rob_RDY_ETC___d15551 &&
NOT_commitStage_rg_run_state_4566_4567_AND_NOT_ETC___d15210 &&
rob$deqPort_0_deq_data[257:253] != 5'd0 &&
rob$deqPort_0_deq_data[257:253] != 5'd21 &&
rob$deqPort_0_deq_data[257:253] != 5'd17 &&
rob$deqPort_0_deq_data[257:253] != 5'd18 &&
rob$deqPort_0_deq_data[257:253] != 5'd13 &&
rob$deqPort_0_deq_data[257:253] != 5'd16 &&
rob$deqPort_0_deq_data[257:253] != 5'd15 &&
rob$deqPort_0_deq_data[257:253] != 5'd19 &&
rob$deqPort_0_deq_data[257:253] != 5'd20 ;
assign WILL_FIRE_RL_commitStage_doCommitNormalInst =
CAN_FIRE_RL_commitStage_doCommitNormalInst &&
!WILL_FIRE_RL_commitStage_rl_send_tv_reset ;
// rule RL_csrf_minstret_ehr_data_canon
assign CAN_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
assign WILL_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
// rule RL_coreFix_aluExe_1_doFinishAlu_T
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
coreFix_aluExe_1_exeToFinQ$first[17] &&
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_1_set &&
epochManager$RDY_incrementEpoch &&
coreFix_trainBPQ_1$FULL_N ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
!WILL_FIRE_RL_rl_debug_resume ;
// rule RL_coreFix_aluExe_0_doFinishAlu_T
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
coreFix_aluExe_0_exeToFinQ$first[17] &&
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_0_set &&
epochManager$RDY_incrementEpoch &&
coreFix_trainBPQ_0$FULL_N ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
!WILL_FIRE_RL_rl_debug_resume ;
// rule RL_coreFix_aluExe_0_doFinishAlu_F
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
!coreFix_aluExe_0_exeToFinQ$first[17] &&
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ_RDY_first__2815_AND_ETC___d12855 ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_aluExe_1_doFinishAlu_F
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
!coreFix_aluExe_1_exeToFinQ$first[17] &&
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ_RDY_first__2141_AND_ETC___d12182 ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_aluExe_1_doExeAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu =
coreFix_aluExe_1_regToExeQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ$RDY_enq &&
coreFix_aluExe_1_regToExeQ$RDY_first ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doExeAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu =
coreFix_aluExe_0_regToExeQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ$RDY_enq &&
coreFix_aluExe_0_regToExeQ$RDY_first ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doRegReadAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
coreFix_aluExe_1_dispToRegQ$RDY_deq &&
coreFix_aluExe_1_regToExeQ$RDY_enq &&
coreFix_aluExe_1_dispToRegQ_RDY_first__1489_AN_ETC___d11580 ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doRegReadAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
coreFix_aluExe_0_dispToRegQ$RDY_deq &&
coreFix_aluExe_0_regToExeQ$RDY_enq &&
coreFix_aluExe_0_dispToRegQ_RDY_first__2348_AN_ETC___d12439 ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doDispatchAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
coreFix_aluExe_0_dispToRegQ$RDY_enq &&
coreFix_aluExe_0_rsAlu$RDY_doDispatch &&
coreFix_aluExe_0_rsAlu$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doDispatchAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
coreFix_aluExe_1_dispToRegQ$RDY_enq &&
coreFix_aluExe_1_rsAlu$RDY_doDispatch &&
coreFix_aluExe_1_rsAlu$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doDeqLdQ_Lr_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
!coreFix_memExe_respLrScAmoQ_empty &&
rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3977 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5369 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6761 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8153 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqLdQ_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
coreFix_memExe_lsq$firstLd[7] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
!coreFix_memExe_lsq$firstLd[101] &&
!coreFix_memExe_lsq$firstLd[16] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
!mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doFinishMem
assign CAN_FIRE_RL_coreFix_memExe_doFinishMem =
rob$RDY_setExecuted_doFinishMem &&
coreFix_memExe_dTlb$RDY_deqProcResp &&
coreFix_memExe_dTlb$RDY_procResp ;
assign WILL_FIRE_RL_coreFix_memExe_doFinishMem =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1026 &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
!coreFix_memExe_lsq$firstSt[77] &&
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1 ||
coreFix_memExe_lsq$firstSt[158:157] == 2'd2) &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
coreFix_memExe_stb$noMatchStQ &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd3 &&
coreFix_memExe_lsq$firstSt[77] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_mmio_dataReqQ_canonicalize
assign CAN_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataReqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataReqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataReqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_sendLrScAmoToMem
assign CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141 &&
(!coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
!coreFix_memExe_reqLrScAmoQ_empty_rl) ;
assign WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_doIssueLdFromIssueQ
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
coreFix_memExe_lsq$RDY_getIssueLd &&
!coreFix_memExe_forwardQ_full &&
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1487 ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doIssueLdFromUpdate
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
!coreFix_memExe_forwardQ_full &&
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1487 &&
coreFix_memExe_issueLd$whas ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqStQ_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
coreFix_memExe_lsq$firstSt[4] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_Fence
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] == 2'd3 &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
!coreFix_memExe_respLrScAmoQ_empty &&
rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
!mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_mmio_dataRespQ_canonicalize
assign CAN_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataRespQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataRespQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataRespQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_canonicalize
assign CAN_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataPendQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_sendLdToMem
assign CAN_FIRE_RL_coreFix_memExe_sendLdToMem =
(!coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_reqLdQ_empty_lat_0$whas ||
!coreFix_memExe_reqLdQ_empty_rl) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141 ;
assign WILL_FIRE_RL_coreFix_memExe_sendLdToMem =
CAN_FIRE_RL_coreFix_memExe_sendLdToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_sendStToMem
assign CAN_FIRE_RL_coreFix_memExe_sendStToMem =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141 &&
(!coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT ||
CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
!coreFix_memExe_reqStQ_empty_rl) ;
assign WILL_FIRE_RL_coreFix_memExe_sendStToMem =
CAN_FIRE_RL_coreFix_memExe_sendStToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2137 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd0 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2748 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
2'd0 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqStQ_St_Mem
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] == 2'd0 &&
!coreFix_memExe_lsq$firstSt[77] &&
coreFix_memExe_stb$getEnqIndex[2] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doRespLdMem
assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem =
!coreFix_memExe_memRespLdQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem =
CAN_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doRespLdForward
assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward =
!coreFix_memExe_forwardQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward =
CAN_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_rl_debug_gpr_write
assign CAN_FIRE_RL_rl_debug_gpr_write =
regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N &&
f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
f_gpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_gpr_write = CAN_FIRE_RL_rl_debug_gpr_write ;
// rule RL_rl_debug_fpr_write
assign CAN_FIRE_RL_rl_debug_fpr_write =
regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N &&
f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$EMPTY_N &&
f_fpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_fpr_write = CAN_FIRE_RL_rl_debug_fpr_write ;
// rule RL_coreFix_memExe_doExeMem
assign CAN_FIRE_RL_coreFix_memExe_doExeMem =
coreFix_memExe_regToExeQ$RDY_deq &&
coreFix_memExe_regToExeQ$RDY_first &&
coreFix_memExe_dTlb$RDY_procReq ;
assign WILL_FIRE_RL_coreFix_memExe_doExeMem =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
// rule RL_prepareCachesAndTlbs
assign CAN_FIRE_RL_prepareCachesAndTlbs =
(!flush_tlbs ||
coreFix_memExe_dTlb$RDY_flush &&
fetchStage$RDY_iTlbIfc_flush) &&
(flush_reservation || flush_tlbs || update_vm_info) ;
assign WILL_FIRE_RL_prepareCachesAndTlbs =
CAN_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_rl_debug_resume
assign CAN_FIRE_RL_rl_debug_resume =
commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush &&
fetchStage$RDY_iTlbIfc_flush &&
f_run_halt_reqs$EMPTY_N &&
f_run_halt_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
f_run_halt_reqs$D_OUT &&
!f_gpr_reqs$EMPTY_N &&
!f_fpr_reqs$EMPTY_N &&
!f_csr_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ;
// rule RL_coreFix_memExe_doRegReadMem
assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem =
coreFix_memExe_dispToRegQ$RDY_deq &&
coreFix_memExe_regToExeQ_RDY_enq__564_AND_core_ETC___d1654 ;
assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem =
CAN_FIRE_RL_coreFix_memExe_doRegReadMem &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doDispatchMem
assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem =
coreFix_memExe_dispToRegQ$RDY_enq &&
coreFix_memExe_rsMem$RDY_doDispatch &&
coreFix_memExe_rsMem$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem =
CAN_FIRE_RL_coreFix_memExe_doDispatchMem &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit &&
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
(!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq &&
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8542 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq &&
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq &&
coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first__2_ETC___d8396 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
!coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready =
1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon =
1'd1 ;
// rule RL_renameStage_doRenaming_Trap
assign CAN_FIRE_RL_renameStage_doRenaming_Trap =
epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq &&
fetchStage$RDY_pipelines_0_first &&
fetchStage$RDY_pipelines_0_deq &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13223 &&
rob$isEmpty &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_renameStage_doRenaming_Trap =
CAN_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_renameStage_doRenaming_SystemInst
assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst =
epochManager$RDY_incrementEpoch &&
rob_RDY_enqPort_0_enq__2954_AND_regRenamingTab_ETC___d13476 &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13530 &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst =
CAN_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_csrInstOrInterruptInflight_canon
assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
assign WILL_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
// rule RL_commitStage_doSetLSQAtCommit
assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit =
MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 ||
WILL_FIRE_RL_commitStage_notifyLSQCommit ;
assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
// rule RL_commitStage_doSetLSQAtCommit_1
assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] != 5'd0 &&
rob$deqPort_1_deq_data[257:253] != 5'd21 &&
rob$deqPort_1_deq_data[257:253] != 5'd17 &&
rob$deqPort_1_deq_data[257:253] != 5'd18 &&
rob$deqPort_1_deq_data[257:253] != 5'd13 &&
rob$deqPort_1_deq_data[257:253] != 5'd16 &&
rob$deqPort_1_deq_data[257:253] != 5'd15 &&
rob$deqPort_1_deq_data[257:253] != 5'd19 &&
rob$deqPort_1_deq_data[257:253] != 5'd20 &&
rob$deqPort_1_deq_data[13] ;
assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
// rule RL_renameStage_doRenaming
assign CAN_FIRE_RL_renameStage_doRenaming =
(!fetchStage$pipelines_0_canDeq ||
IF_fetchStage_RDY_pipelines_0_first__2929_AND__ETC___d13610) &&
IF_NOT_fetchStage_pipelines_0_canDeq__2930_293_ETC___d14074 &&
IF_NOT_fetchStage_pipelines_0_canDeq__2930_293_ETC___d14082 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14256 &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14260 ;
assign WILL_FIRE_RL_renameStage_doRenaming =
CAN_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_mmio_pRqQ_canonicalize
assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
// rule RL_mmio_pRqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_pRqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_pRqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_globalSpecUpdate_canon_correct_spec
assign CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_1 =
WILL_FIRE_RL_renameStage_doRenaming ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_2 =
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_3 =
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign MUX_commitStage_rg_run_state$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ;
assign MUX_commitStage_rg_serial_num$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 ;
assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[13] ;
assign MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3 =
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2628 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2564) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2611 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2822 &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
2'd0 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046) ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2152) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2667) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2731 ;
assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634) ;
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2659) ;
assign MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2594 ;
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign MUX_coreFix_trainBPQ_0$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ;
assign MUX_coreFix_trainBPQ_1$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ;
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 ;
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
(commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] == 4'd3) ;
assign MUX_csrf_external_int_en_vec_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd22) ;
assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ;
assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd16 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd29) ;
assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd29 ;
assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ;
assign MUX_csrf_fflags_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__5509_5510_OR__ETC___d15835 ;
assign MUX_csrf_fflags_reg$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd2) ;
assign MUX_csrf_fflags_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
assign MUX_csrf_frm_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd2) ;
assign MUX_csrf_fs_reg$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd2 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18) ;
assign MUX_csrf_fs_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3 ||
f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
assign MUX_csrf_ie_vec_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18) ;
assign MUX_csrf_ie_vec_0$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
assign MUX_csrf_ie_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_ie_vec_1$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ;
assign MUX_csrf_mcause_code_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd27 ;
assign MUX_csrf_mcause_code_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ;
assign MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ;
assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2816 ;
assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd30 ;
assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ;
assign MUX_csrf_mepc_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd26 ;
assign MUX_csrf_mepc_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd833 ;
assign MUX_csrf_mideleg_11_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ;
assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2818 ;
assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd31 ;
assign MUX_csrf_mpp_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_mscratch_csr$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd832 ;
assign MUX_csrf_mtval_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd28 ;
assign MUX_csrf_mtval_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd835 ;
assign MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ;
assign MUX_csrf_ppn_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ;
assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_prv_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ;
assign MUX_csrf_prv_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ;
assign MUX_csrf_rg_dcsr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd36 ;
assign MUX_csrf_rg_dpc$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd37 ;
assign MUX_csrf_rg_dpc$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1969 ;
assign MUX_csrf_rg_dscratch0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1970 ;
assign MUX_csrf_rg_dscratch1$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1971 ;
assign MUX_csrf_scause_code_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd14 ;
assign MUX_csrf_scause_code_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ;
assign MUX_csrf_scounteren_cy_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ;
assign MUX_csrf_sepc_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd13 ;
assign MUX_csrf_sepc_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd321 ;
assign MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] != 2'd0 &&
mmio_pRqQ_data_0[37:36] != 2'd1 ;
assign MUX_csrf_spp_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_sscratch_csr$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd320 ;
assign MUX_csrf_stats_module_writeQ$enq_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2049 ;
assign MUX_csrf_stval_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd15 ;
assign MUX_csrf_stval_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd323 ;
assign MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ;
assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ;
assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d14401 &&
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 ;
assign MUX_flush_reservation$write_1__SEL_2 =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ;
assign MUX_flush_tlbs$write_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ;
assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 =
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 =
MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 &&
csrf_rg_dcsr[2] ;
assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
csrf_rg_dcsr[2] ;
assign MUX_rf$write_3_wr_1__PSEL_1 =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
assign MUX_rf$write_3_wr_1__SEL_1 =
MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_rf$write_3_wr_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_rf$write_3_wr_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_rf$write_3_wr_1__SEL_4 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_rf$write_3_wr_1__SEL_5 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_rf$write_3_wr_2__SEL_1 =
MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_rg_core_run_state$write_1__SEL_4 =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ;
assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ;
assign MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_1 =
MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_1 =
MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_sbAggr$setReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_sbAggr$setReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_sbCons$setReady_3_put_1__SEL_1 =
MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_sbCons$setReady_3_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_sbCons$setReady_3_put_1__SEL_3 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_started$write_1__SEL_1 =
CAN_FIRE_RL_rl_debug_resume &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
assign MUX_v_f_to_TV_0$enq_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ;
assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 =
{ 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ;
assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 =
{ 2'd3, f_fpr_reqs$D_OUT[68:64], 20'd345386 } ;
assign MUX_commitStage_commitTrap$write_1__VAL_2 =
{ 1'd1,
rob$deqPort_0_deq_data[353:290],
x__h702237,
rob_deqPort_0_deq_data__4560_BIT_166_4576_CONC_ETC___d14625 } ;
assign MUX_commitStage_rg_serial_num$write_1__VAL_1 =
commitStage_rg_serial_num + 64'd1 ;
assign MUX_commitStage_rg_serial_num$write_1__VAL_3 =
commitStage_rg_serial_num + y__h729146 ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 =
(k__h672122 == 1'd0 &&
fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14266) ?
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d13758,
fetchStage_pipelines_1_first__2941_BIT_173_375_ETC___d13842,
fetchStage$pipelines_1_first[160:128],
fetchStage$pipelines_1_first[255:232],
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h687315,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 =
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
5'd10,
sbAggr$eagerLookup_0_get } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 =
{ 1'd1,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 =
{ 1'd1,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 =
{ 1'd1,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 =
{ 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 =
{ 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 =
{ 1'd1, coreFix_memExe_lsq$getHit[7:1] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 ?
3'd3 :
3'd5) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2568 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
53'h15555555555555 } :
58'h155555555555554) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2579 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
55'h15555555555555 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
{ (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } :
{ (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 ?
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2539 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0]) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2552 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2173,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2529 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 =
{ coreFix_memExe_dMem_cache_m_banks_0_processAmo[151:100],
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0],
IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2034,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd0) ?
n__h195496 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2788,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) :
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2555 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 =
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84],
x__h288305 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 =
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
x__h289750,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 =
{ 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2969,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 =
{ 2'd2,
addr__h292526,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3039 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 =
{ x__h155113, x__h155119, 84'h82AAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 =
{ x__h158660, x__h158666, 84'hCAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 =
{ x__h161476,
x__h161480,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1228,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1232,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1237,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1241,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255,
x__h163328,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 =
{ 1'd0,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
resp_addr__h294503,
2'd0,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ;
assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 =
{ prv__h730804,
prv__h730804 != 2'd3 && csrf_vm_mode_sv39_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_ppn_reg } ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_lsq$getIssueLd[76:72],
coreFix_memExe_lsq$issueLd[63:0] } ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_issueLd$wget[76:72],
coreFix_memExe_lsq$issueLd[63:0] } ;
assign MUX_coreFix_memExe_lsq$getHit_1__VAL_1 =
{ 1'd0,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148] } ;
assign MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 =
{ coreFix_memExe_stb$search[67],
coreFix_memExe_stb$search[67] ?
coreFix_memExe_stb$search[66:65] :
2'h2,
coreFix_memExe_stb$search[64],
coreFix_memExe_stb$search[64] ?
coreFix_memExe_stb$search[63:0] :
64'hAAAAAAAAAAAAAAAA } ;
always@(coreFix_memExe_memRespLdQ_deqP or
coreFix_memExe_memRespLdQ_data_0 or
coreFix_memExe_memRespLdQ_data_1)
begin
case (coreFix_memExe_memRespLdQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
coreFix_memExe_memRespLdQ_data_0[68:64];
1'd1:
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
coreFix_memExe_memRespLdQ_data_1[68:64];
endcase
end
always@(coreFix_memExe_forwardQ_deqP or
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
begin
case (coreFix_memExe_forwardQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
coreFix_memExe_forwardQ_data_0[68:64];
1'd1:
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
coreFix_memExe_forwardQ_data_1[68:64];
endcase
end
always@(coreFix_memExe_memRespLdQ_deqP or
coreFix_memExe_memRespLdQ_data_0 or
coreFix_memExe_memRespLdQ_data_1)
begin
case (coreFix_memExe_memRespLdQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
coreFix_memExe_memRespLdQ_data_0[63:0];
1'd1:
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
coreFix_memExe_memRespLdQ_data_1[63:0];
endcase
end
always@(coreFix_memExe_forwardQ_deqP or
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
begin
case (coreFix_memExe_forwardQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
coreFix_memExe_forwardQ_data_0[63:0];
1'd1:
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
coreFix_memExe_forwardQ_data_1[63:0];
endcase
end
assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148],
x__h198698 } ;
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 =
{ 5'd0,
coreFix_memExe_lsq$firstSt[141:78],
2'd3,
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1) ? 3'd3 : 3'd4,
coreFix_memExe_lsq$firstSt[76:5],
coreFix_memExe_lsq$firstSt[156:153],
coreFix_memExe_lsq$firstSt[69] &&
coreFix_memExe_lsq$firstSt[70] &&
coreFix_memExe_lsq$firstSt[71] &&
coreFix_memExe_lsq$firstSt[72] &&
coreFix_memExe_lsq$firstSt[73] &&
coreFix_memExe_lsq$firstSt[74] &&
coreFix_memExe_lsq$firstSt[75] &&
coreFix_memExe_lsq$firstSt[76],
coreFix_memExe_lsq$firstSt[152:151] } ;
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 =
{ 5'd0,
coreFix_memExe_lsq$firstLd[80:17],
84'h92AAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) ?
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2596 } :
65'h10000000000000001) :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2599 ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2596 } ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ?
curData__h193958 :
{ {32{x__h194721[31]}}, x__h194721 } } ;
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 =
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
coreFix_aluExe_0_exeToFinQ$first[326:322],
coreFix_aluExe_0_exeToFinQ$first[18],
coreFix_aluExe_0_exeToFinQ$first[300:277],
1'd0,
coreFix_aluExe_0_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 =
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
coreFix_aluExe_0_exeToFinQ$first[326:322],
coreFix_aluExe_0_exeToFinQ$first[18],
coreFix_aluExe_0_exeToFinQ$first[300:277],
1'd1,
coreFix_aluExe_0_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 =
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
coreFix_aluExe_1_exeToFinQ$first[326:322],
coreFix_aluExe_1_exeToFinQ$first[18],
coreFix_aluExe_1_exeToFinQ$first[300:277],
1'd0,
coreFix_aluExe_1_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 =
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
coreFix_aluExe_1_exeToFinQ$first[326:322],
coreFix_aluExe_1_exeToFinQ$first[18],
coreFix_aluExe_1_exeToFinQ$first[300:277],
1'd1,
coreFix_aluExe_1_exeToFinQ$first[276] } ;
assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 =
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 ||
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ;
assign MUX_csrf_fflags_reg$write_1__VAL_1 =
csrf_fflags_reg | fflags__h729123 ;
assign MUX_csrf_frm_reg$write_1__VAL_1 =
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd1) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] :
robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ;
assign MUX_csrf_frm_reg$write_1__VAL_2 =
(f_csr_reqs$D_OUT[75:64] == 12'd2) ?
f_csr_reqs$D_OUT[2:0] :
f_csr_reqs$D_OUT[7:5] ;
always@(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 or
robdeqPort_0_deq_data_BITS_95_TO_32__q245)
begin
case (IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189)
6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11;
default: MUX_csrf_fs_reg$write_1__VAL_2 =
robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13];
endcase
end
always@(f_csr_reqs$D_OUT)
begin
case (f_csr_reqs$D_OUT[75:64])
12'd1, 12'd2, 12'd3: MUX_csrf_fs_reg$write_1__VAL_3 = 2'b11;
default: MUX_csrf_fs_reg$write_1__VAL_3 = f_csr_reqs$D_OUT[14:13];
endcase
end
assign MUX_csrf_ie_vec_1$write_1__VAL_1 =
(rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18)) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] :
csrf_prev_ie_vec_1 ;
assign MUX_csrf_ie_vec_3$write_1__VAL_1 =
(rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] :
csrf_prev_ie_vec_3 ;
assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 =
rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 =
n__read__h724080 + 64'd1 ;
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 =
n__read__h724080 + { 62'd0, x__h729365 } ;
assign MUX_csrf_mpp_reg$write_1__VAL_1 =
(rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18) ?
MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] :
2'd0 ;
assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_mtval_csr$write_1__VAL_2 =
commitStage_commitTrap[4] ? 64'd0 : trap_val__h709367 ;
assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 =
rob$deqPort_0_deq_data[257:253] != 5'd13 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 !=
6'd8 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 !=
6'd18 ||
MUX_csrf_mtval_csr$write_1__VAL_1[5] ;
assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 =
rob$deqPort_0_deq_data[257:253] != 5'd13 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 !=
6'd18 ||
MUX_csrf_mtval_csr$write_1__VAL_1[7] ;
assign MUX_csrf_prv_reg$write_1__VAL_1 =
(rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd36) ?
MUX_csrf_mtval_csr$write_1__VAL_1[1:0] :
((rob$deqPort_0_deq_data[257:253] == 5'd19) ?
x__h720450 :
csrf_mpp_reg) ;
assign MUX_csrf_rg_dcsr$write_1__VAL_2 =
{ 32'b0,
csrf_rg_dcsr[31:9],
dcsr_cause__h707848,
csrf_rg_dcsr[5:2],
csrf_prv_reg } ;
assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 =
(mmio_pRqQ_data_0[37:36] == 2'd2) ?
mmio_pRqQ_data_0[0] :
amoExec___d882[0] ;
assign MUX_csrf_spp_reg$write_1__VAL_1 =
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18) &&
MUX_csrf_sepc_csr$write_1__VAL_1[8] ;
assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h733205 } ;
assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ;
assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_2 =
{ csrf_prv_reg,
csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_ppn_reg } ;
always@(rob$deqPort_0_deq_data or
next_pc__h720279 or csrf_sepc_csr or csrf_mepc_csr)
begin
case (rob$deqPort_0_deq_data[257:253])
5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr;
5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr;
default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h720279;
endcase
end
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dTlb$toParent_rqToP_first[1:0],
coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ;
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 =
{ 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ;
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
mmio_dataReqQ_data_0[141:78],
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q275,
mmio_dataReqQ_data_0[71:0] } ;
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
fetchStage$mmioIfc_instReq_first_fst,
5'd2,
fetchStage$mmioIfc_instReq_first_snd,
72'hAAAAAAAAAAAAAAAAAA } ;
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_lsq$firstSt[141:78],
(coreFix_memExe_lsq$firstSt[158:157] == 2'd0) ?
6'd42 :
{ 2'd3, coreFix_memExe_lsq$firstSt[156:153] },
coreFix_memExe_lsq$firstSt[76:5] } ;
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_lsq$firstLd[80:17],
6'd26,
coreFix_memExe_lsq$firstLd[15:0],
56'hAAAAAAAAAAAAAA } ;
assign MUX_rf$write_2_wr_2__VAL_2 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
res_data__h340400 :
res_data__h340395 ;
assign MUX_rf$write_2_wr_2__VAL_3 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
res_data__h386102 :
res_data__h386097 ;
assign MUX_rf$write_2_wr_2__VAL_4 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
res_data__h431797 :
res_data__h431792 ;
assign MUX_rf$write_2_wr_2__VAL_5 =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ?
data___1__h477611 :
data__h477099 ;
assign MUX_rf$write_2_wr_2__VAL_6 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ?
data___1__h478505 :
data__h477993 ;
assign MUX_rf$write_3_wr_2__VAL_4 =
coreFix_memExe_lsq$firstLd[100] ?
coreFix_memExe_respLrScAmoQ_data_0 :
IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386 ;
assign MUX_rf$write_3_wr_2__VAL_5 =
coreFix_memExe_lsq$firstLd[100] ?
mmio_dataRespQ_data_0[63:0] :
IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435 ;
assign MUX_rob$enqPort_0_enq_1__VAL_1 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[75:69],
64'hAAAAAAAAAAAAAAAA,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143,
73'h1280000000000000000,
fetchStage$pipelines_0_first[323:260],
5'd0,
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74],
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 &&
fetchStage$pipelines_0_first[194:192] != 3'd2 &&
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4,
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14363 } ;
assign MUX_rob$enqPort_0_enq_1__VAL_2 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[75:69],
64'hAAAAAAAAAAAAAAAA,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143,
2'd1,
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_N_ETC___d13236,
IF_NOT_renameStage_rg_m_halt_req_2959_BIT_4_29_ETC___d13451,
fetchStage$pipelines_0_first[63:0],
2'd0,
fetchStage$pipelines_0_first[323:260],
20'd13601,
specTagManager$currentSpecBits } ;
assign MUX_rob$enqPort_0_enq_1__VAL_3 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[75:69],
64'hAAAAAAAAAAAAAAAA,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143,
73'h1280000000000000000,
fetchStage$pipelines_0_first[323:260],
5'd0,
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74],
fetchStage$pipelines_0_first[194:192] != 3'd0,
13'h1521,
specTagManager$currentSpecBits } ;
assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 =
{ 1'd1,
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 } ;
assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 =
{ 1'd1,
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q277 } ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] :
res_fflags__h340396 ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] :
res_fflags__h386098 ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] :
res_fflags__h431793 ;
assign MUX_v_f_to_TV_0$enq_1__VAL_1 =
{ commitStage_rg_serial_num,
commitStage_f_rob_data$D_OUT[353:181],
CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q278,
commitStage_f_rob_data$D_OUT[167:166],
commitStage_f_rob_data$D_OUT[166] ?
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 :
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q280,
commitStage_f_rob_data_first__4972_BITS_161_TO_ETC___d15136 } ;
assign MUX_v_f_to_TV_0$enq_1__VAL_2 =
{ commitStage_rg_serial_num,
rob$deqPort_0_deq_data[353:182],
rob_deqPort_0_deq_data__4560_BIT_181_4634_CONC_ETC___d14717,
rob$deqPort_0_deq_data[167],
rob_deqPort_0_deq_data__4560_BIT_166_4576_CONC_ETC___d14625,
rob$deqPort_0_deq_data[161:98],
IF_rob_deqPort_0_deq_data__4560_BITS_97_TO_96__ETC___d14724,
rob$deqPort_0_deq_data[31:26],
mstatus_csr__read__h614607,
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_v_f_to_TV_0$enq_1__VAL_3 =
{ 391'h000000000000000055555555555555555555555529555555555555555552AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA94,
mstatus_csr__read__h614607,
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_v_f_to_TV_0$enq_1__VAL_4 =
{ commitStage_rg_serial_num,
rob$deqPort_0_deq_data[353:182],
rob_deqPort_0_deq_data__4560_BIT_181_4634_CONC_ETC___d14717,
rob$deqPort_0_deq_data[167],
rob_deqPort_0_deq_data__4560_BIT_166_4576_CONC_ETC___d14625,
rob_deqPort_0_deq_data__4560_BITS_161_TO_98_45_ETC___d15481 } ;
// inlined wires
assign csrf_minstret_ehr_data_lat_0$whas =
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ||
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 ;
assign csrf_minstret_ehr_data_lat_1$whas =
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
WILL_FIRE_RL_commitStage_doCommitNormalInst ;
assign csrf_minstret_ehr_data_dummy_1_0$whas =
WILL_FIRE_RL_commitStage_doCommitNormalInst ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign csrf_mcycle_ehr_data_lat_0$whas =
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ||
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 ;
assign csrInstOrInterruptInflight_lat_1$whas =
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
WILL_FIRE_RL_renameStage_doRenaming_Trap &&
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_N_ETC___d13466 ;
assign mmio_dataReqQ_enqReq_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ?
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign mmio_dataReqQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
assign mmio_dataRespQ_enqReq_lat_0$wget = { 1'd1, mmio_pRsQ_data_0[64:0] } ;
assign mmio_dataRespQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ;
assign mmio_dataPendQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ;
assign mmio_cRqQ_enqReq_lat_0$wget =
WILL_FIRE_RL_mmio_sendDataReq ?
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign mmio_cRqQ_enqReq_lat_0$whas =
WILL_FIRE_RL_mmio_sendDataReq || WILL_FIRE_RL_mmio_sendInstReq ;
assign mmio_pRsQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRs_enq_x } ;
assign mmio_pRsQ_deqReq_lat_0$whas =
WILL_FIRE_RL_mmio_sendInstResp ||
WILL_FIRE_RL_mmio_sendDataResp ;
assign mmio_pRqQ_enqReq_lat_0$wget =
{ 1'd1,
mmioToPlatform_pRq_enq_x[38],
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q281,
mmioToPlatform_pRq_enq_x[31:0] } ;
assign mmio_cRsQ_enqReq_lat_0$wget =
{ 1'd1, csrf_software_int_pend_vec_3 } ;
assign coreFix_globalSpecUpdate_correctSpecTag_0$whas =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
coreFix_aluExe_0_exeToFinQ$first[16] ;
assign coreFix_globalSpecUpdate_correctSpecTag_1$whas =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
coreFix_aluExe_1_exeToFinQ$first[16] ;
assign coreFix_aluExe_0_bypassWire_0$wget =
{ coreFix_aluExe_0_regToExeQ$first[348:342],
basicExec___d12779[321:258] } ;
assign coreFix_aluExe_0_bypassWire_0$whas =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
coreFix_aluExe_0_regToExeQ$first[349] ;
assign coreFix_aluExe_0_bypassWire_1$wget =
{ coreFix_aluExe_1_regToExeQ$first[348:342],
basicExec___d12105[321:258] } ;
assign coreFix_aluExe_0_bypassWire_1$whas =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
coreFix_aluExe_1_regToExeQ$first[349] ;
assign coreFix_aluExe_0_bypassWire_2$wget =
{ coreFix_aluExe_0_exeToFinQ$first[320:314],
coreFix_aluExe_0_exeToFinQ$first[275:212] } ;
assign coreFix_aluExe_0_bypassWire_2$whas =
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_aluExe_0_bypassWire_3$wget =
{ coreFix_aluExe_1_exeToFinQ$first[320:314],
coreFix_aluExe_1_exeToFinQ$first[275:212] } ;
assign coreFix_aluExe_0_bypassWire_3$whas =
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_aluExe_1_bypassWire_2$whas =
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_aluExe_1_bypassWire_3$whas =
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2$whas =
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_fpuMulDivExe_0_bypassWire_3$whas =
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] != 2'd1 ;
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225])
2'd0, 2'd1:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget =
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225];
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget = 2'd2;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
assign coreFix_memExe_bypassWire_2$whas =
_dor1coreFix_memExe_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_memExe_bypassWire_3$whas =
_dor1coreFix_memExe_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_memExe_issueLd$wget =
{ coreFix_memExe_dTlb$procResp[89:85],
coreFix_memExe_dTlb$procResp[174:111],
coreFix_memExe_dTlb$procResp[84:77] } ;
assign coreFix_memExe_issueLd$whas =
WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
coreFix_memExe_dTlb_procResp__741_BITS_105_TO__ETC___d1895 ;
assign coreFix_memExe_reqLdQ_data_0_lat_0$wget =
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 ?
coreFix_memExe_issueLd$wget[76:8] :
coreFix_memExe_lsq$getIssueLd[76:8] ;
assign coreFix_memExe_reqLdQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLdQ_empty_lat_0$whas =
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLdQ_full_lat_0$whas =
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ?
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
assign coreFix_memExe_reqStQ_data_0_lat_0$wget =
{ coreFix_memExe_stb$issue[635:576], 6'd0 } ;
assign coreFix_memExe_forwardQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ?
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_forwardQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ||
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 ;
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 ;
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
MUX_coreFix_memExe_lsq$getHit_1__SEL_2 ;
always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
default: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
assign coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
always@(WILL_FIRE_RL_coreFix_memExe_sendLdToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_sendStToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_sendLdToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1;
WILL_FIRE_RL_coreFix_memExe_sendStToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3;
default: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[147:84],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[54:53],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[83:82],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[57:55] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget =
{ 1'd1, dCacheToParent_fromP_enq_x } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2678 ;
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
59'h2AAAAAAAAAAAAAA;
default: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
59'h2AAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
assign coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// register commitStage_commitTrap
assign commitStage_commitTrap$D_IN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ?
134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_commitStage_commitTrap$write_1__VAL_2 ;
assign commitStage_commitTrap$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
// register commitStage_rg_just_after_reset
assign commitStage_rg_just_after_reset$D_IN = 1'd0 ;
assign commitStage_rg_just_after_reset$EN =
CAN_FIRE_RL_commitStage_rl_send_tv_reset ;
// register commitStage_rg_run_state
assign commitStage_rg_run_state$D_IN =
MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign commitStage_rg_run_state$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
WILL_FIRE_RL_rl_debug_resume ;
// register commitStage_rg_serial_num
always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
MUX_commitStage_rg_serial_num$write_1__VAL_1 or
WILL_FIRE_RL_commitStage_doCommitSystemInst or
WILL_FIRE_RL_commitStage_doCommitNormalInst or
MUX_commitStage_rg_serial_num$write_1__VAL_3 or
WILL_FIRE_RL_commitStage_rl_send_tv_reset)
begin
case (1'b1) // synopsys parallel_case
MUX_commitStage_rg_serial_num$write_1__SEL_1:
commitStage_rg_serial_num$D_IN =
MUX_commitStage_rg_serial_num$write_1__VAL_1;
WILL_FIRE_RL_commitStage_doCommitSystemInst:
commitStage_rg_serial_num$D_IN =
MUX_commitStage_rg_serial_num$write_1__VAL_1;
WILL_FIRE_RL_commitStage_doCommitNormalInst:
commitStage_rg_serial_num$D_IN =
MUX_commitStage_rg_serial_num$write_1__VAL_3;
WILL_FIRE_RL_commitStage_rl_send_tv_reset:
commitStage_rg_serial_num$D_IN = 64'd1;
default: commitStage_rg_serial_num$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign commitStage_rg_serial_num$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
WILL_FIRE_RL_commitStage_doCommitNormalInst ||
WILL_FIRE_RL_commitStage_rl_send_tv_reset ;
// register coreFix_doStatsReg
assign coreFix_doStatsReg$D_IN = 1'b0 ;
assign coreFix_doStatsReg$EN = 1'b0 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt + 4'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN = 1'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt == 4'd15 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$D_IN = 1'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ?
v__h608281 :
v__h607240 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11201[127:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11188[127:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11194[127:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN =
1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd2 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd4 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd5 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd6 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd7 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
3'd0 :
_theResult_____2__h299047 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN =
1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3155 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3175 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
3'd0 :
v__h298467 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN =
4'b0010 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3155 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3164 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN =
{ !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3277 ||
(EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]),
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3344 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3224 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3235 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3224 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3235 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3224 &&
_theResult_____2__h307043 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3257 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3280 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3224 &&
v__h301812 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN =
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3224 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3257 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3267 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3101,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3109 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas &&
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3395 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3406 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3395 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3406 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3395 &&
_theResult_____2__h313037 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3429 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3452 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3395 &&
v__h312326 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN =
73'h0AAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3395 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3429 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3438 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN =
{ x_addr__h316600,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513],
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3544 ||
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[512] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[512]),
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3491 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3502 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3491 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3502 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3491 &&
_theResult_____2__h320891 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3525 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3548 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3491 &&
v__h316202 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN =
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3491 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3525 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3534 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_data_0
assign coreFix_memExe_dMem_perfReqQ_data_0$D_IN =
coreFix_memExe_dMem_perfReqQ_enqReq_rl[3:0] ;
assign coreFix_memExe_dMem_perfReqQ_data_0$EN =
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1909 &&
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ;
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_empty
assign coreFix_memExe_dMem_perfReqQ_empty$D_IN =
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_clearReq_rl ||
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1953 ;
assign coreFix_memExe_dMem_perfReqQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_full
assign coreFix_memExe_dMem_perfReqQ_full$D_IN =
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1909 &&
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1937 ;
assign coreFix_memExe_dMem_perfReqQ_full$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_clearReq_rl
assign coreFix_memExe_forwardQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_forwardQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_data_0
assign coreFix_memExe_forwardQ_data_0$D_IN =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
assign coreFix_memExe_forwardQ_data_0$EN =
coreFix_memExe_forwardQ_enqP == 1'd0 &&
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3814 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3825 ;
// register coreFix_memExe_forwardQ_data_1
assign coreFix_memExe_forwardQ_data_1$D_IN =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
assign coreFix_memExe_forwardQ_data_1$EN =
coreFix_memExe_forwardQ_enqP == 1'd1 &&
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3814 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3825 ;
// register coreFix_memExe_forwardQ_deqP
assign coreFix_memExe_forwardQ_deqP$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3814 &&
_theResult_____2__h334460 ;
assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_deqReq_rl
assign coreFix_memExe_forwardQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_forwardQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_empty
assign coreFix_memExe_forwardQ_empty$D_IN =
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_forwardQ_clearReq_rl ||
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3847 &&
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3869 ;
assign coreFix_memExe_forwardQ_empty$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_enqP
assign coreFix_memExe_forwardQ_enqP$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3814 &&
v__h334028 ;
assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_enqReq_rl
assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_forwardQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_full
assign coreFix_memExe_forwardQ_full$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3814 &&
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3847 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3856 ;
assign coreFix_memExe_forwardQ_full$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_clearReq_rl
assign coreFix_memExe_memRespLdQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_memRespLdQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_data_0
assign coreFix_memExe_memRespLdQ_data_0$D_IN =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
assign coreFix_memExe_memRespLdQ_data_0$EN =
coreFix_memExe_memRespLdQ_enqP == 1'd0 &&
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3720 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3731 ;
// register coreFix_memExe_memRespLdQ_data_1
assign coreFix_memExe_memRespLdQ_data_1$D_IN =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
assign coreFix_memExe_memRespLdQ_data_1$EN =
coreFix_memExe_memRespLdQ_enqP == 1'd1 &&
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3720 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3731 ;
// register coreFix_memExe_memRespLdQ_deqP
assign coreFix_memExe_memRespLdQ_deqP$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3720 &&
_theResult_____2__h331235 ;
assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_deqReq_rl
assign coreFix_memExe_memRespLdQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_memRespLdQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_empty
assign coreFix_memExe_memRespLdQ_empty$D_IN =
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_memRespLdQ_clearReq_rl ||
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3753 &&
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3775 ;
assign coreFix_memExe_memRespLdQ_empty$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_enqP
assign coreFix_memExe_memRespLdQ_enqP$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3720 &&
v__h330803 ;
assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_enqReq_rl
assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_memRespLdQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_full
assign coreFix_memExe_memRespLdQ_full$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3720 &&
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3753 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3762 ;
assign coreFix_memExe_memRespLdQ_full$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_data_0_rl
assign coreFix_memExe_reqLdQ_data_0_rl$D_IN =
coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget :
coreFix_memExe_reqLdQ_data_0_rl ;
assign coreFix_memExe_reqLdQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_empty_rl
assign coreFix_memExe_reqLdQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
!coreFix_memExe_reqLdQ_empty_lat_0$whas &&
coreFix_memExe_reqLdQ_empty_rl ;
assign coreFix_memExe_reqLdQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_full_rl
assign coreFix_memExe_reqLdQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
(coreFix_memExe_reqLdQ_full_lat_0$whas ||
coreFix_memExe_reqLdQ_full_rl) ;
assign coreFix_memExe_reqLdQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN =
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget :
coreFix_memExe_reqLrScAmoQ_data_0_rl ;
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_empty_rl
assign coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
!coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas &&
coreFix_memExe_reqLrScAmoQ_empty_rl ;
assign coreFix_memExe_reqLrScAmoQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_full_rl
assign coreFix_memExe_reqLrScAmoQ_full_rl$D_IN =
!CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem &&
(coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
coreFix_memExe_reqLrScAmoQ_full_rl) ;
assign coreFix_memExe_reqLrScAmoQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_data_0_rl
assign coreFix_memExe_reqStQ_data_0_rl$D_IN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget :
coreFix_memExe_reqStQ_data_0_rl ;
assign coreFix_memExe_reqStQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_empty_rl
assign coreFix_memExe_reqStQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
!CAN_FIRE_RL_coreFix_memExe_doIssueSB &&
coreFix_memExe_reqStQ_empty_rl ;
assign coreFix_memExe_reqStQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_full_rl
assign coreFix_memExe_reqStQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_sendStToMem &&
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
coreFix_memExe_reqStQ_full_rl) ;
assign coreFix_memExe_reqStQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_data_0
assign coreFix_memExe_respLrScAmoQ_data_0$D_IN =
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[63:0] :
coreFix_memExe_respLrScAmoQ_enqReq_rl[63:0] ;
assign coreFix_memExe_respLrScAmoQ_data_0$EN =
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3644 &&
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3655 ;
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_empty
assign coreFix_memExe_respLrScAmoQ_empty$D_IN =
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_respLrScAmoQ_clearReq_rl ||
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3686 ;
assign coreFix_memExe_respLrScAmoQ_empty$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_full
assign coreFix_memExe_respLrScAmoQ_full$D_IN =
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3644 &&
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3671 ;
assign coreFix_memExe_respLrScAmoQ_full$EN = 1'd1 ;
// register coreFix_memExe_waitLrScAmoMMIOResp
always@(MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd0;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd4;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd2;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd6;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd7;
default: coreFix_memExe_waitLrScAmoMMIOResp$D_IN =
3'b010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_waitLrScAmoMMIOResp$EN =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
// register csrInstOrInterruptInflight_rl
assign csrInstOrInterruptInflight_rl$D_IN =
csrInstOrInterruptInflight_lat_1$whas ?
1'd1 :
(MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 ?
1'd0 :
csrInstOrInterruptInflight_rl) ;
assign csrInstOrInterruptInflight_rl$EN = 1'd1 ;
// register csrf_external_int_en_vec_0
assign csrf_external_int_en_vec_0$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[8] :
f_csr_reqs$D_OUT[8] ;
assign csrf_external_int_en_vec_0$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_external_int_en_vec_1
assign csrf_external_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[9] :
f_csr_reqs$D_OUT[9] ;
assign csrf_external_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_external_int_en_vec_3
assign csrf_external_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[11] :
MUX_csrf_stval_csr$write_1__VAL_1[11] ;
assign csrf_external_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd22 ;
// register csrf_external_int_pend_vec_0
assign csrf_external_int_pend_vec_0$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[8] :
f_csr_reqs$D_OUT[8] ;
assign csrf_external_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_external_int_pend_vec_1
always@(MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_external_int_pend_vec_0$write_1__SEL_2 or
f_csr_reqs$D_OUT or EN_setSEIP or setSEIP_v)
case (1'b1)
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1:
csrf_external_int_pend_vec_1$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[9];
MUX_csrf_external_int_pend_vec_0$write_1__SEL_2:
csrf_external_int_pend_vec_1$D_IN = f_csr_reqs$D_OUT[9];
EN_setSEIP: csrf_external_int_pend_vec_1$D_IN = setSEIP_v;
default: csrf_external_int_pend_vec_1$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_external_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ||
EN_setSEIP ;
// register csrf_external_int_pend_vec_3
always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or
f_csr_reqs$D_OUT or EN_setMEIP or setMEIP_v)
case (1'b1)
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1:
csrf_external_int_pend_vec_3$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[11];
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2:
csrf_external_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[11];
EN_setMEIP: csrf_external_int_pend_vec_3$D_IN = setMEIP_v;
default: csrf_external_int_pend_vec_3$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_external_int_pend_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd29 ||
EN_setMEIP ;
// register csrf_fflags_reg
always@(MUX_csrf_fflags_reg$write_1__SEL_1 or
MUX_csrf_fflags_reg$write_1__VAL_1 or
MUX_csrf_fflags_reg$write_1__SEL_2 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_fflags_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_fflags_reg$write_1__SEL_1:
csrf_fflags_reg$D_IN = MUX_csrf_fflags_reg$write_1__VAL_1;
MUX_csrf_fflags_reg$write_1__SEL_2:
csrf_fflags_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0];
MUX_csrf_fflags_reg$write_1__SEL_3:
csrf_fflags_reg$D_IN = f_csr_reqs$D_OUT[4:0];
default: csrf_fflags_reg$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign csrf_fflags_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd2) ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__5509_5510_OR__ETC___d15835 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
// register csrf_frm_reg
assign csrf_frm_reg$D_IN =
MUX_csrf_frm_reg$write_1__SEL_1 ?
MUX_csrf_frm_reg$write_1__VAL_1 :
MUX_csrf_frm_reg$write_1__VAL_2 ;
assign csrf_frm_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd2) ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
// register csrf_fs_reg
always@(MUX_csrf_fflags_reg$write_1__SEL_1 or
MUX_csrf_fs_reg$write_1__SEL_2 or
MUX_csrf_fs_reg$write_1__VAL_2 or
MUX_csrf_fs_reg$write_1__SEL_3 or MUX_csrf_fs_reg$write_1__VAL_3)
case (1'b1)
MUX_csrf_fflags_reg$write_1__SEL_1: csrf_fs_reg$D_IN = 2'b11;
MUX_csrf_fs_reg$write_1__SEL_2:
csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_2;
MUX_csrf_fs_reg$write_1__SEL_3:
csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_3;
default: csrf_fs_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_fs_reg$EN =
MUX_csrf_fs_reg$write_1__SEL_2 ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__5509_5510_OR__ETC___d15835 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3 ||
f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_0
assign csrf_ie_vec_0$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[0] :
f_csr_reqs$D_OUT[0] ;
assign csrf_ie_vec_0$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_1
always@(MUX_csrf_ie_vec_1$write_1__SEL_1 or
MUX_csrf_ie_vec_1$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_ie_vec_1$write_1__SEL_1:
csrf_ie_vec_1$D_IN = MUX_csrf_ie_vec_1$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_ie_vec_1$D_IN = 1'd0;
MUX_csrf_ie_vec_0$write_1__SEL_2:
csrf_ie_vec_1$D_IN = f_csr_reqs$D_OUT[1];
default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_ie_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_3
always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or
MUX_csrf_ie_vec_3$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_ie_vec_3$write_1__SEL_1:
csrf_ie_vec_3$D_IN = MUX_csrf_ie_vec_3$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_ie_vec_3$D_IN = 1'd0;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_ie_vec_3$D_IN = f_csr_reqs$D_OUT[3];
default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_ie_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 ;
// register csrf_mcause_code_reg
always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
cause_code__h708328 or
MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mcause_code_reg$write_1__SEL_1:
csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mcause_code_reg$D_IN = cause_code__h708328;
MUX_csrf_mcause_code_reg$write_1__SEL_3:
csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0];
default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign csrf_mcause_code_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd27 ;
// register csrf_mcause_interrupt_reg
always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mcause_code_reg$write_1__SEL_1:
csrf_mcause_interrupt_reg$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[63];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mcause_interrupt_reg$D_IN = commitStage_commitTrap[4];
MUX_csrf_mcause_code_reg$write_1__SEL_3:
csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63];
default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_mcause_interrupt_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd27 ;
// register csrf_mcounteren_cy_reg
assign csrf_mcounteren_cy_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_mcounteren_cy_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd24 ;
// register csrf_mcounteren_ir_reg
assign csrf_mcounteren_ir_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[2] :
MUX_csrf_stval_csr$write_1__VAL_1[2] ;
assign csrf_mcounteren_ir_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd24 ;
// register csrf_mcounteren_tm_reg
assign csrf_mcounteren_tm_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1] :
MUX_csrf_stval_csr$write_1__VAL_1[1] ;
assign csrf_mcounteren_tm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd24 ;
// register csrf_mcycle_ehr_data_rl
assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5311 ;
assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ;
// register csrf_medeleg_13_11_reg
assign csrf_medeleg_13_11_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[13:11] :
MUX_csrf_stval_csr$write_1__VAL_1[13:11] ;
assign csrf_medeleg_13_11_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd20 ;
// register csrf_medeleg_15_reg
assign csrf_medeleg_15_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[15] :
MUX_csrf_stval_csr$write_1__VAL_1[15] ;
assign csrf_medeleg_15_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd20 ;
// register csrf_medeleg_9_0_reg
assign csrf_medeleg_9_0_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[9:0] :
MUX_csrf_stval_csr$write_1__VAL_1[9:0] ;
assign csrf_medeleg_9_0_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd20 ;
// register csrf_mepc_csr
always@(MUX_csrf_mepc_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_mepc_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mepc_csr$write_1__SEL_1:
csrf_mepc_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mepc_csr$D_IN = commitStage_commitTrap[132:69];
MUX_csrf_mepc_csr$write_1__SEL_3:
csrf_mepc_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_mepc_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_mepc_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd833 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd26 ;
// register csrf_mideleg_11_reg
assign csrf_mideleg_11_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[11] :
MUX_csrf_stval_csr$write_1__VAL_1[11] ;
assign csrf_mideleg_11_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd21 ;
// register csrf_mideleg_1_0_reg
assign csrf_mideleg_1_0_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1:0] :
MUX_csrf_stval_csr$write_1__VAL_1[1:0] ;
assign csrf_mideleg_1_0_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd21 ;
// register csrf_mideleg_5_3_reg
assign csrf_mideleg_5_3_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[5:3] :
MUX_csrf_stval_csr$write_1__VAL_1[5:3] ;
assign csrf_mideleg_5_3_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd21 ;
// register csrf_mideleg_9_7_reg
assign csrf_mideleg_9_7_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[9:7] :
MUX_csrf_stval_csr$write_1__VAL_1[9:7] ;
assign csrf_mideleg_9_7_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd21 ;
// register csrf_minstret_ehr_data_rl
assign csrf_minstret_ehr_data_rl$D_IN =
csrf_minstret_ehr_data_lat_1$whas ?
upd__h3994 :
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ;
assign csrf_minstret_ehr_data_rl$EN = 1'd1 ;
// register csrf_mpp_reg
always@(MUX_csrf_mpp_reg$write_1__SEL_1 or
MUX_csrf_mpp_reg$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
csrf_prv_reg or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mpp_reg$write_1__SEL_1:
csrf_mpp_reg$D_IN = MUX_csrf_mpp_reg$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mpp_reg$D_IN = csrf_prv_reg;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_mpp_reg$D_IN = f_csr_reqs$D_OUT[12:11];
default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_mpp_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 ;
// register csrf_mprv_reg
assign csrf_mprv_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[17] :
MUX_csrf_stval_csr$write_1__VAL_1[17] ;
assign csrf_mprv_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18 ;
// register csrf_mscratch_csr
assign csrf_mscratch_csr$D_IN =
MUX_csrf_mscratch_csr$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_mscratch_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd832 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd25 ;
// register csrf_mtval_csr
always@(MUX_csrf_mtval_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
MUX_csrf_mtval_csr$write_1__VAL_2 or
MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mtval_csr$write_1__SEL_1:
csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mtval_csr$D_IN = MUX_csrf_mtval_csr$write_1__VAL_2;
MUX_csrf_mtval_csr$write_1__SEL_3:
csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_mtval_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_mtval_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd835 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd28 ;
// register csrf_mtvec_base_hi_reg
assign csrf_mtvec_base_hi_reg$D_IN =
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:2] :
MUX_csrf_stval_csr$write_1__VAL_1[63:2] ;
assign csrf_mtvec_base_hi_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd23 ;
// register csrf_mtvec_mode_low_reg
assign csrf_mtvec_mode_low_reg$D_IN =
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_mtvec_mode_low_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd23 ;
// register csrf_mxr_reg
assign csrf_mxr_reg$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[19] :
f_csr_reqs$D_OUT[19] ;
assign csrf_mxr_reg$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ppn_reg
assign csrf_ppn_reg$D_IN =
MUX_csrf_ppn_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[43:0] :
MUX_csrf_stval_csr$write_1__VAL_1[43:0] ;
assign csrf_ppn_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd17 ;
// register csrf_prev_ie_vec_0
assign csrf_prev_ie_vec_0$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[4] :
f_csr_reqs$D_OUT[4] ;
assign csrf_prev_ie_vec_0$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_prev_ie_vec_1
always@(MUX_csrf_prev_ie_vec_1$write_1__SEL_1 or
MUX_csrf_prev_ie_vec_1$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
csrf_ie_vec_1 or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prev_ie_vec_1$write_1__SEL_1:
csrf_prev_ie_vec_1$D_IN = MUX_csrf_prev_ie_vec_1$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_prev_ie_vec_1$D_IN = csrf_ie_vec_1;
MUX_csrf_ie_vec_0$write_1__SEL_2:
csrf_prev_ie_vec_1$D_IN = f_csr_reqs$D_OUT[5];
default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_prev_ie_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_prev_ie_vec_3
always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or
MUX_csrf_prev_ie_vec_3$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
csrf_ie_vec_3 or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prev_ie_vec_3$write_1__SEL_1:
csrf_prev_ie_vec_3$D_IN = MUX_csrf_prev_ie_vec_3$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_prev_ie_vec_3$D_IN = csrf_ie_vec_3;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_prev_ie_vec_3$D_IN = f_csr_reqs$D_OUT[7];
default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_prev_ie_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 ;
// register csrf_prv_reg
always@(MUX_csrf_prv_reg$write_1__SEL_1 or
MUX_csrf_prv_reg$write_1__VAL_1 or
MUX_commitStage_rg_serial_num$write_1__SEL_1 or
x_prv__h711252 or
MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prv_reg$write_1__SEL_1:
csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1;
MUX_commitStage_rg_serial_num$write_1__SEL_1:
csrf_prv_reg$D_IN = x_prv__h711252;
MUX_csrf_prv_reg$write_1__SEL_3:
csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0];
default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_prv_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ;
// register csrf_rg_dcsr
always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_commitStage_rg_run_state$write_1__SEL_1 or
MUX_csrf_rg_dcsr$write_1__VAL_2 or
MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_rg_dcsr$write_1__SEL_1:
csrf_rg_dcsr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_commitStage_rg_run_state$write_1__SEL_1:
csrf_rg_dcsr$D_IN = MUX_csrf_rg_dcsr$write_1__VAL_2;
MUX_csrf_prv_reg$write_1__SEL_3:
csrf_rg_dcsr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_rg_dcsr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_rg_dcsr$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd36 ;
// register csrf_rg_dpc
always@(MUX_csrf_rg_dpc$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_commitStage_rg_run_state$write_1__SEL_1 or
commitStage_commitTrap or
MUX_csrf_rg_dpc$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_rg_dpc$write_1__SEL_1:
csrf_rg_dpc$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_commitStage_rg_run_state$write_1__SEL_1:
csrf_rg_dpc$D_IN = commitStage_commitTrap[132:69];
MUX_csrf_rg_dpc$write_1__SEL_3: csrf_rg_dpc$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_rg_dpc$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_rg_dpc$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1969 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd37 ;
// register csrf_rg_dscratch0
assign csrf_rg_dscratch0$D_IN =
MUX_csrf_rg_dscratch0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_dscratch0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1970 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd38 ;
// register csrf_rg_dscratch1
assign csrf_rg_dscratch1$D_IN =
MUX_csrf_rg_dscratch1$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_dscratch1$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1971 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd39 ;
// register csrf_scause_code_reg
always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
cause_code__h708328 or
MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_scause_code_reg$write_1__SEL_1:
csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_scause_code_reg$D_IN = cause_code__h708328;
MUX_csrf_scause_code_reg$write_1__SEL_3:
csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0];
default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign csrf_scause_code_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd14 ;
// register csrf_scause_interrupt_reg
always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_scause_code_reg$write_1__SEL_1:
csrf_scause_interrupt_reg$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[63];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_scause_interrupt_reg$D_IN = commitStage_commitTrap[4];
MUX_csrf_scause_code_reg$write_1__SEL_3:
csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63];
default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_scause_interrupt_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd14 ;
// register csrf_scounteren_cy_reg
assign csrf_scounteren_cy_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_scounteren_cy_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd11 ;
// register csrf_scounteren_ir_reg
assign csrf_scounteren_ir_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[2] :
MUX_csrf_stval_csr$write_1__VAL_1[2] ;
assign csrf_scounteren_ir_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd11 ;
// register csrf_scounteren_tm_reg
assign csrf_scounteren_tm_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1] :
MUX_csrf_stval_csr$write_1__VAL_1[1] ;
assign csrf_scounteren_tm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd11 ;
// register csrf_sepc_csr
always@(MUX_csrf_sepc_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_sepc_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_sepc_csr$write_1__SEL_1:
csrf_sepc_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_sepc_csr$D_IN = commitStage_commitTrap[132:69];
MUX_csrf_sepc_csr$write_1__SEL_3:
csrf_sepc_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_sepc_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_sepc_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd321 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd13 ;
// register csrf_software_int_en_vec_0
assign csrf_software_int_en_vec_0$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[0] :
f_csr_reqs$D_OUT[0] ;
assign csrf_software_int_en_vec_0$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_software_int_en_vec_1
assign csrf_software_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[1] :
f_csr_reqs$D_OUT[1] ;
assign csrf_software_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_software_int_en_vec_3
assign csrf_software_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[3] :
MUX_csrf_stval_csr$write_1__VAL_1[3] ;
assign csrf_software_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd22 ;
// register csrf_software_int_pend_vec_0
assign csrf_software_int_pend_vec_0$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[0] :
f_csr_reqs$D_OUT[0] ;
assign csrf_software_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_software_int_pend_vec_1
assign csrf_software_int_pend_vec_1$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[1] :
f_csr_reqs$D_OUT[1] ;
assign csrf_software_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_software_int_pend_vec_3
always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 or
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 or
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1:
csrf_software_int_pend_vec_3$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[3];
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2:
csrf_software_int_pend_vec_3$D_IN =
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2;
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2:
csrf_software_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[3];
default: csrf_software_int_pend_vec_3$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_software_int_pend_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ||
WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] != 2'd0 &&
mmio_pRqQ_data_0[37:36] != 2'd1 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd29 ;
// register csrf_spp_reg
always@(MUX_csrf_spp_reg$write_1__SEL_1 or
MUX_csrf_spp_reg$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
csrf_prv_reg or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_spp_reg$write_1__SEL_1:
csrf_spp_reg$D_IN = MUX_csrf_spp_reg$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_spp_reg$D_IN = csrf_prv_reg[0];
MUX_csrf_ie_vec_0$write_1__SEL_2: csrf_spp_reg$D_IN = f_csr_reqs$D_OUT[8];
default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_spp_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_sscratch_csr
assign csrf_sscratch_csr$D_IN =
MUX_csrf_sscratch_csr$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_sscratch_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd320 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd12 ;
// register csrf_stats_module_doStats
assign csrf_stats_module_doStats$D_IN = recvDoStats_x ;
assign csrf_stats_module_doStats$EN = EN_recvDoStats ;
// register csrf_stval_csr
always@(MUX_csrf_stval_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
MUX_csrf_mtval_csr$write_1__VAL_2 or
MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_stval_csr$write_1__SEL_1:
csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_stval_csr$D_IN = MUX_csrf_mtval_csr$write_1__VAL_2;
MUX_csrf_stval_csr$write_1__SEL_3:
csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_stval_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_stval_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd323 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 &&
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd15 ;
// register csrf_stvec_base_hi_reg
assign csrf_stvec_base_hi_reg$D_IN =
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:2] :
MUX_csrf_stval_csr$write_1__VAL_1[63:2] ;
assign csrf_stvec_base_hi_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd10 ;
// register csrf_stvec_mode_low_reg
assign csrf_stvec_mode_low_reg$D_IN =
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_stvec_mode_low_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd10 ;
// register csrf_sum_reg
assign csrf_sum_reg$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[18] :
f_csr_reqs$D_OUT[18] ;
assign csrf_sum_reg$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_time_reg
assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ;
assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ;
// register csrf_timer_int_en_vec_0
assign csrf_timer_int_en_vec_0$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[4] :
f_csr_reqs$D_OUT[4] ;
assign csrf_timer_int_en_vec_0$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_timer_int_en_vec_1
assign csrf_timer_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[5] :
f_csr_reqs$D_OUT[5] ;
assign csrf_timer_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_timer_int_en_vec_3
assign csrf_timer_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[7] :
MUX_csrf_stval_csr$write_1__VAL_1[7] ;
assign csrf_timer_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd22 ;
// register csrf_timer_int_pend_vec_0
assign csrf_timer_int_pend_vec_0$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[4] :
f_csr_reqs$D_OUT[4] ;
assign csrf_timer_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_timer_int_pend_vec_1
assign csrf_timer_int_pend_vec_1$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[5] :
f_csr_reqs$D_OUT[5] ;
assign csrf_timer_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_timer_int_pend_vec_3
assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ;
assign csrf_timer_int_pend_vec_3$EN =
WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] == 2'd2 ;
// register csrf_tsr_reg
assign csrf_tsr_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[22] :
MUX_csrf_stval_csr$write_1__VAL_1[22] ;
assign csrf_tsr_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18 ;
// register csrf_tvm_reg
assign csrf_tvm_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[20] :
MUX_csrf_stval_csr$write_1__VAL_1[20] ;
assign csrf_tvm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18 ;
// register csrf_tw_reg
assign csrf_tw_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[21] :
MUX_csrf_stval_csr$write_1__VAL_1[21] ;
assign csrf_tw_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18 ;
// register csrf_vm_mode_sv39_reg
assign csrf_vm_mode_sv39_reg$D_IN =
MUX_csrf_ppn_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63] :
MUX_csrf_stval_csr$write_1__VAL_1[63] ;
assign csrf_vm_mode_sv39_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd17 ;
// register flush_brpred
assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign flush_brpred$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
WILL_FIRE_RL_flushBrPred ;
// register flush_caches
assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign flush_caches$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
WILL_FIRE_RL_flushCaches ;
// register flush_reservation
assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ;
assign flush_reservation$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 ||
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
// register flush_tlbs
assign flush_tlbs$D_IN = !MUX_flush_tlbs$write_1__SEL_1 ;
assign flush_tlbs$EN =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
(rob$deqPort_0_deq_data[257:253] == 5'd16 ||
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd17) ;
// register mmio_cRqQ_clearReq_rl
assign mmio_cRqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_cRqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_data_0
assign mmio_cRqQ_data_0$D_IN =
{ x__h46122,
(mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ?
{ 5'd2,
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[72] :
mmio_cRqQ_enqReq_rl[72] } :
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[71:64] :
mmio_cRqQ_enqReq_rl[71:64],
x__h48658 } ;
assign mmio_cRqQ_data_0$EN =
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ;
// register mmio_cRqQ_deqReq_rl
assign mmio_cRqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_cRqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_empty
assign mmio_cRqQ_empty$D_IN =
mmio_cRqQ_clearReq_dummy2_1$Q_OUT && mmio_cRqQ_clearReq_rl ||
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 ;
assign mmio_cRqQ_empty$EN = 1'd1 ;
// register mmio_cRqQ_enqReq_rl
assign mmio_cRqQ_enqReq_rl$D_IN =
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign mmio_cRqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_full
assign mmio_cRqQ_full$D_IN =
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 ;
assign mmio_cRqQ_full$EN = 1'd1 ;
// register mmio_cRsQ_clearReq_rl
assign mmio_cRsQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_cRsQ_clearReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_data_0
assign mmio_cRsQ_data_0$D_IN =
CAN_FIRE_RL_mmio_handlePRq ?
mmio_cRsQ_enqReq_lat_0$wget[0] :
mmio_cRsQ_enqReq_rl[0] ;
assign mmio_cRsQ_data_0$EN =
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ;
// register mmio_cRsQ_deqReq_rl
assign mmio_cRsQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_cRsQ_deqReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_empty
assign mmio_cRsQ_empty$D_IN =
mmio_cRsQ_clearReq_dummy2_1$Q_OUT && mmio_cRsQ_clearReq_rl ||
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 ;
assign mmio_cRsQ_empty$EN = 1'd1 ;
// register mmio_cRsQ_enqReq_rl
assign mmio_cRsQ_enqReq_rl$D_IN = 2'b0 ;
assign mmio_cRsQ_enqReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_full
assign mmio_cRsQ_full$D_IN =
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 ;
assign mmio_cRsQ_full$EN = 1'd1 ;
// register mmio_dataPendQ_clearReq_rl
assign mmio_dataPendQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_deqReq_rl
assign mmio_dataPendQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_empty
assign mmio_dataPendQ_empty$D_IN =
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataPendQ_clearReq_rl ||
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 ;
assign mmio_dataPendQ_empty$EN = 1'd1 ;
// register mmio_dataPendQ_enqReq_rl
assign mmio_dataPendQ_enqReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_full
assign mmio_dataPendQ_full$D_IN =
(!mmio_dataPendQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataPendQ_clearReq_rl) &&
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 ;
assign mmio_dataPendQ_full$EN = 1'd1 ;
// register mmio_dataReqQ_clearReq_rl
assign mmio_dataReqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataReqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_data_0
assign mmio_dataReqQ_data_0$D_IN =
{ x__h18215,
(mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ?
{ 5'd2,
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[72] :
mmio_dataReqQ_enqReq_rl[72] } :
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[71:64] :
mmio_dataReqQ_enqReq_rl[71:64],
x__h20753 } ;
assign mmio_dataReqQ_data_0$EN =
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ;
// register mmio_dataReqQ_deqReq_rl
assign mmio_dataReqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataReqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_empty
assign mmio_dataReqQ_empty$D_IN =
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataReqQ_clearReq_rl ||
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 ;
assign mmio_dataReqQ_empty$EN = 1'd1 ;
// register mmio_dataReqQ_enqReq_rl
assign mmio_dataReqQ_enqReq_rl$D_IN =
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign mmio_dataReqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_full
assign mmio_dataReqQ_full$D_IN =
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 ;
assign mmio_dataReqQ_full$EN = 1'd1 ;
// register mmio_dataRespQ_clearReq_rl
assign mmio_dataRespQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataRespQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_data_0
assign mmio_dataRespQ_data_0$D_IN =
CAN_FIRE_RL_mmio_sendDataResp ?
mmio_dataRespQ_enqReq_lat_0$wget[64:0] :
mmio_dataRespQ_enqReq_rl[64:0] ;
assign mmio_dataRespQ_data_0$EN =
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ;
// register mmio_dataRespQ_deqReq_rl
assign mmio_dataRespQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataRespQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_empty
assign mmio_dataRespQ_empty$D_IN =
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataRespQ_clearReq_rl ||
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 ;
assign mmio_dataRespQ_empty$EN = 1'd1 ;
// register mmio_dataRespQ_enqReq_rl
assign mmio_dataRespQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
assign mmio_dataRespQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_full
assign mmio_dataRespQ_full$D_IN =
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 ;
assign mmio_dataRespQ_full$EN = 1'd1 ;
// register mmio_fromHostAddr
assign mmio_fromHostAddr$D_IN = coreReq_start_fromHostAddr[63:3] ;
assign mmio_fromHostAddr$EN = EN_coreReq_start ;
// register mmio_pRqQ_clearReq_rl
assign mmio_pRqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_pRqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_data_0
assign mmio_pRqQ_data_0$D_IN =
{ EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[38] :
mmio_pRqQ_enqReq_rl[38],
(EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd0 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd0) ?
{ 5'd2,
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[32] :
mmio_pRqQ_enqReq_rl[32] } :
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
x_data__h65916 } ;
assign mmio_pRqQ_data_0$EN =
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ;
// register mmio_pRqQ_deqReq_rl
assign mmio_pRqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_pRqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_empty
assign mmio_pRqQ_empty$D_IN =
mmio_pRqQ_clearReq_dummy2_1$Q_OUT && mmio_pRqQ_clearReq_rl ||
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 ;
assign mmio_pRqQ_empty$EN = 1'd1 ;
// register mmio_pRqQ_enqReq_rl
assign mmio_pRqQ_enqReq_rl$D_IN = 40'h2AAAAAAAAA ;
assign mmio_pRqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_full
assign mmio_pRqQ_full$D_IN =
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 ;
assign mmio_pRqQ_full$EN = 1'd1 ;
// register mmio_pRsQ_clearReq_rl
assign mmio_pRsQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_pRsQ_clearReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_data_0
assign mmio_pRsQ_data_0$D_IN =
{ EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[66] :
mmio_pRsQ_enqReq_rl[66],
IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 } ;
assign mmio_pRsQ_data_0$EN =
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ;
// register mmio_pRsQ_deqReq_rl
assign mmio_pRsQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_pRsQ_deqReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_empty
assign mmio_pRsQ_empty$D_IN =
mmio_pRsQ_clearReq_dummy2_1$Q_OUT && mmio_pRsQ_clearReq_rl ||
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 ;
assign mmio_pRsQ_empty$EN = 1'd1 ;
// register mmio_pRsQ_enqReq_rl
assign mmio_pRsQ_enqReq_rl$D_IN = 68'h2AAAAAAAAAAAAAAAA ;
assign mmio_pRsQ_enqReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_full
assign mmio_pRsQ_full$D_IN =
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 ;
assign mmio_pRsQ_full$EN = 1'd1 ;
// register mmio_toHostAddr
assign mmio_toHostAddr$D_IN = coreReq_start_toHostAddr[63:3] ;
assign mmio_toHostAddr$EN = EN_coreReq_start ;
// register outOfReset
assign outOfReset$D_IN = 1'd1 ;
assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ;
// register renameStage_rg_m_halt_req
always@(WILL_FIRE_RL_rl_debug_resume or
WILL_FIRE_RL_rl_debug_halt_req or
MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or
MUX_renameStage_rg_m_halt_req$write_1__SEL_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10;
WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30;
MUX_renameStage_rg_m_halt_req$write_1__SEL_1 ||
MUX_renameStage_rg_m_halt_req$write_1__SEL_2:
renameStage_rg_m_halt_req$D_IN = 5'd31;
default: renameStage_rg_m_halt_req$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign renameStage_rg_m_halt_req$EN =
(WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap) &&
csrf_rg_dcsr[2] ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
csrf_rg_dcsr[2] ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_rl_debug_halt_req ;
// register rg_core_run_state
always@(WILL_FIRE_RL_rl_debug_resume or
WILL_FIRE_RL_rl_debug_halted or
EN_coreReq_start or MUX_rg_core_run_state$write_1__SEL_4)
case (1'b1)
WILL_FIRE_RL_rl_debug_resume: rg_core_run_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_debug_halted: rg_core_run_state$D_IN = 2'd1;
EN_coreReq_start: rg_core_run_state$D_IN = 2'd2;
MUX_rg_core_run_state$write_1__SEL_4: rg_core_run_state$D_IN = 2'd0;
default: rg_core_run_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_core_run_state$EN =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ||
WILL_FIRE_RL_rl_debug_halted ||
WILL_FIRE_RL_rl_debug_resume ||
EN_coreReq_start ;
// register started
assign started$D_IN = WILL_FIRE_RL_rl_debug_resume || EN_coreReq_start ;
assign started$EN =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ||
WILL_FIRE_RL_rl_debug_resume ||
EN_coreReq_start ;
// register update_vm_info
assign update_vm_info$D_IN =
!MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ;
assign update_vm_info$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 ||
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
// submodule commitStage_f_rob_data
assign commitStage_f_rob_data$D_IN =
{ rob$deqPort_0_deq_data[353:182],
rob_deqPort_0_deq_data__4560_BIT_181_4634_CONC_ETC___d14717,
rob$deqPort_0_deq_data[168:167],
rob_deqPort_0_deq_data__4560_BIT_166_4576_CONC_ETC___d14625,
rob$deqPort_0_deq_data[161:98],
IF_rob_deqPort_0_deq_data__4560_BITS_97_TO_96__ETC___d14724,
rob$deqPort_0_deq_data[31:0] } ;
assign commitStage_f_rob_data$ENQ =
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign commitStage_f_rob_data$DEQ =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
assign commitStage_f_rob_data$CLR = 1'b0 ;
// submodule coreFix_aluExe_0_dispToRegQ
assign coreFix_aluExe_0_dispToRegQ$enq_x =
{ coreFix_aluExe_0_rsAlu$dispatchData[161:157],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283,
coreFix_aluExe_0_rsAlu$dispatchData[135],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q284,
coreFix_aluExe_0_rsAlu$dispatchData[122:90],
coreFix_aluExe_0_rsAlu$dispatchData[65:21],
coreFix_aluExe_0_rsAlu$dispatchData[89:66],
coreFix_aluExe_0_rsAlu$dispatchData[8:4],
coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ;
assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
assign coreFix_aluExe_0_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_exeToFinQ
assign coreFix_aluExe_0_exeToFinQ$enq_x =
{ coreFix_aluExe_0_regToExeQ$first[421:417],
coreFix_aluExe_0_regToExeQ$first[349:305],
coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11,
basicExec___d12779[321:258],
coreFix_aluExe_0_regToExeQ$first[395],
basicExec___d12779[257:194],
basicExec___d12779[129:0],
coreFix_aluExe_0_regToExeQ$first[16:0] } ;
assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_exeToFinQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
assign coreFix_aluExe_0_exeToFinQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_regToExeQ
assign coreFix_aluExe_0_regToExeQ$enq_x =
{ coreFix_aluExe_0_dispToRegQ$first[157:153],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q286,
coreFix_aluExe_0_dispToRegQ$first[131],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q287,
coreFix_aluExe_0_dispToRegQ$first[118:86],
coreFix_aluExe_0_dispToRegQ$first[61:17],
x__h643562,
x__h643563,
rob$getOrigPC_0_get,
rob$getOrigPredPC_0_get,
rob$getOrig_Inst_0_get,
coreFix_aluExe_0_dispToRegQ$first[16:0] } ;
assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
assign coreFix_aluExe_0_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_rsAlu
assign coreFix_aluExe_0_rsAlu$enq_x =
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 ?
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 :
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 ;
assign coreFix_aluExe_0_rsAlu$setRegReady_0_put =
{ 1'd1, coreFix_aluExe_0_rsAlu$dispatchData[40:34] } ;
assign coreFix_aluExe_0_rsAlu$setRegReady_1_put =
{ 1'd1, coreFix_aluExe_1_rsAlu$dispatchData[40:34] } ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_aluExe_0_rsAlu$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$setRegReady_3_put =
{ 1'd1, coreFix_memExe_lsq$issueLd[71:65] } ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
default: coreFix_aluExe_0_rsAlu$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[194:192] == 3'd0 ;
assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ;
assign coreFix_aluExe_0_rsAlu$EN_doDispatch =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_dispToRegQ
assign coreFix_aluExe_1_dispToRegQ$enq_x =
{ coreFix_aluExe_1_rsAlu$dispatchData[161:157],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289,
coreFix_aluExe_1_rsAlu$dispatchData[135],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q290,
coreFix_aluExe_1_rsAlu$dispatchData[122:90],
coreFix_aluExe_1_rsAlu$dispatchData[65:21],
coreFix_aluExe_1_rsAlu$dispatchData[89:66],
coreFix_aluExe_1_rsAlu$dispatchData[8:4],
coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ;
assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
assign coreFix_aluExe_1_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_exeToFinQ
assign coreFix_aluExe_1_exeToFinQ$enq_x =
{ coreFix_aluExe_1_regToExeQ$first[421:417],
coreFix_aluExe_1_regToExeQ$first[349:305],
coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11,
basicExec___d12105[321:258],
coreFix_aluExe_1_regToExeQ$first[395],
basicExec___d12105[257:194],
basicExec___d12105[129:0],
coreFix_aluExe_1_regToExeQ$first[16:0] } ;
assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_exeToFinQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
assign coreFix_aluExe_1_exeToFinQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_regToExeQ
assign coreFix_aluExe_1_regToExeQ$enq_x =
{ coreFix_aluExe_1_dispToRegQ$first[157:153],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q292,
coreFix_aluExe_1_dispToRegQ$first[131],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q293,
coreFix_aluExe_1_dispToRegQ$first[118:86],
coreFix_aluExe_1_dispToRegQ$first[61:17],
x__h621197,
x__h621198,
rob$getOrigPC_1_get,
rob$getOrigPredPC_1_get,
rob$getOrig_Inst_1_get,
coreFix_aluExe_1_dispToRegQ$first[16:0] } ;
assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
assign coreFix_aluExe_1_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_rsAlu
assign coreFix_aluExe_1_rsAlu$enq_x =
(k__h672122 == 1'd1 &&
fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14266) ?
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d13758,
fetchStage_pipelines_1_first__2941_BIT_173_375_ETC___d13842,
fetchStage$pipelines_1_first[160:128],
fetchStage$pipelines_1_first[255:232],
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h687315,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_aluExe_1_rsAlu$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_aluExe_1_rsAlu$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_aluExe_1_rsAlu$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
default: coreFix_aluExe_1_rsAlu$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo16 ;
assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ;
assign coreFix_aluExe_1_rsAlu$EN_doDispatch =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x =
{ CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q295,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829,
coreFix_fpuMulDivExe_0_regToExeQ$first[225],
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10966,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11002,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11050,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11092,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11134,
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28,
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9286,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10766,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10056,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q297,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9286,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x =
{ execFpuSimple___d11168,
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd25 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd26 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd27 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN =
{ x__h606558,
b__h606022 == 64'd0,
a__h606021,
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0,
x__h606584,
a__h606021[63],
8'd0 } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR =
1'b0 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
_theResult___snd__h606570 :
b__h606022 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR =
1'b0 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN =
{ x__h607170,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR = 1'b0 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1)
begin
case (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[1:0])
2'd0:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1[127:0];
2'd1:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1[127:0];
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1[127:0];
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[2] ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR = 1'b0 ;
// submodule coreFix_fpuMulDivExe_0_regToExeQ
assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x =
{ CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299,
coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12],
x__h484697,
x__h484698,
x__h484699,
coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14278) ?
{ IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061,
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d13758,
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h687315,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14278 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14440 &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r =
{ x__h289738,
x__h289750,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2883,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2887,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2891,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2895,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2899,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2904,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2908,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2913,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2917,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2922,
x__h291604,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2930,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2934,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2938,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2942 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n =
x__h288305 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd0) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] :
3'd0) ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
coreFix_memExe_dMem_cache_m_banks_0_processAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574];
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512];
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[159:157];
default: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
3'b010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:84] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 :
3'd3 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[57:55],
55'h15555555555555 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2628 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN =
EN_dCacheToParent_fromP_enq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2611 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2822 &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
2'd0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN =
MUX_flush_reservation$write_1__SEL_2 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2969,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n =
2'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d =
{ !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
coreFix_memExe_dMem_cache_m_banks_0_processAmo or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0];
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq = 4'd2;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
4'b1010 /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'd0;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'd1;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'b0 /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2680 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2684) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN =
EN_dCacheToParent_rqToP_deq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2731 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN =
EN_dCacheToParent_rsToP_deq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_dTlb
assign coreFix_memExe_dTlb$perf_req_r = 3'h0 ;
assign coreFix_memExe_dTlb$perf_setStatus_doStats = 1'b0 ;
assign coreFix_memExe_dTlb$procReq_req =
{ coreFix_memExe_regToExeQ$first[192:190],
coreFix_memExe_regToExeQ$first[157:140],
coreFix_memExe_lsq$getOrigBE << vaddr__h184286[2:0],
vaddr__h184286,
coreFix_memExe_lsq$getOrigBE[7] ?
vaddr__h184286[2:0] != 3'd0 :
(coreFix_memExe_lsq$getOrigBE[3] ?
vaddr__h184286[1:0] != 2'd0 :
coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184286[0]),
coreFix_memExe_regToExeQ$first[11:0] } ;
assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x =
{ l2Tlb$toChildren_rsToC_first[80:0],
l2Tlb$toChildren_rsToC_first[82:81] } ;
assign coreFix_memExe_dTlb$updateVMInfo_vm =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 :
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ;
assign coreFix_memExe_dTlb$EN_flush =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_rl_debug_resume ;
assign coreFix_memExe_dTlb$EN_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign coreFix_memExe_dTlb$EN_procReq =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
assign coreFix_memExe_dTlb$EN_deqProcResp =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign coreFix_memExe_dTlb$EN_toParent_rqToP_deq = CAN_FIRE_RL_sendDTlbReq ;
assign coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq =
CAN_FIRE_RL_sendRsToDTlb ;
assign coreFix_memExe_dTlb$EN_toParent_flush_request_get =
CAN_FIRE_RL_mkConnectionGetPut ;
assign coreFix_memExe_dTlb$EN_toParent_flush_response_put =
CAN_FIRE_RL_sendFlushDone ;
assign coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation = 1'd1 ;
assign coreFix_memExe_dTlb$EN_perf_setStatus = 1'b0 ;
assign coreFix_memExe_dTlb$EN_perf_req = 1'b0 ;
assign coreFix_memExe_dTlb$EN_perf_resp = 1'b0 ;
// submodule coreFix_memExe_dispToRegQ
assign coreFix_memExe_dispToRegQ$enq_x =
{ coreFix_memExe_rsMem$dispatchData[106:72],
coreFix_memExe_rsMem$dispatchData[65:21],
coreFix_memExe_rsMem$dispatchData[71:66],
coreFix_memExe_rsMem$dispatchData[20:9] } ;
assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
assign coreFix_memExe_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
assign coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$EN =
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_lsq
assign coreFix_memExe_lsq$enqLd_dst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14335) ?
regRenamingTable$rename_0_getRename[8:0] :
regRenamingTable$rename_1_getRename[8:0] ;
assign coreFix_memExe_lsq$enqLd_inst_tag =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14335) ?
rob$enqPort_0_getEnqInstTag :
rob$enqPort_1_getEnqInstTag ;
assign coreFix_memExe_lsq$enqLd_mem_inst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14335) ?
fetchStage$pipelines_0_first[191:174] :
fetchStage$pipelines_1_first[191:174] ;
assign coreFix_memExe_lsq$enqLd_spec_bits =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14335) ?
specTagManager$currentSpecBits :
renaming_spec_bits__h687315 ;
assign coreFix_memExe_lsq$enqSt_dst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14343) ?
regRenamingTable$rename_0_getRename[8:0] :
regRenamingTable$rename_1_getRename[8:0] ;
assign coreFix_memExe_lsq$enqSt_inst_tag =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14343) ?
rob$enqPort_0_getEnqInstTag :
rob$enqPort_1_getEnqInstTag ;
assign coreFix_memExe_lsq$enqSt_mem_inst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14343) ?
fetchStage$pipelines_0_first[191:174] :
fetchStage$pipelines_1_first[191:174] ;
assign coreFix_memExe_lsq$enqSt_spec_bits =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14343) ?
specTagManager$currentSpecBits :
renaming_spec_bits__h687315 ;
assign coreFix_memExe_lsq$getHit_t =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
MUX_coreFix_memExe_lsq$getHit_1__VAL_1 :
MUX_coreFix_memExe_lsq$getHit_1__VAL_1 ;
assign coreFix_memExe_lsq$getOrigBE_t =
coreFix_memExe_regToExeQ$first[145:140] ;
assign coreFix_memExe_lsq$issueLd_lsqTag =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[76:72] :
coreFix_memExe_issueLd$wget[76:72] ;
assign coreFix_memExe_lsq$issueLd_paddr =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[71:8] :
coreFix_memExe_issueLd$wget[71:8] ;
assign coreFix_memExe_lsq$issueLd_sbRes =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 :
coreFix_memExe_stb$search ;
assign coreFix_memExe_lsq$issueLd_shiftedBE =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[7:0] :
coreFix_memExe_issueLd$wget[7:0] ;
assign coreFix_memExe_lsq$respLd_alignedData =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 :
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ;
assign coreFix_memExe_lsq$respLd_t =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 :
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 ;
assign coreFix_memExe_lsq$setAtCommit_0_put =
rob$deqPort_0_deq_data[24:19] ;
assign coreFix_memExe_lsq$setAtCommit_1_put =
rob$deqPort_1_deq_data[24:19] ;
assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_lsq$updateAddr_fault =
{ (!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
coreFix_memExe_dTlb$procResp[12] :
coreFix_memExe_dTlb$procResp[12] ||
coreFix_memExe_dTlb$procResp[110],
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1886 } ;
assign coreFix_memExe_lsq$updateAddr_isMMIO =
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760 ;
assign coreFix_memExe_lsq$updateAddr_lsqTag =
coreFix_memExe_dTlb$procResp[90:85] ;
assign coreFix_memExe_lsq$updateAddr_paddr =
coreFix_memExe_dTlb$procResp[174:111] ;
assign coreFix_memExe_lsq$updateAddr_shiftedBE =
coreFix_memExe_dTlb$procResp[84:77] ;
assign coreFix_memExe_lsq$updateData_d =
(coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ?
coreFix_memExe_regToExeQ$first[75:12] :
shiftData__h184291 ;
assign coreFix_memExe_lsq$updateData_t =
coreFix_memExe_regToExeQ$first[143:140] ;
assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
assign coreFix_memExe_lsq$EN_enqLd =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo7 ;
assign coreFix_memExe_lsq$EN_enqSt =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo2 ;
assign coreFix_memExe_lsq$EN_getHit =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign coreFix_memExe_lsq$EN_updateData =
WILL_FIRE_RL_coreFix_memExe_doExeMem &&
coreFix_memExe_regToExeQ$first[145] ;
assign coreFix_memExe_lsq$EN_updateAddr =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign coreFix_memExe_lsq$EN_issueLd =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign coreFix_memExe_lsq$EN_getIssueLd =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ;
assign coreFix_memExe_lsq$EN_respLd =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
assign coreFix_memExe_lsq$EN_deqLd =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign coreFix_memExe_lsq$EN_deqSt =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ;
assign coreFix_memExe_lsq$EN_wakeupLdStalledBySB =
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign coreFix_memExe_lsq$EN_setAtCommit_0_put =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
assign coreFix_memExe_lsq$EN_setAtCommit_1_put =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
assign coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_lsq$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_regToExeQ
assign coreFix_memExe_regToExeQ$enq_x =
{ coreFix_memExe_dispToRegQ$first[97:63],
coreFix_memExe_dispToRegQ$first[29:12],
x__h184198,
x__h184199,
coreFix_memExe_dispToRegQ$first[11:0] } ;
assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
assign coreFix_memExe_regToExeQ$EN_deq =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
assign coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
assign coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
assign coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
assign coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
assign coreFix_memExe_reqLdQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_full_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
assign coreFix_memExe_reqLdQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
assign coreFix_memExe_reqLdQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
assign coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_data_0_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
assign coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
assign coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
assign coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
assign coreFix_memExe_reqStQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_empty_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
assign coreFix_memExe_reqStQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
assign coreFix_memExe_reqStQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
assign coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_enqP_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
assign coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_full_dummy2_0
assign coreFix_memExe_reqStQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_full_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_full_dummy2_1
assign coreFix_memExe_reqStQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_full_dummy2_2
assign coreFix_memExe_reqStQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN =
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2594 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_rsMem
assign coreFix_memExe_rsMem$enq_x =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14301) ?
{ fetchStage$pipelines_0_first[191:189],
IF_fetchStage_pipelines_0_first__2932_BIT_160__ETC___d14317,
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[191:189],
IF_fetchStage_pipelines_1_first__2941_BIT_160__ETC___d14480,
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h687315,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_memExe_rsMem$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_memExe_rsMem$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_memExe_rsMem$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4;
default: coreFix_memExe_rsMem$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo12 ;
assign coreFix_memExe_rsMem$EN_setRobEnqTime = 1'd1 ;
assign coreFix_memExe_rsMem$EN_doDispatch =
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
assign coreFix_memExe_rsMem$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_memExe_rsMem$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_memExe_rsMem$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_memExe_rsMem$EN_setRegReady_3_put =
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_memExe_rsMem$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_stb
assign coreFix_memExe_stb$deq_idx =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[76:69] ;
assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[68:5] ;
assign coreFix_memExe_stb$enq_idx = coreFix_memExe_stb$getEnqIndex[1:0] ;
assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$getEnqIndex_paddr =
coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$noMatchLdQ_be = coreFix_memExe_lsq$firstLd[15:8] ;
assign coreFix_memExe_stb$noMatchLdQ_paddr =
coreFix_memExe_lsq$firstLd[80:17] ;
assign coreFix_memExe_stb$noMatchStQ_be =
coreFix_memExe_lsq$firstSt[76:69] ;
assign coreFix_memExe_stb$noMatchStQ_paddr =
coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$search_be =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[7:0] :
coreFix_memExe_issueLd$wget[7:0] ;
assign coreFix_memExe_stb$search_paddr =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[71:8] :
coreFix_memExe_issueLd$wget[71:8] ;
assign coreFix_memExe_stb$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ;
assign coreFix_memExe_stb$EN_deq =
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign coreFix_memExe_stb$EN_issue = CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_trainBPQ_0
assign coreFix_trainBPQ_0$D_IN =
MUX_coreFix_trainBPQ_0$enq_1__SEL_1 ?
MUX_coreFix_trainBPQ_0$enq_1__VAL_1 :
MUX_coreFix_trainBPQ_0$enq_1__VAL_2 ;
assign coreFix_trainBPQ_0$ENQ =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign coreFix_trainBPQ_0$DEQ = WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
assign coreFix_trainBPQ_0$CLR = 1'b0 ;
// submodule coreFix_trainBPQ_1
assign coreFix_trainBPQ_1$D_IN =
MUX_coreFix_trainBPQ_1$enq_1__SEL_1 ?
MUX_coreFix_trainBPQ_1$enq_1__VAL_1 :
MUX_coreFix_trainBPQ_1$enq_1__VAL_2 ;
assign coreFix_trainBPQ_1$ENQ =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign coreFix_trainBPQ_1$DEQ = coreFix_trainBPQ_1$EMPTY_N ;
assign coreFix_trainBPQ_1$CLR = 1'b0 ;
// submodule csrInstOrInterruptInflight_dummy2_0
assign csrInstOrInterruptInflight_dummy2_0$D_IN = 1'd1 ;
assign csrInstOrInterruptInflight_dummy2_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
(commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] == 4'd3) ;
// submodule csrInstOrInterruptInflight_dummy2_1
assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ;
assign csrInstOrInterruptInflight_dummy2_1$EN =
csrInstOrInterruptInflight_lat_1$whas ;
// submodule csrf_mcycle_ehr_data_dummy2_0
assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ;
assign csrf_mcycle_ehr_data_dummy2_0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2816 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd30 ;
// submodule csrf_mcycle_ehr_data_dummy2_1
assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ;
assign csrf_mcycle_ehr_data_dummy2_1$EN = 1'd1 ;
// submodule csrf_minstret_ehr_data_dummy2_0
assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ;
assign csrf_minstret_ehr_data_dummy2_0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2818 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd31 ;
// submodule csrf_minstret_ehr_data_dummy2_1
assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ;
assign csrf_minstret_ehr_data_dummy2_1$EN =
csrf_minstret_ehr_data_dummy_1_0$whas ;
// submodule csrf_stats_module_writeQ
assign csrf_stats_module_writeQ$D_IN =
MUX_csrf_stats_module_writeQ$enq_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_stats_module_writeQ$ENQ =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2049 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd7 ;
assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ;
assign csrf_stats_module_writeQ$CLR = 1'b0 ;
// submodule csrf_terminate_module_terminateQ
assign csrf_terminate_module_terminateQ$ENQ =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2048 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd6 ;
assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ;
assign csrf_terminate_module_terminateQ$CLR = 1'b0 ;
// submodule epochManager
assign epochManager$checkEpoch_0_check_e =
fetchStage$pipelines_0_first[259:256] ;
assign epochManager$checkEpoch_1_check_e =
fetchStage$pipelines_1_first[259:256] ;
assign epochManager$updatePrevEpoch_0_update_e =
fetchStage$pipelines_0_first[259:256] ;
assign epochManager$updatePrevEpoch_1_update_e =
fetchStage$pipelines_1_first[259:256] ;
assign epochManager$EN_updatePrevEpoch_0_update =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_0_canDeq ||
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign epochManager$EN_updatePrevEpoch_1_update =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_1_canDeq &&
!epochManager$checkEpoch_1_check ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d14401 &&
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 ;
assign epochManager$EN_incrementEpoch =
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[12] ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
// submodule f_csr_reqs
assign f_csr_reqs$D_IN = hart0_csr_mem_server_request_put ;
assign f_csr_reqs$ENQ = EN_hart0_csr_mem_server_request_put ;
assign f_csr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_csr_access_busy ||
WILL_FIRE_RL_rl_debug_csr_write ||
WILL_FIRE_RL_rl_debug_csr_read ;
assign f_csr_reqs$CLR = 1'b0 ;
// submodule f_csr_rsps
always@(WILL_FIRE_RL_rl_debug_csr_write or
WILL_FIRE_RL_rl_debug_csr_access_busy or
WILL_FIRE_RL_rl_debug_csr_read or MUX_f_csr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_csr_write:
f_csr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_csr_access_busy:
f_csr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_csr_read:
f_csr_rsps$D_IN = MUX_f_csr_rsps$enq_1__VAL_3;
default: f_csr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_csr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_csr_write ||
WILL_FIRE_RL_rl_debug_csr_access_busy ||
WILL_FIRE_RL_rl_debug_csr_read ;
assign f_csr_rsps$DEQ = EN_hart0_csr_mem_server_response_get ;
assign f_csr_rsps$CLR = 1'b0 ;
// submodule f_fpr_reqs
assign f_fpr_reqs$D_IN = hart0_fpr_mem_server_request_put ;
assign f_fpr_reqs$ENQ = EN_hart0_fpr_mem_server_request_put ;
assign f_fpr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_fpr_access_busy ||
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign f_fpr_reqs$CLR = 1'b0 ;
// submodule f_fpr_rsps
always@(WILL_FIRE_RL_rl_debug_fpr_write or
WILL_FIRE_RL_rl_debug_fpr_access_busy or
WILL_FIRE_RL_rl_debug_fpr_read or MUX_f_fpr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_fpr_write:
f_fpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_fpr_access_busy:
f_fpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_fpr_read:
f_fpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
default: f_fpr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_fpr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_access_busy ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign f_fpr_rsps$DEQ = EN_hart0_fpr_mem_server_response_get ;
assign f_fpr_rsps$CLR = 1'b0 ;
// submodule f_gpr_reqs
assign f_gpr_reqs$D_IN = hart0_gpr_mem_server_request_put ;
assign f_gpr_reqs$ENQ = EN_hart0_gpr_mem_server_request_put ;
assign f_gpr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_gpr_access_busy ||
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign f_gpr_reqs$CLR = 1'b0 ;
// submodule f_gpr_rsps
always@(WILL_FIRE_RL_rl_debug_gpr_write or
WILL_FIRE_RL_rl_debug_gpr_access_busy or
WILL_FIRE_RL_rl_debug_gpr_read or MUX_f_fpr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_gpr_write:
f_gpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_gpr_access_busy:
f_gpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_gpr_read:
f_gpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
default: f_gpr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_gpr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_access_busy ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign f_gpr_rsps$DEQ = EN_hart0_gpr_mem_server_response_get ;
assign f_gpr_rsps$CLR = 1'b0 ;
// submodule f_run_halt_reqs
assign f_run_halt_reqs$D_IN = hart0_run_halt_server_request_put ;
assign f_run_halt_reqs$ENQ = EN_hart0_run_halt_server_request_put ;
assign f_run_halt_reqs$DEQ =
WILL_FIRE_RL_rl_debug_run_redundant ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_rl_debug_halt_req_already_halted ||
WILL_FIRE_RL_rl_debug_halt_req ;
assign f_run_halt_reqs$CLR = 1'b0 ;
// submodule f_run_halt_rsps
assign f_run_halt_rsps$D_IN = !WILL_FIRE_RL_rl_debug_halted ;
assign f_run_halt_rsps$ENQ =
WILL_FIRE_RL_rl_debug_halted ||
WILL_FIRE_RL_rl_debug_run_redundant ||
WILL_FIRE_RL_rl_debug_resume ;
assign f_run_halt_rsps$DEQ = EN_hart0_run_halt_server_response_get ;
assign f_run_halt_rsps$CLR = 1'b0 ;
// submodule fetchStage
assign fetchStage$iMemIfc_perf_req_r = 2'h0 ;
assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ;
assign fetchStage$iMemIfc_to_parent_fromP_enq_x =
iCacheToParent_fromP_enq_x ;
assign fetchStage$iMemIfc_to_proc_request_put = 64'h0 ;
assign fetchStage$iTlbIfc_perf_req_r = 3'h0 ;
assign fetchStage$iTlbIfc_perf_setStatus_doStats = 1'b0 ;
assign fetchStage$iTlbIfc_toParent_rsFromP_enq_x =
l2Tlb$toChildren_rsToC_first[80:0] ;
assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ;
assign fetchStage$iTlbIfc_updateVMInfo_vm =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_2 :
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_2 ;
assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ;
assign fetchStage$mmioIfc_setHtifAddrs_fromHost =
coreReq_start_fromHostAddr ;
assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ;
assign fetchStage$perf_req_r = 2'h0 ;
assign fetchStage$perf_setStatus_doStats = 1'b0 ;
always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
pc__h711152 or
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
WILL_FIRE_RL_commitStage_doCommitKilledLd or
rob$deqPort_0_deq_data or
WILL_FIRE_RL_rl_debug_resume or
csrf_rg_dpc or
WILL_FIRE_RL_commitStage_doCommitSystemInst or
MUX_fetchStage$redirect_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_commitStage_rg_serial_num$write_1__SEL_1:
fetchStage$redirect_pc = pc__h711152;
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
fetchStage$redirect_pc = coreFix_aluExe_0_exeToFinQ$first[82:19];
WILL_FIRE_RL_commitStage_doCommitKilledLd:
fetchStage$redirect_pc = rob$deqPort_0_deq_data[353:290];
WILL_FIRE_RL_rl_debug_resume: fetchStage$redirect_pc = csrf_rg_dpc;
WILL_FIRE_RL_commitStage_doCommitSystemInst:
fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_6;
default: fetchStage$redirect_pc =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fetchStage$start_pc = coreReq_start_startpc ;
assign fetchStage$train_predictors_dpTrain =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[25:2] :
coreFix_trainBPQ_0$D_OUT[25:2] ;
assign fetchStage$train_predictors_iType =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[31:27] :
coreFix_trainBPQ_0$D_OUT[31:27] ;
assign fetchStage$train_predictors_isCompressed =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[0] :
coreFix_trainBPQ_0$D_OUT[0] ;
assign fetchStage$train_predictors_mispred =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[1] :
coreFix_trainBPQ_0$D_OUT[1] ;
assign fetchStage$train_predictors_next_pc =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[95:32] :
coreFix_trainBPQ_0$D_OUT[95:32] ;
assign fetchStage$train_predictors_pc =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[159:96] :
coreFix_trainBPQ_0$D_OUT[159:96] ;
assign fetchStage$train_predictors_taken =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[26] :
coreFix_trainBPQ_0$D_OUT[26] ;
assign fetchStage$EN_pipelines_0_deq =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_0_canDeq ||
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign fetchStage$EN_pipelines_1_deq =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_1_canDeq &&
!epochManager$checkEpoch_1_check ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d14401 &&
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 ;
assign fetchStage$EN_iTlbIfc_flush =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_rl_debug_resume ;
assign fetchStage$EN_iTlbIfc_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ;
assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ;
assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ;
assign fetchStage$EN_iTlbIfc_toParent_rsFromP_enq =
CAN_FIRE_RL_sendRsToITlb ;
assign fetchStage$EN_iTlbIfc_toParent_flush_request_get =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign fetchStage$EN_iTlbIfc_toParent_flush_response_put =
CAN_FIRE_RL_sendFlushDone ;
assign fetchStage$EN_iTlbIfc_perf_setStatus = 1'b0 ;
assign fetchStage$EN_iTlbIfc_perf_req = 1'b0 ;
assign fetchStage$EN_iTlbIfc_perf_resp = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_proc_request_put = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_proc_response_get = 1'b0 ;
assign fetchStage$EN_iMemIfc_flush = CAN_FIRE_RL_setDoFlushCaches ;
assign fetchStage$EN_iMemIfc_perf_setStatus = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_req = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_resp = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_parent_rsToP_deq =
EN_iCacheToParent_rsToP_deq ;
assign fetchStage$EN_iMemIfc_to_parent_rqToP_deq =
EN_iCacheToParent_rqToP_deq ;
assign fetchStage$EN_iMemIfc_to_parent_fromP_enq =
EN_iCacheToParent_fromP_enq ;
assign fetchStage$EN_iMemIfc_cRqStuck_get = EN_deadlock_iCacheCRqStuck_get ;
assign fetchStage$EN_iMemIfc_pRqStuck_get = EN_deadlock_iCachePRqStuck_get ;
assign fetchStage$EN_mmioIfc_instReq_deq = WILL_FIRE_RL_mmio_sendInstReq ;
assign fetchStage$EN_mmioIfc_instResp_enq = CAN_FIRE_RL_mmio_sendInstResp ;
assign fetchStage$EN_mmioIfc_setHtifAddrs = EN_coreReq_start ;
assign fetchStage$EN_start = EN_coreReq_start ;
assign fetchStage$EN_stop = 1'b0 ;
assign fetchStage$EN_setWaitRedirect =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[12] ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign fetchStage$EN_redirect =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign fetchStage$EN_setWaitFlush =
MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign fetchStage$EN_done_flushing = CAN_FIRE_RL_readyToFetch ;
assign fetchStage$EN_train_predictors =
coreFix_trainBPQ_1$EMPTY_N ||
WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_setDoFlushBrPred ;
assign fetchStage$EN_perf_setStatus = 1'b0 ;
assign fetchStage$EN_perf_req = 1'b0 ;
assign fetchStage$EN_perf_resp = 1'b0 ;
// submodule l2Tlb
assign l2Tlb$perf_req_r = 4'h0 ;
assign l2Tlb$perf_setStatus_doStats = 1'b0 ;
assign l2Tlb$toChildren_rqFromC_put =
WILL_FIRE_RL_sendDTlbReq ?
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 :
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ;
assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ;
assign l2Tlb$updateVMInfo_vmD =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 :
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ;
assign l2Tlb$updateVMInfo_vmI =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_2 :
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_2 ;
assign l2Tlb$EN_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign l2Tlb$EN_toChildren_rqFromC_put =
WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ;
assign l2Tlb$EN_toChildren_rsToC_deq =
WILL_FIRE_RL_sendRsToITlb || WILL_FIRE_RL_sendRsToDTlb ;
assign l2Tlb$EN_toChildren_iTlbReqFlush_put =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign l2Tlb$EN_toChildren_dTlbReqFlush_put =
CAN_FIRE_RL_mkConnectionGetPut ;
assign l2Tlb$EN_toChildren_flushDone_get = CAN_FIRE_RL_sendFlushDone ;
assign l2Tlb$EN_toMem_memReq_deq = EN_tlbToMem_memReq_deq ;
assign l2Tlb$EN_toMem_respLd_enq = EN_tlbToMem_respLd_enq ;
assign l2Tlb$EN_perf_setStatus = 1'b0 ;
assign l2Tlb$EN_perf_req = 1'b0 ;
assign l2Tlb$EN_perf_resp = 1'b0 ;
// submodule mmio_cRqQ_clearReq_dummy2_0
assign mmio_cRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_cRqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_cRqQ_clearReq_dummy2_1
assign mmio_cRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_cRqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_cRqQ_deqReq_dummy2_0
assign mmio_cRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRqQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRq_deq ;
// submodule mmio_cRqQ_deqReq_dummy2_1
assign mmio_cRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRqQ_deqReq_dummy2_2
assign mmio_cRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRqQ_enqReq_dummy2_0
assign mmio_cRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRqQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_mmio_sendInstReq || WILL_FIRE_RL_mmio_sendDataReq ;
// submodule mmio_cRqQ_enqReq_dummy2_1
assign mmio_cRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRqQ_enqReq_dummy2_2
assign mmio_cRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRsQ_clearReq_dummy2_0
assign mmio_cRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_cRsQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_cRsQ_clearReq_dummy2_1
assign mmio_cRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_cRsQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_cRsQ_deqReq_dummy2_0
assign mmio_cRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRsQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRs_deq ;
// submodule mmio_cRsQ_deqReq_dummy2_1
assign mmio_cRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRsQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRsQ_deqReq_dummy2_2
assign mmio_cRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRsQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRsQ_enqReq_dummy2_0
assign mmio_cRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRsQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
// submodule mmio_cRsQ_enqReq_dummy2_1
assign mmio_cRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRsQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRsQ_enqReq_dummy2_2
assign mmio_cRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRsQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataPendQ_clearReq_dummy2_0
assign mmio_dataPendQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataPendQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataPendQ_clearReq_dummy2_1
assign mmio_dataPendQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataPendQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataPendQ_deqReq_dummy2_0
assign mmio_dataPendQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataPendQ_deqReq_dummy2_0$EN =
mmio_dataRespQ_deqReq_lat_0$whas ;
// submodule mmio_dataPendQ_deqReq_dummy2_1
assign mmio_dataPendQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataPendQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataPendQ_deqReq_dummy2_2
assign mmio_dataPendQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataPendQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataPendQ_enqReq_dummy2_0
assign mmio_dataPendQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataPendQ_enqReq_dummy2_0$EN =
mmio_dataPendQ_enqReq_lat_0$whas ;
// submodule mmio_dataPendQ_enqReq_dummy2_1
assign mmio_dataPendQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataPendQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataPendQ_enqReq_dummy2_2
assign mmio_dataPendQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataPendQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataReqQ_clearReq_dummy2_0
assign mmio_dataReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataReqQ_clearReq_dummy2_1
assign mmio_dataReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataReqQ_deqReq_dummy2_0
assign mmio_dataReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataReqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataReq ;
// submodule mmio_dataReqQ_deqReq_dummy2_1
assign mmio_dataReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataReqQ_deqReq_dummy2_2
assign mmio_dataReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataReqQ_enqReq_dummy2_0
assign mmio_dataReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataReqQ_enqReq_dummy2_0$EN = mmio_dataPendQ_enqReq_lat_0$whas ;
// submodule mmio_dataReqQ_enqReq_dummy2_1
assign mmio_dataReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataReqQ_enqReq_dummy2_2
assign mmio_dataReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataRespQ_clearReq_dummy2_0
assign mmio_dataRespQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataRespQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataRespQ_clearReq_dummy2_1
assign mmio_dataRespQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataRespQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataRespQ_deqReq_dummy2_0
assign mmio_dataRespQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataRespQ_deqReq_dummy2_0$EN =
mmio_dataRespQ_deqReq_lat_0$whas ;
// submodule mmio_dataRespQ_deqReq_dummy2_1
assign mmio_dataRespQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataRespQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataRespQ_deqReq_dummy2_2
assign mmio_dataRespQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataRespQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataRespQ_enqReq_dummy2_0
assign mmio_dataRespQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataRespQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataResp ;
// submodule mmio_dataRespQ_enqReq_dummy2_1
assign mmio_dataRespQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataRespQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataRespQ_enqReq_dummy2_2
assign mmio_dataRespQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataRespQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRqQ_clearReq_dummy2_0
assign mmio_pRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_pRqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_pRqQ_clearReq_dummy2_1
assign mmio_pRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_pRqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_pRqQ_deqReq_dummy2_0
assign mmio_pRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
// submodule mmio_pRqQ_deqReq_dummy2_1
assign mmio_pRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRqQ_deqReq_dummy2_2
assign mmio_pRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRqQ_enqReq_dummy2_0
assign mmio_pRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRqQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRq_enq ;
// submodule mmio_pRqQ_enqReq_dummy2_1
assign mmio_pRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRqQ_enqReq_dummy2_2
assign mmio_pRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRsQ_clearReq_dummy2_0
assign mmio_pRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_pRsQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_pRsQ_clearReq_dummy2_1
assign mmio_pRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_pRsQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_pRsQ_deqReq_dummy2_0
assign mmio_pRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRsQ_deqReq_dummy2_0$EN = mmio_pRsQ_deqReq_lat_0$whas ;
// submodule mmio_pRsQ_deqReq_dummy2_1
assign mmio_pRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRsQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRsQ_deqReq_dummy2_2
assign mmio_pRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRsQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRsQ_enqReq_dummy2_0
assign mmio_pRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRsQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRs_enq ;
// submodule mmio_pRsQ_enqReq_dummy2_1
assign mmio_pRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRsQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRsQ_enqReq_dummy2_2
assign mmio_pRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRsQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule perfReqQ
assign perfReqQ$D_IN = { coreReq_perfReq_loc, coreReq_perfReq_t } ;
assign perfReqQ$ENQ = EN_coreReq_perfReq ;
assign perfReqQ$DEQ = EN_coreIndInv_perfResp ;
assign perfReqQ$CLR = 1'b0 ;
// submodule regRenamingTable
assign regRenamingTable$rename_0_claimRename_r =
fetchStage$pipelines_0_first[95:69] ;
assign regRenamingTable$rename_0_claimRename_sb =
specTagManager$currentSpecBits ;
always@(MUX_regRenamingTable$rename_0_getRename_1__SEL_1 or
fetchStage$pipelines_0_first or
MUX_regRenamingTable$rename_0_getRename_1__SEL_2 or
MUX_regRenamingTable$rename_0_getRename_1__VAL_2 or
MUX_regRenamingTable$rename_0_getRename_1__SEL_3 or
MUX_regRenamingTable$rename_0_getRename_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_regRenamingTable$rename_0_getRename_1__SEL_1:
regRenamingTable$rename_0_getRename_r =
fetchStage$pipelines_0_first[95:69];
MUX_regRenamingTable$rename_0_getRename_1__SEL_2:
regRenamingTable$rename_0_getRename_r =
MUX_regRenamingTable$rename_0_getRename_1__VAL_2;
MUX_regRenamingTable$rename_0_getRename_1__SEL_3:
regRenamingTable$rename_0_getRename_r =
MUX_regRenamingTable$rename_0_getRename_1__VAL_3;
default: regRenamingTable$rename_0_getRename_r =
27'b010101010101010101010101010 /* unspecified value */ ;
endcase
end
assign regRenamingTable$rename_1_claimRename_r =
fetchStage$pipelines_1_first[95:69] ;
assign regRenamingTable$rename_1_claimRename_sb =
renaming_spec_bits__h687315 ;
assign regRenamingTable$rename_1_getRename_r =
fetchStage$pipelines_1_first[95:69] ;
assign regRenamingTable$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign regRenamingTable$EN_rename_0_claimRename =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign regRenamingTable$EN_rename_1_claimRename =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign regRenamingTable$EN_commit_0_commit =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign regRenamingTable$EN_commit_1_commit =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] != 5'd0 &&
rob$deqPort_1_deq_data[257:253] != 5'd21 &&
rob$deqPort_1_deq_data[257:253] != 5'd17 &&
rob$deqPort_1_deq_data[257:253] != 5'd18 &&
rob$deqPort_1_deq_data[257:253] != 5'd13 &&
rob$deqPort_1_deq_data[257:253] != 5'd16 &&
rob$deqPort_1_deq_data[257:253] != 5'd15 &&
rob$deqPort_1_deq_data[257:253] != 5'd19 &&
rob$deqPort_1_deq_data[257:253] != 5'd20 ;
assign regRenamingTable$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign regRenamingTable$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule rf
assign rf$read_0_rd1_rindx = coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign rf$read_0_rd2_rindx = coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign rf$read_0_rd3_rindx = 7'h0 ;
assign rf$read_1_rd1_rindx = coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign rf$read_1_rd2_rindx = coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign rf$read_1_rd3_rindx = 7'h0 ;
assign rf$read_2_rd1_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign rf$read_2_rd2_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign rf$read_2_rd3_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[61:55] ;
assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[53:47] ;
assign rf$read_3_rd3_rindx = 7'h0 ;
assign rf$read_4_rd1_rindx = regRenamingTable$rename_0_getRename[31:25] ;
assign rf$read_4_rd2_rindx = 7'h0 ;
assign rf$read_4_rd3_rindx = 7'h0 ;
assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[275:212] ;
assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[275:212] ;
assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_rf$write_2_wr_2__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_rf$write_2_wr_2__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_rf$write_2_wr_2__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_rf$write_2_wr_2__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_rf$write_2_wr_2__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
rf$write_2_wr_data =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_6;
default: rf$write_2_wr_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: rf$write_2_wr_rindx = 7'b0101010 /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_2__SEL_1 or
coreFix_memExe_lsq$respLd or
MUX_rf$write_3_wr_1__SEL_2 or
coreFix_memExe_respLrScAmoQ_data_0 or
MUX_rf$write_3_wr_1__SEL_3 or
mmio_dataRespQ_data_0 or
MUX_rf$write_3_wr_1__SEL_4 or
MUX_rf$write_3_wr_2__VAL_4 or
MUX_rf$write_3_wr_1__SEL_5 or MUX_rf$write_3_wr_2__VAL_5)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_2__SEL_1:
rf$write_3_wr_data = coreFix_memExe_lsq$respLd[63:0];
MUX_rf$write_3_wr_1__SEL_2:
rf$write_3_wr_data = coreFix_memExe_respLrScAmoQ_data_0;
MUX_rf$write_3_wr_1__SEL_3:
rf$write_3_wr_data = mmio_dataRespQ_data_0[63:0];
MUX_rf$write_3_wr_1__SEL_4:
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_4;
MUX_rf$write_3_wr_1__SEL_5:
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_5;
default: rf$write_3_wr_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_1__SEL_1 or
coreFix_memExe_lsq$respLd or
MUX_rf$write_3_wr_1__SEL_4 or
MUX_rf$write_3_wr_1__SEL_5 or
coreFix_memExe_lsq$firstLd or
MUX_rf$write_3_wr_1__SEL_2 or
MUX_rf$write_3_wr_1__SEL_3 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_1__SEL_1:
rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[83:77];
MUX_rf$write_3_wr_1__SEL_4 || MUX_rf$write_3_wr_1__SEL_5:
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[88:82];
MUX_rf$write_3_wr_1__SEL_2 || MUX_rf$write_3_wr_1__SEL_3:
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[149:143];
default: rf$write_3_wr_rindx = 7'b0101010 /* unspecified value */ ;
endcase
end
assign rf$write_4_wr_data =
WILL_FIRE_RL_rl_debug_gpr_write ?
f_gpr_reqs$D_OUT[63:0] :
f_fpr_reqs$D_OUT[63:0] ;
assign rf$write_4_wr_rindx = regRenamingTable$rename_0_getRename[31:25] ;
assign rf$EN_write_0_wr =
_dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[321] ;
assign rf$EN_write_1_wr =
_dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[321] ;
assign rf$EN_write_2_wr =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign rf$EN_write_3_wr =
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[84] ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign rf$EN_write_4_wr =
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_fpr_write ;
// submodule rob
always@(MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 or
MUX_rob$enqPort_0_enq_1__VAL_1 or
WILL_FIRE_RL_renameStage_doRenaming_Trap or
MUX_rob$enqPort_0_enq_1__VAL_2 or
WILL_FIRE_RL_renameStage_doRenaming_SystemInst or
MUX_rob$enqPort_0_enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_1;
WILL_FIRE_RL_renameStage_doRenaming_Trap:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_2;
WILL_FIRE_RL_renameStage_doRenaming_SystemInst:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_3;
default: rob$enqPort_0_enq_x =
354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rob$enqPort_1_enq_x =
{ fetchStage$pipelines_1_first[387:324],
fetchStage$pipelines_1_first[127:96],
fetchStage$pipelines_1_first[199:195],
fetchStage$pipelines_1_first[75:69],
64'hAAAAAAAAAAAAAAAA,
fetchStage_pipelines_1_first__2941_BIT_173_375_ETC___d13842,
73'h1280000000000000000,
fetchStage$pipelines_1_first[323:260],
5'd0,
fetchStage$pipelines_1_first[75] &&
fetchStage$pipelines_1_first[74],
fetchStage$pipelines_1_first[194:192] != 3'd0 &&
fetchStage$pipelines_1_first[194:192] != 3'd1 &&
fetchStage$pipelines_1_first[194:192] != 3'd2 &&
fetchStage$pipelines_1_first[194:192] != 3'd3 &&
fetchStage$pipelines_1_first[194:192] != 3'd4,
fetchStage$pipelines_1_first[194:192] != 3'd2 ||
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14523 ||
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14474,
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14533,
7'd32,
renaming_spec_bits__h687315 } ;
assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
assign rob$getOrigPC_2_get_x = 12'h0 ;
assign rob$getOrigPredPC_0_get_x =
coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrigPredPC_1_get_x =
coreFix_aluExe_1_dispToRegQ$first[52:41] ;
assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or
MUX_rob$setExecuted_deqLSQ_2__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or
MUX_rob$setExecuted_deqLSQ_2__VAL_6 or
MUX_rob$setExecuted_deqLSQ_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault:
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault:
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6;
MUX_rob$setExecuted_deqLSQ_1__SEL_1 ||
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem:
rob$setExecuted_deqLSQ_cause = 5'd10;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault:
rob$setExecuted_deqLSQ_cause = 5'd21;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault:
rob$setExecuted_deqLSQ_cause = 5'd23;
default: rob$setExecuted_deqLSQ_cause =
5'b01010 /* unspecified value */ ;
endcase
end
assign rob$setExecuted_deqLSQ_ld_killed =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ?
coreFix_memExe_lsq$firstLd[2:0] :
3'd2 ;
assign rob$setExecuted_deqLSQ_x =
(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) ?
coreFix_memExe_lsq$firstLd[113:102] :
coreFix_memExe_lsq$firstSt[170:159] ;
assign rob$setExecuted_doFinishAlu_0_set_cf =
coreFix_aluExe_0_exeToFinQ$first[146:17] ;
assign rob$setExecuted_doFinishAlu_0_set_csrData =
coreFix_aluExe_0_exeToFinQ$first[211:147] ;
assign rob$setExecuted_doFinishAlu_0_set_dst_data =
coreFix_aluExe_0_exeToFinQ$first[275:212] ;
assign rob$setExecuted_doFinishAlu_0_set_x =
coreFix_aluExe_0_exeToFinQ$first[312:301] ;
assign rob$setExecuted_doFinishAlu_1_set_cf =
coreFix_aluExe_1_exeToFinQ$first[146:17] ;
assign rob$setExecuted_doFinishAlu_1_set_csrData =
coreFix_aluExe_1_exeToFinQ$first[211:147] ;
assign rob$setExecuted_doFinishAlu_1_set_dst_data =
coreFix_aluExe_1_exeToFinQ$first[275:212] ;
assign rob$setExecuted_doFinishAlu_1_set_x =
coreFix_aluExe_1_exeToFinQ$first[312:301] ;
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
MUX_rf$write_2_wr_2__VAL_2 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
MUX_rf$write_2_wr_2__VAL_3 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
MUX_rf$write_2_wr_2__VAL_4 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
MUX_rf$write_2_wr_2__VAL_5 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
MUX_rf$write_2_wr_2__VAL_6)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_2;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_3;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_4;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_5;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_6;
default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[37:33];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = 5'd0;
default: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
5'b01010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[23:12];
default: rob$setExecuted_doFinishFpuMulDiv_0_set_x =
12'b101010101010 /* unspecified value */ ;
endcase
end
always@(MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_1 or
coreFix_memExe_lsq$respLd or
MUX_rf$write_3_wr_1__SEL_2 or
coreFix_memExe_respLrScAmoQ_data_0 or
MUX_rf$write_3_wr_1__SEL_3 or
mmio_dataRespQ_data_0 or
MUX_rf$write_3_wr_1__SEL_4 or
MUX_rf$write_3_wr_2__VAL_4 or
MUX_rf$write_3_wr_1__SEL_5 or MUX_rf$write_3_wr_2__VAL_5)
begin
case (1'b1) // synopsys parallel_case
MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_1:
rob$setExecuted_doFinishMem_RegData_dst_data =
coreFix_memExe_lsq$respLd[63:0];
MUX_rf$write_3_wr_1__SEL_2:
rob$setExecuted_doFinishMem_RegData_dst_data =
coreFix_memExe_respLrScAmoQ_data_0;
MUX_rf$write_3_wr_1__SEL_3:
rob$setExecuted_doFinishMem_RegData_dst_data =
mmio_dataRespQ_data_0[63:0];
MUX_rf$write_3_wr_1__SEL_4:
rob$setExecuted_doFinishMem_RegData_dst_data =
MUX_rf$write_3_wr_2__VAL_4;
MUX_rf$write_3_wr_1__SEL_5:
rob$setExecuted_doFinishMem_RegData_dst_data =
MUX_rf$write_3_wr_2__VAL_5;
default: rob$setExecuted_doFinishMem_RegData_dst_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_1 or
coreFix_memExe_lsq$respLd or
MUX_rf$write_3_wr_1__SEL_4 or
MUX_rf$write_3_wr_1__SEL_5 or
coreFix_memExe_lsq$firstLd or
MUX_rf$write_3_wr_1__SEL_2 or
MUX_rf$write_3_wr_1__SEL_3 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_1:
rob$setExecuted_doFinishMem_RegData_x =
coreFix_memExe_lsq$respLd[75:64];
MUX_rf$write_3_wr_1__SEL_4 || MUX_rf$write_3_wr_1__SEL_5:
rob$setExecuted_doFinishMem_RegData_x =
coreFix_memExe_lsq$firstLd[113:102];
MUX_rf$write_3_wr_1__SEL_2 || MUX_rf$write_3_wr_1__SEL_3:
rob$setExecuted_doFinishMem_RegData_x =
coreFix_memExe_lsq$firstSt[170:159];
default: rob$setExecuted_doFinishMem_RegData_x =
12'b101010101010 /* unspecified value */ ;
endcase
end
assign rob$setExecuted_doFinishMem_access_at_commit =
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1769 &&
(coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd4) ;
assign rob$setExecuted_doFinishMem_non_mmio_st_done =
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1769 &&
NOT_coreFix_memExe_dTlb_procResp__741_BITS_174_ETC___d1780 &&
coreFix_memExe_dTlb$procResp[105:103] == 3'd1 ;
assign rob$setExecuted_doFinishMem_vaddr =
coreFix_memExe_dTlb$procResp[76:13] ;
assign rob$setExecuted_doFinishMem_x =
coreFix_memExe_dTlb$procResp[102:91] ;
assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ;
assign rob$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_inst_tag =
coreFix_aluExe_1_exeToFinQ$first[312:301];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_inst_tag =
coreFix_aluExe_0_exeToFinQ$first[312:301];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
rob$specUpdate_incorrectSpeculation_inst_tag =
12'b101010101010 /* unspecified value */ ;
default: rob$specUpdate_incorrectSpeculation_inst_tag =
12'b101010101010 /* unspecified value */ ;
endcase
end
assign rob$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_spec_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_spec_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
rob$specUpdate_incorrectSpeculation_spec_tag =
4'b1010 /* unspecified value */ ;
default: rob$specUpdate_incorrectSpeculation_spec_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign rob$EN_enqPort_0_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign rob$EN_enqPort_1_enq =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign rob$EN_deqPort_0_deq =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign rob$EN_deqPort_1_deq =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] != 5'd0 &&
rob$deqPort_1_deq_data[257:253] != 5'd21 &&
rob$deqPort_1_deq_data[257:253] != 5'd17 &&
rob$deqPort_1_deq_data[257:253] != 5'd18 &&
rob$deqPort_1_deq_data[257:253] != 5'd13 &&
rob$deqPort_1_deq_data[257:253] != 5'd16 &&
rob$deqPort_1_deq_data[257:253] != 5'd15 &&
rob$deqPort_1_deq_data[257:253] != 5'd19 &&
rob$deqPort_1_deq_data[257:253] != 5'd20 ;
assign rob$EN_setLSQAtCommitNotified =
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
assign rob$EN_setExecuted_deqLSQ =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ;
assign rob$EN_setExecuted_doFinishAlu_0_set =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign rob$EN_setExecuted_doFinishAlu_1_set =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign rob$EN_setExecuted_doFinishFpuMulDiv_0_set =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign rob$EN_setExecuted_doFinishMem =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign rob$EN_setExecuted_doFinishMem_RegData =
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[84] ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign rob$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign rob$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule sbAggr
assign sbAggr$eagerLookup_0_get_r = regRenamingTable$rename_0_getRename ;
assign sbAggr$eagerLookup_1_get_r = regRenamingTable$rename_1_getRename ;
assign sbAggr$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
assign sbAggr$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
assign sbAggr$setReady_0_put = coreFix_aluExe_0_rsAlu$dispatchData[40:34] ;
assign sbAggr$setReady_1_put = coreFix_aluExe_1_rsAlu$dispatchData[40:34] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: sbAggr$setReady_2_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[71:65] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 or
coreFix_memExe_lsq$getHit or
MUX_sbAggr$setReady_4_put_1__SEL_2 or
coreFix_memExe_lsq$firstLd or
MUX_sbAggr$setReady_4_put_1__SEL_1 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 ||
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
sbAggr$setReady_4_put = coreFix_memExe_lsq$getHit[7:1];
MUX_sbAggr$setReady_4_put_1__SEL_2:
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[88:82];
MUX_sbAggr$setReady_4_put_1__SEL_1:
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[149:143];
default: sbAggr$setReady_4_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbAggr$EN_setBusy_0_set =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign sbAggr$EN_setBusy_1_set =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign sbAggr$EN_setReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign sbAggr$EN_setReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign sbAggr$EN_setReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign sbAggr$EN_setReady_3_put =
_dor1sbAggr$EN_setReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign sbAggr$EN_setReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
// submodule sbCons
assign sbCons$eagerLookup_0_get_r = 33'h0 ;
assign sbCons$eagerLookup_1_get_r = 33'h0 ;
assign sbCons$lazyLookup_0_get_r =
coreFix_aluExe_0_dispToRegQ$first[85:53] ;
assign sbCons$lazyLookup_1_get_r =
coreFix_aluExe_1_dispToRegQ$first[85:53] ;
assign sbCons$lazyLookup_2_get_r =
coreFix_fpuMulDivExe_0_dispToRegQ$first[56:24] ;
assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[62:30] ;
assign sbCons$lazyLookup_4_get_r = 33'h0 ;
assign sbCons$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
assign sbCons$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: sbCons$setReady_2_put = 7'b0101010 /* unspecified value */ ;
endcase
end
always@(MUX_sbCons$setReady_3_put_1__SEL_1 or
coreFix_memExe_lsq$respLd or
MUX_sbCons$setReady_3_put_1__SEL_2 or
coreFix_memExe_lsq$firstSt or
MUX_sbCons$setReady_3_put_1__SEL_3 or coreFix_memExe_lsq$firstLd)
begin
case (1'b1) // synopsys parallel_case
MUX_sbCons$setReady_3_put_1__SEL_1:
sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[83:77];
MUX_sbCons$setReady_3_put_1__SEL_2:
sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[149:143];
MUX_sbCons$setReady_3_put_1__SEL_3:
sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[88:82];
default: sbCons$setReady_3_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbCons$setReady_4_put = 7'h0 ;
assign sbCons$EN_setBusy_0_set =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign sbCons$EN_setBusy_1_set =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign sbCons$EN_setReady_0_put =
_dor1sbCons$EN_setReady_0_put &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign sbCons$EN_setReady_1_put =
_dor1sbCons$EN_setReady_1_put &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign sbCons$EN_setReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign sbCons$EN_setReady_3_put =
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[84] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ;
assign sbCons$EN_setReady_4_put = 1'b0 ;
// submodule specTagManager
assign specTagManager$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 ;
assign specTagManager$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: specTagManager$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign specTagManager$EN_claimSpecTag =
WILL_FIRE_RL_renameStage_doRenaming &&
(fetchStage_pipelines_0_canDeq__2930_AND_specTa_ETC___d14349 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14512) ;
assign specTagManager$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule v_f_to_TV_0
always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
MUX_v_f_to_TV_0$enq_1__VAL_1 or
MUX_v_f_to_TV_0$enq_1__SEL_2 or
MUX_v_f_to_TV_0$enq_1__VAL_2 or
WILL_FIRE_RL_commitStage_rl_send_tv_reset or
MUX_v_f_to_TV_0$enq_1__VAL_3 or
WILL_FIRE_RL_commitStage_doCommitSystemInst or
MUX_v_f_to_TV_0$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_commitStage_rg_serial_num$write_1__SEL_1:
v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_1;
MUX_v_f_to_TV_0$enq_1__SEL_2:
v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_2;
WILL_FIRE_RL_commitStage_rl_send_tv_reset:
v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_3;
WILL_FIRE_RL_commitStage_doCommitSystemInst:
v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_4;
default: v_f_to_TV_0$D_IN =
713'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign v_f_to_TV_0$ENQ =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_rl_send_tv_reset ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign v_f_to_TV_0$DEQ = EN_v_to_TV_0_get ;
assign v_f_to_TV_0$CLR = 1'b0 ;
// submodule v_f_to_TV_1
assign v_f_to_TV_1$D_IN =
{ commitStage_rg_serial_num_4736_PLUS_IF_rob_deq_ETC___d15627,
rob$deqPort_1_deq_data[353:181],
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q301,
6'd10,
rob$deqPort_1_deq_data[161:98],
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q302,
rob$deqPort_1_deq_data[95:26],
mstatus_csr__read__h614607,
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign v_f_to_TV_1$ENQ =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] != 5'd0 &&
rob$deqPort_1_deq_data[257:253] != 5'd21 &&
rob$deqPort_1_deq_data[257:253] != 5'd17 &&
rob$deqPort_1_deq_data[257:253] != 5'd18 &&
rob$deqPort_1_deq_data[257:253] != 5'd13 &&
rob$deqPort_1_deq_data[257:253] != 5'd16 &&
rob$deqPort_1_deq_data[257:253] != 5'd15 &&
rob$deqPort_1_deq_data[257:253] != 5'd19 &&
rob$deqPort_1_deq_data[257:253] != 5'd20 ;
assign v_f_to_TV_1$DEQ = EN_v_to_TV_1_get ;
assign v_f_to_TV_1$CLR = 1'b0 ;
// remaining internal signals
module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]),
.amoExec_current_data(curData__h193958),
.amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]),
.amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]),
.amoExec(n__h195496));
module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32],
3'd0 }),
.amoExec_current_data({ 63'd0,
msip__h75952 }),
.amoExec_in_data({ 32'd0, x__h76067 }),
.amoExec_upper_32_bits(1'd0),
.amoExec(amoExec___d882));
module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228,
{ coreFix_aluExe_1_regToExeQ$first[395],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229,
coreFix_aluExe_1_regToExeQ$first[382],
coreFix_aluExe_1_regToExeQ$first[381:350] } }),
.basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]),
.basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[240:177]),
.basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]),
.basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]),
.basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]),
.basicExec(basicExec___d12105));
module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231,
{ coreFix_aluExe_0_regToExeQ$first[395],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232,
coreFix_aluExe_0_regToExeQ$first[382],
coreFix_aluExe_0_regToExeQ$first[381:350] } }),
.basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]),
.basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]),
.basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]),
.basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]),
.basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]),
.basicExec(basicExec___d12779));
module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061,
{ { fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143 },
fetchStage$pipelines_0_first[160],
x_data_imm__h679352 } }),
.checkForException_regs({ fetchStage$pipelines_0_first[95],
fetchStage$pipelines_0_first[94:89],
{ fetchStage$pipelines_0_first[88],
fetchStage$pipelines_0_first[87:82] },
{ fetchStage$pipelines_0_first[81],
fetchStage$pipelines_0_first[80:76],
{ fetchStage$pipelines_0_first[75],
fetchStage$pipelines_0_first[74:69] } } }),
.checkForException_csrState({ x_decodeInfo_frm__h659119,
r1__read_BITS_13_TO_12___h659304 !=
2'd0,
{ prv__h730760,
tvm_val__h723701,
{ r1__read_BIT_20___h659964,
tsr_val__h723699,
{ csrf_mcounteren_cy_reg,
csrf_mcounteren_cy_reg &&
csrf_scounteren_cy_reg,
{ csrf_mcounteren_ir_reg,
csrf_mcounteren_ir_reg &&
csrf_scounteren_ir_reg,
{ csrf_mcounteren_tm_reg,
csrf_mcounteren_tm_reg &&
csrf_scounteren_tm_reg } } } } } }),
.checkForException(checkForException___d13178));
module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d13758,
{ fetchStage_pipelines_1_first__2941_BIT_173_375_ETC___d13842,
fetchStage$pipelines_1_first[160],
x_data_imm__h694985 } }),
.checkForException_regs({ fetchStage$pipelines_1_first[95],
fetchStage$pipelines_1_first[94:89],
{ fetchStage$pipelines_1_first[88],
fetchStage$pipelines_1_first[87:82] },
{ fetchStage$pipelines_1_first[81],
fetchStage$pipelines_1_first[80:76],
{ fetchStage$pipelines_1_first[75],
fetchStage$pipelines_1_first[74:69] } } }),
.checkForException_csrState({ x_decodeInfo_frm__h659119,
r1__read_BITS_13_TO_12___h659304 !=
2'd0,
{ prv__h730760,
tvm_val__h723701,
{ r1__read_BIT_20___h659964,
tsr_val__h723699,
{ csrf_mcounteren_cy_reg,
csrf_mcounteren_cy_reg &&
csrf_scounteren_cy_reg,
{ csrf_mcounteren_ir_reg,
csrf_mcounteren_ir_reg &&
csrf_scounteren_ir_reg,
{ csrf_mcounteren_tm_reg,
csrf_mcounteren_tm_reg &&
csrf_scounteren_tm_reg } } } } } }),
.checkForException(checkForException___d13864));
module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229],
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q256,
coreFix_fpuMulDivExe_0_regToExeQ$first[225] }),
.execFpuSimple_rVal1(rVal1__h484791),
.execFpuSimple_rVal2(rVal2__h484792),
.execFpuSimple(execFpuSimple___d11168));
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4346 ?
_theResult___snd__h356785 :
_theResult____h348611 ;
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5738 ?
_theResult___snd__h402482 :
_theResult____h394310 ;
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7130 ?
_theResult___snd__h448177 :
_theResult____h440005 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9009 ?
_theResult___snd__h514203 :
_theResult____h505904 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9724 ?
_theResult___snd__h592360 :
_theResult____h584061 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10494 ?
_theResult___snd__h553056 :
_theResult____h544757 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7681 ?
_theResult___snd__h465943 :
_theResult____h457642 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4897 ?
_theResult___snd__h374551 :
_theResult____h366250 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6289 ?
_theResult___snd__h420248 :
_theResult____h411947 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8697 ?
_theResult___snd__h504552 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9059 ?
_theResult___snd__h504552 :
_theResult___snd__h522957 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9427 ?
_theResult___snd__h582709 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9774 ?
_theResult___snd__h582709 :
_theResult___snd__h601114 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10197 ?
_theResult___snd__h543405 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10544 ?
_theResult___snd__h543405 :
_theResult___snd__h561810 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7361 ?
_theResult___snd__h456759 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7754 ?
_theResult___snd__h456759 :
_theResult___snd__h474549 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4577 ?
_theResult___snd__h365367 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4970 ?
_theResult___snd__h365367 :
_theResult___snd__h383157 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5969 ?
_theResult___snd__h411064 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6362 ?
_theResult___snd__h411064 :
_theResult___snd__h428854 ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5166 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
((_theResult___fst_exp__h356722 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5151) :
((_theResult___fst_exp__h365378 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5164) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5216 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
((_theResult___fst_exp__h356722 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5207) :
((_theResult___fst_exp__h365378 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5214) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6558 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
((_theResult___fst_exp__h402419 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6543) :
((_theResult___fst_exp__h411075 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6556) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6608 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
((_theResult___fst_exp__h402419 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6599) :
((_theResult___fst_exp__h411075 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6606) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7950 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
((_theResult___fst_exp__h448114 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7935) :
((_theResult___fst_exp__h456770 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7948) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d8000 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
((_theResult___fst_exp__h448114 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7991) :
((_theResult___fst_exp__h456770 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7998) ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4344 =
(_theResult____h348611[56] ?
6'd0 :
(_theResult____h348611[55] ?
6'd1 :
(_theResult____h348611[54] ?
6'd2 :
(_theResult____h348611[53] ?
6'd3 :
(_theResult____h348611[52] ?
6'd4 :
(_theResult____h348611[51] ?
6'd5 :
(_theResult____h348611[50] ?
6'd6 :
(_theResult____h348611[49] ?
6'd7 :
(_theResult____h348611[48] ?
6'd8 :
(_theResult____h348611[47] ?
6'd9 :
(_theResult____h348611[46] ?
6'd10 :
(_theResult____h348611[45] ?
6'd11 :
(_theResult____h348611[44] ?
6'd12 :
(_theResult____h348611[43] ?
6'd13 :
(_theResult____h348611[42] ?
6'd14 :
(_theResult____h348611[41] ?
6'd15 :
(_theResult____h348611[40] ?
6'd16 :
(_theResult____h348611[39] ?
6'd17 :
(_theResult____h348611[38] ?
6'd18 :
(_theResult____h348611[37] ?
6'd19 :
(_theResult____h348611[36] ?
6'd20 :
(_theResult____h348611[35] ?
6'd21 :
(_theResult____h348611[34] ?
6'd22 :
(_theResult____h348611[33] ?
6'd23 :
(_theResult____h348611[32] ?
6'd24 :
(_theResult____h348611[31] ?
6'd25 :
(_theResult____h348611[30] ?
6'd26 :
(_theResult____h348611[29] ?
6'd27 :
(_theResult____h348611[28] ?
6'd28 :
(_theResult____h348611[27] ?
6'd29 :
(_theResult____h348611[26] ?
6'd30 :
(_theResult____h348611[25] ?
6'd31 :
(_theResult____h348611[24] ?
6'd32 :
(_theResult____h348611[23] ?
6'd33 :
(_theResult____h348611[22] ?
6'd34 :
(_theResult____h348611[21] ?
6'd35 :
(_theResult____h348611[20] ?
6'd36 :
(_theResult____h348611[19] ?
6'd37 :
(_theResult____h348611[18] ?
6'd38 :
(_theResult____h348611[17] ?
6'd39 :
(_theResult____h348611[16] ?
6'd40 :
(_theResult____h348611[15] ?
6'd41 :
(_theResult____h348611[14] ?
6'd42 :
(_theResult____h348611[13] ?
6'd43 :
(_theResult____h348611[12] ?
6'd44 :
(_theResult____h348611[11] ?
6'd45 :
(_theResult____h348611[10] ?
6'd46 :
(_theResult____h348611[9] ?
6'd47 :
(_theResult____h348611[8] ?
6'd48 :
(_theResult____h348611[7] ?
6'd49 :
(_theResult____h348611[6] ?
6'd50 :
(_theResult____h348611[5] ?
6'd51 :
(_theResult____h348611[4] ?
6'd52 :
(_theResult____h348611[3] ?
6'd53 :
(_theResult____h348611[2] ?
6'd54 :
(_theResult____h348611[1] ?
6'd55 :
(_theResult____h348611[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5736 =
(_theResult____h394310[56] ?
6'd0 :
(_theResult____h394310[55] ?
6'd1 :
(_theResult____h394310[54] ?
6'd2 :
(_theResult____h394310[53] ?
6'd3 :
(_theResult____h394310[52] ?
6'd4 :
(_theResult____h394310[51] ?
6'd5 :
(_theResult____h394310[50] ?
6'd6 :
(_theResult____h394310[49] ?
6'd7 :
(_theResult____h394310[48] ?
6'd8 :
(_theResult____h394310[47] ?
6'd9 :
(_theResult____h394310[46] ?
6'd10 :
(_theResult____h394310[45] ?
6'd11 :
(_theResult____h394310[44] ?
6'd12 :
(_theResult____h394310[43] ?
6'd13 :
(_theResult____h394310[42] ?
6'd14 :
(_theResult____h394310[41] ?
6'd15 :
(_theResult____h394310[40] ?
6'd16 :
(_theResult____h394310[39] ?
6'd17 :
(_theResult____h394310[38] ?
6'd18 :
(_theResult____h394310[37] ?
6'd19 :
(_theResult____h394310[36] ?
6'd20 :
(_theResult____h394310[35] ?
6'd21 :
(_theResult____h394310[34] ?
6'd22 :
(_theResult____h394310[33] ?
6'd23 :
(_theResult____h394310[32] ?
6'd24 :
(_theResult____h394310[31] ?
6'd25 :
(_theResult____h394310[30] ?
6'd26 :
(_theResult____h394310[29] ?
6'd27 :
(_theResult____h394310[28] ?
6'd28 :
(_theResult____h394310[27] ?
6'd29 :
(_theResult____h394310[26] ?
6'd30 :
(_theResult____h394310[25] ?
6'd31 :
(_theResult____h394310[24] ?
6'd32 :
(_theResult____h394310[23] ?
6'd33 :
(_theResult____h394310[22] ?
6'd34 :
(_theResult____h394310[21] ?
6'd35 :
(_theResult____h394310[20] ?
6'd36 :
(_theResult____h394310[19] ?
6'd37 :
(_theResult____h394310[18] ?
6'd38 :
(_theResult____h394310[17] ?
6'd39 :
(_theResult____h394310[16] ?
6'd40 :
(_theResult____h394310[15] ?
6'd41 :
(_theResult____h394310[14] ?
6'd42 :
(_theResult____h394310[13] ?
6'd43 :
(_theResult____h394310[12] ?
6'd44 :
(_theResult____h394310[11] ?
6'd45 :
(_theResult____h394310[10] ?
6'd46 :
(_theResult____h394310[9] ?
6'd47 :
(_theResult____h394310[8] ?
6'd48 :
(_theResult____h394310[7] ?
6'd49 :
(_theResult____h394310[6] ?
6'd50 :
(_theResult____h394310[5] ?
6'd51 :
(_theResult____h394310[4] ?
6'd52 :
(_theResult____h394310[3] ?
6'd53 :
(_theResult____h394310[2] ?
6'd54 :
(_theResult____h394310[1] ?
6'd55 :
(_theResult____h394310[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7128 =
(_theResult____h440005[56] ?
6'd0 :
(_theResult____h440005[55] ?
6'd1 :
(_theResult____h440005[54] ?
6'd2 :
(_theResult____h440005[53] ?
6'd3 :
(_theResult____h440005[52] ?
6'd4 :
(_theResult____h440005[51] ?
6'd5 :
(_theResult____h440005[50] ?
6'd6 :
(_theResult____h440005[49] ?
6'd7 :
(_theResult____h440005[48] ?
6'd8 :
(_theResult____h440005[47] ?
6'd9 :
(_theResult____h440005[46] ?
6'd10 :
(_theResult____h440005[45] ?
6'd11 :
(_theResult____h440005[44] ?
6'd12 :
(_theResult____h440005[43] ?
6'd13 :
(_theResult____h440005[42] ?
6'd14 :
(_theResult____h440005[41] ?
6'd15 :
(_theResult____h440005[40] ?
6'd16 :
(_theResult____h440005[39] ?
6'd17 :
(_theResult____h440005[38] ?
6'd18 :
(_theResult____h440005[37] ?
6'd19 :
(_theResult____h440005[36] ?
6'd20 :
(_theResult____h440005[35] ?
6'd21 :
(_theResult____h440005[34] ?
6'd22 :
(_theResult____h440005[33] ?
6'd23 :
(_theResult____h440005[32] ?
6'd24 :
(_theResult____h440005[31] ?
6'd25 :
(_theResult____h440005[30] ?
6'd26 :
(_theResult____h440005[29] ?
6'd27 :
(_theResult____h440005[28] ?
6'd28 :
(_theResult____h440005[27] ?
6'd29 :
(_theResult____h440005[26] ?
6'd30 :
(_theResult____h440005[25] ?
6'd31 :
(_theResult____h440005[24] ?
6'd32 :
(_theResult____h440005[23] ?
6'd33 :
(_theResult____h440005[22] ?
6'd34 :
(_theResult____h440005[21] ?
6'd35 :
(_theResult____h440005[20] ?
6'd36 :
(_theResult____h440005[19] ?
6'd37 :
(_theResult____h440005[18] ?
6'd38 :
(_theResult____h440005[17] ?
6'd39 :
(_theResult____h440005[16] ?
6'd40 :
(_theResult____h440005[15] ?
6'd41 :
(_theResult____h440005[14] ?
6'd42 :
(_theResult____h440005[13] ?
6'd43 :
(_theResult____h440005[12] ?
6'd44 :
(_theResult____h440005[11] ?
6'd45 :
(_theResult____h440005[10] ?
6'd46 :
(_theResult____h440005[9] ?
6'd47 :
(_theResult____h440005[8] ?
6'd48 :
(_theResult____h440005[7] ?
6'd49 :
(_theResult____h440005[6] ?
6'd50 :
(_theResult____h440005[5] ?
6'd51 :
(_theResult____h440005[4] ?
6'd52 :
(_theResult____h440005[3] ?
6'd53 :
(_theResult____h440005[2] ?
6'd54 :
(_theResult____h440005[1] ?
6'd55 :
(_theResult____h440005[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10492 =
(_theResult____h544757[56] ?
6'd0 :
(_theResult____h544757[55] ?
6'd1 :
(_theResult____h544757[54] ?
6'd2 :
(_theResult____h544757[53] ?
6'd3 :
(_theResult____h544757[52] ?
6'd4 :
(_theResult____h544757[51] ?
6'd5 :
(_theResult____h544757[50] ?
6'd6 :
(_theResult____h544757[49] ?
6'd7 :
(_theResult____h544757[48] ?
6'd8 :
(_theResult____h544757[47] ?
6'd9 :
(_theResult____h544757[46] ?
6'd10 :
(_theResult____h544757[45] ?
6'd11 :
(_theResult____h544757[44] ?
6'd12 :
(_theResult____h544757[43] ?
6'd13 :
(_theResult____h544757[42] ?
6'd14 :
(_theResult____h544757[41] ?
6'd15 :
(_theResult____h544757[40] ?
6'd16 :
(_theResult____h544757[39] ?
6'd17 :
(_theResult____h544757[38] ?
6'd18 :
(_theResult____h544757[37] ?
6'd19 :
(_theResult____h544757[36] ?
6'd20 :
(_theResult____h544757[35] ?
6'd21 :
(_theResult____h544757[34] ?
6'd22 :
(_theResult____h544757[33] ?
6'd23 :
(_theResult____h544757[32] ?
6'd24 :
(_theResult____h544757[31] ?
6'd25 :
(_theResult____h544757[30] ?
6'd26 :
(_theResult____h544757[29] ?
6'd27 :
(_theResult____h544757[28] ?
6'd28 :
(_theResult____h544757[27] ?
6'd29 :
(_theResult____h544757[26] ?
6'd30 :
(_theResult____h544757[25] ?
6'd31 :
(_theResult____h544757[24] ?
6'd32 :
(_theResult____h544757[23] ?
6'd33 :
(_theResult____h544757[22] ?
6'd34 :
(_theResult____h544757[21] ?
6'd35 :
(_theResult____h544757[20] ?
6'd36 :
(_theResult____h544757[19] ?
6'd37 :
(_theResult____h544757[18] ?
6'd38 :
(_theResult____h544757[17] ?
6'd39 :
(_theResult____h544757[16] ?
6'd40 :
(_theResult____h544757[15] ?
6'd41 :
(_theResult____h544757[14] ?
6'd42 :
(_theResult____h544757[13] ?
6'd43 :
(_theResult____h544757[12] ?
6'd44 :
(_theResult____h544757[11] ?
6'd45 :
(_theResult____h544757[10] ?
6'd46 :
(_theResult____h544757[9] ?
6'd47 :
(_theResult____h544757[8] ?
6'd48 :
(_theResult____h544757[7] ?
6'd49 :
(_theResult____h544757[6] ?
6'd50 :
(_theResult____h544757[5] ?
6'd51 :
(_theResult____h544757[4] ?
6'd52 :
(_theResult____h544757[3] ?
6'd53 :
(_theResult____h544757[2] ?
6'd54 :
(_theResult____h544757[1] ?
6'd55 :
(_theResult____h544757[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9007 =
(_theResult____h505904[56] ?
6'd0 :
(_theResult____h505904[55] ?
6'd1 :
(_theResult____h505904[54] ?
6'd2 :
(_theResult____h505904[53] ?
6'd3 :
(_theResult____h505904[52] ?
6'd4 :
(_theResult____h505904[51] ?
6'd5 :
(_theResult____h505904[50] ?
6'd6 :
(_theResult____h505904[49] ?
6'd7 :
(_theResult____h505904[48] ?
6'd8 :
(_theResult____h505904[47] ?
6'd9 :
(_theResult____h505904[46] ?
6'd10 :
(_theResult____h505904[45] ?
6'd11 :
(_theResult____h505904[44] ?
6'd12 :
(_theResult____h505904[43] ?
6'd13 :
(_theResult____h505904[42] ?
6'd14 :
(_theResult____h505904[41] ?
6'd15 :
(_theResult____h505904[40] ?
6'd16 :
(_theResult____h505904[39] ?
6'd17 :
(_theResult____h505904[38] ?
6'd18 :
(_theResult____h505904[37] ?
6'd19 :
(_theResult____h505904[36] ?
6'd20 :
(_theResult____h505904[35] ?
6'd21 :
(_theResult____h505904[34] ?
6'd22 :
(_theResult____h505904[33] ?
6'd23 :
(_theResult____h505904[32] ?
6'd24 :
(_theResult____h505904[31] ?
6'd25 :
(_theResult____h505904[30] ?
6'd26 :
(_theResult____h505904[29] ?
6'd27 :
(_theResult____h505904[28] ?
6'd28 :
(_theResult____h505904[27] ?
6'd29 :
(_theResult____h505904[26] ?
6'd30 :
(_theResult____h505904[25] ?
6'd31 :
(_theResult____h505904[24] ?
6'd32 :
(_theResult____h505904[23] ?
6'd33 :
(_theResult____h505904[22] ?
6'd34 :
(_theResult____h505904[21] ?
6'd35 :
(_theResult____h505904[20] ?
6'd36 :
(_theResult____h505904[19] ?
6'd37 :
(_theResult____h505904[18] ?
6'd38 :
(_theResult____h505904[17] ?
6'd39 :
(_theResult____h505904[16] ?
6'd40 :
(_theResult____h505904[15] ?
6'd41 :
(_theResult____h505904[14] ?
6'd42 :
(_theResult____h505904[13] ?
6'd43 :
(_theResult____h505904[12] ?
6'd44 :
(_theResult____h505904[11] ?
6'd45 :
(_theResult____h505904[10] ?
6'd46 :
(_theResult____h505904[9] ?
6'd47 :
(_theResult____h505904[8] ?
6'd48 :
(_theResult____h505904[7] ?
6'd49 :
(_theResult____h505904[6] ?
6'd50 :
(_theResult____h505904[5] ?
6'd51 :
(_theResult____h505904[4] ?
6'd52 :
(_theResult____h505904[3] ?
6'd53 :
(_theResult____h505904[2] ?
6'd54 :
(_theResult____h505904[1] ?
6'd55 :
(_theResult____h505904[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9722 =
(_theResult____h584061[56] ?
6'd0 :
(_theResult____h584061[55] ?
6'd1 :
(_theResult____h584061[54] ?
6'd2 :
(_theResult____h584061[53] ?
6'd3 :
(_theResult____h584061[52] ?
6'd4 :
(_theResult____h584061[51] ?
6'd5 :
(_theResult____h584061[50] ?
6'd6 :
(_theResult____h584061[49] ?
6'd7 :
(_theResult____h584061[48] ?
6'd8 :
(_theResult____h584061[47] ?
6'd9 :
(_theResult____h584061[46] ?
6'd10 :
(_theResult____h584061[45] ?
6'd11 :
(_theResult____h584061[44] ?
6'd12 :
(_theResult____h584061[43] ?
6'd13 :
(_theResult____h584061[42] ?
6'd14 :
(_theResult____h584061[41] ?
6'd15 :
(_theResult____h584061[40] ?
6'd16 :
(_theResult____h584061[39] ?
6'd17 :
(_theResult____h584061[38] ?
6'd18 :
(_theResult____h584061[37] ?
6'd19 :
(_theResult____h584061[36] ?
6'd20 :
(_theResult____h584061[35] ?
6'd21 :
(_theResult____h584061[34] ?
6'd22 :
(_theResult____h584061[33] ?
6'd23 :
(_theResult____h584061[32] ?
6'd24 :
(_theResult____h584061[31] ?
6'd25 :
(_theResult____h584061[30] ?
6'd26 :
(_theResult____h584061[29] ?
6'd27 :
(_theResult____h584061[28] ?
6'd28 :
(_theResult____h584061[27] ?
6'd29 :
(_theResult____h584061[26] ?
6'd30 :
(_theResult____h584061[25] ?
6'd31 :
(_theResult____h584061[24] ?
6'd32 :
(_theResult____h584061[23] ?
6'd33 :
(_theResult____h584061[22] ?
6'd34 :
(_theResult____h584061[21] ?
6'd35 :
(_theResult____h584061[20] ?
6'd36 :
(_theResult____h584061[19] ?
6'd37 :
(_theResult____h584061[18] ?
6'd38 :
(_theResult____h584061[17] ?
6'd39 :
(_theResult____h584061[16] ?
6'd40 :
(_theResult____h584061[15] ?
6'd41 :
(_theResult____h584061[14] ?
6'd42 :
(_theResult____h584061[13] ?
6'd43 :
(_theResult____h584061[12] ?
6'd44 :
(_theResult____h584061[11] ?
6'd45 :
(_theResult____h584061[10] ?
6'd46 :
(_theResult____h584061[9] ?
6'd47 :
(_theResult____h584061[8] ?
6'd48 :
(_theResult____h584061[7] ?
6'd49 :
(_theResult____h584061[6] ?
6'd50 :
(_theResult____h584061[5] ?
6'd51 :
(_theResult____h584061[4] ?
6'd52 :
(_theResult____h584061[3] ?
6'd53 :
(_theResult____h584061[2] ?
6'd54 :
(_theResult____h584061[1] ?
6'd55 :
(_theResult____h584061[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4895 =
(_theResult____h366250[56] ?
6'd0 :
(_theResult____h366250[55] ?
6'd1 :
(_theResult____h366250[54] ?
6'd2 :
(_theResult____h366250[53] ?
6'd3 :
(_theResult____h366250[52] ?
6'd4 :
(_theResult____h366250[51] ?
6'd5 :
(_theResult____h366250[50] ?
6'd6 :
(_theResult____h366250[49] ?
6'd7 :
(_theResult____h366250[48] ?
6'd8 :
(_theResult____h366250[47] ?
6'd9 :
(_theResult____h366250[46] ?
6'd10 :
(_theResult____h366250[45] ?
6'd11 :
(_theResult____h366250[44] ?
6'd12 :
(_theResult____h366250[43] ?
6'd13 :
(_theResult____h366250[42] ?
6'd14 :
(_theResult____h366250[41] ?
6'd15 :
(_theResult____h366250[40] ?
6'd16 :
(_theResult____h366250[39] ?
6'd17 :
(_theResult____h366250[38] ?
6'd18 :
(_theResult____h366250[37] ?
6'd19 :
(_theResult____h366250[36] ?
6'd20 :
(_theResult____h366250[35] ?
6'd21 :
(_theResult____h366250[34] ?
6'd22 :
(_theResult____h366250[33] ?
6'd23 :
(_theResult____h366250[32] ?
6'd24 :
(_theResult____h366250[31] ?
6'd25 :
(_theResult____h366250[30] ?
6'd26 :
(_theResult____h366250[29] ?
6'd27 :
(_theResult____h366250[28] ?
6'd28 :
(_theResult____h366250[27] ?
6'd29 :
(_theResult____h366250[26] ?
6'd30 :
(_theResult____h366250[25] ?
6'd31 :
(_theResult____h366250[24] ?
6'd32 :
(_theResult____h366250[23] ?
6'd33 :
(_theResult____h366250[22] ?
6'd34 :
(_theResult____h366250[21] ?
6'd35 :
(_theResult____h366250[20] ?
6'd36 :
(_theResult____h366250[19] ?
6'd37 :
(_theResult____h366250[18] ?
6'd38 :
(_theResult____h366250[17] ?
6'd39 :
(_theResult____h366250[16] ?
6'd40 :
(_theResult____h366250[15] ?
6'd41 :
(_theResult____h366250[14] ?
6'd42 :
(_theResult____h366250[13] ?
6'd43 :
(_theResult____h366250[12] ?
6'd44 :
(_theResult____h366250[11] ?
6'd45 :
(_theResult____h366250[10] ?
6'd46 :
(_theResult____h366250[9] ?
6'd47 :
(_theResult____h366250[8] ?
6'd48 :
(_theResult____h366250[7] ?
6'd49 :
(_theResult____h366250[6] ?
6'd50 :
(_theResult____h366250[5] ?
6'd51 :
(_theResult____h366250[4] ?
6'd52 :
(_theResult____h366250[3] ?
6'd53 :
(_theResult____h366250[2] ?
6'd54 :
(_theResult____h366250[1] ?
6'd55 :
(_theResult____h366250[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6287 =
(_theResult____h411947[56] ?
6'd0 :
(_theResult____h411947[55] ?
6'd1 :
(_theResult____h411947[54] ?
6'd2 :
(_theResult____h411947[53] ?
6'd3 :
(_theResult____h411947[52] ?
6'd4 :
(_theResult____h411947[51] ?
6'd5 :
(_theResult____h411947[50] ?
6'd6 :
(_theResult____h411947[49] ?
6'd7 :
(_theResult____h411947[48] ?
6'd8 :
(_theResult____h411947[47] ?
6'd9 :
(_theResult____h411947[46] ?
6'd10 :
(_theResult____h411947[45] ?
6'd11 :
(_theResult____h411947[44] ?
6'd12 :
(_theResult____h411947[43] ?
6'd13 :
(_theResult____h411947[42] ?
6'd14 :
(_theResult____h411947[41] ?
6'd15 :
(_theResult____h411947[40] ?
6'd16 :
(_theResult____h411947[39] ?
6'd17 :
(_theResult____h411947[38] ?
6'd18 :
(_theResult____h411947[37] ?
6'd19 :
(_theResult____h411947[36] ?
6'd20 :
(_theResult____h411947[35] ?
6'd21 :
(_theResult____h411947[34] ?
6'd22 :
(_theResult____h411947[33] ?
6'd23 :
(_theResult____h411947[32] ?
6'd24 :
(_theResult____h411947[31] ?
6'd25 :
(_theResult____h411947[30] ?
6'd26 :
(_theResult____h411947[29] ?
6'd27 :
(_theResult____h411947[28] ?
6'd28 :
(_theResult____h411947[27] ?
6'd29 :
(_theResult____h411947[26] ?
6'd30 :
(_theResult____h411947[25] ?
6'd31 :
(_theResult____h411947[24] ?
6'd32 :
(_theResult____h411947[23] ?
6'd33 :
(_theResult____h411947[22] ?
6'd34 :
(_theResult____h411947[21] ?
6'd35 :
(_theResult____h411947[20] ?
6'd36 :
(_theResult____h411947[19] ?
6'd37 :
(_theResult____h411947[18] ?
6'd38 :
(_theResult____h411947[17] ?
6'd39 :
(_theResult____h411947[16] ?
6'd40 :
(_theResult____h411947[15] ?
6'd41 :
(_theResult____h411947[14] ?
6'd42 :
(_theResult____h411947[13] ?
6'd43 :
(_theResult____h411947[12] ?
6'd44 :
(_theResult____h411947[11] ?
6'd45 :
(_theResult____h411947[10] ?
6'd46 :
(_theResult____h411947[9] ?
6'd47 :
(_theResult____h411947[8] ?
6'd48 :
(_theResult____h411947[7] ?
6'd49 :
(_theResult____h411947[6] ?
6'd50 :
(_theResult____h411947[5] ?
6'd51 :
(_theResult____h411947[4] ?
6'd52 :
(_theResult____h411947[3] ?
6'd53 :
(_theResult____h411947[2] ?
6'd54 :
(_theResult____h411947[1] ?
6'd55 :
(_theResult____h411947[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7679 =
(_theResult____h457642[56] ?
6'd0 :
(_theResult____h457642[55] ?
6'd1 :
(_theResult____h457642[54] ?
6'd2 :
(_theResult____h457642[53] ?
6'd3 :
(_theResult____h457642[52] ?
6'd4 :
(_theResult____h457642[51] ?
6'd5 :
(_theResult____h457642[50] ?
6'd6 :
(_theResult____h457642[49] ?
6'd7 :
(_theResult____h457642[48] ?
6'd8 :
(_theResult____h457642[47] ?
6'd9 :
(_theResult____h457642[46] ?
6'd10 :
(_theResult____h457642[45] ?
6'd11 :
(_theResult____h457642[44] ?
6'd12 :
(_theResult____h457642[43] ?
6'd13 :
(_theResult____h457642[42] ?
6'd14 :
(_theResult____h457642[41] ?
6'd15 :
(_theResult____h457642[40] ?
6'd16 :
(_theResult____h457642[39] ?
6'd17 :
(_theResult____h457642[38] ?
6'd18 :
(_theResult____h457642[37] ?
6'd19 :
(_theResult____h457642[36] ?
6'd20 :
(_theResult____h457642[35] ?
6'd21 :
(_theResult____h457642[34] ?
6'd22 :
(_theResult____h457642[33] ?
6'd23 :
(_theResult____h457642[32] ?
6'd24 :
(_theResult____h457642[31] ?
6'd25 :
(_theResult____h457642[30] ?
6'd26 :
(_theResult____h457642[29] ?
6'd27 :
(_theResult____h457642[28] ?
6'd28 :
(_theResult____h457642[27] ?
6'd29 :
(_theResult____h457642[26] ?
6'd30 :
(_theResult____h457642[25] ?
6'd31 :
(_theResult____h457642[24] ?
6'd32 :
(_theResult____h457642[23] ?
6'd33 :
(_theResult____h457642[22] ?
6'd34 :
(_theResult____h457642[21] ?
6'd35 :
(_theResult____h457642[20] ?
6'd36 :
(_theResult____h457642[19] ?
6'd37 :
(_theResult____h457642[18] ?
6'd38 :
(_theResult____h457642[17] ?
6'd39 :
(_theResult____h457642[16] ?
6'd40 :
(_theResult____h457642[15] ?
6'd41 :
(_theResult____h457642[14] ?
6'd42 :
(_theResult____h457642[13] ?
6'd43 :
(_theResult____h457642[12] ?
6'd44 :
(_theResult____h457642[11] ?
6'd45 :
(_theResult____h457642[10] ?
6'd46 :
(_theResult____h457642[9] ?
6'd47 :
(_theResult____h457642[8] ?
6'd48 :
(_theResult____h457642[7] ?
6'd49 :
(_theResult____h457642[6] ?
6'd50 :
(_theResult____h457642[5] ?
6'd51 :
(_theResult____h457642[4] ?
6'd52 :
(_theResult____h457642[3] ?
6'd53 :
(_theResult____h457642[2] ?
6'd54 :
(_theResult____h457642[1] ?
6'd55 :
(_theResult____h457642[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10034 =
(_theResult___fst_exp__h592297 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard84071_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10536 =
(_theResult___fst_exp__h552993 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard44767_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10803 =
(_theResult___fst_exp__h552993 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard44767_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9051 =
(_theResult___fst_exp__h514140 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard05914_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9766 =
(_theResult___fst_exp__h592297 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard84071_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4407 =
(guard__h348621 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h356722 :
_theResult___exp__h357238 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410 =
(guard__h348621 == 2'b0) ?
_theResult___fst_exp__h356722 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h357238 :
_theResult___fst_exp__h356722) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5054 =
(guard__h348621 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
sfdin__h356716[56:34] :
_theResult___sfd__h357239 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5056 =
(guard__h348621 == 2'b0) ?
sfdin__h356716[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h357239 :
sfdin__h356716[56:34]) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5799 =
(guard__h394320 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h402419 :
_theResult___exp__h402935 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802 =
(guard__h394320 == 2'b0) ?
_theResult___fst_exp__h402419 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h402935 :
_theResult___fst_exp__h402419) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6446 =
(guard__h394320 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
sfdin__h402413[56:34] :
_theResult___sfd__h402936 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6448 =
(guard__h394320 == 2'b0) ?
sfdin__h402413[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h402936 :
sfdin__h402413[56:34]) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7191 =
(guard__h440015 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h448114 :
_theResult___exp__h448630 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194 =
(guard__h440015 == 2'b0) ?
_theResult___fst_exp__h448114 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h448630 :
_theResult___fst_exp__h448114) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7838 =
(guard__h440015 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
sfdin__h448108[56:34] :
_theResult___sfd__h448631 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7840 =
(guard__h440015 == 2'b0) ?
sfdin__h448108[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h448631 :
sfdin__h448108[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10648 =
(guard__h544767 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h552993 :
_theResult___exp__h553722 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10650 =
(guard__h544767 == 2'b0) ?
_theResult___fst_exp__h552993 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h553722 :
_theResult___fst_exp__h552993) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10731 =
(guard__h544767 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
sfdin__h552987[56:5] :
_theResult___sfd__h553723 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10733 =
(guard__h544767 == 2'b0) ?
sfdin__h552987[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h553723 :
sfdin__h552987[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9168 =
(guard__h505914 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h514140 :
_theResult___exp__h514869 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9170 =
(guard__h505914 == 2'b0) ?
_theResult___fst_exp__h514140 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h514869 :
_theResult___fst_exp__h514140) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9252 =
(guard__h505914 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
sfdin__h514134[56:5] :
_theResult___sfd__h514870 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9254 =
(guard__h505914 == 2'b0) ?
sfdin__h514134[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h514870 :
sfdin__h514134[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9878 =
(guard__h584071 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h592297 :
_theResult___exp__h593026 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9880 =
(guard__h584071 == 2'b0) ?
_theResult___fst_exp__h592297 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h593026 :
_theResult___fst_exp__h592297) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9961 =
(guard__h584071 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
sfdin__h592291[56:5] :
_theResult___sfd__h593027 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9963 =
(guard__h584071 == 2'b0) ?
sfdin__h592291[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h593027 :
sfdin__h592291[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4954 =
(guard__h366260 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h374488 :
_theResult___exp__h375004 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4956 =
(guard__h366260 == 2'b0) ?
_theResult___fst_exp__h374488 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h375004 :
_theResult___fst_exp__h374488) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5100 =
(guard__h366260 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
sfdin__h374482[56:34] :
_theResult___sfd__h375005 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5102 =
(guard__h366260 == 2'b0) ?
sfdin__h374482[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h375005 :
sfdin__h374482[56:34]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6346 =
(guard__h411957 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h420185 :
_theResult___exp__h420701 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6348 =
(guard__h411957 == 2'b0) ?
_theResult___fst_exp__h420185 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h420701 :
_theResult___fst_exp__h420185) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6492 =
(guard__h411957 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
sfdin__h420179[56:34] :
_theResult___sfd__h420702 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6494 =
(guard__h411957 == 2'b0) ?
sfdin__h420179[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h420702 :
sfdin__h420179[56:34]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7738 =
(guard__h457652 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h465880 :
_theResult___exp__h466396 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7740 =
(guard__h457652 == 2'b0) ?
_theResult___fst_exp__h465880 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h466396 :
_theResult___fst_exp__h465880) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7884 =
(guard__h457652 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
sfdin__h465874[56:34] :
_theResult___sfd__h466397 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7886 =
(guard__h457652 == 2'b0) ?
sfdin__h465874[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h466397 :
sfdin__h465874[56:34]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10610 =
(guard__h535455 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h543416 :
_theResult___exp__h544071 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10612 =
(guard__h535455 == 2'b0) ?
_theResult___fst_exp__h543416 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h544071 :
_theResult___fst_exp__h543416) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10679 =
(guard__h553836 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h561826 :
_theResult___exp__h562506 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10681 =
(guard__h553836 == 2'b0) ?
_theResult___fst_exp__h561826 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h562506 :
_theResult___fst_exp__h561826) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10705 =
(guard__h535455 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___snd__h543367[56:5] :
_theResult___sfd__h544072 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10707 =
(guard__h535455 == 2'b0) ?
_theResult___snd__h543367[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h544072 :
_theResult___snd__h543367[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10750 =
(guard__h553836 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___snd__h561772[56:5] :
_theResult___sfd__h562507 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10752 =
(guard__h553836 == 2'b0) ?
_theResult___snd__h561772[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h562507 :
_theResult___snd__h561772[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9125 =
(guard__h496602 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h504563 :
_theResult___exp__h505218 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9127 =
(guard__h496602 == 2'b0) ?
_theResult___fst_exp__h504563 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h505218 :
_theResult___fst_exp__h504563) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9199 =
(guard__h514983 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h522973 :
_theResult___exp__h523653 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9201 =
(guard__h514983 == 2'b0) ?
_theResult___fst_exp__h522973 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h523653 :
_theResult___fst_exp__h522973) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9225 =
(guard__h496602 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___snd__h504514[56:5] :
_theResult___sfd__h505219 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9227 =
(guard__h496602 == 2'b0) ?
_theResult___snd__h504514[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h505219 :
_theResult___snd__h504514[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9271 =
(guard__h514983 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___snd__h522919[56:5] :
_theResult___sfd__h523654 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9273 =
(guard__h514983 == 2'b0) ?
_theResult___snd__h522919[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h523654 :
_theResult___snd__h522919[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9840 =
(guard__h574759 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h582720 :
_theResult___exp__h583375 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9842 =
(guard__h574759 == 2'b0) ?
_theResult___fst_exp__h582720 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h583375 :
_theResult___fst_exp__h582720) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9909 =
(guard__h593140 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h601130 :
_theResult___exp__h601810 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9911 =
(guard__h593140 == 2'b0) ?
_theResult___fst_exp__h601130 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h601810 :
_theResult___fst_exp__h601130) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9935 =
(guard__h574759 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___snd__h582671[56:5] :
_theResult___sfd__h583376 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9937 =
(guard__h574759 == 2'b0) ?
_theResult___snd__h582671[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h583376 :
_theResult___snd__h582671[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9980 =
(guard__h593140 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___snd__h601076[56:5] :
_theResult___sfd__h601811 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9982 =
(guard__h593140 == 2'b0) ?
_theResult___snd__h601076[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h601811 :
_theResult___snd__h601076[56:5]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4629 =
(guard__h357330 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h365378 :
_theResult___exp__h365820 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4631 =
(guard__h357330 == 2'b0) ?
_theResult___fst_exp__h365378 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h365820 :
_theResult___fst_exp__h365378) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5023 =
(guard__h375096 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h383173 :
_theResult___exp__h383640 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5025 =
(guard__h375096 == 2'b0) ?
_theResult___fst_exp__h383173 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h383640 :
_theResult___fst_exp__h383173) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5073 =
(guard__h357330 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___snd__h365329[56:34] :
_theResult___sfd__h365821 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5075 =
(guard__h357330 == 2'b0) ?
_theResult___snd__h365329[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h365821 :
_theResult___snd__h365329[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5119 =
(guard__h375096 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___snd__h383119[56:34] :
_theResult___sfd__h383641 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5121 =
(guard__h375096 == 2'b0) ?
_theResult___snd__h383119[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h383641 :
_theResult___snd__h383119[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6021 =
(guard__h403027 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h411075 :
_theResult___exp__h411517 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6023 =
(guard__h403027 == 2'b0) ?
_theResult___fst_exp__h411075 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h411517 :
_theResult___fst_exp__h411075) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6415 =
(guard__h420793 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h428870 :
_theResult___exp__h429337 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6417 =
(guard__h420793 == 2'b0) ?
_theResult___fst_exp__h428870 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h429337 :
_theResult___fst_exp__h428870) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6465 =
(guard__h403027 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___snd__h411026[56:34] :
_theResult___sfd__h411518 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6467 =
(guard__h403027 == 2'b0) ?
_theResult___snd__h411026[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h411518 :
_theResult___snd__h411026[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6511 =
(guard__h420793 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___snd__h428816[56:34] :
_theResult___sfd__h429338 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6513 =
(guard__h420793 == 2'b0) ?
_theResult___snd__h428816[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h429338 :
_theResult___snd__h428816[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7413 =
(guard__h448722 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h456770 :
_theResult___exp__h457212 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7415 =
(guard__h448722 == 2'b0) ?
_theResult___fst_exp__h456770 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h457212 :
_theResult___fst_exp__h456770) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7807 =
(guard__h466488 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h474565 :
_theResult___exp__h475032 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7809 =
(guard__h466488 == 2'b0) ?
_theResult___fst_exp__h474565 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h475032 :
_theResult___fst_exp__h474565) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7857 =
(guard__h448722 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___snd__h456721[56:34] :
_theResult___sfd__h457213 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7859 =
(guard__h448722 == 2'b0) ?
_theResult___snd__h456721[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h457213 :
_theResult___snd__h456721[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7903 =
(guard__h466488 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___snd__h474511[56:34] :
_theResult___sfd__h475033 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7905 =
(guard__h466488 == 2'b0) ?
_theResult___snd__h474511[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h475033 :
_theResult___snd__h474511[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10019 =
(_theResult___fst_exp__h582720 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard74759_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10046 =
(_theResult___fst_exp__h601130 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard93140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10582 =
(_theResult___fst_exp__h561826 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard53836_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10788 =
(_theResult___fst_exp__h543416 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard35455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10815 =
(_theResult___fst_exp__h561826 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard53836_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9097 =
(_theResult___fst_exp__h522973 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard14983_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 =
(_theResult___fst_exp__h601130 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard93140_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ;
assign IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002 =
(_theResult____h655256 == 16'd0 &&
(csrf_prv_reg == 2'd0 ||
csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ?
enabled_ints__h655828 :
_theResult____h655256 ;
assign IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13220 =
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15] ||
checkForException___d13178[4] ||
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13213 ||
fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13922 =
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15] ||
checkForException___d13178[4] ||
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13676 ;
assign IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13959 =
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15] ||
checkForException___d13864[4] ||
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13957 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049 =
(f3_exp__h563473 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10019) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10021) :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10048 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10050 =
(f3_exp__h563473 == 8'd255 && f3_sfd__h563474 != 23'd0 ||
(f3_exp__h563473 == 8'd255 || f3_exp__h563473 == 8'd0) &&
f3_sfd__h563474 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10195 =
((f2_exp__h524169 == 8'd0) ?
(f2_sfd__h524170[22] ?
6'd2 :
(f2_sfd__h524170[21] ?
6'd3 :
(f2_sfd__h524170[20] ?
6'd4 :
(f2_sfd__h524170[19] ?
6'd5 :
(f2_sfd__h524170[18] ?
6'd6 :
(f2_sfd__h524170[17] ?
6'd7 :
(f2_sfd__h524170[16] ?
6'd8 :
(f2_sfd__h524170[15] ?
6'd9 :
(f2_sfd__h524170[14] ?
6'd10 :
(f2_sfd__h524170[13] ?
6'd11 :
(f2_sfd__h524170[12] ?
6'd12 :
(f2_sfd__h524170[11] ?
6'd13 :
(f2_sfd__h524170[10] ?
6'd14 :
(f2_sfd__h524170[9] ?
6'd15 :
(f2_sfd__h524170[8] ?
6'd16 :
(f2_sfd__h524170[7] ?
6'd17 :
(f2_sfd__h524170[6] ?
6'd18 :
(f2_sfd__h524170[5] ?
6'd19 :
(f2_sfd__h524170[4] ?
6'd20 :
(f2_sfd__h524170[3] ?
6'd21 :
(f2_sfd__h524170[2] ?
6'd22 :
(f2_sfd__h524170[1] ?
6'd23 :
(f2_sfd__h524170[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10586 =
(f2_exp__h524169 == 8'd255 && f2_sfd__h524170 != 23'd0 ||
(f2_exp__h524169 == 8'd255 || f2_exp__h524169 == 8'd0) &&
f2_sfd__h524170 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((f2_exp__h524169 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10241 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10584) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 =
(f2_exp__h524169 == 8'd255 && f2_sfd__h524170 != 23'd0) ?
_theResult___snd_fst_sfd__h524485 :
_theResult___fst_sfd__h562625 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10764 =
{ (f2_exp__h524169 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h562621,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 } ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818 =
(f2_exp__h524169 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10788) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10790) :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10817 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10819 =
(f2_exp__h524169 == 8'd255 && f2_sfd__h524170 != 23'd0 ||
(f2_exp__h524169 == 8'd255 || f2_exp__h524169 == 8'd0) &&
f2_sfd__h524170 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10874 =
(f1_exp__h485175 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10853[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10870[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10915 =
(f2_exp__h524169 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10894[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10911[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10959 =
(f3_exp__h563473 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10938[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10955[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10974 =
(f1_exp__h485175 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10853[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10870[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10984 =
(f2_exp__h524169 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10894[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10911[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10995 =
(f3_exp__h563473 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10938[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10955[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11014 =
(f1_exp__h485175 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10853[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11012 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11028 =
(f2_exp__h524169 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10894[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11026 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11043 =
(f3_exp__h563473 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10938[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11041 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11060 =
(f1_exp__h485175 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10853[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11058 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11072 =
(f2_exp__h524169 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10894[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11070 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11085 =
(f3_exp__h563473 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10938[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11083 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11102 =
(f1_exp__h485175 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10853[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11100 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11114 =
(f2_exp__h524169 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10894[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11112 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11127 =
(f3_exp__h563473 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10938[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11125 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8695 =
((f1_exp__h485175 == 8'd0) ?
(f1_sfd__h485176[22] ?
6'd2 :
(f1_sfd__h485176[21] ?
6'd3 :
(f1_sfd__h485176[20] ?
6'd4 :
(f1_sfd__h485176[19] ?
6'd5 :
(f1_sfd__h485176[18] ?
6'd6 :
(f1_sfd__h485176[17] ?
6'd7 :
(f1_sfd__h485176[16] ?
6'd8 :
(f1_sfd__h485176[15] ?
6'd9 :
(f1_sfd__h485176[14] ?
6'd10 :
(f1_sfd__h485176[13] ?
6'd11 :
(f1_sfd__h485176[12] ?
6'd12 :
(f1_sfd__h485176[11] ?
6'd13 :
(f1_sfd__h485176[10] ?
6'd14 :
(f1_sfd__h485176[9] ?
6'd15 :
(f1_sfd__h485176[8] ?
6'd16 :
(f1_sfd__h485176[7] ?
6'd17 :
(f1_sfd__h485176[6] ?
6'd18 :
(f1_sfd__h485176[5] ?
6'd19 :
(f1_sfd__h485176[4] ?
6'd20 :
(f1_sfd__h485176[3] ?
6'd21 :
(f1_sfd__h485176[2] ?
6'd22 :
(f1_sfd__h485176[1] ?
6'd23 :
(f1_sfd__h485176[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9101 =
(f1_exp__h485175 == 8'd255 && f1_sfd__h485176 != 23'd0 ||
(f1_exp__h485175 == 8'd255 || f1_exp__h485175 == 8'd0) &&
f1_sfd__h485176 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((f1_exp__h485175 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8756 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9099) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284 =
(f1_exp__h485175 == 8'd255 && f1_sfd__h485176 != 23'd0) ?
_theResult___snd_fst_sfd__h485491 :
_theResult___fst_sfd__h523772 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9285 =
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9101,
(f1_exp__h485175 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h523768,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284 } ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9425 =
((f3_exp__h563473 == 8'd0) ?
(f3_sfd__h563474[22] ?
6'd2 :
(f3_sfd__h563474[21] ?
6'd3 :
(f3_sfd__h563474[20] ?
6'd4 :
(f3_sfd__h563474[19] ?
6'd5 :
(f3_sfd__h563474[18] ?
6'd6 :
(f3_sfd__h563474[17] ?
6'd7 :
(f3_sfd__h563474[16] ?
6'd8 :
(f3_sfd__h563474[15] ?
6'd9 :
(f3_sfd__h563474[14] ?
6'd10 :
(f3_sfd__h563474[13] ?
6'd11 :
(f3_sfd__h563474[12] ?
6'd12 :
(f3_sfd__h563474[11] ?
6'd13 :
(f3_sfd__h563474[10] ?
6'd14 :
(f3_sfd__h563474[9] ?
6'd15 :
(f3_sfd__h563474[8] ?
6'd16 :
(f3_sfd__h563474[7] ?
6'd17 :
(f3_sfd__h563474[6] ?
6'd18 :
(f3_sfd__h563474[5] ?
6'd19 :
(f3_sfd__h563474[4] ?
6'd20 :
(f3_sfd__h563474[3] ?
6'd21 :
(f3_sfd__h563474[2] ?
6'd22 :
(f3_sfd__h563474[1] ?
6'd23 :
(f3_sfd__h563474[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9816 =
(f3_exp__h563473 == 8'd255 && f3_sfd__h563474 != 23'd0 ||
(f3_exp__h563473 == 8'd255 || f3_exp__h563473 == 8'd0) &&
f3_sfd__h563474 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((f3_exp__h563473 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9471 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9814) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 =
(f3_exp__h563473 == 8'd255 && f3_sfd__h563474 != 23'd0) ?
_theResult___snd_fst_sfd__h563789 :
_theResult___fst_sfd__h601929 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9994 =
{ (f3_exp__h563473 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h601925,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 } ;
assign IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1876 =
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1865 ?
4'd11 :
(IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1869 ?
4'd12 :
(IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1873 ?
4'd13 :
4'd15)) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1878 =
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1857 ?
4'd8 :
(IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1861 ?
4'd9 :
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1876) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1880 =
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1849 ?
4'd6 :
(IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1853 ?
4'd7 :
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1878) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1882 =
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1841 ?
4'd4 :
(IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1845 ?
4'd5 :
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1880) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1884 =
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1833 ?
4'd2 :
(IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1837 ?
4'd3 :
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1882) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1886 =
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1825 ?
4'd0 :
(IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1829 ?
4'd1 :
IF_IF_coreFix_memExe_dTlb_procResp__741_BIT_11_ETC___d1884) ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13366 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd12 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd12) ?
4'd13 :
4'd15 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13367 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd11 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd11) ?
4'd12 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13366 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13368 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd10 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd10) ?
4'd11 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13367 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13369 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd9 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd9) ?
4'd9 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13368 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13370 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd8 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd8) ?
4'd8 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13369 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13371 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd7 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd7) ?
4'd7 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13370 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13372 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd6 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd6) ?
4'd6 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13371 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13373 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd5 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd5) ?
4'd5 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13372 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13374 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd4 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd4) ?
4'd4 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13373 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13375 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd3 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd3) ?
4'd3 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13374 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13376 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd2 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd2) ?
4'd2 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13375 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13377 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd1 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd1) ?
4'd1 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13376 ;
assign IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13378 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 ==
4'd0 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 ==
4'd0) ?
4'd0 :
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13377 ;
assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 =
{ (mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd1) ?
2'd1 :
((mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd2) ?
2'd2 :
2'd3),
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[75:72] :
mmio_cRqQ_enqReq_rl[75:72] } ;
assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172 =
{ (mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd1) ?
2'd1 :
((mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd2) ?
2'd2 :
2'd3),
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[75:72] :
mmio_dataReqQ_enqReq_rl[75:72] } ;
assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766 =
{ (EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd1 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd1) ?
2'd1 :
((EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd2 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd2) ?
2'd2 :
2'd3),
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[35:32] :
mmio_pRqQ_enqReq_rl[35:32] } ;
assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 =
(EN_mmioToPlatform_pRs_enq ?
!mmio_pRsQ_enqReq_lat_0$wget[66] :
!mmio_pRsQ_enqReq_rl[66]) ?
{ EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[65] :
mmio_pRsQ_enqReq_rl[65],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[64:33] :
mmio_pRsQ_enqReq_rl[64:33],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[32] :
mmio_pRsQ_enqReq_rl[32],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[31:0] :
mmio_pRsQ_enqReq_rl[31:0] } :
{ 1'h0,
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[64:0] :
mmio_pRsQ_enqReq_rl[64:0] } ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10241 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 ||
_theResult___fst_exp__h543416 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard35455_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8756 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 ||
_theResult___fst_exp__h504563 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard96602_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9471 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 ||
_theResult___fst_exp__h582720 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard74759_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ;
assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 =
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] ?
4'd0 :
(IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] ?
4'd1 :
((IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2]) ?
4'd2 :
((IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3]) ?
4'd3 :
((IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4]) ?
4'd4 :
((IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6]) ?
4'd5 :
((IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7]) ?
4'd6 :
((IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8]) ?
4'd7 :
((IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10]) ?
4'd8 :
((IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13]) ?
4'd9 :
4'd10))))))))) ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12405 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12373) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12386 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12406 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12373) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12386)) ?
coreFix_aluExe_0_bypassWire_2$whas &&
coreFix_aluExe_0_bypassWire_2_wget__2392_BITS__ETC___d12394 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12405 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12407 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2370_2_ETC___d12397 ?
coreFix_aluExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3_wget__2399_BITS__ETC___d12401 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12406 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12432 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12414) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12420 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12433 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12414) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12420)) ?
coreFix_aluExe_0_bypassWire_2$whas &&
coreFix_aluExe_0_bypassWire_2_wget__2392_BITS__ETC___d12424 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12432 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12434 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2370_2_ETC___d12427 ?
coreFix_aluExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3_wget__2399_BITS__ETC___d12428 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12433 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12620 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12373) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12621 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12373) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12386)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12620 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12629 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12414) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12630 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12414) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12420)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12629 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11546 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11514) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11527 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11547 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11514) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11527)) ?
coreFix_aluExe_1_bypassWire_2$whas &&
coreFix_aluExe_1_bypassWire_2_wget__1533_BITS__ETC___d11535 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11546 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11548 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1511_1_ETC___d11538 ?
coreFix_aluExe_1_bypassWire_3$whas &&
coreFix_aluExe_1_bypassWire_3_wget__1540_BITS__ETC___d11542 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11547 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11573 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11555) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11561 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11574 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11555) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11561)) ?
coreFix_aluExe_1_bypassWire_2$whas &&
coreFix_aluExe_1_bypassWire_2_wget__1533_BITS__ETC___d11565 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11573 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11575 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1511_1_ETC___d11568 ?
coreFix_aluExe_1_bypassWire_3$whas &&
coreFix_aluExe_1_bypassWire_3_wget__1540_BITS__ETC___d11569 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11574 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11946 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11514) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11947 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11514) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11527)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11946 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11955 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11555) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11956 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11555) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11561)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11955 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8304) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8317 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8304) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8317)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8325 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8338 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8328 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8332 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8362 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8344) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8350 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8363 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8344) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8350)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8354 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8362 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8364 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8357 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8358 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8363 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8388 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8370) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8376 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8389 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8370) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8376)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8380 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8388 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8390 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8383 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8384 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8389 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8304) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8455 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8304) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8317)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8344) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8463 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8344) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8350)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8370) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8471 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8370) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8376)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1620 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1601 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1621 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1601)) ?
coreFix_memExe_bypassWire_2$whas &&
coreFix_memExe_bypassWire_2_wget__607_BITS_70__ETC___d1609 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1620 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1622 =
NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1612 ?
coreFix_memExe_bypassWire_3$whas &&
coreFix_memExe_bypassWire_3_wget__614_BITS_70__ETC___d1616 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1621 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1646 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1634 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1647 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1634)) ?
coreFix_memExe_bypassWire_2$whas &&
coreFix_memExe_bypassWire_2_wget__607_BITS_70__ETC___d1638 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1646 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1648 =
NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1641 ?
coreFix_memExe_bypassWire_3$whas &&
coreFix_memExe_bypassWire_3_wget__614_BITS_70__ETC___d1642 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1647 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1679 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1680 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1601)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1679 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1687 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1688 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1634)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1687 ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2115 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) ?
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2087 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2113 ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2132 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125) ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2539 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) ?
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2173,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2529 } :
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
4'd2 } :
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 =
(!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb$procResp[12]) ?
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q21 :
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 ;
assign IF_NOT_fetchStage_pipelines_0_canDeq__2930_293_ETC___d14074 =
((!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13640) &&
fetchStage$pipelines_1_canDeq) ?
fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
IF_fetchStage_RDY_pipelines_1_first__2940_AND__ETC___d14071 :
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first ;
assign IF_NOT_fetchStage_pipelines_0_canDeq__2930_293_ETC___d14082 =
((!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13640) &&
fetchStage$pipelines_1_canDeq) ?
IF_NOT_fetchStage_pipelines_1_first__2941_BITS_ETC___d14081 :
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14079 ;
assign IF_NOT_fetchStage_pipelines_1_first__2941_BITS_ETC___d13997 =
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) ?
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d13980 :
((fetchStage$pipelines_1_first[194:192] == 3'd2) ?
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(regRenamingTable_rename_0_canRename__3582_AND__ETC___d13989 ||
NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13967) :
_0_OR_NOT_fetchStage_pipelines_1_first__2941_BI_ETC___d13995) ;
assign IF_NOT_fetchStage_pipelines_1_first__2941_BITS_ETC___d14081 =
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d13905 ?
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 :
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14079 ;
assign IF_NOT_renameStage_rg_m_halt_req_2959_BIT_4_29_ETC___d13451 =
NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d13270 ?
IF_IF_fetchStage_pipelines_0_first__2932_BIT_6_ETC___d13378 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd0 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd0) ?
4'd0 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd1 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd1) ?
4'd1 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd3 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd2) ?
4'd3 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd4 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd3) ?
4'd4 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd5 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd4) ?
4'd5 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd7 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd5) ?
4'd7 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd8 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd6) ?
4'd8 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd9 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd7) ?
4'd9 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd11 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd8) ?
4'd11 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd14 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3__ETC___d13411 ==
4'd9) ?
4'd14 :
4'd15)))))))))) ;
assign IF_NOT_rob_deqPort_1_deq_data__5517_BIT_25_551_ETC___d15829 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[257:253] == 5'd0 ||
rob$deqPort_1_deq_data[257:253] == 5'd21 ||
rob$deqPort_1_deq_data[257:253] == 5'd17 ||
rob$deqPort_1_deq_data[257:253] == 5'd18 ||
rob$deqPort_1_deq_data[257:253] == 5'd13 ||
rob$deqPort_1_deq_data[257:253] == 5'd16 ||
rob$deqPort_1_deq_data[257:253] == 5'd15 ||
rob$deqPort_1_deq_data[257:253] == 5'd19 ||
rob$deqPort_1_deq_data[257:253] == 5'd20) ?
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] :
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ||
rob$deqPort_1_deq_data[26] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10048 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10034 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10046) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10021 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10543 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10584 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10536 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10582) :
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10817 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10803 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10815) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10790 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11012 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10870[2] :
_theResult___fst_exp__h523756 == 11'd2047 &&
_theResult___fst_sfd__h523757 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11026 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10911[2] :
_theResult___fst_exp__h562609 == 11'd2047 &&
_theResult___fst_sfd__h562610 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11041 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10955[2] :
_theResult___fst_exp__h601913 == 11'd2047 &&
_theResult___fst_sfd__h601914 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11058 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10870[1] :
_theResult___fst_exp__h522973 == 11'd0 &&
guard__h514983 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11070 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10911[1] :
_theResult___fst_exp__h561826 == 11'd0 &&
guard__h553836 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11083 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10955[1] :
_theResult___fst_exp__h601130 == 11'd0 &&
guard__h593140 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11100 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10870[0] :
_theResult___fst_exp__h522973 != 11'd2047 &&
guard__h514983 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11112 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10911[0] :
_theResult___fst_exp__h561826 != 11'd2047 &&
guard__h553836 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11125 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10955[0] :
_theResult___fst_exp__h601130 != 11'd2047 &&
guard__h593140 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9058 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9099 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9051 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9097) :
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9773 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9814 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9766 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812) :
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4969 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5196 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 ?
((_theResult___fst_exp__h374488 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5181) :
((_theResult___fst_exp__h383173 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5194) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5233 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 ?
((_theResult___fst_exp__h374488 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5224) :
((_theResult___fst_exp__h383173 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5231) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5324 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5295[2] :
_theResult___fst_exp__h383721 == 8'd255 &&
_theResult___fst_sfd__h383722 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5337 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5295[1] :
_theResult___fst_exp__h383173 == 8'd0 &&
guard__h375096 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5350 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5295[0] :
_theResult___fst_exp__h383173 != 8'd255 &&
guard__h375096 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6361 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6588 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 ?
((_theResult___fst_exp__h420185 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6573) :
((_theResult___fst_exp__h428870 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6586) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6625 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 ?
((_theResult___fst_exp__h420185 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6616) :
((_theResult___fst_exp__h428870 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6623) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6716 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6687[2] :
_theResult___fst_exp__h429418 == 8'd255 &&
_theResult___fst_sfd__h429419 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6729 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6687[1] :
_theResult___fst_exp__h428870 == 8'd0 &&
guard__h420793 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6742 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6687[0] :
_theResult___fst_exp__h428870 != 8'd255 &&
guard__h420793 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7753 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7980 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 ?
((_theResult___fst_exp__h465880 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7965) :
((_theResult___fst_exp__h474565 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7978) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8017 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 ?
((_theResult___fst_exp__h465880 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8008) :
((_theResult___fst_exp__h474565 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8015) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8108 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8079[2] :
_theResult___fst_exp__h475113 == 8'd255 &&
_theResult___fst_sfd__h475114 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8121 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8079[1] :
_theResult___fst_exp__h474565 == 8'd0 &&
guard__h466488 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8134 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8079[0] :
_theResult___fst_exp__h474565 != 8'd255 &&
guard__h466488 != 2'b0 ;
assign IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327 =
checkForException___d13178[4] ?
CASE_checkForException_3178_BITS_3_TO_0_0_chec_ETC__q234 :
4'd2 ;
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2348_ETC___d12381 =
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12373) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2348_ETC___d12417 =
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12414) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1489_ETC___d11522 =
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11514) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1489_ETC___d11558 =
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11555) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8312 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8304) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8347 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8344) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8373 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8370) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6629 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590) :
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6627) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5967 =
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6558 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6560) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6588 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6560) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6627 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6608 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6625 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6691 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6673 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6687[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6702 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6698 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6687[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6718 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6710 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6716 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6731 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6725 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6729 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6744 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6738 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6742 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4575 =
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5166 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5168) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5196 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5168) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5235 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5216 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5233 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5299 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5281 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5295[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5310 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5306 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5295[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5326 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5318 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5324 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5339 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5333 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5337 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5352 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5346 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5350 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7359 =
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7950 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7952) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7980 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7952) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8019 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d8000 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8017 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8083 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8065 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8079[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8094 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8090 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8079[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8110 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8102 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8108 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8123 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8121 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8136 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8130 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8134 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5237 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198) :
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5235) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8021 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982) :
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8019) ;
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_d_ETC___d11256 =
(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ==
64'd0) ?
64'd1 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10021 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10052 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[75],
coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10050,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9994 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10766 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10586,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10764 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10790 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8542 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4) ?
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8508 &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8521 :
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8541 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9286 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9285 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9996 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9816,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9994 } ;
assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12873 =
coreFix_globalSpecUpdate_correctSpecTag_1$whas ?
result__h650833 :
w__h650828 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2113 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101) ?
NOT_coreFix_memExe_respLrScAmoQ_full_978_979_A_ETC___d2111 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2133 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101) ?
NOT_coreFix_memExe_respLrScAmoQ_full_978_979_A_ETC___d2111 :
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2132 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2136 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2135 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2227 =
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd7) ?
n___1__h200101 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd6) ?
n___1__h200101 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd5) ?
n___1__h200101 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd4) ?
n___1__h200101 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2232 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2227,
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd3) ?
n___1__h200101 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd2) ?
n___1__h200101 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2237 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2232,
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd1) ?
n___1__h200101 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd0) ?
n___1__h200101 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
4'd2,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } :
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125) ?
{ 3'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2552 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0] :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2551 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2568 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
3'd5 :
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125) ?
3'd2 :
3'd3) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2579 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
58'h155555555555554 :
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
2'd0,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
1'd0 } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
53'h15555555555555 }) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2596 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2) ?
x__h198698 :
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179 ?
64'd0 :
64'd1) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3143 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3155 =
_theResult_____2__h299047 == v__h298467 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3235 =
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3250 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ||
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3257 =
_theResult_____2__h307043 == v__h301812 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3277 =
EN_dCacheToParent_fromP_enq ?
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3344 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3235 &&
(EN_dCacheToParent_fromP_enq ?
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582])) ?
{ 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } :
{ EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[581:518] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[581:518],
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[517:516] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[517:516],
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3277 ||
(EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[515] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[515]),
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3],
x__h304677 } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3101 =
!MUX_flush_reservation$write_1__SEL_2 &&
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] :
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3109 =
MUX_flush_reservation$write_1__SEL_2 ?
58'h2AAAAAAAAAAAAAA :
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] :
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0]) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2076 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ?
!coreFix_memExe_respLrScAmoQ_full :
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2078 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2) ?
!coreFix_memExe_respLrScAmoQ_full :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2076 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2079 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0) ?
!coreFix_memExe_memRespLdQ_full :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2078 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2087 =
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2079 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq)) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2135 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056)) ?
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2087 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2133 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2137 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 ?
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2115 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2136 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2173 =
{ (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82]) ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2551 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056)) ?
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2173,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2529 } :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2599 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056)) ?
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2596 } :
65'h10000000000000001 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2779 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775) ?
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry :
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2788 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:512] :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
2'd0 :
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:512] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2024 =
{ (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd7) ?
n__h195496 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd6) ?
n__h195496 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd5) ?
n__h195496 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2029 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2024,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd4) ?
n__h195496 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd3) ?
n__h195496 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2034 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2029,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd2) ?
n__h195496 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd1) ?
n__h195496 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2883 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[83:82] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[83:82]) :
2'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2887 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[81:79] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[81:79]) :
3'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2930 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[6:3] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[6:3]) :
4'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3406 =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3421 =
EN_dCacheToParent_rqToP_deq ||
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3429 =
_theResult_____2__h313037 == v__h312326 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3502 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3517 =
EN_dCacheToParent_rsToP_deq ||
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3525 =
_theResult_____2__h320891 == v__h316202 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3544 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
assign IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 =
(coreFix_memExe_dTlb$procResp[105:103] == 3'd3) ?
4'd7 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1769 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
coreFix_memExe_dTlb$procResp[105:103] != 3'd3 &&
!coreFix_memExe_dTlb$procResp[12] :
!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1825 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd0 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd0 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1829 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd1 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd1 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1833 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd2 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd2 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1837 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd3 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd3 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1841 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd4 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd4 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1845 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd5 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd5 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1849 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd6 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd6 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1853 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd7 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd7 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1857 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd8 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd8 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1861 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd9 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd9 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1865 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd10 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd10 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1869 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd11 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd11 ;
assign IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1873 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__741_BITS_105__ETC___d1821 ==
4'd12 :
IF_NOT_coreFix_memExe_dTlb_procResp__741_BIT_1_ETC___d1820 ==
4'd12 ;
assign IF_coreFix_memExe_dispToRegQ_RDY_first__565_AN_ETC___d1596 =
(coreFix_memExe_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_memExe_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_memExe_dispToRegQ$RDY_first ;
assign IF_coreFix_memExe_dispToRegQ_RDY_first__565_AN_ETC___d1631 =
(coreFix_memExe_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_memExe_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_memExe_dispToRegQ$RDY_first ;
assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3847 =
_theResult_____2__h334460 == v__h334028 ;
assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3840 =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
coreFix_memExe_forwardQ_deqReq_rl ;
assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3825 =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
coreFix_memExe_forwardQ_enqReq_rl[69] ;
assign IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1385 =
coreFix_memExe_lsq$firstLd[94] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 48'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 } :
{ {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367[15]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 }) :
(coreFix_memExe_lsq$firstLd[92] ?
{ 56'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 } :
{ {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381[7]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 }) ;
assign IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 =
coreFix_memExe_lsq$firstLd[94] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 48'd0,
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 } :
{ {48{SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417[15]}},
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 }) :
(coreFix_memExe_lsq$firstLd[92] ?
{ 56'd0,
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 } :
{ {56{SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430[7]}},
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 }) ;
assign IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386 =
coreFix_memExe_lsq$firstLd[96] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 32'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356 } :
{ {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356[31]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356 }) :
IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1385 ;
assign IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435 =
coreFix_memExe_lsq$firstLd[96] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 32'd0,
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 } :
{ {32{SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408[31]}},
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) :
IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ;
assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3753 =
_theResult_____2__h331235 == v__h330803 ;
assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3746 =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
coreFix_memExe_memRespLdQ_deqReq_rl ;
assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3731 =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
coreFix_memExe_memRespLdQ_enqReq_rl[69] ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[83:82] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[83:82]) :
2'd0 ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[81:79] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[81:79]) :
3'd0 ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[6:3] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[6:3]) :
4'd0 ;
assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3655 =
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ;
assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 =
csrf_minstret_ehr_data_lat_0$whas ?
upd__h724191 :
csrf_minstret_ehr_data_rl ;
assign IF_csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_c_ETC___d15130 =
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ?
{ 43'd8192,
csrf_mxr_reg,
csrf_sum_reg,
3'd0,
csrf_fs_reg,
4'b0,
csrf_prv_reg[0],
2'b0,
csrf_ie_vec_1,
csrf_prev_ie_vec_0,
3'd0,
csrf_ie_vec_0 } :
{ 40'd5120,
csrf_tsr_reg,
csrf_tw_reg,
csrf_tvm_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_mprv_reg,
2'd0,
csrf_fs_reg,
csrf_prv_reg,
2'b0,
csrf_spp_reg,
csrf_ie_vec_3,
1'b0,
csrf_prev_ie_vec_1,
csrf_prev_ie_vec_0,
2'd0,
csrf_ie_vec_1,
csrf_ie_vec_0 } ;
assign IF_fetchStage_RDY_pipelines_0_first__2929_AND__ETC___d13610 =
(fetchStage$RDY_pipelines_0_first &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604) ?
fetchStage$RDY_pipelines_0_first :
!regRenamingTable$rename_0_canRename ||
fetchStage$RDY_pipelines_0_first ;
assign IF_fetchStage_RDY_pipelines_1_first__2940_AND__ETC___d13999 =
(fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] == 3'd0 ||
fetchStage$pipelines_1_first[194:192] == 3'd1)) ?
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(SEL_ARR_fetchStage_pipelines_0_canDeq__2930_AN_ETC___d13938 ||
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667 ||
NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13967) :
fetchStage$RDY_pipelines_1_first &&
IF_NOT_fetchStage_pipelines_1_first__2941_BITS_ETC___d13997 ;
assign IF_fetchStage_RDY_pipelines_1_first__2940_AND__ETC___d14071 =
(fetchStage$RDY_pipelines_1_first &&
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d13674 &&
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d13905) ?
IF_fetchStage_RDY_pipelines_1_first__2940_AND__ETC___d13999 &&
(IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) :
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first ;
assign IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14120 =
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14113 ||
rob$RDY_enqPort_0_enq &&
regRenamingTable$RDY_rename_0_claimRename &&
regRenamingTable$RDY_rename_0_getRename &&
fetchStage$RDY_pipelines_0_deq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_claimSpecTag) ;
assign IF_fetchStage_pipelines_0_first__2932_BIT_160__ETC___d14317 =
{ fetchStage$pipelines_0_first[159:128],
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14305,
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14308 ?
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14311 :
{ 1'h0,
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14314 } } ;
assign IF_fetchStage_pipelines_0_first__2932_BIT_173__ETC___d13205 =
fetchStage$pipelines_0_first[173] ?
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143 :
12'hCFF ;
assign IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14250 =
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14207 &&
IF_fetchStage_RDY_pipelines_1_first__2940_AND__ETC___d13999 &&
(IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14234 ||
rob$RDY_enqPort_1_enq &&
regRenamingTable$RDY_rename_1_claimRename &&
regRenamingTable$RDY_rename_1_getRename &&
fetchStage_RDY_pipelines_1_deq__2944_AND_NOT_f_ETC___d14244) ;
assign IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14533 =
(fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14468 &&
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14475) ?
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14476 :
{ 1'h0,
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14477 } ;
assign IF_fetchStage_pipelines_1_first__2941_BIT_160__ETC___d14480 =
{ fetchStage$pipelines_1_first[159:128],
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14474,
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14475 ?
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14476 :
{ 1'h0,
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14477 } } ;
assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[142] :
mmio_cRqQ_enqReq_rl[142] ;
assign IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 =
CAN_FIRE_RL_mmio_handlePRq ?
mmio_cRsQ_enqReq_lat_0$wget[1] :
mmio_cRsQ_enqReq_rl[1] ;
assign IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[142] :
mmio_dataReqQ_enqReq_rl[142] ;
assign IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 =
CAN_FIRE_RL_mmio_sendDataResp ?
mmio_dataRespQ_enqReq_lat_0$wget[65] :
mmio_dataRespQ_enqReq_rl[65] ;
assign IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 =
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[39] :
mmio_pRqQ_enqReq_rl[39] ;
assign IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 =
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[67] :
mmio_pRsQ_enqReq_rl[67] ;
assign IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15817 =
rob$deqPort_0_canDeq ? y_avValue_fst__h727013 : 5'd0 ;
assign IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15838 =
rob$deqPort_0_canDeq ?
y_avValue_snd_snd_snd_fst__h727472 :
2'd0 ;
assign IF_rob_deqPort_0_deq_data__4560_BITS_257_TO_25_ETC___d15475 =
(rob$deqPort_0_deq_data[257:253] == 5'd19) ?
{ 43'd8192,
csrf_mxr_reg,
csrf_sum_reg,
3'd0,
csrf_fs_reg,
8'd1,
csrf_prev_ie_vec_0,
2'b0,
csrf_prev_ie_vec_1,
csrf_ie_vec_0 } :
{ 40'd5120,
csrf_tsr_reg,
csrf_tw_reg,
csrf_tvm_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_mprv_reg,
2'd0,
csrf_fs_reg,
4'd0,
csrf_spp_reg,
2'd2,
csrf_prev_ie_vec_1,
csrf_prev_ie_vec_0,
csrf_prev_ie_vec_3,
1'b0,
csrf_ie_vec_1,
csrf_ie_vec_0 } ;
assign IF_rob_deqPort_0_deq_data__4560_BITS_97_TO_96__ETC___d14724 =
{ CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q246,
rob$deqPort_0_deq_data[95:32] } ;
assign IF_rob_deqPort_1_canDeq__5514_THEN_IF_NOT_rob__ETC___d15830 =
rob$deqPort_1_canDeq ?
IF_NOT_rob_deqPort_1_deq_data__5517_BIT_25_551_ETC___d15829 :
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ;
assign IF_sfdin02413_BIT_33_THEN_2_ELSE_0__q65 =
sfdin__h402413[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin14134_BIT_4_THEN_2_ELSE_0__q139 =
sfdin__h514134[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin20179_BIT_33_THEN_2_ELSE_0__q75 =
sfdin__h420179[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin48108_BIT_33_THEN_2_ELSE_0__q100 =
sfdin__h448108[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin52987_BIT_4_THEN_2_ELSE_0__q179 =
sfdin__h552987[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin56716_BIT_33_THEN_2_ELSE_0__q30 =
sfdin__h356716[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin65874_BIT_33_THEN_2_ELSE_0__q110 =
sfdin__h465874[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin74482_BIT_33_THEN_2_ELSE_0__q40 =
sfdin__h374482[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin92291_BIT_4_THEN_2_ELSE_0__q156 =
sfdin__h592291[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd01076_BIT_4_THEN_2_ELSE_0__q159 =
_theResult___snd__h601076[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd04514_BIT_4_THEN_2_ELSE_0__q135 =
_theResult___snd__h504514[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd11026_BIT_33_THEN_2_ELSE_0__q67 =
_theResult___snd__h411026[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd22919_BIT_4_THEN_2_ELSE_0__q142 =
_theResult___snd__h522919[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd28816_BIT_33_THEN_2_ELSE_0__q80 =
_theResult___snd__h428816[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd43367_BIT_4_THEN_2_ELSE_0__q175 =
_theResult___snd__h543367[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd56721_BIT_33_THEN_2_ELSE_0__q102 =
_theResult___snd__h456721[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd61772_BIT_4_THEN_2_ELSE_0__q182 =
_theResult___snd__h561772[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd65329_BIT_33_THEN_2_ELSE_0__q32 =
_theResult___snd__h365329[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd74511_BIT_33_THEN_2_ELSE_0__q115 =
_theResult___snd__h474511[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd82671_BIT_4_THEN_2_ELSE_0__q152 =
_theResult___snd__h582671[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd83119_BIT_33_THEN_2_ELSE_0__q45 =
_theResult___snd__h383119[33] ? 2'd2 : 2'd0 ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5318 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5266[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5278[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5346 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5266[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5278[0]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6710 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6658[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6670[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6738 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6658[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6670[0]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8102 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8050[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8062[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8130 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8050[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8062[0]) ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13509 =
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15] &&
!checkForException___d13178[4] &&
NOT_csrf_fs_reg_read__1727_EQ_0_3167_3168_OR_N_ETC___d13502 &&
(fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13597 =
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15] &&
!checkForException___d13178[4] &&
NOT_csrf_fs_reg_read__1727_EQ_0_3167_3168_OR_N_ETC___d13595 ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13891 =
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15] &&
!checkForException___d13864[4] &&
NOT_csrf_fs_reg_read__1727_EQ_0_3167_3168_OR_N_ETC___d13889 ;
assign NOT_IF_NOT_rob_deqPort_0_canDeq__5509_5510_OR__ETC___d15835 =
(fflags__h729123 & csrf_fflags_reg) != fflags__h729123 ||
csrf_fs_reg != 2'b11 &&
(IF_rob_deqPort_1_canDeq__5514_THEN_IF_NOT_rob__ETC___d15830 ||
fflags__h729123 != 5'd0) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10168 =
!f2_sfd__h524170[21] && !f2_sfd__h524170[20] &&
!f2_sfd__h524170[19] &&
!f2_sfd__h524170[18] &&
!f2_sfd__h524170[17] &&
!f2_sfd__h524170[16] &&
!f2_sfd__h524170[15] &&
!f2_sfd__h524170[14] &&
!f2_sfd__h524170[13] &&
!f2_sfd__h524170[12] &&
!f2_sfd__h524170[11] &&
!f2_sfd__h524170[10] &&
!f2_sfd__h524170[9] &&
!f2_sfd__h524170[8] &&
!f2_sfd__h524170[7] &&
!f2_sfd__h524170[6] &&
!f2_sfd__h524170[5] &&
!f2_sfd__h524170[4] &&
!f2_sfd__h524170[3] &&
!f2_sfd__h524170[2] &&
!f2_sfd__h524170[1] &&
!f2_sfd__h524170[0] ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10877 =
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 == 23'd0) &&
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 != 23'd0) &&
(f1_exp__h485175 != 8'd0 || f1_sfd__h485176 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10874 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10919 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10877 |
((f2_exp__h524169 != 8'd255 || f2_sfd__h524170 == 23'd0) &&
(f2_exp__h524169 != 8'd255 || f2_sfd__h524170 != 23'd0) &&
(f2_exp__h524169 != 8'd0 || f2_sfd__h524170 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10915) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10977 =
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 == 23'd0) &&
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 != 23'd0) &&
(f1_exp__h485175 != 8'd0 || f1_sfd__h485176 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10974 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10988 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10977 |
((f2_exp__h524169 != 8'd255 || f2_sfd__h524170 == 23'd0) &&
(f2_exp__h524169 != 8'd255 || f2_sfd__h524170 != 23'd0) &&
(f2_exp__h524169 != 8'd0 || f2_sfd__h524170 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10984) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11017 =
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 == 23'd0) &&
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 != 23'd0) &&
(f1_exp__h485175 != 8'd0 || f1_sfd__h485176 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11014 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11032 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11017 |
((f2_exp__h524169 != 8'd255 || f2_sfd__h524170 == 23'd0) &&
(f2_exp__h524169 != 8'd255 || f2_sfd__h524170 != 23'd0) &&
(f2_exp__h524169 != 8'd0 || f2_sfd__h524170 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11028) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11063 =
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 == 23'd0) &&
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 != 23'd0) &&
(f1_exp__h485175 != 8'd0 || f1_sfd__h485176 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11060 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11076 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11063 |
((f2_exp__h524169 != 8'd255 || f2_sfd__h524170 == 23'd0) &&
(f2_exp__h524169 != 8'd255 || f2_sfd__h524170 != 23'd0) &&
(f2_exp__h524169 != 8'd0 || f2_sfd__h524170 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11072) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11105 =
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 == 23'd0) &&
(f1_exp__h485175 != 8'd255 || f1_sfd__h485176 != 23'd0) &&
(f1_exp__h485175 != 8'd0 || f1_sfd__h485176 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11102 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11118 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11105 |
((f2_exp__h524169 != 8'd255 || f2_sfd__h524170 == 23'd0) &&
(f2_exp__h524169 != 8'd255 || f2_sfd__h524170 != 23'd0) &&
(f2_exp__h524169 != 8'd0 || f2_sfd__h524170 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11114) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8668 =
!f1_sfd__h485176[21] && !f1_sfd__h485176[20] &&
!f1_sfd__h485176[19] &&
!f1_sfd__h485176[18] &&
!f1_sfd__h485176[17] &&
!f1_sfd__h485176[16] &&
!f1_sfd__h485176[15] &&
!f1_sfd__h485176[14] &&
!f1_sfd__h485176[13] &&
!f1_sfd__h485176[12] &&
!f1_sfd__h485176[11] &&
!f1_sfd__h485176[10] &&
!f1_sfd__h485176[9] &&
!f1_sfd__h485176[8] &&
!f1_sfd__h485176[7] &&
!f1_sfd__h485176[6] &&
!f1_sfd__h485176[5] &&
!f1_sfd__h485176[4] &&
!f1_sfd__h485176[3] &&
!f1_sfd__h485176[2] &&
!f1_sfd__h485176[1] &&
!f1_sfd__h485176[0] ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9398 =
!f3_sfd__h563474[21] && !f3_sfd__h563474[20] &&
!f3_sfd__h563474[19] &&
!f3_sfd__h563474[18] &&
!f3_sfd__h563474[17] &&
!f3_sfd__h563474[16] &&
!f3_sfd__h563474[15] &&
!f3_sfd__h563474[14] &&
!f3_sfd__h563474[13] &&
!f3_sfd__h563474[12] &&
!f3_sfd__h563474[11] &&
!f3_sfd__h563474[10] &&
!f3_sfd__h563474[9] &&
!f3_sfd__h563474[8] &&
!f3_sfd__h563474[7] &&
!f3_sfd__h563474[6] &&
!f3_sfd__h563474[5] &&
!f3_sfd__h563474[4] &&
!f3_sfd__h563474[3] &&
!f3_sfd__h563474[2] &&
!f3_sfd__h563474[1] &&
!f3_sfd__h563474[0] ;
assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13658 =
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 ;
assign NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14843 =
(!commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] == 4'd0 ||
commitStage_commitTrap[3:0] == 4'd1 ||
commitStage_commitTrap[3:0] == 4'd3 ||
commitStage_commitTrap[3:0] == 4'd4 ||
commitStage_commitTrap[3:0] == 4'd5 ||
commitStage_commitTrap[3:0] == 4'd7 ||
commitStage_commitTrap[3:0] == 4'd8 ||
commitStage_commitTrap[3:0] == 4'd9 ||
commitStage_commitTrap[3:0] == 4'd11) &&
(commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] != 4'd3 ||
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ;
assign NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14850 =
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14843 ||
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq ;
assign NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 =
(!commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] != 4'd14) &&
(!commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] == 4'd0 ||
commitStage_commitTrap[3:0] == 4'd1 ||
commitStage_commitTrap[3:0] == 4'd3 ||
commitStage_commitTrap[3:0] == 4'd4 ||
commitStage_commitTrap[3:0] == 4'd5 ||
commitStage_commitTrap[3:0] == 4'd7 ||
commitStage_commitTrap[3:0] == 4'd8 ||
commitStage_commitTrap[3:0] == 4'd9 ||
commitStage_commitTrap[3:0] == 4'd11 ||
commitStage_commitTrap[3:0] == 4'd14) &&
(commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] != 4'd3 ||
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ;
assign NOT_commitStage_rg_run_state_4566_4567_AND_NOT_ETC___d15210 =
!commitStage_rg_run_state && !commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
rob$deqPort_0_deq_data[25] ;
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2370_2_ETC___d12397 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12373) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12386) &&
(!coreFix_aluExe_0_bypassWire_2$whas ||
!coreFix_aluExe_0_bypassWire_2_wget__2392_BITS__ETC___d12394) ;
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2370_2_ETC___d12427 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12414) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12420) &&
(!coreFix_aluExe_0_bypassWire_2$whas ||
!coreFix_aluExe_0_bypassWire_2_wget__2392_BITS__ETC___d12424) ;
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1511_1_ETC___d11538 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11514) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11527) &&
(!coreFix_aluExe_1_bypassWire_2$whas ||
!coreFix_aluExe_1_bypassWire_2_wget__1533_BITS__ETC___d11535) ;
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1511_1_ETC___d11568 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11555) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11561) &&
(!coreFix_aluExe_1_bypassWire_2$whas ||
!coreFix_aluExe_1_bypassWire_2_wget__1533_BITS__ETC___d11565) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8328 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8304) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8317) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8325) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8357 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8344) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8350) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8354) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8383 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8370) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8376) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8380) ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5912 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4520 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7304 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8541 =
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 ||
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q267 ;
assign NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1612 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1601) &&
(!coreFix_memExe_bypassWire_2$whas ||
!coreFix_memExe_bypassWire_2_wget__607_BITS_70__ETC___d1609) ;
assign NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1641 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1634) &&
(!coreFix_memExe_bypassWire_2$whas ||
!coreFix_memExe_bypassWire_2_wget__607_BITS_70__ETC___d1638) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2555 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2731 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3154 =
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3175 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3])) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3143 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3224 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3280 =
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3277) &&
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3250 ||
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101 =
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2099 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2152 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2562 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2564 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2562) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2586 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2590 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2593 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2589 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2590) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2607 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2606 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2610 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2589 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2607) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2621 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2627 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2590) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2659 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2667 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2675 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2684 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd0 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2726 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd0 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2740 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2738 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2748 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ||
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2079 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq)) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2816 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd1 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] <=
2'd1 ||
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] !=
2'd0 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd3 ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot[0]) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141 =
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3395 =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3452 =
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72])) &&
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3421 ||
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3491 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3548 =
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3544) &&
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3517 ||
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ;
assign NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1909 =
!coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1953 =
(!coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_enqReq_rl[4]) &&
(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_deqReq_rl ||
coreFix_memExe_dMem_perfReqQ_empty) ;
assign NOT_coreFix_memExe_dTlb_procResp__741_BITS_174_ETC___d1780 =
!coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1751 &&
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1752 &&
!coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1756 &&
!coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1759 ;
assign NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3814 =
!coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_forwardQ_clearReq_rl ;
assign NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3869 =
(!coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
!coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
!coreFix_memExe_forwardQ_enqReq_rl[69])) &&
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3840 ||
coreFix_memExe_forwardQ_empty) ;
assign NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3720 =
!coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_memRespLdQ_clearReq_rl ;
assign NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3775 =
(!coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
!coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
!coreFix_memExe_memRespLdQ_enqReq_rl[69])) &&
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3746 ||
coreFix_memExe_memRespLdQ_empty) ;
assign NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1487 =
!coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqLdQ_full_rl ;
assign NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1026 =
!coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_rl ;
assign NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3644 =
!coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_respLrScAmoQ_clearReq_rl ;
assign NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3686 =
(!coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
!coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
!coreFix_memExe_respLrScAmoQ_enqReq_rl[64])) &&
(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT &&
(coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ||
coreFix_memExe_respLrScAmoQ_deqReq_rl) ||
coreFix_memExe_respLrScAmoQ_empty) ;
assign NOT_coreFix_memExe_respLrScAmoQ_full_978_979_A_ETC___d2111 =
!coreFix_memExe_respLrScAmoQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ;
assign NOT_csrf_fs_reg_read__1727_EQ_0_3167_3168_OR_N_ETC___d13502 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_0_first[95] ||
!fetchStage$pipelines_0_first[94]) &&
(!fetchStage$pipelines_0_first[88] ||
!fetchStage$pipelines_0_first[87]) &&
!fetchStage$pipelines_0_first[81] &&
(!fetchStage$pipelines_0_first[75] ||
!fetchStage$pipelines_0_first[74])) &&
(fetchStage$pipelines_0_first[199:195] != 5'd13 ||
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13498 &&
!csrf_prv_reg_read__2962_ULT_IF_fetchStage_pipe_ETC___d13210) ;
assign NOT_csrf_fs_reg_read__1727_EQ_0_3167_3168_OR_N_ETC___d13595 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_0_first[95] ||
!fetchStage$pipelines_0_first[94]) &&
(!fetchStage$pipelines_0_first[88] ||
!fetchStage$pipelines_0_first[87]) &&
!fetchStage$pipelines_0_first[81] &&
(!fetchStage$pipelines_0_first[75] ||
!fetchStage$pipelines_0_first[74])) &&
(fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_csrf_fs_reg_read__1727_EQ_0_3167_3168_OR_N_ETC___d13889 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_1_first[95] ||
!fetchStage$pipelines_1_first[94]) &&
(!fetchStage$pipelines_1_first[88] ||
!fetchStage$pipelines_1_first[87]) &&
!fetchStage$pipelines_1_first[81] &&
(!fetchStage$pipelines_1_first[75] ||
!fetchStage$pipelines_1_first[74])) &&
(fetchStage$pipelines_1_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_csrf_prv_reg_read__2962_ULE_1_4914_4955_OR_ETC___d14959 =
!csrf_prv_reg_read__2962_ULE_1___d14914 ||
(commitStage_commitTrap[4] ?
!_0b0_CONCAT_csrf_mideleg_11_reg_read__1840_1841_ETC___d14916 :
!_0b0_CONCAT_csrf_medeleg_15_reg_read__1832_1833_ETC___d14934) ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d13701 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2932_BITS_199_TO_ETC___d13683 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13698 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d13936 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13927 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d13980 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13967) ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14035 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2932_BITS_199_TO_ETC___d13683 ||
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14053 =
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14003 ||
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693) &&
coreFix_memExe_rsMem$canEnq &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14202 =
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14173) &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 &&
(fetchStage$pipelines_1_first[199:195] == 5'd14 ||
coreFix_memExe_rsMem$RDY_enq) ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14256 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14122 &&
IF_fetchStage_RDY_pipelines_0_first__2929_AND__ETC___d13610) &&
fetchStage$RDY_pipelines_0_first &&
fetchStage_pipelines_0_canDeq__2930_AND_fetchS_ETC___d14254 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14385 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14380 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 =
(!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13639) &&
fetchStage$pipelines_1_canDeq ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14392 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14086 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13698 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14404 =
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d14401 &&
(fetchStage$pipelines_1_first[194:192] == 3'd0 ||
fetchStage$pipelines_1_first[194:192] == 3'd1) &&
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14168 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14440 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14086 ||
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14460 =
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14440 &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
NOT_fetchStage_pipelines_1_first__2941_BITS_32_ETC___d14455 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14467 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14086 ||
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14468 =
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14467 &&
coreFix_memExe_rsMem$canEnq &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ;
assign NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14512 =
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14392 &&
specTagManager$canClaim &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 &&
fetchStage$pipelines_1_first[194:192] == 3'd1 ;
assign NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13498 =
(fetchStage$pipelines_0_first[194:192] != 3'd0 ||
fetchStage$pipelines_0_first[178:174] != 5'd15) &&
rs1__h659435 == 5'd0 &&
imm__h659436 == 32'd0 ||
IF_fetchStage_pipelines_0_first__2932_BIT_173__ETC___d13205[11:10] !=
2'b11 ;
assign NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13640 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13639 ;
assign NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13912 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 &&
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d13911 ;
assign NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13918 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 &&
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 &&
(!coreFix_aluExe_0_rsAlu$canEnq ||
!coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619) ;
assign NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14079 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ;
assign NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq ;
assign NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14363 =
{ fetchStage$pipelines_0_first[194:192] != 3'd2 ||
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14305,
(fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14308) ?
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14311 :
{ 1'h0,
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14314 },
7'd32,
specTagManager$currentSpecBits } ;
assign NOT_fetchStage_pipelines_0_first__2932_BITS_32_ETC___d14287 =
fetchStage$pipelines_0_first[323:260] !=
fallthrough_pc__h668411 ;
assign NOT_fetchStage_pipelines_0_first__2932_BIT_68__ETC___d13651 =
!fetchStage$pipelines_0_first[68] &&
!checkForException___d13178[4] &&
NOT_csrf_fs_reg_read__1727_EQ_0_3167_3168_OR_N_ETC___d13595 &&
rob$enqPort_0_canEnq &&
epochManager$checkEpoch_0_check ;
assign NOT_fetchStage_pipelines_1_canDeq__2938_2939_O_ETC___d12947 =
!fetchStage$pipelines_1_canDeq ||
fetchStage$RDY_pipelines_1_first &&
(epochManager$checkEpoch_1_check ||
fetchStage$RDY_pipelines_1_deq) ;
assign NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d13674 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(fetchStage$RDY_pipelines_0_first &&
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667 ||
csrf_rg_dcsr_read__1900_BIT_2_3230_OR_NOT_fetc_ETC___d13672) ;
assign NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d13905 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d13701 &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d13904 ;
assign NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d14022 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14003 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14016 ||
fetchStage$pipelines_0_first[194:192] != 3'd1) &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d13904 ;
assign NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d14401 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14392 &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 ;
assign NOT_fetchStage_pipelines_1_first__2941_BITS_32_ETC___d14455 =
fetchStage$pipelines_1_first[323:260] !=
fallthrough_pc__h683886 ;
assign NOT_fetchStage_pipelines_1_first__2941_BIT_68__ETC___d14398 =
!fetchStage$pipelines_1_first[68] &&
!checkForException___d13864[4] &&
NOT_csrf_fs_reg_read__1727_EQ_0_3167_3168_OR_N_ETC___d13889 &&
rob$enqPort_1_canEnq &&
epochManager$checkEpoch_1_check &&
!csrf_rg_dcsr[2] ;
assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 =
!mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ;
assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 =
(!mmio_cRqQ_enqReq_dummy2_2$Q_OUT ||
(mmio_cRqQ_enqReq_lat_0$whas ?
!mmio_cRqQ_enqReq_lat_0$wget[142] :
!mmio_cRqQ_enqReq_rl[142])) &&
(mmio_cRqQ_deqReq_dummy2_2$Q_OUT &&
(EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl) ||
mmio_cRqQ_empty) ;
assign NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 =
!mmio_cRsQ_clearReq_dummy2_1$Q_OUT || !mmio_cRsQ_clearReq_rl ;
assign NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 =
(!mmio_cRsQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_mmio_handlePRq ?
!mmio_cRsQ_enqReq_lat_0$wget[1] :
!mmio_cRsQ_enqReq_rl[1])) &&
(mmio_cRsQ_deqReq_dummy2_2$Q_OUT &&
(EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl) ||
mmio_cRsQ_empty) ;
assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 =
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt ;
assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 =
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd ;
assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 =
(!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT ||
!mmio_dataPendQ_enqReq_lat_0$whas &&
!mmio_dataPendQ_enqReq_rl) &&
(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT &&
(mmio_dataRespQ_deqReq_lat_0$whas ||
mmio_dataPendQ_deqReq_rl) ||
mmio_dataPendQ_empty) ;
assign NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 =
!mmio_dataReqQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataReqQ_clearReq_rl ;
assign NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 =
(!mmio_dataReqQ_enqReq_dummy2_2$Q_OUT ||
(mmio_dataReqQ_enqReq_lat_0$whas ?
!mmio_dataReqQ_enqReq_lat_0$wget[142] :
!mmio_dataReqQ_enqReq_rl[142])) &&
(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl) ||
mmio_dataReqQ_empty) ;
assign NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 =
!mmio_dataRespQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataRespQ_clearReq_rl ;
assign NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 =
(!mmio_dataRespQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_mmio_sendDataResp ?
!mmio_dataRespQ_enqReq_lat_0$wget[65] :
!mmio_dataRespQ_enqReq_rl[65])) &&
(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT &&
(mmio_dataRespQ_deqReq_lat_0$whas ||
mmio_dataRespQ_deqReq_rl) ||
mmio_dataRespQ_empty) ;
assign NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 =
!mmio_pRqQ_clearReq_dummy2_1$Q_OUT || !mmio_pRqQ_clearReq_rl ;
assign NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 =
(!mmio_pRqQ_enqReq_dummy2_2$Q_OUT ||
(EN_mmioToPlatform_pRq_enq ?
!mmio_pRqQ_enqReq_lat_0$wget[39] :
!mmio_pRqQ_enqReq_rl[39])) &&
(mmio_pRqQ_deqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl) ||
mmio_pRqQ_empty) ;
assign NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 =
!mmio_pRsQ_clearReq_dummy2_1$Q_OUT || !mmio_pRsQ_clearReq_rl ;
assign NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 =
(!mmio_pRsQ_enqReq_dummy2_2$Q_OUT ||
(EN_mmioToPlatform_pRs_enq ?
!mmio_pRsQ_enqReq_lat_0$wget[67] :
!mmio_pRsQ_enqReq_rl[67])) &&
(mmio_pRsQ_deqReq_dummy2_2$Q_OUT &&
(mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) ||
mmio_pRsQ_empty) ;
assign NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13927 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d13925 ;
assign NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14003 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
fetchStage_pipelines_0_first__2932_BIT_68_2961_ETC___d14001 ;
assign NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14380 =
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d13178[4] ||
!rob$enqPort_0_canEnq ;
assign NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13967 =
!regRenamingTable$rename_1_canRename ||
fetchStage$pipelines_1_first[199:195] == 5'd0 ||
fetchStage$pipelines_1_first[199:195] == 5'd21 ||
fetchStage$pipelines_1_first[199:195] == 5'd17 ||
fetchStage$pipelines_1_first[199:195] == 5'd18 ||
fetchStage$pipelines_1_first[199:195] == 5'd13 ||
fetchStage$pipelines_1_first[199:195] == 5'd16 ||
fetchStage$pipelines_1_first[199:195] == 5'd15 ||
fetchStage$pipelines_1_first[199:195] == 5'd19 ||
fetchStage$pipelines_1_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d13965 ;
assign NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d13270 =
!renameStage_rg_m_halt_req[4] &&
(fetchStage$pipelines_0_first[68] ||
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15]) ;
assign NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d13602 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13597 &&
rob$enqPort_0_canEnq &&
epochManager$checkEpoch_0_check ;
assign NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d13902 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13891 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13900 ;
assign NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d14044 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13891 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14042 ;
assign NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d14062 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13891 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14060 ;
assign NOT_rob_deqPort_0_canDeq__5509_5510_OR_rob_RDY_ETC___d15551 =
(!rob$deqPort_0_canDeq ||
rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit &&
v_f_to_TV_0$FULL_N) &&
(!rob$deqPort_1_canDeq ||
rob$RDY_deqPort_1_deq_data &&
NOT_rob_deqPort_1_deq_data__5517_BIT_25_5518_5_ETC___d15548) ;
assign NOT_rob_deqPort_0_canDeq__5509_5510_OR_rob_deq_ETC___d15811 =
(!rob$deqPort_0_canDeq ||
rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] &&
!rob$deqPort_0_deq_data[167] &&
rob$deqPort_0_deq_data[257:253] != 5'd0 &&
rob$deqPort_0_deq_data[257:253] != 5'd21 &&
rob$deqPort_0_deq_data[257:253] != 5'd17 &&
rob$deqPort_0_deq_data[257:253] != 5'd18 &&
rob$deqPort_0_deq_data[257:253] != 5'd13 &&
rob$deqPort_0_deq_data[257:253] != 5'd16 &&
rob$deqPort_0_deq_data[257:253] != 5'd15 &&
rob$deqPort_0_deq_data[257:253] != 5'd19 &&
rob$deqPort_0_deq_data[257:253] != 5'd20) &&
rob$deqPort_1_canDeq ;
assign NOT_rob_deqPort_0_deq_data__4560_BITS_257_TO_2_ETC___d15199 =
rob$deqPort_0_deq_data[257:253] != 5'd13 ||
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 !=
6'd7 ||
csrf_stats_module_writeQ$FULL_N) &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 !=
6'd6 ||
csrf_terminate_module_terminateQ$FULL_N) ;
assign NOT_rob_deqPort_1_deq_data__5517_BIT_25_5518_5_ETC___d15548 =
!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[257:253] == 5'd0 ||
rob$deqPort_1_deq_data[257:253] == 5'd21 ||
rob$deqPort_1_deq_data[257:253] == 5'd17 ||
rob$deqPort_1_deq_data[257:253] == 5'd18 ||
rob$deqPort_1_deq_data[257:253] == 5'd13 ||
rob$deqPort_1_deq_data[257:253] == 5'd16 ||
rob$deqPort_1_deq_data[257:253] == 5'd15 ||
rob$deqPort_1_deq_data[257:253] == 5'd19 ||
rob$deqPort_1_deq_data[257:253] == 5'd20 ||
rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit &&
v_f_to_TV_1$FULL_N ;
assign NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14173 =
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2932_BITS_199_TO_ETC___d13683 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14113 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag ;
assign NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14240 =
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14086 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14113 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3014 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3023 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3014,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3032 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3023,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3039 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265,
!CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3032,
x__h294075 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16241 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16197 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q252,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16206 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16197,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16215 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16206,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 =
{ {4{f2_exp24169_MINUS_127__q176[7]}},
f2_exp24169_MINUS_127__q176 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11188 =
b__h606169 * b__h606245 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11201 =
b__h606169 * b__h606358 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 =
{ {4{f1_exp85175_MINUS_127__q136[7]}},
f1_exp85175_MINUS_127__q136 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 =
{ {4{f3_exp63473_MINUS_127__q153[7]}},
f3_exp63473_MINUS_127__q153 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] -
11'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] -
11'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] -
11'd1023 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72[10],
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37[10],
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107[10],
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4346 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4344 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5266 =
{ 3'd0,
_theResult___fst_exp__h356722 == 8'd0 &&
(sfdin__h356716[56:34] == 23'd0 || guard__h348621 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h357319 == 8'd255 &&
_theResult___fst_sfd__h357320 == 23'd0,
1'd0,
_theResult___fst_exp__h356722 != 8'd255 &&
guard__h348621 != 2'b0 } ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5738 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5736 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6658 =
{ 3'd0,
_theResult___fst_exp__h402419 == 8'd0 &&
(sfdin__h402413[56:34] == 23'd0 || guard__h394320 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h403016 == 8'd255 &&
_theResult___fst_sfd__h403017 == 23'd0,
1'd0,
_theResult___fst_exp__h402419 != 8'd255 &&
guard__h394320 != 2'b0 } ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7130 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7128 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8050 =
{ 3'd0,
_theResult___fst_exp__h448114 == 8'd0 &&
(sfdin__h448108[56:34] == 23'd0 || guard__h440015 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h448711 == 8'd255 &&
_theResult___fst_sfd__h448712 == 23'd0,
1'd0,
_theResult___fst_exp__h448114 != 8'd255 &&
guard__h440015 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10494 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10492 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10870 =
{ 3'd0,
_theResult___fst_exp__h514140 == 11'd0 &&
(sfdin__h514134[56:5] == 52'd0 || guard__h505914 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h514972 == 11'd2047 &&
_theResult___fst_sfd__h514973 == 52'd0,
1'd0,
_theResult___fst_exp__h514140 != 11'd2047 &&
guard__h505914 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10911 =
{ 3'd0,
_theResult___fst_exp__h552993 == 11'd0 &&
(sfdin__h552987[56:5] == 52'd0 || guard__h544767 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h553825 == 11'd2047 &&
_theResult___fst_sfd__h553826 == 52'd0,
1'd0,
_theResult___fst_exp__h552993 != 11'd2047 &&
guard__h544767 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10955 =
{ 3'd0,
_theResult___fst_exp__h592297 == 11'd0 &&
(sfdin__h592291[56:5] == 52'd0 || guard__h584071 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h593129 == 11'd2047 &&
_theResult___fst_sfd__h593130 == 52'd0,
1'd0,
_theResult___fst_exp__h592297 != 11'd2047 &&
guard__h584071 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9009 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9007 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9724 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9722 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4897 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4895 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5295 =
{ 3'd0,
_theResult___fst_exp__h374488 == 8'd0 &&
(sfdin__h374482[56:34] == 23'd0 || guard__h366260 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h375085 == 8'd255 &&
_theResult___fst_sfd__h375086 == 23'd0,
1'd0,
_theResult___fst_exp__h374488 != 8'd255 &&
guard__h366260 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6289 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6287 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6687 =
{ 3'd0,
_theResult___fst_exp__h420185 == 8'd0 &&
(sfdin__h420179[56:34] == 23'd0 || guard__h411957 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h420782 == 8'd255 &&
_theResult___fst_sfd__h420783 == 23'd0,
1'd0,
_theResult___fst_exp__h420185 != 8'd255 &&
guard__h411957 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7681 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7679 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8079 =
{ 3'd0,
_theResult___fst_exp__h465880 == 8'd0 &&
(sfdin__h465874[56:34] == 23'd0 || guard__h457652 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h466477 == 8'd255 &&
_theResult___fst_sfd__h466478 == 23'd0,
1'd0,
_theResult___fst_exp__h465880 != 8'd255 &&
guard__h457652 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10197 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10195 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10544 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10195 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10543 ^
12'h800) ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10853 =
{ 3'd0,
_theResult___fst_exp__h504563 == 11'd0 &&
guard__h496602 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h505321 == 11'd2047 &&
_theResult___fst_sfd__h505322 == 52'd0,
1'd0,
_theResult___fst_exp__h504563 != 11'd2047 &&
guard__h496602 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10894 =
{ 3'd0,
_theResult___fst_exp__h543416 == 11'd0 &&
guard__h535455 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h544174 == 11'd2047 &&
_theResult___fst_sfd__h544175 == 52'd0,
1'd0,
_theResult___fst_exp__h543416 != 11'd2047 &&
guard__h535455 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10938 =
{ 3'd0,
_theResult___fst_exp__h582720 == 11'd0 &&
guard__h574759 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h583478 == 11'd2047 &&
_theResult___fst_sfd__h583479 == 52'd0,
1'd0,
_theResult___fst_exp__h582720 != 11'd2047 &&
guard__h574759 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8697 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8695 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9059 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8695 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9058 ^
12'h800) ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9427 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9425 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9774 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9425 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9773 ^
12'h800) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4577 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4575 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4970 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4575 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4969 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5278 =
{ 3'd0,
_theResult___fst_exp__h365378 == 8'd0 &&
guard__h357330 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h365901 == 8'd255 &&
_theResult___fst_sfd__h365902 == 23'd0,
1'd0,
_theResult___fst_exp__h365378 != 8'd255 &&
guard__h357330 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5969 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5967 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6362 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5967 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6361 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6670 =
{ 3'd0,
_theResult___fst_exp__h411075 == 8'd0 &&
guard__h403027 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h411598 == 8'd255 &&
_theResult___fst_sfd__h411599 == 23'd0,
1'd0,
_theResult___fst_exp__h411075 != 8'd255 &&
guard__h403027 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7361 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7359 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7754 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7359 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7753 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8062 =
{ 3'd0,
_theResult___fst_exp__h456770 == 8'd0 &&
guard__h448722 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h457293 == 8'd255 &&
_theResult___fst_sfd__h457294 == 23'd0,
1'd0,
_theResult___fst_exp__h456770 != 8'd255 &&
guard__h448722 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11194 =
b__h606346 * b__h606358 ;
assign _0_CONCAT_csrf_external_int_en_vec_3_read__1851_ETC___d12970 =
{ 4'd0,
csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3,
1'd0,
csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1,
csrf_external_int_en_vec_0 & csrf_external_int_pend_vec_0 } ;
assign _0_CONCAT_csrf_external_int_en_vec_3_read__1851_ETC___d12975 =
{ _0_CONCAT_csrf_external_int_en_vec_3_read__1851_ETC___d12970,
csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3,
1'd0,
csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1,
csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ;
assign _0_OR_NOT_fetchStage_pipelines_0_first__2932_BI_ETC___d14094 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag) &&
CASE_k72122_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 ;
assign _0_OR_NOT_fetchStage_pipelines_1_first__2941_BI_ETC___d13995 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(fetchStage$RDY_pipelines_0_first &&
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667 ||
NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13967) ;
assign _0_OR_NOT_fetchStage_pipelines_1_first__2941_BI_ETC___d14186 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag) &&
CASE_fetchStage_pipelines_0_canDeq__2930_AND_N_ETC__q241 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10250 =
sfd__h524531 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10246 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8765 =
sfd__h485537 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8761 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9480 =
sfd__h563835 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9476 ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4655 =
sfd__h341006 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4651[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4651) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6047 =
sfd__h386708 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6043[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6043) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7439 =
sfd__h432403 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7435[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7435) ;
assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1832_1833_ETC___d14934 =
medeleg_csr__read__h614755[i__h708343] ;
assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1840_1841_ETC___d14916 =
mideleg_csr__read__h614850[i__h708503] ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5281 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5266[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5278[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5306 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5266[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5278[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5333 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5266[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5278[1]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6673 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6658[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6670[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6698 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6658[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6670[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6725 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6658[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6670[1]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8065 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8050[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8062[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8090 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8050[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8062[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8050[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8062[1]) ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10246 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8761 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9476 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 =
12'd3970 -
{ 7'd0,
f2_sfd__h524170[22] ?
5'd0 :
(f2_sfd__h524170[21] ?
5'd1 :
(f2_sfd__h524170[20] ?
5'd2 :
(f2_sfd__h524170[19] ?
5'd3 :
(f2_sfd__h524170[18] ?
5'd4 :
(f2_sfd__h524170[17] ?
5'd5 :
(f2_sfd__h524170[16] ?
5'd6 :
(f2_sfd__h524170[15] ?
5'd7 :
(f2_sfd__h524170[14] ?
5'd8 :
(f2_sfd__h524170[13] ?
5'd9 :
(f2_sfd__h524170[12] ?
5'd10 :
(f2_sfd__h524170[11] ?
5'd11 :
(f2_sfd__h524170[10] ?
5'd12 :
(f2_sfd__h524170[9] ?
5'd13 :
(f2_sfd__h524170[8] ?
5'd14 :
(f2_sfd__h524170[7] ?
5'd15 :
(f2_sfd__h524170[6] ?
5'd16 :
(f2_sfd__h524170[5] ?
5'd17 :
(f2_sfd__h524170[4] ?
5'd18 :
(f2_sfd__h524170[3] ?
5'd19 :
(f2_sfd__h524170[2] ?
5'd20 :
(f2_sfd__h524170[1] ?
5'd21 :
(f2_sfd__h524170[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 =
12'd3970 -
{ 7'd0,
f1_sfd__h485176[22] ?
5'd0 :
(f1_sfd__h485176[21] ?
5'd1 :
(f1_sfd__h485176[20] ?
5'd2 :
(f1_sfd__h485176[19] ?
5'd3 :
(f1_sfd__h485176[18] ?
5'd4 :
(f1_sfd__h485176[17] ?
5'd5 :
(f1_sfd__h485176[16] ?
5'd6 :
(f1_sfd__h485176[15] ?
5'd7 :
(f1_sfd__h485176[14] ?
5'd8 :
(f1_sfd__h485176[13] ?
5'd9 :
(f1_sfd__h485176[12] ?
5'd10 :
(f1_sfd__h485176[11] ?
5'd11 :
(f1_sfd__h485176[10] ?
5'd12 :
(f1_sfd__h485176[9] ?
5'd13 :
(f1_sfd__h485176[8] ?
5'd14 :
(f1_sfd__h485176[7] ?
5'd15 :
(f1_sfd__h485176[6] ?
5'd16 :
(f1_sfd__h485176[5] ?
5'd17 :
(f1_sfd__h485176[4] ?
5'd18 :
(f1_sfd__h485176[3] ?
5'd19 :
(f1_sfd__h485176[2] ?
5'd20 :
(f1_sfd__h485176[1] ?
5'd21 :
(f1_sfd__h485176[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 =
12'd3970 -
{ 7'd0,
f3_sfd__h563474[22] ?
5'd0 :
(f3_sfd__h563474[21] ?
5'd1 :
(f3_sfd__h563474[20] ?
5'd2 :
(f3_sfd__h563474[19] ?
5'd3 :
(f3_sfd__h563474[18] ?
5'd4 :
(f3_sfd__h563474[17] ?
5'd5 :
(f3_sfd__h563474[16] ?
5'd6 :
(f3_sfd__h563474[15] ?
5'd7 :
(f3_sfd__h563474[14] ?
5'd8 :
(f3_sfd__h563474[13] ?
5'd9 :
(f3_sfd__h563474[12] ?
5'd10 :
(f3_sfd__h563474[11] ?
5'd11 :
(f3_sfd__h563474[10] ?
5'd12 :
(f3_sfd__h563474[9] ?
5'd13 :
(f3_sfd__h563474[8] ?
5'd14 :
(f3_sfd__h563474[7] ?
5'd15 :
(f3_sfd__h563474[6] ?
5'd16 :
(f3_sfd__h563474[5] ?
5'd17 :
(f3_sfd__h563474[4] ?
5'd18 :
(f3_sfd__h563474[3] ?
5'd19 :
(f3_sfd__h563474[2] ?
5'd20 :
(f3_sfd__h563474[1] ?
5'd21 :
(f3_sfd__h563474[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4651 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6043 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7435 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ;
assign _dfoo12 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14301 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14468 &&
fetchStage$pipelines_1_first[199:195] != 5'd14 ;
assign _dfoo16 =
k__h672122 == 1'd1 &&
fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14266 ||
(fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14372 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14385) ==
1'd1 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14404 ;
assign _dfoo18 =
k__h672122 == 1'd0 &&
fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14266 ||
(fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14372 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14385) ==
1'd0 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14404 ;
assign _dfoo2 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14343 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14468 &&
fetchStage$pipelines_1_first[191:189] != 3'd0 &&
fetchStage$pipelines_1_first[191:189] != 3'd2 ;
assign _dfoo20 =
commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 ||
NOT_commitStage_commitTrap_4568_BIT_4_4808_480_ETC___d14913 ;
assign _dfoo24 =
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd36 ||
rob$deqPort_0_deq_data[257:253] == 5'd19 ||
rob$deqPort_0_deq_data[257:253] == 5'd20 ;
assign _dfoo26 =
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18 ||
rob$deqPort_0_deq_data[257:253] == 5'd20 ;
assign _dfoo32 =
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 ==
6'd18) ||
rob$deqPort_0_deq_data[257:253] == 5'd19 ;
assign _dfoo7 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14335 ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14468 &&
(fetchStage$pipelines_1_first[191:189] == 3'd0 ||
fetchStage$pipelines_1_first[191:189] == 3'd2) ;
assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_aluExe_0_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_aluExe_1_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_aluExe_1_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_memExe_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1rf$EN_write_0_wr =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1rf$EN_write_1_wr =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1sbAggr$EN_setReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1sbCons$EN_setReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1sbCons$EN_setReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _theResult_____2__h299047 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3143) ?
next_deqP___1__h299326 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ;
assign _theResult_____2__h307043 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3250) ?
next_deqP___1__h307322 :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ;
assign _theResult_____2__h313037 =
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3421) ?
next_deqP___1__h313603 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ;
assign _theResult_____2__h320891 =
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3517) ?
next_deqP___1__h321457 :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ;
assign _theResult_____2__h331235 =
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3746) ?
next_deqP___1__h331514 :
coreFix_memExe_memRespLdQ_deqP ;
assign _theResult_____2__h334460 =
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3840) ?
next_deqP___1__h334739 :
coreFix_memExe_forwardQ_deqP ;
assign _theResult____h348611 =
(value__h349233 == 54'd0) ? sfd__h341006 : 57'd1 ;
assign _theResult____h366250 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4651 ^
12'h800) <
12'd2105) ?
result__h366863 :
_theResult____h348611 ;
assign _theResult____h394310 =
(value__h394930 == 54'd0) ? sfd__h386708 : 57'd1 ;
assign _theResult____h411947 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6043 ^
12'h800) <
12'd2105) ?
result__h412560 :
_theResult____h394310 ;
assign _theResult____h440005 =
(value__h440625 == 54'd0) ? sfd__h432403 : 57'd1 ;
assign _theResult____h457642 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7435 ^
12'h800) <
12'd2105) ?
result__h458255 :
_theResult____h440005 ;
assign _theResult____h505904 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8761 ^
12'h800) <
12'd2105) ?
result__h506517 :
((value__h490120 == 25'd0) ? sfd__h485537 : 57'd1) ;
assign _theResult____h544757 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10246 ^
12'h800) <
12'd2105) ?
result__h545370 :
((value__h528973 == 25'd0) ? sfd__h524531 : 57'd1) ;
assign _theResult____h584061 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9476 ^
12'h800) <
12'd2105) ?
result__h584674 :
((value__h568277 == 25'd0) ? sfd__h563835 : 57'd1) ;
assign _theResult____h655256 =
(csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ?
enabled_ints___1__h655781 :
16'd0 ;
assign _theResult___exp__h357238 =
sfd__h356814[24] ?
((_theResult___fst_exp__h356722 == 8'd254) ?
8'd255 :
din_inc___2_exp__h383755) :
((_theResult___fst_exp__h356722 == 8'd0 &&
sfd__h356814[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h356722) ;
assign _theResult___exp__h365820 =
sfd__h365396[24] ?
((_theResult___fst_exp__h365378 == 8'd254) ?
8'd255 :
din_inc___2_exp__h383779) :
((_theResult___fst_exp__h365378 == 8'd0 &&
sfd__h365396[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h365378) ;
assign _theResult___exp__h375004 =
sfd__h374580[24] ?
((_theResult___fst_exp__h374488 == 8'd254) ?
8'd255 :
din_inc___2_exp__h383809) :
((_theResult___fst_exp__h374488 == 8'd0 &&
sfd__h374580[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h374488) ;
assign _theResult___exp__h383640 =
sfd__h383192[24] ?
((_theResult___fst_exp__h383173 == 8'd254) ?
8'd255 :
din_inc___2_exp__h383833) :
((_theResult___fst_exp__h383173 == 8'd0 &&
sfd__h383192[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h383173) ;
assign _theResult___exp__h383742 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h383733 ;
assign _theResult___exp__h402935 =
sfd__h402511[24] ?
((_theResult___fst_exp__h402419 == 8'd254) ?
8'd255 :
din_inc___2_exp__h429452) :
((_theResult___fst_exp__h402419 == 8'd0 &&
sfd__h402511[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h402419) ;
assign _theResult___exp__h411517 =
sfd__h411093[24] ?
((_theResult___fst_exp__h411075 == 8'd254) ?
8'd255 :
din_inc___2_exp__h429476) :
((_theResult___fst_exp__h411075 == 8'd0 &&
sfd__h411093[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h411075) ;
assign _theResult___exp__h420701 =
sfd__h420277[24] ?
((_theResult___fst_exp__h420185 == 8'd254) ?
8'd255 :
din_inc___2_exp__h429506) :
((_theResult___fst_exp__h420185 == 8'd0 &&
sfd__h420277[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h420185) ;
assign _theResult___exp__h429337 =
sfd__h428889[24] ?
((_theResult___fst_exp__h428870 == 8'd254) ?
8'd255 :
din_inc___2_exp__h429530) :
((_theResult___fst_exp__h428870 == 8'd0 &&
sfd__h428889[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h428870) ;
assign _theResult___exp__h429439 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h429430 ;
assign _theResult___exp__h448630 =
sfd__h448206[24] ?
((_theResult___fst_exp__h448114 == 8'd254) ?
8'd255 :
din_inc___2_exp__h475147) :
((_theResult___fst_exp__h448114 == 8'd0 &&
sfd__h448206[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h448114) ;
assign _theResult___exp__h457212 =
sfd__h456788[24] ?
((_theResult___fst_exp__h456770 == 8'd254) ?
8'd255 :
din_inc___2_exp__h475171) :
((_theResult___fst_exp__h456770 == 8'd0 &&
sfd__h456788[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h456770) ;
assign _theResult___exp__h466396 =
sfd__h465972[24] ?
((_theResult___fst_exp__h465880 == 8'd254) ?
8'd255 :
din_inc___2_exp__h475201) :
((_theResult___fst_exp__h465880 == 8'd0 &&
sfd__h465972[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h465880) ;
assign _theResult___exp__h475032 =
sfd__h474584[24] ?
((_theResult___fst_exp__h474565 == 8'd254) ?
8'd255 :
din_inc___2_exp__h475225) :
((_theResult___fst_exp__h474565 == 8'd0 &&
sfd__h474584[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h474565) ;
assign _theResult___exp__h475134 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h475125 ;
assign _theResult___exp__h505218 =
sfd__h504581[53] ?
((_theResult___fst_exp__h504563 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h523813) :
((_theResult___fst_exp__h504563 == 11'd0 &&
sfd__h504581[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h504563) ;
assign _theResult___exp__h514869 =
sfd__h514232[53] ?
((_theResult___fst_exp__h514140 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h523848) :
((_theResult___fst_exp__h514140 == 11'd0 &&
sfd__h514232[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h514140) ;
assign _theResult___exp__h523653 =
sfd__h522992[53] ?
((_theResult___fst_exp__h522973 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h523874) :
((_theResult___fst_exp__h522973 == 11'd0 &&
sfd__h522992[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h522973) ;
assign _theResult___exp__h544071 =
sfd__h543434[53] ?
((_theResult___fst_exp__h543416 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h562666) :
((_theResult___fst_exp__h543416 == 11'd0 &&
sfd__h543434[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h543416) ;
assign _theResult___exp__h553722 =
sfd__h553085[53] ?
((_theResult___fst_exp__h552993 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h562701) :
((_theResult___fst_exp__h552993 == 11'd0 &&
sfd__h553085[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h552993) ;
assign _theResult___exp__h562506 =
sfd__h561845[53] ?
((_theResult___fst_exp__h561826 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h562727) :
((_theResult___fst_exp__h561826 == 11'd0 &&
sfd__h561845[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h561826) ;
assign _theResult___exp__h583375 =
sfd__h582738[53] ?
((_theResult___fst_exp__h582720 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h601970) :
((_theResult___fst_exp__h582720 == 11'd0 &&
sfd__h582738[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h582720) ;
assign _theResult___exp__h593026 =
sfd__h592389[53] ?
((_theResult___fst_exp__h592297 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h602005) :
((_theResult___fst_exp__h592297 == 11'd0 &&
sfd__h592389[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h592297) ;
assign _theResult___exp__h601810 =
sfd__h601149[53] ?
((_theResult___fst_exp__h601130 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h602031) :
((_theResult___fst_exp__h601130 == 11'd0 &&
sfd__h601149[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h601130) ;
assign _theResult___fst__h606569 =
a__h606021[63] ? a___1__h606574 : a__h606021 ;
assign _theResult___fst_exp__h356722 =
_theResult____h348611[56] ?
8'd2 :
_theResult___fst_exp__h356796 ;
assign _theResult___fst_exp__h356787 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4344 } ;
assign _theResult___fst_exp__h356793 =
(!_theResult____h348611[56] && !_theResult____h348611[55] &&
!_theResult____h348611[54] &&
!_theResult____h348611[53] &&
!_theResult____h348611[52] &&
!_theResult____h348611[51] &&
!_theResult____h348611[50] &&
!_theResult____h348611[49] &&
!_theResult____h348611[48] &&
!_theResult____h348611[47] &&
!_theResult____h348611[46] &&
!_theResult____h348611[45] &&
!_theResult____h348611[44] &&
!_theResult____h348611[43] &&
!_theResult____h348611[42] &&
!_theResult____h348611[41] &&
!_theResult____h348611[40] &&
!_theResult____h348611[39] &&
!_theResult____h348611[38] &&
!_theResult____h348611[37] &&
!_theResult____h348611[36] &&
!_theResult____h348611[35] &&
!_theResult____h348611[34] &&
!_theResult____h348611[33] &&
!_theResult____h348611[32] &&
!_theResult____h348611[31] &&
!_theResult____h348611[30] &&
!_theResult____h348611[29] &&
!_theResult____h348611[28] &&
!_theResult____h348611[27] &&
!_theResult____h348611[26] &&
!_theResult____h348611[25] &&
!_theResult____h348611[24] &&
!_theResult____h348611[23] &&
!_theResult____h348611[22] &&
!_theResult____h348611[21] &&
!_theResult____h348611[20] &&
!_theResult____h348611[19] &&
!_theResult____h348611[18] &&
!_theResult____h348611[17] &&
!_theResult____h348611[16] &&
!_theResult____h348611[15] &&
!_theResult____h348611[14] &&
!_theResult____h348611[13] &&
!_theResult____h348611[12] &&
!_theResult____h348611[11] &&
!_theResult____h348611[10] &&
!_theResult____h348611[9] &&
!_theResult____h348611[8] &&
!_theResult____h348611[7] &&
!_theResult____h348611[6] &&
!_theResult____h348611[5] &&
!_theResult____h348611[4] &&
!_theResult____h348611[3] &&
!_theResult____h348611[2] &&
!_theResult____h348611[1] &&
!_theResult____h348611[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4346) ?
8'd0 :
_theResult___fst_exp__h356787 ;
assign _theResult___fst_exp__h356796 =
(!_theResult____h348611[56] && _theResult____h348611[55]) ?
8'd1 :
_theResult___fst_exp__h356793 ;
assign _theResult___fst_exp__h357319 =
(_theResult___fst_exp__h356722 == 8'd255) ?
_theResult___fst_exp__h356722 :
_theResult___fst_exp__h357316 ;
assign _theResult___fst_exp__h365369 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4575 } ;
assign _theResult___fst_exp__h365375 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4520 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4577) ?
8'd0 :
_theResult___fst_exp__h365369 ;
assign _theResult___fst_exp__h365378 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h365375 :
8'd129 ;
assign _theResult___fst_exp__h365901 =
(_theResult___fst_exp__h365378 == 8'd255) ?
_theResult___fst_exp__h365378 :
_theResult___fst_exp__h365898 ;
assign _theResult___fst_exp__h374488 =
_theResult____h366250[56] ?
8'd2 :
_theResult___fst_exp__h374562 ;
assign _theResult___fst_exp__h374553 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4895 } ;
assign _theResult___fst_exp__h374559 =
(!_theResult____h366250[56] && !_theResult____h366250[55] &&
!_theResult____h366250[54] &&
!_theResult____h366250[53] &&
!_theResult____h366250[52] &&
!_theResult____h366250[51] &&
!_theResult____h366250[50] &&
!_theResult____h366250[49] &&
!_theResult____h366250[48] &&
!_theResult____h366250[47] &&
!_theResult____h366250[46] &&
!_theResult____h366250[45] &&
!_theResult____h366250[44] &&
!_theResult____h366250[43] &&
!_theResult____h366250[42] &&
!_theResult____h366250[41] &&
!_theResult____h366250[40] &&
!_theResult____h366250[39] &&
!_theResult____h366250[38] &&
!_theResult____h366250[37] &&
!_theResult____h366250[36] &&
!_theResult____h366250[35] &&
!_theResult____h366250[34] &&
!_theResult____h366250[33] &&
!_theResult____h366250[32] &&
!_theResult____h366250[31] &&
!_theResult____h366250[30] &&
!_theResult____h366250[29] &&
!_theResult____h366250[28] &&
!_theResult____h366250[27] &&
!_theResult____h366250[26] &&
!_theResult____h366250[25] &&
!_theResult____h366250[24] &&
!_theResult____h366250[23] &&
!_theResult____h366250[22] &&
!_theResult____h366250[21] &&
!_theResult____h366250[20] &&
!_theResult____h366250[19] &&
!_theResult____h366250[18] &&
!_theResult____h366250[17] &&
!_theResult____h366250[16] &&
!_theResult____h366250[15] &&
!_theResult____h366250[14] &&
!_theResult____h366250[13] &&
!_theResult____h366250[12] &&
!_theResult____h366250[11] &&
!_theResult____h366250[10] &&
!_theResult____h366250[9] &&
!_theResult____h366250[8] &&
!_theResult____h366250[7] &&
!_theResult____h366250[6] &&
!_theResult____h366250[5] &&
!_theResult____h366250[4] &&
!_theResult____h366250[3] &&
!_theResult____h366250[2] &&
!_theResult____h366250[1] &&
!_theResult____h366250[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4897) ?
8'd0 :
_theResult___fst_exp__h374553 ;
assign _theResult___fst_exp__h374562 =
(!_theResult____h366250[56] && _theResult____h366250[55]) ?
8'd1 :
_theResult___fst_exp__h374559 ;
assign _theResult___fst_exp__h375085 =
(_theResult___fst_exp__h374488 == 8'd255) ?
_theResult___fst_exp__h374488 :
_theResult___fst_exp__h375082 ;
assign _theResult___fst_exp__h383125 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] ;
assign _theResult___fst_exp__h383164 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4575 } ;
assign _theResult___fst_exp__h383170 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4520 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4970) ?
8'd0 :
_theResult___fst_exp__h383164 ;
assign _theResult___fst_exp__h383173 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h383170 :
_theResult___fst_exp__h383125 ;
assign _theResult___fst_exp__h383721 =
(_theResult___fst_exp__h383173 == 8'd255) ?
_theResult___fst_exp__h383173 :
_theResult___fst_exp__h383718 ;
assign _theResult___fst_exp__h383730 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
_theResult___snd_fst_exp__h365904 :
_theResult___fst_exp__h348593) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
_theResult___snd_fst_exp__h383724 :
_theResult___fst_exp__h348593) ;
assign _theResult___fst_exp__h383733 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h383730 ;
assign _theResult___fst_exp__h402419 =
_theResult____h394310[56] ?
8'd2 :
_theResult___fst_exp__h402493 ;
assign _theResult___fst_exp__h402484 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5736 } ;
assign _theResult___fst_exp__h402490 =
(!_theResult____h394310[56] && !_theResult____h394310[55] &&
!_theResult____h394310[54] &&
!_theResult____h394310[53] &&
!_theResult____h394310[52] &&
!_theResult____h394310[51] &&
!_theResult____h394310[50] &&
!_theResult____h394310[49] &&
!_theResult____h394310[48] &&
!_theResult____h394310[47] &&
!_theResult____h394310[46] &&
!_theResult____h394310[45] &&
!_theResult____h394310[44] &&
!_theResult____h394310[43] &&
!_theResult____h394310[42] &&
!_theResult____h394310[41] &&
!_theResult____h394310[40] &&
!_theResult____h394310[39] &&
!_theResult____h394310[38] &&
!_theResult____h394310[37] &&
!_theResult____h394310[36] &&
!_theResult____h394310[35] &&
!_theResult____h394310[34] &&
!_theResult____h394310[33] &&
!_theResult____h394310[32] &&
!_theResult____h394310[31] &&
!_theResult____h394310[30] &&
!_theResult____h394310[29] &&
!_theResult____h394310[28] &&
!_theResult____h394310[27] &&
!_theResult____h394310[26] &&
!_theResult____h394310[25] &&
!_theResult____h394310[24] &&
!_theResult____h394310[23] &&
!_theResult____h394310[22] &&
!_theResult____h394310[21] &&
!_theResult____h394310[20] &&
!_theResult____h394310[19] &&
!_theResult____h394310[18] &&
!_theResult____h394310[17] &&
!_theResult____h394310[16] &&
!_theResult____h394310[15] &&
!_theResult____h394310[14] &&
!_theResult____h394310[13] &&
!_theResult____h394310[12] &&
!_theResult____h394310[11] &&
!_theResult____h394310[10] &&
!_theResult____h394310[9] &&
!_theResult____h394310[8] &&
!_theResult____h394310[7] &&
!_theResult____h394310[6] &&
!_theResult____h394310[5] &&
!_theResult____h394310[4] &&
!_theResult____h394310[3] &&
!_theResult____h394310[2] &&
!_theResult____h394310[1] &&
!_theResult____h394310[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5738) ?
8'd0 :
_theResult___fst_exp__h402484 ;
assign _theResult___fst_exp__h402493 =
(!_theResult____h394310[56] && _theResult____h394310[55]) ?
8'd1 :
_theResult___fst_exp__h402490 ;
assign _theResult___fst_exp__h403016 =
(_theResult___fst_exp__h402419 == 8'd255) ?
_theResult___fst_exp__h402419 :
_theResult___fst_exp__h403013 ;
assign _theResult___fst_exp__h411066 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5967 } ;
assign _theResult___fst_exp__h411072 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5912 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5969) ?
8'd0 :
_theResult___fst_exp__h411066 ;
assign _theResult___fst_exp__h411075 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h411072 :
8'd129 ;
assign _theResult___fst_exp__h411598 =
(_theResult___fst_exp__h411075 == 8'd255) ?
_theResult___fst_exp__h411075 :
_theResult___fst_exp__h411595 ;
assign _theResult___fst_exp__h420185 =
_theResult____h411947[56] ?
8'd2 :
_theResult___fst_exp__h420259 ;
assign _theResult___fst_exp__h420250 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6287 } ;
assign _theResult___fst_exp__h420256 =
(!_theResult____h411947[56] && !_theResult____h411947[55] &&
!_theResult____h411947[54] &&
!_theResult____h411947[53] &&
!_theResult____h411947[52] &&
!_theResult____h411947[51] &&
!_theResult____h411947[50] &&
!_theResult____h411947[49] &&
!_theResult____h411947[48] &&
!_theResult____h411947[47] &&
!_theResult____h411947[46] &&
!_theResult____h411947[45] &&
!_theResult____h411947[44] &&
!_theResult____h411947[43] &&
!_theResult____h411947[42] &&
!_theResult____h411947[41] &&
!_theResult____h411947[40] &&
!_theResult____h411947[39] &&
!_theResult____h411947[38] &&
!_theResult____h411947[37] &&
!_theResult____h411947[36] &&
!_theResult____h411947[35] &&
!_theResult____h411947[34] &&
!_theResult____h411947[33] &&
!_theResult____h411947[32] &&
!_theResult____h411947[31] &&
!_theResult____h411947[30] &&
!_theResult____h411947[29] &&
!_theResult____h411947[28] &&
!_theResult____h411947[27] &&
!_theResult____h411947[26] &&
!_theResult____h411947[25] &&
!_theResult____h411947[24] &&
!_theResult____h411947[23] &&
!_theResult____h411947[22] &&
!_theResult____h411947[21] &&
!_theResult____h411947[20] &&
!_theResult____h411947[19] &&
!_theResult____h411947[18] &&
!_theResult____h411947[17] &&
!_theResult____h411947[16] &&
!_theResult____h411947[15] &&
!_theResult____h411947[14] &&
!_theResult____h411947[13] &&
!_theResult____h411947[12] &&
!_theResult____h411947[11] &&
!_theResult____h411947[10] &&
!_theResult____h411947[9] &&
!_theResult____h411947[8] &&
!_theResult____h411947[7] &&
!_theResult____h411947[6] &&
!_theResult____h411947[5] &&
!_theResult____h411947[4] &&
!_theResult____h411947[3] &&
!_theResult____h411947[2] &&
!_theResult____h411947[1] &&
!_theResult____h411947[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6289) ?
8'd0 :
_theResult___fst_exp__h420250 ;
assign _theResult___fst_exp__h420259 =
(!_theResult____h411947[56] && _theResult____h411947[55]) ?
8'd1 :
_theResult___fst_exp__h420256 ;
assign _theResult___fst_exp__h420782 =
(_theResult___fst_exp__h420185 == 8'd255) ?
_theResult___fst_exp__h420185 :
_theResult___fst_exp__h420779 ;
assign _theResult___fst_exp__h428822 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] ;
assign _theResult___fst_exp__h428861 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5967 } ;
assign _theResult___fst_exp__h428867 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5912 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6362) ?
8'd0 :
_theResult___fst_exp__h428861 ;
assign _theResult___fst_exp__h428870 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h428867 :
_theResult___fst_exp__h428822 ;
assign _theResult___fst_exp__h429418 =
(_theResult___fst_exp__h428870 == 8'd255) ?
_theResult___fst_exp__h428870 :
_theResult___fst_exp__h429415 ;
assign _theResult___fst_exp__h429427 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
_theResult___snd_fst_exp__h411601 :
_theResult___fst_exp__h394292) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
_theResult___snd_fst_exp__h429421 :
_theResult___fst_exp__h394292) ;
assign _theResult___fst_exp__h429430 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h429427 ;
assign _theResult___fst_exp__h448114 =
_theResult____h440005[56] ?
8'd2 :
_theResult___fst_exp__h448188 ;
assign _theResult___fst_exp__h448179 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7128 } ;
assign _theResult___fst_exp__h448185 =
(!_theResult____h440005[56] && !_theResult____h440005[55] &&
!_theResult____h440005[54] &&
!_theResult____h440005[53] &&
!_theResult____h440005[52] &&
!_theResult____h440005[51] &&
!_theResult____h440005[50] &&
!_theResult____h440005[49] &&
!_theResult____h440005[48] &&
!_theResult____h440005[47] &&
!_theResult____h440005[46] &&
!_theResult____h440005[45] &&
!_theResult____h440005[44] &&
!_theResult____h440005[43] &&
!_theResult____h440005[42] &&
!_theResult____h440005[41] &&
!_theResult____h440005[40] &&
!_theResult____h440005[39] &&
!_theResult____h440005[38] &&
!_theResult____h440005[37] &&
!_theResult____h440005[36] &&
!_theResult____h440005[35] &&
!_theResult____h440005[34] &&
!_theResult____h440005[33] &&
!_theResult____h440005[32] &&
!_theResult____h440005[31] &&
!_theResult____h440005[30] &&
!_theResult____h440005[29] &&
!_theResult____h440005[28] &&
!_theResult____h440005[27] &&
!_theResult____h440005[26] &&
!_theResult____h440005[25] &&
!_theResult____h440005[24] &&
!_theResult____h440005[23] &&
!_theResult____h440005[22] &&
!_theResult____h440005[21] &&
!_theResult____h440005[20] &&
!_theResult____h440005[19] &&
!_theResult____h440005[18] &&
!_theResult____h440005[17] &&
!_theResult____h440005[16] &&
!_theResult____h440005[15] &&
!_theResult____h440005[14] &&
!_theResult____h440005[13] &&
!_theResult____h440005[12] &&
!_theResult____h440005[11] &&
!_theResult____h440005[10] &&
!_theResult____h440005[9] &&
!_theResult____h440005[8] &&
!_theResult____h440005[7] &&
!_theResult____h440005[6] &&
!_theResult____h440005[5] &&
!_theResult____h440005[4] &&
!_theResult____h440005[3] &&
!_theResult____h440005[2] &&
!_theResult____h440005[1] &&
!_theResult____h440005[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7130) ?
8'd0 :
_theResult___fst_exp__h448179 ;
assign _theResult___fst_exp__h448188 =
(!_theResult____h440005[56] && _theResult____h440005[55]) ?
8'd1 :
_theResult___fst_exp__h448185 ;
assign _theResult___fst_exp__h448711 =
(_theResult___fst_exp__h448114 == 8'd255) ?
_theResult___fst_exp__h448114 :
_theResult___fst_exp__h448708 ;
assign _theResult___fst_exp__h456761 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7359 } ;
assign _theResult___fst_exp__h456767 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7304 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7361) ?
8'd0 :
_theResult___fst_exp__h456761 ;
assign _theResult___fst_exp__h456770 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h456767 :
8'd129 ;
assign _theResult___fst_exp__h457293 =
(_theResult___fst_exp__h456770 == 8'd255) ?
_theResult___fst_exp__h456770 :
_theResult___fst_exp__h457290 ;
assign _theResult___fst_exp__h465880 =
_theResult____h457642[56] ?
8'd2 :
_theResult___fst_exp__h465954 ;
assign _theResult___fst_exp__h465945 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7679 } ;
assign _theResult___fst_exp__h465951 =
(!_theResult____h457642[56] && !_theResult____h457642[55] &&
!_theResult____h457642[54] &&
!_theResult____h457642[53] &&
!_theResult____h457642[52] &&
!_theResult____h457642[51] &&
!_theResult____h457642[50] &&
!_theResult____h457642[49] &&
!_theResult____h457642[48] &&
!_theResult____h457642[47] &&
!_theResult____h457642[46] &&
!_theResult____h457642[45] &&
!_theResult____h457642[44] &&
!_theResult____h457642[43] &&
!_theResult____h457642[42] &&
!_theResult____h457642[41] &&
!_theResult____h457642[40] &&
!_theResult____h457642[39] &&
!_theResult____h457642[38] &&
!_theResult____h457642[37] &&
!_theResult____h457642[36] &&
!_theResult____h457642[35] &&
!_theResult____h457642[34] &&
!_theResult____h457642[33] &&
!_theResult____h457642[32] &&
!_theResult____h457642[31] &&
!_theResult____h457642[30] &&
!_theResult____h457642[29] &&
!_theResult____h457642[28] &&
!_theResult____h457642[27] &&
!_theResult____h457642[26] &&
!_theResult____h457642[25] &&
!_theResult____h457642[24] &&
!_theResult____h457642[23] &&
!_theResult____h457642[22] &&
!_theResult____h457642[21] &&
!_theResult____h457642[20] &&
!_theResult____h457642[19] &&
!_theResult____h457642[18] &&
!_theResult____h457642[17] &&
!_theResult____h457642[16] &&
!_theResult____h457642[15] &&
!_theResult____h457642[14] &&
!_theResult____h457642[13] &&
!_theResult____h457642[12] &&
!_theResult____h457642[11] &&
!_theResult____h457642[10] &&
!_theResult____h457642[9] &&
!_theResult____h457642[8] &&
!_theResult____h457642[7] &&
!_theResult____h457642[6] &&
!_theResult____h457642[5] &&
!_theResult____h457642[4] &&
!_theResult____h457642[3] &&
!_theResult____h457642[2] &&
!_theResult____h457642[1] &&
!_theResult____h457642[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7681) ?
8'd0 :
_theResult___fst_exp__h465945 ;
assign _theResult___fst_exp__h465954 =
(!_theResult____h457642[56] && _theResult____h457642[55]) ?
8'd1 :
_theResult___fst_exp__h465951 ;
assign _theResult___fst_exp__h466477 =
(_theResult___fst_exp__h465880 == 8'd255) ?
_theResult___fst_exp__h465880 :
_theResult___fst_exp__h466474 ;
assign _theResult___fst_exp__h474517 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] ;
assign _theResult___fst_exp__h474556 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7359 } ;
assign _theResult___fst_exp__h474562 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7304 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7754) ?
8'd0 :
_theResult___fst_exp__h474556 ;
assign _theResult___fst_exp__h474565 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h474562 :
_theResult___fst_exp__h474517 ;
assign _theResult___fst_exp__h475113 =
(_theResult___fst_exp__h474565 == 8'd255) ?
_theResult___fst_exp__h474565 :
_theResult___fst_exp__h475110 ;
assign _theResult___fst_exp__h475122 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
_theResult___snd_fst_exp__h457296 :
_theResult___fst_exp__h439987) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
_theResult___snd_fst_exp__h475116 :
_theResult___fst_exp__h439987) ;
assign _theResult___fst_exp__h475125 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h475122 ;
assign _theResult___fst_exp__h489490 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ;
assign _theResult___fst_exp__h504554 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8695 } ;
assign _theResult___fst_exp__h504560 =
(f1_exp__h485175 == 8'd0 && !f1_sfd__h485176[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8668 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8697) ?
11'd0 :
_theResult___fst_exp__h504554 ;
assign _theResult___fst_exp__h504563 =
(f1_exp__h485175 == 8'd0) ?
_theResult___fst_exp__h504560 :
11'd897 ;
assign _theResult___fst_exp__h505318 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q144 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9131 ;
assign _theResult___fst_exp__h505321 =
(_theResult___fst_exp__h504563 == 11'd2047) ?
_theResult___fst_exp__h504563 :
_theResult___fst_exp__h505318 ;
assign _theResult___fst_exp__h514140 =
_theResult____h505904[56] ?
11'd2 :
_theResult___fst_exp__h514214 ;
assign _theResult___fst_exp__h514205 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9007 } ;
assign _theResult___fst_exp__h514211 =
(!_theResult____h505904[56] && !_theResult____h505904[55] &&
!_theResult____h505904[54] &&
!_theResult____h505904[53] &&
!_theResult____h505904[52] &&
!_theResult____h505904[51] &&
!_theResult____h505904[50] &&
!_theResult____h505904[49] &&
!_theResult____h505904[48] &&
!_theResult____h505904[47] &&
!_theResult____h505904[46] &&
!_theResult____h505904[45] &&
!_theResult____h505904[44] &&
!_theResult____h505904[43] &&
!_theResult____h505904[42] &&
!_theResult____h505904[41] &&
!_theResult____h505904[40] &&
!_theResult____h505904[39] &&
!_theResult____h505904[38] &&
!_theResult____h505904[37] &&
!_theResult____h505904[36] &&
!_theResult____h505904[35] &&
!_theResult____h505904[34] &&
!_theResult____h505904[33] &&
!_theResult____h505904[32] &&
!_theResult____h505904[31] &&
!_theResult____h505904[30] &&
!_theResult____h505904[29] &&
!_theResult____h505904[28] &&
!_theResult____h505904[27] &&
!_theResult____h505904[26] &&
!_theResult____h505904[25] &&
!_theResult____h505904[24] &&
!_theResult____h505904[23] &&
!_theResult____h505904[22] &&
!_theResult____h505904[21] &&
!_theResult____h505904[20] &&
!_theResult____h505904[19] &&
!_theResult____h505904[18] &&
!_theResult____h505904[17] &&
!_theResult____h505904[16] &&
!_theResult____h505904[15] &&
!_theResult____h505904[14] &&
!_theResult____h505904[13] &&
!_theResult____h505904[12] &&
!_theResult____h505904[11] &&
!_theResult____h505904[10] &&
!_theResult____h505904[9] &&
!_theResult____h505904[8] &&
!_theResult____h505904[7] &&
!_theResult____h505904[6] &&
!_theResult____h505904[5] &&
!_theResult____h505904[4] &&
!_theResult____h505904[3] &&
!_theResult____h505904[2] &&
!_theResult____h505904[1] &&
!_theResult____h505904[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9009) ?
11'd0 :
_theResult___fst_exp__h514205 ;
assign _theResult___fst_exp__h514214 =
(!_theResult____h505904[56] && _theResult____h505904[55]) ?
11'd1 :
_theResult___fst_exp__h514211 ;
assign _theResult___fst_exp__h514969 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q212 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9174 ;
assign _theResult___fst_exp__h514972 =
(_theResult___fst_exp__h514140 == 11'd2047) ?
_theResult___fst_exp__h514140 :
_theResult___fst_exp__h514969 ;
assign _theResult___fst_exp__h522925 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ;
assign _theResult___fst_exp__h522964 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8695 } ;
assign _theResult___fst_exp__h522970 =
(f1_exp__h485175 == 8'd0 && !f1_sfd__h485176[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8668 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9059) ?
11'd0 :
_theResult___fst_exp__h522964 ;
assign _theResult___fst_exp__h522973 =
(f1_exp__h485175 == 8'd0) ?
_theResult___fst_exp__h522970 :
_theResult___fst_exp__h522925 ;
assign _theResult___fst_exp__h523753 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q214 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9205 ;
assign _theResult___fst_exp__h523756 =
(_theResult___fst_exp__h522973 == 11'd2047) ?
_theResult___fst_exp__h522973 :
_theResult___fst_exp__h523753 ;
assign _theResult___fst_exp__h523765 =
(f1_exp__h485175 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 ?
_theResult___snd_fst_exp__h505324 :
_theResult___fst_exp__h489490) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
_theResult___snd_fst_exp__h523759 :
_theResult___fst_exp__h489490) ;
assign _theResult___fst_exp__h523768 =
(f1_exp__h485175 == 8'd0 && f1_sfd__h485176 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h523765 ;
assign _theResult___fst_exp__h528343 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ;
assign _theResult___fst_exp__h543407 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10195 } ;
assign _theResult___fst_exp__h543413 =
(f2_exp__h524169 == 8'd0 && !f2_sfd__h524170[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10168 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10197) ?
11'd0 :
_theResult___fst_exp__h543407 ;
assign _theResult___fst_exp__h543416 =
(f2_exp__h524169 == 8'd0) ?
_theResult___fst_exp__h543413 :
11'd897 ;
assign _theResult___fst_exp__h544171 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q184 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10616 ;
assign _theResult___fst_exp__h544174 =
(_theResult___fst_exp__h543416 == 11'd2047) ?
_theResult___fst_exp__h543416 :
_theResult___fst_exp__h544171 ;
assign _theResult___fst_exp__h552993 =
_theResult____h544757[56] ?
11'd2 :
_theResult___fst_exp__h553067 ;
assign _theResult___fst_exp__h553058 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10492 } ;
assign _theResult___fst_exp__h553064 =
(!_theResult____h544757[56] && !_theResult____h544757[55] &&
!_theResult____h544757[54] &&
!_theResult____h544757[53] &&
!_theResult____h544757[52] &&
!_theResult____h544757[51] &&
!_theResult____h544757[50] &&
!_theResult____h544757[49] &&
!_theResult____h544757[48] &&
!_theResult____h544757[47] &&
!_theResult____h544757[46] &&
!_theResult____h544757[45] &&
!_theResult____h544757[44] &&
!_theResult____h544757[43] &&
!_theResult____h544757[42] &&
!_theResult____h544757[41] &&
!_theResult____h544757[40] &&
!_theResult____h544757[39] &&
!_theResult____h544757[38] &&
!_theResult____h544757[37] &&
!_theResult____h544757[36] &&
!_theResult____h544757[35] &&
!_theResult____h544757[34] &&
!_theResult____h544757[33] &&
!_theResult____h544757[32] &&
!_theResult____h544757[31] &&
!_theResult____h544757[30] &&
!_theResult____h544757[29] &&
!_theResult____h544757[28] &&
!_theResult____h544757[27] &&
!_theResult____h544757[26] &&
!_theResult____h544757[25] &&
!_theResult____h544757[24] &&
!_theResult____h544757[23] &&
!_theResult____h544757[22] &&
!_theResult____h544757[21] &&
!_theResult____h544757[20] &&
!_theResult____h544757[19] &&
!_theResult____h544757[18] &&
!_theResult____h544757[17] &&
!_theResult____h544757[16] &&
!_theResult____h544757[15] &&
!_theResult____h544757[14] &&
!_theResult____h544757[13] &&
!_theResult____h544757[12] &&
!_theResult____h544757[11] &&
!_theResult____h544757[10] &&
!_theResult____h544757[9] &&
!_theResult____h544757[8] &&
!_theResult____h544757[7] &&
!_theResult____h544757[6] &&
!_theResult____h544757[5] &&
!_theResult____h544757[4] &&
!_theResult____h544757[3] &&
!_theResult____h544757[2] &&
!_theResult____h544757[1] &&
!_theResult____h544757[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10494) ?
11'd0 :
_theResult___fst_exp__h553058 ;
assign _theResult___fst_exp__h553067 =
(!_theResult____h544757[56] && _theResult____h544757[55]) ?
11'd1 :
_theResult___fst_exp__h553064 ;
assign _theResult___fst_exp__h553822 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q186 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10654 ;
assign _theResult___fst_exp__h553825 =
(_theResult___fst_exp__h552993 == 11'd2047) ?
_theResult___fst_exp__h552993 :
_theResult___fst_exp__h553822 ;
assign _theResult___fst_exp__h561778 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ;
assign _theResult___fst_exp__h561817 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10195 } ;
assign _theResult___fst_exp__h561823 =
(f2_exp__h524169 == 8'd0 && !f2_sfd__h524170[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10168 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10544) ?
11'd0 :
_theResult___fst_exp__h561817 ;
assign _theResult___fst_exp__h561826 =
(f2_exp__h524169 == 8'd0) ?
_theResult___fst_exp__h561823 :
_theResult___fst_exp__h561778 ;
assign _theResult___fst_exp__h562606 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q188 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10685 ;
assign _theResult___fst_exp__h562609 =
(_theResult___fst_exp__h561826 == 11'd2047) ?
_theResult___fst_exp__h561826 :
_theResult___fst_exp__h562606 ;
assign _theResult___fst_exp__h562618 =
(f2_exp__h524169 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 ?
_theResult___snd_fst_exp__h544177 :
_theResult___fst_exp__h528343) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
_theResult___snd_fst_exp__h562612 :
_theResult___fst_exp__h528343) ;
assign _theResult___fst_exp__h562621 =
(f2_exp__h524169 == 8'd0 && f2_sfd__h524170 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h562618 ;
assign _theResult___fst_exp__h567647 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ;
assign _theResult___fst_exp__h582711 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9425 } ;
assign _theResult___fst_exp__h582717 =
(f3_exp__h563473 == 8'd0 && !f3_sfd__h563474[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9398 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9427) ?
11'd0 :
_theResult___fst_exp__h582711 ;
assign _theResult___fst_exp__h582720 =
(f3_exp__h563473 == 8'd0) ?
_theResult___fst_exp__h582717 :
11'd897 ;
assign _theResult___fst_exp__h583475 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q161 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9846 ;
assign _theResult___fst_exp__h583478 =
(_theResult___fst_exp__h582720 == 11'd2047) ?
_theResult___fst_exp__h582720 :
_theResult___fst_exp__h583475 ;
assign _theResult___fst_exp__h592297 =
_theResult____h584061[56] ?
11'd2 :
_theResult___fst_exp__h592371 ;
assign _theResult___fst_exp__h592362 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9722 } ;
assign _theResult___fst_exp__h592368 =
(!_theResult____h584061[56] && !_theResult____h584061[55] &&
!_theResult____h584061[54] &&
!_theResult____h584061[53] &&
!_theResult____h584061[52] &&
!_theResult____h584061[51] &&
!_theResult____h584061[50] &&
!_theResult____h584061[49] &&
!_theResult____h584061[48] &&
!_theResult____h584061[47] &&
!_theResult____h584061[46] &&
!_theResult____h584061[45] &&
!_theResult____h584061[44] &&
!_theResult____h584061[43] &&
!_theResult____h584061[42] &&
!_theResult____h584061[41] &&
!_theResult____h584061[40] &&
!_theResult____h584061[39] &&
!_theResult____h584061[38] &&
!_theResult____h584061[37] &&
!_theResult____h584061[36] &&
!_theResult____h584061[35] &&
!_theResult____h584061[34] &&
!_theResult____h584061[33] &&
!_theResult____h584061[32] &&
!_theResult____h584061[31] &&
!_theResult____h584061[30] &&
!_theResult____h584061[29] &&
!_theResult____h584061[28] &&
!_theResult____h584061[27] &&
!_theResult____h584061[26] &&
!_theResult____h584061[25] &&
!_theResult____h584061[24] &&
!_theResult____h584061[23] &&
!_theResult____h584061[22] &&
!_theResult____h584061[21] &&
!_theResult____h584061[20] &&
!_theResult____h584061[19] &&
!_theResult____h584061[18] &&
!_theResult____h584061[17] &&
!_theResult____h584061[16] &&
!_theResult____h584061[15] &&
!_theResult____h584061[14] &&
!_theResult____h584061[13] &&
!_theResult____h584061[12] &&
!_theResult____h584061[11] &&
!_theResult____h584061[10] &&
!_theResult____h584061[9] &&
!_theResult____h584061[8] &&
!_theResult____h584061[7] &&
!_theResult____h584061[6] &&
!_theResult____h584061[5] &&
!_theResult____h584061[4] &&
!_theResult____h584061[3] &&
!_theResult____h584061[2] &&
!_theResult____h584061[1] &&
!_theResult____h584061[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9724) ?
11'd0 :
_theResult___fst_exp__h592362 ;
assign _theResult___fst_exp__h592371 =
(!_theResult____h584061[56] && _theResult____h584061[55]) ?
11'd1 :
_theResult___fst_exp__h592368 ;
assign _theResult___fst_exp__h593126 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q190 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9884 ;
assign _theResult___fst_exp__h593129 =
(_theResult___fst_exp__h592297 == 11'd2047) ?
_theResult___fst_exp__h592297 :
_theResult___fst_exp__h593126 ;
assign _theResult___fst_exp__h601082 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ;
assign _theResult___fst_exp__h601121 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9425 } ;
assign _theResult___fst_exp__h601127 =
(f3_exp__h563473 == 8'd0 && !f3_sfd__h563474[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9398 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9774) ?
11'd0 :
_theResult___fst_exp__h601121 ;
assign _theResult___fst_exp__h601130 =
(f3_exp__h563473 == 8'd0) ?
_theResult___fst_exp__h601127 :
_theResult___fst_exp__h601082 ;
assign _theResult___fst_exp__h601910 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q192 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9915 ;
assign _theResult___fst_exp__h601913 =
(_theResult___fst_exp__h601130 == 11'd2047) ?
_theResult___fst_exp__h601130 :
_theResult___fst_exp__h601910 ;
assign _theResult___fst_exp__h601922 =
(f3_exp__h563473 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 ?
_theResult___snd_fst_exp__h583481 :
_theResult___fst_exp__h567647) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
_theResult___snd_fst_exp__h601916 :
_theResult___fst_exp__h567647) ;
assign _theResult___fst_exp__h601925 =
(f3_exp__h563473 == 8'd0 && f3_sfd__h563474 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h601922 ;
assign _theResult___fst_sfd__h357320 =
(_theResult___fst_exp__h356722 == 8'd255) ?
sfdin__h356716[56:34] :
_theResult___fst_sfd__h357317 ;
assign _theResult___fst_sfd__h365902 =
(_theResult___fst_exp__h365378 == 8'd255) ?
_theResult___snd__h365329[56:34] :
_theResult___fst_sfd__h365899 ;
assign _theResult___fst_sfd__h375086 =
(_theResult___fst_exp__h374488 == 8'd255) ?
sfdin__h374482[56:34] :
_theResult___fst_sfd__h375083 ;
assign _theResult___fst_sfd__h383722 =
(_theResult___fst_exp__h383173 == 8'd255) ?
_theResult___snd__h383119[56:34] :
_theResult___fst_sfd__h383719 ;
assign _theResult___fst_sfd__h383731 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
_theResult___snd_fst_sfd__h365905 :
_theResult___fst_sfd__h348594) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
_theResult___snd_fst_sfd__h383725 :
_theResult___fst_sfd__h348594) ;
assign _theResult___fst_sfd__h383737 =
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h383731 ;
assign _theResult___fst_sfd__h403017 =
(_theResult___fst_exp__h402419 == 8'd255) ?
sfdin__h402413[56:34] :
_theResult___fst_sfd__h403014 ;
assign _theResult___fst_sfd__h411599 =
(_theResult___fst_exp__h411075 == 8'd255) ?
_theResult___snd__h411026[56:34] :
_theResult___fst_sfd__h411596 ;
assign _theResult___fst_sfd__h420783 =
(_theResult___fst_exp__h420185 == 8'd255) ?
sfdin__h420179[56:34] :
_theResult___fst_sfd__h420780 ;
assign _theResult___fst_sfd__h429419 =
(_theResult___fst_exp__h428870 == 8'd255) ?
_theResult___snd__h428816[56:34] :
_theResult___fst_sfd__h429416 ;
assign _theResult___fst_sfd__h429428 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
_theResult___snd_fst_sfd__h411602 :
_theResult___fst_sfd__h394293) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
_theResult___snd_fst_sfd__h429422 :
_theResult___fst_sfd__h394293) ;
assign _theResult___fst_sfd__h429434 =
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h429428 ;
assign _theResult___fst_sfd__h448712 =
(_theResult___fst_exp__h448114 == 8'd255) ?
sfdin__h448108[56:34] :
_theResult___fst_sfd__h448709 ;
assign _theResult___fst_sfd__h457294 =
(_theResult___fst_exp__h456770 == 8'd255) ?
_theResult___snd__h456721[56:34] :
_theResult___fst_sfd__h457291 ;
assign _theResult___fst_sfd__h466478 =
(_theResult___fst_exp__h465880 == 8'd255) ?
sfdin__h465874[56:34] :
_theResult___fst_sfd__h466475 ;
assign _theResult___fst_sfd__h475114 =
(_theResult___fst_exp__h474565 == 8'd255) ?
_theResult___snd__h474511[56:34] :
_theResult___fst_sfd__h475111 ;
assign _theResult___fst_sfd__h475123 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
_theResult___snd_fst_sfd__h457297 :
_theResult___fst_sfd__h439988) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
_theResult___snd_fst_sfd__h475117 :
_theResult___fst_sfd__h439988) ;
assign _theResult___fst_sfd__h475129 =
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h475123 ;
assign _theResult___fst_sfd__h489491 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ;
assign _theResult___fst_sfd__h505319 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q216 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9231 ;
assign _theResult___fst_sfd__h505322 =
(_theResult___fst_exp__h504563 == 11'd2047) ?
_theResult___snd__h504514[56:5] :
_theResult___fst_sfd__h505319 ;
assign _theResult___fst_sfd__h514970 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q218 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9258 ;
assign _theResult___fst_sfd__h514973 =
(_theResult___fst_exp__h514140 == 11'd2047) ?
sfdin__h514134[56:5] :
_theResult___fst_sfd__h514970 ;
assign _theResult___fst_sfd__h523754 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q220 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9277 ;
assign _theResult___fst_sfd__h523757 =
(_theResult___fst_exp__h522973 == 11'd2047) ?
_theResult___snd__h522919[56:5] :
_theResult___fst_sfd__h523754 ;
assign _theResult___fst_sfd__h523766 =
(f1_exp__h485175 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8622 ?
_theResult___snd_fst_sfd__h505325 :
_theResult___fst_sfd__h489491) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
_theResult___snd_fst_sfd__h523760 :
_theResult___fst_sfd__h489491) ;
assign _theResult___fst_sfd__h523772 =
((f1_exp__h485175 == 8'd255 || f1_exp__h485175 == 8'd0) &&
f1_sfd__h485176 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h523766 ;
assign _theResult___fst_sfd__h528344 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ;
assign _theResult___fst_sfd__h544172 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q206 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10711 ;
assign _theResult___fst_sfd__h544175 =
(_theResult___fst_exp__h543416 == 11'd2047) ?
_theResult___snd__h543367[56:5] :
_theResult___fst_sfd__h544172 ;
assign _theResult___fst_sfd__h553823 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q208 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10737 ;
assign _theResult___fst_sfd__h553826 =
(_theResult___fst_exp__h552993 == 11'd2047) ?
sfdin__h552987[56:5] :
_theResult___fst_sfd__h553823 ;
assign _theResult___fst_sfd__h562607 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q210 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10756 ;
assign _theResult___fst_sfd__h562610 =
(_theResult___fst_exp__h561826 == 11'd2047) ?
_theResult___snd__h561772[56:5] :
_theResult___fst_sfd__h562607 ;
assign _theResult___fst_sfd__h562619 =
(f2_exp__h524169 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10122 ?
_theResult___snd_fst_sfd__h544178 :
_theResult___fst_sfd__h528344) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
_theResult___snd_fst_sfd__h562613 :
_theResult___fst_sfd__h528344) ;
assign _theResult___fst_sfd__h562625 =
((f2_exp__h524169 == 8'd255 || f2_exp__h524169 == 8'd0) &&
f2_sfd__h524170 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h562619 ;
assign _theResult___fst_sfd__h567648 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 ;
assign _theResult___fst_sfd__h583476 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q222 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9941 ;
assign _theResult___fst_sfd__h583479 =
(_theResult___fst_exp__h582720 == 11'd2047) ?
_theResult___snd__h582671[56:5] :
_theResult___fst_sfd__h583476 ;
assign _theResult___fst_sfd__h593127 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q224 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9967 ;
assign _theResult___fst_sfd__h593130 =
(_theResult___fst_exp__h592297 == 11'd2047) ?
sfdin__h592291[56:5] :
_theResult___fst_sfd__h593127 ;
assign _theResult___fst_sfd__h601911 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q226 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9986 ;
assign _theResult___fst_sfd__h601914 =
(_theResult___fst_exp__h601130 == 11'd2047) ?
_theResult___snd__h601076[56:5] :
_theResult___fst_sfd__h601911 ;
assign _theResult___fst_sfd__h601923 =
(f3_exp__h563473 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9352 ?
_theResult___snd_fst_sfd__h583482 :
_theResult___fst_sfd__h567648) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
_theResult___snd_fst_sfd__h601917 :
_theResult___fst_sfd__h567648) ;
assign _theResult___fst_sfd__h601929 =
((f3_exp__h563473 == 8'd255 || f3_exp__h563473 == 8'd0) &&
f3_sfd__h563474 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h601923 ;
assign _theResult___sfd__h357239 =
sfd__h356814[24] ?
((_theResult___fst_exp__h356722 == 8'd254) ?
23'd0 :
sfd__h356814[23:1]) :
sfd__h356814[22:0] ;
assign _theResult___sfd__h365821 =
sfd__h365396[24] ?
((_theResult___fst_exp__h365378 == 8'd254) ?
23'd0 :
sfd__h365396[23:1]) :
sfd__h365396[22:0] ;
assign _theResult___sfd__h375005 =
sfd__h374580[24] ?
((_theResult___fst_exp__h374488 == 8'd254) ?
23'd0 :
sfd__h374580[23:1]) :
sfd__h374580[22:0] ;
assign _theResult___sfd__h383641 =
sfd__h383192[24] ?
((_theResult___fst_exp__h383173 == 8'd254) ?
23'd0 :
sfd__h383192[23:1]) :
sfd__h383192[22:0] ;
assign _theResult___sfd__h383743 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h340956 :
_theResult___fst_sfd__h383737 ;
assign _theResult___sfd__h402936 =
sfd__h402511[24] ?
((_theResult___fst_exp__h402419 == 8'd254) ?
23'd0 :
sfd__h402511[23:1]) :
sfd__h402511[22:0] ;
assign _theResult___sfd__h411518 =
sfd__h411093[24] ?
((_theResult___fst_exp__h411075 == 8'd254) ?
23'd0 :
sfd__h411093[23:1]) :
sfd__h411093[22:0] ;
assign _theResult___sfd__h420702 =
sfd__h420277[24] ?
((_theResult___fst_exp__h420185 == 8'd254) ?
23'd0 :
sfd__h420277[23:1]) :
sfd__h420277[22:0] ;
assign _theResult___sfd__h429338 =
sfd__h428889[24] ?
((_theResult___fst_exp__h428870 == 8'd254) ?
23'd0 :
sfd__h428889[23:1]) :
sfd__h428889[22:0] ;
assign _theResult___sfd__h429440 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h386658 :
_theResult___fst_sfd__h429434 ;
assign _theResult___sfd__h448631 =
sfd__h448206[24] ?
((_theResult___fst_exp__h448114 == 8'd254) ?
23'd0 :
sfd__h448206[23:1]) :
sfd__h448206[22:0] ;
assign _theResult___sfd__h457213 =
sfd__h456788[24] ?
((_theResult___fst_exp__h456770 == 8'd254) ?
23'd0 :
sfd__h456788[23:1]) :
sfd__h456788[22:0] ;
assign _theResult___sfd__h466397 =
sfd__h465972[24] ?
((_theResult___fst_exp__h465880 == 8'd254) ?
23'd0 :
sfd__h465972[23:1]) :
sfd__h465972[22:0] ;
assign _theResult___sfd__h475033 =
sfd__h474584[24] ?
((_theResult___fst_exp__h474565 == 8'd254) ?
23'd0 :
sfd__h474584[23:1]) :
sfd__h474584[22:0] ;
assign _theResult___sfd__h475135 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h432353 :
_theResult___fst_sfd__h475129 ;
assign _theResult___sfd__h505219 =
sfd__h504581[53] ?
((_theResult___fst_exp__h504563 == 11'd2046) ?
52'd0 :
sfd__h504581[52:1]) :
sfd__h504581[51:0] ;
assign _theResult___sfd__h514870 =
sfd__h514232[53] ?
((_theResult___fst_exp__h514140 == 11'd2046) ?
52'd0 :
sfd__h514232[52:1]) :
sfd__h514232[51:0] ;
assign _theResult___sfd__h523654 =
sfd__h522992[53] ?
((_theResult___fst_exp__h522973 == 11'd2046) ?
52'd0 :
sfd__h522992[52:1]) :
sfd__h522992[51:0] ;
assign _theResult___sfd__h544072 =
sfd__h543434[53] ?
((_theResult___fst_exp__h543416 == 11'd2046) ?
52'd0 :
sfd__h543434[52:1]) :
sfd__h543434[51:0] ;
assign _theResult___sfd__h553723 =
sfd__h553085[53] ?
((_theResult___fst_exp__h552993 == 11'd2046) ?
52'd0 :
sfd__h553085[52:1]) :
sfd__h553085[51:0] ;
assign _theResult___sfd__h562507 =
sfd__h561845[53] ?
((_theResult___fst_exp__h561826 == 11'd2046) ?
52'd0 :
sfd__h561845[52:1]) :
sfd__h561845[51:0] ;
assign _theResult___sfd__h583376 =
sfd__h582738[53] ?
((_theResult___fst_exp__h582720 == 11'd2046) ?
52'd0 :
sfd__h582738[52:1]) :
sfd__h582738[51:0] ;
assign _theResult___sfd__h593027 =
sfd__h592389[53] ?
((_theResult___fst_exp__h592297 == 11'd2046) ?
52'd0 :
sfd__h592389[52:1]) :
sfd__h592389[51:0] ;
assign _theResult___sfd__h601811 =
sfd__h601149[53] ?
((_theResult___fst_exp__h601130 == 11'd2046) ?
52'd0 :
sfd__h601149[52:1]) :
sfd__h601149[51:0] ;
assign _theResult___snd__h356733 = { _theResult____h348611[55:0], 1'd0 } ;
assign _theResult___snd__h356744 =
(!_theResult____h348611[56] && _theResult____h348611[55]) ?
_theResult___snd__h356746 :
_theResult___snd__h356756 ;
assign _theResult___snd__h356746 = { _theResult____h348611[54:0], 2'd0 } ;
assign _theResult___snd__h356756 =
(!_theResult____h348611[56] && !_theResult____h348611[55] &&
!_theResult____h348611[54] &&
!_theResult____h348611[53] &&
!_theResult____h348611[52] &&
!_theResult____h348611[51] &&
!_theResult____h348611[50] &&
!_theResult____h348611[49] &&
!_theResult____h348611[48] &&
!_theResult____h348611[47] &&
!_theResult____h348611[46] &&
!_theResult____h348611[45] &&
!_theResult____h348611[44] &&
!_theResult____h348611[43] &&
!_theResult____h348611[42] &&
!_theResult____h348611[41] &&
!_theResult____h348611[40] &&
!_theResult____h348611[39] &&
!_theResult____h348611[38] &&
!_theResult____h348611[37] &&
!_theResult____h348611[36] &&
!_theResult____h348611[35] &&
!_theResult____h348611[34] &&
!_theResult____h348611[33] &&
!_theResult____h348611[32] &&
!_theResult____h348611[31] &&
!_theResult____h348611[30] &&
!_theResult____h348611[29] &&
!_theResult____h348611[28] &&
!_theResult____h348611[27] &&
!_theResult____h348611[26] &&
!_theResult____h348611[25] &&
!_theResult____h348611[24] &&
!_theResult____h348611[23] &&
!_theResult____h348611[22] &&
!_theResult____h348611[21] &&
!_theResult____h348611[20] &&
!_theResult____h348611[19] &&
!_theResult____h348611[18] &&
!_theResult____h348611[17] &&
!_theResult____h348611[16] &&
!_theResult____h348611[15] &&
!_theResult____h348611[14] &&
!_theResult____h348611[13] &&
!_theResult____h348611[12] &&
!_theResult____h348611[11] &&
!_theResult____h348611[10] &&
!_theResult____h348611[9] &&
!_theResult____h348611[8] &&
!_theResult____h348611[7] &&
!_theResult____h348611[6] &&
!_theResult____h348611[5] &&
!_theResult____h348611[4] &&
!_theResult____h348611[3] &&
!_theResult____h348611[2] &&
!_theResult____h348611[1] &&
!_theResult____h348611[0]) ?
_theResult____h348611 :
_theResult___snd__h356762 ;
assign _theResult___snd__h356762 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29[54:0],
2'd0 } ;
assign _theResult___snd__h356785 =
_theResult____h348611 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4344 ;
assign _theResult___snd__h365329 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___snd__h365338 :
_theResult___snd__h365331 ;
assign _theResult___snd__h365331 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h365338 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4520) ?
sfd__h341006 :
_theResult___snd__h365344 ;
assign _theResult___snd__h365344 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31[54:0],
2'd0 } ;
assign _theResult___snd__h365367 =
sfd__h341006 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4575 ;
assign _theResult___snd__h374499 = { _theResult____h366250[55:0], 1'd0 } ;
assign _theResult___snd__h374510 =
(!_theResult____h366250[56] && _theResult____h366250[55]) ?
_theResult___snd__h374512 :
_theResult___snd__h374522 ;
assign _theResult___snd__h374512 = { _theResult____h366250[54:0], 2'd0 } ;
assign _theResult___snd__h374522 =
(!_theResult____h366250[56] && !_theResult____h366250[55] &&
!_theResult____h366250[54] &&
!_theResult____h366250[53] &&
!_theResult____h366250[52] &&
!_theResult____h366250[51] &&
!_theResult____h366250[50] &&
!_theResult____h366250[49] &&
!_theResult____h366250[48] &&
!_theResult____h366250[47] &&
!_theResult____h366250[46] &&
!_theResult____h366250[45] &&
!_theResult____h366250[44] &&
!_theResult____h366250[43] &&
!_theResult____h366250[42] &&
!_theResult____h366250[41] &&
!_theResult____h366250[40] &&
!_theResult____h366250[39] &&
!_theResult____h366250[38] &&
!_theResult____h366250[37] &&
!_theResult____h366250[36] &&
!_theResult____h366250[35] &&
!_theResult____h366250[34] &&
!_theResult____h366250[33] &&
!_theResult____h366250[32] &&
!_theResult____h366250[31] &&
!_theResult____h366250[30] &&
!_theResult____h366250[29] &&
!_theResult____h366250[28] &&
!_theResult____h366250[27] &&
!_theResult____h366250[26] &&
!_theResult____h366250[25] &&
!_theResult____h366250[24] &&
!_theResult____h366250[23] &&
!_theResult____h366250[22] &&
!_theResult____h366250[21] &&
!_theResult____h366250[20] &&
!_theResult____h366250[19] &&
!_theResult____h366250[18] &&
!_theResult____h366250[17] &&
!_theResult____h366250[16] &&
!_theResult____h366250[15] &&
!_theResult____h366250[14] &&
!_theResult____h366250[13] &&
!_theResult____h366250[12] &&
!_theResult____h366250[11] &&
!_theResult____h366250[10] &&
!_theResult____h366250[9] &&
!_theResult____h366250[8] &&
!_theResult____h366250[7] &&
!_theResult____h366250[6] &&
!_theResult____h366250[5] &&
!_theResult____h366250[4] &&
!_theResult____h366250[3] &&
!_theResult____h366250[2] &&
!_theResult____h366250[1] &&
!_theResult____h366250[0]) ?
_theResult____h366250 :
_theResult___snd__h374528 ;
assign _theResult___snd__h374528 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39[54:0],
2'd0 } ;
assign _theResult___snd__h374551 =
_theResult____h366250 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4895 ;
assign _theResult___snd__h383119 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___snd__h383133 :
_theResult___snd__h365331 ;
assign _theResult___snd__h383133 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4520) ?
sfd__h341006 :
_theResult___snd__h383139 ;
assign _theResult___snd__h383139 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44[54:0],
2'd0 } ;
assign _theResult___snd__h383157 =
sfd__h341006 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4969[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4969) ;
assign _theResult___snd__h402430 = { _theResult____h394310[55:0], 1'd0 } ;
assign _theResult___snd__h402441 =
(!_theResult____h394310[56] && _theResult____h394310[55]) ?
_theResult___snd__h402443 :
_theResult___snd__h402453 ;
assign _theResult___snd__h402443 = { _theResult____h394310[54:0], 2'd0 } ;
assign _theResult___snd__h402453 =
(!_theResult____h394310[56] && !_theResult____h394310[55] &&
!_theResult____h394310[54] &&
!_theResult____h394310[53] &&
!_theResult____h394310[52] &&
!_theResult____h394310[51] &&
!_theResult____h394310[50] &&
!_theResult____h394310[49] &&
!_theResult____h394310[48] &&
!_theResult____h394310[47] &&
!_theResult____h394310[46] &&
!_theResult____h394310[45] &&
!_theResult____h394310[44] &&
!_theResult____h394310[43] &&
!_theResult____h394310[42] &&
!_theResult____h394310[41] &&
!_theResult____h394310[40] &&
!_theResult____h394310[39] &&
!_theResult____h394310[38] &&
!_theResult____h394310[37] &&
!_theResult____h394310[36] &&
!_theResult____h394310[35] &&
!_theResult____h394310[34] &&
!_theResult____h394310[33] &&
!_theResult____h394310[32] &&
!_theResult____h394310[31] &&
!_theResult____h394310[30] &&
!_theResult____h394310[29] &&
!_theResult____h394310[28] &&
!_theResult____h394310[27] &&
!_theResult____h394310[26] &&
!_theResult____h394310[25] &&
!_theResult____h394310[24] &&
!_theResult____h394310[23] &&
!_theResult____h394310[22] &&
!_theResult____h394310[21] &&
!_theResult____h394310[20] &&
!_theResult____h394310[19] &&
!_theResult____h394310[18] &&
!_theResult____h394310[17] &&
!_theResult____h394310[16] &&
!_theResult____h394310[15] &&
!_theResult____h394310[14] &&
!_theResult____h394310[13] &&
!_theResult____h394310[12] &&
!_theResult____h394310[11] &&
!_theResult____h394310[10] &&
!_theResult____h394310[9] &&
!_theResult____h394310[8] &&
!_theResult____h394310[7] &&
!_theResult____h394310[6] &&
!_theResult____h394310[5] &&
!_theResult____h394310[4] &&
!_theResult____h394310[3] &&
!_theResult____h394310[2] &&
!_theResult____h394310[1] &&
!_theResult____h394310[0]) ?
_theResult____h394310 :
_theResult___snd__h402459 ;
assign _theResult___snd__h402459 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64[54:0],
2'd0 } ;
assign _theResult___snd__h402482 =
_theResult____h394310 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5736 ;
assign _theResult___snd__h411026 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___snd__h411035 :
_theResult___snd__h411028 ;
assign _theResult___snd__h411028 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h411035 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5912) ?
sfd__h386708 :
_theResult___snd__h411041 ;
assign _theResult___snd__h411041 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66[54:0],
2'd0 } ;
assign _theResult___snd__h411064 =
sfd__h386708 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5967 ;
assign _theResult___snd__h420196 = { _theResult____h411947[55:0], 1'd0 } ;
assign _theResult___snd__h420207 =
(!_theResult____h411947[56] && _theResult____h411947[55]) ?
_theResult___snd__h420209 :
_theResult___snd__h420219 ;
assign _theResult___snd__h420209 = { _theResult____h411947[54:0], 2'd0 } ;
assign _theResult___snd__h420219 =
(!_theResult____h411947[56] && !_theResult____h411947[55] &&
!_theResult____h411947[54] &&
!_theResult____h411947[53] &&
!_theResult____h411947[52] &&
!_theResult____h411947[51] &&
!_theResult____h411947[50] &&
!_theResult____h411947[49] &&
!_theResult____h411947[48] &&
!_theResult____h411947[47] &&
!_theResult____h411947[46] &&
!_theResult____h411947[45] &&
!_theResult____h411947[44] &&
!_theResult____h411947[43] &&
!_theResult____h411947[42] &&
!_theResult____h411947[41] &&
!_theResult____h411947[40] &&
!_theResult____h411947[39] &&
!_theResult____h411947[38] &&
!_theResult____h411947[37] &&
!_theResult____h411947[36] &&
!_theResult____h411947[35] &&
!_theResult____h411947[34] &&
!_theResult____h411947[33] &&
!_theResult____h411947[32] &&
!_theResult____h411947[31] &&
!_theResult____h411947[30] &&
!_theResult____h411947[29] &&
!_theResult____h411947[28] &&
!_theResult____h411947[27] &&
!_theResult____h411947[26] &&
!_theResult____h411947[25] &&
!_theResult____h411947[24] &&
!_theResult____h411947[23] &&
!_theResult____h411947[22] &&
!_theResult____h411947[21] &&
!_theResult____h411947[20] &&
!_theResult____h411947[19] &&
!_theResult____h411947[18] &&
!_theResult____h411947[17] &&
!_theResult____h411947[16] &&
!_theResult____h411947[15] &&
!_theResult____h411947[14] &&
!_theResult____h411947[13] &&
!_theResult____h411947[12] &&
!_theResult____h411947[11] &&
!_theResult____h411947[10] &&
!_theResult____h411947[9] &&
!_theResult____h411947[8] &&
!_theResult____h411947[7] &&
!_theResult____h411947[6] &&
!_theResult____h411947[5] &&
!_theResult____h411947[4] &&
!_theResult____h411947[3] &&
!_theResult____h411947[2] &&
!_theResult____h411947[1] &&
!_theResult____h411947[0]) ?
_theResult____h411947 :
_theResult___snd__h420225 ;
assign _theResult___snd__h420225 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74[54:0],
2'd0 } ;
assign _theResult___snd__h420248 =
_theResult____h411947 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6287 ;
assign _theResult___snd__h428816 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___snd__h428830 :
_theResult___snd__h411028 ;
assign _theResult___snd__h428830 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5912) ?
sfd__h386708 :
_theResult___snd__h428836 ;
assign _theResult___snd__h428836 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79[54:0],
2'd0 } ;
assign _theResult___snd__h428854 =
sfd__h386708 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6361[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6361) ;
assign _theResult___snd__h448125 = { _theResult____h440005[55:0], 1'd0 } ;
assign _theResult___snd__h448136 =
(!_theResult____h440005[56] && _theResult____h440005[55]) ?
_theResult___snd__h448138 :
_theResult___snd__h448148 ;
assign _theResult___snd__h448138 = { _theResult____h440005[54:0], 2'd0 } ;
assign _theResult___snd__h448148 =
(!_theResult____h440005[56] && !_theResult____h440005[55] &&
!_theResult____h440005[54] &&
!_theResult____h440005[53] &&
!_theResult____h440005[52] &&
!_theResult____h440005[51] &&
!_theResult____h440005[50] &&
!_theResult____h440005[49] &&
!_theResult____h440005[48] &&
!_theResult____h440005[47] &&
!_theResult____h440005[46] &&
!_theResult____h440005[45] &&
!_theResult____h440005[44] &&
!_theResult____h440005[43] &&
!_theResult____h440005[42] &&
!_theResult____h440005[41] &&
!_theResult____h440005[40] &&
!_theResult____h440005[39] &&
!_theResult____h440005[38] &&
!_theResult____h440005[37] &&
!_theResult____h440005[36] &&
!_theResult____h440005[35] &&
!_theResult____h440005[34] &&
!_theResult____h440005[33] &&
!_theResult____h440005[32] &&
!_theResult____h440005[31] &&
!_theResult____h440005[30] &&
!_theResult____h440005[29] &&
!_theResult____h440005[28] &&
!_theResult____h440005[27] &&
!_theResult____h440005[26] &&
!_theResult____h440005[25] &&
!_theResult____h440005[24] &&
!_theResult____h440005[23] &&
!_theResult____h440005[22] &&
!_theResult____h440005[21] &&
!_theResult____h440005[20] &&
!_theResult____h440005[19] &&
!_theResult____h440005[18] &&
!_theResult____h440005[17] &&
!_theResult____h440005[16] &&
!_theResult____h440005[15] &&
!_theResult____h440005[14] &&
!_theResult____h440005[13] &&
!_theResult____h440005[12] &&
!_theResult____h440005[11] &&
!_theResult____h440005[10] &&
!_theResult____h440005[9] &&
!_theResult____h440005[8] &&
!_theResult____h440005[7] &&
!_theResult____h440005[6] &&
!_theResult____h440005[5] &&
!_theResult____h440005[4] &&
!_theResult____h440005[3] &&
!_theResult____h440005[2] &&
!_theResult____h440005[1] &&
!_theResult____h440005[0]) ?
_theResult____h440005 :
_theResult___snd__h448154 ;
assign _theResult___snd__h448154 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99[54:0],
2'd0 } ;
assign _theResult___snd__h448177 =
_theResult____h440005 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7128 ;
assign _theResult___snd__h456721 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___snd__h456730 :
_theResult___snd__h456723 ;
assign _theResult___snd__h456723 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h456730 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7304) ?
sfd__h432403 :
_theResult___snd__h456736 ;
assign _theResult___snd__h456736 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101[54:0],
2'd0 } ;
assign _theResult___snd__h456759 =
sfd__h432403 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7359 ;
assign _theResult___snd__h465891 = { _theResult____h457642[55:0], 1'd0 } ;
assign _theResult___snd__h465902 =
(!_theResult____h457642[56] && _theResult____h457642[55]) ?
_theResult___snd__h465904 :
_theResult___snd__h465914 ;
assign _theResult___snd__h465904 = { _theResult____h457642[54:0], 2'd0 } ;
assign _theResult___snd__h465914 =
(!_theResult____h457642[56] && !_theResult____h457642[55] &&
!_theResult____h457642[54] &&
!_theResult____h457642[53] &&
!_theResult____h457642[52] &&
!_theResult____h457642[51] &&
!_theResult____h457642[50] &&
!_theResult____h457642[49] &&
!_theResult____h457642[48] &&
!_theResult____h457642[47] &&
!_theResult____h457642[46] &&
!_theResult____h457642[45] &&
!_theResult____h457642[44] &&
!_theResult____h457642[43] &&
!_theResult____h457642[42] &&
!_theResult____h457642[41] &&
!_theResult____h457642[40] &&
!_theResult____h457642[39] &&
!_theResult____h457642[38] &&
!_theResult____h457642[37] &&
!_theResult____h457642[36] &&
!_theResult____h457642[35] &&
!_theResult____h457642[34] &&
!_theResult____h457642[33] &&
!_theResult____h457642[32] &&
!_theResult____h457642[31] &&
!_theResult____h457642[30] &&
!_theResult____h457642[29] &&
!_theResult____h457642[28] &&
!_theResult____h457642[27] &&
!_theResult____h457642[26] &&
!_theResult____h457642[25] &&
!_theResult____h457642[24] &&
!_theResult____h457642[23] &&
!_theResult____h457642[22] &&
!_theResult____h457642[21] &&
!_theResult____h457642[20] &&
!_theResult____h457642[19] &&
!_theResult____h457642[18] &&
!_theResult____h457642[17] &&
!_theResult____h457642[16] &&
!_theResult____h457642[15] &&
!_theResult____h457642[14] &&
!_theResult____h457642[13] &&
!_theResult____h457642[12] &&
!_theResult____h457642[11] &&
!_theResult____h457642[10] &&
!_theResult____h457642[9] &&
!_theResult____h457642[8] &&
!_theResult____h457642[7] &&
!_theResult____h457642[6] &&
!_theResult____h457642[5] &&
!_theResult____h457642[4] &&
!_theResult____h457642[3] &&
!_theResult____h457642[2] &&
!_theResult____h457642[1] &&
!_theResult____h457642[0]) ?
_theResult____h457642 :
_theResult___snd__h465920 ;
assign _theResult___snd__h465920 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109[54:0],
2'd0 } ;
assign _theResult___snd__h465943 =
_theResult____h457642 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7679 ;
assign _theResult___snd__h474511 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___snd__h474525 :
_theResult___snd__h456723 ;
assign _theResult___snd__h474525 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7304) ?
sfd__h432403 :
_theResult___snd__h474531 ;
assign _theResult___snd__h474531 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114[54:0],
2'd0 } ;
assign _theResult___snd__h474549 =
sfd__h432403 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7753[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7753) ;
assign _theResult___snd__h504514 =
(f1_exp__h485175 == 8'd0) ?
_theResult___snd__h504523 :
_theResult___snd__h504516 ;
assign _theResult___snd__h504516 = { f1_sfd__h485176, 34'd0 } ;
assign _theResult___snd__h504523 =
(f1_exp__h485175 == 8'd0 && !f1_sfd__h485176[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8668) ?
sfd__h485537 :
_theResult___snd__h504529 ;
assign _theResult___snd__h504529 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0],
2'd0 } ;
assign _theResult___snd__h504552 =
sfd__h485537 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8695 ;
assign _theResult___snd__h514151 = { _theResult____h505904[55:0], 1'd0 } ;
assign _theResult___snd__h514162 =
(!_theResult____h505904[56] && _theResult____h505904[55]) ?
_theResult___snd__h514164 :
_theResult___snd__h514174 ;
assign _theResult___snd__h514164 = { _theResult____h505904[54:0], 2'd0 } ;
assign _theResult___snd__h514174 =
(!_theResult____h505904[56] && !_theResult____h505904[55] &&
!_theResult____h505904[54] &&
!_theResult____h505904[53] &&
!_theResult____h505904[52] &&
!_theResult____h505904[51] &&
!_theResult____h505904[50] &&
!_theResult____h505904[49] &&
!_theResult____h505904[48] &&
!_theResult____h505904[47] &&
!_theResult____h505904[46] &&
!_theResult____h505904[45] &&
!_theResult____h505904[44] &&
!_theResult____h505904[43] &&
!_theResult____h505904[42] &&
!_theResult____h505904[41] &&
!_theResult____h505904[40] &&
!_theResult____h505904[39] &&
!_theResult____h505904[38] &&
!_theResult____h505904[37] &&
!_theResult____h505904[36] &&
!_theResult____h505904[35] &&
!_theResult____h505904[34] &&
!_theResult____h505904[33] &&
!_theResult____h505904[32] &&
!_theResult____h505904[31] &&
!_theResult____h505904[30] &&
!_theResult____h505904[29] &&
!_theResult____h505904[28] &&
!_theResult____h505904[27] &&
!_theResult____h505904[26] &&
!_theResult____h505904[25] &&
!_theResult____h505904[24] &&
!_theResult____h505904[23] &&
!_theResult____h505904[22] &&
!_theResult____h505904[21] &&
!_theResult____h505904[20] &&
!_theResult____h505904[19] &&
!_theResult____h505904[18] &&
!_theResult____h505904[17] &&
!_theResult____h505904[16] &&
!_theResult____h505904[15] &&
!_theResult____h505904[14] &&
!_theResult____h505904[13] &&
!_theResult____h505904[12] &&
!_theResult____h505904[11] &&
!_theResult____h505904[10] &&
!_theResult____h505904[9] &&
!_theResult____h505904[8] &&
!_theResult____h505904[7] &&
!_theResult____h505904[6] &&
!_theResult____h505904[5] &&
!_theResult____h505904[4] &&
!_theResult____h505904[3] &&
!_theResult____h505904[2] &&
!_theResult____h505904[1] &&
!_theResult____h505904[0]) ?
_theResult____h505904 :
_theResult___snd__h514180 ;
assign _theResult___snd__h514180 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0],
2'd0 } ;
assign _theResult___snd__h514203 =
_theResult____h505904 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9007 ;
assign _theResult___snd__h522919 =
(f1_exp__h485175 == 8'd0) ?
_theResult___snd__h522933 :
_theResult___snd__h504516 ;
assign _theResult___snd__h522933 =
(f1_exp__h485175 == 8'd0 && !f1_sfd__h485176[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8668) ?
sfd__h485537 :
_theResult___snd__h522939 ;
assign _theResult___snd__h522939 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0],
2'd0 } ;
assign _theResult___snd__h522957 =
sfd__h485537 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9058 ;
assign _theResult___snd__h543367 =
(f2_exp__h524169 == 8'd0) ?
_theResult___snd__h543376 :
_theResult___snd__h543369 ;
assign _theResult___snd__h543369 = { f2_sfd__h524170, 34'd0 } ;
assign _theResult___snd__h543376 =
(f2_exp__h524169 == 8'd0 && !f2_sfd__h524170[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10168) ?
sfd__h524531 :
_theResult___snd__h543382 ;
assign _theResult___snd__h543382 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0],
2'd0 } ;
assign _theResult___snd__h543405 =
sfd__h524531 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10195 ;
assign _theResult___snd__h553004 = { _theResult____h544757[55:0], 1'd0 } ;
assign _theResult___snd__h553015 =
(!_theResult____h544757[56] && _theResult____h544757[55]) ?
_theResult___snd__h553017 :
_theResult___snd__h553027 ;
assign _theResult___snd__h553017 = { _theResult____h544757[54:0], 2'd0 } ;
assign _theResult___snd__h553027 =
(!_theResult____h544757[56] && !_theResult____h544757[55] &&
!_theResult____h544757[54] &&
!_theResult____h544757[53] &&
!_theResult____h544757[52] &&
!_theResult____h544757[51] &&
!_theResult____h544757[50] &&
!_theResult____h544757[49] &&
!_theResult____h544757[48] &&
!_theResult____h544757[47] &&
!_theResult____h544757[46] &&
!_theResult____h544757[45] &&
!_theResult____h544757[44] &&
!_theResult____h544757[43] &&
!_theResult____h544757[42] &&
!_theResult____h544757[41] &&
!_theResult____h544757[40] &&
!_theResult____h544757[39] &&
!_theResult____h544757[38] &&
!_theResult____h544757[37] &&
!_theResult____h544757[36] &&
!_theResult____h544757[35] &&
!_theResult____h544757[34] &&
!_theResult____h544757[33] &&
!_theResult____h544757[32] &&
!_theResult____h544757[31] &&
!_theResult____h544757[30] &&
!_theResult____h544757[29] &&
!_theResult____h544757[28] &&
!_theResult____h544757[27] &&
!_theResult____h544757[26] &&
!_theResult____h544757[25] &&
!_theResult____h544757[24] &&
!_theResult____h544757[23] &&
!_theResult____h544757[22] &&
!_theResult____h544757[21] &&
!_theResult____h544757[20] &&
!_theResult____h544757[19] &&
!_theResult____h544757[18] &&
!_theResult____h544757[17] &&
!_theResult____h544757[16] &&
!_theResult____h544757[15] &&
!_theResult____h544757[14] &&
!_theResult____h544757[13] &&
!_theResult____h544757[12] &&
!_theResult____h544757[11] &&
!_theResult____h544757[10] &&
!_theResult____h544757[9] &&
!_theResult____h544757[8] &&
!_theResult____h544757[7] &&
!_theResult____h544757[6] &&
!_theResult____h544757[5] &&
!_theResult____h544757[4] &&
!_theResult____h544757[3] &&
!_theResult____h544757[2] &&
!_theResult____h544757[1] &&
!_theResult____h544757[0]) ?
_theResult____h544757 :
_theResult___snd__h553033 ;
assign _theResult___snd__h553033 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0],
2'd0 } ;
assign _theResult___snd__h553056 =
_theResult____h544757 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10492 ;
assign _theResult___snd__h561772 =
(f2_exp__h524169 == 8'd0) ?
_theResult___snd__h561786 :
_theResult___snd__h543369 ;
assign _theResult___snd__h561786 =
(f2_exp__h524169 == 8'd0 && !f2_sfd__h524170[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10168) ?
sfd__h524531 :
_theResult___snd__h561792 ;
assign _theResult___snd__h561792 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0],
2'd0 } ;
assign _theResult___snd__h561810 =
sfd__h524531 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10543 ;
assign _theResult___snd__h582671 =
(f3_exp__h563473 == 8'd0) ?
_theResult___snd__h582680 :
_theResult___snd__h582673 ;
assign _theResult___snd__h582673 = { f3_sfd__h563474, 34'd0 } ;
assign _theResult___snd__h582680 =
(f3_exp__h563473 == 8'd0 && !f3_sfd__h563474[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9398) ?
sfd__h563835 :
_theResult___snd__h582686 ;
assign _theResult___snd__h582686 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0],
2'd0 } ;
assign _theResult___snd__h582709 =
sfd__h563835 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9425 ;
assign _theResult___snd__h592308 = { _theResult____h584061[55:0], 1'd0 } ;
assign _theResult___snd__h592319 =
(!_theResult____h584061[56] && _theResult____h584061[55]) ?
_theResult___snd__h592321 :
_theResult___snd__h592331 ;
assign _theResult___snd__h592321 = { _theResult____h584061[54:0], 2'd0 } ;
assign _theResult___snd__h592331 =
(!_theResult____h584061[56] && !_theResult____h584061[55] &&
!_theResult____h584061[54] &&
!_theResult____h584061[53] &&
!_theResult____h584061[52] &&
!_theResult____h584061[51] &&
!_theResult____h584061[50] &&
!_theResult____h584061[49] &&
!_theResult____h584061[48] &&
!_theResult____h584061[47] &&
!_theResult____h584061[46] &&
!_theResult____h584061[45] &&
!_theResult____h584061[44] &&
!_theResult____h584061[43] &&
!_theResult____h584061[42] &&
!_theResult____h584061[41] &&
!_theResult____h584061[40] &&
!_theResult____h584061[39] &&
!_theResult____h584061[38] &&
!_theResult____h584061[37] &&
!_theResult____h584061[36] &&
!_theResult____h584061[35] &&
!_theResult____h584061[34] &&
!_theResult____h584061[33] &&
!_theResult____h584061[32] &&
!_theResult____h584061[31] &&
!_theResult____h584061[30] &&
!_theResult____h584061[29] &&
!_theResult____h584061[28] &&
!_theResult____h584061[27] &&
!_theResult____h584061[26] &&
!_theResult____h584061[25] &&
!_theResult____h584061[24] &&
!_theResult____h584061[23] &&
!_theResult____h584061[22] &&
!_theResult____h584061[21] &&
!_theResult____h584061[20] &&
!_theResult____h584061[19] &&
!_theResult____h584061[18] &&
!_theResult____h584061[17] &&
!_theResult____h584061[16] &&
!_theResult____h584061[15] &&
!_theResult____h584061[14] &&
!_theResult____h584061[13] &&
!_theResult____h584061[12] &&
!_theResult____h584061[11] &&
!_theResult____h584061[10] &&
!_theResult____h584061[9] &&
!_theResult____h584061[8] &&
!_theResult____h584061[7] &&
!_theResult____h584061[6] &&
!_theResult____h584061[5] &&
!_theResult____h584061[4] &&
!_theResult____h584061[3] &&
!_theResult____h584061[2] &&
!_theResult____h584061[1] &&
!_theResult____h584061[0]) ?
_theResult____h584061 :
_theResult___snd__h592337 ;
assign _theResult___snd__h592337 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0],
2'd0 } ;
assign _theResult___snd__h592360 =
_theResult____h584061 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9722 ;
assign _theResult___snd__h601076 =
(f3_exp__h563473 == 8'd0) ?
_theResult___snd__h601090 :
_theResult___snd__h582673 ;
assign _theResult___snd__h601090 =
(f3_exp__h563473 == 8'd0 && !f3_sfd__h563474[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9398) ?
sfd__h563835 :
_theResult___snd__h601096 ;
assign _theResult___snd__h601096 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0],
2'd0 } ;
assign _theResult___snd__h601114 =
sfd__h563835 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9773 ;
assign _theResult___snd__h606570 =
b__h606022[63] ? b___1__h606635 : b__h606022 ;
assign _theResult___snd_fst_exp__h365904 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
_theResult___fst_exp__h357319 :
_theResult___fst_exp__h365901 ;
assign _theResult___snd_fst_exp__h383724 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 ?
_theResult___fst_exp__h375085 :
_theResult___fst_exp__h383721 ;
assign _theResult___snd_fst_exp__h411601 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
_theResult___fst_exp__h403016 :
_theResult___fst_exp__h411598 ;
assign _theResult___snd_fst_exp__h429421 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 ?
_theResult___fst_exp__h420782 :
_theResult___fst_exp__h429418 ;
assign _theResult___snd_fst_exp__h457296 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
_theResult___fst_exp__h448711 :
_theResult___fst_exp__h457293 ;
assign _theResult___snd_fst_exp__h475116 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 ?
_theResult___fst_exp__h466477 :
_theResult___fst_exp__h475113 ;
assign _theResult___snd_fst_exp__h505324 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 ?
11'd0 :
_theResult___fst_exp__h505321 ;
assign _theResult___snd_fst_exp__h523759 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 ?
_theResult___fst_exp__h514972 :
_theResult___fst_exp__h523756 ;
assign _theResult___snd_fst_exp__h544177 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 ?
11'd0 :
_theResult___fst_exp__h544174 ;
assign _theResult___snd_fst_exp__h562612 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 ?
_theResult___fst_exp__h553825 :
_theResult___fst_exp__h562609 ;
assign _theResult___snd_fst_exp__h583481 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 ?
11'd0 :
_theResult___fst_exp__h583478 ;
assign _theResult___snd_fst_exp__h601916 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 ?
_theResult___fst_exp__h593129 :
_theResult___fst_exp__h601913 ;
assign _theResult___snd_fst_sfd__h340956 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h365905 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4110 ?
_theResult___fst_sfd__h357320 :
_theResult___fst_sfd__h365902 ;
assign _theResult___snd_fst_sfd__h383725 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4650 ?
_theResult___fst_sfd__h375086 :
_theResult___fst_sfd__h383722 ;
assign _theResult___snd_fst_sfd__h386658 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h411602 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5502 ?
_theResult___fst_sfd__h403017 :
_theResult___fst_sfd__h411599 ;
assign _theResult___snd_fst_sfd__h429422 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6042 ?
_theResult___fst_sfd__h420783 :
_theResult___fst_sfd__h429419 ;
assign _theResult___snd_fst_sfd__h432353 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h457297 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6894 ?
_theResult___fst_sfd__h448712 :
_theResult___fst_sfd__h457294 ;
assign _theResult___snd_fst_sfd__h475117 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7434 ?
_theResult___fst_sfd__h466478 :
_theResult___fst_sfd__h475114 ;
assign _theResult___snd_fst_sfd__h485491 =
(f1_sfd__h485176 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h485239 ;
assign _theResult___snd_fst_sfd__h505325 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 ?
52'd0 :
_theResult___fst_sfd__h505322 ;
assign _theResult___snd_fst_sfd__h523760 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8760 ?
_theResult___fst_sfd__h514973 :
_theResult___fst_sfd__h523757 ;
assign _theResult___snd_fst_sfd__h524485 =
(f2_sfd__h524170 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h524233 ;
assign _theResult___snd_fst_sfd__h544178 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 ?
52'd0 :
_theResult___fst_sfd__h544175 ;
assign _theResult___snd_fst_sfd__h562613 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10245 ?
_theResult___fst_sfd__h553826 :
_theResult___fst_sfd__h562610 ;
assign _theResult___snd_fst_sfd__h563789 =
(f3_sfd__h563474 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h563537 ;
assign _theResult___snd_fst_sfd__h583482 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 ?
52'd0 :
_theResult___fst_sfd__h583479 ;
assign _theResult___snd_fst_sfd__h601917 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9475 ?
_theResult___fst_sfd__h593130 :
_theResult___fst_sfd__h601914 ;
assign a___1__h606183 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ?
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } :
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11[31]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 } ;
assign a___1__h606574 = 64'd0 - a__h606021 ;
assign a__h606021 =
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
a___1__h606183 :
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
assign b___1__h606184 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12[31]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 } :
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ;
assign b___1__h606635 = 64'd0 - b__h606022 ;
assign b__h606022 =
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
b___1__h606184 :
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
assign b__h606169 = { {64{a__h606021[63]}}, a__h606021 } ;
assign b__h606245 = { {64{b__h606022[63]}}, b__h606022 } ;
assign b__h606346 = { 64'd0, a__h606021 } ;
assign b__h606358 = { 64'd0, b__h606022 } ;
assign base__h711168 = { csrf_stvec_base_hi_reg, 2'b0 } ;
assign base__h711188 = { csrf_mtvec_base_hi_reg, 2'b0 } ;
assign cause_code__h708328 =
commitStage_commitTrap[4] ? i__h708503 : i__h708343 ;
assign commitStage_commitTrap_4568_BIT_4_4808_AND_com_ETC___d14873 =
commitStage_commitTrap[4] &&
commitStage_commitTrap[3:0] != 4'd0 &&
commitStage_commitTrap[3:0] != 4'd1 &&
commitStage_commitTrap[3:0] != 4'd3 &&
commitStage_commitTrap[3:0] != 4'd4 &&
commitStage_commitTrap[3:0] != 4'd5 &&
commitStage_commitTrap[3:0] != 4'd7 &&
commitStage_commitTrap[3:0] != 4'd8 &&
commitStage_commitTrap[3:0] != 4'd9 &&
commitStage_commitTrap[3:0] != 4'd11 ||
!commitStage_commitTrap[4] &&
commitStage_commitTrap[3:0] == 4'd3 &&
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ;
assign commitStage_f_rob_data_first__4972_BITS_161_TO_ETC___d15136 =
{ commitStage_f_rob_data$D_OUT[161:98],
CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257,
commitStage_f_rob_data$D_OUT[95:26],
mstatus_csr__read__h614607,
x_prv__h711252,
pc__h711152,
x__h712324,
x__h712515,
commitStage_commitTrap[132:69] } ;
assign commitStage_rg_serial_num_4736_PLUS_IF_rob_deq_ETC___d15627 =
commitStage_rg_serial_num + y__h727463 ;
assign coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12373 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_0_wget__2371_BITS__ETC___d12414 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12386 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_1_wget__2384_BITS__ETC___d12420 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_2_wget__2392_BITS__ETC___d12394 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_2_wget__2392_BITS__ETC___d12424 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_3_wget__2399_BITS__ETC___d12401 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_3_wget__2399_BITS__ETC___d12428 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_dispToRegQ_RDY_first__2348_AN_ETC___d12439 =
coreFix_aluExe_0_dispToRegQ$RDY_first &&
(coreFix_aluExe_0_dispToRegQ$first[131] ||
!coreFix_aluExe_0_dispToRegQ$first[85] ||
sbCons$lazyLookup_0_get[3] ||
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2348_ETC___d12381 &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12407) &&
(!coreFix_aluExe_0_dispToRegQ$first[77] ||
sbCons$lazyLookup_0_get[2] ||
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2348_ETC___d12417 &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12434) ;
assign coreFix_aluExe_0_exeToFinQ_RDY_first__2815_AND_ETC___d12855 =
coreFix_aluExe_0_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_0_set &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 ||
coreFix_trainBPQ_0$FULL_N) ;
assign coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 =
coreFix_aluExe_0_rsAlu$approximateCount <
coreFix_aluExe_1_rsAlu$approximateCount ;
assign coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11514 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_0_wget__1512_BITS__ETC___d11555 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11527 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_1_wget__1525_BITS__ETC___d11561 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_2_wget__1533_BITS__ETC___d11535 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_2_wget__1533_BITS__ETC___d11565 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_3_wget__1540_BITS__ETC___d11542 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_3_wget__1540_BITS__ETC___d11569 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_dispToRegQ_RDY_first__1489_AN_ETC___d11580 =
coreFix_aluExe_1_dispToRegQ$RDY_first &&
(coreFix_aluExe_1_dispToRegQ$first[131] ||
!coreFix_aluExe_1_dispToRegQ$first[85] ||
sbCons$lazyLookup_1_get[3] ||
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1489_ETC___d11522 &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11548) &&
(!coreFix_aluExe_1_dispToRegQ$first[77] ||
sbCons$lazyLookup_1_get[2] ||
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1489_ETC___d11558 &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11575) ;
assign coreFix_aluExe_1_exeToFinQ_RDY_first__2141_AND_ETC___d12182 =
coreFix_aluExe_1_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_1_set &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10 ||
coreFix_trainBPQ_1$FULL_N) ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8304 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8344 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__302__ETC___d8370 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8317 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8350 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__315__ETC___d8376 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8325 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8354 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__323__ETC___d8380 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8332 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8358 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8384 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first__2_ETC___d8396 =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
(!coreFix_fpuMulDivExe_0_dispToRegQ$first[56] ||
sbCons$lazyLookup_2_get[3] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8312 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8338) &&
(!coreFix_fpuMulDivExe_0_dispToRegQ$first[48] ||
sbCons$lazyLookup_2_get[2] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8347 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8364) &&
(!coreFix_fpuMulDivExe_0_dispToRegQ$first[40] ||
sbCons$lazyLookup_2_get[1] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8373 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8390) ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5369 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3977 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6761 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8539 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] /
IF_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_d_ETC___d11256 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11258 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] %
IF_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_d_ETC___d11256 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8153 =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d10964 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10919 |
((f3_exp__h563473 != 8'd255 || f3_sfd__h563474 == 23'd0) &&
(f3_exp__h563473 != 8'd255 || f3_sfd__h563474 != 23'd0) &&
(f3_exp__h563473 != 8'd0 || f3_sfd__h563474 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10959) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11000 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10988 |
((f3_exp__h563473 != 8'd255 || f3_sfd__h563474 == 23'd0) &&
(f3_exp__h563473 != 8'd255 || f3_sfd__h563474 != 23'd0) &&
(f3_exp__h563473 != 8'd0 || f3_sfd__h563474 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10995) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11048 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11032 |
((f3_exp__h563473 != 8'd255 || f3_sfd__h563474 == 23'd0) &&
(f3_exp__h563473 != 8'd255 || f3_sfd__h563474 != 23'd0) &&
(f3_exp__h563473 != 8'd0 || f3_sfd__h563474 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11043) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11090 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11076 |
((f3_exp__h563473 != 8'd255 || f3_sfd__h563474 == 23'd0) &&
(f3_exp__h563473 != 8'd255 || f3_sfd__h563474 != 23'd0) &&
(f3_exp__h563473 != 8'd0 || f3_sfd__h563474 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11085) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11132 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11118 |
((f3_exp__h563473 != 8'd255 || f3_sfd__h563474 == 23'd0) &&
(f3_exp__h563473 != 8'd255 || f3_sfd__h563474 != 23'd0) &&
(f3_exp__h563473 != 8'd0 || f3_sfd__h563474 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11127) ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14193 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
regRenamingTable$RDY_rename_1_getRename &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14173) ;
assign coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1601 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1634 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_2_wget__607_BITS_70__ETC___d1609 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_2_wget__607_BITS_70__ETC___d1638 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_3_wget__614_BITS_70__ETC___d1616 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_3_wget__614_BITS_70__ETC___d1642 =
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2606 =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
y__h256656 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3164 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128 ||
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3267 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3235 ||
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas &&
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2099 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2099 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2822 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ==
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
2'd2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179) ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2589 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2594 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2586 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2593 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2611 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2586 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2610 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2628 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2621 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2627 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2648 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2648 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2672 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2101 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2678 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2672 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2675 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2680 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2715 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot[0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2727 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd0 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd2 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2738 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd0 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot[0] ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2758 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:14] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2891 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[78] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[78]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2895 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[77] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[77]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2899 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[76] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[76]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2904 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[75] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[75]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2908 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[74] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[74]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2913 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[73] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[73]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2917 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[72] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[72]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2922 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[71] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[71]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2934 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[2] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[2]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2938 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[1] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[1]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2942 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[0] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[0]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3438 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3406 ||
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT ||
!EN_dCacheToParent_rqToP_deq &&
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3534 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3502 ||
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT ||
!EN_dCacheToParent_rsToP_deq &&
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1937 =
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ||
(!coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_deqReq_rl) &&
coreFix_memExe_dMem_perfReqQ_full ;
assign coreFix_memExe_dTlb_procResp__741_BITS_105_TO__ETC___d1895 =
coreFix_memExe_dTlb$procResp[105:103] == 3'd0 &&
NOT_coreFix_memExe_dTlb_procResp__741_BITS_174_ETC___d1780 &&
IF_coreFix_memExe_dTlb_procResp__741_BIT_110_7_ETC___d1769 &&
!coreFix_memExe_lsq$updateAddr ;
assign coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1751 =
coreFix_memExe_dTlb$procResp[174:114] < 61'd402653184 ;
assign coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1752 =
coreFix_memExe_dTlb$procResp[174:114] < 61'd536870912 ;
assign coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1756 =
coreFix_memExe_dTlb$procResp[174:114] == mmio_toHostAddr ;
assign coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1759 =
coreFix_memExe_dTlb$procResp[174:114] == mmio_fromHostAddr ;
assign coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1760 =
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1751 ||
!coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1752 ||
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1756 ||
coreFix_memExe_dTlb_procResp__741_BITS_174_TO__ETC___d1759 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3856 =
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3825 ||
(!coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!coreFix_memExe_forwardQ_deqReq_rl) &&
coreFix_memExe_forwardQ_full ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3762 =
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3731 ||
(!coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!coreFix_memExe_memRespLdQ_deqReq_rl) &&
coreFix_memExe_memRespLdQ_full ;
assign coreFix_memExe_regToExeQ_RDY_enq__564_AND_core_ETC___d1654 =
coreFix_memExe_regToExeQ$RDY_enq &&
coreFix_memExe_dispToRegQ$RDY_first &&
(!coreFix_memExe_dispToRegQ$first[62] ||
sbCons$lazyLookup_3_get[3] ||
IF_coreFix_memExe_dispToRegQ_RDY_first__565_AN_ETC___d1596 &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1622) &&
(!coreFix_memExe_dispToRegQ$first[54] ||
sbCons$lazyLookup_3_get[2] ||
IF_coreFix_memExe_dispToRegQ_RDY_first__565_AN_ETC___d1631 &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1648) ;
assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q13 =
coreFix_memExe_regToExeQ$first[189:158] ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[78] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[78]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1228 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[77] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[77]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1232 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[76] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[76]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1237 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[75] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[75]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1241 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[74] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[74]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[73] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[73]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[72] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[72]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[71] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[71]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[2] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[2]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[1] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[1]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[0] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[0]) ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3671 =
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3655 ||
(!coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas &&
!coreFix_memExe_respLrScAmoQ_deqReq_rl) &&
coreFix_memExe_respLrScAmoQ_full ;
assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14875 =
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
v_f_to_TV_0$FULL_N &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq ;
assign csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13213 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_0_first[95] &&
fetchStage$pipelines_0_first[94] ||
fetchStage$pipelines_0_first[88] &&
fetchStage$pipelines_0_first[87] ||
fetchStage$pipelines_0_first[81] ||
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74]) ||
fetchStage$pipelines_0_first[199:195] == 5'd13 &&
(fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d13208 ||
csrf_prv_reg_read__2962_ULT_IF_fetchStage_pipe_ETC___d13210) ;
assign csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13676 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_0_first[95] &&
fetchStage$pipelines_0_first[94] ||
fetchStage$pipelines_0_first[88] &&
fetchStage$pipelines_0_first[87] ||
fetchStage$pipelines_0_first[81] ||
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74]) ||
fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13957 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_1_first[95] &&
fetchStage$pipelines_1_first[94] ||
fetchStage$pipelines_1_first[88] &&
fetchStage$pipelines_1_first[87] ||
fetchStage$pipelines_1_first[81] ||
fetchStage$pipelines_1_first[75] &&
fetchStage$pipelines_1_first[74]) ||
fetchStage$pipelines_1_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 =
csrf_prv_reg_read__2962_ULE_1___d14914 &&
(commitStage_commitTrap[4] ?
_0b0_CONCAT_csrf_mideleg_11_reg_read__1840_1841_ETC___d14916 :
_0b0_CONCAT_csrf_medeleg_15_reg_read__1832_1833_ETC___d14934) ;
assign csrf_prv_reg_read__2962_ULE_1___d14914 = csrf_prv_reg <= 2'd1 ;
assign csrf_prv_reg_read__2962_ULT_IF_fetchStage_pipe_ETC___d13210 =
csrf_prv_reg <
IF_fetchStage_pipelines_0_first__2932_BIT_173__ETC___d13205[9:8] ;
assign csrf_rg_dcsr_read__1900_BIT_2_3230_OR_NOT_fetc_ETC___d13672 =
csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first &&
IF_fetchStage_RDY_pipelines_0_first__2929_AND__ETC___d13610 ;
assign data77099_BITS_31_TO_0__q10 = data__h477099[31:0] ;
assign data77993_BITS_31_TO_0__q14 = data__h477993[31:0] ;
assign data___1__h477611 =
{ {32{data77099_BITS_31_TO_0__q10[31]}},
data77099_BITS_31_TO_0__q10 } ;
assign data___1__h478505 =
{ {32{data77993_BITS_31_TO_0__q14[31]}},
data77993_BITS_31_TO_0__q14 } ;
assign data__h477099 =
(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] ==
2'd0) ?
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] :
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ;
assign data__h477993 =
(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
2'd2) ?
x_quotient__h477795 :
x_remainder__h477796 ;
assign dcsr_cause__h707848 =
(commitStage_commitTrap[4] &&
commitStage_commitTrap[3:0] == 4'd14) ?
3'd3 :
((commitStage_commitTrap[4] &&
commitStage_commitTrap[3:0] != 4'd0 &&
commitStage_commitTrap[3:0] != 4'd1 &&
commitStage_commitTrap[3:0] != 4'd3 &&
commitStage_commitTrap[3:0] != 4'd4 &&
commitStage_commitTrap[3:0] != 4'd5 &&
commitStage_commitTrap[3:0] != 4'd7 &&
commitStage_commitTrap[3:0] != 4'd8 &&
commitStage_commitTrap[3:0] != 4'd9 &&
commitStage_commitTrap[3:0] != 4'd11 &&
commitStage_commitTrap[3:0] != 4'd14) ?
3'd4 :
3'd1) ;
assign din_inc___2_exp__h383755 = _theResult___fst_exp__h356722 + 8'd1 ;
assign din_inc___2_exp__h383779 = _theResult___fst_exp__h365378 + 8'd1 ;
assign din_inc___2_exp__h383809 = _theResult___fst_exp__h374488 + 8'd1 ;
assign din_inc___2_exp__h383833 = _theResult___fst_exp__h383173 + 8'd1 ;
assign din_inc___2_exp__h429452 = _theResult___fst_exp__h402419 + 8'd1 ;
assign din_inc___2_exp__h429476 = _theResult___fst_exp__h411075 + 8'd1 ;
assign din_inc___2_exp__h429506 = _theResult___fst_exp__h420185 + 8'd1 ;
assign din_inc___2_exp__h429530 = _theResult___fst_exp__h428870 + 8'd1 ;
assign din_inc___2_exp__h475147 = _theResult___fst_exp__h448114 + 8'd1 ;
assign din_inc___2_exp__h475171 = _theResult___fst_exp__h456770 + 8'd1 ;
assign din_inc___2_exp__h475201 = _theResult___fst_exp__h465880 + 8'd1 ;
assign din_inc___2_exp__h475225 = _theResult___fst_exp__h474565 + 8'd1 ;
assign din_inc___2_exp__h523813 = _theResult___fst_exp__h504563 + 11'd1 ;
assign din_inc___2_exp__h523848 = _theResult___fst_exp__h514140 + 11'd1 ;
assign din_inc___2_exp__h523874 = _theResult___fst_exp__h522973 + 11'd1 ;
assign din_inc___2_exp__h562666 = _theResult___fst_exp__h543416 + 11'd1 ;
assign din_inc___2_exp__h562701 = _theResult___fst_exp__h552993 + 11'd1 ;
assign din_inc___2_exp__h562727 = _theResult___fst_exp__h561826 + 11'd1 ;
assign din_inc___2_exp__h601970 = _theResult___fst_exp__h582720 + 11'd1 ;
assign din_inc___2_exp__h602005 = _theResult___fst_exp__h592297 + 11'd1 ;
assign din_inc___2_exp__h602031 = _theResult___fst_exp__h601130 + 11'd1 ;
assign enabled_ints___1__h655781 = pend_ints__h655254 & y__h655793 ;
assign enabled_ints__h655828 =
pend_ints__h655254 &
{ r1__read_BITS_13_TO_0___h655804, csrf_mideleg_1_0_reg } ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13900 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13639) ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14042 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14038) ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14060 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14056) ;
assign f1_exp85175_MINUS_127__q136 = f1_exp__h485175 - 8'd127 ;
assign f1_exp__h485175 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] :
8'd255 ;
assign f1_sfd__h485176 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] :
23'd4194304 ;
assign f2_exp24169_MINUS_127__q176 = f2_exp__h524169 - 8'd127 ;
assign f2_exp__h524169 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] :
8'd255 ;
assign f2_sfd__h524170 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] :
23'd4194304 ;
assign f3_exp63473_MINUS_127__q153 = f3_exp__h563473 - 8'd127 ;
assign f3_exp__h563473 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] :
8'd255 ;
assign f3_sfd__h563474 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] :
23'd4194304 ;
assign f_csr_rsps_i_notFull__5945_AND_f_csr_reqs_firs_ETC___d16040 =
f_csr_rsps$FULL_N &&
(f_csr_reqs$D_OUT[75:64] != 12'd2049 ||
csrf_stats_module_writeQ$FULL_N) &&
(f_csr_reqs$D_OUT[75:64] != 12'd2048 ||
csrf_terminate_module_terminateQ$FULL_N) ;
assign fallthrough_pc__h668411 =
(fetchStage$pipelines_0_first[97:96] == 2'b11) ?
fetchStage$pipelines_0_first[387:324] + 64'd4 :
fetchStage$pipelines_0_first[387:324] + 64'd2 ;
assign fallthrough_pc__h683886 =
(fetchStage$pipelines_1_first[97:96] == 2'b11) ?
fetchStage$pipelines_1_first[387:324] + 64'd4 :
fetchStage$pipelines_1_first[387:324] + 64'd2 ;
assign fcsr_csr__read__h613763 = { 56'd0, x__h616893 } ;
assign fetchStage_RDY_pipelines_1_deq__2944_AND_NOT_f_ETC___d14244 =
fetchStage$RDY_pipelines_1_deq &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14240) &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
specTagManager$RDY_claimSpecTag) ;
assign fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14184 =
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d13911 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14180) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ;
assign fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14266 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 ;
assign fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14372 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d14263 &&
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d13911 ||
!coreFix_aluExe_0_rsAlu$canEnq ;
assign fetchStage_pipelines_0_canDeq__2930_AND_fetchS_ETC___d14254 =
fetchStage$pipelines_0_canDeq &&
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14128 ||
!fetchStage$pipelines_1_canDeq ||
fetchStage$RDY_pipelines_1_first &&
(fetchStage_pipelines_1_first__2941_BITS_194_TO_ETC___d14139 ||
!regRenamingTable$rename_1_canRename ||
fetchStage_pipelines_1_first__2941_BITS_199_TO_ETC___d14151 ||
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14250) &&
IF_fetchStage_RDY_pipelines_1_first__2940_AND__ETC___d14071 ;
assign fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14190 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) ;
assign fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14197 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14219 =
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14190 ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14003 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14210) ;
assign fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14231 =
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14197 ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14003 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14222) ;
assign fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14523 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14521 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign fetchStage_pipelines_0_canDeq__2930_AND_specTa_ETC___d14349 =
fetchStage$pipelines_0_canDeq && specTagManager$canClaim &&
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d13208 =
(fetchStage$pipelines_0_first[194:192] == 3'd0 &&
fetchStage$pipelines_0_first[178:174] == 5'd15 ||
rs1__h659435 != 5'd0 ||
imm__h659436 != 32'd0) &&
IF_fetchStage_pipelines_0_first__2932_BIT_173__ETC___d13205[11:10] ==
2'b11 ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d13911 =
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 &&
(!coreFix_aluExe_1_rsAlu$canEnq ||
coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619) ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14010 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14006 ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14122 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14086 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14111 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14120 ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14128 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14086 ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14127 ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14145 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[68] ||
checkForException___d13178[4] ||
!rob$enqPort_0_canEnq ||
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14127 ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14157 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13927 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 ||
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14164 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13927 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 ||
coreFix_aluExe_0_rsAlu$canEnq &&
coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ;
assign fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14180 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2932_BITS_199_TO_ETC___d13683 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 ;
assign fetchStage_pipelines_0_first__2932_BITS_199_TO_ETC___d13683 =
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d13178[4] ||
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13676 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign fetchStage_pipelines_0_first__2932_BIT_68_2961_ETC___d14001 =
fetchStage$pipelines_0_first[68] ||
checkForException___d13178[4] ||
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13676 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign fetchStage_pipelines_1_first__2941_BITS_194_TO_ETC___d14139 =
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14136 ||
!specTagManager$canClaim) ;
assign fetchStage_pipelines_1_first__2941_BITS_199_TO_ETC___d14151 =
fetchStage$pipelines_1_first[199:195] == 5'd0 ||
fetchStage$pipelines_1_first[199:195] == 5'd21 ||
fetchStage$pipelines_1_first[199:195] == 5'd17 ||
fetchStage$pipelines_1_first[199:195] == 5'd18 ||
fetchStage$pipelines_1_first[199:195] == 5'd13 ||
fetchStage$pipelines_1_first[199:195] == 5'd16 ||
fetchStage$pipelines_1_first[199:195] == 5'd15 ||
fetchStage$pipelines_1_first[199:195] == 5'd19 ||
fetchStage$pipelines_1_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_1_first[68] ||
checkForException___d13864[4] ||
csrf_fs_reg_read__1727_EQ_0_3167_AND_fetchStag_ETC___d13957 ||
!rob$enqPort_1_canEnq ||
!epochManager$checkEpoch_1_check ||
csrf_rg_dcsr[2] ||
fetchStage$pipelines_0_canDeq &&
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14145 ;
assign fetchStage_pipelines_1_first__2941_BIT_173_375_ETC___d13842 =
{ fetchStage$pipelines_1_first[173],
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ;
assign fflags__h729123 =
NOT_rob_deqPort_0_canDeq__5509_5510_OR_rob_deq_ETC___d15811 ?
y_avValue_fst__h729066 :
IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15817 ;
assign fflags_csr__read__h613738 = { 59'd0, csrf_fflags_reg } ;
assign frm_csr__read__h613749 = { 61'd0, csrf_frm_reg } ;
assign guard__h348621 =
{ IF_sfdin56716_BIT_33_THEN_2_ELSE_0__q30[1],
{ sfdin__h356716[32:0], 23'd0 } != 56'd0 } ;
assign guard__h357330 =
{ IF_theResult___snd65329_BIT_33_THEN_2_ELSE_0__q32[1],
{ _theResult___snd__h365329[32:0], 23'd0 } != 56'd0 } ;
assign guard__h366260 =
{ IF_sfdin74482_BIT_33_THEN_2_ELSE_0__q40[1],
{ sfdin__h374482[32:0], 23'd0 } != 56'd0 } ;
assign guard__h366858 = x__h366960 != 57'd0 ;
assign guard__h375096 =
{ IF_theResult___snd83119_BIT_33_THEN_2_ELSE_0__q45[1],
{ _theResult___snd__h383119[32:0], 23'd0 } != 56'd0 } ;
assign guard__h394320 =
{ IF_sfdin02413_BIT_33_THEN_2_ELSE_0__q65[1],
{ sfdin__h402413[32:0], 23'd0 } != 56'd0 } ;
assign guard__h403027 =
{ IF_theResult___snd11026_BIT_33_THEN_2_ELSE_0__q67[1],
{ _theResult___snd__h411026[32:0], 23'd0 } != 56'd0 } ;
assign guard__h411957 =
{ IF_sfdin20179_BIT_33_THEN_2_ELSE_0__q75[1],
{ sfdin__h420179[32:0], 23'd0 } != 56'd0 } ;
assign guard__h412555 = x__h412657 != 57'd0 ;
assign guard__h420793 =
{ IF_theResult___snd28816_BIT_33_THEN_2_ELSE_0__q80[1],
{ _theResult___snd__h428816[32:0], 23'd0 } != 56'd0 } ;
assign guard__h440015 =
{ IF_sfdin48108_BIT_33_THEN_2_ELSE_0__q100[1],
{ sfdin__h448108[32:0], 23'd0 } != 56'd0 } ;
assign guard__h448722 =
{ IF_theResult___snd56721_BIT_33_THEN_2_ELSE_0__q102[1],
{ _theResult___snd__h456721[32:0], 23'd0 } != 56'd0 } ;
assign guard__h457652 =
{ IF_sfdin65874_BIT_33_THEN_2_ELSE_0__q110[1],
{ sfdin__h465874[32:0], 23'd0 } != 56'd0 } ;
assign guard__h458250 = x__h458352 != 57'd0 ;
assign guard__h466488 =
{ IF_theResult___snd74511_BIT_33_THEN_2_ELSE_0__q115[1],
{ _theResult___snd__h474511[32:0], 23'd0 } != 56'd0 } ;
assign guard__h496602 =
{ IF_theResult___snd04514_BIT_4_THEN_2_ELSE_0__q135[1],
{ _theResult___snd__h504514[3:0], 52'd0 } != 56'd0 } ;
assign guard__h505914 =
{ IF_sfdin14134_BIT_4_THEN_2_ELSE_0__q139[1],
{ sfdin__h514134[3:0], 52'd0 } != 56'd0 } ;
assign guard__h506512 = x__h506612 != 57'd0 ;
assign guard__h514983 =
{ IF_theResult___snd22919_BIT_4_THEN_2_ELSE_0__q142[1],
{ _theResult___snd__h522919[3:0], 52'd0 } != 56'd0 } ;
assign guard__h535455 =
{ IF_theResult___snd43367_BIT_4_THEN_2_ELSE_0__q175[1],
{ _theResult___snd__h543367[3:0], 52'd0 } != 56'd0 } ;
assign guard__h544767 =
{ IF_sfdin52987_BIT_4_THEN_2_ELSE_0__q179[1],
{ sfdin__h552987[3:0], 52'd0 } != 56'd0 } ;
assign guard__h545365 = x__h545465 != 57'd0 ;
assign guard__h553836 =
{ IF_theResult___snd61772_BIT_4_THEN_2_ELSE_0__q182[1],
{ _theResult___snd__h561772[3:0], 52'd0 } != 56'd0 } ;
assign guard__h574759 =
{ IF_theResult___snd82671_BIT_4_THEN_2_ELSE_0__q152[1],
{ _theResult___snd__h582671[3:0], 52'd0 } != 56'd0 } ;
assign guard__h584071 =
{ IF_sfdin92291_BIT_4_THEN_2_ELSE_0__q156[1],
{ sfdin__h592291[3:0], 52'd0 } != 56'd0 } ;
assign guard__h584669 = x__h584769 != 57'd0 ;
assign guard__h593140 =
{ IF_theResult___snd01076_BIT_4_THEN_2_ELSE_0__q159[1],
{ _theResult___snd__h601076[3:0], 52'd0 } != 56'd0 } ;
assign idx__h687446 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13912 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d13936 ;
assign imm__h659436 =
fetchStage$pipelines_0_first[160] ?
fetchStage$pipelines_0_first[159:128] :
32'd0 ;
assign k__h672122 =
!coreFix_aluExe_0_rsAlu$canEnq ||
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ;
assign mcause_csr__read__h615403 =
{ r1__read__h618414, csrf_mcause_code_reg } ;
assign mcounteren_csr__read__h615148 =
{ r1__read__h618401, csrf_mcounteren_cy_reg } ;
assign medeleg_csr__read__h614755 =
{ r1__read__h618244, csrf_medeleg_9_0_reg } ;
assign mideleg_csr__read__h614850 =
{ r1__read__h618261, csrf_mideleg_1_0_reg } ;
assign mie_csr__read__h614974 =
{ r1__read__h618285, csrf_software_int_en_vec_0 } ;
assign mip_csr__read__h615636 =
{ r1__read__h618420, csrf_software_int_pend_vec_0 } ;
assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 =
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ||
(!mmio_cRqQ_deqReq_dummy2_2$Q_OUT ||
!EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl) &&
mmio_cRqQ_full ;
assign mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 =
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ||
(!mmio_cRsQ_deqReq_dummy2_2$Q_OUT ||
!EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl) &&
mmio_cRsQ_full ;
assign mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 =
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT &&
(mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl) ||
(!mmio_dataPendQ_deqReq_dummy2_2$Q_OUT ||
!mmio_dataRespQ_deqReq_lat_0$whas &&
!mmio_dataPendQ_deqReq_rl) &&
mmio_dataPendQ_full ;
assign mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 =
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ||
(!mmio_dataReqQ_deqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl) &&
mmio_dataReqQ_full ;
assign mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 =
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ||
(!mmio_dataRespQ_deqReq_dummy2_2$Q_OUT ||
!mmio_dataRespQ_deqReq_lat_0$whas &&
!mmio_dataRespQ_deqReq_rl) &&
mmio_dataRespQ_full ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13223 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
(renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13220) ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13512 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13509 ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13530 =
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13512 &&
(fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20) &&
rob$isEmpty ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14258 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_296_ETC___d13597 ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14260 =
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14258 &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
rg_core_run_state == 2'd2 ;
assign mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 =
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ||
(!mmio_pRqQ_deqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl) &&
mmio_pRqQ_full ;
assign mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 =
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ||
(!mmio_pRsQ_deqReq_dummy2_2$Q_OUT ||
!mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) &&
mmio_pRsQ_full ;
assign msip__h75952 = csrf_software_int_pend_vec_3 ;
assign mstatus_csr__read__h614607 = { r1__read__h618119, csrf_ie_vec_0 } ;
assign mtvec_csr__read__h615056 =
{ r1__read__h618396, csrf_mtvec_mode_low_reg } ;
assign n___1__h200101 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] :
x__h198698[63:56],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] :
x__h198698[55:48],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] :
x__h198698[47:40],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] :
x__h198698[39:32],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] :
x__h198698[31:24],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] :
x__h198698[23:16],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] :
x__h198698[15:8],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] :
x__h198698[7:0] } ;
assign n__read__h615740 =
(csrf_mcycle_ehr_data_dummy2_0$Q_OUT &&
csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ?
csrf_mcycle_ehr_data_rl :
64'd0 ;
assign n__read__h615931 =
(csrf_minstret_ehr_data_dummy2_0$Q_OUT &&
csrf_minstret_ehr_data_dummy2_1$Q_OUT) ?
csrf_minstret_ehr_data_rl :
64'd0 ;
assign n__read__h6607 =
csrf_mcycle_ehr_data_dummy2_1$Q_OUT ?
(csrf_mcycle_ehr_data_lat_0$whas ?
upd__h6721 :
csrf_mcycle_ehr_data_rl) :
64'd0 ;
assign n__read__h724080 =
csrf_minstret_ehr_data_dummy2_1$Q_OUT ?
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 :
64'd0 ;
assign next_deqP___1__h299326 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ==
3'd7) ?
3'd0 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP +
3'd1 ;
assign next_deqP___1__h307322 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ;
assign next_deqP___1__h313603 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ;
assign next_deqP___1__h321457 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ;
assign next_deqP___1__h331514 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ;
assign next_deqP___1__h334739 = coreFix_memExe_forwardQ_deqP + 1'd1 ;
assign next_pc__h720279 =
(rob$deqPort_0_deq_data[257:253] != 5'd13 &&
rob$deqPort_0_deq_data[97:96] == 2'd0) ?
rob$deqPort_0_deq_data[95:32] :
rob_deqPort_0_deq_data__4560_BITS_353_TO_290_4_ETC___d15379 ;
assign out___1_sfd__h485239 = { f1_sfd__h485176, 29'd0 } ;
assign out___1_sfd__h524233 = { f2_sfd__h524170, 29'd0 } ;
assign out___1_sfd__h563537 = { f3_sfd__h563474, 29'd0 } ;
assign out_exp__h357241 =
sfdin__h356716[34] ?
_theResult___exp__h357238 :
_theResult___fst_exp__h356722 ;
assign out_exp__h365823 =
_theResult___snd__h365329[34] ?
_theResult___exp__h365820 :
_theResult___fst_exp__h365378 ;
assign out_exp__h375007 =
sfdin__h374482[34] ?
_theResult___exp__h375004 :
_theResult___fst_exp__h374488 ;
assign out_exp__h383643 =
_theResult___snd__h383119[34] ?
_theResult___exp__h383640 :
_theResult___fst_exp__h383173 ;
assign out_exp__h402938 =
sfdin__h402413[34] ?
_theResult___exp__h402935 :
_theResult___fst_exp__h402419 ;
assign out_exp__h411520 =
_theResult___snd__h411026[34] ?
_theResult___exp__h411517 :
_theResult___fst_exp__h411075 ;
assign out_exp__h420704 =
sfdin__h420179[34] ?
_theResult___exp__h420701 :
_theResult___fst_exp__h420185 ;
assign out_exp__h429340 =
_theResult___snd__h428816[34] ?
_theResult___exp__h429337 :
_theResult___fst_exp__h428870 ;
assign out_exp__h448633 =
sfdin__h448108[34] ?
_theResult___exp__h448630 :
_theResult___fst_exp__h448114 ;
assign out_exp__h457215 =
_theResult___snd__h456721[34] ?
_theResult___exp__h457212 :
_theResult___fst_exp__h456770 ;
assign out_exp__h466399 =
sfdin__h465874[34] ?
_theResult___exp__h466396 :
_theResult___fst_exp__h465880 ;
assign out_exp__h475035 =
_theResult___snd__h474511[34] ?
_theResult___exp__h475032 :
_theResult___fst_exp__h474565 ;
assign out_exp__h505221 =
_theResult___snd__h504514[5] ?
_theResult___exp__h505218 :
_theResult___fst_exp__h504563 ;
assign out_exp__h514872 =
sfdin__h514134[5] ?
_theResult___exp__h514869 :
_theResult___fst_exp__h514140 ;
assign out_exp__h523656 =
_theResult___snd__h522919[5] ?
_theResult___exp__h523653 :
_theResult___fst_exp__h522973 ;
assign out_exp__h544074 =
_theResult___snd__h543367[5] ?
_theResult___exp__h544071 :
_theResult___fst_exp__h543416 ;
assign out_exp__h553725 =
sfdin__h552987[5] ?
_theResult___exp__h553722 :
_theResult___fst_exp__h552993 ;
assign out_exp__h562509 =
_theResult___snd__h561772[5] ?
_theResult___exp__h562506 :
_theResult___fst_exp__h561826 ;
assign out_exp__h583378 =
_theResult___snd__h582671[5] ?
_theResult___exp__h583375 :
_theResult___fst_exp__h582720 ;
assign out_exp__h593029 =
sfdin__h592291[5] ?
_theResult___exp__h593026 :
_theResult___fst_exp__h592297 ;
assign out_exp__h601813 =
_theResult___snd__h601076[5] ?
_theResult___exp__h601810 :
_theResult___fst_exp__h601130 ;
assign out_f_exp__h384019 =
(_theResult___exp__h383742 == 8'd255 &&
_theResult___sfd__h383743 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h383733 ;
assign out_f_exp__h429716 =
(_theResult___exp__h429439 == 8'd255 &&
_theResult___sfd__h429440 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h429430 ;
assign out_f_exp__h475411 =
(_theResult___exp__h475134 == 8'd255 &&
_theResult___sfd__h475135 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h475125 ;
assign out_f_sfd__h384020 =
(_theResult___exp__h383742 == 8'd255 &&
_theResult___sfd__h383743 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h383743 ;
assign out_f_sfd__h429717 =
(_theResult___exp__h429439 == 8'd255 &&
_theResult___sfd__h429440 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h429440 ;
assign out_f_sfd__h475412 =
(_theResult___exp__h475134 == 8'd255 &&
_theResult___sfd__h475135 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h475135 ;
assign out_sfd__h357242 =
sfdin__h356716[34] ?
_theResult___sfd__h357239 :
sfdin__h356716[56:34] ;
assign out_sfd__h365824 =
_theResult___snd__h365329[34] ?
_theResult___sfd__h365821 :
_theResult___snd__h365329[56:34] ;
assign out_sfd__h375008 =
sfdin__h374482[34] ?
_theResult___sfd__h375005 :
sfdin__h374482[56:34] ;
assign out_sfd__h383644 =
_theResult___snd__h383119[34] ?
_theResult___sfd__h383641 :
_theResult___snd__h383119[56:34] ;
assign out_sfd__h402939 =
sfdin__h402413[34] ?
_theResult___sfd__h402936 :
sfdin__h402413[56:34] ;
assign out_sfd__h411521 =
_theResult___snd__h411026[34] ?
_theResult___sfd__h411518 :
_theResult___snd__h411026[56:34] ;
assign out_sfd__h420705 =
sfdin__h420179[34] ?
_theResult___sfd__h420702 :
sfdin__h420179[56:34] ;
assign out_sfd__h429341 =
_theResult___snd__h428816[34] ?
_theResult___sfd__h429338 :
_theResult___snd__h428816[56:34] ;
assign out_sfd__h448634 =
sfdin__h448108[34] ?
_theResult___sfd__h448631 :
sfdin__h448108[56:34] ;
assign out_sfd__h457216 =
_theResult___snd__h456721[34] ?
_theResult___sfd__h457213 :
_theResult___snd__h456721[56:34] ;
assign out_sfd__h466400 =
sfdin__h465874[34] ?
_theResult___sfd__h466397 :
sfdin__h465874[56:34] ;
assign out_sfd__h475036 =
_theResult___snd__h474511[34] ?
_theResult___sfd__h475033 :
_theResult___snd__h474511[56:34] ;
assign out_sfd__h505222 =
_theResult___snd__h504514[5] ?
_theResult___sfd__h505219 :
_theResult___snd__h504514[56:5] ;
assign out_sfd__h514873 =
sfdin__h514134[5] ?
_theResult___sfd__h514870 :
sfdin__h514134[56:5] ;
assign out_sfd__h523657 =
_theResult___snd__h522919[5] ?
_theResult___sfd__h523654 :
_theResult___snd__h522919[56:5] ;
assign out_sfd__h544075 =
_theResult___snd__h543367[5] ?
_theResult___sfd__h544072 :
_theResult___snd__h543367[56:5] ;
assign out_sfd__h553726 =
sfdin__h552987[5] ?
_theResult___sfd__h553723 :
sfdin__h552987[56:5] ;
assign out_sfd__h562510 =
_theResult___snd__h561772[5] ?
_theResult___sfd__h562507 :
_theResult___snd__h561772[56:5] ;
assign out_sfd__h583379 =
_theResult___snd__h582671[5] ?
_theResult___sfd__h583376 :
_theResult___snd__h582671[56:5] ;
assign out_sfd__h593030 =
sfdin__h592291[5] ?
_theResult___sfd__h593027 :
sfdin__h592291[56:5] ;
assign out_sfd__h601814 =
_theResult___snd__h601076[5] ?
_theResult___sfd__h601811 :
_theResult___snd__h601076[56:5] ;
assign pc__h711152 =
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ?
y_avValue_new_pc__h710944 :
y_avValue_new_pc__h711130 ;
assign pend_ints__h655254 =
{ _0_CONCAT_csrf_external_int_en_vec_3_read__1851_ETC___d12975,
csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3,
1'd0,
csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1,
csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ;
assign prv__h730760 = csrf_prv_reg ;
assign prv__h730804 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ;
assign q___1__h478580 =
64'd0 -
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ;
assign r1__read_BITS_13_TO_0___h655804 =
{ 4'd0,
csrf_mideleg_11_reg,
1'b0,
csrf_mideleg_9_7_reg,
1'b0,
csrf_mideleg_5_3_reg,
1'b0 } ;
assign r1__read_BITS_13_TO_12___h659304 = csrf_fs_reg ;
assign r1__read_BIT_20___h659964 = csrf_tw_reg ;
assign r1__read__h616908 = { r1__read__h616910, csrf_ie_vec_1 } ;
assign r1__read__h616910 = { r1__read__h616912, 2'b0 } ;
assign r1__read__h616912 = { r1__read__h616914, csrf_prev_ie_vec_0 } ;
assign r1__read__h616914 = { r1__read__h616916, csrf_prev_ie_vec_1 } ;
assign r1__read__h616916 = { r1__read__h616918, 2'b0 } ;
assign r1__read__h616918 = { r1__read__h616920, csrf_spp_reg } ;
assign r1__read__h616920 = { r1__read__h616922, 4'b0 } ;
assign r1__read__h616922 = { r1__read__h616924, csrf_fs_reg } ;
assign r1__read__h616924 = { r1__read__h616926, 2'd0 } ;
assign r1__read__h616926 = { r1__read__h616928, 1'b0 } ;
assign r1__read__h616928 = { r1__read__h616930, csrf_sum_reg } ;
assign r1__read__h616930 = { r1__read__h616932, csrf_mxr_reg } ;
assign r1__read__h616932 = { r1__read__h616934, 12'b0 } ;
assign r1__read__h616934 = { r1__read__h616936, 2'b10 } ;
assign r1__read__h616936 = { csrf_fs_reg == 2'b11, 29'b0 } ;
assign r1__read__h617312 =
{ r1__read__h617314, csrf_software_int_en_vec_1 } ;
assign r1__read__h617314 = { r1__read__h617316, 2'b0 } ;
assign r1__read__h617316 = { r1__read__h617318, csrf_timer_int_en_vec_0 } ;
assign r1__read__h617318 = { r1__read__h617320, csrf_timer_int_en_vec_1 } ;
assign r1__read__h617320 = { r1__read__h617322, 2'b0 } ;
assign r1__read__h617322 =
{ r1__read__h617324, csrf_external_int_en_vec_0 } ;
assign r1__read__h617324 = { 54'b0, csrf_external_int_en_vec_1 } ;
assign r1__read__h617842 = { csrf_stvec_base_hi_reg, 1'b0 } ;
assign r1__read__h617847 = { r1__read__h617849, csrf_scounteren_tm_reg } ;
assign r1__read__h617849 = { 61'd0, csrf_scounteren_ir_reg } ;
assign r1__read__h617860 = { csrf_scause_interrupt_reg, 59'b0 } ;
assign r1__read__h617866 =
{ r1__read__h617868, csrf_software_int_pend_vec_1 } ;
assign r1__read__h617868 = { r1__read__h617870, 2'b0 } ;
assign r1__read__h617870 =
{ r1__read__h617872, csrf_timer_int_pend_vec_0 } ;
assign r1__read__h617872 =
{ r1__read__h617874, csrf_timer_int_pend_vec_1 } ;
assign r1__read__h617874 = { r1__read__h617876, 2'b0 } ;
assign r1__read__h617876 =
{ r1__read__h617878, csrf_external_int_pend_vec_0 } ;
assign r1__read__h617878 = { 54'b0, csrf_external_int_pend_vec_1 } ;
assign r1__read__h618096 = { vm_mode_reg__read__h618102, 16'd0 } ;
assign r1__read__h618119 = { r1__read__h618121, csrf_ie_vec_1 } ;
assign r1__read__h618121 = { r1__read__h618123, 1'b0 } ;
assign r1__read__h618123 = { r1__read__h618125, csrf_ie_vec_3 } ;
assign r1__read__h618125 = { r1__read__h618127, csrf_prev_ie_vec_0 } ;
assign r1__read__h618127 = { r1__read__h618129, csrf_prev_ie_vec_1 } ;
assign r1__read__h618129 = { r1__read__h618131, 1'b0 } ;
assign r1__read__h618131 = { r1__read__h618133, csrf_prev_ie_vec_3 } ;
assign r1__read__h618133 = { r1__read__h618135, csrf_spp_reg } ;
assign r1__read__h618135 = { r1__read__h618137, 2'b0 } ;
assign r1__read__h618137 = { r1__read__h618139, csrf_mpp_reg } ;
assign r1__read__h618139 = { r1__read__h618141, csrf_fs_reg } ;
assign r1__read__h618141 = { r1__read__h618143, 2'd0 } ;
assign r1__read__h618143 = { r1__read__h618145, csrf_mprv_reg } ;
assign r1__read__h618145 = { r1__read__h618147, csrf_sum_reg } ;
assign r1__read__h618147 = { r1__read__h618149, csrf_mxr_reg } ;
assign r1__read__h618149 = { r1__read__h618151, csrf_tvm_reg } ;
assign r1__read__h618151 = { r1__read__h618153, csrf_tw_reg } ;
assign r1__read__h618153 = { r1__read__h618155, csrf_tsr_reg } ;
assign r1__read__h618155 = { r1__read__h618157, 9'b0 } ;
assign r1__read__h618157 = { r1__read__h618159, 2'b10 } ;
assign r1__read__h618159 = { r1__read__h618161, 2'b10 } ;
assign r1__read__h618161 = { csrf_fs_reg == 2'b11, 27'b0 } ;
assign r1__read__h618244 = { r1__read__h618246, 1'b0 } ;
assign r1__read__h618246 = { r1__read__h618248, csrf_medeleg_13_11_reg } ;
assign r1__read__h618248 = { r1__read__h618250, 1'b0 } ;
assign r1__read__h618250 = { 48'b0, csrf_medeleg_15_reg } ;
assign r1__read__h618261 = { r1__read__h618263, 1'b0 } ;
assign r1__read__h618263 = { r1__read__h618265, csrf_mideleg_5_3_reg } ;
assign r1__read__h618265 = { r1__read__h618267, 1'b0 } ;
assign r1__read__h618267 = { r1__read__h618269, csrf_mideleg_9_7_reg } ;
assign r1__read__h618269 = { r1__read__h618271, 1'b0 } ;
assign r1__read__h618271 = { 52'b0, csrf_mideleg_11_reg } ;
assign r1__read__h618285 =
{ r1__read__h618287, csrf_software_int_en_vec_1 } ;
assign r1__read__h618287 = { r1__read__h618289, 1'b0 } ;
assign r1__read__h618289 =
{ r1__read__h618291, csrf_software_int_en_vec_3 } ;
assign r1__read__h618291 = { r1__read__h618293, csrf_timer_int_en_vec_0 } ;
assign r1__read__h618293 = { r1__read__h618295, csrf_timer_int_en_vec_1 } ;
assign r1__read__h618295 = { r1__read__h618297, 1'b0 } ;
assign r1__read__h618297 = { r1__read__h618299, csrf_timer_int_en_vec_3 } ;
assign r1__read__h618299 =
{ r1__read__h618301, csrf_external_int_en_vec_0 } ;
assign r1__read__h618301 =
{ r1__read__h618303, csrf_external_int_en_vec_1 } ;
assign r1__read__h618303 = { r1__read__h618305, 1'b0 } ;
assign r1__read__h618305 = { 52'b0, csrf_external_int_en_vec_3 } ;
assign r1__read__h618396 = { csrf_mtvec_base_hi_reg, 1'b0 } ;
assign r1__read__h618401 = { r1__read__h618403, csrf_mcounteren_tm_reg } ;
assign r1__read__h618403 = { 61'd0, csrf_mcounteren_ir_reg } ;
assign r1__read__h618414 = { csrf_mcause_interrupt_reg, 59'b0 } ;
assign r1__read__h618420 =
{ r1__read__h618422, csrf_software_int_pend_vec_1 } ;
assign r1__read__h618422 = { r1__read__h618424, 1'b0 } ;
assign r1__read__h618424 =
{ r1__read__h618426, csrf_software_int_pend_vec_3 } ;
assign r1__read__h618426 =
{ r1__read__h618428, csrf_timer_int_pend_vec_0 } ;
assign r1__read__h618428 =
{ r1__read__h618430, csrf_timer_int_pend_vec_1 } ;
assign r1__read__h618430 = { r1__read__h618432, 1'b0 } ;
assign r1__read__h618432 =
{ r1__read__h618434, csrf_timer_int_pend_vec_3 } ;
assign r1__read__h618434 =
{ r1__read__h618436, csrf_external_int_pend_vec_0 } ;
assign r1__read__h618436 =
{ r1__read__h618438, csrf_external_int_pend_vec_1 } ;
assign r1__read__h618438 = { r1__read__h618440, 1'b0 } ;
assign r1__read__h618440 = { 52'b0, csrf_external_int_pend_vec_3 } ;
assign rVal1__h484791 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
assign rVal2__h484792 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
assign r___1__h478607 =
64'd0 -
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ;
assign regRenamingTable_RDY_rename_0_getRename__3468__ETC___d14107 =
regRenamingTable$RDY_rename_0_getRename &&
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 &&
(fetchStage$pipelines_0_first[199:195] == 5'd14 ||
coreFix_memExe_rsMem$RDY_enq) ;
assign regRenamingTable_RDY_rename_1_getRename__4170__ETC___d14188 =
regRenamingTable$RDY_rename_1_getRename &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14173) &&
_0_OR_NOT_fetchStage_pipelines_1_first__2941_BI_ETC___d14186 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 =
regRenamingTable$rename_0_canRename &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d13602 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 =
regRenamingTable$rename_0_canRename &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
NOT_fetchStage_pipelines_0_first__2932_BIT_68__ETC___d13651 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667 =
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ||
!specTagManager$canClaim ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d13989 =
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14136 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14134 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14278 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14291 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_32_ETC___d14287 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14296 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
fetchStage$pipelines_0_first[173] ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14301 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 &&
fetchStage$pipelines_0_first[199:195] != 5'd14 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14321 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 &&
NOT_fetchStage_pipelines_0_first__2932_BITS_32_ETC___d14287 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14325 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 &&
fetchStage$pipelines_0_first[173] ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14331 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 &&
(fetchStage$pipelines_0_first[199:195] != 5'd14) !=
fetchStage$pipelines_0_first[160] ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14335 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 &&
(fetchStage$pipelines_0_first[191:189] == 3'd0 ||
fetchStage$pipelines_0_first[191:189] == 3'd2) ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14343 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 &&
fetchStage$pipelines_0_first[191:189] != 3'd0 &&
fetchStage$pipelines_0_first[191:189] != 3'd2 ;
assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14521 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13178[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 ;
assign regRenamingTable_rename_1_canRename__3704_AND__ETC___d13904 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d13902 ;
assign regRenamingTable_rename_1_canRename__3704_AND__ETC___d14046 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d14044 ;
assign regRenamingTable_rename_1_canRename__3704_AND__ETC___d14064 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2959_BIT_4_2960__ETC___d14062 ;
assign regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_fetchStage_pipelines_1_first__2941_BIT_68__ETC___d14398 ;
assign renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_N_ETC___d13236 =
renameStage_rg_m_halt_req[4] ||
!fetchStage$pipelines_0_first[68] &&
(IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15]) ;
assign renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_N_ETC___d13466 =
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_N_ETC___d13236 ||
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 :
IF_checkForException_3178_BIT_4_3179_THEN_IF_c_ETC___d13327) ==
4'd3 ;
assign renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d13925 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13922 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d13965 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_1_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13959 ||
!rob$enqPort_1_canEnq ||
!epochManager$checkEpoch_1_check ||
csrf_rg_dcsr_read__1900_BIT_2_3230_OR_NOT_fetc_ETC___d13672 ;
assign renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14006 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[0] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[1] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[2] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[3] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[4] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[5] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[6] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[7] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[8] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[9] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[10] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[11] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[12] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[13] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[14] ||
IF_IF_NOT_csrf_prv_reg_read__2962_EQ_3_2963_29_ETC___d13002[15] ;
assign renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14086 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d13178[4] ||
!rob$enqPort_0_canEnq ;
assign renaming_spec_bits__h687315 =
fetchStage$pipelines_0_canDeq ?
y_avValue_fst__h683778 :
specTagManager$currentSpecBits ;
assign res_data__h340395 = { 32'hFFFFFFFF, x__h340410 } ;
assign res_data__h340400 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ;
assign res_data__h386097 = { 32'hFFFFFFFF, x__h386112 } ;
assign res_data__h386102 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ;
assign res_data__h431792 = { 32'hFFFFFFFF, x__h431807 } ;
assign res_data__h431797 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ;
assign res_fflags__h340396 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5299,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5310,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5326,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5339,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5352 } ;
assign res_fflags__h386098 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6691,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6702,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6718,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6731,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6744 } ;
assign res_fflags__h431793 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8083,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8094,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8110,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8123,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8136 } ;
assign resp_addr__h294503 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ;
assign result__h366863 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4655[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4655[0] |
guard__h366858 } ;
assign result__h412560 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6047[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6047[0] |
guard__h412555 } ;
assign result__h458255 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7439[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7439[0] |
guard__h458250 } ;
assign result__h506517 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8765[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8765[0] |
guard__h506512 } ;
assign result__h545370 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10250[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10250[0] |
guard__h545365 } ;
assign result__h584674 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9480[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9480[0] |
guard__h584669 } ;
assign result__h650833 = w__h650828 & y__h650862 ;
assign result__h650884 = ~x__h650883 ;
assign rg_core_run_state_read__3226_EQ_2_3227_AND_NOT_ETC___d15884 =
rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs &&
!update_vm_info &&
fetchStage$iTlbIfc_flush_done &&
coreFix_memExe_dTlb$flush_done &&
!flush_caches ;
assign rob_RDY_deqPort_0_deq_data__4557_AND_rob_RDY_d_ETC___d15204 =
rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq &&
regRenamingTable$RDY_commit_0_commit &&
v_f_to_TV_0$FULL_N &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq &&
NOT_rob_deqPort_0_deq_data__4560_BITS_257_TO_2_ETC___d15199 ;
assign rob_RDY_enqPort_0_enq__2954_AND_regRenamingTab_ETC___d13476 =
rob$RDY_enqPort_0_enq &&
regRenamingTable$RDY_rename_0_claimRename &&
regRenamingTable$RDY_rename_0_getRename &&
fetchStage$RDY_pipelines_0_first &&
fetchStage$RDY_pipelines_0_deq &&
(fetchStage$pipelines_0_first[194:192] != 3'd0 ||
coreFix_aluExe_0_rsAlu$RDY_enq) ;
assign rob_deqPort_0_deq_data__4560_BITS_161_TO_98_45_ETC___d15481 =
{ rob$deqPort_0_deq_data[161:98],
(rob$deqPort_0_deq_data[257:253] != 5'd13 &&
rob$deqPort_0_deq_data[97:96] == 2'd0) ?
{ 2'd0, rob$deqPort_0_deq_data[95:32] } :
((rob$deqPort_0_deq_data[257:253] != 5'd13 &&
rob$deqPort_0_deq_data[97:96] == 2'd1) ?
{ 2'd1, rob$deqPort_0_deq_data[95:32] } :
{ 2'd2,
(rob$deqPort_0_deq_data[257:253] == 5'd13) ?
data_warl_xformed__h720256 :
rob$deqPort_0_deq_data[95:32] }),
rob$deqPort_0_deq_data[31:26],
mstatus_csr__read__h614607,
x_prv__h720900,
64'hAAAAAAAAAAAAAAAA,
x__h723610,
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign rob_deqPort_0_deq_data__4560_BITS_353_TO_290_4_ETC___d15379 =
rob$deqPort_0_deq_data[353:290] + 64'd4 ;
assign rob_deqPort_0_deq_data__4560_BIT_166_4576_CONC_ETC___d14625 =
{ rob$deqPort_0_deq_data[166],
rob$deqPort_0_deq_data[166] ?
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 :
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q249 } ;
assign rob_deqPort_0_deq_data__4560_BIT_181_4634_CONC_ETC___d14717 =
{ rob$deqPort_0_deq_data[181],
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q247 } ;
assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 =
rob$deqPort_0_deq_data[95:32] ;
assign rs1__h659435 =
(fetchStage$pipelines_0_first[88] &&
!fetchStage$pipelines_0_first[87]) ?
fetchStage$pipelines_0_first[86:82] :
5'd0 ;
assign satp_csr__read__h614464 = { r1__read__h618096, csrf_ppn_reg } ;
assign sbIdx__h158539 =
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] :
coreFix_memExe_reqStQ_data_0_rl[65:64]) :
2'd0 ;
assign scause_csr__read__h614262 =
{ r1__read__h617860, csrf_scause_code_reg } ;
assign scounteren_csr__read__h614124 =
{ r1__read__h617847, csrf_scounteren_cy_reg } ;
assign sfd__h341006 = { value__h349233, 3'd0 } ;
assign sfd__h356814 =
{ 1'b0,
_theResult___fst_exp__h356722 != 8'd0,
sfdin__h356716[56:34] } +
25'd1 ;
assign sfd__h365396 =
{ 1'b0,
_theResult___fst_exp__h365378 != 8'd0,
_theResult___snd__h365329[56:34] } +
25'd1 ;
assign sfd__h374580 =
{ 1'b0,
_theResult___fst_exp__h374488 != 8'd0,
sfdin__h374482[56:34] } +
25'd1 ;
assign sfd__h383192 =
{ 1'b0,
_theResult___fst_exp__h383173 != 8'd0,
_theResult___snd__h383119[56:34] } +
25'd1 ;
assign sfd__h386708 = { value__h394930, 3'd0 } ;
assign sfd__h402511 =
{ 1'b0,
_theResult___fst_exp__h402419 != 8'd0,
sfdin__h402413[56:34] } +
25'd1 ;
assign sfd__h411093 =
{ 1'b0,
_theResult___fst_exp__h411075 != 8'd0,
_theResult___snd__h411026[56:34] } +
25'd1 ;
assign sfd__h420277 =
{ 1'b0,
_theResult___fst_exp__h420185 != 8'd0,
sfdin__h420179[56:34] } +
25'd1 ;
assign sfd__h428889 =
{ 1'b0,
_theResult___fst_exp__h428870 != 8'd0,
_theResult___snd__h428816[56:34] } +
25'd1 ;
assign sfd__h432403 = { value__h440625, 3'd0 } ;
assign sfd__h448206 =
{ 1'b0,
_theResult___fst_exp__h448114 != 8'd0,
sfdin__h448108[56:34] } +
25'd1 ;
assign sfd__h456788 =
{ 1'b0,
_theResult___fst_exp__h456770 != 8'd0,
_theResult___snd__h456721[56:34] } +
25'd1 ;
assign sfd__h465972 =
{ 1'b0,
_theResult___fst_exp__h465880 != 8'd0,
sfdin__h465874[56:34] } +
25'd1 ;
assign sfd__h474584 =
{ 1'b0,
_theResult___fst_exp__h474565 != 8'd0,
_theResult___snd__h474511[56:34] } +
25'd1 ;
assign sfd__h485537 = { value__h490120, 32'd0 } ;
assign sfd__h504581 =
{ 1'b0,
_theResult___fst_exp__h504563 != 11'd0,
_theResult___snd__h504514[56:5] } +
54'd1 ;
assign sfd__h514232 =
{ 1'b0,
_theResult___fst_exp__h514140 != 11'd0,
sfdin__h514134[56:5] } +
54'd1 ;
assign sfd__h522992 =
{ 1'b0,
_theResult___fst_exp__h522973 != 11'd0,
_theResult___snd__h522919[56:5] } +
54'd1 ;
assign sfd__h524531 = { value__h528973, 32'd0 } ;
assign sfd__h543434 =
{ 1'b0,
_theResult___fst_exp__h543416 != 11'd0,
_theResult___snd__h543367[56:5] } +
54'd1 ;
assign sfd__h553085 =
{ 1'b0,
_theResult___fst_exp__h552993 != 11'd0,
sfdin__h552987[56:5] } +
54'd1 ;
assign sfd__h561845 =
{ 1'b0,
_theResult___fst_exp__h561826 != 11'd0,
_theResult___snd__h561772[56:5] } +
54'd1 ;
assign sfd__h563835 = { value__h568277, 32'd0 } ;
assign sfd__h582738 =
{ 1'b0,
_theResult___fst_exp__h582720 != 11'd0,
_theResult___snd__h582671[56:5] } +
54'd1 ;
assign sfd__h592389 =
{ 1'b0,
_theResult___fst_exp__h592297 != 11'd0,
sfdin__h592291[56:5] } +
54'd1 ;
assign sfd__h601149 =
{ 1'b0,
_theResult___fst_exp__h601130 != 11'd0,
_theResult___snd__h601076[56:5] } +
54'd1 ;
assign sfdin__h356716 =
_theResult____h348611[56] ?
_theResult___snd__h356733 :
_theResult___snd__h356744 ;
assign sfdin__h374482 =
_theResult____h366250[56] ?
_theResult___snd__h374499 :
_theResult___snd__h374510 ;
assign sfdin__h402413 =
_theResult____h394310[56] ?
_theResult___snd__h402430 :
_theResult___snd__h402441 ;
assign sfdin__h420179 =
_theResult____h411947[56] ?
_theResult___snd__h420196 :
_theResult___snd__h420207 ;
assign sfdin__h448108 =
_theResult____h440005[56] ?
_theResult___snd__h448125 :
_theResult___snd__h448136 ;
assign sfdin__h465874 =
_theResult____h457642[56] ?
_theResult___snd__h465891 :
_theResult___snd__h465902 ;
assign sfdin__h514134 =
_theResult____h505904[56] ?
_theResult___snd__h514151 :
_theResult___snd__h514162 ;
assign sfdin__h552987 =
_theResult____h544757[56] ?
_theResult___snd__h553004 :
_theResult___snd__h553015 ;
assign sfdin__h592291 =
_theResult____h584061[56] ?
_theResult___snd__h592308 :
_theResult___snd__h592319 ;
assign shiftData__h184291 =
coreFix_memExe_regToExeQ$first[75:12] << x__h184420 ;
assign sie_csr__read__h614028 =
{ r1__read__h617312, csrf_software_int_en_vec_0 } ;
assign sip_csr__read__h614401 =
{ r1__read__h617866, csrf_software_int_pend_vec_0 } ;
assign spec_bits__h690442 = specTagManager$currentSpecBits | y__h690455 ;
assign sstatus_csr__read__h613959 = { r1__read__h616908, csrf_ie_vec_0 } ;
assign stvec_csr__read__h614071 =
{ r1__read__h617842, csrf_stvec_mode_low_reg } ;
assign tsr_val__h723699 = csrf_tsr_reg ;
assign tvm_val__h723701 = csrf_tvm_reg ;
assign upd__h3994 =
WILL_FIRE_RL_commitStage_doCommitSystemInst ?
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 :
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ;
assign upd__h5311 = n__read__h6607 + 64'd1 ;
assign upd__h6721 =
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign upd__h724191 =
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign v__h298467 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3128) ?
v__h298698 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ;
assign v__h298698 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd7) ?
3'd0 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP +
3'd1 ;
assign v__h301812 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3235) ?
v__h302330 :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ;
assign v__h302330 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ;
assign v__h312326 =
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3406) ?
v__h312557 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ;
assign v__h312557 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ;
assign v__h316202 =
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3502) ?
v__h316433 :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ;
assign v__h316433 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ;
assign v__h330803 =
(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3731) ?
v__h331034 :
coreFix_memExe_memRespLdQ_enqP ;
assign v__h331034 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ;
assign v__h334028 =
(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3825) ?
v__h334259 :
coreFix_memExe_forwardQ_enqP ;
assign v__h334259 = coreFix_memExe_forwardQ_enqP + 1'd1 ;
assign v__h607240 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ?
v__h607250 :
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ;
assign v__h607250 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ;
assign v__h608281 = v__h607240 - 2'd1 ;
assign v__h612270 =
sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h613404 ;
assign v__h637067 =
sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h638049 ;
assign vaddr__h184286 =
coreFix_memExe_regToExeQ$first[139:76] +
{ {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q13[31]}},
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q13 } ;
assign value__h349233 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ;
assign value__h394930 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ;
assign value__h440625 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ;
assign value__h490120 = { 1'b0, f1_exp__h485175 != 8'd0, f1_sfd__h485176 } ;
assign value__h528973 = { 1'b0, f2_exp__h524169 != 8'd0, f2_sfd__h524170 } ;
assign value__h568277 = { 1'b0, f3_exp__h563473 != 8'd0, f3_sfd__h563474 } ;
assign vm_mode_reg__read__h618102 = { csrf_vm_mode_sv39_reg, 3'b0 } ;
assign w__h650828 =
coreFix_globalSpecUpdate_correctSpecTag_0$whas ?
result__h650884 :
12'd4095 ;
assign x__h155113 =
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] :
coreFix_memExe_reqLdQ_data_0_rl[68:64]) :
5'd0 ;
assign x__h155119 =
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] :
coreFix_memExe_reqLdQ_data_0_rl[63:0]) :
64'd0 ;
assign x__h158660 = { 3'd0, sbIdx__h158539 } ;
assign x__h158666 =
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] :
coreFix_memExe_reqStQ_data_0_rl[63:0]) :
64'd0 ;
assign x__h161476 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) :
5'd0 ;
assign x__h161480 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) :
64'd0 ;
assign x__h163328 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) :
64'd0 ;
assign x__h18215 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[141:78] :
mmio_dataReqQ_enqReq_rl[141:78] ;
assign x__h184198 =
sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183364 ;
assign x__h184199 =
sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184045 ;
assign x__h184420 = { vaddr__h184286[2:0], 3'b0 } ;
assign x__h194721 =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ?
curData__h193958[63:32] :
curData__h193958[31:0] ;
assign x__h20753 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[63:0] :
mmio_dataReqQ_enqReq_rl[63:0] ;
assign x__h289738 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) :
5'd0 ;
assign x__h289750 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) :
64'd0 ;
assign x__h291604 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) :
64'd0 ;
assign x__h304677 =
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ;
assign x__h340410 =
{ (_theResult___exp__h383742 != 8'd255 ||
_theResult___sfd__h383743 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5237,
out_f_exp__h384019,
out_f_sfd__h384020 } ;
assign x__h366960 =
sfd__h341006 << (x__h366993[11] ? 12'hAAA : x__h366993) ;
assign x__h366993 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4651 ;
assign x__h386112 =
{ (_theResult___exp__h429439 != 8'd255 ||
_theResult___sfd__h429440 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6629,
out_f_exp__h429716,
out_f_sfd__h429717 } ;
assign x__h412657 =
sfd__h386708 << (x__h412690[11] ? 12'hAAA : x__h412690) ;
assign x__h412690 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6043 ;
assign x__h431807 =
{ (_theResult___exp__h475134 != 8'd255 ||
_theResult___sfd__h475135 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8021,
out_f_exp__h475411,
out_f_sfd__h475412 } ;
assign x__h458352 =
sfd__h432403 << (x__h458385[11] ? 12'hAAA : x__h458385) ;
assign x__h458385 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7435 ;
assign x__h46122 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[141:78] :
mmio_cRqQ_enqReq_rl[141:78] ;
assign x__h484697 =
sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h481835 ;
assign x__h484698 =
sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h482519 ;
assign x__h484699 =
sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h483196 ;
assign x__h48658 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[63:0] :
mmio_cRqQ_enqReq_rl[63:0] ;
assign x__h506612 = sfd__h485537 << x__h506645 ;
assign x__h506645 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8761 ;
assign x__h545465 = sfd__h524531 << x__h545498 ;
assign x__h545498 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10246 ;
assign x__h584769 = sfd__h563835 << x__h584802 ;
assign x__h584802 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9476 ;
assign x__h606558 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
_theResult___fst__h606569 :
a__h606021 ;
assign x__h606584 = a__h606021[63] ^ b__h606022[63] ;
assign x__h607170 =
(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ==
64'd0) ?
{ 64'hFFFFFFFFFFFFFFFF,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } :
{ coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11258 } ;
assign x__h616893 = { csrf_frm_reg, csrf_fflags_reg } ;
assign x__h621197 =
coreFix_aluExe_1_dispToRegQ$first[131] ?
rVal1__h613461 :
v__h612270 ;
assign x__h621198 =
sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h619207 ;
assign x__h643562 =
coreFix_aluExe_0_dispToRegQ$first[131] ?
rVal1__h638104 :
v__h637067 ;
assign x__h643563 =
sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h641582 ;
assign x__h650832 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ;
assign x__h650883 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ;
assign x__h702237 =
(!rob$deqPort_0_deq_data[166] &&
(rob$deqPort_0_deq_data[165:162] == 4'd1 ||
rob$deqPort_0_deq_data[165:162] == 4'd12)) ?
rob$deqPort_0_deq_data[161:98] :
rob$deqPort_0_deq_data[95:32] ;
assign x__h711183 = { cause_code__h708328, 2'b0 } ;
assign x__h712324 =
{ csrf_fs_reg == 2'b11,
IF_csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_c_ETC___d15130 } ;
assign x__h712515 =
{ commitStage_commitTrap[4], 59'b0, cause_code__h708328 } ;
assign x__h720450 = { 1'b0, csrf_spp_reg } ;
assign x__h723610 =
{ csrf_fs_reg == 2'b11,
IF_rob_deqPort_0_deq_data__4560_BITS_257_TO_25_ETC___d15475 } ;
assign x__h729365 =
NOT_rob_deqPort_0_canDeq__5509_5510_OR_rob_deq_ETC___d15811 ?
y_avValue_snd_snd_snd_fst__h729189 :
IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15838 ;
assign x__h76067 = mmio_pRqQ_data_0[31:0] ;
assign x_addr__h316600 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ;
assign x_data__h65916 =
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[31:0] :
mmio_pRqQ_enqReq_rl[31:0] ;
assign x_data_imm__h679352 = fetchStage$pipelines_0_first[159:128] ;
assign x_data_imm__h694985 = fetchStage$pipelines_1_first[159:128] ;
assign x_decodeInfo_frm__h659119 = csrf_frm_reg ;
assign x_prv__h711252 =
csrf_prv_reg_read__2962_ULE_1_4914_AND_IF_comm_ETC___d14936 ?
2'd1 :
2'd3 ;
assign x_prv__h720900 =
(rob$deqPort_0_deq_data[257:253] == 5'd19) ?
x__h720450 :
csrf_mpp_reg ;
assign x_quotient__h477795 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ?
64'hFFFFFFFFFFFFFFFF :
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ?
q___1__h478580 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ;
assign x_reg_ifc__read__h613868 = { 63'd0, csrf_stats_module_doStats } ;
assign x_remainder__h477796 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ?
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] :
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ?
r___1__h478607 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ;
assign y__h256656 =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ;
assign y__h623923 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ;
assign y__h645995 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ;
assign y__h650862 = ~x__h650832 ;
assign y__h655793 =
{ 4'd15,
~csrf_mideleg_11_reg,
1'd1,
~csrf_mideleg_9_7_reg,
1'd1,
~csrf_mideleg_5_3_reg,
1'd1,
~csrf_mideleg_1_0_reg } ;
assign y__h690455 = 12'd1 << specTagManager$nextSpecTag ;
assign y__h727463 =
rob$deqPort_0_canDeq ?
y_avValue_snd_snd_snd_snd_snd__h727478 :
64'd0 ;
assign y__h729146 =
NOT_rob_deqPort_0_canDeq__5509_5510_OR_rob_deq_ETC___d15811 ?
y_avValue_snd_snd_snd_snd_snd__h729195 :
y__h727463 ;
assign y_avValue__h183364 =
NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1612 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1680 ;
assign y_avValue__h184045 =
NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1641 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1688 ;
assign y_avValue__h481835 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8328 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8455 ;
assign y_avValue__h482519 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8357 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8463 ;
assign y_avValue__h483196 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8383 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8471 ;
assign y_avValue__h613404 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1511_1_ETC___d11538 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11947 ;
assign y_avValue__h619207 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1511_1_ETC___d11568 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11956 ;
assign y_avValue__h638049 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2370_2_ETC___d12397 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12621 ;
assign y_avValue__h641582 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2370_2_ETC___d12427 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12630 ;
assign y_avValue_fst__h683715 =
(fetchStage$pipelines_0_first[194:192] == 3'd1) ?
spec_bits__h690442 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h683744 =
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 ?
y_avValue_fst__h683715 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h683778 =
((fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604) ?
y_avValue_fst__h683744 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h727013 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[257:253] == 5'd0 ||
rob$deqPort_0_deq_data[257:253] == 5'd21 ||
rob$deqPort_0_deq_data[257:253] == 5'd17 ||
rob$deqPort_0_deq_data[257:253] == 5'd18 ||
rob$deqPort_0_deq_data[257:253] == 5'd13 ||
rob$deqPort_0_deq_data[257:253] == 5'd16 ||
rob$deqPort_0_deq_data[257:253] == 5'd15 ||
rob$deqPort_0_deq_data[257:253] == 5'd19 ||
rob$deqPort_0_deq_data[257:253] == 5'd20) ?
5'd0 :
rob$deqPort_0_deq_data[31:27] ;
assign y_avValue_fst__h729038 =
IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15817 |
rob$deqPort_1_deq_data[31:27] ;
assign y_avValue_fst__h729066 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[257:253] == 5'd0 ||
rob$deqPort_1_deq_data[257:253] == 5'd21 ||
rob$deqPort_1_deq_data[257:253] == 5'd17 ||
rob$deqPort_1_deq_data[257:253] == 5'd18 ||
rob$deqPort_1_deq_data[257:253] == 5'd13 ||
rob$deqPort_1_deq_data[257:253] == 5'd16 ||
rob$deqPort_1_deq_data[257:253] == 5'd15 ||
rob$deqPort_1_deq_data[257:253] == 5'd19 ||
rob$deqPort_1_deq_data[257:253] == 5'd20) ?
IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15817 :
y_avValue_fst__h729038 ;
assign y_avValue_new_pc__h710944 =
(csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ?
base__h711168 + { 58'd0, x__h711183 } :
base__h711168 ;
assign y_avValue_new_pc__h711130 =
(csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ?
base__h711188 + { 58'd0, x__h711183 } :
base__h711188 ;
assign y_avValue_snd_snd_snd_fst__h727472 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[257:253] == 5'd0 ||
rob$deqPort_0_deq_data[257:253] == 5'd21 ||
rob$deqPort_0_deq_data[257:253] == 5'd17 ||
rob$deqPort_0_deq_data[257:253] == 5'd18 ||
rob$deqPort_0_deq_data[257:253] == 5'd13 ||
rob$deqPort_0_deq_data[257:253] == 5'd16 ||
rob$deqPort_0_deq_data[257:253] == 5'd15 ||
rob$deqPort_0_deq_data[257:253] == 5'd19 ||
rob$deqPort_0_deq_data[257:253] == 5'd20) ?
2'd0 :
2'd1 ;
assign y_avValue_snd_snd_snd_fst__h729189 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[257:253] == 5'd0 ||
rob$deqPort_1_deq_data[257:253] == 5'd21 ||
rob$deqPort_1_deq_data[257:253] == 5'd17 ||
rob$deqPort_1_deq_data[257:253] == 5'd18 ||
rob$deqPort_1_deq_data[257:253] == 5'd13 ||
rob$deqPort_1_deq_data[257:253] == 5'd16 ||
rob$deqPort_1_deq_data[257:253] == 5'd15 ||
rob$deqPort_1_deq_data[257:253] == 5'd19 ||
rob$deqPort_1_deq_data[257:253] == 5'd20) ?
IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15838 :
y_avValue_snd_snd_snd_fst__h729218 ;
assign y_avValue_snd_snd_snd_fst__h729218 =
IF_rob_deqPort_0_canDeq__5509_THEN_IF_NOT_rob__ETC___d15838 +
2'd1 ;
assign y_avValue_snd_snd_snd_snd_snd__h727478 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[257:253] == 5'd0 ||
rob$deqPort_0_deq_data[257:253] == 5'd21 ||
rob$deqPort_0_deq_data[257:253] == 5'd17 ||
rob$deqPort_0_deq_data[257:253] == 5'd18 ||
rob$deqPort_0_deq_data[257:253] == 5'd13 ||
rob$deqPort_0_deq_data[257:253] == 5'd16 ||
rob$deqPort_0_deq_data[257:253] == 5'd15 ||
rob$deqPort_0_deq_data[257:253] == 5'd19 ||
rob$deqPort_0_deq_data[257:253] == 5'd20) ?
64'd0 :
64'd1 ;
assign y_avValue_snd_snd_snd_snd_snd__h729195 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[257:253] == 5'd0 ||
rob$deqPort_1_deq_data[257:253] == 5'd21 ||
rob$deqPort_1_deq_data[257:253] == 5'd17 ||
rob$deqPort_1_deq_data[257:253] == 5'd18 ||
rob$deqPort_1_deq_data[257:253] == 5'd13 ||
rob$deqPort_1_deq_data[257:253] == 5'd16 ||
rob$deqPort_1_deq_data[257:253] == 5'd15 ||
rob$deqPort_1_deq_data[257:253] == 5'd19 ||
rob$deqPort_1_deq_data[257:253] == 5'd20) ?
y__h727463 :
y_avValue_snd_snd_snd_snd_snd__h729224 ;
assign y_avValue_snd_snd_snd_snd_snd__h729224 = y__h727463 + 64'd1 ;
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[475:464])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1 =
v_f_to_TV_1$D_OUT[475:464];
default: CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1 =
12'd2303;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[461:458])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 =
v_f_to_TV_1$D_OUT[461:458];
default: CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 = 4'd15;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[461:458])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3 =
v_f_to_TV_1$D_OUT[461:458];
default: CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3 = 4'd15;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[393:392])
2'd0, 2'd1:
CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4 =
v_f_to_TV_1$D_OUT[393:392];
default: CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4 = 2'd2;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[475:464])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5 =
v_f_to_TV_0$D_OUT[475:464];
default: CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5 =
12'd2303;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[461:458])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 =
v_f_to_TV_0$D_OUT[461:458];
default: CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 = 4'd15;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[461:458])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7 =
v_f_to_TV_0$D_OUT[461:458];
default: CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7 = 4'd15;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[393:392])
2'd0, 2'd1:
CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8 =
v_f_to_TV_0$D_OUT[393:392];
default: CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8 = 2'd2;
endcase
end
always@(mmio_cRqQ_data_0)
begin
case (mmio_cRqQ_data_0[77:76])
2'd0, 2'd1, 2'd2:
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 =
mmio_cRqQ_data_0[77:72];
2'd3:
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 =
{ 2'd3, mmio_cRqQ_data_0[75:72] };
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87])
3'd0:
x__h198698 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
3'd1:
x__h198698 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
3'd2:
x__h198698 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
3'd3:
x__h198698 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
3'd4:
x__h198698 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
3'd5:
x__h198698 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
3'd6:
x__h198698 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
3'd7:
x__h198698 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP)
3'd0:
x__h288305 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
3'd1:
x__h288305 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
3'd2:
x__h288305 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
3'd3:
x__h288305 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
3'd4:
x__h288305 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
3'd5:
x__h288305 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
3'd6:
x__h288305 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
3'd7:
x__h288305 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
addr__h292526 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518];
1'd1:
addr__h292526 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91])
3'd0:
curData__h193958 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
3'd1:
curData__h193958 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
3'd2:
curData__h193958 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
3'd3:
curData__h193958 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
3'd4:
curData__h193958 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
3'd5:
curData__h193958 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
3'd6:
curData__h193958 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
3'd7:
curData__h193958 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0, 4'd3: trap_val__h709367 = commitStage_commitTrap[132:69];
default: trap_val__h709367 =
(commitStage_commitTrap[3:0] != 4'd2 &&
commitStage_commitTrap[3:0] != 4'd8 &&
commitStage_commitTrap[3:0] != 4'd9 &&
commitStage_commitTrap[3:0] != 4'd11) ?
commitStage_commitTrap[68:5] :
64'd0;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
x__h294075 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0];
1'd1:
x__h294075 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0];
endcase
end
always@(f_csr_reqs$D_OUT or
fflags_csr__read__h613738 or
frm_csr__read__h613749 or
fcsr_csr__read__h613763 or
sstatus_csr__read__h613959 or
sie_csr__read__h614028 or
stvec_csr__read__h614071 or
scounteren_csr__read__h614124 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h614262 or
csrf_stval_csr or
sip_csr__read__h614401 or
satp_csr__read__h614464 or
mstatus_csr__read__h614607 or
medeleg_csr__read__h614755 or
mideleg_csr__read__h614850 or
mie_csr__read__h614974 or
mtvec_csr__read__h615056 or
mcounteren_csr__read__h615148 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h615403 or
csrf_mtval_csr or
mip_csr__read__h615636 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h613868 or
n__read__h615740 or n__read__h615931 or csrf_time_reg)
begin
case (f_csr_reqs$D_OUT[75:64])
12'd1: data_out__h733205 = fflags_csr__read__h613738;
12'd2: data_out__h733205 = frm_csr__read__h613749;
12'd3: data_out__h733205 = fcsr_csr__read__h613763;
12'd256: data_out__h733205 = sstatus_csr__read__h613959;
12'd260: data_out__h733205 = sie_csr__read__h614028;
12'd261: data_out__h733205 = stvec_csr__read__h614071;
12'd262: data_out__h733205 = scounteren_csr__read__h614124;
12'd320: data_out__h733205 = csrf_sscratch_csr;
12'd321: data_out__h733205 = csrf_sepc_csr;
12'd322: data_out__h733205 = scause_csr__read__h614262;
12'd323: data_out__h733205 = csrf_stval_csr;
12'd324: data_out__h733205 = sip_csr__read__h614401;
12'd384: data_out__h733205 = satp_csr__read__h614464;
12'd768: data_out__h733205 = mstatus_csr__read__h614607;
12'd769: data_out__h733205 = 64'h800000000014112D;
12'd770: data_out__h733205 = medeleg_csr__read__h614755;
12'd771: data_out__h733205 = mideleg_csr__read__h614850;
12'd772: data_out__h733205 = mie_csr__read__h614974;
12'd773: data_out__h733205 = mtvec_csr__read__h615056;
12'd774: data_out__h733205 = mcounteren_csr__read__h615148;
12'd832: data_out__h733205 = csrf_mscratch_csr;
12'd833: data_out__h733205 = csrf_mepc_csr;
12'd834: data_out__h733205 = mcause_csr__read__h615403;
12'd835: data_out__h733205 = csrf_mtval_csr;
12'd836: data_out__h733205 = mip_csr__read__h615636;
12'd1968: data_out__h733205 = csrf_rg_dcsr;
12'd1969: data_out__h733205 = csrf_rg_dpc;
12'd1970: data_out__h733205 = csrf_rg_dscratch0;
12'd1971: data_out__h733205 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
data_out__h733205 = 64'd0;
12'd2049: data_out__h733205 = x_reg_ifc__read__h613868;
12'd2816, 12'd3072: data_out__h733205 = n__read__h615740;
12'd2818, 12'd3074: data_out__h733205 = n__read__h615931;
12'd3073: data_out__h733205 = csrf_time_reg;
default: data_out__h733205 = 64'b0;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first or
fflags_csr__read__h613738 or
frm_csr__read__h613749 or
fcsr_csr__read__h613763 or
sstatus_csr__read__h613959 or
sie_csr__read__h614028 or
stvec_csr__read__h614071 or
scounteren_csr__read__h614124 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h614262 or
csrf_stval_csr or
sip_csr__read__h614401 or
satp_csr__read__h614464 or
mstatus_csr__read__h614607 or
medeleg_csr__read__h614755 or
mideleg_csr__read__h614850 or
mie_csr__read__h614974 or
mtvec_csr__read__h615056 or
mcounteren_csr__read__h615148 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h615403 or
csrf_mtval_csr or
mip_csr__read__h615636 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h613868 or
n__read__h615740 or n__read__h615931 or csrf_time_reg)
begin
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
12'd1: rVal1__h613461 = fflags_csr__read__h613738;
12'd2: rVal1__h613461 = frm_csr__read__h613749;
12'd3: rVal1__h613461 = fcsr_csr__read__h613763;
12'd256: rVal1__h613461 = sstatus_csr__read__h613959;
12'd260: rVal1__h613461 = sie_csr__read__h614028;
12'd261: rVal1__h613461 = stvec_csr__read__h614071;
12'd262: rVal1__h613461 = scounteren_csr__read__h614124;
12'd320: rVal1__h613461 = csrf_sscratch_csr;
12'd321: rVal1__h613461 = csrf_sepc_csr;
12'd322: rVal1__h613461 = scause_csr__read__h614262;
12'd323: rVal1__h613461 = csrf_stval_csr;
12'd324: rVal1__h613461 = sip_csr__read__h614401;
12'd384: rVal1__h613461 = satp_csr__read__h614464;
12'd768: rVal1__h613461 = mstatus_csr__read__h614607;
12'd769: rVal1__h613461 = 64'h800000000014112D;
12'd770: rVal1__h613461 = medeleg_csr__read__h614755;
12'd771: rVal1__h613461 = mideleg_csr__read__h614850;
12'd772: rVal1__h613461 = mie_csr__read__h614974;
12'd773: rVal1__h613461 = mtvec_csr__read__h615056;
12'd774: rVal1__h613461 = mcounteren_csr__read__h615148;
12'd832: rVal1__h613461 = csrf_mscratch_csr;
12'd833: rVal1__h613461 = csrf_mepc_csr;
12'd834: rVal1__h613461 = mcause_csr__read__h615403;
12'd835: rVal1__h613461 = csrf_mtval_csr;
12'd836: rVal1__h613461 = mip_csr__read__h615636;
12'd1968: rVal1__h613461 = csrf_rg_dcsr;
12'd1969: rVal1__h613461 = csrf_rg_dpc;
12'd1970: rVal1__h613461 = csrf_rg_dscratch0;
12'd1971: rVal1__h613461 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
rVal1__h613461 = 64'd0;
12'd2049: rVal1__h613461 = x_reg_ifc__read__h613868;
12'd2816, 12'd3072: rVal1__h613461 = n__read__h615740;
12'd2818, 12'd3074: rVal1__h613461 = n__read__h615931;
12'd3073: rVal1__h613461 = csrf_time_reg;
default: rVal1__h613461 = 64'b0;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first or
fflags_csr__read__h613738 or
frm_csr__read__h613749 or
fcsr_csr__read__h613763 or
sstatus_csr__read__h613959 or
sie_csr__read__h614028 or
stvec_csr__read__h614071 or
scounteren_csr__read__h614124 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h614262 or
csrf_stval_csr or
sip_csr__read__h614401 or
satp_csr__read__h614464 or
mstatus_csr__read__h614607 or
medeleg_csr__read__h614755 or
mideleg_csr__read__h614850 or
mie_csr__read__h614974 or
mtvec_csr__read__h615056 or
mcounteren_csr__read__h615148 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h615403 or
csrf_mtval_csr or
mip_csr__read__h615636 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h613868 or
n__read__h615740 or n__read__h615931 or csrf_time_reg)
begin
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
12'd1: rVal1__h638104 = fflags_csr__read__h613738;
12'd2: rVal1__h638104 = frm_csr__read__h613749;
12'd3: rVal1__h638104 = fcsr_csr__read__h613763;
12'd256: rVal1__h638104 = sstatus_csr__read__h613959;
12'd260: rVal1__h638104 = sie_csr__read__h614028;
12'd261: rVal1__h638104 = stvec_csr__read__h614071;
12'd262: rVal1__h638104 = scounteren_csr__read__h614124;
12'd320: rVal1__h638104 = csrf_sscratch_csr;
12'd321: rVal1__h638104 = csrf_sepc_csr;
12'd322: rVal1__h638104 = scause_csr__read__h614262;
12'd323: rVal1__h638104 = csrf_stval_csr;
12'd324: rVal1__h638104 = sip_csr__read__h614401;
12'd384: rVal1__h638104 = satp_csr__read__h614464;
12'd768: rVal1__h638104 = mstatus_csr__read__h614607;
12'd769: rVal1__h638104 = 64'h800000000014112D;
12'd770: rVal1__h638104 = medeleg_csr__read__h614755;
12'd771: rVal1__h638104 = mideleg_csr__read__h614850;
12'd772: rVal1__h638104 = mie_csr__read__h614974;
12'd773: rVal1__h638104 = mtvec_csr__read__h615056;
12'd774: rVal1__h638104 = mcounteren_csr__read__h615148;
12'd832: rVal1__h638104 = csrf_mscratch_csr;
12'd833: rVal1__h638104 = csrf_mepc_csr;
12'd834: rVal1__h638104 = mcause_csr__read__h615403;
12'd835: rVal1__h638104 = csrf_mtval_csr;
12'd836: rVal1__h638104 = mip_csr__read__h615636;
12'd1968: rVal1__h638104 = csrf_rg_dcsr;
12'd1969: rVal1__h638104 = csrf_rg_dpc;
12'd1970: rVal1__h638104 = csrf_rg_dscratch0;
12'd1971: rVal1__h638104 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
rVal1__h638104 = 64'd0;
12'd2049: rVal1__h638104 = x_reg_ifc__read__h613868;
12'd2816, 12'd3072: rVal1__h638104 = n__read__h615740;
12'd2818, 12'd3074: rVal1__h638104 = n__read__h615931;
12'd3073: rVal1__h638104 = csrf_time_reg;
default: rVal1__h638104 = 64'b0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h348593 = 8'd255;
3'd2:
_theResult___fst_exp__h348593 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h348593 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h348593 = 8'd254;
default: _theResult___fst_exp__h348593 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h348594 = 23'd0;
3'd2:
_theResult___fst_sfd__h348594 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h348594 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h348594 = 23'd8388607;
default: _theResult___fst_sfd__h348594 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h394292 = 8'd255;
3'd2:
_theResult___fst_exp__h394292 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h394292 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h394292 = 8'd254;
default: _theResult___fst_exp__h394292 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h394293 = 23'd0;
3'd2:
_theResult___fst_sfd__h394293 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h394293 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h394293 = 23'd8388607;
default: _theResult___fst_sfd__h394293 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h439987 = 8'd255;
3'd2:
_theResult___fst_exp__h439987 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h439987 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h439987 = 8'd254;
default: _theResult___fst_exp__h439987 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h439988 = 23'd0;
3'd2:
_theResult___fst_sfd__h439988 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h439988 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h439988 = 23'd8388607;
default: _theResult___fst_sfd__h439988 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 = 52'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 = 52'd0;
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
i__h708343 = commitStage_commitTrap[3:0];
default: i__h708343 = 4'd15;
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
i__h708503 = commitStage_commitTrap[3:0];
default: i__h708503 = 4'd15;
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19])
1'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356 =
coreFix_memExe_respLrScAmoQ_data_0[31:0];
1'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356 =
coreFix_memExe_respLrScAmoQ_data_0[63:32];
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:18])
2'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 =
coreFix_memExe_respLrScAmoQ_data_0[15:0];
2'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 =
coreFix_memExe_respLrScAmoQ_data_0[31:16];
2'd2:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 =
coreFix_memExe_respLrScAmoQ_data_0[47:32];
2'd3:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 =
coreFix_memExe_respLrScAmoQ_data_0[63:48];
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:17])
3'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
coreFix_memExe_respLrScAmoQ_data_0[7:0];
3'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
coreFix_memExe_respLrScAmoQ_data_0[15:8];
3'd2:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
coreFix_memExe_respLrScAmoQ_data_0[23:16];
3'd3:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
coreFix_memExe_respLrScAmoQ_data_0[31:24];
3'd4:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
coreFix_memExe_respLrScAmoQ_data_0[39:32];
3'd5:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
coreFix_memExe_respLrScAmoQ_data_0[47:40];
3'd6:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
coreFix_memExe_respLrScAmoQ_data_0[55:48];
3'd7:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
coreFix_memExe_respLrScAmoQ_data_0[63:56];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19])
1'd0:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 =
mmio_dataRespQ_data_0[31:0];
1'd1:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 =
mmio_dataRespQ_data_0[63:32];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:18])
2'd0:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 =
mmio_dataRespQ_data_0[15:0];
2'd1:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 =
mmio_dataRespQ_data_0[31:16];
2'd2:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 =
mmio_dataRespQ_data_0[47:32];
2'd3:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 =
mmio_dataRespQ_data_0[63:48];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:17])
3'd0:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
mmio_dataRespQ_data_0[7:0];
3'd1:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
mmio_dataRespQ_data_0[15:8];
3'd2:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
mmio_dataRespQ_data_0[23:16];
3'd3:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
mmio_dataRespQ_data_0[31:24];
3'd4:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
mmio_dataRespQ_data_0[39:32];
3'd5:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
mmio_dataRespQ_data_0[47:40];
3'd6:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
mmio_dataRespQ_data_0[55:48];
3'd7:
SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
mmio_dataRespQ_data_0[63:56];
endcase
end
always@(coreFix_memExe_dTlb$procResp)
begin
case (coreFix_memExe_dTlb$procResp[105:103])
3'd0, 3'd2:
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q21 = 4'd4;
default: CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q21 = 4'd6;
endcase
end
always@(coreFix_memExe_dTlb$procResp)
begin
case (coreFix_memExe_dTlb$procResp[109:106])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 =
coreFix_memExe_dTlb$procResp[109:106];
4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = 4'd10;
4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = 4'd11;
4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = 4'd12;
default: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = 4'd13;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2969 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[65:2];
1'd1:
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2969 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[65:2];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131];
endcase
end
always@(guard__h357330 or
_theResult___fst_exp__h365378 or
out_exp__h365823 or _theResult___exp__h365820)
begin
case (guard__h357330)
2'b0, 2'b01:
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q33 =
_theResult___fst_exp__h365378;
2'b10:
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q33 =
out_exp__h365823;
2'b11:
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q33 =
_theResult___exp__h365820;
endcase
end
always@(guard__h357330 or
_theResult___fst_exp__h365378 or _theResult___exp__h365820)
begin
case (guard__h357330)
2'b0:
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q34 =
_theResult___fst_exp__h365378;
2'b01, 2'b10, 2'b11:
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q34 =
_theResult___exp__h365820;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q33 or
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q34 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4629 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4631 or
_theResult___fst_exp__h365378)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h365898 =
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q33;
3'd1:
_theResult___fst_exp__h365898 =
CASE_guard57330_0b0_theResult___fst_exp65378_0_ETC__q34;
3'd2:
_theResult___fst_exp__h365898 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4629;
3'd3:
_theResult___fst_exp__h365898 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4631;
3'd4: _theResult___fst_exp__h365898 = _theResult___fst_exp__h365378;
default: _theResult___fst_exp__h365898 = 8'd0;
endcase
end
always@(guard__h348621 or
_theResult___fst_exp__h356722 or
out_exp__h357241 or _theResult___exp__h357238)
begin
case (guard__h348621)
2'b0, 2'b01:
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q35 =
_theResult___fst_exp__h356722;
2'b10:
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q35 =
out_exp__h357241;
2'b11:
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q35 =
_theResult___exp__h357238;
endcase
end
always@(guard__h348621 or
_theResult___fst_exp__h356722 or _theResult___exp__h357238)
begin
case (guard__h348621)
2'b0:
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q36 =
_theResult___fst_exp__h356722;
2'b01, 2'b10, 2'b11:
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q36 =
_theResult___exp__h357238;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q35 or
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q36 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4407 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410 or
_theResult___fst_exp__h356722)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h357316 =
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q35;
3'd1:
_theResult___fst_exp__h357316 =
CASE_guard48621_0b0_theResult___fst_exp56722_0_ETC__q36;
3'd2:
_theResult___fst_exp__h357316 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4407;
3'd3:
_theResult___fst_exp__h357316 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410;
3'd4: _theResult___fst_exp__h357316 = _theResult___fst_exp__h356722;
default: _theResult___fst_exp__h357316 = 8'd0;
endcase
end
always@(guard__h366260 or
_theResult___fst_exp__h374488 or
out_exp__h375007 or _theResult___exp__h375004)
begin
case (guard__h366260)
2'b0, 2'b01:
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q41 =
_theResult___fst_exp__h374488;
2'b10:
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q41 =
out_exp__h375007;
2'b11:
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q41 =
_theResult___exp__h375004;
endcase
end
always@(guard__h366260 or
_theResult___fst_exp__h374488 or _theResult___exp__h375004)
begin
case (guard__h366260)
2'b0:
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q42 =
_theResult___fst_exp__h374488;
2'b01, 2'b10, 2'b11:
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q42 =
_theResult___exp__h375004;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q41 or
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q42 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4954 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4956 or
_theResult___fst_exp__h374488)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h375082 =
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q41;
3'd1:
_theResult___fst_exp__h375082 =
CASE_guard66260_0b0_theResult___fst_exp74488_0_ETC__q42;
3'd2:
_theResult___fst_exp__h375082 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4954;
3'd3:
_theResult___fst_exp__h375082 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4956;
3'd4: _theResult___fst_exp__h375082 = _theResult___fst_exp__h374488;
default: _theResult___fst_exp__h375082 = 8'd0;
endcase
end
always@(guard__h375096 or
_theResult___fst_exp__h383173 or
out_exp__h383643 or _theResult___exp__h383640)
begin
case (guard__h375096)
2'b0, 2'b01:
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q46 =
_theResult___fst_exp__h383173;
2'b10:
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q46 =
out_exp__h383643;
2'b11:
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q46 =
_theResult___exp__h383640;
endcase
end
always@(guard__h375096 or
_theResult___fst_exp__h383173 or _theResult___exp__h383640)
begin
case (guard__h375096)
2'b0:
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q47 =
_theResult___fst_exp__h383173;
2'b01, 2'b10, 2'b11:
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q47 =
_theResult___exp__h383640;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q46 or
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q47 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5023 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5025 or
_theResult___fst_exp__h383173)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h383718 =
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q46;
3'd1:
_theResult___fst_exp__h383718 =
CASE_guard75096_0b0_theResult___fst_exp83173_0_ETC__q47;
3'd2:
_theResult___fst_exp__h383718 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5023;
3'd3:
_theResult___fst_exp__h383718 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5025;
3'd4: _theResult___fst_exp__h383718 = _theResult___fst_exp__h383173;
default: _theResult___fst_exp__h383718 = 8'd0;
endcase
end
always@(guard__h357330 or
_theResult___snd__h365329 or
out_sfd__h365824 or _theResult___sfd__h365821)
begin
case (guard__h357330)
2'b0, 2'b01:
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q48 =
_theResult___snd__h365329[56:34];
2'b10:
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q48 =
out_sfd__h365824;
2'b11:
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q48 =
_theResult___sfd__h365821;
endcase
end
always@(guard__h357330 or
_theResult___snd__h365329 or _theResult___sfd__h365821)
begin
case (guard__h357330)
2'b0:
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q49 =
_theResult___snd__h365329[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q49 =
_theResult___sfd__h365821;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q48 or
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q49 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5073 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5075 or
_theResult___snd__h365329)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h365899 =
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q48;
3'd1:
_theResult___fst_sfd__h365899 =
CASE_guard57330_0b0_theResult___snd65329_BITS__ETC__q49;
3'd2:
_theResult___fst_sfd__h365899 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5073;
3'd3:
_theResult___fst_sfd__h365899 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5075;
3'd4: _theResult___fst_sfd__h365899 = _theResult___snd__h365329[56:34];
default: _theResult___fst_sfd__h365899 = 23'd0;
endcase
end
always@(guard__h348621 or
sfdin__h356716 or out_sfd__h357242 or _theResult___sfd__h357239)
begin
case (guard__h348621)
2'b0, 2'b01:
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q50 =
sfdin__h356716[56:34];
2'b10:
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q50 =
out_sfd__h357242;
2'b11:
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q50 =
_theResult___sfd__h357239;
endcase
end
always@(guard__h348621 or sfdin__h356716 or _theResult___sfd__h357239)
begin
case (guard__h348621)
2'b0:
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q51 =
sfdin__h356716[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q51 =
_theResult___sfd__h357239;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q50 or
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q51 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5054 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5056 or
sfdin__h356716)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h357317 =
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q50;
3'd1:
_theResult___fst_sfd__h357317 =
CASE_guard48621_0b0_sfdin56716_BITS_56_TO_34_0_ETC__q51;
3'd2:
_theResult___fst_sfd__h357317 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5054;
3'd3:
_theResult___fst_sfd__h357317 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5056;
3'd4: _theResult___fst_sfd__h357317 = sfdin__h356716[56:34];
default: _theResult___fst_sfd__h357317 = 23'd0;
endcase
end
always@(guard__h366260 or
sfdin__h374482 or out_sfd__h375008 or _theResult___sfd__h375005)
begin
case (guard__h366260)
2'b0, 2'b01:
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q52 =
sfdin__h374482[56:34];
2'b10:
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q52 =
out_sfd__h375008;
2'b11:
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q52 =
_theResult___sfd__h375005;
endcase
end
always@(guard__h366260 or sfdin__h374482 or _theResult___sfd__h375005)
begin
case (guard__h366260)
2'b0:
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q53 =
sfdin__h374482[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q53 =
_theResult___sfd__h375005;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q52 or
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q53 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5100 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5102 or
sfdin__h374482)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h375083 =
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q52;
3'd1:
_theResult___fst_sfd__h375083 =
CASE_guard66260_0b0_sfdin74482_BITS_56_TO_34_0_ETC__q53;
3'd2:
_theResult___fst_sfd__h375083 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5100;
3'd3:
_theResult___fst_sfd__h375083 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5102;
3'd4: _theResult___fst_sfd__h375083 = sfdin__h374482[56:34];
default: _theResult___fst_sfd__h375083 = 23'd0;
endcase
end
always@(guard__h375096 or
_theResult___snd__h383119 or
out_sfd__h383644 or _theResult___sfd__h383641)
begin
case (guard__h375096)
2'b0, 2'b01:
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q54 =
_theResult___snd__h383119[56:34];
2'b10:
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q54 =
out_sfd__h383644;
2'b11:
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q54 =
_theResult___sfd__h383641;
endcase
end
always@(guard__h375096 or
_theResult___snd__h383119 or _theResult___sfd__h383641)
begin
case (guard__h375096)
2'b0:
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q55 =
_theResult___snd__h383119[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q55 =
_theResult___sfd__h383641;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q54 or
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q55 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5119 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5121 or
_theResult___snd__h383119)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h383719 =
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q54;
3'd1:
_theResult___fst_sfd__h383719 =
CASE_guard75096_0b0_theResult___snd83119_BITS__ETC__q55;
3'd2:
_theResult___fst_sfd__h383719 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5119;
3'd3:
_theResult___fst_sfd__h383719 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5121;
3'd4: _theResult___fst_sfd__h383719 = _theResult___snd__h383119[56:34];
default: _theResult___fst_sfd__h383719 = 23'd0;
endcase
end
always@(guard__h348621 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h348621)
2'b0, 2'b01, 2'b10:
CASE_guard48621_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard48621_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 =
guard__h348621 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard48621_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or
guard__h348621)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5207 =
CASE_guard48621_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5207 =
(guard__h348621 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h348621 == 2'b01 || guard__h348621 == 2'b10 ||
guard__h348621 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5207 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5207 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h348621 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h348621)
2'b0, 2'b01, 2'b10:
CASE_guard48621_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard48621_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 =
guard__h348621 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard48621_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or
guard__h348621)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5151 =
CASE_guard48621_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5151 =
(guard__h348621 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h348621 != 2'b01 && guard__h348621 != 2'b10 &&
guard__h348621 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5151 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5151 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h357330 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h357330)
2'b0, 2'b01, 2'b10:
CASE_guard57330_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard57330_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 =
guard__h357330 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard57330_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 or
guard__h357330)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5214 =
CASE_guard57330_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5214 =
(guard__h357330 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h357330 == 2'b01 || guard__h357330 == 2'b10 ||
guard__h357330 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5214 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5214 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h357330 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h357330)
2'b0, 2'b01, 2'b10:
CASE_guard57330_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard57330_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 =
guard__h357330 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard57330_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 or
guard__h357330)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5164 =
CASE_guard57330_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5164 =
(guard__h357330 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h357330 != 2'b01 && guard__h357330 != 2'b10 &&
guard__h357330 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5164 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5164 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h366260 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h366260)
2'b0, 2'b01, 2'b10:
CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 =
guard__h366260 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 or
guard__h366260)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5224 =
CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5224 =
(guard__h366260 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h366260 == 2'b01 || guard__h366260 == 2'b10 ||
guard__h366260 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5224 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5224 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h366260 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h366260)
2'b0, 2'b01, 2'b10:
CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 =
guard__h366260 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 or
guard__h366260)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5181 =
CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5181 =
(guard__h366260 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h366260 != 2'b01 && guard__h366260 != 2'b10 &&
guard__h366260 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5181 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5181 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h375096 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h375096)
2'b0, 2'b01, 2'b10:
CASE_guard75096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard75096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 =
guard__h375096 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard75096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 or
guard__h375096)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5231 =
CASE_guard75096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5231 =
(guard__h375096 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h375096 == 2'b01 || guard__h375096 == 2'b10 ||
guard__h375096 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5231 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5231 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h375096 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h375096)
2'b0, 2'b01, 2'b10:
CASE_guard75096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard75096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 =
guard__h375096 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard75096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 or
guard__h375096)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5194 =
CASE_guard75096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5194 =
(guard__h375096 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h375096 != 2'b01 && guard__h375096 != 2'b10 &&
guard__h375096 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5194 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5194 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5168 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5168 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h403027 or
_theResult___fst_exp__h411075 or
out_exp__h411520 or _theResult___exp__h411517)
begin
case (guard__h403027)
2'b0, 2'b01:
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q68 =
_theResult___fst_exp__h411075;
2'b10:
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q68 =
out_exp__h411520;
2'b11:
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q68 =
_theResult___exp__h411517;
endcase
end
always@(guard__h403027 or
_theResult___fst_exp__h411075 or _theResult___exp__h411517)
begin
case (guard__h403027)
2'b0:
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q69 =
_theResult___fst_exp__h411075;
2'b01, 2'b10, 2'b11:
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q69 =
_theResult___exp__h411517;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q68 or
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q69 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6021 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6023 or
_theResult___fst_exp__h411075)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h411595 =
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q68;
3'd1:
_theResult___fst_exp__h411595 =
CASE_guard03027_0b0_theResult___fst_exp11075_0_ETC__q69;
3'd2:
_theResult___fst_exp__h411595 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6021;
3'd3:
_theResult___fst_exp__h411595 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6023;
3'd4: _theResult___fst_exp__h411595 = _theResult___fst_exp__h411075;
default: _theResult___fst_exp__h411595 = 8'd0;
endcase
end
always@(guard__h394320 or
_theResult___fst_exp__h402419 or
out_exp__h402938 or _theResult___exp__h402935)
begin
case (guard__h394320)
2'b0, 2'b01:
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q70 =
_theResult___fst_exp__h402419;
2'b10:
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q70 =
out_exp__h402938;
2'b11:
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q70 =
_theResult___exp__h402935;
endcase
end
always@(guard__h394320 or
_theResult___fst_exp__h402419 or _theResult___exp__h402935)
begin
case (guard__h394320)
2'b0:
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q71 =
_theResult___fst_exp__h402419;
2'b01, 2'b10, 2'b11:
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q71 =
_theResult___exp__h402935;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q70 or
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q71 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5799 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802 or
_theResult___fst_exp__h402419)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h403013 =
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q70;
3'd1:
_theResult___fst_exp__h403013 =
CASE_guard94320_0b0_theResult___fst_exp02419_0_ETC__q71;
3'd2:
_theResult___fst_exp__h403013 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5799;
3'd3:
_theResult___fst_exp__h403013 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802;
3'd4: _theResult___fst_exp__h403013 = _theResult___fst_exp__h402419;
default: _theResult___fst_exp__h403013 = 8'd0;
endcase
end
always@(guard__h411957 or
_theResult___fst_exp__h420185 or
out_exp__h420704 or _theResult___exp__h420701)
begin
case (guard__h411957)
2'b0, 2'b01:
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q76 =
_theResult___fst_exp__h420185;
2'b10:
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q76 =
out_exp__h420704;
2'b11:
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q76 =
_theResult___exp__h420701;
endcase
end
always@(guard__h411957 or
_theResult___fst_exp__h420185 or _theResult___exp__h420701)
begin
case (guard__h411957)
2'b0:
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q77 =
_theResult___fst_exp__h420185;
2'b01, 2'b10, 2'b11:
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q77 =
_theResult___exp__h420701;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q76 or
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q77 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6346 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6348 or
_theResult___fst_exp__h420185)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h420779 =
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q76;
3'd1:
_theResult___fst_exp__h420779 =
CASE_guard11957_0b0_theResult___fst_exp20185_0_ETC__q77;
3'd2:
_theResult___fst_exp__h420779 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6346;
3'd3:
_theResult___fst_exp__h420779 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6348;
3'd4: _theResult___fst_exp__h420779 = _theResult___fst_exp__h420185;
default: _theResult___fst_exp__h420779 = 8'd0;
endcase
end
always@(guard__h420793 or
_theResult___fst_exp__h428870 or
out_exp__h429340 or _theResult___exp__h429337)
begin
case (guard__h420793)
2'b0, 2'b01:
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q81 =
_theResult___fst_exp__h428870;
2'b10:
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q81 =
out_exp__h429340;
2'b11:
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q81 =
_theResult___exp__h429337;
endcase
end
always@(guard__h420793 or
_theResult___fst_exp__h428870 or _theResult___exp__h429337)
begin
case (guard__h420793)
2'b0:
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q82 =
_theResult___fst_exp__h428870;
2'b01, 2'b10, 2'b11:
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q82 =
_theResult___exp__h429337;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q81 or
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q82 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6415 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6417 or
_theResult___fst_exp__h428870)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h429415 =
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q81;
3'd1:
_theResult___fst_exp__h429415 =
CASE_guard20793_0b0_theResult___fst_exp28870_0_ETC__q82;
3'd2:
_theResult___fst_exp__h429415 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6415;
3'd3:
_theResult___fst_exp__h429415 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6417;
3'd4: _theResult___fst_exp__h429415 = _theResult___fst_exp__h428870;
default: _theResult___fst_exp__h429415 = 8'd0;
endcase
end
always@(guard__h403027 or
_theResult___snd__h411026 or
out_sfd__h411521 or _theResult___sfd__h411518)
begin
case (guard__h403027)
2'b0, 2'b01:
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q83 =
_theResult___snd__h411026[56:34];
2'b10:
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q83 =
out_sfd__h411521;
2'b11:
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q83 =
_theResult___sfd__h411518;
endcase
end
always@(guard__h403027 or
_theResult___snd__h411026 or _theResult___sfd__h411518)
begin
case (guard__h403027)
2'b0:
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q84 =
_theResult___snd__h411026[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q84 =
_theResult___sfd__h411518;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q83 or
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q84 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6465 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6467 or
_theResult___snd__h411026)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h411596 =
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q83;
3'd1:
_theResult___fst_sfd__h411596 =
CASE_guard03027_0b0_theResult___snd11026_BITS__ETC__q84;
3'd2:
_theResult___fst_sfd__h411596 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6465;
3'd3:
_theResult___fst_sfd__h411596 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6467;
3'd4: _theResult___fst_sfd__h411596 = _theResult___snd__h411026[56:34];
default: _theResult___fst_sfd__h411596 = 23'd0;
endcase
end
always@(guard__h394320 or
sfdin__h402413 or out_sfd__h402939 or _theResult___sfd__h402936)
begin
case (guard__h394320)
2'b0, 2'b01:
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q85 =
sfdin__h402413[56:34];
2'b10:
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q85 =
out_sfd__h402939;
2'b11:
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q85 =
_theResult___sfd__h402936;
endcase
end
always@(guard__h394320 or sfdin__h402413 or _theResult___sfd__h402936)
begin
case (guard__h394320)
2'b0:
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q86 =
sfdin__h402413[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q86 =
_theResult___sfd__h402936;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q85 or
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q86 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6446 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6448 or
sfdin__h402413)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h403014 =
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q85;
3'd1:
_theResult___fst_sfd__h403014 =
CASE_guard94320_0b0_sfdin02413_BITS_56_TO_34_0_ETC__q86;
3'd2:
_theResult___fst_sfd__h403014 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6446;
3'd3:
_theResult___fst_sfd__h403014 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6448;
3'd4: _theResult___fst_sfd__h403014 = sfdin__h402413[56:34];
default: _theResult___fst_sfd__h403014 = 23'd0;
endcase
end
always@(guard__h411957 or
sfdin__h420179 or out_sfd__h420705 or _theResult___sfd__h420702)
begin
case (guard__h411957)
2'b0, 2'b01:
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q87 =
sfdin__h420179[56:34];
2'b10:
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q87 =
out_sfd__h420705;
2'b11:
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q87 =
_theResult___sfd__h420702;
endcase
end
always@(guard__h411957 or sfdin__h420179 or _theResult___sfd__h420702)
begin
case (guard__h411957)
2'b0:
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q88 =
sfdin__h420179[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q88 =
_theResult___sfd__h420702;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q87 or
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q88 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6492 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6494 or
sfdin__h420179)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h420780 =
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q87;
3'd1:
_theResult___fst_sfd__h420780 =
CASE_guard11957_0b0_sfdin20179_BITS_56_TO_34_0_ETC__q88;
3'd2:
_theResult___fst_sfd__h420780 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6492;
3'd3:
_theResult___fst_sfd__h420780 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6494;
3'd4: _theResult___fst_sfd__h420780 = sfdin__h420179[56:34];
default: _theResult___fst_sfd__h420780 = 23'd0;
endcase
end
always@(guard__h420793 or
_theResult___snd__h428816 or
out_sfd__h429341 or _theResult___sfd__h429338)
begin
case (guard__h420793)
2'b0, 2'b01:
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q89 =
_theResult___snd__h428816[56:34];
2'b10:
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q89 =
out_sfd__h429341;
2'b11:
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q89 =
_theResult___sfd__h429338;
endcase
end
always@(guard__h420793 or
_theResult___snd__h428816 or _theResult___sfd__h429338)
begin
case (guard__h420793)
2'b0:
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q90 =
_theResult___snd__h428816[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q90 =
_theResult___sfd__h429338;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q89 or
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q90 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6511 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6513 or
_theResult___snd__h428816)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h429416 =
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q89;
3'd1:
_theResult___fst_sfd__h429416 =
CASE_guard20793_0b0_theResult___snd28816_BITS__ETC__q90;
3'd2:
_theResult___fst_sfd__h429416 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6511;
3'd3:
_theResult___fst_sfd__h429416 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6513;
3'd4: _theResult___fst_sfd__h429416 = _theResult___snd__h428816[56:34];
default: _theResult___fst_sfd__h429416 = 23'd0;
endcase
end
always@(guard__h394320 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h394320)
2'b0, 2'b01, 2'b10:
CASE_guard94320_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard94320_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 =
guard__h394320 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard94320_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 or
guard__h394320)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6599 =
CASE_guard94320_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6599 =
(guard__h394320 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h394320 == 2'b01 || guard__h394320 == 2'b10 ||
guard__h394320 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6599 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6599 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h394320 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h394320)
2'b0, 2'b01, 2'b10:
CASE_guard94320_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard94320_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 =
guard__h394320 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard94320_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or
guard__h394320)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6543 =
CASE_guard94320_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6543 =
(guard__h394320 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h394320 != 2'b01 && guard__h394320 != 2'b10 &&
guard__h394320 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6543 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6543 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h403027 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h403027)
2'b0, 2'b01, 2'b10:
CASE_guard03027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard03027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 =
guard__h403027 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard03027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 or
guard__h403027)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6606 =
CASE_guard03027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6606 =
(guard__h403027 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h403027 == 2'b01 || guard__h403027 == 2'b10 ||
guard__h403027 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6606 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6606 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h403027 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h403027)
2'b0, 2'b01, 2'b10:
CASE_guard03027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard03027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 =
guard__h403027 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard03027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 or
guard__h403027)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6556 =
CASE_guard03027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6556 =
(guard__h403027 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h403027 != 2'b01 && guard__h403027 != 2'b10 &&
guard__h403027 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6556 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6556 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h411957 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h411957)
2'b0, 2'b01, 2'b10:
CASE_guard11957_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard11957_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 =
guard__h411957 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard11957_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 or
guard__h411957)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6616 =
CASE_guard11957_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6616 =
(guard__h411957 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h411957 == 2'b01 || guard__h411957 == 2'b10 ||
guard__h411957 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6616 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6616 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h411957 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h411957)
2'b0, 2'b01, 2'b10:
CASE_guard11957_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard11957_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 =
guard__h411957 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard11957_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or
guard__h411957)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6573 =
CASE_guard11957_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6573 =
(guard__h411957 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h411957 != 2'b01 && guard__h411957 != 2'b10 &&
guard__h411957 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6573 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6573 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h420793 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h420793)
2'b0, 2'b01, 2'b10:
CASE_guard20793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard20793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 =
guard__h420793 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard20793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or
guard__h420793)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6623 =
CASE_guard20793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6623 =
(guard__h420793 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h420793 == 2'b01 || guard__h420793 == 2'b10 ||
guard__h420793 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6623 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6623 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h420793 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h420793)
2'b0, 2'b01, 2'b10:
CASE_guard20793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard20793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 =
guard__h420793 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard20793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 or
guard__h420793)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6586 =
CASE_guard20793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6586 =
(guard__h420793 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h420793 != 2'b01 && guard__h420793 != 2'b10 &&
guard__h420793 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6586 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6586 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6560 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6560 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h448722 or
_theResult___fst_exp__h456770 or
out_exp__h457215 or _theResult___exp__h457212)
begin
case (guard__h448722)
2'b0, 2'b01:
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q103 =
_theResult___fst_exp__h456770;
2'b10:
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q103 =
out_exp__h457215;
2'b11:
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q103 =
_theResult___exp__h457212;
endcase
end
always@(guard__h448722 or
_theResult___fst_exp__h456770 or _theResult___exp__h457212)
begin
case (guard__h448722)
2'b0:
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q104 =
_theResult___fst_exp__h456770;
2'b01, 2'b10, 2'b11:
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q104 =
_theResult___exp__h457212;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q103 or
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q104 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7413 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7415 or
_theResult___fst_exp__h456770)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h457290 =
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q103;
3'd1:
_theResult___fst_exp__h457290 =
CASE_guard48722_0b0_theResult___fst_exp56770_0_ETC__q104;
3'd2:
_theResult___fst_exp__h457290 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7413;
3'd3:
_theResult___fst_exp__h457290 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7415;
3'd4: _theResult___fst_exp__h457290 = _theResult___fst_exp__h456770;
default: _theResult___fst_exp__h457290 = 8'd0;
endcase
end
always@(guard__h440015 or
_theResult___fst_exp__h448114 or
out_exp__h448633 or _theResult___exp__h448630)
begin
case (guard__h440015)
2'b0, 2'b01:
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q105 =
_theResult___fst_exp__h448114;
2'b10:
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q105 =
out_exp__h448633;
2'b11:
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q105 =
_theResult___exp__h448630;
endcase
end
always@(guard__h440015 or
_theResult___fst_exp__h448114 or _theResult___exp__h448630)
begin
case (guard__h440015)
2'b0:
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q106 =
_theResult___fst_exp__h448114;
2'b01, 2'b10, 2'b11:
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q106 =
_theResult___exp__h448630;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q105 or
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q106 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7191 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194 or
_theResult___fst_exp__h448114)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h448708 =
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q105;
3'd1:
_theResult___fst_exp__h448708 =
CASE_guard40015_0b0_theResult___fst_exp48114_0_ETC__q106;
3'd2:
_theResult___fst_exp__h448708 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7191;
3'd3:
_theResult___fst_exp__h448708 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194;
3'd4: _theResult___fst_exp__h448708 = _theResult___fst_exp__h448114;
default: _theResult___fst_exp__h448708 = 8'd0;
endcase
end
always@(guard__h457652 or
_theResult___fst_exp__h465880 or
out_exp__h466399 or _theResult___exp__h466396)
begin
case (guard__h457652)
2'b0, 2'b01:
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q111 =
_theResult___fst_exp__h465880;
2'b10:
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q111 =
out_exp__h466399;
2'b11:
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q111 =
_theResult___exp__h466396;
endcase
end
always@(guard__h457652 or
_theResult___fst_exp__h465880 or _theResult___exp__h466396)
begin
case (guard__h457652)
2'b0:
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q112 =
_theResult___fst_exp__h465880;
2'b01, 2'b10, 2'b11:
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q112 =
_theResult___exp__h466396;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q111 or
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q112 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7738 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7740 or
_theResult___fst_exp__h465880)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h466474 =
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q111;
3'd1:
_theResult___fst_exp__h466474 =
CASE_guard57652_0b0_theResult___fst_exp65880_0_ETC__q112;
3'd2:
_theResult___fst_exp__h466474 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7738;
3'd3:
_theResult___fst_exp__h466474 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7740;
3'd4: _theResult___fst_exp__h466474 = _theResult___fst_exp__h465880;
default: _theResult___fst_exp__h466474 = 8'd0;
endcase
end
always@(guard__h466488 or
_theResult___fst_exp__h474565 or
out_exp__h475035 or _theResult___exp__h475032)
begin
case (guard__h466488)
2'b0, 2'b01:
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q116 =
_theResult___fst_exp__h474565;
2'b10:
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q116 =
out_exp__h475035;
2'b11:
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q116 =
_theResult___exp__h475032;
endcase
end
always@(guard__h466488 or
_theResult___fst_exp__h474565 or _theResult___exp__h475032)
begin
case (guard__h466488)
2'b0:
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q117 =
_theResult___fst_exp__h474565;
2'b01, 2'b10, 2'b11:
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q117 =
_theResult___exp__h475032;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q116 or
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q117 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7807 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7809 or
_theResult___fst_exp__h474565)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h475110 =
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q116;
3'd1:
_theResult___fst_exp__h475110 =
CASE_guard66488_0b0_theResult___fst_exp74565_0_ETC__q117;
3'd2:
_theResult___fst_exp__h475110 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7807;
3'd3:
_theResult___fst_exp__h475110 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7809;
3'd4: _theResult___fst_exp__h475110 = _theResult___fst_exp__h474565;
default: _theResult___fst_exp__h475110 = 8'd0;
endcase
end
always@(guard__h448722 or
_theResult___snd__h456721 or
out_sfd__h457216 or _theResult___sfd__h457213)
begin
case (guard__h448722)
2'b0, 2'b01:
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q118 =
_theResult___snd__h456721[56:34];
2'b10:
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q118 =
out_sfd__h457216;
2'b11:
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q118 =
_theResult___sfd__h457213;
endcase
end
always@(guard__h448722 or
_theResult___snd__h456721 or _theResult___sfd__h457213)
begin
case (guard__h448722)
2'b0:
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q119 =
_theResult___snd__h456721[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q119 =
_theResult___sfd__h457213;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q118 or
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q119 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7857 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7859 or
_theResult___snd__h456721)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h457291 =
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q118;
3'd1:
_theResult___fst_sfd__h457291 =
CASE_guard48722_0b0_theResult___snd56721_BITS__ETC__q119;
3'd2:
_theResult___fst_sfd__h457291 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7857;
3'd3:
_theResult___fst_sfd__h457291 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7859;
3'd4: _theResult___fst_sfd__h457291 = _theResult___snd__h456721[56:34];
default: _theResult___fst_sfd__h457291 = 23'd0;
endcase
end
always@(guard__h440015 or
sfdin__h448108 or out_sfd__h448634 or _theResult___sfd__h448631)
begin
case (guard__h440015)
2'b0, 2'b01:
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q120 =
sfdin__h448108[56:34];
2'b10:
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q120 =
out_sfd__h448634;
2'b11:
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q120 =
_theResult___sfd__h448631;
endcase
end
always@(guard__h440015 or sfdin__h448108 or _theResult___sfd__h448631)
begin
case (guard__h440015)
2'b0:
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q121 =
sfdin__h448108[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q121 =
_theResult___sfd__h448631;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q120 or
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q121 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7838 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7840 or
sfdin__h448108)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h448709 =
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q120;
3'd1:
_theResult___fst_sfd__h448709 =
CASE_guard40015_0b0_sfdin48108_BITS_56_TO_34_0_ETC__q121;
3'd2:
_theResult___fst_sfd__h448709 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7838;
3'd3:
_theResult___fst_sfd__h448709 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7840;
3'd4: _theResult___fst_sfd__h448709 = sfdin__h448108[56:34];
default: _theResult___fst_sfd__h448709 = 23'd0;
endcase
end
always@(guard__h457652 or
sfdin__h465874 or out_sfd__h466400 or _theResult___sfd__h466397)
begin
case (guard__h457652)
2'b0, 2'b01:
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q122 =
sfdin__h465874[56:34];
2'b10:
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q122 =
out_sfd__h466400;
2'b11:
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q122 =
_theResult___sfd__h466397;
endcase
end
always@(guard__h457652 or sfdin__h465874 or _theResult___sfd__h466397)
begin
case (guard__h457652)
2'b0:
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q123 =
sfdin__h465874[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q123 =
_theResult___sfd__h466397;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q122 or
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q123 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7884 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7886 or
sfdin__h465874)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h466475 =
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q122;
3'd1:
_theResult___fst_sfd__h466475 =
CASE_guard57652_0b0_sfdin65874_BITS_56_TO_34_0_ETC__q123;
3'd2:
_theResult___fst_sfd__h466475 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7884;
3'd3:
_theResult___fst_sfd__h466475 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7886;
3'd4: _theResult___fst_sfd__h466475 = sfdin__h465874[56:34];
default: _theResult___fst_sfd__h466475 = 23'd0;
endcase
end
always@(guard__h466488 or
_theResult___snd__h474511 or
out_sfd__h475036 or _theResult___sfd__h475033)
begin
case (guard__h466488)
2'b0, 2'b01:
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q124 =
_theResult___snd__h474511[56:34];
2'b10:
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q124 =
out_sfd__h475036;
2'b11:
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q124 =
_theResult___sfd__h475033;
endcase
end
always@(guard__h466488 or
_theResult___snd__h474511 or _theResult___sfd__h475033)
begin
case (guard__h466488)
2'b0:
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q125 =
_theResult___snd__h474511[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q125 =
_theResult___sfd__h475033;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q124 or
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q125 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7903 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7905 or
_theResult___snd__h474511)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h475111 =
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q124;
3'd1:
_theResult___fst_sfd__h475111 =
CASE_guard66488_0b0_theResult___snd74511_BITS__ETC__q125;
3'd2:
_theResult___fst_sfd__h475111 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7903;
3'd3:
_theResult___fst_sfd__h475111 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7905;
3'd4: _theResult___fst_sfd__h475111 = _theResult___snd__h474511[56:34];
default: _theResult___fst_sfd__h475111 = 23'd0;
endcase
end
always@(guard__h440015 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h440015)
2'b0, 2'b01, 2'b10:
CASE_guard40015_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard40015_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 =
guard__h440015 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard40015_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or
guard__h440015)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7991 =
CASE_guard40015_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7991 =
(guard__h440015 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h440015 == 2'b01 || guard__h440015 == 2'b10 ||
guard__h440015 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7991 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7991 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h440015 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h440015)
2'b0, 2'b01, 2'b10:
CASE_guard40015_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard40015_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 =
guard__h440015 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard40015_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or
guard__h440015)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7935 =
CASE_guard40015_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7935 =
(guard__h440015 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h440015 != 2'b01 && guard__h440015 != 2'b10 &&
guard__h440015 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7935 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7935 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h448722 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h448722)
2'b0, 2'b01, 2'b10:
CASE_guard48722_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard48722_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 =
guard__h448722 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard48722_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 or
guard__h448722)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7998 =
CASE_guard48722_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7998 =
(guard__h448722 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h448722 == 2'b01 || guard__h448722 == 2'b10 ||
guard__h448722 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7998 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7998 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h448722 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h448722)
2'b0, 2'b01, 2'b10:
CASE_guard48722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard48722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 =
guard__h448722 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard48722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 or
guard__h448722)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7948 =
CASE_guard48722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7948 =
(guard__h448722 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h448722 != 2'b01 && guard__h448722 != 2'b10 &&
guard__h448722 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7948 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7948 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h457652 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h457652)
2'b0, 2'b01, 2'b10:
CASE_guard57652_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard57652_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 =
guard__h457652 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard57652_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or
guard__h457652)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8008 =
CASE_guard57652_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8008 =
(guard__h457652 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h457652 == 2'b01 || guard__h457652 == 2'b10 ||
guard__h457652 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8008 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8008 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h457652 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h457652)
2'b0, 2'b01, 2'b10:
CASE_guard57652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard57652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 =
guard__h457652 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard57652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or
guard__h457652)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7965 =
CASE_guard57652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7965 =
(guard__h457652 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h457652 != 2'b01 && guard__h457652 != 2'b10 &&
guard__h457652 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7965 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7965 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h466488 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h466488)
2'b0, 2'b01, 2'b10:
CASE_guard66488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard66488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 =
guard__h466488 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard66488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 or
guard__h466488)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8015 =
CASE_guard66488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8015 =
(guard__h466488 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h466488 == 2'b01 || guard__h466488 == 2'b10 ||
guard__h466488 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8015 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8015 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h466488 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h466488)
2'b0, 2'b01, 2'b10:
CASE_guard66488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard66488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 =
guard__h466488 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard66488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 or
guard__h466488)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7978 =
CASE_guard66488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7978 =
(guard__h466488 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h466488 != 2'b01 && guard__h466488 != 2'b10 &&
guard__h466488 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7978 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7978 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7952 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7952 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put or
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8508 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8508 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8508 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8508 =
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
endcase
end
always@(guard__h496602 or
_theResult___fst_exp__h504563 or _theResult___exp__h505218)
begin
case (guard__h496602)
2'b0:
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q143 =
_theResult___fst_exp__h504563;
2'b01, 2'b10, 2'b11:
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q143 =
_theResult___exp__h505218;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h504563 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9127 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9125 or
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q143)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9131 =
_theResult___fst_exp__h504563;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9131 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9127;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9131 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9125;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9131 =
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q143;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9131 =
11'd0;
endcase
end
always@(guard__h496602 or
_theResult___fst_exp__h504563 or
out_exp__h505221 or _theResult___exp__h505218)
begin
case (guard__h496602)
2'b0, 2'b01:
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q144 =
_theResult___fst_exp__h504563;
2'b10:
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q144 =
out_exp__h505221;
2'b11:
CASE_guard96602_0b0_theResult___fst_exp04563_0_ETC__q144 =
_theResult___exp__h505218;
endcase
end
always@(guard__h496602 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h496602)
2'b0, 2'b01, 2'b10:
CASE_guard96602_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard96602_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 =
guard__h496602 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h496602)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
(guard__h496602 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h496602 == 2'b01 || guard__h496602 == 2'b10 ||
guard__h496602 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h505914 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h505914)
2'b0, 2'b01, 2'b10:
CASE_guard05914_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard05914_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 =
guard__h505914 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h505914)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
(guard__h505914 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h505914 == 2'b01 || guard__h505914 == 2'b10 ||
guard__h505914 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h514983 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h514983)
2'b0, 2'b01, 2'b10:
CASE_guard14983_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard14983_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 =
guard__h514983 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h514983)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
(guard__h514983 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h514983 == 2'b01 || guard__h514983 == 2'b10 ||
guard__h514983 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h574759 or
_theResult___fst_exp__h582720 or _theResult___exp__h583375)
begin
case (guard__h574759)
2'b0:
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q160 =
_theResult___fst_exp__h582720;
2'b01, 2'b10, 2'b11:
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q160 =
_theResult___exp__h583375;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h582720 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9842 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9840 or
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q160)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9846 =
_theResult___fst_exp__h582720;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9846 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9842;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9846 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9840;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9846 =
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q160;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9846 =
11'd0;
endcase
end
always@(guard__h574759 or
_theResult___fst_exp__h582720 or
out_exp__h583378 or _theResult___exp__h583375)
begin
case (guard__h574759)
2'b0, 2'b01:
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q161 =
_theResult___fst_exp__h582720;
2'b10:
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q161 =
out_exp__h583378;
2'b11:
CASE_guard74759_0b0_theResult___fst_exp82720_0_ETC__q161 =
_theResult___exp__h583375;
endcase
end
always@(guard__h574759 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h574759)
2'b0, 2'b01, 2'b10:
CASE_guard74759_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard74759_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 =
guard__h574759 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h574759)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
(guard__h574759 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h574759 == 2'b01 || guard__h574759 == 2'b10 ||
guard__h574759 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h584071 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h584071)
2'b0, 2'b01, 2'b10:
CASE_guard84071_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard84071_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 =
guard__h584071 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h584071)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
(guard__h584071 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h584071 == 2'b01 || guard__h584071 == 2'b10 ||
guard__h584071 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h593140 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h593140)
2'b0, 2'b01, 2'b10:
CASE_guard93140_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard93140_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 =
guard__h593140 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h593140)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
(guard__h593140 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h593140 == 2'b01 || guard__h593140 == 2'b10 ||
guard__h593140 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h584071 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h584071)
2'b0, 2'b01, 2'b10:
CASE_guard84071_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard84071_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 =
guard__h584071 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h584071)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
(guard__h584071 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h584071 != 2'b01 && guard__h584071 != 2'b10 &&
guard__h584071 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h593140 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h593140)
2'b0, 2'b01, 2'b10:
CASE_guard93140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard93140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 =
guard__h593140 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h593140)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
(guard__h593140 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h593140 != 2'b01 && guard__h593140 != 2'b10 &&
guard__h593140 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h574759 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h574759)
2'b0, 2'b01, 2'b10:
CASE_guard74759_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard74759_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 =
guard__h574759 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h574759)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
(guard__h574759 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h574759 != 2'b01 && guard__h574759 != 2'b10 &&
guard__h574759 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h535455 or
_theResult___fst_exp__h543416 or _theResult___exp__h544071)
begin
case (guard__h535455)
2'b0:
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q183 =
_theResult___fst_exp__h543416;
2'b01, 2'b10, 2'b11:
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q183 =
_theResult___exp__h544071;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h543416 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10612 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10610 or
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q183)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10616 =
_theResult___fst_exp__h543416;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10616 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10612;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10616 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10610;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10616 =
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q183;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10616 =
11'd0;
endcase
end
always@(guard__h535455 or
_theResult___fst_exp__h543416 or
out_exp__h544074 or _theResult___exp__h544071)
begin
case (guard__h535455)
2'b0, 2'b01:
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q184 =
_theResult___fst_exp__h543416;
2'b10:
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q184 =
out_exp__h544074;
2'b11:
CASE_guard35455_0b0_theResult___fst_exp43416_0_ETC__q184 =
_theResult___exp__h544071;
endcase
end
always@(guard__h544767 or
_theResult___fst_exp__h552993 or _theResult___exp__h553722)
begin
case (guard__h544767)
2'b0:
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q185 =
_theResult___fst_exp__h552993;
2'b01, 2'b10, 2'b11:
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q185 =
_theResult___exp__h553722;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h552993 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10650 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10648 or
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q185)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10654 =
_theResult___fst_exp__h552993;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10654 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10650;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10654 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10648;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10654 =
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q185;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10654 =
11'd0;
endcase
end
always@(guard__h544767 or
_theResult___fst_exp__h552993 or
out_exp__h553725 or _theResult___exp__h553722)
begin
case (guard__h544767)
2'b0, 2'b01:
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q186 =
_theResult___fst_exp__h552993;
2'b10:
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q186 =
out_exp__h553725;
2'b11:
CASE_guard44767_0b0_theResult___fst_exp52993_0_ETC__q186 =
_theResult___exp__h553722;
endcase
end
always@(guard__h553836 or
_theResult___fst_exp__h561826 or _theResult___exp__h562506)
begin
case (guard__h553836)
2'b0:
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q187 =
_theResult___fst_exp__h561826;
2'b01, 2'b10, 2'b11:
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q187 =
_theResult___exp__h562506;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h561826 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10681 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10679 or
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q187)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10685 =
_theResult___fst_exp__h561826;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10685 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10681;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10685 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10679;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10685 =
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q187;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10685 =
11'd0;
endcase
end
always@(guard__h553836 or
_theResult___fst_exp__h561826 or
out_exp__h562509 or _theResult___exp__h562506)
begin
case (guard__h553836)
2'b0, 2'b01:
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q188 =
_theResult___fst_exp__h561826;
2'b10:
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q188 =
out_exp__h562509;
2'b11:
CASE_guard53836_0b0_theResult___fst_exp61826_0_ETC__q188 =
_theResult___exp__h562506;
endcase
end
always@(guard__h584071 or
_theResult___fst_exp__h592297 or _theResult___exp__h593026)
begin
case (guard__h584071)
2'b0:
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q189 =
_theResult___fst_exp__h592297;
2'b01, 2'b10, 2'b11:
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q189 =
_theResult___exp__h593026;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h592297 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9880 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9878 or
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q189)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9884 =
_theResult___fst_exp__h592297;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9884 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9880;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9884 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9878;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9884 =
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q189;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9884 =
11'd0;
endcase
end
always@(guard__h584071 or
_theResult___fst_exp__h592297 or
out_exp__h593029 or _theResult___exp__h593026)
begin
case (guard__h584071)
2'b0, 2'b01:
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q190 =
_theResult___fst_exp__h592297;
2'b10:
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q190 =
out_exp__h593029;
2'b11:
CASE_guard84071_0b0_theResult___fst_exp92297_0_ETC__q190 =
_theResult___exp__h593026;
endcase
end
always@(guard__h593140 or
_theResult___fst_exp__h601130 or _theResult___exp__h601810)
begin
case (guard__h593140)
2'b0:
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q191 =
_theResult___fst_exp__h601130;
2'b01, 2'b10, 2'b11:
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q191 =
_theResult___exp__h601810;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h601130 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9911 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9909 or
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q191)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9915 =
_theResult___fst_exp__h601130;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9915 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9911;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9915 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9909;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9915 =
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q191;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9915 =
11'd0;
endcase
end
always@(guard__h593140 or
_theResult___fst_exp__h601130 or
out_exp__h601813 or _theResult___exp__h601810)
begin
case (guard__h593140)
2'b0, 2'b01:
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q192 =
_theResult___fst_exp__h601130;
2'b10:
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q192 =
out_exp__h601813;
2'b11:
CASE_guard93140_0b0_theResult___fst_exp01130_0_ETC__q192 =
_theResult___exp__h601810;
endcase
end
always@(guard__h535455 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h535455)
2'b0, 2'b01, 2'b10:
CASE_guard35455_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard35455_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 =
guard__h535455 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h535455)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
(guard__h535455 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h535455 == 2'b01 || guard__h535455 == 2'b10 ||
guard__h535455 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h544767 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h544767)
2'b0, 2'b01, 2'b10:
CASE_guard44767_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard44767_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 =
guard__h544767 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h544767)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
(guard__h544767 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h544767 == 2'b01 || guard__h544767 == 2'b10 ||
guard__h544767 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h553836 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h553836)
2'b0, 2'b01, 2'b10:
CASE_guard53836_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard53836_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 =
guard__h553836 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h553836)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
(guard__h553836 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h553836 == 2'b01 || guard__h553836 == 2'b10 ||
guard__h553836 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h544767 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h544767)
2'b0, 2'b01, 2'b10:
CASE_guard44767_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard44767_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 =
guard__h544767 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h544767)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
(guard__h544767 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h544767 != 2'b01 && guard__h544767 != 2'b10 &&
guard__h544767 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h553836 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h553836)
2'b0, 2'b01, 2'b10:
CASE_guard53836_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard53836_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 =
guard__h553836 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h553836)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
(guard__h553836 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h553836 != 2'b01 && guard__h553836 != 2'b10 &&
guard__h553836 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h535455 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h535455)
2'b0, 2'b01, 2'b10:
CASE_guard35455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard35455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 =
guard__h535455 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h535455)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
(guard__h535455 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h535455 != 2'b01 && guard__h535455 != 2'b10 &&
guard__h535455 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h535455 or
_theResult___snd__h543367 or _theResult___sfd__h544072)
begin
case (guard__h535455)
2'b0:
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q205 =
_theResult___snd__h543367[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q205 =
_theResult___sfd__h544072;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h543367 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10707 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10705 or
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q205)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10711 =
_theResult___snd__h543367[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10711 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10707;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10711 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10705;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10711 =
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q205;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10711 =
52'd0;
endcase
end
always@(guard__h535455 or
_theResult___snd__h543367 or
out_sfd__h544075 or _theResult___sfd__h544072)
begin
case (guard__h535455)
2'b0, 2'b01:
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q206 =
_theResult___snd__h543367[56:5];
2'b10:
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q206 =
out_sfd__h544075;
2'b11:
CASE_guard35455_0b0_theResult___snd43367_BITS__ETC__q206 =
_theResult___sfd__h544072;
endcase
end
always@(guard__h544767 or sfdin__h552987 or _theResult___sfd__h553723)
begin
case (guard__h544767)
2'b0:
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q207 =
sfdin__h552987[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q207 =
_theResult___sfd__h553723;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h552987 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10733 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10731 or
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q207)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10737 =
sfdin__h552987[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10737 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10733;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10737 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10731;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10737 =
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q207;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10737 =
52'd0;
endcase
end
always@(guard__h544767 or
sfdin__h552987 or out_sfd__h553726 or _theResult___sfd__h553723)
begin
case (guard__h544767)
2'b0, 2'b01:
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q208 =
sfdin__h552987[56:5];
2'b10:
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q208 =
out_sfd__h553726;
2'b11:
CASE_guard44767_0b0_sfdin52987_BITS_56_TO_5_0b_ETC__q208 =
_theResult___sfd__h553723;
endcase
end
always@(guard__h553836 or
_theResult___snd__h561772 or _theResult___sfd__h562507)
begin
case (guard__h553836)
2'b0:
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q209 =
_theResult___snd__h561772[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q209 =
_theResult___sfd__h562507;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h561772 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10752 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10750 or
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q209)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10756 =
_theResult___snd__h561772[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10756 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10752;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10756 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10750;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10756 =
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q209;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10756 =
52'd0;
endcase
end
always@(guard__h553836 or
_theResult___snd__h561772 or
out_sfd__h562510 or _theResult___sfd__h562507)
begin
case (guard__h553836)
2'b0, 2'b01:
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q210 =
_theResult___snd__h561772[56:5];
2'b10:
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q210 =
out_sfd__h562510;
2'b11:
CASE_guard53836_0b0_theResult___snd61772_BITS__ETC__q210 =
_theResult___sfd__h562507;
endcase
end
always@(guard__h505914 or
_theResult___fst_exp__h514140 or _theResult___exp__h514869)
begin
case (guard__h505914)
2'b0:
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q211 =
_theResult___fst_exp__h514140;
2'b01, 2'b10, 2'b11:
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q211 =
_theResult___exp__h514869;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h514140 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9170 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9168 or
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q211)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9174 =
_theResult___fst_exp__h514140;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9174 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9170;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9174 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9168;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9174 =
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q211;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9174 =
11'd0;
endcase
end
always@(guard__h505914 or
_theResult___fst_exp__h514140 or
out_exp__h514872 or _theResult___exp__h514869)
begin
case (guard__h505914)
2'b0, 2'b01:
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q212 =
_theResult___fst_exp__h514140;
2'b10:
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q212 =
out_exp__h514872;
2'b11:
CASE_guard05914_0b0_theResult___fst_exp14140_0_ETC__q212 =
_theResult___exp__h514869;
endcase
end
always@(guard__h514983 or
_theResult___fst_exp__h522973 or _theResult___exp__h523653)
begin
case (guard__h514983)
2'b0:
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q213 =
_theResult___fst_exp__h522973;
2'b01, 2'b10, 2'b11:
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q213 =
_theResult___exp__h523653;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h522973 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9201 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9199 or
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q213)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9205 =
_theResult___fst_exp__h522973;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9205 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9201;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9205 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9199;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9205 =
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q213;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9205 =
11'd0;
endcase
end
always@(guard__h514983 or
_theResult___fst_exp__h522973 or
out_exp__h523656 or _theResult___exp__h523653)
begin
case (guard__h514983)
2'b0, 2'b01:
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q214 =
_theResult___fst_exp__h522973;
2'b10:
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q214 =
out_exp__h523656;
2'b11:
CASE_guard14983_0b0_theResult___fst_exp22973_0_ETC__q214 =
_theResult___exp__h523653;
endcase
end
always@(guard__h496602 or
_theResult___snd__h504514 or _theResult___sfd__h505219)
begin
case (guard__h496602)
2'b0:
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q215 =
_theResult___snd__h504514[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q215 =
_theResult___sfd__h505219;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h504514 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9227 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9225 or
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q215)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9231 =
_theResult___snd__h504514[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9231 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9227;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9231 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9225;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9231 =
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q215;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9231 =
52'd0;
endcase
end
always@(guard__h496602 or
_theResult___snd__h504514 or
out_sfd__h505222 or _theResult___sfd__h505219)
begin
case (guard__h496602)
2'b0, 2'b01:
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q216 =
_theResult___snd__h504514[56:5];
2'b10:
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q216 =
out_sfd__h505222;
2'b11:
CASE_guard96602_0b0_theResult___snd04514_BITS__ETC__q216 =
_theResult___sfd__h505219;
endcase
end
always@(guard__h505914 or sfdin__h514134 or _theResult___sfd__h514870)
begin
case (guard__h505914)
2'b0:
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q217 =
sfdin__h514134[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q217 =
_theResult___sfd__h514870;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h514134 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9254 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9252 or
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q217)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9258 =
sfdin__h514134[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9258 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9254;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9258 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9252;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9258 =
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q217;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9258 =
52'd0;
endcase
end
always@(guard__h505914 or
sfdin__h514134 or out_sfd__h514873 or _theResult___sfd__h514870)
begin
case (guard__h505914)
2'b0, 2'b01:
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q218 =
sfdin__h514134[56:5];
2'b10:
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q218 =
out_sfd__h514873;
2'b11:
CASE_guard05914_0b0_sfdin14134_BITS_56_TO_5_0b_ETC__q218 =
_theResult___sfd__h514870;
endcase
end
always@(guard__h514983 or
_theResult___snd__h522919 or _theResult___sfd__h523654)
begin
case (guard__h514983)
2'b0:
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q219 =
_theResult___snd__h522919[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q219 =
_theResult___sfd__h523654;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h522919 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9273 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9271 or
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q219)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9277 =
_theResult___snd__h522919[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9277 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9273;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9277 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9271;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9277 =
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q219;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9277 =
52'd0;
endcase
end
always@(guard__h514983 or
_theResult___snd__h522919 or
out_sfd__h523657 or _theResult___sfd__h523654)
begin
case (guard__h514983)
2'b0, 2'b01:
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q220 =
_theResult___snd__h522919[56:5];
2'b10:
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q220 =
out_sfd__h523657;
2'b11:
CASE_guard14983_0b0_theResult___snd22919_BITS__ETC__q220 =
_theResult___sfd__h523654;
endcase
end
always@(guard__h574759 or
_theResult___snd__h582671 or _theResult___sfd__h583376)
begin
case (guard__h574759)
2'b0:
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q221 =
_theResult___snd__h582671[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q221 =
_theResult___sfd__h583376;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h582671 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9937 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9935 or
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q221)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9941 =
_theResult___snd__h582671[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9941 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9937;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9941 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9935;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9941 =
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q221;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9941 =
52'd0;
endcase
end
always@(guard__h574759 or
_theResult___snd__h582671 or
out_sfd__h583379 or _theResult___sfd__h583376)
begin
case (guard__h574759)
2'b0, 2'b01:
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q222 =
_theResult___snd__h582671[56:5];
2'b10:
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q222 =
out_sfd__h583379;
2'b11:
CASE_guard74759_0b0_theResult___snd82671_BITS__ETC__q222 =
_theResult___sfd__h583376;
endcase
end
always@(guard__h584071 or sfdin__h592291 or _theResult___sfd__h593027)
begin
case (guard__h584071)
2'b0:
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q223 =
sfdin__h592291[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q223 =
_theResult___sfd__h593027;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h592291 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9963 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9961 or
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q223)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9967 =
sfdin__h592291[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9967 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9963;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9967 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9961;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9967 =
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q223;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9967 =
52'd0;
endcase
end
always@(guard__h584071 or
sfdin__h592291 or out_sfd__h593030 or _theResult___sfd__h593027)
begin
case (guard__h584071)
2'b0, 2'b01:
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q224 =
sfdin__h592291[56:5];
2'b10:
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q224 =
out_sfd__h593030;
2'b11:
CASE_guard84071_0b0_sfdin92291_BITS_56_TO_5_0b_ETC__q224 =
_theResult___sfd__h593027;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11000 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10988 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10977)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11002 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10988;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11002 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10977;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11002 =
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11000;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d10964 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10919 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10877)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10966 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10919;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10966 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10877;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10966 =
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d10964;
endcase
end
always@(guard__h593140 or
_theResult___snd__h601076 or _theResult___sfd__h601811)
begin
case (guard__h593140)
2'b0:
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q225 =
_theResult___snd__h601076[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q225 =
_theResult___sfd__h601811;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h601076 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9982 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9980 or
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q225)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9986 =
_theResult___snd__h601076[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9986 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9982;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9986 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9980;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9986 =
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q225;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9986 =
52'd0;
endcase
end
always@(guard__h593140 or
_theResult___snd__h601076 or
out_sfd__h601814 or _theResult___sfd__h601811)
begin
case (guard__h593140)
2'b0, 2'b01:
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q226 =
_theResult___snd__h601076[56:5];
2'b10:
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q226 =
out_sfd__h601814;
2'b11:
CASE_guard93140_0b0_theResult___snd01076_BITS__ETC__q226 =
_theResult___sfd__h601811;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11048 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11032 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11017)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11050 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11032;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11050 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11017;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11050 =
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11048;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11090 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11076 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11063)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11092 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11076;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11092 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11063;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11092 =
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11090;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11132 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11118 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11105)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11134 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11118;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11134 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11105;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d11134 =
coreFix_fpuMulDivExe_0_regToExeQ_first__483_BI_ETC___d11132;
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first)
begin
case (coreFix_aluExe_1_regToExeQ$first[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 =
coreFix_aluExe_1_regToExeQ$first[399:397];
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first or
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227)
begin
case (coreFix_aluExe_1_regToExeQ$first[416:414])
3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
coreFix_aluExe_1_regToExeQ$first[416:396];
3'd4:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
{ coreFix_aluExe_1_regToExeQ$first[416:414],
9'h0AA,
coreFix_aluExe_1_regToExeQ$first[404:400],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227,
coreFix_aluExe_1_regToExeQ$first[396] };
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
{ 3'd5, 18'h2AAAA };
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first)
begin
case (coreFix_aluExe_1_regToExeQ$first[394:383])
12'd1971,
12'd1970,
12'd1969,
12'd1968,
12'd3860,
12'd3859,
12'd3858,
12'd3857,
12'd2818,
12'd2816,
12'd836,
12'd835,
12'd834,
12'd833,
12'd832,
12'd774,
12'd773,
12'd772,
12'd771,
12'd770,
12'd769,
12'd768,
12'd384,
12'd324,
12'd323,
12'd322,
12'd321,
12'd320,
12'd262,
12'd261,
12'd260,
12'd256,
12'd2049,
12'd2048,
12'd3074,
12'd3073,
12'd3072,
12'd3,
12'd2,
12'd1:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 =
coreFix_aluExe_1_regToExeQ$first[394:383];
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 =
12'd2303;
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first)
begin
case (coreFix_aluExe_0_regToExeQ$first[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 =
coreFix_aluExe_0_regToExeQ$first[399:397];
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first or
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230)
begin
case (coreFix_aluExe_0_regToExeQ$first[416:414])
3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
coreFix_aluExe_0_regToExeQ$first[416:396];
3'd4:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
{ coreFix_aluExe_0_regToExeQ$first[416:414],
9'h0AA,
coreFix_aluExe_0_regToExeQ$first[404:400],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230,
coreFix_aluExe_0_regToExeQ$first[396] };
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
{ 3'd5, 18'h2AAAA };
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first)
begin
case (coreFix_aluExe_0_regToExeQ$first[394:383])
12'd1971,
12'd1970,
12'd1969,
12'd1968,
12'd3860,
12'd3859,
12'd3858,
12'd3857,
12'd2818,
12'd2816,
12'd836,
12'd835,
12'd834,
12'd833,
12'd832,
12'd774,
12'd773,
12'd772,
12'd771,
12'd770,
12'd769,
12'd768,
12'd384,
12'd324,
12'd323,
12'd322,
12'd321,
12'd320,
12'd262,
12'd261,
12'd260,
12'd256,
12'd2049,
12'd2048,
12'd3074,
12'd3073,
12'd3072,
12'd3,
12'd2,
12'd1:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 =
coreFix_aluExe_0_regToExeQ$first[394:383];
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[172:161])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143 =
fetchStage$pipelines_0_first[172:161];
default: IF_fetchStage_pipelines_0_first__2932_BITS_172_ETC___d13143 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[67:64])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 =
fetchStage$pipelines_0_first[67:64];
4'd11:
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 = 4'd10;
4'd12:
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 = 4'd11;
4'd13:
IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 = 4'd12;
default: IF_fetchStage_pipelines_0_first__2932_BIT_68_2_ETC___d13298 =
4'd13;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[177:175])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 =
fetchStage$pipelines_0_first[177:175];
default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 = 3'd7;
endcase
end
always@(fetchStage$pipelines_0_first or
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1, 3'd2, 3'd3:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061 =
fetchStage$pipelines_0_first[194:174];
3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061 =
{ fetchStage$pipelines_0_first[194:192],
9'h0AA,
fetchStage$pipelines_0_first[182:178],
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233,
fetchStage$pipelines_0_first[174] };
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13061 =
21'd1485482;
endcase
end
always@(checkForException___d13178)
begin
case (checkForException___d13178[3:0])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
CASE_checkForException_3178_BITS_3_TO_0_0_chec_ETC__q234 =
checkForException___d13178[3:0];
4'd11: CASE_checkForException_3178_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10;
4'd12: CASE_checkForException_3178_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11;
4'd13: CASE_checkForException_3178_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12;
default: CASE_checkForException_3178_BITS_3_TO_0_0_chec_ETC__q234 =
4'd13;
endcase
end
always@(k__h672122 or
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
begin
case (k__h672122)
1'd0:
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 =
coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 =
coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 =
coreFix_memExe_lsq$enqLdTag[6];
default: IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 =
coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13639 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13639 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13639 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635;
endcase
end
always@(k__h672122 or
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
begin
case (k__h672122)
1'd0:
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 =
!coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 =
!coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_0_first or
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 or
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13658 or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 =
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13658;
3'd2:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 =
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13663 =
regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 =
!coreFix_memExe_lsq$enqLdTag[6];
default: IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 =
!coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 or
specTagManager$canClaim or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13698 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13698 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d13698 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693);
endcase
end
always@(fetchStage$pipelines_1_first)
begin
case (fetchStage$pipelines_1_first[172:161])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 =
fetchStage$pipelines_1_first[172:161];
default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_1_first)
begin
case (fetchStage$pipelines_1_first[177:175])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 =
fetchStage$pipelines_1_first[177:175];
default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 = 3'd7;
endcase
end
always@(fetchStage$pipelines_1_first or
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1, 3'd2, 3'd3:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d13758 =
fetchStage$pipelines_1_first[194:174];
3'd4:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d13758 =
{ fetchStage$pipelines_1_first[194:192],
9'h0AA,
fetchStage$pipelines_1_first[182:178],
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236,
fetchStage$pipelines_1_first[174] };
default: IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d13758 =
21'd1485482;
endcase
end
always@(idx__h687446 or
fetchStage$pipelines_0_canDeq or
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13912 or
coreFix_aluExe_0_rsAlu$canEnq or
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13918 or
coreFix_aluExe_1_rsAlu$canEnq)
begin
case (idx__h687446)
1'd0:
SEL_ARR_fetchStage_pipelines_0_canDeq__2930_AN_ETC___d13938 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13912 ||
!coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_fetchStage_pipelines_0_canDeq__2930_AN_ETC___d13938 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2932_BITS_19_ETC___d13918 ||
!coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 =
!coreFix_memExe_lsq$enqLdTag[6];
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 =
!coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14006 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 or
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14010 or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14016 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 ||
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14010;
3'd2:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14016 =
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14006;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14016 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14006;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14016 =
renameStage_rg_m_halt_req_2959_BIT_4_2960_OR_f_ETC___d14006;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14038 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14038 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635;
endcase
end
always@(fetchStage$pipelines_0_first or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14056 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14056 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14056 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 =
coreFix_memExe_lsq$enqLdTag[6];
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 =
coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_1_first or
regRenamingTable_rename_1_canRename__3704_AND__ETC___d13904 or
SEL_ARR_fetchStage_pipelines_0_canDeq__2930_AN_ETC___d13938 or
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d14022 or
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14053 or
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14064 or
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14035 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14046)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 =
!SEL_ARR_fetchStage_pipelines_0_canDeq__2930_AN_ETC___d13938 &&
NOT_fetchStage_pipelines_1_first__2941_BITS_19_ETC___d14022;
3'd2:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 =
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14053 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14064;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 =
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14035 &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14046;
default: IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14068 =
regRenamingTable_rename_1_canRename__3704_AND__ETC___d13904;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 =
coreFix_memExe_lsq$RDY_enqLd;
default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 =
coreFix_memExe_lsq$RDY_enqSt;
endcase
end
always@(k__h672122 or
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
begin
case (k__h672122)
1'd0:
CASE_k72122_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 =
coreFix_aluExe_0_rsAlu$RDY_enq;
1'd1:
CASE_k72122_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 =
coreFix_aluExe_1_rsAlu$RDY_enq;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14113 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14113 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14113 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693);
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 or
regRenamingTable_RDY_rename_0_getRename__3468__ETC___d14107 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or
regRenamingTable$RDY_rename_0_getRename or
_0_OR_NOT_fetchStage_pipelines_0_first__2932_BI_ETC___d14094 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14111 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 ||
regRenamingTable$RDY_rename_0_getRename &&
_0_OR_NOT_fetchStage_pipelines_0_first__2932_BI_ETC___d14094;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14111 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
regRenamingTable$RDY_rename_0_getRename;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14111 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 ||
regRenamingTable_RDY_rename_0_getRename__3468__ETC___d14107;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14127 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14127 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14127 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693);
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 or
specTagManager$canClaim or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14134 =
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim);
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14134 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14134 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13635;
endcase
end
always@(idx__h687446 or
fetchStage$pipelines_0_canDeq or
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14157 or
coreFix_aluExe_0_rsAlu$canEnq or
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14164 or
coreFix_aluExe_1_rsAlu$canEnq)
begin
case (idx__h687446)
1'd0:
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14168 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14157) &&
coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14168 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2932_BITS_194_TO_ETC___d14164) &&
coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14184 or
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
begin
case (fetchStage_pipelines_0_canDeq__2930_AND_NOT_fe_ETC___d14184)
1'd0:
CASE_fetchStage_pipelines_0_canDeq__2930_AND_N_ETC__q241 =
coreFix_aluExe_0_rsAlu$RDY_enq;
1'd1:
CASE_fetchStage_pipelines_0_canDeq__2930_AND_N_ETC__q241 =
coreFix_aluExe_1_rsAlu$RDY_enq;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 =
coreFix_memExe_lsq$RDY_enqLd;
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 =
coreFix_memExe_lsq$RDY_enqSt;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14210 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14210 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693);
endcase
end
always@(fetchStage$pipelines_0_first or
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14222 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14222 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2932_BITS_194_ETC___d14222 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d13693;
endcase
end
always@(fetchStage$pipelines_1_first or
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14231 or
SEL_ARR_fetchStage_pipelines_0_canDeq__2930_AN_ETC___d13938 or
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14219)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14234 =
SEL_ARR_fetchStage_pipelines_0_canDeq__2930_AN_ETC___d13938;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14234 =
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14219;
default: IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14234 =
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14231;
endcase
end
always@(fetchStage$pipelines_1_first or
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14197 or
regRenamingTable$RDY_rename_1_getRename or
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14202 or
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14168 or
regRenamingTable_RDY_rename_1_getRename__4170__ETC___d14188 or
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14190 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14193)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14207 =
!SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14168 ||
regRenamingTable_RDY_rename_1_getRename__4170__ETC___d14188;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14207 =
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14190 ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14193;
default: IF_fetchStage_pipelines_1_first__2941_BITS_194_ETC___d14207 =
fetchStage$pipelines_1_first[194:192] != 3'd2 ||
fetchStage_pipelines_0_canDeq__2930_AND_regRen_ETC___d14197 ||
regRenamingTable$RDY_rename_1_getRename &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14202;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14308 =
!coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14308 =
!coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14314 =
coreFix_memExe_lsq$enqLdTag[3:0];
default: IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14314 =
coreFix_memExe_lsq$enqStTag[3:0];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14305 =
coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14305 =
coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14311 =
coreFix_memExe_lsq$enqLdTag[4:0];
default: IF_fetchStage_pipelines_0_first__2932_BITS_191_ETC___d14311 =
coreFix_memExe_lsq$enqStTag[4:0];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14477 =
coreFix_memExe_lsq$enqLdTag[3:0];
default: IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14477 =
coreFix_memExe_lsq$enqStTag[3:0];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14475 =
!coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14475 =
!coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14474 =
coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14474 =
coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14476 =
coreFix_memExe_lsq$enqLdTag[4:0];
default: IF_fetchStage_pipelines_1_first__2941_BITS_191_ETC___d14476 =
coreFix_memExe_lsq$enqStTag[4:0];
endcase
end
always@(csrf_prv_reg or csrf_rg_dcsr)
begin
case (csrf_prv_reg)
2'd1:
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
!csrf_rg_dcsr[13];
2'd3:
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
!csrf_rg_dcsr[15];
default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
!csrf_rg_dcsr[12];
endcase
end
always@(csrf_prv_reg or csrf_rg_dcsr)
begin
case (csrf_prv_reg)
2'd1:
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
csrf_rg_dcsr[13];
2'd3:
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
csrf_rg_dcsr[15];
default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
csrf_rg_dcsr[12];
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[180:169])
12'd1:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd0;
12'd2:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd1;
12'd3:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd2;
12'd256:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd8;
12'd260:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd9;
12'd261:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd10;
12'd262:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd11;
12'd320:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd12;
12'd321:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd13;
12'd322:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd14;
12'd323:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd15;
12'd324:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd16;
12'd384:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd17;
12'd768:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd18;
12'd769:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd19;
12'd770:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd20;
12'd771:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd21;
12'd772:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd22;
12'd773:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd23;
12'd774:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd24;
12'd832:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd25;
12'd833:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd26;
12'd834:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd27;
12'd835:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd28;
12'd836:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd29;
12'd1968:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd36;
12'd1969:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd37;
12'd1970:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd38;
12'd1971:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd39;
12'd2048:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd6;
12'd2049:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd7;
12'd2816:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd30;
12'd2818:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd31;
12'd3072:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd3;
12'd3073:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd4;
12'd3074:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd5;
12'd3857:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd32;
12'd3858:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd33;
12'd3859:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd34;
12'd3860:
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 = 6'd35;
default: IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 =
6'd40;
endcase
end
always@(IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 or
rob$deqPort_0_deq_data or robdeqPort_0_deq_data_BITS_95_TO_32__q245)
begin
case (IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189)
6'd0:
data_warl_xformed__h720256 =
{ 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] };
6'd1, 6'd11, 6'd24:
data_warl_xformed__h720256 =
{ 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] };
6'd2:
data_warl_xformed__h720256 =
{ 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] };
6'd8:
data_warl_xformed__h720256 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11,
43'd8192,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18],
3'd0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13],
4'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[8],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:4],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
6'd9, 6'd16:
data_warl_xformed__h720256 =
{ 54'd0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:8],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:4],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
6'd10, 6'd23:
data_warl_xformed__h720256 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] };
6'd14, 6'd27:
data_warl_xformed__h720256 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[63],
59'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] };
6'd17:
data_warl_xformed__h720256 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[63],
19'd0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] };
6'd18:
data_warl_xformed__h720256 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11,
40'd5120,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:11],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[8:7],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
6'd19: data_warl_xformed__h720256 = 64'h800000000014112D;
6'd20, 6'd21, 6'd22, 6'd29:
data_warl_xformed__h720256 =
{ 52'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[11],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:7],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h720256 = 64'd0;
6'd36:
data_warl_xformed__h720256 =
{ 32'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28],
12'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[14],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] };
default: data_warl_xformed__h720256 = rob$deqPort_0_deq_data[95:32];
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[97:96])
2'd0, 2'd1:
CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q246 =
rob$deqPort_0_deq_data[97:96];
default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q246 = 2'd2;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[180:169])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q247 =
rob$deqPort_0_deq_data[180:169];
default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q247 =
12'd2303;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[165:162])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 =
rob$deqPort_0_deq_data[165:162];
default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 =
4'd15;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[165:162])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q249 =
rob$deqPort_0_deq_data[165:162];
default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q249 =
4'd15;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q252 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q252 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd0:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 = 3'd4;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 = 3'd3;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 = 3'd2;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 = 3'd1;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10829 =
3'd0;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
coreFix_memExe_stb$deq or
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179 or
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2237)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79])
3'd0, 3'd2, 3'd4:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2529 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
3'd1:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2529 =
{ coreFix_memExe_stb$deq[575] ?
coreFix_memExe_stb$deq[511:504] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504],
coreFix_memExe_stb$deq[574] ?
coreFix_memExe_stb$deq[503:496] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496],
coreFix_memExe_stb$deq[573] ?
coreFix_memExe_stb$deq[495:488] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488],
coreFix_memExe_stb$deq[572] ?
coreFix_memExe_stb$deq[487:480] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480],
coreFix_memExe_stb$deq[571] ?
coreFix_memExe_stb$deq[479:472] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472],
coreFix_memExe_stb$deq[570] ?
coreFix_memExe_stb$deq[471:464] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464],
coreFix_memExe_stb$deq[569] ?
coreFix_memExe_stb$deq[463:456] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456],
coreFix_memExe_stb$deq[568] ?
coreFix_memExe_stb$deq[455:448] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448],
coreFix_memExe_stb$deq[567] ?
coreFix_memExe_stb$deq[447:440] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440],
coreFix_memExe_stb$deq[566] ?
coreFix_memExe_stb$deq[439:432] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432],
coreFix_memExe_stb$deq[565] ?
coreFix_memExe_stb$deq[431:424] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424],
coreFix_memExe_stb$deq[564] ?
coreFix_memExe_stb$deq[423:416] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416],
coreFix_memExe_stb$deq[563] ?
coreFix_memExe_stb$deq[415:408] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408],
coreFix_memExe_stb$deq[562] ?
coreFix_memExe_stb$deq[407:400] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400],
coreFix_memExe_stb$deq[561] ?
coreFix_memExe_stb$deq[399:392] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392],
coreFix_memExe_stb$deq[560] ?
coreFix_memExe_stb$deq[391:384] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384],
coreFix_memExe_stb$deq[559] ?
coreFix_memExe_stb$deq[383:376] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376],
coreFix_memExe_stb$deq[558] ?
coreFix_memExe_stb$deq[375:368] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368],
coreFix_memExe_stb$deq[557] ?
coreFix_memExe_stb$deq[367:360] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360],
coreFix_memExe_stb$deq[556] ?
coreFix_memExe_stb$deq[359:352] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352],
coreFix_memExe_stb$deq[555] ?
coreFix_memExe_stb$deq[351:344] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344],
coreFix_memExe_stb$deq[554] ?
coreFix_memExe_stb$deq[343:336] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336],
coreFix_memExe_stb$deq[553] ?
coreFix_memExe_stb$deq[335:328] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328],
coreFix_memExe_stb$deq[552] ?
coreFix_memExe_stb$deq[327:320] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320],
coreFix_memExe_stb$deq[551] ?
coreFix_memExe_stb$deq[319:312] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312],
coreFix_memExe_stb$deq[550] ?
coreFix_memExe_stb$deq[311:304] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304],
coreFix_memExe_stb$deq[549] ?
coreFix_memExe_stb$deq[303:296] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296],
coreFix_memExe_stb$deq[548] ?
coreFix_memExe_stb$deq[295:288] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288],
coreFix_memExe_stb$deq[547] ?
coreFix_memExe_stb$deq[287:280] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280],
coreFix_memExe_stb$deq[546] ?
coreFix_memExe_stb$deq[279:272] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272],
coreFix_memExe_stb$deq[545] ?
coreFix_memExe_stb$deq[271:264] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264],
coreFix_memExe_stb$deq[544] ?
coreFix_memExe_stb$deq[263:256] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256],
coreFix_memExe_stb$deq[543] ?
coreFix_memExe_stb$deq[255:248] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248],
coreFix_memExe_stb$deq[542] ?
coreFix_memExe_stb$deq[247:240] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240],
coreFix_memExe_stb$deq[541] ?
coreFix_memExe_stb$deq[239:232] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232],
coreFix_memExe_stb$deq[540] ?
coreFix_memExe_stb$deq[231:224] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224],
coreFix_memExe_stb$deq[539] ?
coreFix_memExe_stb$deq[223:216] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216],
coreFix_memExe_stb$deq[538] ?
coreFix_memExe_stb$deq[215:208] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208],
coreFix_memExe_stb$deq[537] ?
coreFix_memExe_stb$deq[207:200] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200],
coreFix_memExe_stb$deq[536] ?
coreFix_memExe_stb$deq[199:192] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192],
coreFix_memExe_stb$deq[535] ?
coreFix_memExe_stb$deq[191:184] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184],
coreFix_memExe_stb$deq[534] ?
coreFix_memExe_stb$deq[183:176] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176],
coreFix_memExe_stb$deq[533] ?
coreFix_memExe_stb$deq[175:168] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168],
coreFix_memExe_stb$deq[532] ?
coreFix_memExe_stb$deq[167:160] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160],
coreFix_memExe_stb$deq[531] ?
coreFix_memExe_stb$deq[159:152] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152],
coreFix_memExe_stb$deq[530] ?
coreFix_memExe_stb$deq[151:144] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144],
coreFix_memExe_stb$deq[529] ?
coreFix_memExe_stb$deq[143:136] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136],
coreFix_memExe_stb$deq[528] ?
coreFix_memExe_stb$deq[135:128] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128],
coreFix_memExe_stb$deq[527] ?
coreFix_memExe_stb$deq[127:120] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120],
coreFix_memExe_stb$deq[526] ?
coreFix_memExe_stb$deq[119:112] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112],
coreFix_memExe_stb$deq[525] ?
coreFix_memExe_stb$deq[111:104] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104],
coreFix_memExe_stb$deq[524] ?
coreFix_memExe_stb$deq[103:96] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96],
coreFix_memExe_stb$deq[523] ?
coreFix_memExe_stb$deq[95:88] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88],
coreFix_memExe_stb$deq[522] ?
coreFix_memExe_stb$deq[87:80] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80],
coreFix_memExe_stb$deq[521] ?
coreFix_memExe_stb$deq[79:72] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72],
coreFix_memExe_stb$deq[520] ?
coreFix_memExe_stb$deq[71:64] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64],
coreFix_memExe_stb$deq[519] ?
coreFix_memExe_stb$deq[63:56] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56],
coreFix_memExe_stb$deq[518] ?
coreFix_memExe_stb$deq[55:48] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48],
coreFix_memExe_stb$deq[517] ?
coreFix_memExe_stb$deq[47:40] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40],
coreFix_memExe_stb$deq[516] ?
coreFix_memExe_stb$deq[39:32] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32],
coreFix_memExe_stb$deq[515] ?
coreFix_memExe_stb$deq[31:24] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24],
coreFix_memExe_stb$deq[514] ?
coreFix_memExe_stb$deq[23:16] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16],
coreFix_memExe_stb$deq[513] ?
coreFix_memExe_stb$deq[15:8] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8],
coreFix_memExe_stb$deq[512] ?
coreFix_memExe_stb$deq[7:0] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] };
3'd3:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2529 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2179 ?
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2237 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2529 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd4, 3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q256 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q256 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9996 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9286 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10052)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10056 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9286;
5'd25:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10056 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9996;
5'd26, 5'd27:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10056 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10052;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10056 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9996;
endcase
end
always@(commitStage_f_rob_data$D_OUT)
begin
case (commitStage_f_rob_data$D_OUT[97:96])
2'd0, 2'd1:
CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 =
commitStage_f_rob_data$D_OUT[97:96];
default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 = 2'd2;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8521 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq;
5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8521 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8521 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d8521 =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8539 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228])
2'd0, 2'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q267 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q267 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8539;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
endcase
end
always@(mmio_dataReqQ_data_0)
begin
case (mmio_dataReqQ_data_0[77:76])
2'd0, 2'd1, 2'd2:
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q275 =
mmio_dataReqQ_data_0[77:72];
2'd3:
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q275 =
{ 2'd3, mmio_dataReqQ_data_0[75:72] };
endcase
end
always@(coreFix_memExe_lsq$firstSt)
begin
case (coreFix_memExe_lsq$firstSt[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 =
coreFix_memExe_lsq$firstSt[3:0];
default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 =
4'd15;
endcase
end
always@(coreFix_memExe_lsq$firstLd)
begin
case (coreFix_memExe_lsq$firstLd[6:3])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q277 =
coreFix_memExe_lsq$firstLd[6:3];
default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q277 =
4'd15;
endcase
end
always@(commitStage_f_rob_data$D_OUT)
begin
case (commitStage_f_rob_data$D_OUT[180:169])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q278 =
commitStage_f_rob_data$D_OUT[180:169];
default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q278 =
12'd2303;
endcase
end
always@(commitStage_f_rob_data$D_OUT)
begin
case (commitStage_f_rob_data$D_OUT[165:162])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 =
commitStage_f_rob_data$D_OUT[165:162];
default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 =
4'd15;
endcase
end
always@(commitStage_f_rob_data$D_OUT)
begin
case (commitStage_f_rob_data$D_OUT[165:162])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q280 =
commitStage_f_rob_data$D_OUT[165:162];
default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q280 =
4'd15;
endcase
end
always@(mmioToPlatform_pRq_enq_x)
begin
case (mmioToPlatform_pRq_enq_x[37:36])
2'd0, 2'd1, 2'd2:
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q281 =
mmioToPlatform_pRq_enq_x[37:32];
2'd3:
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q281 =
{ 2'd3, mmioToPlatform_pRq_enq_x[35:32] };
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[139:137])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282 =
coreFix_aluExe_0_rsAlu$dispatchData[139:137];
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData or
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[156:154])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283 =
coreFix_aluExe_0_rsAlu$dispatchData[156:136];
3'd4:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283 =
{ coreFix_aluExe_0_rsAlu$dispatchData[156:154],
9'h0AA,
coreFix_aluExe_0_rsAlu$dispatchData[144:140],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282,
coreFix_aluExe_0_rsAlu$dispatchData[136] };
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[134:123])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q284 =
coreFix_aluExe_0_rsAlu$dispatchData[134:123];
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q284 =
12'd2303;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first)
begin
case (coreFix_aluExe_0_dispToRegQ$first[135:133])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q285 =
coreFix_aluExe_0_dispToRegQ$first[135:133];
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q285 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first or
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q285)
begin
case (coreFix_aluExe_0_dispToRegQ$first[152:150])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q286 =
coreFix_aluExe_0_dispToRegQ$first[152:132];
3'd4:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q286 =
{ coreFix_aluExe_0_dispToRegQ$first[152:150],
9'h0AA,
coreFix_aluExe_0_dispToRegQ$first[140:136],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q285,
coreFix_aluExe_0_dispToRegQ$first[132] };
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q286 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first)
begin
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q287 =
coreFix_aluExe_0_dispToRegQ$first[130:119];
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q287 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[139:137])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288 =
coreFix_aluExe_1_rsAlu$dispatchData[139:137];
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData or
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[156:154])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289 =
coreFix_aluExe_1_rsAlu$dispatchData[156:136];
3'd4:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289 =
{ coreFix_aluExe_1_rsAlu$dispatchData[156:154],
9'h0AA,
coreFix_aluExe_1_rsAlu$dispatchData[144:140],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288,
coreFix_aluExe_1_rsAlu$dispatchData[136] };
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[134:123])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q290 =
coreFix_aluExe_1_rsAlu$dispatchData[134:123];
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q290 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first)
begin
case (coreFix_aluExe_1_dispToRegQ$first[135:133])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q291 =
coreFix_aluExe_1_dispToRegQ$first[135:133];
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q291 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first or
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q291)
begin
case (coreFix_aluExe_1_dispToRegQ$first[152:150])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q292 =
coreFix_aluExe_1_dispToRegQ$first[152:132];
3'd4:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q292 =
{ coreFix_aluExe_1_dispToRegQ$first[152:150],
9'h0AA,
coreFix_aluExe_1_dispToRegQ$first[140:136],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q291,
coreFix_aluExe_1_dispToRegQ$first[132] };
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q292 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first)
begin
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q293 =
coreFix_aluExe_1_dispToRegQ$first[130:119];
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q293 =
12'd2303;
endcase
end
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData)
begin
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67];
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294)
begin
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q295 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66];
3'd4:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q295 =
{ coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84],
9'h0AA,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70],
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] };
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q295 =
21'd1485482;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9286 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10766 or
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10819 or
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10764)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10766;
5'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[139],
coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10819,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10764 };
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d9286;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10766)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q297 =
64'h3FF0000000000000;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q297 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__483_ETC___d10766;
endcase
end
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first)
begin
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298 =
coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58];
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298)
begin
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299 =
coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57];
3'd4:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299 =
{ coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75],
9'h0AA,
coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61],
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298,
coreFix_fpuMulDivExe_0_dispToRegQ$first[57] };
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299 =
21'd1485482;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0];
endcase
end
always@(rob$deqPort_1_deq_data)
begin
case (rob$deqPort_1_deq_data[180:169])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q301 =
rob$deqPort_1_deq_data[180:169];
default: CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q301 =
12'd2303;
endcase
end
always@(rob$deqPort_1_deq_data)
begin
case (rob$deqPort_1_deq_data[97:96])
2'd0, 2'd1:
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q302 =
rob$deqPort_1_deq_data[97:96];
default: CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q302 = 2'd2;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY 64'd0;
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
4'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
2'd3;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
3'd2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
3'd2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
4'd2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
59'h2AAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
72'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
72'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
73'h0AAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
66'h2AAAAAAAAAAAAAAAA;
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY 5'd0;
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY 10'd0;
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY 44'd0;
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY 2'd3;
csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY 64'd1073741843;
csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY 64'd1879048192;
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_brpred <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_caches <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_reservation <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_tlbs <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
142'h000000000000000004000000000000000000;
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
142'h000000000000000004000000000000000000;
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
66'h0AAAAAAAAAAAAAAAA;
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 39'h0400000000;
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 40'h2AAAAAAAAA;
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 67'h155555554AAAAAAAA;
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA;
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
outOfReset <= `BSV_ASSIGNMENT_DELAY 1'd0;
renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY 5'd10;
rg_core_run_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
started <= `BSV_ASSIGNMENT_DELAY 1'd0;
update_vm_info <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (commitStage_commitTrap$EN)
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
commitStage_commitTrap$D_IN;
if (commitStage_rg_just_after_reset$EN)
commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_just_after_reset$D_IN;
if (commitStage_rg_run_state$EN)
commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_run_state$D_IN;
if (commitStage_rg_serial_num$EN)
commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_serial_num$D_IN;
if (coreFix_doStatsReg$EN)
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY coreFix_doStatsReg$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN)
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN;
if (coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_data_0$EN)
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
if (coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_empty$EN)
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_empty$D_IN;
if (coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_full$EN)
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_full$D_IN;
if (coreFix_memExe_forwardQ_clearReq_rl$EN)
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_clearReq_rl$D_IN;
if (coreFix_memExe_forwardQ_data_0$EN)
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_data_0$D_IN;
if (coreFix_memExe_forwardQ_data_1$EN)
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_data_1$D_IN;
if (coreFix_memExe_forwardQ_deqP$EN)
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_deqP$D_IN;
if (coreFix_memExe_forwardQ_deqReq_rl$EN)
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_deqReq_rl$D_IN;
if (coreFix_memExe_forwardQ_empty$EN)
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_empty$D_IN;
if (coreFix_memExe_forwardQ_enqP$EN)
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_enqP$D_IN;
if (coreFix_memExe_forwardQ_enqReq_rl$EN)
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_enqReq_rl$D_IN;
if (coreFix_memExe_forwardQ_full$EN)
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_full$D_IN;
if (coreFix_memExe_memRespLdQ_clearReq_rl$EN)
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_clearReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_data_0$EN)
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_data_0$D_IN;
if (coreFix_memExe_memRespLdQ_data_1$EN)
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_data_1$D_IN;
if (coreFix_memExe_memRespLdQ_deqP$EN)
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_deqP$D_IN;
if (coreFix_memExe_memRespLdQ_deqReq_rl$EN)
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_deqReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_empty$EN)
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_empty$D_IN;
if (coreFix_memExe_memRespLdQ_enqP$EN)
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_enqP$D_IN;
if (coreFix_memExe_memRespLdQ_enqReq_rl$EN)
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_full$EN)
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_full$D_IN;
if (coreFix_memExe_reqLdQ_data_0_rl$EN)
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_data_0_rl$D_IN;
if (coreFix_memExe_reqLdQ_empty_rl$EN)
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_empty_rl$D_IN;
if (coreFix_memExe_reqLdQ_full_rl$EN)
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_full_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_data_0_rl$EN)
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_empty_rl$EN)
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_full_rl$EN)
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_full_rl$D_IN;
if (coreFix_memExe_reqStQ_data_0_rl$EN)
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_data_0_rl$D_IN;
if (coreFix_memExe_reqStQ_empty_rl$EN)
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_empty_rl$D_IN;
if (coreFix_memExe_reqStQ_full_rl$EN)
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_full_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_clearReq_rl$EN)
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_data_0$EN)
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_data_0$D_IN;
if (coreFix_memExe_respLrScAmoQ_deqReq_rl$EN)
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_empty$EN)
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_empty$D_IN;
if (coreFix_memExe_respLrScAmoQ_enqReq_rl$EN)
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_full$EN)
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_full$D_IN;
if (coreFix_memExe_waitLrScAmoMMIOResp$EN)
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
if (csrInstOrInterruptInflight_rl$EN)
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY
csrInstOrInterruptInflight_rl$D_IN;
if (csrf_external_int_en_vec_0$EN)
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_0$D_IN;
if (csrf_external_int_en_vec_1$EN)
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_1$D_IN;
if (csrf_external_int_en_vec_3$EN)
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_3$D_IN;
if (csrf_external_int_pend_vec_0$EN)
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_0$D_IN;
if (csrf_external_int_pend_vec_1$EN)
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_1$D_IN;
if (csrf_external_int_pend_vec_3$EN)
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_3$D_IN;
if (csrf_fflags_reg$EN)
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY csrf_fflags_reg$D_IN;
if (csrf_frm_reg$EN)
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY csrf_frm_reg$D_IN;
if (csrf_fs_reg$EN)
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY csrf_fs_reg$D_IN;
if (csrf_ie_vec_0$EN)
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_0$D_IN;
if (csrf_ie_vec_1$EN)
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_1$D_IN;
if (csrf_ie_vec_3$EN)
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_3$D_IN;
if (csrf_mcause_code_reg$EN)
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcause_code_reg$D_IN;
if (csrf_mcause_interrupt_reg$EN)
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcause_interrupt_reg$D_IN;
if (csrf_mcounteren_cy_reg$EN)
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_cy_reg$D_IN;
if (csrf_mcounteren_ir_reg$EN)
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_ir_reg$D_IN;
if (csrf_mcounteren_tm_reg$EN)
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_tm_reg$D_IN;
if (csrf_mcycle_ehr_data_rl$EN)
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
csrf_mcycle_ehr_data_rl$D_IN;
if (csrf_medeleg_13_11_reg$EN)
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_13_11_reg$D_IN;
if (csrf_medeleg_15_reg$EN)
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_15_reg$D_IN;
if (csrf_medeleg_9_0_reg$EN)
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_9_0_reg$D_IN;
if (csrf_mepc_csr$EN)
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_mepc_csr$D_IN;
if (csrf_mideleg_11_reg$EN)
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_11_reg$D_IN;
if (csrf_mideleg_1_0_reg$EN)
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_1_0_reg$D_IN;
if (csrf_mideleg_5_3_reg$EN)
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_5_3_reg$D_IN;
if (csrf_mideleg_9_7_reg$EN)
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_9_7_reg$D_IN;
if (csrf_minstret_ehr_data_rl$EN)
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
csrf_minstret_ehr_data_rl$D_IN;
if (csrf_mpp_reg$EN)
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY csrf_mpp_reg$D_IN;
if (csrf_mprv_reg$EN)
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY csrf_mprv_reg$D_IN;
if (csrf_mscratch_csr$EN)
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_mscratch_csr$D_IN;
if (csrf_mtval_csr$EN)
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY csrf_mtval_csr$D_IN;
if (csrf_mtvec_base_hi_reg$EN)
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mtvec_base_hi_reg$D_IN;
if (csrf_mtvec_mode_low_reg$EN)
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mtvec_mode_low_reg$D_IN;
if (csrf_mxr_reg$EN)
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mxr_reg$D_IN;
if (csrf_ppn_reg$EN)
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY csrf_ppn_reg$D_IN;
if (csrf_prev_ie_vec_0$EN)
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_0$D_IN;
if (csrf_prev_ie_vec_1$EN)
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_1$D_IN;
if (csrf_prev_ie_vec_3$EN)
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_3$D_IN;
if (csrf_prv_reg$EN)
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY csrf_prv_reg$D_IN;
if (csrf_rg_dcsr$EN)
csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY csrf_rg_dcsr$D_IN;
if (csrf_rg_dpc$EN)
csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY csrf_rg_dpc$D_IN;
if (csrf_scause_code_reg$EN)
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scause_code_reg$D_IN;
if (csrf_scause_interrupt_reg$EN)
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scause_interrupt_reg$D_IN;
if (csrf_scounteren_cy_reg$EN)
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_cy_reg$D_IN;
if (csrf_scounteren_ir_reg$EN)
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_ir_reg$D_IN;
if (csrf_scounteren_tm_reg$EN)
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_tm_reg$D_IN;
if (csrf_sepc_csr$EN)
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_sepc_csr$D_IN;
if (csrf_software_int_en_vec_0$EN)
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_0$D_IN;
if (csrf_software_int_en_vec_1$EN)
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_1$D_IN;
if (csrf_software_int_en_vec_3$EN)
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_3$D_IN;
if (csrf_software_int_pend_vec_0$EN)
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_0$D_IN;
if (csrf_software_int_pend_vec_1$EN)
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_1$D_IN;
if (csrf_software_int_pend_vec_3$EN)
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_3$D_IN;
if (csrf_spp_reg$EN)
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY csrf_spp_reg$D_IN;
if (csrf_sscratch_csr$EN)
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_sscratch_csr$D_IN;
if (csrf_stats_module_doStats$EN)
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY
csrf_stats_module_doStats$D_IN;
if (csrf_stval_csr$EN)
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY csrf_stval_csr$D_IN;
if (csrf_stvec_base_hi_reg$EN)
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
csrf_stvec_base_hi_reg$D_IN;
if (csrf_stvec_mode_low_reg$EN)
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
csrf_stvec_mode_low_reg$D_IN;
if (csrf_sum_reg$EN)
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY csrf_sum_reg$D_IN;
if (csrf_time_reg$EN)
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY csrf_time_reg$D_IN;
if (csrf_timer_int_en_vec_0$EN)
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_0$D_IN;
if (csrf_timer_int_en_vec_1$EN)
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_1$D_IN;
if (csrf_timer_int_en_vec_3$EN)
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_3$D_IN;
if (csrf_timer_int_pend_vec_0$EN)
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_0$D_IN;
if (csrf_timer_int_pend_vec_1$EN)
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_1$D_IN;
if (csrf_timer_int_pend_vec_3$EN)
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_3$D_IN;
if (csrf_tsr_reg$EN)
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY csrf_tsr_reg$D_IN;
if (csrf_tvm_reg$EN)
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY csrf_tvm_reg$D_IN;
if (csrf_tw_reg$EN)
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY csrf_tw_reg$D_IN;
if (csrf_vm_mode_sv39_reg$EN)
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY
csrf_vm_mode_sv39_reg$D_IN;
if (flush_brpred$EN)
flush_brpred <= `BSV_ASSIGNMENT_DELAY flush_brpred$D_IN;
if (flush_caches$EN)
flush_caches <= `BSV_ASSIGNMENT_DELAY flush_caches$D_IN;
if (flush_reservation$EN)
flush_reservation <= `BSV_ASSIGNMENT_DELAY flush_reservation$D_IN;
if (flush_tlbs$EN)
flush_tlbs <= `BSV_ASSIGNMENT_DELAY flush_tlbs$D_IN;
if (mmio_cRqQ_clearReq_rl$EN)
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_clearReq_rl$D_IN;
if (mmio_cRqQ_data_0$EN)
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_data_0$D_IN;
if (mmio_cRqQ_deqReq_rl$EN)
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_deqReq_rl$D_IN;
if (mmio_cRqQ_empty$EN)
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_empty$D_IN;
if (mmio_cRqQ_enqReq_rl$EN)
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_enqReq_rl$D_IN;
if (mmio_cRqQ_full$EN)
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_full$D_IN;
if (mmio_cRsQ_clearReq_rl$EN)
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_clearReq_rl$D_IN;
if (mmio_cRsQ_data_0$EN)
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_data_0$D_IN;
if (mmio_cRsQ_deqReq_rl$EN)
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_deqReq_rl$D_IN;
if (mmio_cRsQ_empty$EN)
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_empty$D_IN;
if (mmio_cRsQ_enqReq_rl$EN)
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_enqReq_rl$D_IN;
if (mmio_cRsQ_full$EN)
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_full$D_IN;
if (mmio_dataPendQ_clearReq_rl$EN)
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_clearReq_rl$D_IN;
if (mmio_dataPendQ_deqReq_rl$EN)
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_deqReq_rl$D_IN;
if (mmio_dataPendQ_empty$EN)
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_empty$D_IN;
if (mmio_dataPendQ_enqReq_rl$EN)
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_enqReq_rl$D_IN;
if (mmio_dataPendQ_full$EN)
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_full$D_IN;
if (mmio_dataReqQ_clearReq_rl$EN)
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_clearReq_rl$D_IN;
if (mmio_dataReqQ_data_0$EN)
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_data_0$D_IN;
if (mmio_dataReqQ_deqReq_rl$EN)
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_deqReq_rl$D_IN;
if (mmio_dataReqQ_empty$EN)
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_empty$D_IN;
if (mmio_dataReqQ_enqReq_rl$EN)
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_enqReq_rl$D_IN;
if (mmio_dataReqQ_full$EN)
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_dataReqQ_full$D_IN;
if (mmio_dataRespQ_clearReq_rl$EN)
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_clearReq_rl$D_IN;
if (mmio_dataRespQ_data_0$EN)
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_data_0$D_IN;
if (mmio_dataRespQ_deqReq_rl$EN)
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_deqReq_rl$D_IN;
if (mmio_dataRespQ_empty$EN)
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_empty$D_IN;
if (mmio_dataRespQ_enqReq_rl$EN)
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_enqReq_rl$D_IN;
if (mmio_dataRespQ_full$EN)
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_full$D_IN;
if (mmio_fromHostAddr$EN)
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_fromHostAddr$D_IN;
if (mmio_pRqQ_clearReq_rl$EN)
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_clearReq_rl$D_IN;
if (mmio_pRqQ_data_0$EN)
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_data_0$D_IN;
if (mmio_pRqQ_deqReq_rl$EN)
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_deqReq_rl$D_IN;
if (mmio_pRqQ_empty$EN)
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_empty$D_IN;
if (mmio_pRqQ_enqReq_rl$EN)
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_enqReq_rl$D_IN;
if (mmio_pRqQ_full$EN)
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_full$D_IN;
if (mmio_pRsQ_clearReq_rl$EN)
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_clearReq_rl$D_IN;
if (mmio_pRsQ_data_0$EN)
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_data_0$D_IN;
if (mmio_pRsQ_deqReq_rl$EN)
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_deqReq_rl$D_IN;
if (mmio_pRsQ_empty$EN)
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_empty$D_IN;
if (mmio_pRsQ_enqReq_rl$EN)
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_enqReq_rl$D_IN;
if (mmio_pRsQ_full$EN)
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_full$D_IN;
if (mmio_toHostAddr$EN)
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_toHostAddr$D_IN;
if (outOfReset$EN)
outOfReset <= `BSV_ASSIGNMENT_DELAY outOfReset$D_IN;
if (renameStage_rg_m_halt_req$EN)
renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY
renameStage_rg_m_halt_req$D_IN;
if (rg_core_run_state$EN)
rg_core_run_state <= `BSV_ASSIGNMENT_DELAY rg_core_run_state$D_IN;
if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN;
if (update_vm_info$EN)
update_vm_info <= `BSV_ASSIGNMENT_DELAY update_vm_info$D_IN;
end
if (csrf_rg_dscratch0$EN)
csrf_rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch0$D_IN;
if (csrf_rg_dscratch1$EN)
csrf_rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch1$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
commitStage_commitTrap = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitStage_rg_just_after_reset = 1'h0;
commitStage_rg_run_state = 1'h0;
commitStage_rg_serial_num = 64'hAAAAAAAAAAAAAAAA;
coreFix_doStatsReg = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt = 4'hA;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit = 2'h2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 = 3'h2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl = 4'hA;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 =
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 =
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl = 59'h2AAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_processAmo =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 =
72'hAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 =
72'hAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl =
73'h0AAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 =
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 =
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl =
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full = 1'h0;
coreFix_memExe_dMem_perfReqQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_perfReqQ_data_0 = 4'hA;
coreFix_memExe_dMem_perfReqQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_perfReqQ_empty = 1'h0;
coreFix_memExe_dMem_perfReqQ_enqReq_rl = 5'h0A;
coreFix_memExe_dMem_perfReqQ_full = 1'h0;
coreFix_memExe_forwardQ_clearReq_rl = 1'h0;
coreFix_memExe_forwardQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_deqP = 1'h0;
coreFix_memExe_forwardQ_deqReq_rl = 1'h0;
coreFix_memExe_forwardQ_empty = 1'h0;
coreFix_memExe_forwardQ_enqP = 1'h0;
coreFix_memExe_forwardQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_full = 1'h0;
coreFix_memExe_memRespLdQ_clearReq_rl = 1'h0;
coreFix_memExe_memRespLdQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_deqP = 1'h0;
coreFix_memExe_memRespLdQ_deqReq_rl = 1'h0;
coreFix_memExe_memRespLdQ_empty = 1'h0;
coreFix_memExe_memRespLdQ_enqP = 1'h0;
coreFix_memExe_memRespLdQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_full = 1'h0;
coreFix_memExe_reqLdQ_data_0_rl = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLdQ_empty_rl = 1'h0;
coreFix_memExe_reqLdQ_full_rl = 1'h0;
coreFix_memExe_reqLrScAmoQ_data_0_rl =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLrScAmoQ_empty_rl = 1'h0;
coreFix_memExe_reqLrScAmoQ_full_rl = 1'h0;
coreFix_memExe_reqStQ_data_0_rl = 66'h2AAAAAAAAAAAAAAAA;
coreFix_memExe_reqStQ_empty_rl = 1'h0;
coreFix_memExe_reqStQ_full_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_clearReq_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_deqReq_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_empty = 1'h0;
coreFix_memExe_respLrScAmoQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_full = 1'h0;
coreFix_memExe_waitLrScAmoMMIOResp = 3'h2;
csrInstOrInterruptInflight_rl = 1'h0;
csrf_external_int_en_vec_0 = 1'h0;
csrf_external_int_en_vec_1 = 1'h0;
csrf_external_int_en_vec_3 = 1'h0;
csrf_external_int_pend_vec_0 = 1'h0;
csrf_external_int_pend_vec_1 = 1'h0;
csrf_external_int_pend_vec_3 = 1'h0;
csrf_fflags_reg = 5'h0A;
csrf_frm_reg = 3'h2;
csrf_fs_reg = 2'h2;
csrf_ie_vec_0 = 1'h0;
csrf_ie_vec_1 = 1'h0;
csrf_ie_vec_3 = 1'h0;
csrf_mcause_code_reg = 4'hA;
csrf_mcause_interrupt_reg = 1'h0;
csrf_mcounteren_cy_reg = 1'h0;
csrf_mcounteren_ir_reg = 1'h0;
csrf_mcounteren_tm_reg = 1'h0;
csrf_mcycle_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
csrf_medeleg_13_11_reg = 3'h2;
csrf_medeleg_15_reg = 1'h0;
csrf_medeleg_9_0_reg = 10'h2AA;
csrf_mepc_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mideleg_11_reg = 1'h0;
csrf_mideleg_1_0_reg = 2'h2;
csrf_mideleg_5_3_reg = 3'h2;
csrf_mideleg_9_7_reg = 3'h2;
csrf_minstret_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
csrf_mpp_reg = 2'h2;
csrf_mprv_reg = 1'h0;
csrf_mscratch_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mtval_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mtvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
csrf_mtvec_mode_low_reg = 1'h0;
csrf_mxr_reg = 1'h0;
csrf_ppn_reg = 44'hAAAAAAAAAAA;
csrf_prev_ie_vec_0 = 1'h0;
csrf_prev_ie_vec_1 = 1'h0;
csrf_prev_ie_vec_3 = 1'h0;
csrf_prv_reg = 2'h2;
csrf_rg_dcsr = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dpc = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA;
csrf_scause_code_reg = 4'hA;
csrf_scause_interrupt_reg = 1'h0;
csrf_scounteren_cy_reg = 1'h0;
csrf_scounteren_ir_reg = 1'h0;
csrf_scounteren_tm_reg = 1'h0;
csrf_sepc_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_software_int_en_vec_0 = 1'h0;
csrf_software_int_en_vec_1 = 1'h0;
csrf_software_int_en_vec_3 = 1'h0;
csrf_software_int_pend_vec_0 = 1'h0;
csrf_software_int_pend_vec_1 = 1'h0;
csrf_software_int_pend_vec_3 = 1'h0;
csrf_spp_reg = 1'h0;
csrf_sscratch_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_stats_module_doStats = 1'h0;
csrf_stval_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_stvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
csrf_stvec_mode_low_reg = 1'h0;
csrf_sum_reg = 1'h0;
csrf_time_reg = 64'hAAAAAAAAAAAAAAAA;
csrf_timer_int_en_vec_0 = 1'h0;
csrf_timer_int_en_vec_1 = 1'h0;
csrf_timer_int_en_vec_3 = 1'h0;
csrf_timer_int_pend_vec_0 = 1'h0;
csrf_timer_int_pend_vec_1 = 1'h0;
csrf_timer_int_pend_vec_3 = 1'h0;
csrf_tsr_reg = 1'h0;
csrf_tvm_reg = 1'h0;
csrf_tw_reg = 1'h0;
csrf_vm_mode_sv39_reg = 1'h0;
flush_brpred = 1'h0;
flush_caches = 1'h0;
flush_reservation = 1'h0;
flush_tlbs = 1'h0;
mmio_cRqQ_clearReq_rl = 1'h0;
mmio_cRqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_deqReq_rl = 1'h0;
mmio_cRqQ_empty = 1'h0;
mmio_cRqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_full = 1'h0;
mmio_cRsQ_clearReq_rl = 1'h0;
mmio_cRsQ_data_0 = 1'h0;
mmio_cRsQ_deqReq_rl = 1'h0;
mmio_cRsQ_empty = 1'h0;
mmio_cRsQ_enqReq_rl = 2'h2;
mmio_cRsQ_full = 1'h0;
mmio_dataPendQ_clearReq_rl = 1'h0;
mmio_dataPendQ_deqReq_rl = 1'h0;
mmio_dataPendQ_empty = 1'h0;
mmio_dataPendQ_enqReq_rl = 1'h0;
mmio_dataPendQ_full = 1'h0;
mmio_dataReqQ_clearReq_rl = 1'h0;
mmio_dataReqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_deqReq_rl = 1'h0;
mmio_dataReqQ_empty = 1'h0;
mmio_dataReqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_full = 1'h0;
mmio_dataRespQ_clearReq_rl = 1'h0;
mmio_dataRespQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
mmio_dataRespQ_deqReq_rl = 1'h0;
mmio_dataRespQ_empty = 1'h0;
mmio_dataRespQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
mmio_dataRespQ_full = 1'h0;
mmio_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
mmio_pRqQ_clearReq_rl = 1'h0;
mmio_pRqQ_data_0 = 39'h2AAAAAAAAA;
mmio_pRqQ_deqReq_rl = 1'h0;
mmio_pRqQ_empty = 1'h0;
mmio_pRqQ_enqReq_rl = 40'hAAAAAAAAAA;
mmio_pRqQ_full = 1'h0;
mmio_pRsQ_clearReq_rl = 1'h0;
mmio_pRsQ_data_0 = 67'h2AAAAAAAAAAAAAAAA;
mmio_pRsQ_deqReq_rl = 1'h0;
mmio_pRsQ_empty = 1'h0;
mmio_pRsQ_enqReq_rl = 68'hAAAAAAAAAAAAAAAAA;
mmio_pRsQ_full = 1'h0;
mmio_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
outOfReset = 1'h0;
renameStage_rg_m_halt_req = 5'h0A;
rg_core_run_state = 2'h2;
started = 1'h0;
update_vm_info = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_outOfReset)
$fwrite(32'h80000002, "mkProc came out of reset\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2048)
$display("[Terminate CSR] being written (val = %x), ",
"send terminate signal to host",
f_csr_reqs$D_OUT[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] != 2'd2)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue &&
coreFix_memExe_lsq$firstLd[2])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
coreFix_memExe_lsq$firstLd[2])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
coreFix_memExe_lsq$firstLd[101])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState !=
3'd2)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo &&
coreFix_memExe_dMem_cache_m_banks_0_processAmo[87:86] != 2'd3)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2772 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775) &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd1 ||
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] !=
2'd1 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2775))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2816)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serial_num,
rob$deqPort_0_deq_data[353:290],
rob$deqPort_0_deq_data[289:258],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd0)
$write("Unsupported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd13)
$write("Csr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd15)
$write("FenceI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd16)
$write("SFence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd17)
$write("Ecall");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd18)
$write("Ebreak");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd19)
$write("Sret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] == 5'd20)
$write("Mret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[257:253] != 5'd0 &&
rob$deqPort_0_deq_data[257:253] != 5'd1 &&
rob$deqPort_0_deq_data[257:253] != 5'd2 &&
rob$deqPort_0_deq_data[257:253] != 5'd3 &&
rob$deqPort_0_deq_data[257:253] != 5'd4 &&
rob$deqPort_0_deq_data[257:253] != 5'd5 &&
rob$deqPort_0_deq_data[257:253] != 5'd6 &&
rob$deqPort_0_deq_data[257:253] != 5'd7 &&
rob$deqPort_0_deq_data[257:253] != 5'd8 &&
rob$deqPort_0_deq_data[257:253] != 5'd9 &&
rob$deqPort_0_deq_data[257:253] != 5'd10 &&
rob$deqPort_0_deq_data[257:253] != 5'd11 &&
rob$deqPort_0_deq_data[257:253] != 5'd12 &&
rob$deqPort_0_deq_data[257:253] != 5'd13 &&
rob$deqPort_0_deq_data[257:253] != 5'd14 &&
rob$deqPort_0_deq_data[257:253] != 5'd15 &&
rob$deqPort_0_deq_data[257:253] != 5'd16 &&
rob$deqPort_0_deq_data[257:253] != 5'd17 &&
rob$deqPort_0_deq_data[257:253] != 5'd18 &&
rob$deqPort_0_deq_data[257:253] != 5'd19 &&
rob$deqPort_0_deq_data[257:253] != 5'd20)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
$write(" [doCommitTrap]", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[25])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[11:0] != 12'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
rob$deqPort_0_deq_data[12])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!rob$deqPort_0_deq_data[25])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
rob$deqPort_0_deq_data[11:0] != 12'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serial_num,
rob$deqPort_0_deq_data[353:290],
rob$deqPort_0_deq_data[289:258],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd0)
$write("Unsupported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13)
$write("Csr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd15)
$write("FenceI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd16)
$write("SFence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd17)
$write("Ecall");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd18)
$write("Ebreak");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd19)
$write("Sret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd20)
$write("Mret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] != 5'd0 &&
rob$deqPort_0_deq_data[257:253] != 5'd1 &&
rob$deqPort_0_deq_data[257:253] != 5'd2 &&
rob$deqPort_0_deq_data[257:253] != 5'd3 &&
rob$deqPort_0_deq_data[257:253] != 5'd4 &&
rob$deqPort_0_deq_data[257:253] != 5'd5 &&
rob$deqPort_0_deq_data[257:253] != 5'd6 &&
rob$deqPort_0_deq_data[257:253] != 5'd7 &&
rob$deqPort_0_deq_data[257:253] != 5'd8 &&
rob$deqPort_0_deq_data[257:253] != 5'd9 &&
rob$deqPort_0_deq_data[257:253] != 5'd10 &&
rob$deqPort_0_deq_data[257:253] != 5'd11 &&
rob$deqPort_0_deq_data[257:253] != 5'd12 &&
rob$deqPort_0_deq_data[257:253] != 5'd13 &&
rob$deqPort_0_deq_data[257:253] != 5'd14 &&
rob$deqPort_0_deq_data[257:253] != 5'd15 &&
rob$deqPort_0_deq_data[257:253] != 5'd16 &&
rob$deqPort_0_deq_data[257:253] != 5'd17 &&
rob$deqPort_0_deq_data[257:253] != 5'd18 &&
rob$deqPort_0_deq_data[257:253] != 5'd19 &&
rob$deqPort_0_deq_data[257:253] != 5'd20)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
$write(" [doCommitSystemInst]", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
(rob$deqPort_0_deq_data[97:96] == 2'd0 ||
rob$deqPort_0_deq_data[97:96] == 2'd1))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[257:253] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4560_BIT_181_4634_T_ETC___d15189 == 6'd6)
$display("[Terminate CSR] being written (val = %x), ",
"send terminate signal to host",
rob$deqPort_0_deq_data[95:32]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
next_pc__h720279 !=
rob_deqPort_0_deq_data__4560_BITS_353_TO_290_4_ETC___d15379)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
!rob$deqPort_0_deq_data[12])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
(rob$deqPort_0_deq_data[257:253] == 5'd13) !=
rob$deqPort_0_deq_data[181])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
(rob$deqPort_0_deq_data[31:27] != 5'd0 ||
rob$deqPort_0_deq_data[26]))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[11:0] != 12'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
!rob$deqPort_0_deq_data[168])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serial_num,
rob$deqPort_0_deq_data[353:290],
rob$deqPort_0_deq_data[289:258],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[257:253] != 5'd1 &&
rob$deqPort_0_deq_data[257:253] != 5'd2 &&
rob$deqPort_0_deq_data[257:253] != 5'd3 &&
rob$deqPort_0_deq_data[257:253] != 5'd4 &&
rob$deqPort_0_deq_data[257:253] != 5'd5 &&
rob$deqPort_0_deq_data[257:253] != 5'd6 &&
rob$deqPort_0_deq_data[257:253] != 5'd7 &&
rob$deqPort_0_deq_data[257:253] != 5'd8 &&
rob$deqPort_0_deq_data[257:253] != 5'd9 &&
rob$deqPort_0_deq_data[257:253] != 5'd10 &&
rob$deqPort_0_deq_data[257:253] != 5'd11 &&
rob$deqPort_0_deq_data[257:253] != 5'd12 &&
rob$deqPort_0_deq_data[257:253] != 5'd14)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
$write(" [doCommitNormalInst [%0d]]", $signed(32'd0), "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
!rob$deqPort_0_deq_data[168])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] != 5'd0 &&
rob$deqPort_1_deq_data[257:253] != 5'd21 &&
rob$deqPort_1_deq_data[257:253] != 5'd17 &&
rob$deqPort_1_deq_data[257:253] != 5'd18 &&
rob$deqPort_1_deq_data[257:253] != 5'd13 &&
rob$deqPort_1_deq_data[257:253] != 5'd16 &&
rob$deqPort_1_deq_data[257:253] != 5'd15 &&
rob$deqPort_1_deq_data[257:253] != 5'd19 &&
rob$deqPort_1_deq_data[257:253] != 5'd20)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serial_num_4736_PLUS_IF_rob_deq_ETC___d15627,
rob$deqPort_1_deq_data[353:290],
rob$deqPort_1_deq_data[289:258],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] != 5'd0 &&
rob$deqPort_1_deq_data[257:253] != 5'd21 &&
rob$deqPort_1_deq_data[257:253] != 5'd17 &&
rob$deqPort_1_deq_data[257:253] != 5'd18 &&
rob$deqPort_1_deq_data[257:253] != 5'd13 &&
rob$deqPort_1_deq_data[257:253] != 5'd16 &&
rob$deqPort_1_deq_data[257:253] != 5'd15 &&
rob$deqPort_1_deq_data[257:253] != 5'd19 &&
rob$deqPort_1_deq_data[257:253] != 5'd20 &&
rob$deqPort_1_deq_data[257:253] != 5'd1 &&
rob$deqPort_1_deq_data[257:253] != 5'd2 &&
rob$deqPort_1_deq_data[257:253] != 5'd3 &&
rob$deqPort_1_deq_data[257:253] != 5'd4 &&
rob$deqPort_1_deq_data[257:253] != 5'd5 &&
rob$deqPort_1_deq_data[257:253] != 5'd6 &&
rob$deqPort_1_deq_data[257:253] != 5'd7 &&
rob$deqPort_1_deq_data[257:253] != 5'd8 &&
rob$deqPort_1_deq_data[257:253] != 5'd9 &&
rob$deqPort_1_deq_data[257:253] != 5'd10 &&
rob$deqPort_1_deq_data[257:253] != 5'd11 &&
rob$deqPort_1_deq_data[257:253] != 5'd12 &&
rob$deqPort_1_deq_data[257:253] != 5'd14)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] != 5'd0 &&
rob$deqPort_1_deq_data[257:253] != 5'd21 &&
rob$deqPort_1_deq_data[257:253] != 5'd17 &&
rob$deqPort_1_deq_data[257:253] != 5'd18 &&
rob$deqPort_1_deq_data[257:253] != 5'd13 &&
rob$deqPort_1_deq_data[257:253] != 5'd16 &&
rob$deqPort_1_deq_data[257:253] != 5'd15 &&
rob$deqPort_1_deq_data[257:253] != 5'd19 &&
rob$deqPort_1_deq_data[257:253] != 5'd20)
$write(" [doCommitNormalInst [%0d]]", $signed(32'd1), "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[257:253] != 5'd0 &&
rob$deqPort_1_deq_data[257:253] != 5'd21 &&
rob$deqPort_1_deq_data[257:253] != 5'd17 &&
rob$deqPort_1_deq_data[257:253] != 5'd18 &&
rob$deqPort_1_deq_data[257:253] != 5'd13 &&
rob$deqPort_1_deq_data[257:253] != 5'd16 &&
rob$deqPort_1_deq_data[257:253] != 5'd15 &&
rob$deqPort_1_deq_data[257:253] != 5'd19 &&
rob$deqPort_1_deq_data[257:253] != 5'd20 &&
!rob$deqPort_1_deq_data[168])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!coreFix_aluExe_1_exeToFinQ$first[16])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!coreFix_aluExe_0_exeToFinQ$first[16])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
coreFix_aluExe_1_regToExeQ$first[395] &&
coreFix_aluExe_1_regToExeQ$first[421:417] != 5'd13)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
coreFix_aluExe_1_regToExeQ$first[395] &&
basicExec___d12105[0])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
coreFix_aluExe_1_regToExeQ$first[395] &&
(basicExec___d12105[65:2] !=
coreFix_aluExe_1_regToExeQ$first[112:49] ||
coreFix_aluExe_1_regToExeQ$first[112:49] != y__h623923))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
coreFix_aluExe_0_regToExeQ$first[395] &&
coreFix_aluExe_0_regToExeQ$first[421:417] != 5'd13)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
coreFix_aluExe_0_regToExeQ$first[395] &&
basicExec___d12779[0])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
coreFix_aluExe_0_regToExeQ$first[395] &&
(basicExec___d12779[65:2] !=
coreFix_aluExe_0_regToExeQ$first[112:49] ||
coreFix_aluExe_0_regToExeQ$first[112:49] != y__h645995))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
!coreFix_aluExe_1_dispToRegQ$first[131] &&
coreFix_aluExe_1_dispToRegQ$first[85] &&
!sbCons$lazyLookup_1_get[3] &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11548 &&
NOT_coreFix_aluExe_1_bypassWire_0_whas__1511_1_ETC___d11538 &&
(!coreFix_aluExe_1_bypassWire_3$whas ||
!coreFix_aluExe_1_bypassWire_3_wget__1540_BITS__ETC___d11542))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
coreFix_aluExe_1_dispToRegQ$first[77] &&
!sbCons$lazyLookup_1_get[2] &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11575 &&
NOT_coreFix_aluExe_1_bypassWire_0_whas__1511_1_ETC___d11568 &&
(!coreFix_aluExe_1_bypassWire_3$whas ||
!coreFix_aluExe_1_bypassWire_3_wget__1540_BITS__ETC___d11569))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
!coreFix_aluExe_0_dispToRegQ$first[131] &&
coreFix_aluExe_0_dispToRegQ$first[85] &&
!sbCons$lazyLookup_0_get[3] &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12407 &&
NOT_coreFix_aluExe_0_bypassWire_0_whas__2370_2_ETC___d12397 &&
(!coreFix_aluExe_0_bypassWire_3$whas ||
!coreFix_aluExe_0_bypassWire_3_wget__2399_BITS__ETC___d12401))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
coreFix_aluExe_0_dispToRegQ$first[77] &&
!sbCons$lazyLookup_0_get[2] &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12434 &&
NOT_coreFix_aluExe_0_bypassWire_0_whas__2370_2_ETC___d12427 &&
(!coreFix_aluExe_0_bypassWire_3$whas ||
!coreFix_aluExe_0_bypassWire_3_wget__2399_BITS__ETC___d12428))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
(!coreFix_memExe_lsq$firstLd[101] ||
coreFix_memExe_lsq$firstLd[16]))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
(coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
(coreFix_memExe_lsq$firstLd[101] ||
!coreFix_memExe_lsq$firstLd[16]))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
(coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] != 2'd0 &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] != 2'd1)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != 2'd2 &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != 2'd3)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
coreFix_memExe_lsq$firstLd[2])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
coreFix_memExe_lsq$firstLd[90])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
(coreFix_memExe_lsq$firstLd[101] ||
!coreFix_memExe_lsq$firstLd[16]))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
(coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
coreFix_memExe_dTlb_procResp__741_BITS_105_TO__ETC___d1895 &&
coreFix_memExe_dTlb$procResp[90])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
(coreFix_memExe_lsq$firstSt[158:157] != 2'd1 &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd2 ||
coreFix_memExe_lsq$firstSt[77]))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[4])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[4])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
coreFix_memExe_lsq$firstSt[4])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd5)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd0 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2056) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd0 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd2 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2715)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd0 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2046 &&
!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2726)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2727)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2740)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2054 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2125))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2758)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd0 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd2 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
coreFix_memExe_lsq$firstSt[151])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
coreFix_memExe_lsq$respLd[85] &&
coreFix_memExe_lsq$respLd[84])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
coreFix_memExe_lsq$respLd[85] &&
coreFix_memExe_lsq$respLd[84])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem &&
coreFix_memExe_dispToRegQ$first[62] &&
!sbCons$lazyLookup_3_get[3] &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1622 &&
NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1612 &&
(!coreFix_memExe_bypassWire_3$whas ||
!coreFix_memExe_bypassWire_3_wget__614_BITS_70__ETC___d1616))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem &&
coreFix_memExe_dispToRegQ$first[54] &&
!sbCons$lazyLookup_3_get[2] &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1648 &&
NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1641 &&
(!coreFix_memExe_bypassWire_3$whas ||
!coreFix_memExe_bypassWire_3_wget__614_BITS_70__ETC___d1642))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem &&
coreFix_memExe_rsMem$dispatchData[106:104] == 3'd1 &&
coreFix_memExe_rsMem$dispatchData[41])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
coreFix_fpuMulDivExe_0_dispToRegQ$first[56] &&
!sbCons$lazyLookup_2_get[3] &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8338 &&
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8328 &&
(!coreFix_fpuMulDivExe_0_bypassWire_3$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8332))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
coreFix_fpuMulDivExe_0_dispToRegQ$first[48] &&
!sbCons$lazyLookup_2_get[2] &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8364 &&
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8357 &&
(!coreFix_fpuMulDivExe_0_bypassWire_3$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8358))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
coreFix_fpuMulDivExe_0_dispToRegQ$first[40] &&
!sbCons$lazyLookup_2_get[1] &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8390 &&
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8383 &&
(!coreFix_fpuMulDivExe_0_bypassWire_3$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_3_wget__330__ETC___d8384))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[8])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
v__h607240 == 2'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
specTagManager$currentSpecBits != 12'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[194:192] == 3'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd13)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 ||
fetchStage$pipelines_0_first[194:192] == 3'd2 ||
fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4))
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14291)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14296)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14321)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14325)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3582_AND__ETC___d14331)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14460)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
fetchStage$pipelines_1_first[194:192] != 3'd0 &&
fetchStage$pipelines_1_first[194:192] != 3'd1 &&
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14440 &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
fetchStage$pipelines_1_first[173])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14468 &&
NOT_fetchStage_pipelines_1_first__2941_BITS_32_ETC___d14455)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14468 &&
fetchStage$pipelines_1_first[173])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14390 &&
regRenamingTable_rename_1_canRename__3704_AND__ETC___d14400 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2930_2931_O_ETC___d14468 &&
(fetchStage$pipelines_1_first[199:195] != 5'd14) !=
fetchStage$pipelines_1_first[160])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
end
// synopsys translate_on
endmodule // mkCore
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