68d3bd484e
When DEBUG_WEDGE is defined, expose the last committed and next in the reorder buffer PC and corresponding instruction via DMI registers, since even when the core is wedged and we can't read GPRs etc we can still interact with the debug module itself. Hopefully this proves useful for debugging wedges.
514 lines
18 KiB
Plaintext
514 lines
18 KiB
Plaintext
// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved.
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//
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Alexandre Joannou
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// Copyright (c) 2020 Peter Rugg
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package CoreW;
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// ================================================================
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// This package is called 'CoreW' for 'Core Wrapper'
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// and corresponds to 'Core' in Piccolo and Flute.
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//
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// Here in Toooba, we use the name 'CoreW' to avoid a name-clash with
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// an inner module called 'Core' in MIT's RISCY-OOO.
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//
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// The specific correspondence with Piccolo/Flute structure is:
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// Piccolo/Flute Toooba
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// mkCore mkCoreW
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// mkProc
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// mkCPU mkCore
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// This package defines:
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// Core_IFC
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// mkCore #(Core_IFC)
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//
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// mkCoreW instantiates:
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// - mkProc (the RISC-V CPU, a version of MIT's RISCY-OOO)
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// - mkPLIC_16_2_7
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// - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF)
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// - mkDebug_Module (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL)
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// and connects them all up.
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// ================================================================
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// BSV library imports
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import Vector :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Connectable :: *;
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import Clocks :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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import Routable :: *;
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import AXI4 :: *;
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import TagControllerAXI :: *;
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// ================================================================
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// Project imports
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// ----------------
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// From RISCY-ooo
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import ProcTypes :: *;
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// ----------------
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// From Toooba
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// Main fabric
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import Fabric_Defs :: *; // for Wd_Id, Wd_Addr, Wd_Data...
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import SoC_Map :: *;
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`ifdef INCLUDE_GDB_CONTROL
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import Debug_Module :: *;
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`endif
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import CoreW_IFC :: *;
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import PLIC :: *;
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import PLIC_16_2_7 :: *;
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import Proc_IFC :: *;
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import Proc :: *;
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`ifdef INCLUDE_TANDEM_VERIF
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import TV_Info :: *;
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import Trace_Data2 :: *;
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import TV_Encode :: *;
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import Trace_Data2_to_Trace_Data :: *;
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`endif
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// TV_Taps needed when both GDB_CONTROL and TANDEM_VERIF are present
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`ifdef INCLUDE_GDB_CONTROL
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`ifdef INCLUDE_TANDEM_VERIF
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import TV_Taps :: *;
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`endif
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`endif
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import DM_CPU_Req_Rsp ::*;
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// ================================================================
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// The Core module
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(* synthesize *)
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module mkCoreW #(Reset dm_power_on_reset)
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(CoreW_IFC #(N_External_Interrupt_Sources));
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// ================================================================
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// Notes on 'reset'
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// This module's default reset (Verilog RST_N) is a
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// 'non-debug-module reset', or 'ndm-reset': it resets everything
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// in mkCoreW other than the optional RISC-V Debug Module (DM).
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// DM is reset ONLY by 'dm_power_on_reset' (parameter of this module).
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// This is expected to be performed exactly once, on power-up.
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// Note: DM has an internal functionality that the DM spec calls
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// 'dm_reset'. This is not really an electrical reset, it is just
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// a module initializer wholly within the DM to put it into a
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// known state. To be able to do a dm_reset, the DM has to be
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// working already, at least to the point that it can field DMI
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// requests from the external debugger asking the DM to proform a
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// dm_reset.
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// DM can ask the environment to perform an 'ndm-reset', which the
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// environment does by asserting the default reset (RST_N). At the
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// same time, the environment may also reset part or all of the
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// rest of the SoC.
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// DM can also individually reset each hart in mkCPU.
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// 'hart' = hardware thread = independent PC and fetch-and-execute pipeline.
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// mkCPU (instantiated in this module) has one or more harts.
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// This hart-reset logic is entirely within this module.
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// ================================================================
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// The CPU's (hart's) reset is the ``or'' of the default reset
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// (power-on reset) and the Debug Module's 'hart_reset' control.
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let ndm_reset <- exposeCurrentReset;
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`ifdef INCLUDE_GDB_CONTROL
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let clk <- exposeCurrentClock;
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Bool initial_reset_val = False;
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Integer hart_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for hart
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let dm_hart0_reset_controller <- mkReset(hart_reset_duration, initial_reset_val, clk);
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let hart0_reset <- mkResetEither (ndm_reset, dm_hart0_reset_controller.new_rst);
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`else
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let hart0_reset = ndm_reset;
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`endif
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// ================================================================
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// STATE
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// System address map
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SoC_Map_IFC soc_map <- mkSoC_Map;
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// RISCY-OOO processor
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// TODO (when we do multicore): need resets for each core.
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Proc_IFC proc <- mkProc (reset_by hart0_reset);
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// handle uncached interface
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let proc_uncached <- toAXI4_Master_Synth(extendIDFields(zeroMasterUserFields(proc.master1), 0));
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// Bridge for uncached expernal bus transactions.
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let uncached_mem_shim <- mkAXI4ShimFF(reset_by hart0_reset);
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let uncached_mem_master <- toAXI4_Master_Synth(extendIDFields(zeroMasterUserFields(uncached_mem_shim.master), 0), reset_by hart0_reset);
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// handle cached interface
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// AXI4 tagController
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TagControllerAXI#(Wd_MId, Wd_Addr, Wd_Data) tagController <- mkTagControllerAXI(reset_by hart0_reset); // TODO double check if reseting like this is good enough
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AXI4_Master#(Wd_MId, Wd_Addr, Wd_Data, Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User)
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tmp2 <- fromAXI4_Master_Synth(proc.master0, reset_by hart0_reset);
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mkConnection(tmp2, tagController.slave, reset_by hart0_reset);
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// PLIC (Platform-Level Interrupt Controller)
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PLIC_IFC_16_2_7 plic <- mkPLIC_16_2_7;
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`ifdef INCLUDE_GDB_CONTROL
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// Debug Module
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Debug_Module_IFC debug_module <- mkDebug_Module (reset_by dm_power_on_reset);
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// The following are a superscalar-wide set of transformers from RISCY-OOO output Trace_Data2
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// to Trace_Data which is input to the TV encoder
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Vector #(SupSize, Trace_Data2_to_Trace_Data_IFC) v_td2_to_td <- replicateM (mkTrace_Data2_to_Trace_Data);
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// The TV encoder transforms Trace_Data structures from the CPU and DM
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// into encoded byte vectors for transmission to the Tandem Verifier
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TV_Encode_IFC tv_encode <- mkTV_Encode;
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`endif
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// ================================================================
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// Hart-reset from DM
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`ifdef INCLUDE_GDB_CONTROL
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Reg #(Bit #(8)) rg_hart0_reset_delay <- mkReg (0);
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Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0);
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Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0);
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rule rl_dm_hart0_reset (rg_hart0_reset_delay == 0);
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let x <- debug_module.hart0_reset_client.request.get;
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dm_hart0_reset_controller.assertReset;
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rg_hart0_reset_delay <= fromInteger (hart_reset_duration + 200); // NOTE: heuristic
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$display ("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles",
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cur_cycle, hart_reset_duration);
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endrule
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rule rl_dm_hart0_reset_wait (rg_hart0_reset_delay != 0);
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if (rg_hart0_reset_delay == 1) begin
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let pc = soc_map_struct.pc_reset_value;
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Bool is_running = True;
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proc.start (is_running, pc, rg_tohost_addr, rg_fromhost_addr);
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debug_module.hart0_reset_client.response.put (is_running);
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$display ("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h",
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cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr);
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end
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rg_hart0_reset_delay <= rg_hart0_reset_delay - 1;
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endrule
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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// ================================================================
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// Direct DM-to-CPU connections for run-control and other misc requests
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mkConnection (debug_module.hart0_client_run_halt, proc.hart0_run_halt_server);
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mkConnection (debug_module.hart0_get_other_req, proc.hart0_put_other_req);
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`ifdef DEBUG_WEDGE
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mkConnection (proc.hart0_last_inst, debug_module.hart0_last_inst);
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mkConnection (proc.hart0_next_inst, debug_module.hart0_next_inst);
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`endif
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// ================================================================
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// Direct CPU-to-TV connections for TV trace data
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for (Integer j = 0; j < valueOf (SupSize); j = j + 1) begin
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// CPU Trace_Data2 output streams to Trace_Data2_to_Trace_Data converters
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mkConnection (proc.v_to_TV [j], v_td2_to_td [j].in);
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// Trace_Data2_to_Trace_Data converters to TV encoder
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mkConnection (v_td2_to_td [j].out, tv_encode.v_cpu_in [j]);
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end
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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`ifdef INCLUDE_TANDEM_VERIF
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// ================================================================
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// BEGIN SECTION: DM and TV both present
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// We instantiate 'taps' into connections where DM writes CPU GPRs,
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// FPRs, CSRs, and main memory. The tap outputs go the TV encoder,
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// to keep the tandem verifier in sync with DM updates to the CPU.
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// Create a tap for DM's memory-writes to the bus, and merge-in the trace data.
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DM_Mem_Tap_IFC dm_mem_tap <- mkDM_Mem_Tap;
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mkConnection (debug_module.master, dm_mem_tap.slave);
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let dm_master_local = dm_mem_tap.master;
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rule rl_merge_dm_mem_trace_data;
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let tmp <- dm_mem_tap.trace_data_out.get;
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tv_encode.dm_in.put (tmp);
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endrule
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// Create a tap for DM's GPR writes to the CPU, and merge-in the trace data.
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DM_GPR_Tap_IFC dm_gpr_tap_ifc <- mkDM_GPR_Tap;
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mkConnection (debug_module.hart0_gpr_mem_client, dm_gpr_tap_ifc.server);
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mkConnection (dm_gpr_tap_ifc.client, proc.hart0_gpr_mem_server);
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rule rl_merge_dm_gpr_trace_data;
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let tmp <- dm_gpr_tap_ifc.trace_data_out.get;
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tv_encode.dm_in.put (tmp);
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endrule
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`ifdef ISA_F_OR_D
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// Create a tap for DM's FPR writes to the CPU, and merge-in the trace data.
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DM_FPR_Tap_IFC dm_fpr_tap_ifc <- mkDM_FPR_Tap;
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mkConnection (debug_module.hart0_fpr_mem_client, dm_fpr_tap_ifc.server);
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mkConnection (dm_fpr_tap_ifc.client, proc.hart0_fpr_mem_server);
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rule rl_merge_dm_fpr_trace_data;
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let tmp <- dm_fpr_tap_ifc.trace_data_out.get;
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tv_encode.dm_in.put (tmp);
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endrule
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`endif
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// for ifdef ISA_F_OR_D
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// Create a tap for DM's CSR writes, and merge-in the trace data.
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DM_CSR_Tap_IFC dm_csr_tap <- mkDM_CSR_Tap;
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mkConnection(debug_module.hart0_csr_mem_client, dm_csr_tap.server);
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mkConnection(dm_csr_tap.client, proc.hart0_csr_mem_server);
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rule rl_merge_dm_csr_trace_data;
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let tmp <- dm_csr_tap.trace_data_out.get;
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tv_encode.dm_in.put(tmp);
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endrule
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`ifdef ISA_F_OR_D
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(* descending_urgency = "rl_merge_dm_fpr_trace_data, rl_merge_dm_gpr_trace_data" *)
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`endif
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(* descending_urgency = "rl_merge_dm_gpr_trace_data, rl_merge_dm_csr_trace_data" *)
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(* descending_urgency = "rl_merge_dm_csr_trace_data, rl_merge_dm_mem_trace_data" *)
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rule rl_bogus_for_sched_attributes;
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endrule
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// END SECTION: DM and TV
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// ================================================================
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`else // of ifdef INCLUDE_TANDEM_VERIF
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// ================================================================
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// BEGIN SECTION: DM, no TV
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// Connect DM's GPR interface directly to CPU
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mkConnection (debug_module.hart0_gpr_mem_client, proc.hart0_gpr_mem_server);
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`ifdef ISA_F_OR_D
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// Connect DM's FPR interface directly to CPU
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mkConnection (debug_module.hart0_fpr_mem_client, proc.hart0_fpr_mem_server);
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`endif
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// Connect DM's CSR interface directly to CPU
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mkConnection (debug_module.hart0_csr_mem_client, proc.hart0_csr_mem_server);
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// DM's bus master is directly the bus master
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let dm_master_local = debug_module.master;
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// END SECTION: DM, no TV
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// ================================================================
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`endif // for ifdef INCLUDE_TANDEM_VERIF
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// ================================================================
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`else // for ifdef INCLUDE_GDB_CONTROL
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// ================================================================
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// BEGIN SECTION: no DM
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// No DM, so 'DM bus master' is AXI4 dummy
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let dm_master_local = culDeSac;
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`ifdef INCLUDE_TANDEM_VERIF
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// TV, no DM: stub out the dm input to TV
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Get #(Trace_Data) gs = getstub;
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mkConnection (tv_encode.dm_in, gs);
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`endif
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`endif // for ifdef INCLUDE_GDB_CONTROL
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// ================================================================
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// Connect the local 2x3 fabric
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// Masters on the local 2x3 fabric
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Vector#(Num_Masters_2x3,
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AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data,
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Wd_AW_User, Wd_W_User, Wd_B_User,
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Wd_AR_User, Wd_R_User))
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master_vector = newVector;
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//let master_vector = newVector;
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master_vector[cpu_uncached_master_num] = proc_uncached;
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master_vector[debug_module_sba_master_num] = dm_master_local;
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// Slaves on the local 2x3 fabric
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// default slave is forwarded out directly to the Core interface
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Vector#(Num_Slaves_2x3,
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AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data,
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Wd_AW_User, Wd_W_User, Wd_B_User,
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Wd_AR_User, Wd_R_User))
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slave_vector = newVector;
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//let slave_vector = newVector;
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slave_vector[default_slave_num] <- toAXI4_Slave_Synth(uncached_mem_shim.slave);
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slave_vector[llc_slave_num] = proc.debug_module_mem_server;
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slave_vector[plic_slave_num] = plic.axi4_slave;
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function Vector#(Num_Slaves_2x3, Bool) route_2x3 (Bit#(Wd_Addr) addr);
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Vector#(Num_Slaves_2x3, Bool) res = replicate(False);
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if (inRange(soc_map.m_mem0_controller_addr_range, addr))
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res[llc_slave_num] = True;
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else if (inRange(soc_map.m_plic_addr_range, addr))
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res[plic_slave_num] = True;
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else
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res[default_slave_num] = True;
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//Bit #(24) topBits = truncateLSB(addr); //XXX TODO Tag controller masks to 40 bits
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//if (topBits != 0) res = replicate(False);
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return res;
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endfunction
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mkAXI4Bus_Synth (route_2x3, master_vector, slave_vector);
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let cached_mem_master <- toAXI4_Master_Synth(tagController.master);
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// ================================================================
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// Connect external interrupt lines from PLIC to CPU
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rule rl_relay_external_interrupts; // from PLIC
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Bool meip = plic.v_targets [0].m_eip;
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proc.m_external_interrupt_req (meip);
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Bool seip = plic.v_targets [1].m_eip;
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proc.s_external_interrupt_req (seip);
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// $display ("%0d: Core.rl_relay_external_interrupts: relaying: %d", cur_cycle, pack (x));
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endrule
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// ================================================================
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// INTERFACE
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// ----------------------------------------------------------------
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// Debugging: set core's verbosity, htif addrs
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method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);
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// Warning: ignoring logdelay
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proc.set_verbosity (verbosity);
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endmethod
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// ----------------------------------------------------------------
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// Start
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method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
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plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base),
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zeroExtend (rangeTop(soc_map.m_plic_addr_range)));
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let pc = soc_map_struct.pc_reset_value;
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proc.start (is_running, pc, tohost_addr, fromhost_addr);
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`ifdef INCLUDE_GDB_CONTROL
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// Save for potential future use by rl_dm_hart0_reset
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rg_tohost_addr <= tohost_addr;
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rg_fromhost_addr <= fromhost_addr;
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`endif
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$display ("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)",
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cur_cycle, pc, tohost_addr, fromhost_addr);
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endmethod
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// ----------------------------------------------------------------
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// AXI4 Fabric interfaces
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// Cached master to Fabric master interface
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interface cpu_imem_master = cached_mem_master;
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// Uncached master to Fabric master interface
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interface cpu_dmem_master = uncached_mem_master;
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// ----------------------------------------------------------------
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// External interrupt sources
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interface core_external_interrupt_sources = plic.v_sources;
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// ----------------------------------------------------------------
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// Non-maskable interrupt request
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|
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method Action nmi_req (Bool set_not_clear);
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|
// TODO: fixup; passing const False for now
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|
proc.non_maskable_interrupt_req (False);
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|
endmethod
|
|
|
|
`ifdef RVFI_DII
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|
interface Toooba_RVFI_DII_Server rvfi_dii_server = proc.rvfi_dii_server;
|
|
`endif
|
|
|
|
`ifdef INCLUDE_GDB_CONTROL
|
|
// ----------------------------------------------------------------
|
|
// Optional DM interfaces
|
|
|
|
// ----------------
|
|
// DMI (Debug Module Interface) facing remote debugger
|
|
|
|
interface DMI dmi = debug_module.dmi;
|
|
|
|
// ----------------
|
|
// Facing Platform
|
|
|
|
// Non-Debug-Module Reset (reset all except DM)
|
|
interface Client ndm_reset_client = debug_module.ndm_reset_client;
|
|
`endif
|
|
|
|
`ifdef INCLUDE_TANDEM_VERIF
|
|
// ----------------------------------------------------------------
|
|
// Optional TV interface
|
|
|
|
interface Get tv_verifier_info_get;
|
|
method ActionValue #(Info_CPU_to_Verifier) get();
|
|
match { .n, .v } <- tv_encode.out.get;
|
|
return (Info_CPU_to_Verifier { num_bytes: n, vec_bytes: v });
|
|
endmethod
|
|
endinterface
|
|
`endif
|
|
|
|
endmodule: mkCoreW
|
|
|
|
// ================================================================
|
|
// 2x3 Fabric for this Core
|
|
// Masters: CPU DMem, Debug Module System Bus Access, External access
|
|
|
|
// ----------------
|
|
// Fabric port numbers for masters
|
|
|
|
Master_Num_2x3 cpu_uncached_master_num = 0;
|
|
Master_Num_2x3 debug_module_sba_master_num = 1;
|
|
|
|
// ----------------
|
|
// Fabric port numbers for slaves
|
|
|
|
Slave_Num_2x3 default_slave_num = 0; // for I/O, uncached memory, etc.
|
|
Slave_Num_2x3 plic_slave_num = 1; // PLIC mem-mapped registers
|
|
Slave_Num_2x3 llc_slave_num = 2; // Normal cached memory (connects to coherent Last-Level Cache)
|
|
|
|
// ================================================================
|
|
|
|
endpackage
|