68d3bd484e
When DEBUG_WEDGE is defined, expose the last committed and next in the reorder buffer PC and corresponding instruction via DMI registers, since even when the core is wedged and we can't read GPRs etc we can still interact with the debug module itself. Hopefully this proves useful for debugging wedges.
392 lines
12 KiB
Plaintext
392 lines
12 KiB
Plaintext
// Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.
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//
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Alexandre Joannou
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// Copyright (c) 2020 Peter Rugg
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package Debug_Module;
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// ================================================================
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// This is the top-level package of a collection that implements the
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// "Debug Module" specified in:
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//
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// "RISC-V External Debug Support"
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// Version 0.13
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// 7c760b0151e43523ab3d2180e7852cd6f27d942c
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// Mon Jul 3 17:04:59 2017 -0700
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// Note: the spec actually represents three (almost) completely
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// independent functionalities:
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// Run Control: to start/stop harts, query their start/stop status, etc.
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// Abstract Commands: to read/write RISC-V registers and RISC-V CSRs
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// System Bus Access: to read/write RISC-V memory/devices
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// The only exception to complete independence is that the Run Control
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// part has a 'reset' for the Debug Module itself, which includes all
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// three parts.
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// Unfortunately the spec is not written to make this three-part
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// organization clear--aspects of the three parts are completely
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// intermingled. Even the address map mixes registers from the three
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// parts.
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// Here, this top-level package is merely a wrapper that dispatches
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// DMI requests to the three packages that implement the three parts:
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// DM_Run_Control
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// DM_Abstract_Commands
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// DM_System_Bus
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// DM_Common contains common spec-level (implementation-independent) definitions.
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// ================================================================
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// Our Debug Module (DM) has a two sides:
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// - GDB/Host-facing
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// - CPU/Platform-facing
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// The GDB/Host-facing side is called DMI (Debug Module Interface) in
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// the spec, and is a simple memory-like read/write interface, into a
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// debug module address space (unrelated to the RISC-V memory address
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// space).
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// The CPU/Platform-facing side has request/response interfaces for
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// CPU run-control, CPU register/CSR access and RISC-V system memory
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// access.
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// ================================================================
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// BSV library imports
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import Memory :: *;
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import FIFO :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import SpecialFIFOs :: *;
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// ----------------
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// Other library imports
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import Semi_FIFOF :: *;
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import Cur_Cycle :: *;
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import AXI4 :: *;
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// ================================================================
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// Project imports
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import ISA_Decls :: *;
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import Fabric_Defs :: *;
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import DM_Common :: *;
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import DM_CPU_Req_Rsp :: *;
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import DM_Run_Control :: *;
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import DM_Abstract_Commands :: *;
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import DM_System_Bus :: *;
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`ifdef DEBUG_WEDGE
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import ConfigReg :: *;
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import CHERICap :: *;
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import CHERICC_Fat :: *;
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`endif
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// ================================================================
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export DM_Common :: *;
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export Debug_Module_IFC (..);
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export mkDebug_Module;
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// ================================================================
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// Interface to the Debug Module
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interface Debug_Module_IFC;
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// ----------------
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// DMI (Debug Module Interface) facing remote debugger
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interface DMI dmi;
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// ----------------
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// Facing CPU
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// This section replicated for additional harts.
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// Reset and run-control
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interface Client #(Bool, Bool) hart0_reset_client;
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interface Client #(Bool, Bool) hart0_client_run_halt;
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interface Get #(Bit #(4)) hart0_get_other_req;
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// GPR access
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interface Client #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN)) hart0_gpr_mem_client;
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// FPR access
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`ifdef ISA_F
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interface Client #(DM_CPU_Req #(5, FLEN), DM_CPU_Rsp #(FLEN)) hart0_fpr_mem_client;
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`endif
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// CSR access
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interface Client #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN)) hart0_csr_mem_client;
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// Optional debug from commit stage and ROB
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`ifdef DEBUG_WEDGE
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(* always_enabled *)
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method Action hart0_last_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
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(* always_enabled *)
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method Action hart0_next_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
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`endif
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// ----------------
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// Facing Platform
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// Non-Debug-Module Reset (reset all except DM)
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// Bool indicates 'running' hart state.
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interface Client #(Bool, Bool) ndm_reset_client;
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// Read/Write RISC-V memory
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interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph,
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Wd_AW_User, Wd_W_User, Wd_B_User,
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Wd_AR_User, Wd_R_User) master;
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endinterface
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// ================================================================
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(* synthesize *)
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module mkDebug_Module (Debug_Module_IFC);
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// Local verbosity: 0 = quiet; 1 = print DMI transactions
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Integer verbosity = 0;
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// The three parts
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DM_Run_Control_IFC dm_run_control <- mkDM_Run_Control;
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DM_Abstract_Commands_IFC dm_abstract_commands <- mkDM_Abstract_Commands;
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DM_System_Bus_IFC dm_system_bus <- mkDM_System_Bus;
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FIFO#(DM_Addr) f_read_addr <- mkFIFO1;
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`ifdef DEBUG_WEDGE
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Reg #(CapMem) rg_last_pcc <- mkConfigReg (unpack (0));
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Reg #(Bit #(32)) rg_last_inst <- mkConfigReg (0);
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Reg #(CapMem) rg_next_pcc <- mkConfigReg (unpack (0));
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Reg #(Bit #(32)) rg_next_inst <- mkConfigReg (0);
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`endif
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// ================================================================
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// Reset all three parts when dm_run_control.dmactive is low
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rule rl_reset (! dm_run_control.dmactive);
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$display ("%0d: Debug_Module reset", cur_cycle);
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dm_run_control.reset;
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dm_abstract_commands.reset;
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dm_system_bus.reset;
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endrule
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// ================================================================
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// INTERFACE
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// ----------------
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// Facing GDB/DMI (Debug Module Interface)
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interface DMI dmi;
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method Action read_addr (DM_Addr dm_addr) if (dm_run_control.dmactive);
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f_read_addr.enq(dm_addr);
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if (verbosity != 0)
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$display ("%0d: %m.DMI read: dm_addr 0x%0h", cur_cycle, dm_addr);
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endmethod
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method ActionValue #(DM_Word) read_data;
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let dm_addr = f_read_addr.first;
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f_read_addr.deq;
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DM_Word dm_word = ?;
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if ( (dm_addr == dm_addr_dmcontrol)
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|| (dm_addr == dm_addr_dmstatus)
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|| (dm_addr == dm_addr_hartinfo)
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|| (dm_addr == dm_addr_haltsum)
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|| (dm_addr == dm_addr_hawindowsel)
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|| (dm_addr == dm_addr_hawindow)
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|| (dm_addr == dm_addr_devtreeaddr0)
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|| (dm_addr == dm_addr_authdata)
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|| (dm_addr == dm_addr_haltregion0)
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|| (dm_addr == dm_addr_haltregion31)
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|| (dm_addr == dm_addr_verbosity))
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dm_word <- dm_run_control.av_read (dm_addr);
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else if ( (dm_addr == dm_addr_abstractcs)
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|| (dm_addr == dm_addr_command)
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|| (dm_addr == dm_addr_data0)
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|| (dm_addr == dm_addr_data1)
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|| (dm_addr == dm_addr_data2)
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|| (dm_addr == dm_addr_data3)
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|| (dm_addr == dm_addr_data4)
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|| (dm_addr == dm_addr_data5)
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|| (dm_addr == dm_addr_data6)
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|| (dm_addr == dm_addr_data7)
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|| (dm_addr == dm_addr_data8)
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|| (dm_addr == dm_addr_data9)
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|| (dm_addr == dm_addr_data10)
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|| (dm_addr == dm_addr_data11)
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|| (dm_addr == dm_addr_abstractauto)
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|| (dm_addr == dm_addr_progbuf0))
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dm_word <- dm_abstract_commands.av_read (dm_addr);
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else if ( (dm_addr == dm_addr_sbcs)
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|| (dm_addr == dm_addr_sbaddress0)
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|| (dm_addr == dm_addr_sbaddress1)
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|| (dm_addr == dm_addr_sbaddress2)
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|| (dm_addr == dm_addr_sbdata0)
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|| (dm_addr == dm_addr_sbdata1)
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|| (dm_addr == dm_addr_sbdata2)
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|| (dm_addr == dm_addr_sbdata3))
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dm_word <- dm_system_bus.av_read (dm_addr);
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`ifdef DEBUG_WEDGE
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else if (dm_addr == dm_addr_custom0)
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dm_word = getAddr (rg_last_pcc) [31:0];
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else if (dm_addr == dm_addr_custom1)
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dm_word = getAddr (rg_last_pcc) [63:32];
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else if (dm_addr == dm_addr_custom2)
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dm_word = rg_last_inst;
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else if (dm_addr == dm_addr_custom3)
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dm_word = getAddr (rg_next_pcc) [31:0];
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else if (dm_addr == dm_addr_custom4)
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dm_word = getAddr (rg_next_pcc) [63:32];
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else if (dm_addr == dm_addr_custom5)
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dm_word = rg_next_inst;
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`endif
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else begin
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// TODO: set error status?
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dm_word = 0;
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end
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if (verbosity != 0)
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$display ("%0d: %m.DMI read response: dm_addr 0x%0h, dm_word 0x%0h",
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cur_cycle, dm_addr, dm_word);
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return dm_word;
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endmethod
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method Action write (DM_Addr dm_addr, DM_Word dm_word) if (dm_run_control.dmactive);
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if ( (dm_addr == dm_addr_dmcontrol)
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|| (dm_addr == dm_addr_dmstatus)
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|| (dm_addr == dm_addr_hartinfo)
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|| (dm_addr == dm_addr_haltsum)
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|| (dm_addr == dm_addr_hawindowsel)
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|| (dm_addr == dm_addr_hawindow)
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|| (dm_addr == dm_addr_devtreeaddr0)
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|| (dm_addr == dm_addr_authdata)
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|| (dm_addr == dm_addr_haltregion0)
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|| (dm_addr == dm_addr_haltregion31)
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|| (dm_addr == dm_addr_verbosity))
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dm_run_control.write (dm_addr, dm_word);
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else if ( (dm_addr == dm_addr_abstractcs)
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|| (dm_addr == dm_addr_command)
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|| (dm_addr == dm_addr_data0)
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|| (dm_addr == dm_addr_data1)
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|| (dm_addr == dm_addr_data2)
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|| (dm_addr == dm_addr_data3)
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|| (dm_addr == dm_addr_data4)
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|| (dm_addr == dm_addr_data5)
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|| (dm_addr == dm_addr_data6)
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|| (dm_addr == dm_addr_data7)
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|| (dm_addr == dm_addr_data8)
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|| (dm_addr == dm_addr_data9)
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|| (dm_addr == dm_addr_data10)
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|| (dm_addr == dm_addr_data11)
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|| (dm_addr == dm_addr_abstractauto)
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|| (dm_addr == dm_addr_progbuf0))
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dm_abstract_commands.write (dm_addr, dm_word);
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else if ( (dm_addr == dm_addr_sbcs)
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|| (dm_addr == dm_addr_sbaddress0)
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|| (dm_addr == dm_addr_sbaddress1)
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|| (dm_addr == dm_addr_sbaddress2)
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|| (dm_addr == dm_addr_sbdata0)
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|| (dm_addr == dm_addr_sbdata1)
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|| (dm_addr == dm_addr_sbdata2)
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|| (dm_addr == dm_addr_sbdata3))
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dm_system_bus.write (dm_addr, dm_word);
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else begin
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// TODO: set error status?
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noAction;
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end
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if (verbosity != 0)
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$display ("%0d: %m.DMI write: dm_addr 0x%0h, dm_word 0x%0h",
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cur_cycle, dm_addr, dm_word);
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endmethod
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endinterface
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// ----------------
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// Facing CPU/hart0
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// Reset and run-control
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interface Client hart0_reset_client = dm_run_control.hart0_reset_client;
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interface Client hart0_client_run_halt = dm_run_control.hart0_client_run_halt;
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interface Get hart0_get_other_req = dm_run_control.hart0_get_other_req;
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// GPR access
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interface Client hart0_gpr_mem_client = dm_abstract_commands.hart0_gpr_mem_client;
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// FPR access
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`ifdef ISA_F
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interface Client hart0_fpr_mem_client = dm_abstract_commands.hart0_fpr_mem_client;
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`endif
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// CSR access
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interface Client hart0_csr_mem_client = dm_abstract_commands.hart0_csr_mem_client;
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// Optional debug from commit stage
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`ifdef DEBUG_WEDGE
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method Action hart0_last_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
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rg_last_pcc <= tpl_1 (pcc_inst);
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rg_last_inst <= tpl_2 (pcc_inst);
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endmethod
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method Action hart0_next_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
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rg_next_pcc <= tpl_1 (pcc_inst);
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rg_next_inst <= tpl_2 (pcc_inst);
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endmethod
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`endif
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// ----------------
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// Facing Platform
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// Non-Debug-Module Reset (reset all except DM)
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interface Client ndm_reset_client = dm_run_control.ndm_reset_client;
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// Read/Write RISC-V memory
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interface AXI4_Master_IFC master = dm_system_bus.master;
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endmodule
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// ================================================================
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endpackage
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