Cheri-research/Toooba
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68d3bd484e85d2a49ab5e9a78ddbb85ace0dfec1
Toooba/src_Core/RISCY_OOO/procs/lib
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Jessica Clarke 68d3bd484e Provide opt-in wedge debugging info 
When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.
2020-07-07 23:59:35 +01:00
..
Amo.bsv
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Bht.bsv
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BrPred.bsv
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Btb.bsv
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Bypass.bsv
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CacheUtils.bsv
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CapChecks.bsvi
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ConcatReg.bsv
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CSRs.bsvi
Factor out Opcodes and CSRs into separate files
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Decode.bsv
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DirPredictor.bsv
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DTlb.bsv
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Ehr.bsv
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EpochManager.bsv
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Exec.bsv
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Fifos.bsv
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FP_Utils.bsv
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Fpu.bsv
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FullAssocTlb.bsv
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GlobalBrHistReg.bsv
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GlobalSpecUpdate.bsv
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GSelectPred.bsv
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GSharePred.bsv
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HasSpecBits.bsv
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ITlb.bsv
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L1CoCache.bsv
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L1LLConnect.bsv
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L2SetAssocTlb.bsv
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L2Tlb.bsv
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LatencyTimer.bsv
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LLCache.bsv
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LLCDmaConnect.bsv
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LLCRqMshrSecureModel.bsv
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MemLoader.bsv
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MemLoaderIF.bsv
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MemoryTypes.bsv
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MMIOAddrs.bsv
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MMIOCore.bsv
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MMIOInst.bsv
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MsgFifo.bsv
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MulDiv.bsv
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Opcodes.bsvi
Support for permissions and bounds checks for memory operations, taking
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Performance.bsv
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PhysRFile.bsv
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ProcTypes.bsv
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Ras.bsv
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RenameDebugIF.bsv
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RenamingTable.bsv
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ReorderBuffer.bsv
Provide opt-in wedge debugging info
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ReservationStationEhr.bsv
Added verbosity guards around $displays to dial down log verbosity
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SafeCounter.bsv
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Scoreboard.bsv
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SetAssocTlb.bsv
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SpecFifo.bsv
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SpecPoisonFifo.bsv
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SpecTagManager.bsv
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SplitLSQ.bsv
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StoreBuffer.bsv
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TlbConnect.bsv
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TlbTypes.bsv
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TourPred.bsv
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TourPredSecure.bsv
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TranslationCache.bsv
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Types.bsv
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VerificationPacket.bsv
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