Toooba

Files

Jessica Clarke 68d3bd484e Provide opt-in wedge debugging info

When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.

2020-07-07 23:59:35 +01:00

src_BSV

Provide opt-in wedge debugging info

2020-07-07 23:59:35 +01:00

Verilog_RTL

Regenerate verilog

2020-07-06 19:32:56 +01:00

Verilog_RTL_sim

Regenerate verilog

2020-07-06 19:32:56 +01:00

xilinx_ip

Regenerate verilog

2020-07-06 19:32:56 +01:00

Makefile

Provide opt-in wedge debugging info

2020-07-07 23:59:35 +01:00

README.txt

Merged src_SSITH_P3 and src_SSITH_P3_sim

2020-02-07 21:00:50 +05:30

README.txt

Copyright (c) 2019 Bluespec, Inc.  All Rights Reserved.

This directory is intended for DARPA SSITH users; others may safely ignore it.

This directory contains a wrapper and other resources that package up
MIT's RISCY-OOO to fit into the "standard" core socket in the SSITH GFE
("Government Furnished Equipment").

>================================================================
Context:

The SSITH system is an SoC with a "socket" (placeholder) for a "Core"
module (a RISC-V CPU).  Various implementations are/will be plugged
into this socket:

 - "P1"
    - Baseline Piccolo (BSV) based core
    - Baseline Rocket (Chisel) based core
    - Variations/alternatives by various SSITH project teams

 - "P2"
    - Baseline Flute (BSV) based core
    - Baseline Rocket (Chisel) based core
    - Variations/alternatives by various SSITH project teams

 - "P3"
    - Baseline Tooba (BSV) based core
    - Baseline BOOM (Chisel) based core
    - Variations/alternatives by various SSITH project teams

>================================================================
Whenever there are changes to the Toooba core, rerun:

  $ make compile
      (which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)

The synthesis version (Verilog_RTL) uses Xilinx IP for the integer divider,
while the simulation version (Verilog_RTL_sim) uses a model.

>================================================================